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V4L/DVB (7094): static memory
[mirror_ubuntu-zesty-kernel.git] / drivers / media / dvb / frontends / s5h1420.c
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96bf2f2b
AQ		 1/*
2Driver for Samsung S5H1420 QPSK Demodulator
3
4Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program; if not, write to the Free Software
19Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21*/
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
4e57b681
TS		 29#include <linux/jiffies.h>
30#include <asm/div64.h>
96bf2f2b
AQ		 31
32#include "dvb_frontend.h"
33#include "s5h1420.h"
34
35
36
37#define TONE_FREQ 22000
38
39struct s5h1420_state {
40 struct i2c_adapter* i2c;
96bf2f2b
AQ		 41 const struct s5h1420_config* config;
42 struct dvb_frontend frontend;
43
44 u8 postlocked:1;
45 u32 fclk;
46 u32 tunedfreq;
47 fe_code_rate_t fec_inner;
48 u32 symbol_rate;
49};
50
51static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
a9d6a80b
AQ		 52static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
53 struct dvb_frontend_tune_settings* fesettings);
96bf2f2b
AQ		 54
55
ff699e6b 56static int debug;
96bf2f2b
AQ		 57#define dprintk if (debug) printk
58
59static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
60{
61 u8 buf [] = { reg, data };
62 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
63 int err;
64
65 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
66 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data);
67 return -EREMOTEIO;
68 }
69
70 return 0;
71}
72
73static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
74{
75 int ret;
76 u8 b0 [] = { reg };
77 u8 b1 [] = { 0 };
78 struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
79 struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
80
81 if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
82 return ret;
83
84 if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
85 return ret;
86
87 return b1[0];
88}
89
90static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
91{
92 struct s5h1420_state* state = fe->demodulator_priv;
93
94 switch(voltage) {
95 case SEC_VOLTAGE_13:
a9d6a80b
AQ		 96 s5h1420_writereg(state, 0x3c,
97 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
96bf2f2b
AQ		 98 break;
99
100 case SEC_VOLTAGE_18:
101 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
102 break;
103
104 case SEC_VOLTAGE_OFF:
105 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
106 break;
107 }
108
109 return 0;
110}
111
112static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
113{
114 struct s5h1420_state* state = fe->demodulator_priv;
115
116 switch(tone) {
117 case SEC_TONE_ON:
a9d6a80b
AQ		 118 s5h1420_writereg(state, 0x3b,
119 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
96bf2f2b
AQ		 120 break;
121
122 case SEC_TONE_OFF:
a9d6a80b
AQ		 123 s5h1420_writereg(state, 0x3b,
124 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
96bf2f2b
AQ		 125 break;
126 }
127
128 return 0;
129}
130
a9d6a80b
AQ		 131static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
132 struct dvb_diseqc_master_cmd* cmd)
96bf2f2b
AQ		 133{
134 struct s5h1420_state* state = fe->demodulator_priv;
135 u8 val;
136 int i;
137 unsigned long timeout;
138 int result = 0;
139
a9d6a80b
AQ		 140 if (cmd->msg_len > 8)
141 return -EINVAL;
142
96bf2f2b
AQ		 143 /* setup for DISEQC */
144 val = s5h1420_readreg(state, 0x3b);
145 s5h1420_writereg(state, 0x3b, 0x02);
146 msleep(15);
147
148 /* write the DISEQC command bytes */
149 for(i=0; i< cmd->msg_len; i++) {
a9d6a80b 150 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
96bf2f2b
AQ		 151 }
152
153 /* kick off transmission */
a9d6a80b
AQ		 154 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
155 ((cmd->msg_len-1) << 4) | 0x08);
96bf2f2b
AQ		 156
157 /* wait for transmission to complete */
158 timeout = jiffies + ((100*HZ) / 1000);
159 while(time_before(jiffies, timeout)) {
a9d6a80b 160 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
96bf2f2b
AQ		 161 break;
162
163 msleep(5);
164 }
165 if (time_after(jiffies, timeout))
166 result = -ETIMEDOUT;
167
168 /* restore original settings */
169 s5h1420_writereg(state, 0x3b, val);
170 msleep(15);
171 return result;
172}
173
a9d6a80b
AQ		 174static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
175 struct dvb_diseqc_slave_reply* reply)
96bf2f2b
AQ		 176{
177 struct s5h1420_state* state = fe->demodulator_priv;
178 u8 val;
179 int i;
180 int length;
181 unsigned long timeout;
182 int result = 0;
183
184 /* setup for DISEQC recieve */
185 val = s5h1420_readreg(state, 0x3b);
186 s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
187 msleep(15);
188
189 /* wait for reception to complete */
190 timeout = jiffies + ((reply->timeout*HZ) / 1000);
191 while(time_before(jiffies, timeout)) {
192 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
193 break;
194
195 msleep(5);
196 }
197 if (time_after(jiffies, timeout)) {
198 result = -ETIMEDOUT;
199 goto exit;
200 }
201
202 /* check error flag - FIXME: not sure what this does - docs do not describe
203 * beyond "error flag for diseqc receive data :( */
204 if (s5h1420_readreg(state, 0x49)) {
205 result = -EIO;
206 goto exit;
207 }
208
209 /* check length */
210 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
211 if (length > sizeof(reply->msg)) {
212 result = -EOVERFLOW;
213 goto exit;
214 }
215 reply->msg_len = length;
216
217 /* extract data */
218 for(i=0; i< length; i++) {
a9d6a80b 219 reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
96bf2f2b
AQ		 220 }
221
222exit:
223 /* restore original settings */
224 s5h1420_writereg(state, 0x3b, val);
225 msleep(15);
226 return result;
227}
228
229static int s5h1420_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
230{
231 struct s5h1420_state* state = fe->demodulator_priv;
232 u8 val;
233 int result = 0;
234 unsigned long timeout;
235
236 /* setup for tone burst */
237 val = s5h1420_readreg(state, 0x3b);
238 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
239
240 /* set value for B position if requested */
241 if (minicmd == SEC_MINI_B) {
242 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
243 }
244 msleep(15);
245
246 /* start transmission */
247 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
248
249 /* wait for transmission to complete */
a9d6a80b 250 timeout = jiffies + ((100*HZ) / 1000);
96bf2f2b
AQ		 251 while(time_before(jiffies, timeout)) {
252 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
253 break;
254
255 msleep(5);
256 }
257 if (time_after(jiffies, timeout))
258 result = -ETIMEDOUT;
259
260 /* restore original settings */
261 s5h1420_writereg(state, 0x3b, val);
262 msleep(15);
263 return result;
264}
265
266static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
267{
268 u8 val;
269 fe_status_t status = 0;
270
271 val = s5h1420_readreg(state, 0x14);
272 if (val & 0x02)
a9d6a80b 273 status |= FE_HAS_SIGNAL;
96bf2f2b 274 if (val & 0x01)
a9d6a80b 275 status |= FE_HAS_CARRIER;
96bf2f2b
AQ		 276 val = s5h1420_readreg(state, 0x36);
277 if (val & 0x01)
278 status |= FE_HAS_VITERBI;
279 if (val & 0x20)
280 status |= FE_HAS_SYNC;
281 if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
282 status |= FE_HAS_LOCK;
283
284 return status;
285}
286
287static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
288{
289 struct s5h1420_state* state = fe->demodulator_priv;
290 u8 val;
291
292 if (status == NULL)
293 return -EINVAL;
294
295 /* determine lock state */
296 *status = s5h1420_get_status_bits(state);
297
a9d6a80b
AQ		 298 /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
299 the inversion, wait a bit and check again */
96bf2f2b
AQ		 300 if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
301 val = s5h1420_readreg(state, 0x32);
302 if ((val & 0x07) == 0x03) {
303 if (val & 0x08)
304 s5h1420_writereg(state, 0x31, 0x13);
305 else
306 s5h1420_writereg(state, 0x31, 0x1b);
307
308 /* wait a bit then update lock status */
309 mdelay(200);
310 *status = s5h1420_get_status_bits(state);
311 }
312 }
313
314 /* perform post lock setup */
315 if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {
316
317 /* calculate the data rate */
318 u32 tmp = s5h1420_getsymbolrate(state);
319 switch(s5h1420_readreg(state, 0x32) & 0x07) {
320 case 0:
321 tmp = (tmp * 2 * 1) / 2;
322 break;
323
324 case 1:
325 tmp = (tmp * 2 * 2) / 3;
326 break;
327
328 case 2:
329 tmp = (tmp * 2 * 3) / 4;
330 break;
331
332 case 3:
333 tmp = (tmp * 2 * 5) / 6;
334 break;
335
336 case 4:
337 tmp = (tmp * 2 * 6) / 7;
338 break;
339
340 case 5:
341 tmp = (tmp * 2 * 7) / 8;
342 break;
343 }
a9d6a80b
AQ		 344 if (tmp == 0) {
345 printk("s5h1420: avoided division by 0\n");
346 tmp = 1;
347 }
96bf2f2b
AQ		 348 tmp = state->fclk / tmp;
349
350 /* set the MPEG_CLK_INTL for the calculated data rate */
351 if (tmp < 4)
352 val = 0x00;
353 else if (tmp < 8)
354 val = 0x01;
355 else if (tmp < 12)
356 val = 0x02;
357 else if (tmp < 16)
358 val = 0x03;
359 else if (tmp < 24)
360 val = 0x04;
361 else if (tmp < 32)
362 val = 0x05;
363 else
364 val = 0x06;
365 s5h1420_writereg(state, 0x22, val);
366
367 /* DC freeze */
368 s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);
369
370 /* kicker disable + remove DC offset */
371 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);
372
373 /* post-lock processing has been done! */
374 state->postlocked = 1;
375 }
376
377 return 0;
378}
379
380static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
381{
382 struct s5h1420_state* state = fe->demodulator_priv;
383
384 s5h1420_writereg(state, 0x46, 0x1d);
385 mdelay(25);
a9d6a80b
AQ		 386
387 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
388
389 return 0;
96bf2f2b
AQ		 390}
391
392static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
393{
394 struct s5h1420_state* state = fe->demodulator_priv;
395
a9d6a80b 396 u8 val = s5h1420_readreg(state, 0x15);
96bf2f2b 397
a9d6a80b
AQ		 398 *strength = (u16) ((val << 8) | val);
399
400 return 0;
96bf2f2b
AQ		 401}
402
403static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
404{
405 struct s5h1420_state* state = fe->demodulator_priv;
406
407 s5h1420_writereg(state, 0x46, 0x1f);
408 mdelay(25);
a9d6a80b
AQ		 409
410 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
411
412 return 0;
96bf2f2b
AQ		 413}
414
415static void s5h1420_reset(struct s5h1420_state* state)
416{
417 s5h1420_writereg (state, 0x01, 0x08);
418 s5h1420_writereg (state, 0x01, 0x00);
419 udelay(10);
420}
421
a9d6a80b
AQ		 422static void s5h1420_setsymbolrate(struct s5h1420_state* state,
423 struct dvb_frontend_parameters *p)
96bf2f2b
AQ		 424{
425 u64 val;
426
a9d6a80b 427 val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
96bf2f2b
AQ		 428 if (p->u.qpsk.symbol_rate <= 21000000) {
429 val *= 2;
430 }
431 do_div(val, (state->fclk / 1000));
432
433 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f);
434 s5h1420_writereg(state, 0x11, val >> 16);
435 s5h1420_writereg(state, 0x12, val >> 8);
436 s5h1420_writereg(state, 0x13, val & 0xff);
437 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80);
438}
439
440static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
441{
a9d6a80b 442 u64 val = 0;
96bf2f2b
AQ		 443 int sampling = 2;
444
445 if (s5h1420_readreg(state, 0x05) & 0x2)
446 sampling = 1;
447
448 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
449 val = s5h1420_readreg(state, 0x11) << 16;
450 val |= s5h1420_readreg(state, 0x12) << 8;
451 val |= s5h1420_readreg(state, 0x13);
452 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
453
a9d6a80b 454 val *= (state->fclk / 1000ULL);
96bf2f2b
AQ		 455 do_div(val, ((1<<24) * sampling));
456
a9d6a80b 457 return (u32) (val * 1000ULL);
96bf2f2b
AQ		 458}
459
460static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
461{
462 int val;
463
464 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
465 * divide fclk by 1000000 to get the correct value. */
466 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
467
468 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf);
469 s5h1420_writereg(state, 0x0e, val >> 16);
470 s5h1420_writereg(state, 0x0f, val >> 8);
471 s5h1420_writereg(state, 0x10, val & 0xff);
472 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40);
473}
474
475static int s5h1420_getfreqoffset(struct s5h1420_state* state)
476{
477 int val;
478
479 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
480 val = s5h1420_readreg(state, 0x0e) << 16;
481 val |= s5h1420_readreg(state, 0x0f) << 8;
482 val |= s5h1420_readreg(state, 0x10);
483 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
484
485 if (val & 0x800000)
486 val |= 0xff000000;
487
488 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
489 * divide fclk by 1000000 to get the correct value. */
a9d6a80b 490 val = (((-val) * (state->fclk/1000000)) / (1<<24));
96bf2f2b
AQ		 491
492 return val;
493}
494
a9d6a80b 495static void s5h1420_setfec_inversion(struct s5h1420_state* state,
9101e622 496 struct dvb_frontend_parameters *p)
96bf2f2b 497{
a9d6a80b
AQ		 498 u8 inversion = 0;
499
500 if (p->inversion == INVERSION_OFF) {
501 inversion = state->config->invert ? 0x08 : 0;
502 } else if (p->inversion == INVERSION_ON) {
503 inversion = state->config->invert ? 0 : 0x08;
504 }
505
96bf2f2b 506 if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
96bf2f2b 507 s5h1420_writereg(state, 0x30, 0x3f);
a9d6a80b 508 s5h1420_writereg(state, 0x31, 0x00 | inversion);
96bf2f2b
AQ		 509 } else {
510 switch(p->u.qpsk.fec_inner) {
511 case FEC_1_2:
96bf2f2b 512 s5h1420_writereg(state, 0x30, 0x01);
a9d6a80b 513 s5h1420_writereg(state, 0x31, 0x10 | inversion);
96bf2f2b
AQ		 514 break;
515
516 case FEC_2_3:
96bf2f2b 517 s5h1420_writereg(state, 0x30, 0x02);
a9d6a80b 518 s5h1420_writereg(state, 0x31, 0x11 | inversion);
96bf2f2b
AQ		 519 break;
520
521 case FEC_3_4:
96bf2f2b 522 s5h1420_writereg(state, 0x30, 0x04);
50c25fff
MK		 523 s5h1420_writereg(state, 0x31, 0x12 | inversion);
524 break;
96bf2f2b
AQ		 525
526 case FEC_5_6:
96bf2f2b 527 s5h1420_writereg(state, 0x30, 0x08);
a9d6a80b 528 s5h1420_writereg(state, 0x31, 0x13 | inversion);
96bf2f2b
AQ		 529 break;
530
531 case FEC_6_7:
96bf2f2b 532 s5h1420_writereg(state, 0x30, 0x10);
a9d6a80b 533 s5h1420_writereg(state, 0x31, 0x14 | inversion);
96bf2f2b
AQ		 534 break;
535
536 case FEC_7_8:
96bf2f2b 537 s5h1420_writereg(state, 0x30, 0x20);
a9d6a80b 538 s5h1420_writereg(state, 0x31, 0x15 | inversion);
96bf2f2b
AQ		 539 break;
540
541 default:
542 return;
543 }
544 }
545}
546
547static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
548{
549 switch(s5h1420_readreg(state, 0x32) & 0x07) {
550 case 0:
551 return FEC_1_2;
552
553 case 1:
554 return FEC_2_3;
555
556 case 2:
557 return FEC_3_4;
558
559 case 3:
560 return FEC_5_6;
561
562 case 4:
563 return FEC_6_7;
564
565 case 5:
566 return FEC_7_8;
567 }
568
569 return FEC_NONE;
570}
571
96bf2f2b
AQ		 572static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
573{
574 if (s5h1420_readreg(state, 0x32) & 0x08)
575 return INVERSION_ON;
576
577 return INVERSION_OFF;
578}
579
a9d6a80b
AQ		 580static int s5h1420_set_frontend(struct dvb_frontend* fe,
581 struct dvb_frontend_parameters *p)
96bf2f2b
AQ		 582{
583 struct s5h1420_state* state = fe->demodulator_priv;
a9d6a80b 584 int frequency_delta;
96bf2f2b
AQ		 585 struct dvb_frontend_tune_settings fesettings;
586
587 /* check if we should do a fast-tune */
588 memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
589 s5h1420_get_tune_settings(fe, &fesettings);
590 frequency_delta = p->frequency - state->tunedfreq;
a9d6a80b
AQ		 591 if ((frequency_delta > -fesettings.max_drift) &&
592 (frequency_delta < fesettings.max_drift) &&
96bf2f2b
AQ		 593 (frequency_delta != 0) &&
594 (state->fec_inner == p->u.qpsk.fec_inner) &&
595 (state->symbol_rate == p->u.qpsk.symbol_rate)) {
596
dea74869
PB		 597 if (fe->ops.tuner_ops.set_params) {
598 fe->ops.tuner_ops.set_params(fe, p);
599 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
a98af224 600 }
dea74869 601 if (fe->ops.tuner_ops.get_frequency) {
a98af224 602 u32 tmp;
dea74869
PB		 603 fe->ops.tuner_ops.get_frequency(fe, &tmp);
604 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
a9d6a80b 605 s5h1420_setfreqoffset(state, p->frequency - tmp);
a98af224
AQ		 606 } else {
607 s5h1420_setfreqoffset(state, 0);
a9d6a80b 608 }
96bf2f2b
AQ		 609 return 0;
610 }
611
612 /* first of all, software reset */
613 s5h1420_reset(state);
614
96bf2f2b
AQ		 615 /* set s5h1420 fclk PLL according to desired symbol rate */
616 if (p->u.qpsk.symbol_rate > 28000000) {
617 state->fclk = 88000000;
618 s5h1420_writereg(state, 0x03, 0x50);
619 s5h1420_writereg(state, 0x04, 0x40);
620 s5h1420_writereg(state, 0x05, 0xae);
621 } else if (p->u.qpsk.symbol_rate > 21000000) {
622 state->fclk = 59000000;
623 s5h1420_writereg(state, 0x03, 0x33);
624 s5h1420_writereg(state, 0x04, 0x40);
625 s5h1420_writereg(state, 0x05, 0xae);
626 } else {
627 state->fclk = 88000000;
628 s5h1420_writereg(state, 0x03, 0x50);
629 s5h1420_writereg(state, 0x04, 0x40);
630 s5h1420_writereg(state, 0x05, 0xac);
631 }
632
633 /* set misc registers */
634 s5h1420_writereg(state, 0x02, 0x00);
a9d6a80b 635 s5h1420_writereg(state, 0x06, 0x00);
96bf2f2b 636 s5h1420_writereg(state, 0x07, 0xb0);
a9d6a80b 637 s5h1420_writereg(state, 0x0a, 0xe7);
96bf2f2b
AQ		 638 s5h1420_writereg(state, 0x0b, 0x78);
639 s5h1420_writereg(state, 0x0c, 0x48);
640 s5h1420_writereg(state, 0x0d, 0x6b);
641 s5h1420_writereg(state, 0x2e, 0x8e);
642 s5h1420_writereg(state, 0x35, 0x33);
643 s5h1420_writereg(state, 0x38, 0x01);
644 s5h1420_writereg(state, 0x39, 0x7d);
645 s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
646 s5h1420_writereg(state, 0x3c, 0x00);
647 s5h1420_writereg(state, 0x45, 0x61);
648 s5h1420_writereg(state, 0x46, 0x1d);
649
650 /* start QPSK */
651 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
652
a9d6a80b 653 /* set tuner PLL */
dea74869
PB		 654 if (fe->ops.tuner_ops.set_params) {
655 fe->ops.tuner_ops.set_params(fe, p);
656 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
a9d6a80b
AQ		 657 s5h1420_setfreqoffset(state, 0);
658 }
96bf2f2b
AQ		 659
660 /* set the reset of the parameters */
661 s5h1420_setsymbolrate(state, p);
a9d6a80b 662 s5h1420_setfec_inversion(state, p);
96bf2f2b
AQ		 663
664 state->fec_inner = p->u.qpsk.fec_inner;
665 state->symbol_rate = p->u.qpsk.symbol_rate;
666 state->postlocked = 0;
a9d6a80b 667 state->tunedfreq = p->frequency;
96bf2f2b
AQ		 668 return 0;
669}
670
a9d6a80b
AQ		 671static int s5h1420_get_frontend(struct dvb_frontend* fe,
672 struct dvb_frontend_parameters *p)
96bf2f2b
AQ		 673{
674 struct s5h1420_state* state = fe->demodulator_priv;
675
676 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
677 p->inversion = s5h1420_getinversion(state);
678 p->u.qpsk.symbol_rate = s5h1420_getsymbolrate(state);
679 p->u.qpsk.fec_inner = s5h1420_getfec(state);
680
681 return 0;
682}
683
a9d6a80b
AQ		 684static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
685 struct dvb_frontend_tune_settings* fesettings)
96bf2f2b
AQ		 686{
687 if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) {
688 fesettings->min_delay_ms = 50;
689 fesettings->step_size = 2000;
690 fesettings->max_drift = 8000;
691 } else if (fesettings->parameters.u.qpsk.symbol_rate > 12000000) {
692 fesettings->min_delay_ms = 100;
693 fesettings->step_size = 1500;
694 fesettings->max_drift = 9000;
695 } else if (fesettings->parameters.u.qpsk.symbol_rate > 8000000) {
696 fesettings->min_delay_ms = 100;
697 fesettings->step_size = 1000;
698 fesettings->max_drift = 8000;
699 } else if (fesettings->parameters.u.qpsk.symbol_rate > 4000000) {
700 fesettings->min_delay_ms = 100;
701 fesettings->step_size = 500;
702 fesettings->max_drift = 7000;
703 } else if (fesettings->parameters.u.qpsk.symbol_rate > 2000000) {
704 fesettings->min_delay_ms = 200;
705 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
706 fesettings->max_drift = 14 * fesettings->step_size;
707 } else {
708 fesettings->min_delay_ms = 200;
709 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
710 fesettings->max_drift = 18 * fesettings->step_size;
711 }
712
713 return 0;
714}
715
a98af224
AQ		 716static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
717{
718 struct s5h1420_state* state = fe->demodulator_priv;
719
720 if (enable) {
721 return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
722 } else {
723 return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
724 }
725}
726
96bf2f2b
AQ		 727static int s5h1420_init (struct dvb_frontend* fe)
728{
729 struct s5h1420_state* state = fe->demodulator_priv;
730
731 /* disable power down and do reset */
732 s5h1420_writereg(state, 0x02, 0x10);
733 msleep(10);
734 s5h1420_reset(state);
735
96bf2f2b
AQ		 736 return 0;
737}
738
739static int s5h1420_sleep(struct dvb_frontend* fe)
740{
741 struct s5h1420_state* state = fe->demodulator_priv;
742
743 return s5h1420_writereg(state, 0x02, 0x12);
744}
745
746static void s5h1420_release(struct dvb_frontend* fe)
747{
748 struct s5h1420_state* state = fe->demodulator_priv;
749 kfree(state);
750}
751
752static struct dvb_frontend_ops s5h1420_ops;
753
a9d6a80b
AQ		 754struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
755 struct i2c_adapter* i2c)
96bf2f2b
AQ		 756{
757 struct s5h1420_state* state = NULL;
758 u8 identity;
759
760 /* allocate memory for the internal state */
761 state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
762 if (state == NULL)
763 goto error;
764
765 /* setup the state */
766 state->config = config;
767 state->i2c = i2c;
96bf2f2b
AQ		 768 state->postlocked = 0;
769 state->fclk = 88000000;
770 state->tunedfreq = 0;
771 state->fec_inner = FEC_NONE;
772 state->symbol_rate = 0;
773
774 /* check if the demod is there + identify it */
775 identity = s5h1420_readreg(state, 0x00);
776 if (identity != 0x03)
777 goto error;
778
779 /* create dvb_frontend */
dea74869 780 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
96bf2f2b
AQ		 781 state->frontend.demodulator_priv = state;
782 return &state->frontend;
783
784error:
785 kfree(state);
786 return NULL;
787}
788
789static struct dvb_frontend_ops s5h1420_ops = {
790
791 .info = {
792 .name = "Samsung S5H1420 DVB-S",
793 .type = FE_QPSK,
794 .frequency_min = 950000,
795 .frequency_max = 2150000,
796 .frequency_stepsize = 125, /* kHz for QPSK frontends */
797 .frequency_tolerance = 29500,
798 .symbol_rate_min = 1000000,
799 .symbol_rate_max = 45000000,
800 /* .symbol_rate_tolerance = ???,*/
801 .caps = FE_CAN_INVERSION_AUTO |
802 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
803 FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
804 FE_CAN_QPSK
805 },
806
807 .release = s5h1420_release,
808
809 .init = s5h1420_init,
810 .sleep = s5h1420_sleep,
a98af224 811 .i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
96bf2f2b
AQ		 812
813 .set_frontend = s5h1420_set_frontend,
814 .get_frontend = s5h1420_get_frontend,
815 .get_tune_settings = s5h1420_get_tune_settings,
816
817 .read_status = s5h1420_read_status,
818 .read_ber = s5h1420_read_ber,
819 .read_signal_strength = s5h1420_read_signal_strength,
820 .read_ucblocks = s5h1420_read_ucblocks,
821
822 .diseqc_send_master_cmd = s5h1420_send_master_cmd,
823 .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
824 .diseqc_send_burst = s5h1420_send_burst,
825 .set_tone = s5h1420_set_tone,
826 .set_voltage = s5h1420_set_voltage,
827};
828
829module_param(debug, int, 0644);
830
831MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
832MODULE_AUTHOR("Andrew de Quincey");
833MODULE_LICENSE("GPL");
834
835EXPORT_SYMBOL(s5h1420_attach);
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