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8bd135ba MA |
1 | /* |
2 | STB0899 Multistandard Frontend driver | |
3 | Copyright (C) Manu Abraham (abraham.manu@gmail.com) | |
4 | ||
5 | Copyright (C) ST Microelectronics | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include "stb0899_drv.h" | |
23 | #include "stb0899_priv.h" | |
24 | #include "stb0899_reg.h" | |
25 | ||
27713c8b | 26 | inline u32 stb0899_do_div(u64 n, u32 d) |
8bd135ba | 27 | { |
27713c8b RN |
28 | /* wrap do_div() for ease of use */ |
29 | ||
30 | do_div(n, d); | |
31 | return n; | |
8bd135ba MA |
32 | } |
33 | ||
34 | /* | |
35 | * stb0899_calc_srate | |
36 | * Compute symbol rate | |
37 | */ | |
38 | static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr) | |
39 | { | |
27713c8b | 40 | u64 tmp; |
8bd135ba | 41 | |
27713c8b | 42 | /* srate = (SFR * master_clk) >> 20 */ |
8bd135ba | 43 | |
27713c8b RN |
44 | /* sfr is of size 20 bit, stored with an offset of 4 bit */ |
45 | tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2]; | |
46 | tmp &= ~0xf; | |
47 | tmp *= master_clk; | |
48 | tmp >>= 24; | |
8bd135ba MA |
49 | |
50 | return tmp; | |
51 | } | |
52 | ||
53 | /* | |
54 | * stb0899_get_srate | |
55 | * Get the current symbol rate | |
56 | */ | |
57 | u32 stb0899_get_srate(struct stb0899_state *state) | |
58 | { | |
59 | struct stb0899_internal *internal = &state->internal; | |
27713c8b | 60 | u8 sfr[3]; |
8bd135ba MA |
61 | |
62 | stb0899_read_regs(state, STB0899_SFRH, sfr, 3); | |
63 | ||
64 | return stb0899_calc_srate(internal->master_clk, sfr); | |
65 | } | |
66 | ||
67 | /* | |
68 | * stb0899_set_srate | |
69 | * Set symbol frequency | |
70 | * MasterClock: master clock frequency (hz) | |
71 | * SymbolRate: symbol rate (bauds) | |
72 | * return symbol frequency | |
73 | */ | |
74 | static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate) | |
75 | { | |
b359325d MA |
76 | u32 tmp; |
77 | u8 sfr[3]; | |
8bd135ba | 78 | |
8bd135ba MA |
79 | dprintk(state->verbose, FE_DEBUG, 1, "-->"); |
80 | /* | |
81 | * in order to have the maximum precision, the symbol rate entered into | |
82 | * the chip is computed as the closest value of the "true value". | |
83 | * In this purpose, the symbol rate value is rounded (1 is added on the bit | |
84 | * below the LSB ) | |
b359325d | 85 | * |
27713c8b RN |
86 | * srate = (SFR * master_clk) >> 20 |
87 | * <=> | |
88 | * SFR = srate << 20 / master_clk | |
89 | * | |
90 | * rounded: | |
91 | * SFR = (srate << 21 + master_clk) / (2 * master_clk) | |
92 | * | |
93 | * stored as 20 bit number with an offset of 4 bit: | |
94 | * sfr = SFR << 4; | |
95 | */ | |
27713c8b RN |
96 | |
97 | tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk); | |
98 | tmp <<= 4; | |
8bd135ba | 99 | |
27713c8b RN |
100 | sfr[0] = tmp >> 16; |
101 | sfr[1] = tmp >> 8; | |
102 | sfr[2] = tmp; | |
8bd135ba | 103 | |
8bd135ba MA |
104 | stb0899_write_regs(state, STB0899_SFRH, sfr, 3); |
105 | ||
106 | return srate; | |
107 | } | |
108 | ||
8bd135ba MA |
109 | /* |
110 | * stb0899_calc_derot_time | |
111 | * Compute the amount of time needed by the derotator to lock | |
112 | * SymbolRate: Symbol rate | |
113 | * return: derotator time constant (ms) | |
114 | */ | |
115 | static long stb0899_calc_derot_time(long srate) | |
116 | { | |
117 | if (srate > 0) | |
118 | return (100000 / (srate / 1000)); | |
119 | else | |
120 | return 0; | |
121 | } | |
122 | ||
123 | /* | |
124 | * stb0899_carr_width | |
125 | * Compute the width of the carrier | |
126 | * return: width of carrier (kHz or Mhz) | |
127 | */ | |
128 | long stb0899_carr_width(struct stb0899_state *state) | |
129 | { | |
130 | struct stb0899_internal *internal = &state->internal; | |
131 | ||
132 | return (internal->srate + (internal->srate * internal->rolloff) / 100); | |
133 | } | |
134 | ||
135 | /* | |
136 | * stb0899_first_subrange | |
137 | * Compute the first subrange of the search | |
138 | */ | |
139 | static void stb0899_first_subrange(struct stb0899_state *state) | |
140 | { | |
141 | struct stb0899_internal *internal = &state->internal; | |
142 | struct stb0899_params *params = &state->params; | |
143 | struct stb0899_config *config = state->config; | |
144 | ||
145 | int range = 0; | |
146 | u32 bandwidth = 0; | |
147 | ||
148 | if (config->tuner_get_bandwidth) { | |
9a286097 | 149 | stb0899_i2c_gate_ctrl(&state->frontend, 1); |
8bd135ba | 150 | config->tuner_get_bandwidth(&state->frontend, &bandwidth); |
9a286097 | 151 | stb0899_i2c_gate_ctrl(&state->frontend, 0); |
8bd135ba MA |
152 | range = bandwidth - stb0899_carr_width(state) / 2; |
153 | } | |
154 | ||
155 | if (range > 0) | |
156 | internal->sub_range = MIN(internal->srch_range, range); | |
157 | else | |
158 | internal->sub_range = 0; | |
159 | ||
160 | internal->freq = params->freq; | |
161 | internal->tuner_offst = 0L; | |
162 | internal->sub_dir = 1; | |
163 | } | |
164 | ||
165 | /* | |
166 | * stb0899_check_tmg | |
167 | * check for timing lock | |
168 | * internal.Ttiming: time to wait for loop lock | |
169 | */ | |
170 | static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state) | |
171 | { | |
172 | struct stb0899_internal *internal = &state->internal; | |
eadf29b9 | 173 | int lock; |
8bd135ba | 174 | u8 reg; |
eadf29b9 | 175 | s8 timing; |
8bd135ba | 176 | |
b359325d | 177 | msleep(internal->t_derot); |
8bd135ba | 178 | |
85eabac4 | 179 | stb0899_write_reg(state, STB0899_RTF, 0xf2); |
8bd135ba MA |
180 | reg = stb0899_read_reg(state, STB0899_TLIR); |
181 | lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg); | |
182 | timing = stb0899_read_reg(state, STB0899_RTF); | |
183 | ||
184 | if (lock >= 42) { | |
eadf29b9 | 185 | if ((lock > 48) && (ABS(timing) >= 110)) { |
8bd135ba MA |
186 | internal->status = ANALOGCARRIER; |
187 | dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !"); | |
188 | } else { | |
189 | internal->status = TIMINGOK; | |
190 | dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !"); | |
191 | } | |
192 | } else { | |
193 | internal->status = NOTIMING; | |
194 | dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !"); | |
195 | } | |
196 | return internal->status; | |
197 | } | |
198 | ||
199 | /* | |
200 | * stb0899_search_tmg | |
201 | * perform a fs/2 zig-zag to find timing | |
202 | */ | |
203 | static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state) | |
204 | { | |
205 | struct stb0899_internal *internal = &state->internal; | |
206 | struct stb0899_params *params = &state->params; | |
207 | ||
208 | short int derot_step, derot_freq = 0, derot_limit, next_loop = 3; | |
209 | int index = 0; | |
210 | u8 cfr[2]; | |
211 | ||
212 | internal->status = NOTIMING; | |
213 | ||
214 | /* timing loop computation & symbol rate optimisation */ | |
215 | derot_limit = (internal->sub_range / 2L) / internal->mclk; | |
216 | derot_step = (params->srate / 2L) / internal->mclk; | |
217 | ||
218 | while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) { | |
219 | index++; | |
220 | derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */ | |
221 | ||
222 | if (ABS(derot_freq) > derot_limit) | |
223 | next_loop--; | |
224 | ||
225 | if (next_loop) { | |
226 | STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq)); | |
227 | STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); | |
228 | stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ | |
229 | } | |
230 | internal->direction = -internal->direction; /* Change zigzag direction */ | |
231 | } | |
232 | ||
233 | if (internal->status == TIMINGOK) { | |
234 | stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ | |
235 | internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]); | |
236 | dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq); | |
237 | } | |
238 | ||
239 | return internal->status; | |
240 | } | |
241 | ||
242 | /* | |
243 | * stb0899_check_carrier | |
244 | * Check for carrier found | |
245 | */ | |
246 | static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state) | |
247 | { | |
248 | struct stb0899_internal *internal = &state->internal; | |
249 | u8 reg; | |
250 | ||
251 | msleep(internal->t_derot); /* wait for derotator ok */ | |
252 | ||
253 | reg = stb0899_read_reg(state, STB0899_CFD); | |
254 | STB0899_SETFIELD_VAL(CFD_ON, reg, 1); | |
57ad94a6 | 255 | stb0899_write_reg(state, STB0899_CFD, reg); |
8bd135ba MA |
256 | |
257 | reg = stb0899_read_reg(state, STB0899_DSTATUS); | |
258 | dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg); | |
259 | if (STB0899_GETFIELD(CARRIER_FOUND, reg)) { | |
260 | internal->status = CARRIEROK; | |
261 | dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !"); | |
262 | } else { | |
263 | internal->status = NOCARRIER; | |
264 | dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !"); | |
265 | } | |
266 | ||
267 | return internal->status; | |
268 | } | |
269 | ||
270 | /* | |
271 | * stb0899_search_carrier | |
272 | * Search for a QPSK carrier with the derotator | |
273 | */ | |
274 | static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state) | |
275 | { | |
276 | struct stb0899_internal *internal = &state->internal; | |
277 | ||
278 | short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3; | |
279 | int index = 0; | |
280 | u8 cfr[2]; | |
281 | u8 reg; | |
282 | ||
283 | internal->status = NOCARRIER; | |
284 | derot_limit = (internal->sub_range / 2L) / internal->mclk; | |
285 | derot_freq = internal->derot_freq; | |
286 | ||
287 | reg = stb0899_read_reg(state, STB0899_CFD); | |
288 | STB0899_SETFIELD_VAL(CFD_ON, reg, 1); | |
57ad94a6 | 289 | stb0899_write_reg(state, STB0899_CFD, reg); |
8bd135ba MA |
290 | |
291 | do { | |
292 | dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk); | |
293 | if (stb0899_check_carrier(state) == NOCARRIER) { | |
294 | index++; | |
295 | last_derot_freq = derot_freq; | |
3f400925 | 296 | derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */ |
8bd135ba MA |
297 | |
298 | if(ABS(derot_freq) > derot_limit) | |
299 | next_loop--; | |
300 | ||
301 | if (next_loop) { | |
302 | reg = stb0899_read_reg(state, STB0899_CFD); | |
303 | STB0899_SETFIELD_VAL(CFD_ON, reg, 1); | |
57ad94a6 | 304 | stb0899_write_reg(state, STB0899_CFD, reg); |
8bd135ba MA |
305 | |
306 | STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq)); | |
307 | STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); | |
308 | stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ | |
309 | } | |
310 | } | |
311 | ||
3f400925 | 312 | internal->direction = -internal->direction; /* Change zigzag direction */ |
8bd135ba MA |
313 | } while ((internal->status != CARRIEROK) && next_loop); |
314 | ||
315 | if (internal->status == CARRIEROK) { | |
3f400925 | 316 | stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ |
8bd135ba MA |
317 | internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]); |
318 | dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq); | |
319 | } else { | |
320 | internal->derot_freq = last_derot_freq; | |
321 | } | |
322 | ||
323 | return internal->status; | |
324 | } | |
325 | ||
326 | /* | |
327 | * stb0899_check_data | |
328 | * Check for data found | |
329 | */ | |
330 | static enum stb0899_status stb0899_check_data(struct stb0899_state *state) | |
331 | { | |
332 | struct stb0899_internal *internal = &state->internal; | |
333 | struct stb0899_params *params = &state->params; | |
334 | ||
335 | int lock = 0, index = 0, dataTime = 500, loop; | |
336 | u8 reg; | |
337 | ||
338 | internal->status = NODATA; | |
339 | ||
340 | /* RESET FEC */ | |
341 | reg = stb0899_read_reg(state, STB0899_TSTRES); | |
342 | STB0899_SETFIELD_VAL(FRESACS, reg, 1); | |
343 | stb0899_write_reg(state, STB0899_TSTRES, reg); | |
344 | msleep(1); | |
345 | reg = stb0899_read_reg(state, STB0899_TSTRES); | |
346 | STB0899_SETFIELD_VAL(FRESACS, reg, 0); | |
347 | stb0899_write_reg(state, STB0899_TSTRES, reg); | |
348 | ||
349 | if (params->srate <= 2000000) | |
350 | dataTime = 2000; | |
351 | else if (params->srate <= 5000000) | |
352 | dataTime = 1500; | |
353 | else if (params->srate <= 15000000) | |
354 | dataTime = 1000; | |
355 | else | |
356 | dataTime = 500; | |
357 | ||
358 | stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */ | |
359 | while (1) { | |
360 | /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */ | |
361 | reg = stb0899_read_reg(state, STB0899_VSTATUS); | |
362 | lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg); | |
363 | loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg); | |
364 | ||
365 | if (lock || loop || (index > dataTime)) | |
366 | break; | |
367 | index++; | |
368 | } | |
369 | ||
370 | if (lock) { /* DATA LOCK indicator */ | |
371 | internal->status = DATAOK; | |
372 | dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !"); | |
373 | } | |
374 | ||
375 | return internal->status; | |
376 | } | |
377 | ||
378 | /* | |
379 | * stb0899_search_data | |
380 | * Search for a QPSK carrier with the derotator | |
381 | */ | |
382 | static enum stb0899_status stb0899_search_data(struct stb0899_state *state) | |
383 | { | |
384 | short int derot_freq, derot_step, derot_limit, next_loop = 3; | |
385 | u8 cfr[2]; | |
386 | u8 reg; | |
387 | int index = 1; | |
388 | ||
389 | struct stb0899_internal *internal = &state->internal; | |
390 | struct stb0899_params *params = &state->params; | |
391 | ||
392 | derot_step = (params->srate / 4L) / internal->mclk; | |
393 | derot_limit = (internal->sub_range / 2L) / internal->mclk; | |
394 | derot_freq = internal->derot_freq; | |
395 | ||
396 | do { | |
397 | if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) { | |
398 | ||
3f400925 | 399 | derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */ |
8bd135ba MA |
400 | if (ABS(derot_freq) > derot_limit) |
401 | next_loop--; | |
402 | ||
403 | if (next_loop) { | |
404 | dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk); | |
405 | reg = stb0899_read_reg(state, STB0899_CFD); | |
406 | STB0899_SETFIELD_VAL(CFD_ON, reg, 1); | |
57ad94a6 | 407 | stb0899_write_reg(state, STB0899_CFD, reg); |
8bd135ba MA |
408 | |
409 | STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq)); | |
410 | STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); | |
411 | stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ | |
412 | ||
413 | stb0899_check_carrier(state); | |
414 | index++; | |
415 | } | |
416 | } | |
3f400925 | 417 | internal->direction = -internal->direction; /* change zig zag direction */ |
8bd135ba MA |
418 | } while ((internal->status != DATAOK) && next_loop); |
419 | ||
420 | if (internal->status == DATAOK) { | |
3f400925 | 421 | stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */ |
8bd135ba MA |
422 | internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]); |
423 | dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq); | |
424 | } | |
425 | ||
426 | return internal->status; | |
427 | } | |
428 | ||
429 | /* | |
430 | * stb0899_check_range | |
431 | * check if the found frequency is in the correct range | |
432 | */ | |
433 | static enum stb0899_status stb0899_check_range(struct stb0899_state *state) | |
434 | { | |
435 | struct stb0899_internal *internal = &state->internal; | |
436 | struct stb0899_params *params = &state->params; | |
437 | ||
438 | int range_offst, tp_freq; | |
439 | ||
440 | range_offst = internal->srch_range / 2000; | |
441 | tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000; | |
442 | ||
443 | if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) { | |
444 | internal->status = RANGEOK; | |
445 | dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !"); | |
446 | } else { | |
447 | internal->status = OUTOFRANGE; | |
448 | dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !"); | |
449 | } | |
450 | ||
451 | return internal->status; | |
452 | } | |
453 | ||
454 | /* | |
455 | * NextSubRange | |
456 | * Compute the next subrange of the search | |
457 | */ | |
458 | static void next_sub_range(struct stb0899_state *state) | |
459 | { | |
460 | struct stb0899_internal *internal = &state->internal; | |
461 | struct stb0899_params *params = &state->params; | |
462 | ||
463 | long old_sub_range; | |
464 | ||
465 | if (internal->sub_dir > 0) { | |
466 | old_sub_range = internal->sub_range; | |
467 | internal->sub_range = MIN((internal->srch_range / 2) - | |
468 | (internal->tuner_offst + internal->sub_range / 2), | |
469 | internal->sub_range); | |
470 | ||
471 | if (internal->sub_range < 0) | |
472 | internal->sub_range = 0; | |
473 | ||
474 | internal->tuner_offst += (old_sub_range + internal->sub_range) / 2; | |
475 | } | |
476 | ||
477 | internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000; | |
478 | internal->sub_dir = -internal->sub_dir; | |
479 | } | |
480 | ||
481 | /* | |
482 | * stb0899_dvbs_algo | |
483 | * Search for a signal, timing, carrier and data for a | |
484 | * given frequency in a given range | |
485 | */ | |
486 | enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state) | |
487 | { | |
488 | struct stb0899_params *params = &state->params; | |
489 | struct stb0899_internal *internal = &state->internal; | |
490 | struct stb0899_config *config = state->config; | |
491 | ||
492 | u8 bclc, reg; | |
7d8f1e57 | 493 | u8 cfr[2]; |
8bd135ba MA |
494 | u8 eq_const[10]; |
495 | s32 clnI = 3; | |
496 | u32 bandwidth = 0; | |
497 | ||
498 | /* BETA values rated @ 99MHz */ | |
499 | s32 betaTab[5][4] = { | |
500 | /* 5 10 20 30MBps */ | |
501 | { 37, 34, 32, 31 }, /* QPSK 1/2 */ | |
502 | { 37, 35, 33, 31 }, /* QPSK 2/3 */ | |
503 | { 37, 35, 33, 31 }, /* QPSK 3/4 */ | |
504 | { 37, 36, 33, 32 }, /* QPSK 5/6 */ | |
505 | { 37, 36, 33, 32 } /* QPSK 7/8 */ | |
506 | }; | |
507 | ||
508 | internal->direction = 1; | |
509 | ||
510 | stb0899_set_srate(state, internal->master_clk, params->srate); | |
511 | /* Carrier loop optimization versus symbol rate for acquisition*/ | |
512 | if (params->srate <= 5000000) { | |
513 | stb0899_write_reg(state, STB0899_ACLC, 0x89); | |
514 | bclc = stb0899_read_reg(state, STB0899_BCLC); | |
515 | STB0899_SETFIELD_VAL(BETA, bclc, 0x1c); | |
516 | stb0899_write_reg(state, STB0899_BCLC, bclc); | |
517 | clnI = 0; | |
518 | } else if (params->srate <= 15000000) { | |
519 | stb0899_write_reg(state, STB0899_ACLC, 0xc9); | |
520 | bclc = stb0899_read_reg(state, STB0899_BCLC); | |
521 | STB0899_SETFIELD_VAL(BETA, bclc, 0x22); | |
522 | stb0899_write_reg(state, STB0899_BCLC, bclc); | |
523 | clnI = 1; | |
524 | } else if(params->srate <= 25000000) { | |
525 | stb0899_write_reg(state, STB0899_ACLC, 0x89); | |
526 | bclc = stb0899_read_reg(state, STB0899_BCLC); | |
527 | STB0899_SETFIELD_VAL(BETA, bclc, 0x27); | |
528 | stb0899_write_reg(state, STB0899_BCLC, bclc); | |
529 | clnI = 2; | |
530 | } else { | |
531 | stb0899_write_reg(state, STB0899_ACLC, 0xc8); | |
532 | bclc = stb0899_read_reg(state, STB0899_BCLC); | |
533 | STB0899_SETFIELD_VAL(BETA, bclc, 0x29); | |
534 | stb0899_write_reg(state, STB0899_BCLC, bclc); | |
535 | clnI = 3; | |
536 | } | |
537 | ||
538 | dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition"); | |
539 | /* Set the timing loop to acquisition */ | |
540 | stb0899_write_reg(state, STB0899_RTC, 0x46); | |
541 | stb0899_write_reg(state, STB0899_CFD, 0xee); | |
542 | ||
543 | /* !! WARNING !! | |
544 | * Do not read any status variables while acquisition, | |
545 | * If any needed, read before the acquisition starts | |
546 | * querying status while acquiring causes the | |
547 | * acquisition to go bad and hence no locks. | |
548 | */ | |
549 | dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d", | |
550 | internal->derot_percent, params->srate, internal->mclk); | |
551 | ||
552 | /* Initial calculations */ | |
553 | internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */ | |
8bd135ba MA |
554 | internal->t_derot = stb0899_calc_derot_time(params->srate); |
555 | internal->t_data = 500; | |
556 | ||
557 | dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger"); | |
558 | /* RESET Stream merger */ | |
559 | reg = stb0899_read_reg(state, STB0899_TSTRES); | |
560 | STB0899_SETFIELD_VAL(FRESRS, reg, 1); | |
561 | stb0899_write_reg(state, STB0899_TSTRES, reg); | |
562 | ||
563 | /* | |
564 | * Set KDIVIDER to an intermediate value between | |
565 | * 1/2 and 7/8 for acquisition | |
566 | */ | |
567 | reg = stb0899_read_reg(state, STB0899_DEMAPVIT); | |
568 | STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60); | |
569 | stb0899_write_reg(state, STB0899_DEMAPVIT, reg); | |
570 | ||
3f400925 | 571 | stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */ |
8bd135ba MA |
572 | stb0899_write_reg(state, STB0899_VITSYNC, 0x19); |
573 | ||
574 | stb0899_first_subrange(state); | |
575 | do { | |
3f400925 | 576 | /* Initialisations */ |
8bd135ba MA |
577 | cfr[0] = cfr[1] = 0; |
578 | stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */ | |
579 | ||
85eabac4 | 580 | stb0899_write_reg(state, STB0899_RTF, 0); |
8bd135ba MA |
581 | reg = stb0899_read_reg(state, STB0899_CFD); |
582 | STB0899_SETFIELD_VAL(CFD_ON, reg, 1); | |
57ad94a6 | 583 | stb0899_write_reg(state, STB0899_CFD, reg); |
8bd135ba MA |
584 | |
585 | internal->derot_freq = 0; | |
586 | internal->status = NOAGC1; | |
587 | ||
40e8ce3d MA |
588 | /* enable tuner I/O */ |
589 | stb0899_i2c_gate_ctrl(&state->frontend, 1); | |
590 | ||
3f400925 | 591 | /* Move tuner to frequency */ |
8bd135ba MA |
592 | dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency"); |
593 | if (state->config->tuner_set_frequency) | |
594 | state->config->tuner_set_frequency(&state->frontend, internal->freq); | |
595 | ||
8bd135ba MA |
596 | if (state->config->tuner_get_frequency) |
597 | state->config->tuner_get_frequency(&state->frontend, &internal->freq); | |
598 | ||
b359325d | 599 | msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */ |
8bd135ba MA |
600 | dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq); |
601 | internal->status = AGC1OK; | |
602 | ||
603 | /* There is signal in the band */ | |
604 | if (config->tuner_get_bandwidth) | |
605 | config->tuner_get_bandwidth(&state->frontend, &bandwidth); | |
40e8ce3d MA |
606 | |
607 | /* disable tuner I/O */ | |
608 | stb0899_i2c_gate_ctrl(&state->frontend, 0); | |
609 | ||
8bd135ba MA |
610 | if (params->srate <= bandwidth / 2) |
611 | stb0899_search_tmg(state); /* For low rates (SCPC) */ | |
612 | else | |
613 | stb0899_check_tmg(state); /* For high rates (MCPC) */ | |
614 | ||
615 | if (internal->status == TIMINGOK) { | |
616 | dprintk(state->verbose, FE_DEBUG, 1, | |
617 | "TIMING OK ! Derot freq=%d, mclk=%d", | |
618 | internal->derot_freq, internal->mclk); | |
619 | ||
620 | if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */ | |
621 | dprintk(state->verbose, FE_DEBUG, 1, | |
622 | "CARRIER OK ! Derot freq=%d, mclk=%d", | |
623 | internal->derot_freq, internal->mclk); | |
624 | ||
625 | if (stb0899_search_data(state) == DATAOK) { /* Check for data */ | |
626 | dprintk(state->verbose, FE_DEBUG, 1, | |
627 | "DATA OK ! Derot freq=%d, mclk=%d", | |
628 | internal->derot_freq, internal->mclk); | |
629 | ||
630 | if (stb0899_check_range(state) == RANGEOK) { | |
631 | dprintk(state->verbose, FE_DEBUG, 1, | |
632 | "RANGE OK ! derot freq=%d, mclk=%d", | |
633 | internal->derot_freq, internal->mclk); | |
634 | ||
635 | internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000); | |
636 | reg = stb0899_read_reg(state, STB0899_PLPARM); | |
637 | internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg); | |
638 | dprintk(state->verbose, FE_DEBUG, 1, | |
639 | "freq=%d, internal resultant freq=%d", | |
640 | params->freq, internal->freq); | |
641 | ||
642 | dprintk(state->verbose, FE_DEBUG, 1, | |
643 | "internal puncture rate=%d", | |
644 | internal->fecrate); | |
645 | } | |
646 | } | |
647 | } | |
648 | } | |
649 | if (internal->status != RANGEOK) | |
650 | next_sub_range(state); | |
651 | ||
652 | } while (internal->sub_range && internal->status != RANGEOK); | |
653 | ||
654 | /* Set the timing loop to tracking */ | |
655 | stb0899_write_reg(state, STB0899_RTC, 0x33); | |
656 | stb0899_write_reg(state, STB0899_CFD, 0xf7); | |
8bd135ba MA |
657 | /* if locked and range ok, set Kdiv */ |
658 | if (internal->status == RANGEOK) { | |
659 | dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !"); | |
660 | stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */ | |
661 | stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */ | |
662 | ||
663 | /* | |
664 | * Carrier loop optimization versus | |
665 | * symbol Rate/Puncture Rate for Tracking | |
666 | */ | |
b655b6cb | 667 | reg = stb0899_read_reg(state, STB0899_BCLC); |
8bd135ba MA |
668 | switch (internal->fecrate) { |
669 | case STB0899_FEC_1_2: /* 13 */ | |
b655b6cb | 670 | stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a); |
8bd135ba MA |
671 | STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]); |
672 | stb0899_write_reg(state, STB0899_BCLC, reg); | |
673 | break; | |
674 | case STB0899_FEC_2_3: /* 18 */ | |
b655b6cb | 675 | stb0899_write_reg(state, STB0899_DEMAPVIT, 44); |
8bd135ba MA |
676 | STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]); |
677 | stb0899_write_reg(state, STB0899_BCLC, reg); | |
678 | break; | |
679 | case STB0899_FEC_3_4: /* 21 */ | |
b655b6cb | 680 | stb0899_write_reg(state, STB0899_DEMAPVIT, 60); |
8bd135ba MA |
681 | STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]); |
682 | stb0899_write_reg(state, STB0899_BCLC, reg); | |
683 | break; | |
684 | case STB0899_FEC_5_6: /* 24 */ | |
b655b6cb | 685 | stb0899_write_reg(state, STB0899_DEMAPVIT, 75); |
8bd135ba MA |
686 | STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]); |
687 | stb0899_write_reg(state, STB0899_BCLC, reg); | |
688 | break; | |
689 | case STB0899_FEC_6_7: /* 25 */ | |
b655b6cb | 690 | stb0899_write_reg(state, STB0899_DEMAPVIT, 88); |
8bd135ba MA |
691 | stb0899_write_reg(state, STB0899_ACLC, 0x88); |
692 | stb0899_write_reg(state, STB0899_BCLC, 0x9a); | |
693 | break; | |
694 | case STB0899_FEC_7_8: /* 26 */ | |
b655b6cb | 695 | stb0899_write_reg(state, STB0899_DEMAPVIT, 94); |
8bd135ba MA |
696 | STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]); |
697 | stb0899_write_reg(state, STB0899_BCLC, reg); | |
698 | break; | |
699 | default: | |
700 | dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate"); | |
701 | break; | |
702 | } | |
703 | /* release stream merger RESET */ | |
704 | reg = stb0899_read_reg(state, STB0899_TSTRES); | |
705 | STB0899_SETFIELD_VAL(FRESRS, reg, 0); | |
706 | stb0899_write_reg(state, STB0899_TSTRES, reg); | |
707 | ||
708 | /* disable carrier detector */ | |
709 | reg = stb0899_read_reg(state, STB0899_CFD); | |
710 | STB0899_SETFIELD_VAL(CFD_ON, reg, 0); | |
57ad94a6 | 711 | stb0899_write_reg(state, STB0899_CFD, reg); |
8bd135ba MA |
712 | |
713 | stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10); | |
714 | } | |
715 | ||
716 | return internal->status; | |
717 | } | |
718 | ||
719 | /* | |
720 | * stb0899_dvbs2_config_uwp | |
721 | * Configure UWP state machine | |
722 | */ | |
723 | static void stb0899_dvbs2_config_uwp(struct stb0899_state *state) | |
724 | { | |
725 | struct stb0899_internal *internal = &state->internal; | |
726 | struct stb0899_config *config = state->config; | |
727 | u32 uwp1, uwp2, uwp3, reg; | |
728 | ||
729 | uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1); | |
730 | uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2); | |
731 | uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3); | |
732 | ||
733 | STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave); | |
734 | STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant); | |
735 | STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof); | |
736 | ||
737 | STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse); | |
738 | STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine); | |
739 | STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold); | |
740 | ||
741 | STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq); | |
742 | STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track); | |
743 | ||
744 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1); | |
745 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2); | |
746 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3); | |
747 | ||
748 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO); | |
749 | STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout); | |
750 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg); | |
751 | } | |
752 | ||
753 | /* | |
754 | * stb0899_dvbs2_config_csm_auto | |
755 | * Set CSM to AUTO mode | |
756 | */ | |
757 | static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state) | |
758 | { | |
759 | u32 reg; | |
760 | ||
761 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); | |
762 | STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1); | |
763 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg); | |
764 | } | |
765 | ||
766 | long Log2Int(int number) | |
767 | { | |
768 | int i; | |
769 | ||
770 | i = 0; | |
771 | while ((1 << i) <= ABS(number)) | |
772 | i++; | |
773 | ||
774 | if (number == 0) | |
775 | i = 1; | |
776 | ||
777 | return i - 1; | |
778 | } | |
779 | ||
780 | /* | |
781 | * stb0899_dvbs2_calc_srate | |
782 | * compute BTR_NOM_FREQ for the symbol rate | |
783 | */ | |
784 | static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state) | |
785 | { | |
786 | struct stb0899_internal *internal = &state->internal; | |
787 | struct stb0899_config *config = state->config; | |
788 | ||
789 | u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq; | |
790 | u32 master_clk, srate; | |
791 | ||
792 | dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); | |
793 | dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; | |
794 | dec_rate = Log2Int(dec_ratio); | |
795 | decim = 1 << dec_rate; | |
796 | master_clk = internal->master_clk / 1000; | |
797 | srate = internal->srate / 1000; | |
798 | ||
799 | if (decim <= 4) { | |
800 | intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk; | |
801 | remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk; | |
802 | } else { | |
803 | intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100; | |
804 | remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk; | |
805 | } | |
806 | btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk); | |
807 | ||
808 | return btr_nom_freq; | |
809 | } | |
810 | ||
811 | /* | |
812 | * stb0899_dvbs2_calc_dev | |
813 | * compute the correction to be applied to symbol rate | |
814 | */ | |
815 | static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state) | |
816 | { | |
817 | struct stb0899_internal *internal = &state->internal; | |
818 | u32 dec_ratio, correction, master_clk, srate; | |
819 | ||
820 | dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); | |
821 | dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; | |
822 | ||
823 | master_clk = internal->master_clk / 1000; /* for integer Caculation*/ | |
824 | srate = internal->srate / 1000; /* for integer Caculation*/ | |
825 | correction = (512 * master_clk) / (2 * dec_ratio * srate); | |
826 | ||
827 | return correction; | |
828 | } | |
829 | ||
830 | /* | |
831 | * stb0899_dvbs2_set_srate | |
832 | * Set DVBS2 symbol rate | |
833 | */ | |
834 | static void stb0899_dvbs2_set_srate(struct stb0899_state *state) | |
835 | { | |
836 | struct stb0899_internal *internal = &state->internal; | |
837 | ||
838 | u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq; | |
839 | u32 correction, freq_adj, band_lim, decim_cntrl, reg; | |
840 | u8 anti_alias; | |
841 | ||
842 | /*set decimation to 1*/ | |
843 | dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); | |
844 | dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; | |
845 | dec_rate = Log2Int(dec_ratio); | |
846 | ||
847 | win_sel = 0; | |
848 | if (dec_rate >= 5) | |
849 | win_sel = dec_rate - 4; | |
850 | ||
851 | decim = (1 << dec_rate); | |
852 | /* (FSamp/Fsymbol *100) for integer Caculation */ | |
853 | f_sym = internal->master_clk / ((decim * internal->srate) / 1000); | |
854 | ||
855 | if (f_sym <= 2250) /* don't band limit signal going into btr block*/ | |
856 | band_lim = 1; | |
857 | else | |
858 | band_lim = 0; /* band limit signal going into btr block*/ | |
859 | ||
860 | decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7); | |
861 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl); | |
862 | ||
863 | if (f_sym <= 3450) | |
864 | anti_alias = 0; | |
865 | else if (f_sym <= 4250) | |
866 | anti_alias = 1; | |
867 | else | |
868 | anti_alias = 2; | |
869 | ||
870 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias); | |
871 | btr_nom_freq = stb0899_dvbs2_calc_srate(state); | |
872 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq); | |
873 | ||
874 | correction = stb0899_dvbs2_calc_dev(state); | |
875 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); | |
876 | STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction); | |
877 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); | |
878 | ||
879 | /* scale UWP+CSM frequency to sample rate*/ | |
880 | freq_adj = internal->srate / (internal->master_clk / 4096); | |
881 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj); | |
882 | } | |
883 | ||
884 | /* | |
885 | * stb0899_dvbs2_set_btr_loopbw | |
886 | * set bit timing loop bandwidth as a percentage of the symbol rate | |
887 | */ | |
888 | static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state) | |
889 | { | |
890 | struct stb0899_internal *internal = &state->internal; | |
891 | struct stb0899_config *config = state->config; | |
892 | ||
893 | u32 sym_peak = 23, zeta = 707, loopbw_percent = 60; | |
894 | s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft; | |
895 | s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift; | |
896 | u32 decim, K, wn, k_direct, k_indirect; | |
897 | u32 reg; | |
898 | ||
899 | dec_ratio = (internal->master_clk * 2) / (5 * internal->srate); | |
900 | dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio; | |
901 | dec_rate = Log2Int(dec_ratio); | |
902 | decim = (1 << dec_rate); | |
903 | ||
904 | sym_peak *= 576000; | |
905 | K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000); | |
906 | K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/ | |
8bd135ba MA |
907 | |
908 | if (K != 0) { | |
b797c206 | 909 | K = sym_peak / K; |
8bd135ba MA |
910 | wn = (4 * zeta * zeta) + 1000000; |
911 | wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/ | |
912 | ||
913 | k_indirect = (wn * wn) / K; | |
914 | k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/ | |
915 | k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/ | |
916 | k_direct *= 100; | |
917 | ||
918 | k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2; | |
919 | k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset; | |
920 | k_btr1 = k_direct / (1 << k_direct_shift); | |
921 | k_btr1 /= 10000; | |
922 | ||
923 | k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/; | |
924 | k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset; | |
925 | k_btr0 = k_indirect * (1 << (-k_indirect_shift)); | |
926 | k_btr0 /= 1000000; | |
927 | ||
928 | k_btr2_rshft = 0; | |
929 | if (k_btr0_rshft > 15) { | |
930 | k_btr2_rshft = k_btr0_rshft - 15; | |
931 | k_btr0_rshft = 15; | |
932 | } | |
933 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN); | |
934 | STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft); | |
935 | STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0); | |
936 | STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft); | |
937 | STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1); | |
938 | STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft); | |
939 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg); | |
940 | } else | |
941 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f); | |
942 | } | |
943 | ||
944 | /* | |
945 | * stb0899_dvbs2_set_carr_freq | |
946 | * set nominal frequency for carrier search | |
947 | */ | |
948 | static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk) | |
949 | { | |
950 | struct stb0899_config *config = state->config; | |
951 | s32 crl_nom_freq; | |
952 | u32 reg; | |
953 | ||
954 | crl_nom_freq = (1 << config->crl_nco_bits) / master_clk; | |
955 | crl_nom_freq *= carr_freq; | |
956 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); | |
957 | STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq); | |
958 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); | |
959 | } | |
960 | ||
961 | /* | |
962 | * stb0899_dvbs2_init_calc | |
963 | * Initialize DVBS2 UWP, CSM, carrier and timing loops | |
964 | */ | |
965 | static void stb0899_dvbs2_init_calc(struct stb0899_state *state) | |
966 | { | |
967 | struct stb0899_internal *internal = &state->internal; | |
968 | s32 steps, step_size; | |
969 | u32 range, reg; | |
970 | ||
971 | /* config uwp and csm */ | |
972 | stb0899_dvbs2_config_uwp(state); | |
973 | stb0899_dvbs2_config_csm_auto(state); | |
974 | ||
975 | /* initialize BTR */ | |
976 | stb0899_dvbs2_set_srate(state); | |
977 | stb0899_dvbs2_set_btr_loopbw(state); | |
978 | ||
979 | if (internal->srate / 1000000 >= 15) | |
980 | step_size = (1 << 17) / 5; | |
981 | else if (internal->srate / 1000000 >= 10) | |
982 | step_size = (1 << 17) / 7; | |
983 | else if (internal->srate / 1000000 >= 5) | |
984 | step_size = (1 << 17) / 10; | |
985 | else | |
986 | step_size = (1 << 17) / 4; | |
987 | ||
988 | range = internal->srch_range / 1000000; | |
989 | steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000)); | |
990 | steps = (steps + 6) / 10; | |
991 | steps = (steps == 0) ? 1 : steps; | |
992 | if (steps % 2 == 0) | |
993 | stb0899_dvbs2_set_carr_freq(state, internal->center_freq - | |
994 | (internal->step_size * (internal->srate / 20000000)), | |
995 | (internal->master_clk) / 1000000); | |
996 | else | |
997 | stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000); | |
998 | ||
999 | /*Set Carrier Search params (zigzag, num steps and freq step size*/ | |
1000 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2); | |
1001 | STB0899_SETFIELD_VAL(ZIGZAG, reg, 1); | |
1002 | STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps); | |
1003 | STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size); | |
1004 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg); | |
1005 | } | |
1006 | ||
1007 | /* | |
1008 | * stb0899_dvbs2_btr_init | |
1009 | * initialize the timing loop | |
1010 | */ | |
1011 | static void stb0899_dvbs2_btr_init(struct stb0899_state *state) | |
1012 | { | |
1013 | u32 reg; | |
1014 | ||
1015 | /* set enable BTR loopback */ | |
1016 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); | |
1017 | STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1); | |
1018 | STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1); | |
1019 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); | |
1020 | ||
1021 | /* fix btr freq accum at 0 */ | |
1022 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000); | |
1023 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000); | |
1024 | ||
1025 | /* fix btr freq accum at 0 */ | |
1026 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000); | |
1027 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000); | |
1028 | } | |
1029 | ||
1030 | /* | |
1031 | * stb0899_dvbs2_reacquire | |
1032 | * trigger a DVB-S2 acquisition | |
1033 | */ | |
1034 | static void stb0899_dvbs2_reacquire(struct stb0899_state *state) | |
1035 | { | |
1036 | u32 reg = 0; | |
1037 | ||
1038 | /* demod soft reset */ | |
1039 | STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1); | |
1040 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); | |
1041 | ||
1042 | /*Reset Timing Loop */ | |
1043 | stb0899_dvbs2_btr_init(state); | |
1044 | ||
1045 | /* reset Carrier loop */ | |
1046 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30)); | |
1047 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0); | |
1048 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0); | |
1049 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30)); | |
1050 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0); | |
1051 | ||
1052 | /*release demod soft reset */ | |
1053 | reg = 0; | |
1054 | STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0); | |
1055 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); | |
1056 | ||
1057 | /* start acquisition process */ | |
1058 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1); | |
1059 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0); | |
1060 | ||
1061 | /* equalizer Init */ | |
1062 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1); | |
1063 | ||
1064 | /*Start equilizer */ | |
1065 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0); | |
1066 | ||
1067 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); | |
1068 | STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0); | |
1069 | STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0); | |
1070 | STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05); | |
1071 | STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01); | |
1072 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); | |
1073 | ||
1074 | /* RESET Packet delineator */ | |
1075 | stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a); | |
1076 | } | |
1077 | ||
1078 | /* | |
1079 | * stb0899_dvbs2_get_dmd_status | |
1080 | * get DVB-S2 Demod LOCK status | |
1081 | */ | |
1082 | static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout) | |
1083 | { | |
1084 | int time = -10, lock = 0, uwp, csm; | |
1085 | u32 reg; | |
1086 | ||
1087 | do { | |
1088 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS); | |
1089 | dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg); | |
1090 | if (STB0899_GETFIELD(IF_AGC_LOCK, reg)) | |
1091 | dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !"); | |
1092 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2); | |
1093 | dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg); | |
1094 | uwp = STB0899_GETFIELD(UWP_LOCK, reg); | |
1095 | csm = STB0899_GETFIELD(CSM_LOCK, reg); | |
1096 | if (uwp && csm) | |
1097 | lock = 1; | |
1098 | ||
1099 | time += 10; | |
1100 | msleep(10); | |
1101 | ||
1102 | } while ((!lock) && (time <= timeout)); | |
1103 | ||
1104 | if (lock) { | |
1105 | dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !"); | |
1106 | return DVBS2_DEMOD_LOCK; | |
1107 | } else { | |
1108 | return DVBS2_DEMOD_NOLOCK; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * stb0899_dvbs2_get_data_lock | |
1114 | * get FEC status | |
1115 | */ | |
1116 | static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout) | |
1117 | { | |
1118 | int time = 0, lock = 0; | |
1119 | u8 reg; | |
1120 | ||
1121 | while ((!lock) && (time < timeout)) { | |
1122 | reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); | |
1123 | dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg); | |
1124 | lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg); | |
1125 | time++; | |
1126 | } | |
1127 | ||
1128 | return lock; | |
1129 | } | |
1130 | ||
1131 | /* | |
1132 | * stb0899_dvbs2_get_fec_status | |
1133 | * get DVB-S2 FEC LOCK status | |
1134 | */ | |
1135 | static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout) | |
1136 | { | |
1137 | int time = 0, Locked; | |
1138 | ||
1139 | do { | |
1140 | Locked = stb0899_dvbs2_get_data_lock(state, 1); | |
1141 | time++; | |
1142 | msleep(1); | |
1143 | ||
1144 | } while ((!Locked) && (time < timeout)); | |
1145 | ||
1146 | if (Locked) { | |
1147 | dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !"); | |
1148 | return DVBS2_FEC_LOCK; | |
1149 | } else { | |
1150 | return DVBS2_FEC_NOLOCK; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | ||
1155 | /* | |
1156 | * stb0899_dvbs2_init_csm | |
1157 | * set parameters for manual mode | |
1158 | */ | |
1159 | static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod) | |
1160 | { | |
1161 | struct stb0899_internal *internal = &state->internal; | |
1162 | ||
1163 | s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80; | |
1164 | s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr; | |
1165 | u32 csm1, csm2, csm3, csm4; | |
1166 | ||
1167 | if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) { | |
1168 | switch (modcod) { | |
1169 | case STB0899_QPSK_12: | |
1170 | gamma_acq = 25; | |
1171 | gamma_rho_acq = 2700; | |
1172 | gamma_trk = 12; | |
1173 | gamma_rho_trk = 180; | |
1174 | lock_count_thr = 8; | |
1175 | break; | |
1176 | case STB0899_QPSK_35: | |
1177 | gamma_acq = 38; | |
1178 | gamma_rho_acq = 7182; | |
1179 | gamma_trk = 14; | |
1180 | gamma_rho_trk = 308; | |
1181 | lock_count_thr = 8; | |
1182 | break; | |
1183 | case STB0899_QPSK_23: | |
1184 | gamma_acq = 42; | |
1185 | gamma_rho_acq = 9408; | |
1186 | gamma_trk = 17; | |
1187 | gamma_rho_trk = 476; | |
1188 | lock_count_thr = 8; | |
1189 | break; | |
1190 | case STB0899_QPSK_34: | |
1191 | gamma_acq = 53; | |
1192 | gamma_rho_acq = 16642; | |
1193 | gamma_trk = 19; | |
1194 | gamma_rho_trk = 646; | |
1195 | lock_count_thr = 8; | |
1196 | break; | |
1197 | case STB0899_QPSK_45: | |
1198 | gamma_acq = 53; | |
1199 | gamma_rho_acq = 17119; | |
1200 | gamma_trk = 22; | |
1201 | gamma_rho_trk = 880; | |
1202 | lock_count_thr = 8; | |
1203 | break; | |
1204 | case STB0899_QPSK_56: | |
1205 | gamma_acq = 55; | |
1206 | gamma_rho_acq = 19250; | |
1207 | gamma_trk = 23; | |
1208 | gamma_rho_trk = 989; | |
1209 | lock_count_thr = 8; | |
1210 | break; | |
1211 | case STB0899_QPSK_89: | |
1212 | gamma_acq = 60; | |
1213 | gamma_rho_acq = 24240; | |
1214 | gamma_trk = 24; | |
1215 | gamma_rho_trk = 1176; | |
1216 | lock_count_thr = 8; | |
1217 | break; | |
1218 | case STB0899_QPSK_910: | |
1219 | gamma_acq = 66; | |
1220 | gamma_rho_acq = 29634; | |
1221 | gamma_trk = 24; | |
1222 | gamma_rho_trk = 1176; | |
1223 | lock_count_thr = 8; | |
1224 | break; | |
1225 | default: | |
1226 | gamma_acq = 66; | |
1227 | gamma_rho_acq = 29634; | |
1228 | gamma_trk = 24; | |
1229 | gamma_rho_trk = 1176; | |
1230 | lock_count_thr = 8; | |
1231 | break; | |
1232 | } | |
1233 | ||
1234 | csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); | |
1235 | STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0); | |
1236 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); | |
1237 | ||
1238 | csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); | |
1239 | csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2); | |
1240 | csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3); | |
1241 | csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4); | |
1242 | ||
1243 | STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl); | |
1244 | STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass); | |
1245 | STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain); | |
1246 | STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift); | |
1247 | STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift); | |
1248 | STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq); | |
1249 | STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq); | |
1250 | STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk); | |
1251 | STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk); | |
1252 | STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr); | |
1253 | STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr); | |
1254 | ||
1255 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); | |
1256 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2); | |
1257 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3); | |
1258 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4); | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | /* | |
1263 | * stb0899_dvbs2_get_srate | |
1264 | * get DVB-S2 Symbol Rate | |
1265 | */ | |
1266 | static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state) | |
1267 | { | |
1268 | struct stb0899_internal *internal = &state->internal; | |
1269 | struct stb0899_config *config = state->config; | |
1270 | ||
1271 | u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg; | |
1272 | int div1, div2, rem1, rem2; | |
1273 | ||
1274 | div1 = config->btr_nco_bits / 2; | |
1275 | div2 = config->btr_nco_bits - div1 - 1; | |
1276 | ||
1277 | bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ); | |
1278 | ||
1279 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL); | |
1280 | decimRate = STB0899_GETFIELD(DECIM_RATE, reg); | |
1281 | decimRate = (1 << decimRate); | |
1282 | ||
1283 | intval1 = internal->master_clk / (1 << div1); | |
1284 | intval2 = bTrNomFreq / (1 << div2); | |
1285 | ||
1286 | rem1 = internal->master_clk % (1 << div1); | |
1287 | rem2 = bTrNomFreq % (1 << div2); | |
1288 | /* only for integer calculation */ | |
1289 | srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1)); | |
1290 | srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */ | |
1291 | ||
1292 | return srate; | |
1293 | } | |
1294 | ||
1295 | /* | |
1296 | * stb0899_dvbs2_algo | |
1297 | * Search for signal, timing, carrier and data for a given | |
1298 | * frequency in a given range | |
1299 | */ | |
1300 | enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state) | |
1301 | { | |
1302 | struct stb0899_internal *internal = &state->internal; | |
1303 | enum stb0899_modcod modcod; | |
1304 | ||
1305 | s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum; | |
1306 | int i = 0; | |
1307 | u32 reg, csm1; | |
1308 | ||
1309 | if (internal->srate <= 2000000) { | |
1310 | searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */ | |
1311 | FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */ | |
1312 | } else if (internal->srate <= 5000000) { | |
1313 | searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */ | |
1314 | FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */ | |
1315 | } else if (internal->srate <= 10000000) { | |
1316 | searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */ | |
1317 | FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */ | |
1318 | } else if (internal->srate <= 15000000) { | |
1319 | searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */ | |
1320 | FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */ | |
1321 | } else if (internal->srate <= 20000000) { | |
1322 | searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */ | |
1323 | FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */ | |
1324 | } else if (internal->srate <= 25000000) { | |
1325 | searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */ | |
1326 | FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */ | |
1327 | } else { | |
1328 | searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */ | |
1329 | FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */ | |
1330 | } | |
1331 | ||
1332 | /* Maintain Stream Merger in reset during acquisition */ | |
1333 | reg = stb0899_read_reg(state, STB0899_TSTRES); | |
1334 | STB0899_SETFIELD_VAL(FRESRS, reg, 1); | |
1335 | stb0899_write_reg(state, STB0899_TSTRES, reg); | |
1336 | ||
40e8ce3d MA |
1337 | /* enable tuner I/O */ |
1338 | stb0899_i2c_gate_ctrl(&state->frontend, 1); | |
1339 | ||
8bd135ba MA |
1340 | /* Move tuner to frequency */ |
1341 | if (state->config->tuner_set_frequency) | |
1342 | state->config->tuner_set_frequency(&state->frontend, internal->freq); | |
1343 | if (state->config->tuner_get_frequency) | |
1344 | state->config->tuner_get_frequency(&state->frontend, &internal->freq); | |
1345 | ||
40e8ce3d MA |
1346 | /* disable tuner I/O */ |
1347 | stb0899_i2c_gate_ctrl(&state->frontend, 0); | |
1348 | ||
8bd135ba MA |
1349 | /* Set IF AGC to acquisition */ |
1350 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); | |
1351 | STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4); | |
1352 | STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32); | |
1353 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); | |
1354 | ||
1355 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); | |
1356 | STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0); | |
1357 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); | |
1358 | ||
1359 | /* Initialisation */ | |
1360 | stb0899_dvbs2_init_calc(state); | |
1361 | ||
1362 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); | |
1363 | switch (internal->inversion) { | |
1364 | case IQ_SWAP_OFF: | |
1365 | STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0); | |
1366 | break; | |
1367 | case IQ_SWAP_ON: | |
1368 | STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1); | |
1369 | break; | |
1370 | case IQ_SWAP_AUTO: /* use last successful search first */ | |
1371 | STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1); | |
1372 | break; | |
1373 | } | |
1374 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); | |
1375 | stb0899_dvbs2_reacquire(state); | |
1376 | ||
1377 | /* Wait for demod lock (UWP and CSM) */ | |
1378 | internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime); | |
1379 | ||
1380 | if (internal->status == DVBS2_DEMOD_LOCK) { | |
1381 | dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !"); | |
1382 | i = 0; | |
1383 | /* Demod Locked, check FEC status */ | |
1384 | internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); | |
1385 | ||
1386 | /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/ | |
1387 | while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) { | |
1388 | /* Read the frequency offset*/ | |
1389 | offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ); | |
1390 | ||
1391 | /* Set the Nominal frequency to the found frequency offset for the next reacquire*/ | |
1392 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); | |
1393 | STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); | |
08bcdbec | 1394 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); |
8bd135ba MA |
1395 | stb0899_dvbs2_reacquire(state); |
1396 | internal->status = stb0899_dvbs2_get_fec_status(state, searchTime); | |
1397 | i++; | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | if (internal->status != DVBS2_FEC_LOCK) { | |
1402 | if (internal->inversion == IQ_SWAP_AUTO) { | |
1403 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); | |
1404 | iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg); | |
1405 | /* IQ Spectrum Inversion */ | |
1406 | STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum); | |
1407 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); | |
1408 | /* start acquistion process */ | |
1409 | stb0899_dvbs2_reacquire(state); | |
1410 | ||
1411 | /* Wait for demod lock (UWP and CSM) */ | |
1412 | internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime); | |
1413 | if (internal->status == DVBS2_DEMOD_LOCK) { | |
1414 | i = 0; | |
1415 | /* Demod Locked, check FEC */ | |
1416 | internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); | |
1417 | /*try thrice for false locks, (UWP and CSM Locked but no FEC) */ | |
1418 | while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) { | |
1419 | /* Read the frequency offset*/ | |
1420 | offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ); | |
1421 | ||
1422 | /* Set the Nominal frequency to the found frequency offset for the next reacquire*/ | |
1423 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); | |
1424 | STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); | |
08bcdbec | 1425 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); |
8bd135ba MA |
1426 | |
1427 | stb0899_dvbs2_reacquire(state); | |
1428 | internal->status = stb0899_dvbs2_get_fec_status(state, searchTime); | |
1429 | i++; | |
1430 | } | |
1431 | } | |
1432 | /* | |
1433 | if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED) | |
1434 | pParams->IQLocked = !iqSpectrum; | |
1435 | */ | |
1436 | } | |
1437 | } | |
1438 | if (internal->status == DVBS2_FEC_LOCK) { | |
1439 | dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !"); | |
1440 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); | |
1441 | modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; | |
1442 | pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; | |
1443 | ||
1444 | if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) && | |
1445 | (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) && | |
1446 | (pilots == 1)) { | |
1447 | ||
1448 | stb0899_dvbs2_init_csm(state, pilots, modcod); | |
1449 | /* Wait for UWP,CSM and data LOCK 20ms max */ | |
1450 | internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); | |
1451 | ||
1452 | i = 0; | |
1453 | while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) { | |
1454 | csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); | |
1455 | STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1); | |
1456 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); | |
1457 | csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); | |
1458 | STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0); | |
1459 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1); | |
1460 | ||
1461 | internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime); | |
1462 | i++; | |
1463 | } | |
1464 | } | |
1465 | ||
1466 | if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) && | |
1467 | (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) && | |
1468 | (pilots == 1)) { | |
1469 | ||
1470 | /* Equalizer Disable update */ | |
1471 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); | |
1472 | STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1); | |
1473 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); | |
1474 | } | |
1475 | ||
1476 | /* slow down the Equalizer once locked */ | |
1477 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); | |
1478 | STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02); | |
1479 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); | |
1480 | ||
1481 | /* Store signal parameters */ | |
1482 | offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ); | |
1483 | ||
1484 | offsetfreq = offsetfreq / ((1 << 30) / 1000); | |
1485 | offsetfreq *= (internal->master_clk / 1000000); | |
1486 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); | |
1487 | if (STB0899_GETFIELD(SPECTRUM_INVERT, reg)) | |
1488 | offsetfreq *= -1; | |
1489 | ||
1490 | internal->freq = internal->freq - offsetfreq; | |
1491 | internal->srate = stb0899_dvbs2_get_srate(state); | |
1492 | ||
1493 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); | |
1494 | internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; | |
1495 | internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; | |
1496 | internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01; | |
1497 | ||
1498 | /* Set IF AGC to tracking */ | |
1499 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); | |
1500 | STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3); | |
1501 | ||
1502 | /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/ | |
1503 | if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23)) | |
1504 | STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16); | |
1505 | ||
1506 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); | |
1507 | ||
1508 | reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); | |
1509 | STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7); | |
1510 | stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); | |
1511 | } | |
1512 | ||
1513 | /* Release Stream Merger Reset */ | |
1514 | reg = stb0899_read_reg(state, STB0899_TSTRES); | |
1515 | STB0899_SETFIELD_VAL(FRESRS, reg, 0); | |
1516 | stb0899_write_reg(state, STB0899_TSTRES, reg); | |
1517 | ||
1518 | return internal->status; | |
1519 | } |