]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | Driver for STV0297 demodulator | |
3 | ||
4 | Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net> | |
5 | Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de> | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/string.h> | |
26 | #include <linux/delay.h> | |
27 | ||
28 | #include "dvb_frontend.h" | |
29 | #include "stv0297.h" | |
30 | ||
31 | struct stv0297_state { | |
32 | struct i2c_adapter *i2c; | |
33 | struct dvb_frontend_ops ops; | |
34 | const struct stv0297_config *config; | |
35 | struct dvb_frontend frontend; | |
36 | ||
37 | unsigned long base_freq; | |
38 | u8 pwm; | |
39 | }; | |
40 | ||
41 | #if 1 | |
42 | #define dprintk(x...) printk(x) | |
43 | #else | |
44 | #define dprintk(x...) | |
45 | #endif | |
46 | ||
47 | #define STV0297_CLOCK_KHZ 28900 | |
48 | ||
49 | static u8 init_tab[] = { | |
50 | 0x00, 0x09, | |
51 | 0x01, 0x69, | |
52 | 0x03, 0x00, | |
53 | 0x04, 0x00, | |
54 | 0x07, 0x00, | |
55 | 0x08, 0x00, | |
56 | 0x20, 0x00, | |
57 | 0x21, 0x40, | |
58 | 0x22, 0x00, | |
59 | 0x23, 0x00, | |
60 | 0x24, 0x40, | |
61 | 0x25, 0x88, | |
62 | 0x30, 0xff, | |
63 | 0x31, 0x00, | |
64 | 0x32, 0xff, | |
65 | 0x33, 0x00, | |
66 | 0x34, 0x50, | |
67 | 0x35, 0x7f, | |
68 | 0x36, 0x00, | |
69 | 0x37, 0x20, | |
70 | 0x38, 0x00, | |
71 | 0x40, 0x1c, | |
72 | 0x41, 0xff, | |
73 | 0x42, 0x29, | |
74 | 0x43, 0x00, | |
75 | 0x44, 0xff, | |
76 | 0x45, 0x00, | |
77 | 0x46, 0x00, | |
78 | 0x49, 0x04, | |
79 | 0x4a, 0xff, | |
80 | 0x4b, 0x7f, | |
81 | 0x52, 0x30, | |
82 | 0x55, 0xae, | |
83 | 0x56, 0x47, | |
84 | 0x57, 0xe1, | |
85 | 0x58, 0x3a, | |
86 | 0x5a, 0x1e, | |
87 | 0x5b, 0x34, | |
88 | 0x60, 0x00, | |
89 | 0x63, 0x00, | |
90 | 0x64, 0x00, | |
91 | 0x65, 0x00, | |
92 | 0x66, 0x00, | |
93 | 0x67, 0x00, | |
94 | 0x68, 0x00, | |
95 | 0x69, 0x00, | |
96 | 0x6a, 0x02, | |
97 | 0x6b, 0x00, | |
98 | 0x70, 0xff, | |
99 | 0x71, 0x00, | |
100 | 0x72, 0x00, | |
101 | 0x73, 0x00, | |
102 | 0x74, 0x0c, | |
103 | 0x80, 0x00, | |
104 | 0x81, 0x00, | |
105 | 0x82, 0x00, | |
106 | 0x83, 0x00, | |
107 | 0x84, 0x04, | |
108 | 0x85, 0x80, | |
109 | 0x86, 0x24, | |
110 | 0x87, 0x78, | |
111 | 0x88, 0x00, | |
112 | 0x89, 0x00, | |
113 | 0x90, 0x01, | |
114 | 0x91, 0x01, | |
115 | 0xa0, 0x00, | |
116 | 0xa1, 0x00, | |
117 | 0xa2, 0x00, | |
118 | 0xb0, 0x91, | |
119 | 0xb1, 0x0b, | |
120 | 0xc0, 0x53, | |
121 | 0xc1, 0x70, | |
122 | 0xc2, 0x12, | |
123 | 0xd0, 0x00, | |
124 | 0xd1, 0x00, | |
125 | 0xd2, 0x00, | |
126 | 0xd3, 0x00, | |
127 | 0xd4, 0x00, | |
128 | 0xd5, 0x00, | |
129 | 0xde, 0x00, | |
130 | 0xdf, 0x00, | |
131 | 0x61, 0x49, | |
132 | 0x62, 0x0b, | |
133 | 0x53, 0x08, | |
134 | 0x59, 0x08, | |
135 | }; | |
136 | ||
137 | ||
138 | static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data) | |
139 | { | |
140 | int ret; | |
141 | u8 buf[] = { reg, data }; | |
142 | struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 }; | |
143 | ||
144 | ret = i2c_transfer(state->i2c, &msg, 1); | |
145 | ||
146 | if (ret != 1) | |
147 | dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, " | |
148 | "ret == %i)\n", __FUNCTION__, reg, data, ret); | |
149 | ||
150 | return (ret != 1) ? -1 : 0; | |
151 | } | |
152 | ||
153 | static int stv0297_readreg(struct stv0297_state *state, u8 reg) | |
154 | { | |
155 | int ret; | |
156 | u8 b0[] = { reg }; | |
157 | u8 b1[] = { 0 }; | |
158 | struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = | |
159 | 1}, | |
160 | {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1} | |
161 | }; | |
162 | ||
163 | // this device needs a STOP between the register and data | |
164 | if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) { | |
165 | dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret); | |
166 | return -1; | |
167 | } | |
168 | if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) { | |
169 | dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret); | |
170 | return -1; | |
171 | } | |
172 | ||
173 | return b1[0]; | |
174 | } | |
175 | ||
176 | static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data) | |
177 | { | |
178 | int val; | |
179 | ||
180 | val = stv0297_readreg(state, reg); | |
181 | val &= ~mask; | |
182 | val |= (data & mask); | |
183 | stv0297_writereg(state, reg, val); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) | |
189 | { | |
190 | int ret; | |
191 | struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = | |
192 | ®1,.len = 1}, | |
193 | {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len} | |
194 | }; | |
195 | ||
196 | // this device needs a STOP between the register and data | |
197 | if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) { | |
198 | dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret); | |
199 | return -1; | |
200 | } | |
201 | if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) { | |
202 | dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret); | |
203 | return -1; | |
204 | } | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | static u32 stv0297_get_symbolrate(struct stv0297_state *state) | |
210 | { | |
211 | u64 tmp; | |
212 | ||
213 | tmp = stv0297_readreg(state, 0x55); | |
214 | tmp |= stv0297_readreg(state, 0x56) << 8; | |
215 | tmp |= stv0297_readreg(state, 0x57) << 16; | |
216 | tmp |= stv0297_readreg(state, 0x58) << 24; | |
217 | ||
218 | tmp *= STV0297_CLOCK_KHZ; | |
219 | tmp >>= 32; | |
220 | ||
221 | return (u32) tmp; | |
222 | } | |
223 | ||
224 | static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate) | |
225 | { | |
226 | long tmp; | |
227 | ||
228 | tmp = 131072L * srate; /* 131072 = 2^17 */ | |
229 | tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */ | |
230 | tmp = tmp * 8192L; /* 8192 = 2^13 */ | |
231 | ||
232 | stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF)); | |
233 | stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8)); | |
234 | stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16)); | |
235 | stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24)); | |
236 | } | |
237 | ||
238 | static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate) | |
239 | { | |
240 | long tmp; | |
241 | ||
242 | tmp = (long) fshift *262144L; /* 262144 = 2*18 */ | |
243 | tmp /= symrate; | |
244 | tmp *= 1024; /* 1024 = 2*10 */ | |
245 | ||
246 | // adjust | |
247 | if (tmp >= 0) { | |
248 | tmp += 500000; | |
249 | } else { | |
250 | tmp -= 500000; | |
251 | } | |
252 | tmp /= 1000000; | |
253 | ||
254 | stv0297_writereg(state, 0x60, tmp & 0xFF); | |
255 | stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0); | |
256 | } | |
257 | ||
258 | static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset) | |
259 | { | |
260 | long tmp; | |
261 | ||
262 | /* symrate is hardcoded to 10000 */ | |
263 | tmp = offset * 26844L; /* (2**28)/10000 */ | |
264 | if (tmp < 0) | |
265 | tmp += 0x10000000; | |
266 | tmp &= 0x0FFFFFFF; | |
267 | ||
268 | stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF)); | |
269 | stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8)); | |
270 | stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16)); | |
271 | stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f); | |
272 | } | |
273 | ||
274 | /* | |
275 | static long stv0297_get_carrieroffset(struct stv0297_state *state) | |
276 | { | |
277 | s64 tmp; | |
278 | ||
279 | stv0297_writereg(state, 0x6B, 0x00); | |
280 | ||
281 | tmp = stv0297_readreg(state, 0x66); | |
282 | tmp |= (stv0297_readreg(state, 0x67) << 8); | |
283 | tmp |= (stv0297_readreg(state, 0x68) << 16); | |
284 | tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24; | |
285 | ||
286 | tmp *= stv0297_get_symbolrate(state); | |
287 | tmp >>= 28; | |
288 | ||
289 | return (s32) tmp; | |
290 | } | |
291 | */ | |
292 | ||
293 | static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq) | |
294 | { | |
295 | s32 tmp; | |
296 | ||
297 | if (freq > 10000) | |
298 | freq -= STV0297_CLOCK_KHZ; | |
299 | ||
300 | tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16); | |
301 | tmp = (freq * 1000) / tmp; | |
302 | if (tmp > 0xffff) | |
303 | tmp = 0xffff; | |
304 | ||
305 | stv0297_writereg_mask(state, 0x25, 0x80, 0x80); | |
306 | stv0297_writereg(state, 0x21, tmp >> 8); | |
307 | stv0297_writereg(state, 0x20, tmp); | |
308 | } | |
309 | ||
310 | static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation) | |
311 | { | |
312 | int val = 0; | |
313 | ||
314 | switch (modulation) { | |
315 | case QAM_16: | |
316 | val = 0; | |
317 | break; | |
318 | ||
319 | case QAM_32: | |
320 | val = 1; | |
321 | break; | |
322 | ||
323 | case QAM_64: | |
324 | val = 4; | |
325 | break; | |
326 | ||
327 | case QAM_128: | |
328 | val = 2; | |
329 | break; | |
330 | ||
331 | case QAM_256: | |
332 | val = 3; | |
333 | break; | |
334 | ||
335 | default: | |
336 | return -EINVAL; | |
337 | } | |
338 | ||
339 | stv0297_writereg_mask(state, 0x00, 0x70, val << 4); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion) | |
345 | { | |
346 | int val = 0; | |
347 | ||
348 | switch (inversion) { | |
349 | case INVERSION_OFF: | |
350 | val = 0; | |
351 | break; | |
352 | ||
353 | case INVERSION_ON: | |
354 | val = 1; | |
355 | break; | |
356 | ||
357 | default: | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | stv0297_writereg_mask(state, 0x83, 0x08, val << 3); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | int stv0297_enable_plli2c(struct dvb_frontend *fe) | |
367 | { | |
368 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
369 | ||
370 | stv0297_writereg(state, 0x87, 0x78); | |
371 | stv0297_writereg(state, 0x86, 0xc8); | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | static int stv0297_init(struct dvb_frontend *fe) | |
377 | { | |
378 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
379 | int i; | |
380 | ||
381 | /* soft reset */ | |
382 | stv0297_writereg_mask(state, 0x80, 1, 1); | |
383 | stv0297_writereg_mask(state, 0x80, 1, 0); | |
384 | ||
385 | /* reset deinterleaver */ | |
386 | stv0297_writereg_mask(state, 0x81, 1, 1); | |
387 | stv0297_writereg_mask(state, 0x81, 1, 0); | |
388 | ||
389 | /* load init table */ | |
390 | for (i = 0; i < sizeof(init_tab); i += 2) { | |
391 | stv0297_writereg(state, init_tab[i], init_tab[i + 1]); | |
392 | } | |
393 | ||
394 | /* set a dummy symbol rate */ | |
395 | stv0297_set_symbolrate(state, 6900); | |
396 | ||
397 | /* invert AGC1 polarity */ | |
398 | stv0297_writereg_mask(state, 0x88, 0x10, 0x10); | |
399 | ||
400 | /* setup bit error counting */ | |
401 | stv0297_writereg_mask(state, 0xA0, 0x80, 0x00); | |
402 | stv0297_writereg_mask(state, 0xA0, 0x10, 0x00); | |
403 | stv0297_writereg_mask(state, 0xA0, 0x08, 0x00); | |
404 | stv0297_writereg_mask(state, 0xA0, 0x07, 0x04); | |
405 | ||
406 | /* min + max PWM */ | |
407 | stv0297_writereg(state, 0x4a, 0x00); | |
408 | stv0297_writereg(state, 0x4b, state->pwm); | |
409 | msleep(200); | |
410 | ||
411 | if (state->config->pll_init) | |
412 | state->config->pll_init(fe); | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int stv0297_sleep(struct dvb_frontend *fe) | |
418 | { | |
419 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
420 | ||
421 | stv0297_writereg_mask(state, 0x80, 1, 1); | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status) | |
427 | { | |
428 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
429 | ||
430 | u8 sync = stv0297_readreg(state, 0xDF); | |
431 | ||
432 | *status = 0; | |
433 | if (sync & 0x80) | |
434 | *status |= | |
435 | FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK; | |
436 | return 0; | |
437 | } | |
438 | ||
439 | static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber) | |
440 | { | |
441 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
442 | u8 BER[3]; | |
443 | ||
444 | stv0297_writereg(state, 0xA0, 0x80); // Start Counting bit errors for 4096 Bytes | |
445 | mdelay(25); // Hopefully got 4096 Bytes | |
446 | stv0297_readregs(state, 0xA0, BER, 3); | |
447 | mdelay(25); | |
448 | *ber = (BER[2] << 8 | BER[1]) / (8 * 4096); | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | ||
454 | static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength) | |
455 | { | |
456 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
457 | u8 STRENGTH[2]; | |
458 | ||
459 | stv0297_readregs(state, 0x41, STRENGTH, 2); | |
460 | *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0]; | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr) | |
466 | { | |
467 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
468 | u8 SNR[2]; | |
469 | ||
470 | stv0297_readregs(state, 0x07, SNR, 2); | |
471 | *snr = SNR[1] << 8 | SNR[0]; | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) | |
477 | { | |
478 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
479 | ||
480 | *ucblocks = (stv0297_readreg(state, 0xD5) << 8) | |
481 | | stv0297_readreg(state, 0xD4); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) | |
487 | { | |
488 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
489 | int u_threshold; | |
490 | int initial_u; | |
491 | int blind_u; | |
492 | int delay; | |
493 | int sweeprate; | |
494 | int carrieroffset; | |
495 | unsigned long starttime; | |
496 | unsigned long timeout; | |
497 | fe_spectral_inversion_t inversion; | |
498 | ||
499 | switch (p->u.qam.modulation) { | |
500 | case QAM_16: | |
501 | case QAM_32: | |
502 | case QAM_64: | |
503 | delay = 100; | |
504 | sweeprate = 1500; | |
505 | break; | |
506 | ||
507 | case QAM_128: | |
508 | delay = 150; | |
509 | sweeprate = 1000; | |
510 | break; | |
511 | ||
512 | case QAM_256: | |
513 | delay = 200; | |
514 | sweeprate = 500; | |
515 | break; | |
516 | ||
517 | default: | |
518 | return -EINVAL; | |
519 | } | |
520 | ||
521 | // determine inversion dependant parameters | |
522 | inversion = p->inversion; | |
523 | if (state->config->invert) | |
524 | inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON; | |
525 | carrieroffset = -330; | |
526 | switch (inversion) { | |
527 | case INVERSION_OFF: | |
528 | break; | |
529 | ||
530 | case INVERSION_ON: | |
531 | sweeprate = -sweeprate; | |
532 | carrieroffset = -carrieroffset; | |
533 | break; | |
534 | ||
535 | default: | |
536 | return -EINVAL; | |
537 | } | |
538 | ||
539 | stv0297_init(fe); | |
540 | state->config->pll_set(fe, p); | |
541 | ||
542 | /* clear software interrupts */ | |
543 | stv0297_writereg(state, 0x82, 0x0); | |
544 | ||
545 | /* set initial demodulation frequency */ | |
546 | stv0297_set_initialdemodfreq(state, 7250); | |
547 | ||
548 | /* setup AGC */ | |
549 | stv0297_writereg_mask(state, 0x43, 0x10, 0x00); | |
550 | stv0297_writereg(state, 0x41, 0x00); | |
551 | stv0297_writereg_mask(state, 0x42, 0x03, 0x01); | |
552 | stv0297_writereg_mask(state, 0x36, 0x60, 0x00); | |
553 | stv0297_writereg_mask(state, 0x36, 0x18, 0x00); | |
554 | stv0297_writereg_mask(state, 0x71, 0x80, 0x80); | |
555 | stv0297_writereg(state, 0x72, 0x00); | |
556 | stv0297_writereg(state, 0x73, 0x00); | |
557 | stv0297_writereg_mask(state, 0x74, 0x0F, 0x00); | |
558 | stv0297_writereg_mask(state, 0x43, 0x08, 0x00); | |
559 | stv0297_writereg_mask(state, 0x71, 0x80, 0x00); | |
560 | ||
561 | /* setup STL */ | |
562 | stv0297_writereg_mask(state, 0x5a, 0x20, 0x20); | |
563 | stv0297_writereg_mask(state, 0x5b, 0x02, 0x02); | |
564 | stv0297_writereg_mask(state, 0x5b, 0x02, 0x00); | |
565 | stv0297_writereg_mask(state, 0x5b, 0x01, 0x00); | |
566 | stv0297_writereg_mask(state, 0x5a, 0x40, 0x40); | |
567 | ||
568 | /* disable frequency sweep */ | |
569 | stv0297_writereg_mask(state, 0x6a, 0x01, 0x00); | |
570 | ||
571 | /* reset deinterleaver */ | |
572 | stv0297_writereg_mask(state, 0x81, 0x01, 0x01); | |
573 | stv0297_writereg_mask(state, 0x81, 0x01, 0x00); | |
574 | ||
575 | /* ??? */ | |
576 | stv0297_writereg_mask(state, 0x83, 0x20, 0x20); | |
577 | stv0297_writereg_mask(state, 0x83, 0x20, 0x00); | |
578 | ||
579 | /* reset equaliser */ | |
580 | u_threshold = stv0297_readreg(state, 0x00) & 0xf; | |
581 | initial_u = stv0297_readreg(state, 0x01) >> 4; | |
582 | blind_u = stv0297_readreg(state, 0x01) & 0xf; | |
583 | stv0297_writereg_mask(state, 0x84, 0x01, 0x01); | |
584 | stv0297_writereg_mask(state, 0x84, 0x01, 0x00); | |
585 | stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold); | |
586 | stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4); | |
587 | stv0297_writereg_mask(state, 0x01, 0x0f, blind_u); | |
588 | ||
589 | /* data comes from internal A/D */ | |
590 | stv0297_writereg_mask(state, 0x87, 0x80, 0x00); | |
591 | ||
592 | /* clear phase registers */ | |
593 | stv0297_writereg(state, 0x63, 0x00); | |
594 | stv0297_writereg(state, 0x64, 0x00); | |
595 | stv0297_writereg(state, 0x65, 0x00); | |
596 | stv0297_writereg(state, 0x66, 0x00); | |
597 | stv0297_writereg(state, 0x67, 0x00); | |
598 | stv0297_writereg(state, 0x68, 0x00); | |
599 | stv0297_writereg_mask(state, 0x69, 0x0f, 0x00); | |
600 | ||
601 | /* set parameters */ | |
602 | stv0297_set_qam(state, p->u.qam.modulation); | |
603 | stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000); | |
604 | stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000); | |
605 | stv0297_set_carrieroffset(state, carrieroffset); | |
606 | stv0297_set_inversion(state, inversion); | |
607 | ||
608 | /* kick off lock */ | |
609 | stv0297_writereg_mask(state, 0x88, 0x08, 0x08); | |
610 | stv0297_writereg_mask(state, 0x5a, 0x20, 0x00); | |
611 | stv0297_writereg_mask(state, 0x6a, 0x01, 0x01); | |
612 | stv0297_writereg_mask(state, 0x43, 0x40, 0x40); | |
613 | stv0297_writereg_mask(state, 0x5b, 0x30, 0x00); | |
614 | stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c); | |
615 | stv0297_writereg_mask(state, 0x03, 0x03, 0x03); | |
616 | stv0297_writereg_mask(state, 0x43, 0x10, 0x10); | |
617 | ||
618 | /* wait for WGAGC lock */ | |
619 | starttime = jiffies; | |
620 | timeout = jiffies + (200 * HZ) / 1000; | |
621 | while (time_before(jiffies, timeout)) { | |
622 | msleep(10); | |
623 | if (stv0297_readreg(state, 0x43) & 0x08) | |
624 | break; | |
625 | } | |
626 | if (time_after(jiffies, timeout)) { | |
627 | goto timeout; | |
628 | } | |
629 | msleep(20); | |
630 | ||
631 | /* wait for equaliser partial convergence */ | |
632 | timeout = jiffies + (50 * HZ) / 1000; | |
633 | while (time_before(jiffies, timeout)) { | |
634 | msleep(10); | |
635 | ||
636 | if (stv0297_readreg(state, 0x82) & 0x04) { | |
637 | break; | |
638 | } | |
639 | } | |
640 | if (time_after(jiffies, timeout)) { | |
641 | goto timeout; | |
642 | } | |
643 | ||
644 | /* wait for equaliser full convergence */ | |
645 | timeout = jiffies + (delay * HZ) / 1000; | |
646 | while (time_before(jiffies, timeout)) { | |
647 | msleep(10); | |
648 | ||
649 | if (stv0297_readreg(state, 0x82) & 0x08) { | |
650 | break; | |
651 | } | |
652 | } | |
653 | if (time_after(jiffies, timeout)) { | |
654 | goto timeout; | |
655 | } | |
656 | ||
657 | /* disable sweep */ | |
658 | stv0297_writereg_mask(state, 0x6a, 1, 0); | |
659 | stv0297_writereg_mask(state, 0x88, 8, 0); | |
660 | ||
661 | /* wait for main lock */ | |
662 | timeout = jiffies + (20 * HZ) / 1000; | |
663 | while (time_before(jiffies, timeout)) { | |
664 | msleep(10); | |
665 | ||
666 | if (stv0297_readreg(state, 0xDF) & 0x80) { | |
667 | break; | |
668 | } | |
669 | } | |
670 | if (time_after(jiffies, timeout)) { | |
671 | goto timeout; | |
672 | } | |
673 | msleep(100); | |
674 | ||
675 | /* is it still locked after that delay? */ | |
676 | if (!(stv0297_readreg(state, 0xDF) & 0x80)) { | |
677 | goto timeout; | |
678 | } | |
679 | ||
680 | /* success!! */ | |
681 | stv0297_writereg_mask(state, 0x5a, 0x40, 0x00); | |
682 | state->base_freq = p->frequency; | |
683 | return 0; | |
684 | ||
685 | timeout: | |
686 | stv0297_writereg_mask(state, 0x6a, 0x01, 0x00); | |
687 | return 0; | |
688 | } | |
689 | ||
690 | static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) | |
691 | { | |
692 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
693 | int reg_00, reg_83; | |
694 | ||
695 | reg_00 = stv0297_readreg(state, 0x00); | |
696 | reg_83 = stv0297_readreg(state, 0x83); | |
697 | ||
698 | p->frequency = state->base_freq; | |
699 | p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF; | |
700 | if (state->config->invert) | |
701 | p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON; | |
702 | p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000; | |
703 | p->u.qam.fec_inner = FEC_NONE; | |
704 | ||
705 | switch ((reg_00 >> 4) & 0x7) { | |
706 | case 0: | |
707 | p->u.qam.modulation = QAM_16; | |
708 | break; | |
709 | case 1: | |
710 | p->u.qam.modulation = QAM_32; | |
711 | break; | |
712 | case 2: | |
713 | p->u.qam.modulation = QAM_128; | |
714 | break; | |
715 | case 3: | |
716 | p->u.qam.modulation = QAM_256; | |
717 | break; | |
718 | case 4: | |
719 | p->u.qam.modulation = QAM_64; | |
720 | break; | |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
726 | static void stv0297_release(struct dvb_frontend *fe) | |
727 | { | |
728 | struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; | |
729 | kfree(state); | |
730 | } | |
731 | ||
732 | static struct dvb_frontend_ops stv0297_ops; | |
733 | ||
734 | struct dvb_frontend *stv0297_attach(const struct stv0297_config *config, | |
735 | struct i2c_adapter *i2c, int pwm) | |
736 | { | |
737 | struct stv0297_state *state = NULL; | |
738 | ||
739 | /* allocate memory for the internal state */ | |
740 | state = (struct stv0297_state *) kmalloc(sizeof(struct stv0297_state), GFP_KERNEL); | |
741 | if (state == NULL) | |
742 | goto error; | |
743 | ||
744 | /* setup the state */ | |
745 | state->config = config; | |
746 | state->i2c = i2c; | |
747 | memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops)); | |
748 | state->base_freq = 0; | |
749 | state->pwm = pwm; | |
750 | ||
751 | /* check if the demod is there */ | |
752 | if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20) | |
753 | goto error; | |
754 | ||
755 | /* create dvb_frontend */ | |
756 | state->frontend.ops = &state->ops; | |
757 | state->frontend.demodulator_priv = state; | |
758 | return &state->frontend; | |
759 | ||
760 | error: | |
761 | kfree(state); | |
762 | return NULL; | |
763 | } | |
764 | ||
765 | static struct dvb_frontend_ops stv0297_ops = { | |
766 | ||
767 | .info = { | |
768 | .name = "ST STV0297 DVB-C", | |
769 | .type = FE_QAM, | |
770 | .frequency_min = 64000000, | |
771 | .frequency_max = 1300000000, | |
772 | .frequency_stepsize = 62500, | |
773 | .symbol_rate_min = 870000, | |
774 | .symbol_rate_max = 11700000, | |
775 | .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | | |
776 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO}, | |
777 | ||
778 | .release = stv0297_release, | |
779 | ||
780 | .init = stv0297_init, | |
781 | .sleep = stv0297_sleep, | |
782 | ||
783 | .set_frontend = stv0297_set_frontend, | |
784 | .get_frontend = stv0297_get_frontend, | |
785 | ||
786 | .read_status = stv0297_read_status, | |
787 | .read_ber = stv0297_read_ber, | |
788 | .read_signal_strength = stv0297_read_signal_strength, | |
789 | .read_snr = stv0297_read_snr, | |
790 | .read_ucblocks = stv0297_read_ucblocks, | |
791 | }; | |
792 | ||
793 | MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver"); | |
794 | MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey"); | |
795 | MODULE_LICENSE("GPL"); | |
796 | ||
797 | EXPORT_SYMBOL(stv0297_attach); | |
798 | EXPORT_SYMBOL(stv0297_enable_plli2c); |