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[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb / frontends / stv0900_sw.c
CommitLineData
ce45264e
IL		 1/*
2 * stv0900_sw.c
3 *
4 * Driver for ST STV0900 satellite demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include "stv0900.h"
27#include "stv0900_reg.h"
28#include "stv0900_priv.h"
29
a3a4f7e1
IL		 30s32 shiftx(s32 x, int demod, s32 shift)
31{
32 if (demod == 1)
33 return x - shift;
34
35 return x;
36}
37
38int stv0900_check_signal_presence(struct stv0900_internal *intp,
ce45264e
IL		 39 enum fe_stv0900_demod_num demod)
40{
a3a4f7e1
IL		 41 s32 carr_offset,
42 agc2_integr,
43 max_carrier;
ce45264e 44
a3a4f7e1 45 int no_signal = FALSE;
ce45264e 46
a3a4f7e1
IL		 47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
48 | stv0900_read_reg(intp, CFR1);
49 carr_offset = ge2comp(carr_offset, 16);
50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
51 | stv0900_read_reg(intp, AGC2I0);
52 max_carrier = intp->srch_range[demod] / 1000;
ce45264e
IL		 53
54 max_carrier += (max_carrier / 10);
55 max_carrier = 65536 * (max_carrier / 2);
a3a4f7e1 56 max_carrier /= intp->mclk / 1000;
ce45264e
IL		 57 if (max_carrier > 0x4000)
58 max_carrier = 0x4000;
59
60 if ((agc2_integr > 0x2000)
a3a4f7e1
IL		 61 || (carr_offset > (2 * max_carrier))
62 || (carr_offset < (-2 * max_carrier)))
ce45264e 63 no_signal = TRUE;
ce45264e
IL		 64
65 return no_signal;
66}
67
a3a4f7e1 68static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
ce45264e
IL		 69 s32 *frequency_inc, s32 *sw_timeout,
70 s32 *steps,
71 enum fe_stv0900_demod_num demod)
72{
73 s32 timeout, freq_inc, max_steps, srate, max_carrier;
74
75 enum fe_stv0900_search_standard standard;
76
a3a4f7e1
IL		 77 srate = intp->symbol_rate[demod];
78 max_carrier = intp->srch_range[demod] / 1000;
79 max_carrier += max_carrier / 10;
80 standard = intp->srch_standard[demod];
ce45264e
IL		 81
82 max_carrier = 65536 * (max_carrier / 2);
a3a4f7e1 83 max_carrier /= intp->mclk / 1000;
ce45264e
IL		 84
85 if (max_carrier > 0x4000)
86 max_carrier = 0x4000;
87
88 freq_inc = srate;
a3a4f7e1 89 freq_inc /= intp->mclk >> 10;
ce45264e
IL		 90 freq_inc = freq_inc << 6;
91
92 switch (standard) {
93 case STV0900_SEARCH_DVBS1:
94 case STV0900_SEARCH_DSS:
95 freq_inc *= 3;
96 timeout = 20;
97 break;
98 case STV0900_SEARCH_DVBS2:
99 freq_inc *= 4;
100 timeout = 25;
101 break;
102 case STV0900_AUTO_SEARCH:
103 default:
104 freq_inc *= 3;
105 timeout = 25;
106 break;
107 }
108
109 freq_inc /= 100;
110
111 if ((freq_inc > max_carrier) || (freq_inc < 0))
112 freq_inc = max_carrier / 2;
113
114 timeout *= 27500;
115
116 if (srate > 0)
117 timeout /= srate / 1000;
118
119 if ((timeout > 100) || (timeout < 0))
120 timeout = 100;
121
122 max_steps = (max_carrier / freq_inc) + 1;
123
124 if ((max_steps > 100) || (max_steps < 0)) {
125 max_steps = 100;
126 freq_inc = max_carrier / max_steps;
127 }
128
129 *frequency_inc = freq_inc;
130 *sw_timeout = timeout;
131 *steps = max_steps;
132
133}
134
a3a4f7e1 135static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
ce45264e
IL		 136 s32 FreqIncr, s32 Timeout, int zigzag,
137 s32 MaxStep, enum fe_stv0900_demod_num demod)
138{
139 int no_signal,
140 lock = FALSE;
141 s32 stepCpt,
142 freqOffset,
143 max_carrier;
144
a3a4f7e1
IL		 145 max_carrier = intp->srch_range[demod] / 1000;
146 max_carrier += (max_carrier / 10);
ce45264e
IL		 147
148 max_carrier = 65536 * (max_carrier / 2);
a3a4f7e1 149 max_carrier /= intp->mclk / 1000;
ce45264e
IL		 150
151 if (max_carrier > 0x4000)
152 max_carrier = 0x4000;
153
154 if (zigzag == TRUE)
155 freqOffset = 0;
156 else
157 freqOffset = -max_carrier + FreqIncr;
158
159 stepCpt = 0;
160
161 do {
a3a4f7e1
IL		 162 stv0900_write_reg(intp, DMDISTATE, 0x1c);
163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
165 stv0900_write_reg(intp, DMDISTATE, 0x18);
166 stv0900_write_bits(intp, ALGOSWRST, 1);
167
168 if (intp->chip_id == 0x12) {
169 stv0900_write_bits(intp, RST_HWARE, 1);
170 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e
IL		 171 }
172
173 if (zigzag == TRUE) {
174 if (freqOffset >= 0)
175 freqOffset = -freqOffset - 2 * FreqIncr;
176 else
177 freqOffset = -freqOffset;
178 } else
179 freqOffset += + 2 * FreqIncr;
180
181 stepCpt++;
a3a4f7e1
IL		 182 lock = stv0900_get_demod_lock(intp, demod, Timeout);
183 no_signal = stv0900_check_signal_presence(intp, demod);
ce45264e
IL		 184
185 } while ((lock == FALSE)
186 && (no_signal == FALSE)
187 && ((freqOffset - FreqIncr) < max_carrier)
188 && ((freqOffset + FreqIncr) > -max_carrier)
189 && (stepCpt < MaxStep));
190
a3a4f7e1 191 stv0900_write_bits(intp, ALGOSWRST, 0);
ce45264e
IL		 192
193 return lock;
194}
195
a3a4f7e1 196int stv0900_sw_algo(struct stv0900_internal *intp,
ce45264e
IL		 197 enum fe_stv0900_demod_num demod)
198{
a3a4f7e1
IL		 199 int lock = FALSE,
200 no_signal,
201 zigzag;
202 s32 s2fw,
203 fqc_inc,
204 sft_stp_tout,
205 trial_cntr,
206 max_steps;
207
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
ce45264e 209 &max_steps, demod);
a3a4f7e1
IL		 210 switch (intp->srch_standard[demod]) {
211 case STV0900_SEARCH_DVBS1:
212 case STV0900_SEARCH_DSS:
213 if (intp->chip_id >= 0x20)
214 stv0900_write_reg(intp, CARFREQ, 0x3b);
215 else
216 stv0900_write_reg(intp, CARFREQ, 0xef);
ce45264e 217
a3a4f7e1
IL		 218 stv0900_write_reg(intp, DMDCFGMD, 0x49);
219 zigzag = FALSE;
220 break;
221 case STV0900_SEARCH_DVBS2:
222 if (intp->chip_id >= 0x20)
223 stv0900_write_reg(intp, CORRELABS, 0x79);
224 else
225 stv0900_write_reg(intp, CORRELABS, 0x68);
ce45264e 226
a3a4f7e1 227 stv0900_write_reg(intp, DMDCFGMD, 0x89);
ce45264e 228
a3a4f7e1
IL		 229 zigzag = TRUE;
230 break;
231 case STV0900_AUTO_SEARCH:
232 default:
233 if (intp->chip_id >= 0x20) {
234 stv0900_write_reg(intp, CARFREQ, 0x3b);
235 stv0900_write_reg(intp, CORRELABS, 0x79);
236 } else {
237 stv0900_write_reg(intp, CARFREQ, 0xef);
238 stv0900_write_reg(intp, CORRELABS, 0x68);
ce45264e
IL		 239 }
240
a3a4f7e1
IL		 241 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
242 zigzag = FALSE;
ce45264e 243 break;
a3a4f7e1 244 }
ce45264e 245
a3a4f7e1
IL		 246 trial_cntr = 0;
247 do {
248 lock = stv0900_search_carr_sw_loop(intp,
249 fqc_inc,
250 sft_stp_tout,
251 zigzag,
252 max_steps,
253 demod);
254 no_signal = stv0900_check_signal_presence(intp, demod);
255 trial_cntr++;
256 if ((lock == TRUE)
257 || (no_signal == TRUE)
258 || (trial_cntr == 2)) {
259
260 if (intp->chip_id >= 0x20) {
261 stv0900_write_reg(intp, CARFREQ, 0x49);
262 stv0900_write_reg(intp, CORRELABS, 0x9e);
ce45264e 263 } else {
a3a4f7e1
IL		 264 stv0900_write_reg(intp, CARFREQ, 0xed);
265 stv0900_write_reg(intp, CORRELABS, 0x88);
ce45264e
IL		 266 }
267
a3a4f7e1
IL		 268 if ((stv0900_get_bits(intp, HEADER_MODE) ==
269 STV0900_DVBS2_FOUND) &&
270 (lock == TRUE)) {
271 msleep(sft_stp_tout);
272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
ce45264e 273
a3a4f7e1
IL		 274 if (s2fw < 0xd) {
275 msleep(sft_stp_tout);
276 s2fw = stv0900_get_bits(intp,
277 FLYWHEEL_CPT);
ce45264e
IL		 278 }
279
a3a4f7e1
IL		 280 if (s2fw < 0xd) {
281 lock = FALSE;
ce45264e 282
a3a4f7e1
IL		 283 if (trial_cntr < 2) {
284 if (intp->chip_id >= 0x20)
285 stv0900_write_reg(intp,
286 CORRELABS,
287 0x79);
288 else
289 stv0900_write_reg(intp,
290 CORRELABS,
291 0x68);
ce45264e 292
a3a4f7e1
IL		 293 stv0900_write_reg(intp,
294 DMDCFGMD,
295 0x89);
ce45264e
IL		 296 }
297 }
298 }
a3a4f7e1 299 }
ce45264e 300
a3a4f7e1
IL		 301 } while ((lock == FALSE)
302 && (trial_cntr < 2)
303 && (no_signal == FALSE));
ce45264e
IL		 304
305 return lock;
306}
307
a3a4f7e1 308static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
ce45264e
IL		 309 u32 mclk,
310 enum fe_stv0900_demod_num demod)
311{
a3a4f7e1
IL		 312 s32 rem1, rem2, intval1, intval2, srate;
313
314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
317 (stv0900_get_bits(intp, SYMB_FREQ0));
ce45264e 318 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
a3a4f7e1
IL		 319 srate, stv0900_get_bits(intp, SYMB_FREQ0),
320 stv0900_get_bits(intp, SYMB_FREQ1),
321 stv0900_get_bits(intp, SYMB_FREQ2),
322 stv0900_get_bits(intp, SYMB_FREQ3));
ce45264e
IL		 323
324 intval1 = (mclk) >> 16;
325 intval2 = (srate) >> 16;
326
327 rem1 = (mclk) % 0x10000;
328 rem2 = (srate) % 0x10000;
329 srate = (intval1 * intval2) +
330 ((intval1 * rem2) >> 16) +
331 ((intval2 * rem1) >> 16);
332
333 return srate;
334}
335
a3a4f7e1 336static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
ce45264e
IL		 337 u32 mclk, u32 srate,
338 enum fe_stv0900_demod_num demod)
339{
ce45264e
IL		 340 u32 symb;
341
8171c205 342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
ce45264e
IL		 343 srate, demod);
344
ce45264e
IL		 345 if (srate > 60000000) {
346 symb = srate << 4;
347 symb /= (mclk >> 12);
348 } else if (srate > 6000000) {
349 symb = srate << 6;
350 symb /= (mclk >> 10);
351 } else {
352 symb = srate << 9;
353 symb /= (mclk >> 7);
354 }
355
a3a4f7e1
IL		 356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
ce45264e
IL		 358}
359
a3a4f7e1 360static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
ce45264e
IL		 361 u32 mclk, u32 srate,
362 enum fe_stv0900_demod_num demod)
363{
ce45264e
IL		 364 u32 symb;
365
ce45264e
IL		 366 srate = 105 * (srate / 100);
367
368 if (srate > 60000000) {
369 symb = srate << 4;
370 symb /= (mclk >> 12);
371 } else if (srate > 6000000) {
372 symb = srate << 6;
373 symb /= (mclk >> 10);
374 } else {
375 symb = srate << 9;
376 symb /= (mclk >> 7);
377 }
378
379 if (symb < 0x7fff) {
a3a4f7e1
IL		 380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
ce45264e 382 } else {
a3a4f7e1
IL		 383 stv0900_write_reg(intp, SFRUP1, 0x7f);
384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
ce45264e
IL		 385 }
386}
387
a3a4f7e1 388static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
ce45264e
IL		 389 u32 mclk, u32 srate,
390 enum fe_stv0900_demod_num demod)
391{
ce45264e
IL		 392 u32 symb;
393
ce45264e
IL		 394 srate = 95 * (srate / 100);
395 if (srate > 60000000) {
396 symb = srate << 4;
397 symb /= (mclk >> 12);
398
399 } else if (srate > 6000000) {
400 symb = srate << 6;
401 symb /= (mclk >> 10);
402
403 } else {
404 symb = srate << 9;
405 symb /= (mclk >> 7);
406 }
407
a3a4f7e1
IL		 408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
ce45264e
IL		 410}
411
a3a4f7e1 412static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
ce45264e
IL		 413 u32 srate,
414 enum fe_stv0900_demod_num demod)
415{
a3a4f7e1 416 s32 timingoffset;
ce45264e 417
ce45264e 418
a3a4f7e1
IL		 419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
421 (stv0900_read_reg(intp, TMGREG2 + 2));
ce45264e
IL		 422
423 timingoffset = ge2comp(timingoffset, 24);
424
425
426 if (timingoffset == 0)
427 timingoffset = 1;
428
429 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
430 timingoffset /= 320;
431
432 return timingoffset;
433}
434
a3a4f7e1 435static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
ce45264e
IL		 436 enum fe_stv0900_demod_num demod)
437{
a3a4f7e1
IL		 438 s32 rolloff;
439
440 if (intp->chip_id == 0x10) {
441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
444 } else if (intp->chip_id <= 0x20)
445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
446 else /* cut 3.0 */
447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
ce45264e
IL		 448}
449
450static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
451{
452 u32 rolloff;
453
454 switch (ro) {
455 case STV0900_20:
456 rolloff = 20;
457 break;
458 case STV0900_25:
459 rolloff = 25;
460 break;
461 case STV0900_35:
462 default:
463 rolloff = 35;
464 break;
465 }
466
467 return srate + (srate * rolloff) / 100;
468}
469
a3a4f7e1 470static int stv0900_check_timing_lock(struct stv0900_internal *intp,
ce45264e
IL		 471 enum fe_stv0900_demod_num demod)
472{
473 int timingLock = FALSE;
a3a4f7e1
IL		 474 s32 i,
475 timingcpt = 0;
476 u8 car_freq,
477 tmg_th_high,
478 tmg_th_low;
479
480 car_freq = stv0900_read_reg(intp, CARFREQ);
481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
483 stv0900_write_reg(intp, TMGTHRISE, 0x20);
484 stv0900_write_reg(intp, TMGTHFALL, 0x0);
485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
486 stv0900_write_reg(intp, RTC, 0x80);
487 stv0900_write_reg(intp, RTCS2, 0x40);
488 stv0900_write_reg(intp, CARFREQ, 0x0);
489 stv0900_write_reg(intp, CFRINIT1, 0x0);
490 stv0900_write_reg(intp, CFRINIT0, 0x0);
491 stv0900_write_reg(intp, AGC2REF, 0x65);
492 stv0900_write_reg(intp, DMDISTATE, 0x18);
493 msleep(7);
494
495 for (i = 0; i < 10; i++) {
496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
497 timingcpt++;
498
499 msleep(1);
500 }
ce45264e 501
a3a4f7e1
IL		 502 if (timingcpt >= 3)
503 timingLock = TRUE;
ce45264e 504
a3a4f7e1
IL		 505 stv0900_write_reg(intp, AGC2REF, 0x38);
506 stv0900_write_reg(intp, RTC, 0x88);
507 stv0900_write_reg(intp, RTCS2, 0x68);
508 stv0900_write_reg(intp, CARFREQ, car_freq);
509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
ce45264e
IL		 511
512 return timingLock;
513}
514
515static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
516 s32 demod_timeout)
517{
518 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 519 struct stv0900_internal *intp = state->internal;
ce45264e 520 enum fe_stv0900_demod_num demod = state->demod;
a3a4f7e1
IL		 521 int lock = FALSE,
522 d = demod;
523 s32 srate,
524 search_range,
525 locktimeout,
526 currier_step,
527 nb_steps,
528 current_step,
529 direction,
530 tuner_freq,
531 timeout,
532 freq;
ce45264e 533
a3a4f7e1
IL		 534 srate = intp->symbol_rate[d];
535 search_range = intp->srch_range[d];
ce45264e
IL		 536
537 if (srate >= 10000000)
538 locktimeout = demod_timeout / 3;
539 else
540 locktimeout = demod_timeout / 2;
541
a3a4f7e1 542 lock = stv0900_get_demod_lock(intp, d, locktimeout);
ce45264e 543
a3a4f7e1
IL		 544 if (lock != FALSE)
545 return lock;
546
547 if (srate >= 10000000) {
548 if (stv0900_check_timing_lock(intp, d) == TRUE) {
549 stv0900_write_reg(intp, DMDISTATE, 0x1f);
550 stv0900_write_reg(intp, DMDISTATE, 0x15);
551 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
552 } else
553 lock = FALSE;
554
555 return lock;
556 }
557
558 if (intp->chip_id <= 0x20) {
559 if (srate <= 1000000)
560 currier_step = 500;
561 else if (srate <= 4000000)
562 currier_step = 1000;
563 else if (srate <= 7000000)
564 currier_step = 2000;
565 else if (srate <= 10000000)
566 currier_step = 3000;
567 else
568 currier_step = 5000;
569
570 if (srate >= 2000000) {
ce45264e
IL		 571 timeout = (demod_timeout / 3);
572 if (timeout > 1000)
573 timeout = 1000;
a3a4f7e1
IL		 574 } else
575 timeout = (demod_timeout / 2);
576 } else {
577 /*cut 3.0 */
578 currier_step = srate / 4000;
579 timeout = (demod_timeout * 3) / 4;
580 }
ce45264e 581
a3a4f7e1 582 nb_steps = ((search_range / 1000) / currier_step);
ce45264e 583
a3a4f7e1
IL		 584 if ((nb_steps % 2) != 0)
585 nb_steps += 1;
ce45264e 586
a3a4f7e1
IL		 587 if (nb_steps <= 0)
588 nb_steps = 2;
589 else if (nb_steps > 12)
590 nb_steps = 12;
ce45264e 591
a3a4f7e1
IL		 592 current_step = 1;
593 direction = 1;
ce45264e 594
a3a4f7e1
IL		 595 if (intp->chip_id <= 0x20) {
596 tuner_freq = intp->freq[d];
597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
598 intp->rolloff) + intp->symbol_rate[d];
599 } else
600 tuner_freq = 0;
601
602 while ((current_step <= nb_steps) && (lock == FALSE)) {
603 if (direction > 0)
604 tuner_freq += (current_step * currier_step);
605 else
606 tuner_freq -= (current_step * currier_step);
607
608 if (intp->chip_id <= 0x20) {
609 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
610 stv0900_write_reg(intp, DMDISTATE, 0x1c);
611 stv0900_write_reg(intp, CFRINIT1, 0);
612 stv0900_write_reg(intp, CFRINIT0, 0);
613 stv0900_write_reg(intp, DMDISTATE, 0x1f);
614 stv0900_write_reg(intp, DMDISTATE, 0x15);
615 } else {
616 stv0900_write_reg(intp, DMDISTATE, 0x1c);
617 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
618 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
619 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
620 stv0900_write_reg(intp, DMDISTATE, 0x1f);
621 stv0900_write_reg(intp, DMDISTATE, 0x05);
ce45264e 622 }
a3a4f7e1
IL		 623
624 lock = stv0900_get_demod_lock(intp, d, timeout);
625 direction *= -1;
626 current_step++;
ce45264e
IL		 627 }
628
629 return lock;
630}
631
632static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
633 s32 srate,
634 enum fe_stv0900_search_algo algo)
635{
636 switch (algo) {
637 case STV0900_BLIND_SEARCH:
638 if (srate <= 1500000) {
639 (*demod_timeout) = 1500;
640 (*fec_timeout) = 400;
641 } else if (srate <= 5000000) {
642 (*demod_timeout) = 1000;
643 (*fec_timeout) = 300;
644 } else {
645 (*demod_timeout) = 700;
646 (*fec_timeout) = 100;
647 }
648
649 break;
650 case STV0900_COLD_START:
651 case STV0900_WARM_START:
652 default:
653 if (srate <= 1000000) {
654 (*demod_timeout) = 3000;
655 (*fec_timeout) = 1700;
656 } else if (srate <= 2000000) {
657 (*demod_timeout) = 2500;
658 (*fec_timeout) = 1100;
659 } else if (srate <= 5000000) {
660 (*demod_timeout) = 1000;
661 (*fec_timeout) = 550;
662 } else if (srate <= 10000000) {
663 (*demod_timeout) = 700;
664 (*fec_timeout) = 250;
665 } else if (srate <= 20000000) {
666 (*demod_timeout) = 400;
667 (*fec_timeout) = 130;
a3a4f7e1 668 } else {
ce45264e
IL		 669 (*demod_timeout) = 300;
670 (*fec_timeout) = 100;
671 }
672
673 break;
674
675 }
676
677 if (algo == STV0900_WARM_START)
678 (*demod_timeout) /= 2;
679}
680
a3a4f7e1 681static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
ce45264e
IL		 682 enum fe_stv0900_demod_num demod)
683{
684
a3a4f7e1 685 s32 vth_reg = VTH12;
ce45264e 686
8171c205 687 dprintk("%s\n", __func__);
ce45264e 688
a3a4f7e1
IL		 689 stv0900_write_reg(intp, vth_reg++, 0xd0);
690 stv0900_write_reg(intp, vth_reg++, 0x7d);
691 stv0900_write_reg(intp, vth_reg++, 0x53);
692 stv0900_write_reg(intp, vth_reg++, 0x2f);
693 stv0900_write_reg(intp, vth_reg++, 0x24);
694 stv0900_write_reg(intp, vth_reg++, 0x1f);
ce45264e
IL		 695}
696
a3a4f7e1
IL		 697static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
698 enum fe_stv0900_search_standard standard,
699 enum fe_stv0900_fec fec,
ce45264e
IL		 700 enum fe_stv0900_demod_num demod)
701{
8171c205 702 dprintk("%s: ViterbiStandard = ", __func__);
ce45264e 703
a3a4f7e1 704 switch (standard) {
ce45264e
IL		 705 case STV0900_AUTO_SEARCH:
706 dprintk("Auto\n");
a3a4f7e1
IL		 707 stv0900_write_reg(intp, FECM, 0x10);
708 stv0900_write_reg(intp, PRVIT, 0x3f);
ce45264e
IL		 709 break;
710 case STV0900_SEARCH_DVBS1:
711 dprintk("DVBS1\n");
a3a4f7e1
IL		 712 stv0900_write_reg(intp, FECM, 0x00);
713 switch (fec) {
ce45264e
IL		 714 case STV0900_FEC_UNKNOWN:
715 default:
a3a4f7e1 716 stv0900_write_reg(intp, PRVIT, 0x2f);
ce45264e
IL		 717 break;
718 case STV0900_FEC_1_2:
a3a4f7e1 719 stv0900_write_reg(intp, PRVIT, 0x01);
ce45264e
IL		 720 break;
721 case STV0900_FEC_2_3:
a3a4f7e1 722 stv0900_write_reg(intp, PRVIT, 0x02);
ce45264e
IL		 723 break;
724 case STV0900_FEC_3_4:
a3a4f7e1 725 stv0900_write_reg(intp, PRVIT, 0x04);
ce45264e
IL		 726 break;
727 case STV0900_FEC_5_6:
a3a4f7e1 728 stv0900_write_reg(intp, PRVIT, 0x08);
ce45264e
IL		 729 break;
730 case STV0900_FEC_7_8:
a3a4f7e1 731 stv0900_write_reg(intp, PRVIT, 0x20);
ce45264e
IL		 732 break;
733 }
734
735 break;
736 case STV0900_SEARCH_DSS:
737 dprintk("DSS\n");
a3a4f7e1
IL		 738 stv0900_write_reg(intp, FECM, 0x80);
739 switch (fec) {
ce45264e
IL		 740 case STV0900_FEC_UNKNOWN:
741 default:
a3a4f7e1 742 stv0900_write_reg(intp, PRVIT, 0x13);
ce45264e
IL		 743 break;
744 case STV0900_FEC_1_2:
a3a4f7e1 745 stv0900_write_reg(intp, PRVIT, 0x01);
ce45264e
IL		 746 break;
747 case STV0900_FEC_2_3:
a3a4f7e1 748 stv0900_write_reg(intp, PRVIT, 0x02);
ce45264e
IL		 749 break;
750 case STV0900_FEC_6_7:
a3a4f7e1 751 stv0900_write_reg(intp, PRVIT, 0x10);
ce45264e
IL		 752 break;
753 }
754 break;
755 default:
756 break;
757 }
758}
759
a3a4f7e1
IL		 760static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
761 enum fe_stv0900_demod_num demod)
762{
763 enum fe_stv0900_fec prate;
764 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
765
766 switch (rate_fld) {
767 case 13:
768 prate = STV0900_FEC_1_2;
769 break;
770 case 18:
771 prate = STV0900_FEC_2_3;
772 break;
773 case 21:
774 prate = STV0900_FEC_3_4;
775 break;
776 case 24:
777 prate = STV0900_FEC_5_6;
778 break;
779 case 25:
780 prate = STV0900_FEC_6_7;
781 break;
782 case 26:
783 prate = STV0900_FEC_7_8;
784 break;
785 default:
786 prate = STV0900_FEC_UNKNOWN;
787 break;
788 }
789
790 return prate;
791}
792
793void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
794 enum fe_stv0900_demod_num demod,
795 u32 srate)
796{
797 if (intp->chip_id >= 0x30) {
798 if (srate >= 15000000) {
799 stv0900_write_reg(intp, ACLC, 0x2b);
800 stv0900_write_reg(intp, BCLC, 0x1a);
801 } else if ((srate >= 7000000) && (15000000 > srate)) {
802 stv0900_write_reg(intp, ACLC, 0x0c);
803 stv0900_write_reg(intp, BCLC, 0x1b);
804 } else if (srate < 7000000) {
805 stv0900_write_reg(intp, ACLC, 0x2c);
806 stv0900_write_reg(intp, BCLC, 0x1c);
807 }
808
809 } else { /*cut 2.0 and 1.x*/
810 stv0900_write_reg(intp, ACLC, 0x1a);
811 stv0900_write_reg(intp, BCLC, 0x09);
812 }
813
814}
815
ce45264e
IL		 816static void stv0900_track_optimization(struct dvb_frontend *fe)
817{
818 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 819 struct stv0900_internal *intp = state->internal;
ce45264e
IL		 820 enum fe_stv0900_demod_num demod = state->demod;
821
a3a4f7e1
IL		 822 s32 srate,
823 pilots,
824 aclc,
825 freq1,
826 freq0,
827 i = 0,
828 timed,
829 timef,
830 blind_tun_sw = 0,
831 modulation;
ce45264e
IL		 832
833 enum fe_stv0900_rolloff rolloff;
834 enum fe_stv0900_modcode foundModcod;
835
8171c205 836 dprintk("%s\n", __func__);
ce45264e 837
a3a4f7e1
IL		 838 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
839 srate += stv0900_get_timing_offst(intp, srate, demod);
ce45264e 840
a3a4f7e1
IL		 841 switch (intp->result[demod].standard) {
842 case STV0900_DVBS1_STANDARD:
843 case STV0900_DSS_STANDARD:
844 dprintk("%s: found DVB-S or DSS\n", __func__);
845 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
846 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
847 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
848 }
ce45264e 849
a3a4f7e1
IL		 850 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
851 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
ce45264e 852
a3a4f7e1
IL		 853 if (intp->chip_id < 0x30) {
854 stv0900_write_reg(intp, ERRCTRL1, 0x75);
ce45264e 855 break;
a3a4f7e1 856 }
ce45264e 857
a3a4f7e1
IL		 858 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
859 stv0900_write_reg(intp, GAUSSR0, 0x98);
860 stv0900_write_reg(intp, CCIR0, 0x18);
861 } else {
862 stv0900_write_reg(intp, GAUSSR0, 0x18);
863 stv0900_write_reg(intp, CCIR0, 0x18);
864 }
ce45264e 865
a3a4f7e1
IL		 866 stv0900_write_reg(intp, ERRCTRL1, 0x75);
867 break;
868 case STV0900_DVBS2_STANDARD:
869 dprintk("%s: found DVB-S2\n", __func__);
870 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
871 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
872 stv0900_write_reg(intp, ACLC, 0);
873 stv0900_write_reg(intp, BCLC, 0);
874 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
875 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
876 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
877 aclc = stv0900_get_optim_carr_loop(srate,
878 foundModcod,
879 pilots,
880 intp->chip_id);
881 if (foundModcod <= STV0900_QPSK_910)
882 stv0900_write_reg(intp, ACLC2S2Q, aclc);
883 else if (foundModcod <= STV0900_8PSK_910) {
884 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
885 stv0900_write_reg(intp, ACLC2S28, aclc);
ce45264e
IL		 886 }
887
a3a4f7e1
IL		 888 if ((intp->demod_mode == STV0900_SINGLE) &&
889 (foundModcod > STV0900_8PSK_910)) {
890 if (foundModcod <= STV0900_16APSK_910) {
891 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
892 stv0900_write_reg(intp, ACLC2S216A,
893 aclc);
894 } else if (foundModcod <= STV0900_32APSK_910) {
895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
896 stv0900_write_reg(intp, ACLC2S232A,
897 aclc);
898 }
899 }
ce45264e 900
a3a4f7e1
IL		 901 } else {
902 modulation = intp->result[demod].modulation;
903 aclc = stv0900_get_optim_short_carr_loop(srate,
904 modulation, intp->chip_id);
905 if (modulation == STV0900_QPSK)
906 stv0900_write_reg(intp, ACLC2S2Q, aclc);
907 else if (modulation == STV0900_8PSK) {
908 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
909 stv0900_write_reg(intp, ACLC2S28, aclc);
910 } else if (modulation == STV0900_16APSK) {
911 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
912 stv0900_write_reg(intp, ACLC2S216A, aclc);
913 } else if (modulation == STV0900_32APSK) {
914 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
915 stv0900_write_reg(intp, ACLC2S232A, aclc);
ce45264e
IL		 916 }
917
ce45264e
IL		 918 }
919
a3a4f7e1
IL		 920 if (intp->chip_id <= 0x11) {
921 if (intp->demod_mode != STV0900_SINGLE)
922 stv0900_activate_s2_modcod(intp, demod);
ce45264e 923
ce45264e
IL		 924 }
925
a3a4f7e1
IL		 926 stv0900_write_reg(intp, ERRCTRL1, 0x67);
927 break;
928 case STV0900_UNKNOWN_STANDARD:
929 default:
930 dprintk("%s: found unknown standard\n", __func__);
931 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
932 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
933 break;
934 }
ce45264e 935
a3a4f7e1
IL		 936 freq1 = stv0900_read_reg(intp, CFR2);
937 freq0 = stv0900_read_reg(intp, CFR1);
938 rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
939 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
940 stv0900_write_reg(intp, SFRSTEP, 0x00);
941 stv0900_write_bits(intp, SCAN_ENABLE, 0);
942 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
943 stv0900_write_reg(intp, TMGCFG2, 0xc1);
944 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
945 blind_tun_sw = 1;
946 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
947 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
ce45264e 948
a3a4f7e1 949 }
ce45264e 950
a3a4f7e1
IL		 951 if (intp->chip_id >= 0x20) {
952 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
953 (intp->srch_standard[demod] ==
954 STV0900_SEARCH_DSS) ||
955 (intp->srch_standard[demod] ==
956 STV0900_AUTO_SEARCH)) {
957 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
958 stv0900_write_reg(intp, VITSCALE, 0x0);
959 }
960 }
ce45264e 961
a3a4f7e1
IL		 962 if (intp->chip_id < 0x20)
963 stv0900_write_reg(intp, CARHDR, 0x08);
ce45264e 964
a3a4f7e1
IL		 965 if (intp->chip_id == 0x10)
966 stv0900_write_reg(intp, CORRELEXP, 0x0a);
ce45264e 967
a3a4f7e1 968 stv0900_write_reg(intp, AGC2REF, 0x38);
ce45264e 969
a3a4f7e1
IL		 970 if ((intp->chip_id >= 0x20) ||
971 (blind_tun_sw == 1) ||
972 (intp->symbol_rate[demod] < 10000000)) {
973 stv0900_write_reg(intp, CFRINIT1, freq1);
974 stv0900_write_reg(intp, CFRINIT0, freq0);
975 intp->bw[demod] = stv0900_carrier_width(srate,
976 intp->rolloff) + 10000000;
ce45264e 977
a3a4f7e1
IL		 978 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
979 if (intp->srch_algo[demod] != STV0900_WARM_START)
980 stv0900_set_bandwidth(fe, intp->bw[demod]);
981 }
ce45264e 982
a3a4f7e1
IL		 983 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
984 (intp->symbol_rate[demod] < 10000000))
985 msleep(50);
986 else
987 msleep(5);
ce45264e 988
a3a4f7e1
IL		 989 stv0900_get_lock_timeout(&timed, &timef, srate,
990 STV0900_WARM_START);
ce45264e 991
a3a4f7e1
IL		 992 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
993 stv0900_write_reg(intp, DMDISTATE, 0x1f);
994 stv0900_write_reg(intp, CFRINIT1, freq1);
995 stv0900_write_reg(intp, CFRINIT0, freq0);
996 stv0900_write_reg(intp, DMDISTATE, 0x18);
997 i = 0;
998 while ((stv0900_get_demod_lock(intp,
999 demod,
1000 timed / 2) == FALSE) &&
1001 (i <= 2)) {
1002 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1003 stv0900_write_reg(intp, CFRINIT1, freq1);
1004 stv0900_write_reg(intp, CFRINIT0, freq0);
1005 stv0900_write_reg(intp, DMDISTATE, 0x18);
1006 i++;
ce45264e 1007 }
a3a4f7e1 1008 }
ce45264e 1009
a3a4f7e1 1010 }
ce45264e 1011
a3a4f7e1
IL		 1012 if (intp->chip_id >= 0x20)
1013 stv0900_write_reg(intp, CARFREQ, 0x49);
ce45264e 1014
a3a4f7e1
IL		 1015 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1016 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1017 stv0900_set_viterbi_tracq(intp, demod);
ce45264e 1018
a3a4f7e1 1019}
ce45264e 1020
a3a4f7e1
IL		 1021static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1022 enum fe_stv0900_demod_num demod, s32 time_out)
1023{
1024 s32 timer = 0, lock = 0;
ce45264e 1025
a3a4f7e1 1026 enum fe_stv0900_search_state dmd_state;
ce45264e 1027
8171c205 1028 dprintk("%s\n", __func__);
ce45264e 1029
a3a4f7e1 1030 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
ce45264e
IL		 1031
1032 while ((timer < time_out) && (lock == 0)) {
1033 switch (dmd_state) {
1034 case STV0900_SEARCH:
1035 case STV0900_PLH_DETECTED:
1036 default:
1037 lock = 0;
1038 break;
1039 case STV0900_DVBS2_FOUND:
a3a4f7e1 1040 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
ce45264e
IL		 1041 break;
1042 case STV0900_DVBS_FOUND:
a3a4f7e1 1043 lock = stv0900_get_bits(intp, LOCKEDVIT);
ce45264e
IL		 1044 break;
1045 }
1046
1047 if (lock == 0) {
1048 msleep(10);
1049 timer += 10;
1050 }
1051 }
1052
1053 if (lock)
a3a4f7e1 1054 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
ce45264e 1055 else
a3a4f7e1 1056 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
ce45264e
IL		 1057
1058 return lock;
1059}
1060
a3a4f7e1 1061static int stv0900_wait_for_lock(struct stv0900_internal *intp,
ce45264e
IL		 1062 enum fe_stv0900_demod_num demod,
1063 s32 dmd_timeout, s32 fec_timeout)
1064{
1065
a3a4f7e1 1066 s32 timer = 0, lock = 0;
ce45264e 1067
8171c205 1068 dprintk("%s\n", __func__);
ce45264e 1069
a3a4f7e1 1070 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
ce45264e
IL		 1071
1072 if (lock)
a3a4f7e1 1073 lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
ce45264e
IL		 1074
1075 if (lock) {
1076 lock = 0;
1077
a3a4f7e1
IL		 1078 dprintk("%s: Timer = %d, time_out = %d\n",
1079 __func__, timer, fec_timeout);
ce45264e
IL		 1080
1081 while ((timer < fec_timeout) && (lock == 0)) {
a3a4f7e1 1082 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
ce45264e
IL		 1083 msleep(1);
1084 timer++;
1085 }
1086 }
1087
1088 if (lock)
8171c205 1089 dprintk("%s: DEMOD LOCK OK\n", __func__);
ce45264e 1090 else
8171c205 1091 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
ce45264e
IL		 1092
1093 if (lock)
1094 return TRUE;
1095 else
1096 return FALSE;
1097}
1098
1099enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1100 enum fe_stv0900_demod_num demod)
1101{
1102 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1103 struct stv0900_internal *intp = state->internal;
ce45264e 1104 enum fe_stv0900_tracking_standard fnd_standard;
ce45264e 1105
a3a4f7e1 1106 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
ce45264e 1107
a3a4f7e1
IL		 1108 switch (hdr_mode) {
1109 case 2:
ce45264e 1110 fnd_standard = STV0900_DVBS2_STANDARD;
a3a4f7e1
IL		 1111 break;
1112 case 3:
1113 if (stv0900_get_bits(intp, DSS_DVB) == 1)
ce45264e
IL		 1114 fnd_standard = STV0900_DSS_STANDARD;
1115 else
1116 fnd_standard = STV0900_DVBS1_STANDARD;
a3a4f7e1
IL		 1117
1118 break;
1119 default:
ce45264e 1120 fnd_standard = STV0900_UNKNOWN_STANDARD;
a3a4f7e1
IL		 1121 }
1122
1123 dprintk("%s: standard %d\n", __func__, fnd_standard);
ce45264e
IL		 1124
1125 return fnd_standard;
1126}
1127
a3a4f7e1 1128static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
ce45264e
IL		 1129 enum fe_stv0900_demod_num demod)
1130{
a3a4f7e1
IL		 1131 s32 derot,
1132 rem1,
1133 rem2,
1134 intval1,
1135 intval2;
ce45264e 1136
a3a4f7e1
IL		 1137 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1138 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1139 (stv0900_get_bits(intp, CAR_FREQ0));
ce45264e
IL		 1140
1141 derot = ge2comp(derot, 24);
1142 intval1 = mclk >> 12;
1143 intval2 = derot >> 12;
1144 rem1 = mclk % 0x1000;
1145 rem2 = derot % 0x1000;
1146 derot = (intval1 * intval2) +
1147 ((intval1 * rem2) >> 12) +
1148 ((intval2 * rem1) >> 12);
1149
1150 return derot;
1151}
1152
1153static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1154{
1155 struct dvb_frontend_ops *frontend_ops = NULL;
1156 struct dvb_tuner_ops *tuner_ops = NULL;
a3a4f7e1 1157 u32 freq = 0;
ce45264e
IL		 1158
1159 if (&fe->ops)
1160 frontend_ops = &fe->ops;
1161
1162 if (&frontend_ops->tuner_ops)
1163 tuner_ops = &frontend_ops->tuner_ops;
1164
1165 if (tuner_ops->get_frequency) {
a3a4f7e1 1166 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
ce45264e
IL		 1167 dprintk("%s: Invalid parameter\n", __func__);
1168 else
a3a4f7e1 1169 dprintk("%s: Frequency=%d\n", __func__, freq);
ce45264e 1170
ce45264e
IL		 1171 }
1172
a3a4f7e1 1173 return freq;
ce45264e
IL		 1174}
1175
a3a4f7e1
IL		 1176static enum
1177fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
ce45264e
IL		 1178{
1179 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1180 struct stv0900_internal *intp = state->internal;
ce45264e
IL		 1181 enum fe_stv0900_demod_num demod = state->demod;
1182 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
a3a4f7e1
IL		 1183 struct stv0900_signal_info *result = &intp->result[demod];
1184 s32 offsetFreq,
1185 srate_offset;
1186 int i = 0,
1187 d = demod;
ce45264e
IL		 1188
1189 u8 timing;
1190
1191 msleep(5);
a3a4f7e1
IL		 1192 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1193 timing = stv0900_read_reg(intp, TMGREG2);
1194 i = 0;
1195 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1196
1197 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1198 timing = stv0900_read_reg(intp, TMGREG2);
1199 msleep(5);
1200 i += 5;
ce45264e 1201 }
a3a4f7e1 1202 }
ce45264e 1203
a3a4f7e1
IL		 1204 result->standard = stv0900_get_standard(fe, d);
1205 result->frequency = stv0900_get_tuner_freq(fe);
1206 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1207 result->frequency += offsetFreq;
1208 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1209 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1210 result->symbol_rate += srate_offset;
1211 result->fec = stv0900_get_vit_fec(intp, d);
1212 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1213 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1214 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1215 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1216 switch (result->standard) {
1217 case STV0900_DVBS2_STANDARD:
1218 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1219 if (result->modcode <= STV0900_QPSK_910)
1220 result->modulation = STV0900_QPSK;
1221 else if (result->modcode <= STV0900_8PSK_910)
1222 result->modulation = STV0900_8PSK;
1223 else if (result->modcode <= STV0900_16APSK_910)
1224 result->modulation = STV0900_16APSK;
1225 else if (result->modcode <= STV0900_32APSK_910)
1226 result->modulation = STV0900_32APSK;
1227 else
1228 result->modulation = STV0900_UNKNOWN;
ce45264e 1229 break;
a3a4f7e1
IL		 1230 case STV0900_DVBS1_STANDARD:
1231 case STV0900_DSS_STANDARD:
1232 result->spectrum = stv0900_get_bits(intp, IQINV);
1233 result->modulation = STV0900_QPSK;
1234 break;
1235 default:
1236 break;
1237 }
ce45264e 1238
a3a4f7e1
IL		 1239 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1240 (intp->symbol_rate[d] < 10000000)) {
1241 offsetFreq = result->frequency - intp->freq[d];
1242 intp->freq[d] = stv0900_get_tuner_freq(fe);
1243 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1244 range = STV0900_RANGEOK;
1245 else if (ABS(offsetFreq) <=
1246 (stv0900_carrier_width(result->symbol_rate,
1247 result->rolloff) / 2000))
1248 range = STV0900_RANGEOK;
ce45264e 1249
a3a4f7e1
IL		 1250 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1251 range = STV0900_RANGEOK;
ce45264e 1252
a3a4f7e1 1253 dprintk("%s: range %d\n", __func__, range);
ce45264e
IL		 1254
1255 return range;
1256}
1257
a3a4f7e1
IL		 1258static enum
1259fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
ce45264e
IL		 1260{
1261 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1262 struct stv0900_internal *intp = state->internal;
ce45264e 1263 enum fe_stv0900_demod_num demod = state->demod;
1ebcad77 1264 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
ce45264e 1265
a3a4f7e1
IL		 1266 s32 srate,
1267 demod_timeout,
1268 fec_timeout,
1269 freq1,
1270 freq0;
1271
1272 intp->result[demod].locked = FALSE;
1273
1274 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1275 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1276 srate += stv0900_get_timing_offst(intp, srate, demod);
1277 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1278 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1279
1280 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1281 srate, STV0900_WARM_START);
1282 freq1 = stv0900_read_reg(intp, CFR2);
1283 freq0 = stv0900_read_reg(intp, CFR1);
1284 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1285 stv0900_write_bits(intp, SPECINV_CONTROL,
1286 STV0900_IQ_FORCE_SWAPPED);
1287 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1288 stv0900_write_reg(intp, CFRINIT1, freq1);
1289 stv0900_write_reg(intp, CFRINIT0, freq0);
1290 stv0900_write_reg(intp, DMDISTATE, 0x18);
1291 if (stv0900_wait_for_lock(intp, demod,
1292 demod_timeout, fec_timeout) == TRUE) {
1293 intp->result[demod].locked = TRUE;
1294 signal_type = stv0900_get_signal_params(fe);
1295 stv0900_track_optimization(fe);
1296 } else {
1297 stv0900_write_bits(intp, SPECINV_CONTROL,
1298 STV0900_IQ_FORCE_NORMAL);
1299 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1300 stv0900_write_reg(intp, CFRINIT1, freq1);
1301 stv0900_write_reg(intp, CFRINIT0, freq0);
1302 stv0900_write_reg(intp, DMDISTATE, 0x18);
1303 if (stv0900_wait_for_lock(intp, demod,
1304 demod_timeout, fec_timeout) == TRUE) {
1305 intp->result[demod].locked = TRUE;
ce45264e
IL		 1306 signal_type = stv0900_get_signal_params(fe);
1307 stv0900_track_optimization(fe);
ce45264e
IL		 1308 }
1309
a3a4f7e1 1310 }
ce45264e 1311
a3a4f7e1
IL		 1312 } else
1313 intp->result[demod].locked = FALSE;
ce45264e
IL		 1314
1315 return signal_type;
1316}
1317
a3a4f7e1 1318static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
ce45264e
IL		 1319 enum fe_stv0900_demod_num demod)
1320{
1321 u32 minagc2level = 0xffff,
1322 agc2level,
1323 init_freq, freq_step;
1324
1325 s32 i, j, nb_steps, direction;
1326
8171c205 1327 dprintk("%s\n", __func__);
ce45264e 1328
a3a4f7e1
IL		 1329 stv0900_write_reg(intp, AGC2REF, 0x38);
1330 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1331 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
ce45264e 1332
a3a4f7e1
IL		 1333 stv0900_write_bits(intp, AUTO_GUP, 1);
1334 stv0900_write_bits(intp, AUTO_GLOW, 1);
ce45264e 1335
a3a4f7e1 1336 stv0900_write_reg(intp, DMDT0M, 0x0);
ce45264e 1337
a3a4f7e1
IL		 1338 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1339 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1340 nb_steps /= 2;
1341 nb_steps = (2 * nb_steps) + 1;
ce45264e 1342
a3a4f7e1
IL		 1343 if (nb_steps < 0)
1344 nb_steps = 1;
ce45264e 1345
a3a4f7e1 1346 direction = 1;
ce45264e 1347
a3a4f7e1 1348 freq_step = (1000000 << 8) / (intp->mclk >> 8);
ce45264e 1349
a3a4f7e1 1350 init_freq = 0;
ce45264e 1351
a3a4f7e1
IL		 1352 for (i = 0; i < nb_steps; i++) {
1353 if (direction > 0)
1354 init_freq = init_freq + (freq_step * i);
1355 else
1356 init_freq = init_freq - (freq_step * i);
ce45264e 1357
a3a4f7e1
IL		 1358 direction *= -1;
1359 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1360 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1361 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1362 stv0900_write_reg(intp, DMDISTATE, 0x58);
1363 msleep(10);
1364 agc2level = 0;
ce45264e 1365
a3a4f7e1
IL		 1366 for (j = 0; j < 10; j++)
1367 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1368 | stv0900_read_reg(intp, AGC2I0);
ce45264e 1369
a3a4f7e1 1370 agc2level /= 10;
ce45264e 1371
a3a4f7e1
IL		 1372 if (agc2level < minagc2level)
1373 minagc2level = agc2level;
ce45264e 1374
ce45264e
IL		 1375 }
1376
1377 return (u16)minagc2level;
1378}
1379
1380static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1381{
1382 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1383 struct stv0900_internal *intp = state->internal;
ce45264e 1384 enum fe_stv0900_demod_num demod = state->demod;
a3a4f7e1 1385 int timing_lck = FALSE;
ce45264e
IL		 1386 s32 i, timingcpt = 0,
1387 direction = 1,
1388 nb_steps,
1389 current_step = 0,
1390 tuner_freq;
a3a4f7e1
IL		 1391 u32 agc2_th,
1392 coarse_srate = 0,
1393 agc2_integr = 0,
1394 currier_step = 1200;
ce45264e 1395
a3a4f7e1
IL		 1396 if (intp->chip_id >= 0x30)
1397 agc2_th = 0x2e00;
1398 else
1399 agc2_th = 0x1f00;
1400
1401 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1402 stv0900_write_reg(intp, TMGCFG, 0x12);
1403 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1404 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1405 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1406 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1407 stv0900_write_reg(intp, SFRUP1, 0x83);
1408 stv0900_write_reg(intp, SFRUP0, 0xc0);
1409 stv0900_write_reg(intp, SFRLOW1, 0x82);
1410 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1411 stv0900_write_reg(intp, DMDT0M, 0x0);
1412 stv0900_write_reg(intp, AGC2REF, 0x50);
1413
1414 if (intp->chip_id >= 0x30) {
1415 stv0900_write_reg(intp, CARFREQ, 0x99);
1416 stv0900_write_reg(intp, SFRSTEP, 0x98);
1417 } else if (intp->chip_id >= 0x20) {
1418 stv0900_write_reg(intp, CARFREQ, 0x6a);
1419 stv0900_write_reg(intp, SFRSTEP, 0x95);
1420 } else {
1421 stv0900_write_reg(intp, CARFREQ, 0xed);
1422 stv0900_write_reg(intp, SFRSTEP, 0x73);
1423 }
ce45264e 1424
a3a4f7e1
IL		 1425 if (intp->symbol_rate[demod] <= 2000000)
1426 currier_step = 1000;
1427 else if (intp->symbol_rate[demod] <= 5000000)
1428 currier_step = 2000;
1429 else if (intp->symbol_rate[demod] <= 12000000)
1430 currier_step = 3000;
1431 else
ce45264e
IL		 1432 currier_step = 5000;
1433
a3a4f7e1
IL		 1434 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1435 nb_steps /= 2;
1436 nb_steps = (2 * nb_steps) + 1;
ce45264e 1437
a3a4f7e1
IL		 1438 if (nb_steps < 0)
1439 nb_steps = 1;
1440 else if (nb_steps > 10) {
1441 nb_steps = 11;
1442 currier_step = (intp->srch_range[demod] / 1000) / 10;
1443 }
ce45264e 1444
a3a4f7e1
IL		 1445 current_step = 0;
1446 direction = 1;
ce45264e 1447
a3a4f7e1 1448 tuner_freq = intp->freq[demod];
ce45264e 1449
a3a4f7e1
IL		 1450 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1451 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1452 stv0900_write_bits(intp, DEMOD_MODE, 0);
ce45264e 1453
a3a4f7e1 1454 msleep(50);
ce45264e 1455
a3a4f7e1
IL		 1456 for (i = 0; i < 10; i++) {
1457 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1458 timingcpt++;
ce45264e 1459
a3a4f7e1
IL		 1460 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1461 stv0900_read_reg(intp, AGC2I0);
ce45264e
IL		 1462 }
1463
a3a4f7e1
IL		 1464 agc2_integr /= 10;
1465 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1466 current_step++;
1467 direction *= -1;
1468
1469 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
1470 " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1471 tuner_freq, agc2_integr, coarse_srate, timingcpt);
1472
1473 if ((timingcpt >= 5) &&
1474 (agc2_integr < agc2_th) &&
1475 (coarse_srate < 55000000) &&
1476 (coarse_srate > 850000))
1477 timing_lck = TRUE;
1478 else if (current_step < nb_steps) {
1479 if (direction > 0)
1480 tuner_freq += (current_step * currier_step);
1481 else
1482 tuner_freq -= (current_step * currier_step);
ce45264e 1483
a3a4f7e1 1484 stv0900_set_tuner(fe, tuner_freq, intp->bw[demod]);
ce45264e 1485 }
ce45264e
IL		 1486 }
1487
a3a4f7e1
IL		 1488 if (timing_lck == FALSE)
1489 coarse_srate = 0;
1490 else
1491 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1492
ce45264e
IL		 1493 return coarse_srate;
1494}
1495
1496static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1497{
1498 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1499 struct stv0900_internal *intp = state->internal;
ce45264e 1500 enum fe_stv0900_demod_num demod = state->demod;
a3a4f7e1
IL		 1501 u32 coarse_srate,
1502 coarse_freq,
1503 symb,
1504 symbmax,
1505 symbmin,
1506 symbcomp;
1507
1508 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1509
1510 if (coarse_srate > 3000000) {
1511 symbmax = 13 * (coarse_srate / 10);
1512 symbmax = (symbmax / 1000) * 65536;
1513 symbmax /= (intp->mclk / 1000);
1514
1515 symbmin = 10 * (coarse_srate / 13);
1516 symbmin = (symbmin / 1000)*65536;
1517 symbmin /= (intp->mclk / 1000);
1518
1519 symb = (coarse_srate / 1000) * 65536;
1520 symb /= (intp->mclk / 1000);
1521 } else {
1522 symbmax = 13 * (coarse_srate / 10);
1523 symbmax = (symbmax / 100) * 65536;
1524 symbmax /= (intp->mclk / 100);
ce45264e 1525
a3a4f7e1
IL		 1526 symbmin = 10 * (coarse_srate / 14);
1527 symbmin = (symbmin / 100) * 65536;
1528 symbmin /= (intp->mclk / 100);
ce45264e 1529
a3a4f7e1
IL		 1530 symb = (coarse_srate / 100) * 65536;
1531 symb /= (intp->mclk / 100);
1532 }
ce45264e 1533
a3a4f7e1
IL		 1534 symbcomp = 13 * (coarse_srate / 10);
1535 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1536 | stv0900_read_reg(intp, CFR1);
1537
1538 if (symbcomp < intp->symbol_rate[demod])
1539 coarse_srate = 0;
1540 else {
1541 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1542 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1543 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1544 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1545 stv0900_write_reg(intp, TMGCFG, 0xd2);
1546 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1547 stv0900_write_reg(intp, AGC2REF, 0x38);
1548
1549 if (intp->chip_id >= 0x30)
1550 stv0900_write_reg(intp, CARFREQ, 0x79);
1551 else if (intp->chip_id >= 0x20)
1552 stv0900_write_reg(intp, CARFREQ, 0x49);
1553 else
1554 stv0900_write_reg(intp, CARFREQ, 0xed);
ce45264e 1555
a3a4f7e1
IL		 1556 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1557 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
ce45264e 1558
a3a4f7e1
IL		 1559 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1560 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1561
1562 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1563 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1564
1565 stv0900_write_reg(intp, DMDT0M, 0x20);
1566 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1567 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1568 stv0900_write_reg(intp, DMDISTATE, 0x15);
ce45264e
IL		 1569 }
1570
1571 return coarse_srate;
1572}
1573
1574static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1575{
1576 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1577 struct stv0900_internal *intp = state->internal;
ce45264e 1578 enum fe_stv0900_demod_num demod = state->demod;
a3a4f7e1
IL		 1579 u8 k_ref_tmg,
1580 k_ref_tmg_max,
1581 k_ref_tmg_min;
1582 u32 coarse_srate,
1583 agc2_th;
1584 int lock = FALSE,
1585 coarse_fail = FALSE;
1586 s32 demod_timeout = 500,
1587 fec_timeout = 50,
1588 fail_cpt,
1589 i,
1590 agc2_overflow;
1591 u16 agc2_int;
1592 u8 dstatus2;
ce45264e 1593
8171c205 1594 dprintk("%s\n", __func__);
ce45264e 1595
a3a4f7e1 1596 if (intp->chip_id < 0x20) {
ce45264e
IL		 1597 k_ref_tmg_max = 233;
1598 k_ref_tmg_min = 143;
1599 } else {
a3a4f7e1
IL		 1600 k_ref_tmg_max = 110;
1601 k_ref_tmg_min = 10;
ce45264e
IL		 1602 }
1603
a3a4f7e1
IL		 1604 if (intp->chip_id <= 0x20)
1605 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1606 else
1607 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
ce45264e 1608
a3a4f7e1 1609 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
ce45264e 1610
a3a4f7e1
IL		 1611 if (agc2_int > STV0900_BLIND_SEARCH_AGC2_TH)
1612 return FALSE;
ce45264e 1613
a3a4f7e1
IL		 1614 if (intp->chip_id == 0x10)
1615 stv0900_write_reg(intp, CORRELEXP, 0xaa);
ce45264e 1616
a3a4f7e1
IL		 1617 if (intp->chip_id < 0x20)
1618 stv0900_write_reg(intp, CARHDR, 0x55);
1619 else
1620 stv0900_write_reg(intp, CARHDR, 0x20);
ce45264e 1621
a3a4f7e1
IL		 1622 if (intp->chip_id <= 0x20)
1623 stv0900_write_reg(intp, CARCFG, 0xc4);
1624 else
1625 stv0900_write_reg(intp, CARCFG, 0x6);
ce45264e 1626
a3a4f7e1 1627 stv0900_write_reg(intp, RTCS2, 0x44);
ce45264e 1628
a3a4f7e1
IL		 1629 if (intp->chip_id >= 0x20) {
1630 stv0900_write_reg(intp, EQUALCFG, 0x41);
1631 stv0900_write_reg(intp, FFECFG, 0x41);
1632 stv0900_write_reg(intp, VITSCALE, 0x82);
1633 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1634 }
ce45264e 1635
a3a4f7e1 1636 k_ref_tmg = k_ref_tmg_max;
ce45264e 1637
a3a4f7e1
IL		 1638 do {
1639 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1640 if (stv0900_search_srate_coarse(fe) != 0) {
1641 coarse_srate = stv0900_search_srate_fine(fe);
1642
1643 if (coarse_srate != 0) {
1644 stv0900_get_lock_timeout(&demod_timeout,
1645 &fec_timeout,
1646 coarse_srate,
1647 STV0900_BLIND_SEARCH);
1648 lock = stv0900_get_demod_lock(intp,
1649 demod,
1650 demod_timeout);
1651 } else
1652 lock = FALSE;
1653 } else {
1654 fail_cpt = 0;
1655 agc2_overflow = 0;
ce45264e 1656
a3a4f7e1
IL		 1657 for (i = 0; i < 10; i++) {
1658 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1659 | stv0900_read_reg(intp, AGC2I0);
ce45264e 1660
a3a4f7e1
IL		 1661 if (agc2_int >= 0xff00)
1662 agc2_overflow++;
ce45264e 1663
a3a4f7e1 1664 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
ce45264e 1665
a3a4f7e1
IL		 1666 if (((dstatus2 & 0x1) == 0x1) &&
1667 ((dstatus2 >> 7) == 1))
1668 fail_cpt++;
1669 }
ce45264e 1670
a3a4f7e1
IL		 1671 if ((fail_cpt > 7) || (agc2_overflow > 7))
1672 coarse_fail = TRUE;
ce45264e 1673
a3a4f7e1
IL		 1674 lock = FALSE;
1675 }
1676 k_ref_tmg -= 30;
1677 } while ((k_ref_tmg >= k_ref_tmg_min) &&
1678 (lock == FALSE) &&
1679 (coarse_fail == FALSE));
ce45264e
IL		 1680
1681 return lock;
1682}
1683
a3a4f7e1 1684static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
ce45264e
IL		 1685 enum fe_stv0900_demod_num demod)
1686{
a3a4f7e1 1687 s32 vth_reg = VTH12;
ce45264e 1688
8171c205 1689 dprintk("%s\n", __func__);
ce45264e 1690
a3a4f7e1
IL		 1691 stv0900_write_reg(intp, vth_reg++, 0x96);
1692 stv0900_write_reg(intp, vth_reg++, 0x64);
1693 stv0900_write_reg(intp, vth_reg++, 0x36);
1694 stv0900_write_reg(intp, vth_reg++, 0x23);
1695 stv0900_write_reg(intp, vth_reg++, 0x1e);
1696 stv0900_write_reg(intp, vth_reg++, 0x19);
ce45264e
IL		 1697}
1698
a3a4f7e1 1699static void stv0900_set_search_standard(struct stv0900_internal *intp,
ce45264e
IL		 1700 enum fe_stv0900_demod_num demod)
1701{
1702
8171c205 1703 dprintk("%s\n", __func__);
ce45264e 1704
a3a4f7e1 1705 switch (intp->srch_standard[demod]) {
ce45264e
IL		 1706 case STV0900_SEARCH_DVBS1:
1707 dprintk("Search Standard = DVBS1\n");
1708 break;
1709 case STV0900_SEARCH_DSS:
1710 dprintk("Search Standard = DSS\n");
1711 case STV0900_SEARCH_DVBS2:
1712 break;
1713 dprintk("Search Standard = DVBS2\n");
1714 case STV0900_AUTO_SEARCH:
1715 default:
1716 dprintk("Search Standard = AUTO\n");
1717 break;
1718 }
1719
a3a4f7e1
IL		 1720 switch (intp->srch_standard[demod]) {
1721 case STV0900_SEARCH_DVBS1:
1722 case STV0900_SEARCH_DSS:
1723 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1724 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1725 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1726 stv0900_set_dvbs1_track_car_loop(intp,
1727 demod,
1728 intp->symbol_rate[demod]);
1729 stv0900_write_reg(intp, CAR2CFG, 0x22);
1730
1731 stv0900_set_viterbi_acq(intp, demod);
1732 stv0900_set_viterbi_standard(intp,
1733 intp->srch_standard[demod],
1734 intp->fec[demod], demod);
ce45264e 1735
a3a4f7e1
IL		 1736 break;
1737 case STV0900_SEARCH_DVBS2:
1738 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1739 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1740 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1741 stv0900_write_reg(intp, ACLC, 0x1a);
1742 stv0900_write_reg(intp, BCLC, 0x09);
1743 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1744 stv0900_write_reg(intp, CAR2CFG, 0x26);
1745 else
1746 stv0900_write_reg(intp, CAR2CFG, 0x66);
ce45264e 1747
a3a4f7e1
IL		 1748 if (intp->demod_mode != STV0900_SINGLE) {
1749 if (intp->chip_id <= 0x11)
1750 stv0900_stop_all_s2_modcod(intp, demod);
ce45264e 1751 else
a3a4f7e1 1752 stv0900_activate_s2_modcod(intp, demod);
ce45264e 1753
a3a4f7e1
IL		 1754 } else
1755 stv0900_activate_s2_modcod_single(intp, demod);
ce45264e 1756
a3a4f7e1 1757 stv0900_set_viterbi_tracq(intp, demod);
ce45264e 1758
a3a4f7e1
IL		 1759 break;
1760 case STV0900_AUTO_SEARCH:
1761 default:
1762 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1763 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1764 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1765 stv0900_write_reg(intp, ACLC, 0x1a);
1766 stv0900_write_reg(intp, BCLC, 0x09);
1767 stv0900_set_dvbs1_track_car_loop(intp,
1768 demod,
1769 intp->symbol_rate[demod]);
1770 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1771 stv0900_write_reg(intp, CAR2CFG, 0x26);
1772 else
1773 stv0900_write_reg(intp, CAR2CFG, 0x66);
ce45264e 1774
a3a4f7e1
IL		 1775 if (intp->demod_mode != STV0900_SINGLE) {
1776 if (intp->chip_id <= 0x11)
1777 stv0900_stop_all_s2_modcod(intp, demod);
ce45264e 1778 else
a3a4f7e1 1779 stv0900_activate_s2_modcod(intp, demod);
ce45264e 1780
a3a4f7e1
IL		 1781 } else
1782 stv0900_activate_s2_modcod_single(intp, demod);
ce45264e 1783
a3a4f7e1
IL		 1784 stv0900_set_viterbi_tracq(intp, demod);
1785 stv0900_set_viterbi_standard(intp,
1786 intp->srch_standard[demod],
1787 intp->fec[demod], demod);
ce45264e
IL		 1788
1789 break;
1790 }
1791}
1792
1793enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1794{
1795 struct stv0900_state *state = fe->demodulator_priv;
a3a4f7e1 1796 struct stv0900_internal *intp = state->internal;
ce45264e
IL		 1797 enum fe_stv0900_demod_num demod = state->demod;
1798
a3a4f7e1
IL		 1799 s32 demod_timeout = 500, fec_timeout = 50;
1800 s32 aq_power, agc1_power, i;
ce45264e
IL		 1801
1802 int lock = FALSE, low_sr = FALSE;
1803
1804 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1805 enum fe_stv0900_search_algo algo;
1806 int no_signal = FALSE;
1807
8171c205 1808 dprintk("%s\n", __func__);
ce45264e 1809
a3a4f7e1
IL		 1810 algo = intp->srch_algo[demod];
1811 stv0900_write_bits(intp, RST_HWARE, 1);
1812 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1813 if (intp->chip_id >= 0x20) {
1814 if (intp->symbol_rate[demod] > 5000000)
1815 stv0900_write_reg(intp, CORRELABS, 0x9e);
ce45264e 1816 else
a3a4f7e1
IL		 1817 stv0900_write_reg(intp, CORRELABS, 0x82);
1818 } else
1819 stv0900_write_reg(intp, CORRELABS, 0x88);
ce45264e 1820
a3a4f7e1
IL		 1821 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1822 intp->symbol_rate[demod],
1823 intp->srch_algo[demod]);
ce45264e 1824
a3a4f7e1
IL		 1825 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1826 intp->bw[demod] = 2 * 36000000;
ce45264e 1827
a3a4f7e1
IL		 1828 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1829 stv0900_write_reg(intp, CORRELMANT, 0x70);
ce45264e 1830
a3a4f7e1
IL		 1831 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1832 } else {
1833 stv0900_write_reg(intp, DMDT0M, 0x20);
1834 stv0900_write_reg(intp, TMGCFG, 0xd2);
ce45264e 1835
a3a4f7e1
IL		 1836 if (intp->symbol_rate[demod] < 2000000)
1837 stv0900_write_reg(intp, CORRELMANT, 0x63);
ce45264e 1838 else
a3a4f7e1 1839 stv0900_write_reg(intp, CORRELMANT, 0x70);
ce45264e 1840
a3a4f7e1 1841 stv0900_write_reg(intp, AGC2REF, 0x38);
ce45264e 1842
a3a4f7e1
IL		 1843 intp->bw[demod] =
1844 stv0900_carrier_width(intp->symbol_rate[demod],
1845 intp->rolloff);
1846 if (intp->chip_id >= 0x20) {
1847 stv0900_write_reg(intp, KREFTMG, 0x5a);
ce45264e 1848
a3a4f7e1
IL		 1849 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1850 intp->bw[demod] += 10000000;
1851 intp->bw[demod] *= 15;
1852 intp->bw[demod] /= 10;
1853 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1854 intp->bw[demod] += 10000000;
ce45264e 1855
ce45264e 1856 } else {
a3a4f7e1
IL		 1857 stv0900_write_reg(intp, KREFTMG, 0xc1);
1858 intp->bw[demod] += 10000000;
1859 intp->bw[demod] *= 15;
1860 intp->bw[demod] /= 10;
1861 }
ce45264e 1862
a3a4f7e1 1863 stv0900_write_reg(intp, TMGCFG2, 0xc1);
ce45264e 1864
a3a4f7e1
IL		 1865 stv0900_set_symbol_rate(intp, intp->mclk,
1866 intp->symbol_rate[demod], demod);
1867 stv0900_set_max_symbol_rate(intp, intp->mclk,
1868 intp->symbol_rate[demod], demod);
1869 stv0900_set_min_symbol_rate(intp, intp->mclk,
1870 intp->symbol_rate[demod], demod);
1871 if (intp->symbol_rate[demod] >= 10000000)
1872 low_sr = FALSE;
1873 else
1874 low_sr = TRUE;
ce45264e 1875
a3a4f7e1 1876 }
ce45264e 1877
a3a4f7e1 1878 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
ce45264e 1879
a3a4f7e1
IL		 1880 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1881 stv0900_get_bits(intp, AGCIQ_VALUE0));
ce45264e 1882
a3a4f7e1 1883 aq_power = 0;
ce45264e 1884
a3a4f7e1
IL		 1885 if (agc1_power == 0) {
1886 for (i = 0; i < 5; i++)
1887 aq_power += (stv0900_get_bits(intp, POWER_I) +
1888 stv0900_get_bits(intp, POWER_Q)) / 2;
ce45264e 1889
a3a4f7e1
IL		 1890 aq_power /= 5;
1891 }
ce45264e 1892
a3a4f7e1
IL		 1893 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1894 intp->result[demod].locked = FALSE;
1895 signal_type = STV0900_NOAGC1;
1896 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1897 } else {
1898 stv0900_write_bits(intp, SPECINV_CONTROL,
1899 intp->srch_iq_inv[demod]);
1900 if (intp->chip_id <= 0x20) /*cut 2.0*/
1901 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1902 else /*cut 3.0*/
1903 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
ce45264e 1904
a3a4f7e1 1905 stv0900_set_search_standard(intp, demod);
ce45264e 1906
a3a4f7e1
IL		 1907 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1908 stv0900_start_search(intp, demod);
ce45264e
IL		 1909 }
1910
a3a4f7e1
IL		 1911 if (signal_type == STV0900_NOAGC1)
1912 return signal_type;
1913
1914 if (intp->chip_id == 0x12) {
1915 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e 1916 msleep(3);
a3a4f7e1
IL		 1917 stv0900_write_bits(intp, RST_HWARE, 1);
1918 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e
IL		 1919 }
1920
1921 if (algo == STV0900_BLIND_SEARCH)
1922 lock = stv0900_blind_search_algo(fe);
1923 else if (algo == STV0900_COLD_START)
1924 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1925 else if (algo == STV0900_WARM_START)
a3a4f7e1 1926 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
ce45264e
IL		 1927
1928 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1929 if (low_sr == FALSE) {
a3a4f7e1
IL		 1930 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1931 lock = stv0900_sw_algo(intp, demod);
ce45264e
IL		 1932 }
1933 }
1934
1935 if (lock == TRUE)
1936 signal_type = stv0900_get_signal_params(fe);
1937
1938 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1939 stv0900_track_optimization(fe);
a3a4f7e1
IL		 1940 if (intp->chip_id <= 0x11) {
1941 if ((stv0900_get_standard(fe, 0) ==
1942 STV0900_DVBS1_STANDARD) &&
1943 (stv0900_get_standard(fe, 1) ==
1944 STV0900_DVBS1_STANDARD)) {
ce45264e 1945 msleep(20);
a3a4f7e1 1946 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e 1947 } else {
a3a4f7e1 1948 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e 1949 msleep(3);
a3a4f7e1
IL		 1950 stv0900_write_bits(intp, RST_HWARE, 1);
1951 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e 1952 }
a3a4f7e1
IL		 1953
1954 } else if (intp->chip_id >= 0x20) {
1955 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e 1956 msleep(3);
a3a4f7e1
IL		 1957 stv0900_write_bits(intp, RST_HWARE, 1);
1958 stv0900_write_bits(intp, RST_HWARE, 0);
ce45264e
IL		 1959 }
1960
a3a4f7e1
IL		 1961 if (stv0900_wait_for_lock(intp, demod,
1962 fec_timeout, fec_timeout) == TRUE) {
ce45264e 1963 lock = TRUE;
a3a4f7e1
IL		 1964 intp->result[demod].locked = TRUE;
1965 if (intp->result[demod].standard ==
1966 STV0900_DVBS2_STANDARD) {
1967 stv0900_set_dvbs2_rolloff(intp, demod);
1968 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1969 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
1970 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1971 } else {
1972 stv0900_write_reg(intp, ERRCTRL1, 0x75);
ce45264e 1973 }
a3a4f7e1
IL		 1974
1975 stv0900_write_reg(intp, FBERCPT4, 0);
1976 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
ce45264e
IL		 1977 } else {
1978 lock = FALSE;
1979 signal_type = STV0900_NODATA;
a3a4f7e1
IL		 1980 no_signal = stv0900_check_signal_presence(intp, demod);
1981
1982 intp->result[demod].locked = FALSE;
ce45264e
IL		 1983 }
1984 }
1985
a3a4f7e1
IL		 1986 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
1987 return signal_type;
ce45264e 1988
a3a4f7e1
IL		 1989 if (intp->chip_id > 0x11) {
1990 intp->result[demod].locked = FALSE;
1991 return signal_type;
ce45264e
IL		 1992 }
1993
a3a4f7e1
IL		 1994 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
1995 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
1996 signal_type = stv0900_dvbs1_acq_workaround(fe);
1997
ce45264e
IL		 1998 return signal_type;
1999}
2000
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