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V4L/DVB (13986): [STV090x] Disable I2C gate on error
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb / frontends / stv090x.c
CommitLineData
e415c689
MA		 1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/mutex.h>
27
28#include <linux/dvb/frontend.h>
29#include "dvb_frontend.h"
30
31#include "stv6110x.h" /* for demodulator internal modes */
32
33#include "stv090x_reg.h"
34#include "stv090x.h"
35#include "stv090x_priv.h"
36
37static unsigned int verbose;
38module_param(verbose, int, 0644);
39
97f7a2ae
AR		 40/* internal params node */
41struct stv090x_dev {
42 /* pointer for internal params, one for each pair of demods */
43 struct stv090x_internal *internal;
44 struct stv090x_dev *next_dev;
45};
46
47/* first internal params */
48static struct stv090x_dev *stv090x_first_dev;
49
50/* find chip by i2c adapter and i2c address */
51static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
52 u8 i2c_addr)
53{
54 struct stv090x_dev *temp_dev = stv090x_first_dev;
55
56 /*
57 Search of the last stv0900 chip or
58 find it by i2c adapter and i2c address */
59 while ((temp_dev != NULL) &&
60 ((temp_dev->internal->i2c_adap != i2c_adap) ||
61 (temp_dev->internal->i2c_addr != i2c_addr))) {
62
63 temp_dev = temp_dev->next_dev;
64 }
65
66 return temp_dev;
67}
68
69/* deallocating chip */
70static void remove_dev(struct stv090x_internal *internal)
71{
72 struct stv090x_dev *prev_dev = stv090x_first_dev;
73 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
74 internal->i2c_addr);
75
76 if (del_dev != NULL) {
77 if (del_dev == stv090x_first_dev) {
78 stv090x_first_dev = del_dev->next_dev;
79 } else {
80 while (prev_dev->next_dev != del_dev)
81 prev_dev = prev_dev->next_dev;
82
83 prev_dev->next_dev = del_dev->next_dev;
84 }
85
86 kfree(del_dev);
87 }
88}
89
90/* allocating new chip */
91static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
92{
93 struct stv090x_dev *new_dev;
94 struct stv090x_dev *temp_dev;
95
96 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
97 if (new_dev != NULL) {
98 new_dev->internal = internal;
99 new_dev->next_dev = NULL;
100
101 /* append to list */
102 if (stv090x_first_dev == NULL) {
103 stv090x_first_dev = new_dev;
104 } else {
105 temp_dev = stv090x_first_dev;
106 while (temp_dev->next_dev != NULL)
107 temp_dev = temp_dev->next_dev;
108
109 temp_dev->next_dev = new_dev;
110 }
111 }
112
113 return new_dev;
114}
115
e415c689
MA		 116
117/* DVBS1 and DSS C/N Lookup table */
118static const struct stv090x_tab stv090x_s1cn_tab[] = {
119 { 0, 8917 }, /* 0.0dB */
120 { 5, 8801 }, /* 0.5dB */
121 { 10, 8667 }, /* 1.0dB */
122 { 15, 8522 }, /* 1.5dB */
123 { 20, 8355 }, /* 2.0dB */
124 { 25, 8175 }, /* 2.5dB */
125 { 30, 7979 }, /* 3.0dB */
126 { 35, 7763 }, /* 3.5dB */
127 { 40, 7530 }, /* 4.0dB */
128 { 45, 7282 }, /* 4.5dB */
129 { 50, 7026 }, /* 5.0dB */
130 { 55, 6781 }, /* 5.5dB */
131 { 60, 6514 }, /* 6.0dB */
132 { 65, 6241 }, /* 6.5dB */
133 { 70, 5965 }, /* 7.0dB */
134 { 75, 5690 }, /* 7.5dB */
135 { 80, 5424 }, /* 8.0dB */
136 { 85, 5161 }, /* 8.5dB */
137 { 90, 4902 }, /* 9.0dB */
138 { 95, 4654 }, /* 9.5dB */
139 { 100, 4417 }, /* 10.0dB */
140 { 105, 4186 }, /* 10.5dB */
141 { 110, 3968 }, /* 11.0dB */
142 { 115, 3757 }, /* 11.5dB */
143 { 120, 3558 }, /* 12.0dB */
144 { 125, 3366 }, /* 12.5dB */
145 { 130, 3185 }, /* 13.0dB */
146 { 135, 3012 }, /* 13.5dB */
147 { 140, 2850 }, /* 14.0dB */
148 { 145, 2698 }, /* 14.5dB */
149 { 150, 2550 }, /* 15.0dB */
150 { 160, 2283 }, /* 16.0dB */
151 { 170, 2042 }, /* 17.0dB */
152 { 180, 1827 }, /* 18.0dB */
153 { 190, 1636 }, /* 19.0dB */
154 { 200, 1466 }, /* 20.0dB */
155 { 210, 1315 }, /* 21.0dB */
156 { 220, 1181 }, /* 22.0dB */
157 { 230, 1064 }, /* 23.0dB */
158 { 240, 960 }, /* 24.0dB */
159 { 250, 869 }, /* 25.0dB */
160 { 260, 792 }, /* 26.0dB */
161 { 270, 724 }, /* 27.0dB */
162 { 280, 665 }, /* 28.0dB */
163 { 290, 616 }, /* 29.0dB */
164 { 300, 573 }, /* 30.0dB */
165 { 310, 537 }, /* 31.0dB */
166 { 320, 507 }, /* 32.0dB */
167 { 330, 483 }, /* 33.0dB */
168 { 400, 398 }, /* 40.0dB */
169 { 450, 381 }, /* 45.0dB */
170 { 500, 377 } /* 50.0dB */
171};
172
173/* DVBS2 C/N Lookup table */
174static const struct stv090x_tab stv090x_s2cn_tab[] = {
175 { -30, 13348 }, /* -3.0dB */
176 { -20, 12640 }, /* -2d.0B */
177 { -10, 11883 }, /* -1.0dB */
178 { 0, 11101 }, /* -0.0dB */
179 { 5, 10718 }, /* 0.5dB */
180 { 10, 10339 }, /* 1.0dB */
181 { 15, 9947 }, /* 1.5dB */
182 { 20, 9552 }, /* 2.0dB */
183 { 25, 9183 }, /* 2.5dB */
184 { 30, 8799 }, /* 3.0dB */
185 { 35, 8422 }, /* 3.5dB */
186 { 40, 8062 }, /* 4.0dB */
187 { 45, 7707 }, /* 4.5dB */
188 { 50, 7353 }, /* 5.0dB */
189 { 55, 7025 }, /* 5.5dB */
190 { 60, 6684 }, /* 6.0dB */
191 { 65, 6331 }, /* 6.5dB */
192 { 70, 6036 }, /* 7.0dB */
193 { 75, 5727 }, /* 7.5dB */
194 { 80, 5437 }, /* 8.0dB */
195 { 85, 5164 }, /* 8.5dB */
196 { 90, 4902 }, /* 9.0dB */
197 { 95, 4653 }, /* 9.5dB */
198 { 100, 4408 }, /* 10.0dB */
199 { 105, 4187 }, /* 10.5dB */
200 { 110, 3961 }, /* 11.0dB */
201 { 115, 3751 }, /* 11.5dB */
202 { 120, 3558 }, /* 12.0dB */
203 { 125, 3368 }, /* 12.5dB */
204 { 130, 3191 }, /* 13.0dB */
205 { 135, 3017 }, /* 13.5dB */
206 { 140, 2862 }, /* 14.0dB */
207 { 145, 2710 }, /* 14.5dB */
208 { 150, 2565 }, /* 15.0dB */
209 { 160, 2300 }, /* 16.0dB */
210 { 170, 2058 }, /* 17.0dB */
211 { 180, 1849 }, /* 18.0dB */
212 { 190, 1663 }, /* 19.0dB */
213 { 200, 1495 }, /* 20.0dB */
214 { 210, 1349 }, /* 21.0dB */
215 { 220, 1222 }, /* 22.0dB */
216 { 230, 1110 }, /* 23.0dB */
217 { 240, 1011 }, /* 24.0dB */
218 { 250, 925 }, /* 25.0dB */
219 { 260, 853 }, /* 26.0dB */
220 { 270, 789 }, /* 27.0dB */
221 { 280, 734 }, /* 28.0dB */
222 { 290, 690 }, /* 29.0dB */
223 { 300, 650 }, /* 30.0dB */
224 { 310, 619 }, /* 31.0dB */
225 { 320, 593 }, /* 32.0dB */
226 { 330, 571 }, /* 33.0dB */
227 { 400, 498 }, /* 40.0dB */
228 { 450, 484 }, /* 45.0dB */
229 { 500, 481 } /* 50.0dB */
230};
231
232/* RF level C/N lookup table */
233static const struct stv090x_tab stv090x_rf_tab[] = {
234 { -5, 0xcaa1 }, /* -5dBm */
235 { -10, 0xc229 }, /* -10dBm */
236 { -15, 0xbb08 }, /* -15dBm */
237 { -20, 0xb4bc }, /* -20dBm */
238 { -25, 0xad5a }, /* -25dBm */
239 { -30, 0xa298 }, /* -30dBm */
240 { -35, 0x98a8 }, /* -35dBm */
241 { -40, 0x8389 }, /* -40dBm */
242 { -45, 0x59be }, /* -45dBm */
243 { -50, 0x3a14 }, /* -50dBm */
244 { -55, 0x2d11 }, /* -55dBm */
245 { -60, 0x210d }, /* -60dBm */
246 { -65, 0xa14f }, /* -65dBm */
247 { -70, 0x07aa } /* -70dBm */
248};
249
250
251static struct stv090x_reg stv0900_initval[] = {
252
253 { STV090x_OUTCFG, 0x00 },
56571507 254 { STV090x_MODECFG, 0xff },
e415c689
MA		 255 { STV090x_AGCRF1CFG, 0x11 },
256 { STV090x_AGCRF2CFG, 0x13 },
56571507 257 { STV090x_TSGENERAL1X, 0x14 },
e415c689
MA		 258 { STV090x_TSTTNR2, 0x21 },
259 { STV090x_TSTTNR4, 0x21 },
260 { STV090x_P2_DISTXCTL, 0x22 },
261 { STV090x_P2_F22TX, 0xc0 },
262 { STV090x_P2_F22RX, 0xc0 },
263 { STV090x_P2_DISRXCTL, 0x00 },
264 { STV090x_P2_DMDCFGMD, 0xF9 },
265 { STV090x_P2_DEMOD, 0x08 },
266 { STV090x_P2_DMDCFG3, 0xc4 },
267 { STV090x_P2_CARFREQ, 0xed },
268 { STV090x_P2_LDT, 0xd0 },
269 { STV090x_P2_LDT2, 0xb8 },
270 { STV090x_P2_TMGCFG, 0xd2 },
271 { STV090x_P2_TMGTHRISE, 0x20 },
272 { STV090x_P1_TMGCFG, 0xd2 },
273
274 { STV090x_P2_TMGTHFALL, 0x00 },
275 { STV090x_P2_FECSPY, 0x88 },
276 { STV090x_P2_FSPYDATA, 0x3a },
277 { STV090x_P2_FBERCPT4, 0x00 },
278 { STV090x_P2_FSPYBER, 0x10 },
279 { STV090x_P2_ERRCTRL1, 0x35 },
280 { STV090x_P2_ERRCTRL2, 0xc1 },
281 { STV090x_P2_CFRICFG, 0xf8 },
282 { STV090x_P2_NOSCFG, 0x1c },
56571507 283 { STV090x_P2_DMDTOM, 0x20 },
e415c689
MA		 284 { STV090x_P2_CORRELMANT, 0x70 },
285 { STV090x_P2_CORRELABS, 0x88 },
56571507 286 { STV090x_P2_AGC2O, 0x5b },
e415c689
MA		 287 { STV090x_P2_AGC2REF, 0x38 },
288 { STV090x_P2_CARCFG, 0xe4 },
289 { STV090x_P2_ACLC, 0x1A },
290 { STV090x_P2_BCLC, 0x09 },
291 { STV090x_P2_CARHDR, 0x08 },
292 { STV090x_P2_KREFTMG, 0xc1 },
293 { STV090x_P2_SFRUPRATIO, 0xf0 },
294 { STV090x_P2_SFRLOWRATIO, 0x70 },
295 { STV090x_P2_SFRSTEP, 0x58 },
296 { STV090x_P2_TMGCFG2, 0x01 },
297 { STV090x_P2_CAR2CFG, 0x26 },
298 { STV090x_P2_BCLC2S2Q, 0x86 },
299 { STV090x_P2_BCLC2S28, 0x86 },
300 { STV090x_P2_SMAPCOEF7, 0x77 },
301 { STV090x_P2_SMAPCOEF6, 0x85 },
302 { STV090x_P2_SMAPCOEF5, 0x77 },
303 { STV090x_P2_TSCFGL, 0x20 },
304 { STV090x_P2_DMDCFG2, 0x3b },
305 { STV090x_P2_MODCODLST0, 0xff },
306 { STV090x_P2_MODCODLST1, 0xff },
307 { STV090x_P2_MODCODLST2, 0xff },
308 { STV090x_P2_MODCODLST3, 0xff },
309 { STV090x_P2_MODCODLST4, 0xff },
310 { STV090x_P2_MODCODLST5, 0xff },
311 { STV090x_P2_MODCODLST6, 0xff },
312 { STV090x_P2_MODCODLST7, 0xcc },
313 { STV090x_P2_MODCODLST8, 0xcc },
314 { STV090x_P2_MODCODLST9, 0xcc },
315 { STV090x_P2_MODCODLSTA, 0xcc },
316 { STV090x_P2_MODCODLSTB, 0xcc },
317 { STV090x_P2_MODCODLSTC, 0xcc },
318 { STV090x_P2_MODCODLSTD, 0xcc },
319 { STV090x_P2_MODCODLSTE, 0xcc },
320 { STV090x_P2_MODCODLSTF, 0xcf },
321 { STV090x_P1_DISTXCTL, 0x22 },
322 { STV090x_P1_F22TX, 0xc0 },
323 { STV090x_P1_F22RX, 0xc0 },
324 { STV090x_P1_DISRXCTL, 0x00 },
325 { STV090x_P1_DMDCFGMD, 0xf9 },
326 { STV090x_P1_DEMOD, 0x08 },
327 { STV090x_P1_DMDCFG3, 0xc4 },
56571507 328 { STV090x_P1_DMDTOM, 0x20 },
e415c689
MA		 329 { STV090x_P1_CARFREQ, 0xed },
330 { STV090x_P1_LDT, 0xd0 },
331 { STV090x_P1_LDT2, 0xb8 },
332 { STV090x_P1_TMGCFG, 0xd2 },
333 { STV090x_P1_TMGTHRISE, 0x20 },
334 { STV090x_P1_TMGTHFALL, 0x00 },
335 { STV090x_P1_SFRUPRATIO, 0xf0 },
336 { STV090x_P1_SFRLOWRATIO, 0x70 },
337 { STV090x_P1_TSCFGL, 0x20 },
338 { STV090x_P1_FECSPY, 0x88 },
339 { STV090x_P1_FSPYDATA, 0x3a },
340 { STV090x_P1_FBERCPT4, 0x00 },
341 { STV090x_P1_FSPYBER, 0x10 },
342 { STV090x_P1_ERRCTRL1, 0x35 },
343 { STV090x_P1_ERRCTRL2, 0xc1 },
344 { STV090x_P1_CFRICFG, 0xf8 },
345 { STV090x_P1_NOSCFG, 0x1c },
346 { STV090x_P1_CORRELMANT, 0x70 },
347 { STV090x_P1_CORRELABS, 0x88 },
56571507 348 { STV090x_P1_AGC2O, 0x5b },
e415c689
MA		 349 { STV090x_P1_AGC2REF, 0x38 },
350 { STV090x_P1_CARCFG, 0xe4 },
351 { STV090x_P1_ACLC, 0x1A },
352 { STV090x_P1_BCLC, 0x09 },
353 { STV090x_P1_CARHDR, 0x08 },
354 { STV090x_P1_KREFTMG, 0xc1 },
355 { STV090x_P1_SFRSTEP, 0x58 },
356 { STV090x_P1_TMGCFG2, 0x01 },
357 { STV090x_P1_CAR2CFG, 0x26 },
358 { STV090x_P1_BCLC2S2Q, 0x86 },
359 { STV090x_P1_BCLC2S28, 0x86 },
360 { STV090x_P1_SMAPCOEF7, 0x77 },
361 { STV090x_P1_SMAPCOEF6, 0x85 },
362 { STV090x_P1_SMAPCOEF5, 0x77 },
363 { STV090x_P1_DMDCFG2, 0x3b },
364 { STV090x_P1_MODCODLST0, 0xff },
365 { STV090x_P1_MODCODLST1, 0xff },
366 { STV090x_P1_MODCODLST2, 0xff },
367 { STV090x_P1_MODCODLST3, 0xff },
368 { STV090x_P1_MODCODLST4, 0xff },
369 { STV090x_P1_MODCODLST5, 0xff },
370 { STV090x_P1_MODCODLST6, 0xff },
371 { STV090x_P1_MODCODLST7, 0xcc },
372 { STV090x_P1_MODCODLST8, 0xcc },
373 { STV090x_P1_MODCODLST9, 0xcc },
374 { STV090x_P1_MODCODLSTA, 0xcc },
375 { STV090x_P1_MODCODLSTB, 0xcc },
376 { STV090x_P1_MODCODLSTC, 0xcc },
377 { STV090x_P1_MODCODLSTD, 0xcc },
378 { STV090x_P1_MODCODLSTE, 0xcc },
379 { STV090x_P1_MODCODLSTF, 0xcf },
380 { STV090x_GENCFG, 0x1d },
381 { STV090x_NBITER_NF4, 0x37 },
382 { STV090x_NBITER_NF5, 0x29 },
383 { STV090x_NBITER_NF6, 0x37 },
384 { STV090x_NBITER_NF7, 0x33 },
385 { STV090x_NBITER_NF8, 0x31 },
386 { STV090x_NBITER_NF9, 0x2f },
387 { STV090x_NBITER_NF10, 0x39 },
388 { STV090x_NBITER_NF11, 0x3a },
389 { STV090x_NBITER_NF12, 0x29 },
390 { STV090x_NBITER_NF13, 0x37 },
391 { STV090x_NBITER_NF14, 0x33 },
392 { STV090x_NBITER_NF15, 0x2f },
393 { STV090x_NBITER_NF16, 0x39 },
394 { STV090x_NBITER_NF17, 0x3a },
395 { STV090x_NBITERNOERR, 0x04 },
396 { STV090x_GAINLLR_NF4, 0x0C },
397 { STV090x_GAINLLR_NF5, 0x0F },
398 { STV090x_GAINLLR_NF6, 0x11 },
399 { STV090x_GAINLLR_NF7, 0x14 },
400 { STV090x_GAINLLR_NF8, 0x17 },
401 { STV090x_GAINLLR_NF9, 0x19 },
402 { STV090x_GAINLLR_NF10, 0x20 },
403 { STV090x_GAINLLR_NF11, 0x21 },
404 { STV090x_GAINLLR_NF12, 0x0D },
405 { STV090x_GAINLLR_NF13, 0x0F },
406 { STV090x_GAINLLR_NF14, 0x13 },
407 { STV090x_GAINLLR_NF15, 0x1A },
408 { STV090x_GAINLLR_NF16, 0x1F },
409 { STV090x_GAINLLR_NF17, 0x21 },
56571507 410 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 411 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
412 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
413 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
414 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
415};
416
417static struct stv090x_reg stv0903_initval[] = {
418 { STV090x_OUTCFG, 0x00 },
419 { STV090x_AGCRF1CFG, 0x11 },
420 { STV090x_STOPCLK1, 0x48 },
421 { STV090x_STOPCLK2, 0x14 },
422 { STV090x_TSTTNR1, 0x27 },
423 { STV090x_TSTTNR2, 0x21 },
424 { STV090x_P1_DISTXCTL, 0x22 },
425 { STV090x_P1_F22TX, 0xc0 },
426 { STV090x_P1_F22RX, 0xc0 },
427 { STV090x_P1_DISRXCTL, 0x00 },
428 { STV090x_P1_DMDCFGMD, 0xF9 },
429 { STV090x_P1_DEMOD, 0x08 },
430 { STV090x_P1_DMDCFG3, 0xc4 },
431 { STV090x_P1_CARFREQ, 0xed },
432 { STV090x_P1_TNRCFG2, 0x82 },
433 { STV090x_P1_LDT, 0xd0 },
434 { STV090x_P1_LDT2, 0xb8 },
435 { STV090x_P1_TMGCFG, 0xd2 },
436 { STV090x_P1_TMGTHRISE, 0x20 },
437 { STV090x_P1_TMGTHFALL, 0x00 },
438 { STV090x_P1_SFRUPRATIO, 0xf0 },
439 { STV090x_P1_SFRLOWRATIO, 0x70 },
440 { STV090x_P1_TSCFGL, 0x20 },
441 { STV090x_P1_FECSPY, 0x88 },
442 { STV090x_P1_FSPYDATA, 0x3a },
443 { STV090x_P1_FBERCPT4, 0x00 },
444 { STV090x_P1_FSPYBER, 0x10 },
445 { STV090x_P1_ERRCTRL1, 0x35 },
446 { STV090x_P1_ERRCTRL2, 0xc1 },
447 { STV090x_P1_CFRICFG, 0xf8 },
448 { STV090x_P1_NOSCFG, 0x1c },
56571507 449 { STV090x_P1_DMDTOM, 0x20 },
e415c689
MA		 450 { STV090x_P1_CORRELMANT, 0x70 },
451 { STV090x_P1_CORRELABS, 0x88 },
56571507
MA		 452 { STV090x_P1_AGC2O, 0x5b },
453 { STV090x_P1_AGC2REF, 0x38 },
e415c689
MA		 454 { STV090x_P1_CARCFG, 0xe4 },
455 { STV090x_P1_ACLC, 0x1A },
56571507 456 { STV090x_P1_BCLC, 0x09 },
e415c689
MA		 457 { STV090x_P1_CARHDR, 0x08 },
458 { STV090x_P1_KREFTMG, 0xc1 },
459 { STV090x_P1_SFRSTEP, 0x58 },
460 { STV090x_P1_TMGCFG2, 0x01 },
461 { STV090x_P1_CAR2CFG, 0x26 },
462 { STV090x_P1_BCLC2S2Q, 0x86 },
463 { STV090x_P1_BCLC2S28, 0x86 },
464 { STV090x_P1_SMAPCOEF7, 0x77 },
465 { STV090x_P1_SMAPCOEF6, 0x85 },
466 { STV090x_P1_SMAPCOEF5, 0x77 },
467 { STV090x_P1_DMDCFG2, 0x3b },
468 { STV090x_P1_MODCODLST0, 0xff },
469 { STV090x_P1_MODCODLST1, 0xff },
470 { STV090x_P1_MODCODLST2, 0xff },
471 { STV090x_P1_MODCODLST3, 0xff },
472 { STV090x_P1_MODCODLST4, 0xff },
473 { STV090x_P1_MODCODLST5, 0xff },
474 { STV090x_P1_MODCODLST6, 0xff },
475 { STV090x_P1_MODCODLST7, 0xcc },
476 { STV090x_P1_MODCODLST8, 0xcc },
477 { STV090x_P1_MODCODLST9, 0xcc },
478 { STV090x_P1_MODCODLSTA, 0xcc },
479 { STV090x_P1_MODCODLSTB, 0xcc },
480 { STV090x_P1_MODCODLSTC, 0xcc },
481 { STV090x_P1_MODCODLSTD, 0xcc },
482 { STV090x_P1_MODCODLSTE, 0xcc },
483 { STV090x_P1_MODCODLSTF, 0xcf },
484 { STV090x_GENCFG, 0x1c },
485 { STV090x_NBITER_NF4, 0x37 },
486 { STV090x_NBITER_NF5, 0x29 },
487 { STV090x_NBITER_NF6, 0x37 },
488 { STV090x_NBITER_NF7, 0x33 },
489 { STV090x_NBITER_NF8, 0x31 },
490 { STV090x_NBITER_NF9, 0x2f },
491 { STV090x_NBITER_NF10, 0x39 },
492 { STV090x_NBITER_NF11, 0x3a },
493 { STV090x_NBITER_NF12, 0x29 },
494 { STV090x_NBITER_NF13, 0x37 },
495 { STV090x_NBITER_NF14, 0x33 },
496 { STV090x_NBITER_NF15, 0x2f },
497 { STV090x_NBITER_NF16, 0x39 },
498 { STV090x_NBITER_NF17, 0x3a },
499 { STV090x_NBITERNOERR, 0x04 },
500 { STV090x_GAINLLR_NF4, 0x0C },
501 { STV090x_GAINLLR_NF5, 0x0F },
502 { STV090x_GAINLLR_NF6, 0x11 },
503 { STV090x_GAINLLR_NF7, 0x14 },
504 { STV090x_GAINLLR_NF8, 0x17 },
505 { STV090x_GAINLLR_NF9, 0x19 },
506 { STV090x_GAINLLR_NF10, 0x20 },
507 { STV090x_GAINLLR_NF11, 0x21 },
508 { STV090x_GAINLLR_NF12, 0x0D },
509 { STV090x_GAINLLR_NF13, 0x0F },
510 { STV090x_GAINLLR_NF14, 0x13 },
511 { STV090x_GAINLLR_NF15, 0x1A },
512 { STV090x_GAINLLR_NF16, 0x1F },
513 { STV090x_GAINLLR_NF17, 0x21 },
56571507 514 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 515 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
516 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
517};
518
519static struct stv090x_reg stv0900_cut20_val[] = {
520
521 { STV090x_P2_DMDCFG3, 0xe8 },
56571507 522 { STV090x_P2_DMDCFG4, 0x10 },
e415c689
MA		 523 { STV090x_P2_CARFREQ, 0x38 },
524 { STV090x_P2_CARHDR, 0x20 },
525 { STV090x_P2_KREFTMG, 0x5a },
526 { STV090x_P2_SMAPCOEF7, 0x06 },
527 { STV090x_P2_SMAPCOEF6, 0x00 },
528 { STV090x_P2_SMAPCOEF5, 0x04 },
529 { STV090x_P2_NOSCFG, 0x0c },
530 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 531 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 532 { STV090x_P1_CARFREQ, 0x38 },
533 { STV090x_P1_CARHDR, 0x20 },
534 { STV090x_P1_KREFTMG, 0x5a },
535 { STV090x_P1_SMAPCOEF7, 0x06 },
536 { STV090x_P1_SMAPCOEF6, 0x00 },
537 { STV090x_P1_SMAPCOEF5, 0x04 },
538 { STV090x_P1_NOSCFG, 0x0c },
539 { STV090x_GAINLLR_NF4, 0x21 },
540 { STV090x_GAINLLR_NF5, 0x21 },
541 { STV090x_GAINLLR_NF6, 0x20 },
542 { STV090x_GAINLLR_NF7, 0x1F },
543 { STV090x_GAINLLR_NF8, 0x1E },
544 { STV090x_GAINLLR_NF9, 0x1E },
545 { STV090x_GAINLLR_NF10, 0x1D },
546 { STV090x_GAINLLR_NF11, 0x1B },
547 { STV090x_GAINLLR_NF12, 0x20 },
548 { STV090x_GAINLLR_NF13, 0x20 },
549 { STV090x_GAINLLR_NF14, 0x20 },
550 { STV090x_GAINLLR_NF15, 0x20 },
551 { STV090x_GAINLLR_NF16, 0x20 },
552 { STV090x_GAINLLR_NF17, 0x21 },
553};
554
555static struct stv090x_reg stv0903_cut20_val[] = {
556 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 557 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 558 { STV090x_P1_CARFREQ, 0x38 },
559 { STV090x_P1_CARHDR, 0x20 },
560 { STV090x_P1_KREFTMG, 0x5a },
561 { STV090x_P1_SMAPCOEF7, 0x06 },
562 { STV090x_P1_SMAPCOEF6, 0x00 },
563 { STV090x_P1_SMAPCOEF5, 0x04 },
564 { STV090x_P1_NOSCFG, 0x0c },
565 { STV090x_GAINLLR_NF4, 0x21 },
566 { STV090x_GAINLLR_NF5, 0x21 },
567 { STV090x_GAINLLR_NF6, 0x20 },
568 { STV090x_GAINLLR_NF7, 0x1F },
569 { STV090x_GAINLLR_NF8, 0x1E },
570 { STV090x_GAINLLR_NF9, 0x1E },
571 { STV090x_GAINLLR_NF10, 0x1D },
572 { STV090x_GAINLLR_NF11, 0x1B },
573 { STV090x_GAINLLR_NF12, 0x20 },
574 { STV090x_GAINLLR_NF13, 0x20 },
575 { STV090x_GAINLLR_NF14, 0x20 },
576 { STV090x_GAINLLR_NF15, 0x20 },
577 { STV090x_GAINLLR_NF16, 0x20 },
578 { STV090x_GAINLLR_NF17, 0x21 }
579};
580
e415c689
MA		 581/* Cut 2.0 Long Frame Tracking CR loop */
582static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
583 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
584 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
585 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
586 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
587 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
588 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
589 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
590 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
593 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
594 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
595 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
596 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
597 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
598};
599
27d40321
MA		 600/* Cut 3.0 Long Frame Tracking CR loop */
601static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
602 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
603 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
604 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
605 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
606 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
607 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
608 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
609 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
610 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
611 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
612 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
613 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
614 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
615 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
616 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
617};
e415c689
MA		 618
619/* Cut 2.0 Long Frame Tracking CR Loop */
620static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
621 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
622 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
623 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
624 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
625 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
626 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
627 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
628 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
629 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
630 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
631 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
632 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
633};
634
27d40321
MA		 635/* Cut 3.0 Long Frame Tracking CR Loop */
636static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
637 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
638 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
639 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
640 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
641 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
642 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
643 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
644 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
645 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
646 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
647 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
648 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
649};
e415c689
MA		 650
651static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
652 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
653 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
654 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
655 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
656};
657
27d40321
MA		 658static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
659 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
660 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
661 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
662 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
663};
e415c689 664
27d40321
MA		 665/* Cut 2.0 Short Frame Tracking CR Loop */
666static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
667 /* MODCOD 2M 5M 10M 20M 30M */
668 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
669 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
670 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
671 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
e415c689
MA		 672};
673
27d40321
MA		 674/* Cut 3.0 Short Frame Tracking CR Loop */
675static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
676 /* MODCOD 2M 5M 10M 20M 30M */
677 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
678 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
679 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
680 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
681};
e415c689
MA		 682
683static inline s32 comp2(s32 __x, s32 __width)
684{
685 if (__width == 32)
686 return __x;
687 else
688 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
689}
690
691static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
692{
693 const struct stv090x_config *config = state->config;
694 int ret;
695
696 u8 b0[] = { reg >> 8, reg & 0xff };
697 u8 buf;
698
699 struct i2c_msg msg[] = {
700 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
701 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
702 };
703
704 ret = i2c_transfer(state->i2c, msg, 2);
705 if (ret != 2) {
706 if (ret != -ERESTARTSYS)
707 dprintk(FE_ERROR, 1,
708 "Read error, Reg=[0x%02x], Status=%d",
709 reg, ret);
710
711 return ret < 0 ? ret : -EREMOTEIO;
712 }
713 if (unlikely(*state->verbose >= FE_DEBUGREG))
714 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
715 reg, buf);
716
717 return (unsigned int) buf;
718}
719
720static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
721{
722 const struct stv090x_config *config = state->config;
723 int ret;
724 u8 buf[2 + count];
725 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
726
727 buf[0] = reg >> 8;
728 buf[1] = reg & 0xff;
729 memcpy(&buf[2], data, count);
730
731 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
732 int i;
733
734 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
735 for (i = 0; i < count; i++)
736 printk(" %02x", data[i]);
737 printk("\n");
738 }
739
740 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
741 if (ret != 1) {
742 if (ret != -ERESTARTSYS)
743 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
744 reg, data[0], count, ret);
745 return ret < 0 ? ret : -EREMOTEIO;
746 }
747
748 return 0;
749}
750
751static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
752{
753 return stv090x_write_regs(state, reg, &data, 1);
754}
755
756static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
757{
758 struct stv090x_state *state = fe->demodulator_priv;
759 u32 reg;
760
96506a50
AR		 761 if (enable)
762 mutex_lock(&state->internal->tuner_lock);
763
e415c689 764 reg = STV090x_READ_DEMOD(state, I2CRPT);
e415c689 765 if (enable) {
017eb038 766 dprintk(FE_DEBUG, 1, "Enable Gate");
e415c689
MA		 767 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
768 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
769 goto err;
770
771 } else {
017eb038 772 dprintk(FE_DEBUG, 1, "Disable Gate");
e415c689
MA		 773 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
774 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
775 goto err;
776 }
96506a50
AR		 777
778 if (!enable)
779 mutex_unlock(&state->internal->tuner_lock);
780
e415c689
MA		 781 return 0;
782err:
783 dprintk(FE_ERROR, 1, "I/O error");
96506a50 784 mutex_unlock(&state->internal->tuner_lock);
e415c689
MA		 785 return -1;
786}
787
788static void stv090x_get_lock_tmg(struct stv090x_state *state)
789{
790 switch (state->algo) {
791 case STV090x_BLIND_SEARCH:
792 dprintk(FE_DEBUG, 1, "Blind Search");
793 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
794 state->DemodTimeout = 1500;
795 state->FecTimeout = 400;
796 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
797 state->DemodTimeout = 1000;
798 state->FecTimeout = 300;
799 } else { /*SR >20Msps*/
800 state->DemodTimeout = 700;
801 state->FecTimeout = 100;
802 }
803 break;
804
805 case STV090x_COLD_SEARCH:
806 case STV090x_WARM_SEARCH:
807 default:
808 dprintk(FE_DEBUG, 1, "Normal Search");
809 if (state->srate <= 1000000) { /*SR <=1Msps*/
810 state->DemodTimeout = 4500;
811 state->FecTimeout = 1700;
812 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
813 state->DemodTimeout = 2500;
814 state->FecTimeout = 1100;
815 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
816 state->DemodTimeout = 1000;
817 state->FecTimeout = 550;
818 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
819 state->DemodTimeout = 700;
820 state->FecTimeout = 250;
821 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
822 state->DemodTimeout = 400;
823 state->FecTimeout = 130;
824 } else { /*SR >20Msps*/
825 state->DemodTimeout = 300;
826 state->FecTimeout = 100;
827 }
828 break;
829 }
830
831 if (state->algo == STV090x_WARM_SEARCH)
832 state->DemodTimeout /= 2;
833}
834
835static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
836{
837 u32 sym;
838
15bb366e
MA		 839 if (srate > 60000000) {
840 sym = (srate << 4); /* SR * 2^16 / master_clk */
97f7a2ae 841 sym /= (state->internal->mclk >> 12);
15bb366e
MA		 842 } else if (srate > 6000000) {
843 sym = (srate << 6);
97f7a2ae 844 sym /= (state->internal->mclk >> 10);
e415c689 845 } else {
15bb366e 846 sym = (srate << 9);
97f7a2ae 847 sym /= (state->internal->mclk >> 7);
e415c689
MA		 848 }
849
15bb366e 850 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
e415c689
MA		 851 goto err;
852 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
853 goto err;
15bb366e 854
e415c689
MA		 855 return 0;
856err:
857 dprintk(FE_ERROR, 1, "I/O error");
858 return -1;
859}
860
861static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
862{
863 u32 sym;
864
865 srate = 105 * (srate / 100);
15bb366e
MA		 866 if (srate > 60000000) {
867 sym = (srate << 4); /* SR * 2^16 / master_clk */
97f7a2ae 868 sym /= (state->internal->mclk >> 12);
15bb366e
MA		 869 } else if (srate > 6000000) {
870 sym = (srate << 6);
97f7a2ae 871 sym /= (state->internal->mclk >> 10);
e415c689 872 } else {
15bb366e 873 sym = (srate << 9);
97f7a2ae 874 sym /= (state->internal->mclk >> 7);
e415c689 875 }
15bb366e
MA		 876
877 if (sym < 0x7fff) {
878 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
879 goto err;
880 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
881 goto err;
882 } else {
883 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
884 goto err;
885 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
886 goto err;
887 }
888
e415c689
MA		 889 return 0;
890err:
891 dprintk(FE_ERROR, 1, "I/O error");
892 return -1;
893}
894
895static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
896{
897 u32 sym;
898
899 srate = 95 * (srate / 100);
15bb366e
MA		 900 if (srate > 60000000) {
901 sym = (srate << 4); /* SR * 2^16 / master_clk */
97f7a2ae 902 sym /= (state->internal->mclk >> 12);
15bb366e
MA		 903 } else if (srate > 6000000) {
904 sym = (srate << 6);
97f7a2ae 905 sym /= (state->internal->mclk >> 10);
e415c689 906 } else {
15bb366e 907 sym = (srate << 9);
97f7a2ae 908 sym /= (state->internal->mclk >> 7);
e415c689 909 }
15bb366e 910
b671a8d4 911 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
e415c689
MA		 912 goto err;
913 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
914 goto err;
915 return 0;
916err:
917 dprintk(FE_ERROR, 1, "I/O error");
918 return -1;
919}
920
4e58a682 921static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
e415c689 922{
4e58a682
AR		 923 u32 ro;
924
925 switch (rolloff) {
926 case STV090x_RO_20:
927 ro = 20;
928 break;
929 case STV090x_RO_25:
930 ro = 25;
931 break;
932 case STV090x_RO_35:
933 default:
934 ro = 35;
935 break;
936 }
937
938 return srate + (srate * ro) / 100;
e415c689
MA		 939}
940
941static int stv090x_set_vit_thacq(struct stv090x_state *state)
942{
943 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
944 goto err;
945 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
946 goto err;
947 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
948 goto err;
949 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
950 goto err;
951 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
952 goto err;
953 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
954 goto err;
955 return 0;
956err:
957 dprintk(FE_ERROR, 1, "I/O error");
958 return -1;
959}
960
961static int stv090x_set_vit_thtracq(struct stv090x_state *state)
962{
963 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
964 goto err;
965 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
966 goto err;
967 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
968 goto err;
969 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
970 goto err;
971 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
972 goto err;
973 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
974 goto err;
975 return 0;
976err:
977 dprintk(FE_ERROR, 1, "I/O error");
978 return -1;
979}
980
981static int stv090x_set_viterbi(struct stv090x_state *state)
982{
983 switch (state->search_mode) {
984 case STV090x_SEARCH_AUTO:
985 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
986 goto err;
987 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
988 goto err;
989 break;
990 case STV090x_SEARCH_DVBS1:
991 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
992 goto err;
993 switch (state->fec) {
994 case STV090x_PR12:
995 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
996 goto err;
997 break;
998
999 case STV090x_PR23:
1000 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1001 goto err;
1002 break;
1003
1004 case STV090x_PR34:
1005 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1006 goto err;
1007 break;
1008
1009 case STV090x_PR56:
1010 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1011 goto err;
1012 break;
1013
1014 case STV090x_PR78:
1015 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1016 goto err;
1017 break;
1018
1019 default:
1020 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1021 goto err;
1022 break;
1023 }
1024 break;
1025 case STV090x_SEARCH_DSS:
1026 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1027 goto err;
1028 switch (state->fec) {
1029 case STV090x_PR12:
1030 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1031 goto err;
1032 break;
1033
1034 case STV090x_PR23:
1035 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1036 goto err;
1037 break;
1038
1039 case STV090x_PR67:
1040 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1041 goto err;
1042 break;
1043
1044 default:
1045 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1046 goto err;
1047 break;
1048 }
1049 break;
1050 default:
1051 break;
1052 }
1053 return 0;
1054err:
1055 dprintk(FE_ERROR, 1, "I/O error");
1056 return -1;
1057}
1058
1059static int stv090x_stop_modcod(struct stv090x_state *state)
1060{
1061 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1062 goto err;
1063 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1064 goto err;
1065 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1066 goto err;
1067 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1068 goto err;
1069 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1070 goto err;
1071 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1072 goto err;
1073 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1074 goto err;
1075 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1076 goto err;
1077 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1078 goto err;
1079 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1080 goto err;
1081 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1082 goto err;
1083 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1084 goto err;
1085 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1086 goto err;
1087 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1088 goto err;
1089 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1090 goto err;
1091 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1092 goto err;
1093 return 0;
1094err:
1095 dprintk(FE_ERROR, 1, "I/O error");
1096 return -1;
1097}
1098
1099static int stv090x_activate_modcod(struct stv090x_state *state)
1100{
27d40321
MA		 1101 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1102 goto err;
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1104 goto err;
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1106 goto err;
1107 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1108 goto err;
1109 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1110 goto err;
1111 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1112 goto err;
1113 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1114 goto err;
1115 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1116 goto err;
1117 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1118 goto err;
1119 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1120 goto err;
1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1122 goto err;
1123 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1124 goto err;
1125 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1126 goto err;
1127 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1128 goto err;
1129 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1130 goto err;
1131 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1132 goto err;
e415c689 1133
27d40321
MA		 1134 return 0;
1135err:
1136 dprintk(FE_ERROR, 1, "I/O error");
1137 return -1;
1138}
1139
1140static int stv090x_activate_modcod_single(struct stv090x_state *state)
1141{
1142
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1144 goto err;
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1146 goto err;
1147 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1148 goto err;
1149 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1150 goto err;
1151 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1152 goto err;
1153 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1154 goto err;
1155 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1156 goto err;
1157 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1158 goto err;
1159 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1160 goto err;
1161 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1162 goto err;
1163 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1164 goto err;
1165 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1166 goto err;
1167 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1168 goto err;
1169 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1170 goto err;
1171 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1172 goto err;
1173 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1174 goto err;
e415c689 1175
e415c689 1176 return 0;
27d40321 1177
e415c689
MA		 1178err:
1179 dprintk(FE_ERROR, 1, "I/O error");
1180 return -1;
1181}
1182
1183static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1184{
1185 u32 reg;
1186
1187 switch (state->demod) {
1188 case STV090x_DEMODULATOR_0:
97f7a2ae 1189 mutex_lock(&state->internal->demod_lock);
e415c689
MA		 1190 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1191 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1192 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1193 goto err;
97f7a2ae 1194 mutex_unlock(&state->internal->demod_lock);
e415c689
MA		 1195 break;
1196
1197 case STV090x_DEMODULATOR_1:
97f7a2ae 1198 mutex_lock(&state->internal->demod_lock);
e415c689
MA		 1199 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1200 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1201 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1202 goto err;
97f7a2ae 1203 mutex_unlock(&state->internal->demod_lock);
e415c689
MA		 1204 break;
1205
1206 default:
1207 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1208 break;
1209 }
1210 return 0;
1211err:
97f7a2ae 1212 mutex_unlock(&state->internal->demod_lock);
e415c689
MA		 1213 dprintk(FE_ERROR, 1, "I/O error");
1214 return -1;
1215}
1216
27d40321
MA		 1217static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1218{
97f7a2ae 1219 if (state->internal->dev_ver >= 0x30) {
27d40321
MA		 1220 /* Set ACLC BCLC optimised value vs SR */
1221 if (state->srate >= 15000000) {
1222 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1223 goto err;
1224 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1225 goto err;
1226 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1227 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1228 goto err;
1229 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1230 goto err;
1231 } else if (state->srate < 7000000) {
1232 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1233 goto err;
1234 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1235 goto err;
1236 }
1237
1238 } else {
1239 /* Cut 2.0 */
1240 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1241 goto err;
1242 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1243 goto err;
1244 }
1245 return 0;
1246err:
1247 dprintk(FE_ERROR, 1, "I/O error");
1248 return -1;
1249}
1250
e415c689
MA		 1251static int stv090x_delivery_search(struct stv090x_state *state)
1252{
1253 u32 reg;
1254
1255 switch (state->search_mode) {
1256 case STV090x_SEARCH_DVBS1:
1257 case STV090x_SEARCH_DSS:
1258 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1259 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1260 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1261 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1262 goto err;
1263
27d40321
MA		 1264 /* Activate Viterbi decoder in legacy search,
1265 * do not use FRESVIT1, might impact VITERBI2
1266 */
e415c689
MA		 1267 if (stv090x_vitclk_ctl(state, 0) < 0)
1268 goto err;
1269
27d40321 1270 if (stv090x_dvbs_track_crl(state) < 0)
e415c689 1271 goto err;
27d40321 1272
e415c689
MA		 1273 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1274 goto err;
1275
27d40321
MA		 1276 if (stv090x_set_vit_thacq(state) < 0)
1277 goto err;
1278 if (stv090x_set_viterbi(state) < 0)
1279 goto err;
e415c689
MA		 1280 break;
1281
1282 case STV090x_SEARCH_DVBS2:
1283 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1284 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1285 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1286 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1287 goto err;
1288 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1289 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1290 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1291 goto err;
1292
1293 if (stv090x_vitclk_ctl(state, 1) < 0)
1294 goto err;
1295
1296 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1297 goto err;
1298 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1299 goto err;
27d40321 1300
97f7a2ae 1301 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1302 /* enable S2 carrier loop */
1303 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1304 goto err;
1305 } else {
1306 /* > Cut 3: Stop carrier 3 */
1307 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1308 goto err;
1309 }
e415c689
MA		 1310
1311 if (state->demod_mode != STV090x_SINGLE) {
27d40321
MA		 1312 /* Cut 2: enable link during search */
1313 if (stv090x_activate_modcod(state) < 0)
1314 goto err;
1315 } else {
1316 /* Single demodulator
1317 * Authorize SHORT and LONG frames,
1318 * QPSK, 8PSK, 16APSK and 32APSK
1319 */
1320 if (stv090x_activate_modcod_single(state) < 0)
1321 goto err;
e415c689 1322 }
27d40321 1323
7b035da9
AR		 1324 if (stv090x_set_vit_thtracq(state) < 0)
1325 goto err;
e415c689
MA		 1326 break;
1327
1328 case STV090x_SEARCH_AUTO:
1329 default:
27d40321 1330 /* enable DVB-S2 and DVB-S2 in Auto MODE */
e415c689 1331 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
b79c6df7
AR		 1332 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1333 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1334 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1335 goto err;
e415c689
MA		 1336 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1337 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1338 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1339 goto err;
1340
4e58a682 1341 if (stv090x_vitclk_ctl(state, 0) < 0)
e415c689
MA		 1342 goto err;
1343
27d40321 1344 if (stv090x_dvbs_track_crl(state) < 0)
e415c689
MA		 1345 goto err;
1346
97f7a2ae 1347 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1348 /* enable S2 carrier loop */
1349 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1350 goto err;
1351 } else {
1352 /* > Cut 3: Stop carrier 3 */
1353 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1354 goto err;
1355 }
1356
e415c689 1357 if (state->demod_mode != STV090x_SINGLE) {
27d40321
MA		 1358 /* Cut 2: enable link during search */
1359 if (stv090x_activate_modcod(state) < 0)
1360 goto err;
1361 } else {
1362 /* Single demodulator
1363 * Authorize SHORT and LONG frames,
1364 * QPSK, 8PSK, 16APSK and 32APSK
1365 */
1366 if (stv090x_activate_modcod_single(state) < 0)
1367 goto err;
e415c689 1368 }
27d40321 1369
7b035da9
AR		 1370 if (stv090x_set_vit_thacq(state) < 0)
1371 goto err;
27d40321
MA		 1372
1373 if (stv090x_set_viterbi(state) < 0)
1374 goto err;
e415c689
MA		 1375 break;
1376 }
1377 return 0;
1378err:
1379 dprintk(FE_ERROR, 1, "I/O error");
1380 return -1;
1381}
1382
1383static int stv090x_start_search(struct stv090x_state *state)
1384{
27d40321
MA		 1385 u32 reg, freq_abs;
1386 s16 freq;
e415c689 1387
27d40321 1388 /* Reset demodulator */
e415c689
MA		 1389 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1390 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1391 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1392 goto err;
1393
97f7a2ae 1394 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1395 if (state->srate <= 5000000) {
1396 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1397 goto err;
1398 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1399 goto err;
b671a8d4 1400 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
27d40321
MA		 1401 goto err;
1402 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1403 goto err;
1404 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1405 goto err;
1406
1407 /*enlarge the timing bandwith for Low SR*/
1408 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1409 goto err;
1410 } else {
1411 /* If the symbol rate is >5 Msps
1412 Set The carrier search up and low to auto mode */
1413 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1414 goto err;
1415 /*reduce the timing bandwith for high SR*/
1416 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1417 goto err;
1418 }
1419 } else {
1420 /* >= Cut 3 */
1421 if (state->srate <= 5000000) {
1422 /* enlarge the timing bandwith for Low SR */
1423 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1424 } else {
1425 /* reduce timing bandwith for high SR */
1426 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1427 }
1428
1429 /* Set CFR min and max to manual mode */
1430 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1431
1432 if (state->algo == STV090x_WARM_SEARCH) {
1433 /* WARM Start
1434 * CFR min = -1MHz,
1435 * CFR max = +1MHz
1436 */
1437 freq_abs = 1000 << 16;
97f7a2ae 1438 freq_abs /= (state->internal->mclk / 1000);
27d40321
MA		 1439 freq = (s16) freq_abs;
1440 } else {
1441 /* COLD Start
1442 * CFR min =- (SearchRange / 2 + 600KHz)
1443 * CFR max = +(SearchRange / 2 + 600KHz)
1444 * (600KHz for the tuner step size)
1445 */
1446 freq_abs = (state->search_range / 2000) + 600;
1447 freq_abs = freq_abs << 16;
97f7a2ae 1448 freq_abs /= (state->internal->mclk / 1000);
27d40321
MA		 1449 freq = (s16) freq_abs;
1450 }
1451
1452 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
e415c689 1453 goto err;
b671a8d4 1454 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
e415c689
MA		 1455 goto err;
1456
27d40321
MA		 1457 freq *= -1;
1458
1459 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
e415c689 1460 goto err;
27d40321 1461 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
e415c689 1462 goto err;
27d40321 1463
e415c689 1464 }
27d40321 1465
e415c689
MA		 1466 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1467 goto err;
1468 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1469 goto err;
1470
97f7a2ae 1471 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 1472 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1473 goto err;
1474 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1475 goto err;
1476
1477 if ((state->search_mode == STV090x_DVBS1) ||
1478 (state->search_mode == STV090x_DSS) ||
1479 (state->search_mode == STV090x_SEARCH_AUTO)) {
1480
1481 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1482 goto err;
1483 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1484 goto err;
1485 }
1486 }
1487
1488 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1489 goto err;
1490 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1491 goto err;
1492 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1493 goto err;
1494
1495 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1496 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1497 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1498 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1499 goto err;
1500 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1501 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1502 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1503 goto err;
1504
7b035da9
AR		 1505 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1506 goto err;
1507
97f7a2ae 1508 if (state->internal->dev_ver >= 0x20) {
27d40321
MA		 1509 /*Frequency offset detector setting*/
1510 if (state->srate < 2000000) {
97f7a2ae 1511 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1512 /* Cut 2 */
1513 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1514 goto err;
1515 } else {
7b035da9 1516 /* Cut 3 */
27d40321
MA		 1517 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1518 goto err;
1519 }
1520 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1521 goto err;
a4978a83 1522 } else if (state->srate < 10000000) {
e415c689
MA		 1523 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1524 goto err;
7b035da9
AR		 1525 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1526 goto err;
e415c689
MA		 1527 } else {
1528 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1529 goto err;
7b035da9
AR		 1530 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1531 goto err;
e415c689
MA		 1532 }
1533 } else {
1534 if (state->srate < 10000000) {
1535 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1536 goto err;
1537 } else {
1538 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1539 goto err;
1540 }
1541 }
1542
1543 switch (state->algo) {
27d40321
MA		 1544 case STV090x_WARM_SEARCH:
1545 /* The symbol rate and the exact
1546 * carrier Frequency are known
1547 */
e415c689
MA		 1548 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1549 goto err;
1550 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1551 goto err;
1552 break;
1553
27d40321
MA		 1554 case STV090x_COLD_SEARCH:
1555 /* The symbol rate is known */
e415c689
MA		 1556 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1557 goto err;
1558 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1559 goto err;
1560 break;
1561
1562 default:
1563 break;
1564 }
1565 return 0;
1566err:
1567 dprintk(FE_ERROR, 1, "I/O error");
1568 return -1;
1569}
1570
1571static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1572{
b4a4248d 1573 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
e415c689
MA		 1574 s32 i, j, steps, dir;
1575
1576 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1577 goto err;
1578 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
7b035da9
AR		 1579 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1580 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
e415c689
MA		 1581 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1582 goto err;
1583
1584 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1585 goto err;
1586 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1587 goto err;
1588 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1589 goto err;
1590 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1591 goto err;
1592 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1593 goto err;
27d40321
MA		 1594 if (stv090x_set_srate(state, 1000000) < 0)
1595 goto err;
e415c689 1596
7b035da9
AR		 1597 steps = state->search_range / 1000000;
1598 if (steps <= 0)
e415c689
MA		 1599 steps = 1;
1600
1601 dir = 1;
97f7a2ae 1602 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
e415c689
MA		 1603 freq_init = 0;
1604
1605 for (i = 0; i < steps; i++) {
1606 if (dir > 0)
1607 freq_init = freq_init + (freq_step * i);
1608 else
1609 freq_init = freq_init - (freq_step * i);
1610
b671a8d4 1611 dir *= -1;
e415c689
MA		 1612
1613 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1614 goto err;
1615 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1616 goto err;
1617 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1618 goto err;
1619 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1620 goto err;
1621 msleep(10);
b4a4248d
AR		 1622
1623 agc2 = 0;
e415c689 1624 for (j = 0; j < 10; j++) {
b4a4248d
AR		 1625 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1626 STV090x_READ_DEMOD(state, AGC2I0);
e415c689
MA		 1627 }
1628 agc2 /= 10;
b4a4248d 1629 if (agc2 < agc2_min)
e415c689
MA		 1630 agc2_min = agc2;
1631 }
1632
1633 return agc2_min;
1634err:
1635 dprintk(FE_ERROR, 1, "I/O error");
1636 return -1;
1637}
1638
1639static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1640{
1641 u8 r3, r2, r1, r0;
1642 s32 srate, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 1643
1644 r3 = STV090x_READ_DEMOD(state, SFR3);
1645 r2 = STV090x_READ_DEMOD(state, SFR2);
1646 r1 = STV090x_READ_DEMOD(state, SFR1);
1647 r0 = STV090x_READ_DEMOD(state, SFR0);
1648
1649 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1650
f430fff1
MA		 1651 int_1 = clk >> 16;
1652 int_2 = srate >> 16;
e415c689 1653
f430fff1
MA		 1654 tmp_1 = clk % 0x10000;
1655 tmp_2 = srate % 0x10000;
e415c689
MA		 1656
1657 srate = (int_1 * int_2) +
f430fff1
MA		 1658 ((int_1 * tmp_2) >> 16) +
1659 ((int_2 * tmp_1) >> 16);
e415c689
MA		 1660
1661 return srate;
1662}
1663
1664static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1665{
1666 struct dvb_frontend *fe = &state->frontend;
1667
1668 int tmg_lock = 0, i;
1669 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1670 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
b4a4248d
AR		 1671 u32 agc2th;
1672
97f7a2ae 1673 if (state->internal->dev_ver >= 0x30)
b4a4248d
AR		 1674 agc2th = 0x2e00;
1675 else
1676 agc2th = 0x1f00;
e415c689
MA		 1677
1678 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1679 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1680 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1681 goto err;
1682 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1683 goto err;
7b035da9
AR		 1684 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1685 goto err;
e415c689
MA		 1686 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1687 goto err;
1688 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1689 goto err;
1690 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1691 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
7b035da9 1692 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
e415c689
MA		 1693 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1694 goto err;
1695
1696 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1697 goto err;
1698 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1699 goto err;
1700 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1701 goto err;
1702 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1703 goto err;
1704 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1705 goto err;
b4a4248d 1706 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
e415c689
MA		 1707 goto err;
1708
97f7a2ae 1709 if (state->internal->dev_ver >= 0x30) {
27d40321 1710 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
e415c689 1711 goto err;
7b035da9 1712 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
e415c689 1713 goto err;
27d40321 1714
97f7a2ae 1715 } else if (state->internal->dev_ver >= 0x20) {
27d40321 1716 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
e415c689 1717 goto err;
27d40321 1718 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
e415c689
MA		 1719 goto err;
1720 }
1721
1722 if (state->srate <= 2000000)
1723 car_step = 1000;
1724 else if (state->srate <= 5000000)
1725 car_step = 2000;
1726 else if (state->srate <= 12000000)
1727 car_step = 3000;
1728 else
1729 car_step = 5000;
1730
1731 steps = -1 + ((state->search_range / 1000) / car_step);
1732 steps /= 2;
1733 steps = (2 * steps) + 1;
1734 if (steps < 0)
1735 steps = 1;
1736 else if (steps > 10) {
1737 steps = 11;
1738 car_step = (state->search_range / 1000) / 10;
1739 }
1740 cur_step = 0;
1741 dir = 1;
1742 freq = state->frequency;
1743
1744 while ((!tmg_lock) && (cur_step < steps)) {
1745 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1746 goto err;
7b035da9
AR		 1747 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1748 goto err;
1749 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1750 goto err;
1751 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1752 goto err;
1753 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1754 goto err;
1755 /* trigger acquisition */
1756 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
e415c689
MA		 1757 goto err;
1758 msleep(50);
1759 for (i = 0; i < 10; i++) {
1760 reg = STV090x_READ_DEMOD(state, DSTATUS);
1761 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1762 tmg_cpt++;
b4a4248d
AR		 1763 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1764 STV090x_READ_DEMOD(state, AGC2I0);
e415c689
MA		 1765 }
1766 agc2 /= 10;
97f7a2ae 1767 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 1768 cur_step++;
1769 dir *= -1;
b4a4248d
AR		 1770 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1771 (srate_coarse < 50000000) && (srate_coarse > 850000))
e415c689
MA		 1772 tmg_lock = 1;
1773 else if (cur_step < steps) {
1774 if (dir > 0)
1775 freq += cur_step * car_step;
1776 else
1777 freq -= cur_step * car_step;
1778
1779 /* Setup tuner */
27d40321
MA		 1780 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1781 goto err;
e415c689 1782
27d40321 1783 if (state->config->tuner_set_frequency) {
a4978a83 1784 if (state->config->tuner_set_frequency(fe, freq) < 0)
2c1f750b 1785 goto err_gateoff;
27d40321 1786 }
e415c689 1787
27d40321
MA		 1788 if (state->config->tuner_set_bandwidth) {
1789 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 1790 goto err_gateoff;
27d40321
MA		 1791 }
1792
1793 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1794 goto err;
e415c689 1795
e415c689 1796 msleep(50);
e415c689 1797
27d40321
MA		 1798 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1799 goto err;
1800
1801 if (state->config->tuner_get_status) {
1802 if (state->config->tuner_get_status(fe, &reg) < 0)
2c1f750b 1803 goto err_gateoff;
27d40321 1804 }
e415c689
MA		 1805
1806 if (reg)
1807 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1808 else
1809 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1810
27d40321
MA		 1811 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1812 goto err;
e415c689
MA		 1813
1814 }
1815 }
1816 if (!tmg_lock)
1817 srate_coarse = 0;
1818 else
97f7a2ae 1819 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 1820
1821 return srate_coarse;
2c1f750b
OE		 1822
1823err_gateoff:
1824 stv090x_i2c_gate_ctrl(fe, 0);
e415c689
MA		 1825err:
1826 dprintk(FE_ERROR, 1, "I/O error");
1827 return -1;
1828}
1829
1830static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1831{
1832 u32 srate_coarse, freq_coarse, sym, reg;
1833
97f7a2ae 1834 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 1835 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1836 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1837 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1838
1839 if (sym < state->srate)
1840 srate_coarse = 0;
1841 else {
1842 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1843 goto err;
7b035da9 1844 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
e415c689
MA		 1845 goto err;
1846 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1847 goto err;
1848 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1849 goto err;
1850 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1851 goto err;
1852 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1853 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1854 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1855 goto err;
1856
b4a4248d
AR		 1857 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1858 goto err;
1859
97f7a2ae 1860 if (state->internal->dev_ver >= 0x30) {
27d40321 1861 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
e415c689 1862 goto err;
97f7a2ae 1863 } else if (state->internal->dev_ver >= 0x20) {
27d40321 1864 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
e415c689
MA		 1865 goto err;
1866 }
1867
1868 if (srate_coarse > 3000000) {
1869 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1870 sym = (sym / 1000) * 65536;
97f7a2ae 1871 sym /= (state->internal->mclk / 1000);
e415c689
MA		 1872 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1873 goto err;
1874 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1875 goto err;
1876 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1877 sym = (sym / 1000) * 65536;
97f7a2ae 1878 sym /= (state->internal->mclk / 1000);
e415c689
MA		 1879 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1880 goto err;
1881 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1882 goto err;
1883 sym = (srate_coarse / 1000) * 65536;
97f7a2ae 1884 sym /= (state->internal->mclk / 1000);
e415c689
MA		 1885 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1886 goto err;
1887 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1888 goto err;
1889 } else {
1890 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1891 sym = (sym / 100) * 65536;
97f7a2ae 1892 sym /= (state->internal->mclk / 100);
e415c689
MA		 1893 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1894 goto err;
1895 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1896 goto err;
1897 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1898 sym = (sym / 100) * 65536;
97f7a2ae 1899 sym /= (state->internal->mclk / 100);
e415c689
MA		 1900 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1901 goto err;
1902 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1903 goto err;
1904 sym = (srate_coarse / 100) * 65536;
97f7a2ae 1905 sym /= (state->internal->mclk / 100);
e415c689
MA		 1906 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1907 goto err;
1908 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1909 goto err;
1910 }
1911 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1912 goto err;
1913 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1914 goto err;
1915 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1916 goto err;
1917 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1918 goto err;
1919 }
1920
1921 return srate_coarse;
1922
1923err:
1924 dprintk(FE_ERROR, 1, "I/O error");
1925 return -1;
1926}
1927
1928static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1929{
1930 s32 timer = 0, lock = 0;
1931 u32 reg;
1932 u8 stat;
1933
1934 while ((timer < timeout) && (!lock)) {
1935 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1936 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1937
1938 switch (stat) {
1939 case 0: /* searching */
1940 case 1: /* first PLH detected */
1941 default:
1942 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1943 lock = 0;
1944 break;
1945 case 2: /* DVB-S2 mode */
1946 case 3: /* DVB-S1/legacy mode */
1947 reg = STV090x_READ_DEMOD(state, DSTATUS);
1948 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1949 break;
1950 }
1951
1952 if (!lock)
1953 msleep(10);
1954 else
1955 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1956
1957 timer += 10;
1958 }
1959 return lock;
1960}
1961
1962static int stv090x_blind_search(struct stv090x_state *state)
1963{
1964 u32 agc2, reg, srate_coarse;
a4978a83 1965 s32 cpt_fail, agc2_ovflw, i;
e415c689
MA		 1966 u8 k_ref, k_max, k_min;
1967 int coarse_fail, lock;
1968
7b035da9
AR		 1969 k_max = 110;
1970 k_min = 10;
e415c689
MA		 1971
1972 agc2 = stv090x_get_agc2_min_level(state);
1973
97f7a2ae 1974 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
e415c689
MA		 1975 lock = 0;
1976 } else {
27d40321 1977
97f7a2ae 1978 if (state->internal->dev_ver <= 0x20) {
27d40321 1979 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
e415c689 1980 goto err;
27d40321
MA		 1981 } else {
1982 /* > Cut 3 */
1983 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
e415c689
MA		 1984 goto err;
1985 }
1986
e415c689
MA		 1987 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1988 goto err;
27d40321 1989
97f7a2ae 1990 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 1991 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1992 goto err;
1993 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1994 goto err;
1995 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1996 goto err;
1997 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1998 goto err;
1999 }
2000
2001 k_ref = k_max;
2002 do {
2003 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2004 goto err;
2005 if (stv090x_srate_srch_coarse(state) != 0) {
2006 srate_coarse = stv090x_srate_srch_fine(state);
2007 if (srate_coarse != 0) {
2008 stv090x_get_lock_tmg(state);
a4978a83
AR		 2009 lock = stv090x_get_dmdlock(state,
2010 state->DemodTimeout);
e415c689
MA		 2011 } else {
2012 lock = 0;
2013 }
2014 } else {
2015 cpt_fail = 0;
2016 agc2_ovflw = 0;
2017 for (i = 0; i < 10; i++) {
b4a4248d
AR		 2018 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2019 STV090x_READ_DEMOD(state, AGC2I0);
e415c689
MA		 2020 if (agc2 >= 0xff00)
2021 agc2_ovflw++;
2022 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2023 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2024 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2025
2026 cpt_fail++;
2027 }
2028 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2029 coarse_fail = 1;
2030
2031 lock = 0;
2032 }
7b035da9 2033 k_ref -= 20;
e415c689
MA		 2034 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2035 }
2036
2037 return lock;
2038
2039err:
2040 dprintk(FE_ERROR, 1, "I/O error");
2041 return -1;
2042}
2043
2044static int stv090x_chk_tmg(struct stv090x_state *state)
2045{
2046 u32 reg;
27d40321 2047 s32 tmg_cpt = 0, i;
e415c689
MA		 2048 u8 freq, tmg_thh, tmg_thl;
2049 int tmg_lock;
2050
2051 freq = STV090x_READ_DEMOD(state, CARFREQ);
2052 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2053 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2054 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2055 goto err;
2056 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2057 goto err;
2058
2059 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2060 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2061 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2062 goto err;
2063 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2064 goto err;
2065
2066 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2067 goto err;
2068 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2069 goto err;
2070
2071 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2072 goto err;
2073 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2074 goto err;
2075 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2076 goto err;
2077
2078 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2079 goto err;
2080 msleep(10);
2081
2082 for (i = 0; i < 10; i++) {
2083 reg = STV090x_READ_DEMOD(state, DSTATUS);
2084 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2085 tmg_cpt++;
2086 msleep(1);
2087 }
2088 if (tmg_cpt >= 3)
2089 tmg_lock = 1;
2090
2091 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2092 goto err;
2093 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2094 goto err;
2095 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2096 goto err;
2097
2098 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2099 goto err;
2100 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2101 goto err;
2102 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2103 goto err;
2104
2105 return tmg_lock;
2106
2107err:
2108 dprintk(FE_ERROR, 1, "I/O error");
2109 return -1;
2110}
2111
2112static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2113{
2114 struct dvb_frontend *fe = &state->frontend;
2115
2116 u32 reg;
2117 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2118 int lock = 0;
2119
2120 if (state->srate >= 10000000)
2121 timeout_lock = timeout_dmd / 3;
2122 else
2123 timeout_lock = timeout_dmd / 2;
2124
2125 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2126 if (!lock) {
2127 if (state->srate >= 10000000) {
2128 if (stv090x_chk_tmg(state)) {
2129 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2130 goto err;
2131 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2132 goto err;
2133 lock = stv090x_get_dmdlock(state, timeout_dmd);
2134 } else {
2135 lock = 0;
2136 }
2137 } else {
2138 if (state->srate <= 4000000)
2139 car_step = 1000;
2140 else if (state->srate <= 7000000)
2141 car_step = 2000;
2142 else if (state->srate <= 10000000)
2143 car_step = 3000;
2144 else
2145 car_step = 5000;
2146
2147 steps = (state->search_range / 1000) / car_step;
2148 steps /= 2;
2149 steps = 2 * (steps + 1);
2150 if (steps < 0)
2151 steps = 2;
2152 else if (steps > 12)
2153 steps = 12;
2154
2155 cur_step = 1;
2156 dir = 1;
2157
2158 if (!lock) {
2159 freq = state->frequency;
2160 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2161 while ((cur_step <= steps) && (!lock)) {
2162 if (dir > 0)
2163 freq += cur_step * car_step;
2164 else
2165 freq -= cur_step * car_step;
2166
2167 /* Setup tuner */
27d40321
MA		 2168 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2169 goto err;
e415c689 2170
27d40321 2171 if (state->config->tuner_set_frequency) {
a4978a83 2172 if (state->config->tuner_set_frequency(fe, freq) < 0)
2c1f750b 2173 goto err_gateoff;
27d40321 2174 }
e415c689 2175
27d40321
MA		 2176 if (state->config->tuner_set_bandwidth) {
2177 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 2178 goto err_gateoff;
27d40321 2179 }
e415c689 2180
27d40321
MA		 2181 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2182 goto err;
e415c689
MA		 2183
2184 msleep(50);
2185
27d40321
MA		 2186 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2187 goto err;
e415c689 2188
27d40321
MA		 2189 if (state->config->tuner_get_status) {
2190 if (state->config->tuner_get_status(fe, &reg) < 0)
2c1f750b 2191 goto err_gateoff;
27d40321 2192 }
e415c689
MA		 2193
2194 if (reg)
2195 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2196 else
2197 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2198
27d40321
MA		 2199 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2200 goto err;
e415c689
MA		 2201
2202 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
e415c689
MA		 2203 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2204 goto err;
2205 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2206 goto err;
2207 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2208 goto err;
2209 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2210 goto err;
2211 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2212
2213 dir *= -1;
2214 cur_step++;
2215 }
2216 }
2217 }
2218 }
2219
2220 return lock;
2221
2c1f750b
OE		 2222err_gateoff:
2223 stv090x_i2c_gate_ctrl(fe, 0);
e415c689
MA		 2224err:
2225 dprintk(FE_ERROR, 1, "I/O error");
2226 return -1;
2227}
2228
2229static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2230{
2231 s32 timeout, inc, steps_max, srate, car_max;
2232
2233 srate = state->srate;
2234 car_max = state->search_range / 1000;
2f5914be 2235 car_max += car_max / 10;
e415c689 2236 car_max = 65536 * (car_max / 2);
97f7a2ae 2237 car_max /= (state->internal->mclk / 1000);
e415c689
MA		 2238
2239 if (car_max > 0x4000)
2240 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2241
2242 inc = srate;
97f7a2ae 2243 inc /= state->internal->mclk / 1000;
e415c689
MA		 2244 inc *= 256;
2245 inc *= 256;
2246 inc /= 1000;
2247
72982f76 2248 switch (state->search_mode) {
e415c689
MA		 2249 case STV090x_SEARCH_DVBS1:
2250 case STV090x_SEARCH_DSS:
2251 inc *= 3; /* freq step = 3% of srate */
2252 timeout = 20;
2253 break;
2254
2255 case STV090x_SEARCH_DVBS2:
2256 inc *= 4;
2257 timeout = 25;
2258 break;
2259
2260 case STV090x_SEARCH_AUTO:
2261 default:
2262 inc *= 3;
2263 timeout = 25;
2264 break;
2265 }
2266 inc /= 100;
2267 if ((inc > car_max) || (inc < 0))
2268 inc = car_max / 2; /* increment <= 1/8 Mclk */
2269
2270 timeout *= 27500; /* 27.5 Msps reference */
2271 if (srate > 0)
2272 timeout /= (srate / 1000);
2273
2274 if ((timeout > 100) || (timeout < 0))
2275 timeout = 100;
2276
2277 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2278 if ((steps_max > 100) || (steps_max < 0)) {
2279 steps_max = 100; /* max steps <= 100 */
2280 inc = car_max / steps_max;
2281 }
2282 *freq_inc = inc;
2283 *timeout_sw = timeout;
2284 *steps = steps_max;
2285
2286 return 0;
2287}
2288
2289static int stv090x_chk_signal(struct stv090x_state *state)
2290{
2291 s32 offst_car, agc2, car_max;
2292 int no_signal;
2293
2294 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2295 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2f5914be 2296 offst_car = comp2(offst_car, 16);
e415c689
MA		 2297
2298 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2299 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2300 car_max = state->search_range / 1000;
2301
2302 car_max += (car_max / 10); /* 10% margin */
2303 car_max = (65536 * car_max / 2);
97f7a2ae 2304 car_max /= state->internal->mclk / 1000;
e415c689
MA		 2305
2306 if (car_max > 0x4000)
2307 car_max = 0x4000;
2308
2309 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2310 no_signal = 1;
2311 dprintk(FE_DEBUG, 1, "No Signal");
2312 } else {
2313 no_signal = 0;
2314 dprintk(FE_DEBUG, 1, "Found Signal");
2315 }
2316
2317 return no_signal;
2318}
2319
2320static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2321{
2322 int no_signal, lock = 0;
27d40321 2323 s32 cpt_step = 0, offst_freq, car_max;
e415c689
MA		 2324 u32 reg;
2325
2326 car_max = state->search_range / 1000;
2327 car_max += (car_max / 10);
2328 car_max = (65536 * car_max / 2);
97f7a2ae 2329 car_max /= (state->internal->mclk / 1000);
e415c689
MA		 2330 if (car_max > 0x4000)
2331 car_max = 0x4000;
2332
2333 if (zigzag)
2334 offst_freq = 0;
2335 else
2336 offst_freq = -car_max + inc;
2337
e415c689
MA		 2338 do {
2339 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2340 goto err;
2341 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2342 goto err;
2343 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2344 goto err;
2345 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2346 goto err;
2347
2348 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2349 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2350 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2351 goto err;
2352
e415c689
MA		 2353 if (zigzag) {
2354 if (offst_freq >= 0)
2355 offst_freq = -offst_freq - 2 * inc;
2356 else
2357 offst_freq = -offst_freq;
2358 } else {
2359 offst_freq += 2 * inc;
2360 }
2361
2f5914be
AR		 2362 cpt_step++;
2363
e415c689
MA		 2364 lock = stv090x_get_dmdlock(state, timeout);
2365 no_signal = stv090x_chk_signal(state);
2366
2367 } while ((!lock) &&
2368 (!no_signal) &&
2369 ((offst_freq - inc) < car_max) &&
2370 ((offst_freq + inc) > -car_max) &&
2371 (cpt_step < steps_max));
2372
2373 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2374 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2375 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2376 goto err;
2377
2378 return lock;
2379err:
2380 dprintk(FE_ERROR, 1, "I/O error");
2381 return -1;
2382}
2383
2384static int stv090x_sw_algo(struct stv090x_state *state)
2385{
2386 int no_signal, zigzag, lock = 0;
2387 u32 reg;
2388
2389 s32 dvbs2_fly_wheel;
2390 s32 inc, timeout_step, trials, steps_max;
2391
27d40321
MA		 2392 /* get params */
2393 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
e415c689 2394
72982f76 2395 switch (state->search_mode) {
e415c689
MA		 2396 case STV090x_SEARCH_DVBS1:
2397 case STV090x_SEARCH_DSS:
2398 /* accelerate the frequency detector */
97f7a2ae 2399 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2400 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2401 goto err;
e415c689 2402 }
27d40321 2403
e415c689
MA		 2404 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2405 goto err;
2406 zigzag = 0;
2407 break;
2408
2409 case STV090x_SEARCH_DVBS2:
97f7a2ae 2410 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2411 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2412 goto err;
e415c689 2413 }
27d40321 2414
e415c689
MA		 2415 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2416 goto err;
2417 zigzag = 1;
2418 break;
2419
2420 case STV090x_SEARCH_AUTO:
2421 default:
2422 /* accelerate the frequency detector */
97f7a2ae 2423 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2424 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2425 goto err;
2426 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2427 goto err;
e415c689 2428 }
27d40321 2429
2f5914be 2430 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
e415c689
MA		 2431 goto err;
2432 zigzag = 0;
2433 break;
2434 }
2435
2436 trials = 0;
2437 do {
2438 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2439 no_signal = stv090x_chk_signal(state);
2440 trials++;
2441
2442 /*run the SW search 2 times maximum*/
2443 if (lock || no_signal || (trials == 2)) {
2444 /*Check if the demod is not losing lock in DVBS2*/
97f7a2ae 2445 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2446 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2447 goto err;
2448 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2449 goto err;
e415c689
MA		 2450 }
2451
2452 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2453 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2454 /*Check if the demod is not losing lock in DVBS2*/
2455 msleep(timeout_step);
2456 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2457 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2458 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2459 msleep(timeout_step);
2460 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2461 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2462 }
2463 if (dvbs2_fly_wheel < 0xd) {
2464 /*FALSE lock, The demod is loosing lock */
2465 lock = 0;
2466 if (trials < 2) {
97f7a2ae 2467 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2468 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2469 goto err;
e415c689 2470 }
27d40321 2471
e415c689
MA		 2472 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2473 goto err;
2474 }
2475 }
2476 }
2477 }
2478 } while ((!lock) && (trials < 2) && (!no_signal));
2479
2480 return lock;
2481err:
2482 dprintk(FE_ERROR, 1, "I/O error");
2483 return -1;
2484}
2485
2486static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2487{
2488 u32 reg;
2489 enum stv090x_delsys delsys;
2490
2491 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2492 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2493 delsys = STV090x_DVBS2;
2494 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2495 reg = STV090x_READ_DEMOD(state, FECM);
2496 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2497 delsys = STV090x_DSS;
2498 else
2499 delsys = STV090x_DVBS1;
2500 } else {
2501 delsys = STV090x_ERROR;
2502 }
2503
2504 return delsys;
2505}
2506
2507/* in Hz */
2508static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2509{
2510 s32 derot, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 2511
2512 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2513 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2514 derot |= STV090x_READ_DEMOD(state, CFR0);
2515
2516 derot = comp2(derot, 24);
97f7a2ae 2517 int_1 = mclk >> 12;
da4b9059 2518 int_2 = derot >> 12;
e415c689 2519
da4b9059 2520 /* carrier_frequency = MasterClock * Reg / 2^24 */
97f7a2ae 2521 tmp_1 = mclk % 0x1000;
da4b9059 2522 tmp_2 = derot % 0x1000;
e415c689
MA		 2523
2524 derot = (int_1 * int_2) +
da4b9059 2525 ((int_1 * tmp_2) >> 12) +
b671a8d4 2526 ((int_2 * tmp_1) >> 12);
e415c689
MA		 2527
2528 return derot;
2529}
2530
2531static int stv090x_get_viterbi(struct stv090x_state *state)
2532{
2533 u32 reg, rate;
2534
2535 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2536 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2537
2538 switch (rate) {
2539 case 13:
2540 state->fec = STV090x_PR12;
2541 break;
2542
2543 case 18:
2544 state->fec = STV090x_PR23;
2545 break;
2546
2547 case 21:
2548 state->fec = STV090x_PR34;
2549 break;
2550
2551 case 24:
2552 state->fec = STV090x_PR56;
2553 break;
2554
2555 case 25:
2556 state->fec = STV090x_PR67;
2557 break;
2558
2559 case 26:
2560 state->fec = STV090x_PR78;
2561 break;
2562
2563 default:
2564 state->fec = STV090x_PRERR;
2565 break;
2566 }
2567
2568 return 0;
2569}
2570
2571static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2572{
2573 struct dvb_frontend *fe = &state->frontend;
2574
2575 u8 tmg;
2576 u32 reg;
2577 s32 i = 0, offst_freq;
2578
2579 msleep(5);
2580
2581 if (state->algo == STV090x_BLIND_SEARCH) {
2582 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2583 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2f5914be 2584 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
e415c689
MA		 2585 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2586 msleep(5);
2587 i += 5;
2588 }
2589 }
2590 state->delsys = stv090x_get_std(state);
2591
27d40321
MA		 2592 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2593 goto err;
e415c689 2594
27d40321
MA		 2595 if (state->config->tuner_get_frequency) {
2596 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2c1f750b 2597 goto err_gateoff;
27d40321 2598 }
e415c689 2599
27d40321
MA		 2600 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2601 goto err;
e415c689 2602
97f7a2ae 2603 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
e415c689 2604 state->frequency += offst_freq;
27d40321
MA		 2605
2606 if (stv090x_get_viterbi(state) < 0)
2607 goto err;
2608
e415c689
MA		 2609 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2610 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2611 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2612 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2613 reg = STV090x_READ_DEMOD(state, TMGOBS);
2614 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2615 reg = STV090x_READ_DEMOD(state, FECM);
2616 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2617
2618 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2619
27d40321
MA		 2620 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2621 goto err;
e415c689 2622
27d40321
MA		 2623 if (state->config->tuner_get_frequency) {
2624 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2c1f750b 2625 goto err_gateoff;
27d40321 2626 }
e415c689 2627
27d40321
MA		 2628 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2629 goto err;
e415c689
MA		 2630
2631 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2f5914be 2632 return STV090x_RANGEOK;
e415c689
MA		 2633 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2634 return STV090x_RANGEOK;
2635 else
2636 return STV090x_OUTOFRANGE; /* Out of Range */
2637 } else {
2638 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2639 return STV090x_RANGEOK;
2640 else
2641 return STV090x_OUTOFRANGE;
2642 }
2643
2644 return STV090x_OUTOFRANGE;
2c1f750b
OE		 2645
2646err_gateoff:
2647 stv090x_i2c_gate_ctrl(fe, 0);
27d40321
MA		 2648err:
2649 dprintk(FE_ERROR, 1, "I/O error");
2650 return -1;
e415c689
MA		 2651}
2652
2653static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2654{
2655 s32 offst_tmg;
e415c689
MA		 2656
2657 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2658 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2659 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2660
e415c689
MA		 2661 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2662 if (!offst_tmg)
2663 offst_tmg = 1;
2664
5f99feff 2665 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
e415c689
MA		 2666 offst_tmg /= 320;
2667
2668 return offst_tmg;
2669}
2670
2671static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2672{
2673 u8 aclc = 0x29;
2674 s32 i;
27d40321 2675 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
e415c689 2676
97f7a2ae 2677 if (state->internal->dev_ver == 0x20) {
27d40321
MA		 2678 car_loop = stv090x_s2_crl_cut20;
2679 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2680 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2681 } else {
2682 /* >= Cut 3 */
2683 car_loop = stv090x_s2_crl_cut30;
2684 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2685 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2686 }
e415c689
MA		 2687
2688 if (modcod < STV090x_QPSK_12) {
2689 i = 0;
27d40321 2690 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
e415c689
MA		 2691 i++;
2692
2693 if (i >= 3)
2694 i = 2;
2695
2696 } else {
2697 i = 0;
2698 while ((i < 14) && (modcod != car_loop[i].modcod))
2699 i++;
2700
2701 if (i >= 14) {
2702 i = 0;
27d40321 2703 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
e415c689
MA		 2704 i++;
2705
2706 if (i >= 11)
2707 i = 10;
2708 }
2709 }
2710
2711 if (modcod <= STV090x_QPSK_25) {
2712 if (pilots) {
2713 if (state->srate <= 3000000)
27d40321 2714 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
e415c689 2715 else if (state->srate <= 7000000)
27d40321 2716 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
e415c689 2717 else if (state->srate <= 15000000)
27d40321 2718 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
e415c689 2719 else if (state->srate <= 25000000)
27d40321 2720 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
e415c689 2721 else
27d40321 2722 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
e415c689
MA		 2723 } else {
2724 if (state->srate <= 3000000)
27d40321 2725 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
e415c689 2726 else if (state->srate <= 7000000)
27d40321 2727 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
e415c689 2728 else if (state->srate <= 15000000)
27d40321 2729 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
e415c689 2730 else if (state->srate <= 25000000)
27d40321 2731 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
e415c689 2732 else
27d40321 2733 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
e415c689
MA		 2734 }
2735
2736 } else if (modcod <= STV090x_8PSK_910) {
2737 if (pilots) {
2738 if (state->srate <= 3000000)
2739 aclc = car_loop[i].crl_pilots_on_2;
2740 else if (state->srate <= 7000000)
2741 aclc = car_loop[i].crl_pilots_on_5;
2742 else if (state->srate <= 15000000)
2743 aclc = car_loop[i].crl_pilots_on_10;
2744 else if (state->srate <= 25000000)
2745 aclc = car_loop[i].crl_pilots_on_20;
2746 else
2747 aclc = car_loop[i].crl_pilots_on_30;
2748 } else {
2749 if (state->srate <= 3000000)
2750 aclc = car_loop[i].crl_pilots_off_2;
2751 else if (state->srate <= 7000000)
2752 aclc = car_loop[i].crl_pilots_off_5;
2753 else if (state->srate <= 15000000)
2754 aclc = car_loop[i].crl_pilots_off_10;
2755 else if (state->srate <= 25000000)
2756 aclc = car_loop[i].crl_pilots_off_20;
2757 else
2758 aclc = car_loop[i].crl_pilots_off_30;
2759 }
2760 } else { /* 16APSK and 32APSK */
2761 if (state->srate <= 3000000)
27d40321 2762 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
e415c689 2763 else if (state->srate <= 7000000)
27d40321 2764 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
e415c689 2765 else if (state->srate <= 15000000)
27d40321 2766 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
e415c689 2767 else if (state->srate <= 25000000)
27d40321 2768 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
e415c689 2769 else
27d40321 2770 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
e415c689
MA		 2771 }
2772
2773 return aclc;
2774}
2775
2776static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2777{
0a5ded56 2778 struct stv090x_short_frame_crloop *short_crl = NULL;
e415c689
MA		 2779 s32 index = 0;
2780 u8 aclc = 0x0b;
2781
2782 switch (state->modulation) {
2783 case STV090x_QPSK:
2784 default:
2785 index = 0;
2786 break;
2787 case STV090x_8PSK:
2788 index = 1;
2789 break;
2790 case STV090x_16APSK:
2791 index = 2;
2792 break;
2793 case STV090x_32APSK:
2794 index = 3;
2795 break;
2796 }
2797
97f7a2ae 2798 if (state->internal->dev_ver >= 0x30) {
eebf8d86 2799 /* Cut 3.0 and up */
27d40321 2800 short_crl = stv090x_s2_short_crl_cut30;
eebf8d86
MA		 2801 } else {
2802 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2803 short_crl = stv090x_s2_short_crl_cut20;
2804 }
27d40321
MA		 2805
2806 if (state->srate <= 3000000)
2807 aclc = short_crl[index].crl_2;
2808 else if (state->srate <= 7000000)
2809 aclc = short_crl[index].crl_5;
2810 else if (state->srate <= 15000000)
2811 aclc = short_crl[index].crl_10;
2812 else if (state->srate <= 25000000)
2813 aclc = short_crl[index].crl_20;
2814 else
2815 aclc = short_crl[index].crl_30;
e415c689
MA		 2816
2817 return aclc;
2818}
2819
2820static int stv090x_optimize_track(struct stv090x_state *state)
2821{
2822 struct dvb_frontend *fe = &state->frontend;
2823
2824 enum stv090x_rolloff rolloff;
2825 enum stv090x_modcod modcod;
2826
2827 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2828 u32 reg;
2829
97f7a2ae 2830 srate = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 2831 srate += stv090x_get_tmgoffst(state, srate);
2832
2833 switch (state->delsys) {
2834 case STV090x_DVBS1:
2835 case STV090x_DSS:
b671a8d4 2836 if (state->search_mode == STV090x_SEARCH_AUTO) {
e415c689
MA		 2837 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2838 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2839 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2840 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2841 goto err;
2842 }
2843 reg = STV090x_READ_DEMOD(state, DEMOD);
2844 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
27d40321 2845 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
e415c689
MA		 2846 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2847 goto err;
27d40321 2848
97f7a2ae 2849 if (state->internal->dev_ver >= 0x30) {
27d40321
MA		 2850 if (stv090x_get_viterbi(state) < 0)
2851 goto err;
2852
2853 if (state->fec == STV090x_PR12) {
2854 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2855 goto err;
2856 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2857 goto err;
2858 } else {
2859 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2860 goto err;
2861 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2862 goto err;
2863 }
2864 }
2865
e415c689
MA		 2866 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2867 goto err;
2868 break;
2869
2870 case STV090x_DVBS2:
2871 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2f5914be
AR		 2872 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2873 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
e415c689
MA		 2874 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2875 goto err;
2876 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2877 goto err;
2878 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2879 goto err;
2880 if (state->frame_len == STV090x_LONG_FRAME) {
2881 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2882 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2883 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2884 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2885 if (modcod <= STV090x_QPSK_910) {
2886 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2887 } else if (modcod <= STV090x_8PSK_910) {
2888 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2889 goto err;
2890 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2891 goto err;
2892 }
2893 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2894 if (modcod <= STV090x_16APSK_910) {
2895 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2896 goto err;
2897 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2898 goto err;
2899 } else {
2900 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2901 goto err;
2902 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2903 goto err;
2904 }
2905 }
2906 } else {
2907 /*Carrier loop setting for short frame*/
2908 aclc = stv090x_optimize_carloop_short(state);
2909 if (state->modulation == STV090x_QPSK) {
2910 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2911 goto err;
2912 } else if (state->modulation == STV090x_8PSK) {
2913 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2914 goto err;
2915 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2916 goto err;
2917 } else if (state->modulation == STV090x_16APSK) {
2918 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2919 goto err;
2920 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2921 goto err;
2922 } else if (state->modulation == STV090x_32APSK) {
2923 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2924 goto err;
2925 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2926 goto err;
2927 }
2928 }
27d40321 2929
e415c689
MA		 2930 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2931 break;
2932
2933 case STV090x_UNKNOWN:
2934 default:
2935 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2936 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2937 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2938 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2939 goto err;
2940 break;
2941 }
2942
2943 f_1 = STV090x_READ_DEMOD(state, CFR2);
2944 f_0 = STV090x_READ_DEMOD(state, CFR1);
2945 reg = STV090x_READ_DEMOD(state, TMGOBS);
2946 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2947
2948 if (state->algo == STV090x_BLIND_SEARCH) {
2949 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2950 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2951 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2952 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2953 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2954 goto err;
27d40321
MA		 2955 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2956 goto err;
2957
2958 if (stv090x_set_srate(state, srate) < 0)
e415c689 2959 goto err;
e415c689 2960 blind_tune = 1;
7b035da9
AR		 2961
2962 if (stv090x_dvbs_track_crl(state) < 0)
2963 goto err;
e415c689
MA		 2964 }
2965
97f7a2ae 2966 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2967 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2968 (state->search_mode == STV090x_SEARCH_DSS) ||
2969 (state->search_mode == STV090x_SEARCH_AUTO)) {
2970
2971 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2972 goto err;
2973 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2974 goto err;
2975 }
2976 }
2977
e415c689
MA		 2978 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2979 goto err;
2980
27d40321
MA		 2981 /* AUTO tracking MODE */
2982 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2983 goto err;
2984 /* AUTO tracking MODE */
2985 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
2986 goto err;
e415c689 2987
97f7a2ae
AR		 2988 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
2989 (state->srate < 10000000)) {
27d40321 2990 /* update initial carrier freq with the found freq offset */
e415c689
MA		 2991 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2992 goto err;
2993 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2994 goto err;
2995 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2996
97f7a2ae 2997 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
e415c689
MA		 2998
2999 if (state->algo != STV090x_WARM_SEARCH) {
3000
27d40321
MA		 3001 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3002 goto err;
e415c689 3003
27d40321
MA		 3004 if (state->config->tuner_set_bandwidth) {
3005 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 3006 goto err_gateoff;
27d40321 3007 }
e415c689 3008
27d40321
MA		 3009 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3010 goto err;
e415c689
MA		 3011
3012 }
3013 }
3014 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3015 msleep(50); /* blind search: wait 50ms for SR stabilization */
3016 else
3017 msleep(5);
3018
3019 stv090x_get_lock_tmg(state);
3020
3021 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3022 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3023 goto err;
3024 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3025 goto err;
3026 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3027 goto err;
3028 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3029 goto err;
3030
3031 i = 0;
3032
3033 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3034
3035 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3036 goto err;
3037 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3038 goto err;
3039 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3040 goto err;
3041 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3042 goto err;
3043 i++;
3044 }
3045 }
3046
3047 }
3048
97f7a2ae 3049 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 3050 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3051 goto err;
3052 }
27d40321 3053
e415c689
MA		 3054 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3055 stv090x_set_vit_thtracq(state);
3056
3057 return 0;
2c1f750b
OE		 3058
3059err_gateoff:
3060 stv090x_i2c_gate_ctrl(fe, 0);
e415c689
MA		 3061err:
3062 dprintk(FE_ERROR, 1, "I/O error");
3063 return -1;
3064}
3065
3066static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3067{
3068 s32 timer = 0, lock = 0, stat;
3069 u32 reg;
3070
3071 while ((timer < timeout) && (!lock)) {
3072 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3073 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3074
3075 switch (stat) {
3076 case 0: /* searching */
3077 case 1: /* first PLH detected */
3078 default:
3079 lock = 0;
3080 break;
3081
3082 case 2: /* DVB-S2 mode */
3083 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3084 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3085 break;
3086
3087 case 3: /* DVB-S1/legacy mode */
3088 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3089 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3090 break;
3091 }
3092 if (!lock) {
3093 msleep(10);
3094 timer += 10;
3095 }
3096 }
3097 return lock;
3098}
3099
3100static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3101{
3102 u32 reg;
3103 s32 timer = 0;
3104 int lock;
3105
3106 lock = stv090x_get_dmdlock(state, timeout_dmd);
3107 if (lock)
3108 lock = stv090x_get_feclock(state, timeout_fec);
3109
3110 if (lock) {
3111 lock = 0;
3112
3113 while ((timer < timeout_fec) && (!lock)) {
3114 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3115 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3116 msleep(1);
3117 timer++;
3118 }
3119 }
3120
3121 return lock;
3122}
3123
3124static int stv090x_set_s2rolloff(struct stv090x_state *state)
3125{
e415c689
MA		 3126 u32 reg;
3127
97f7a2ae 3128 if (state->internal->dev_ver <= 0x20) {
27d40321 3129 /* rolloff to auto mode if DVBS2 */
e415c689 3130 reg = STV090x_READ_DEMOD(state, DEMOD);
27d40321 3131 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
e415c689
MA		 3132 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3133 goto err;
3134 } else {
27d40321 3135 /* DVB-S2 rolloff to auto mode if DVBS2 */
e415c689 3136 reg = STV090x_READ_DEMOD(state, DEMOD);
27d40321 3137 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
e415c689
MA		 3138 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3139 goto err;
3140 }
3141 return 0;
3142err:
3143 dprintk(FE_ERROR, 1, "I/O error");
3144 return -1;
3145}
3146
e415c689
MA		 3147
3148static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3149{
3150 struct dvb_frontend *fe = &state->frontend;
3151 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3152 u32 reg;
a4978a83 3153 s32 agc1_power, power_iq = 0, i;
4e58a682 3154 int lock = 0, low_sr = 0, no_signal = 0;
e415c689
MA		 3155
3156 reg = STV090x_READ_DEMOD(state, TSCFGH);
3157 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3158 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3159 goto err;
3160
3161 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3162 goto err;
3163
97f7a2ae 3164 if (state->internal->dev_ver >= 0x20) {
7b035da9
AR		 3165 if (state->srate > 5000000) {
3166 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3167 goto err;
3168 } else {
3169 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3170 goto err;
3171 }
e415c689
MA		 3172 }
3173
3174 stv090x_get_lock_tmg(state);
3175
3176 if (state->algo == STV090x_BLIND_SEARCH) {
3177 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
27d40321
MA		 3178 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3179 goto err;
3180 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3181 goto err;
3182 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
e415c689 3183 goto err;
e415c689
MA		 3184 } else {
3185 /* known srate */
3186 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3187 goto err;
3188 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3189 goto err;
3190
27d40321
MA		 3191 if (state->srate < 2000000) {
3192 /* SR < 2MSPS */
3193 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
e415c689
MA		 3194 goto err;
3195 } else {
27d40321
MA		 3196 /* SR >= 2Msps */
3197 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
e415c689
MA		 3198 goto err;
3199 }
3200
27d40321
MA		 3201 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3202 goto err;
3203
97f7a2ae 3204 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 3205 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3206 goto err;
3207 if (state->algo == STV090x_COLD_SEARCH)
4e58a682 3208 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
e415c689
MA		 3209 else if (state->algo == STV090x_WARM_SEARCH)
3210 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
e415c689 3211 }
27d40321
MA		 3212
3213 /* if cold start or warm (Symbolrate is known)
3214 * use a Narrow symbol rate scan range
3215 */
3216 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3217 goto err;
3218
3219 if (stv090x_set_srate(state, state->srate) < 0)
3220 goto err;
3221
97f7a2ae
AR		 3222 if (stv090x_set_max_srate(state, state->internal->mclk,
3223 state->srate) < 0)
27d40321 3224 goto err;
97f7a2ae
AR		 3225 if (stv090x_set_min_srate(state, state->internal->mclk,
3226 state->srate) < 0)
e415c689 3227 goto err;
e415c689
MA		 3228
3229 if (state->srate >= 10000000)
4e58a682
AR		 3230 low_sr = 0;
3231 else
e415c689
MA		 3232 low_sr = 1;
3233 }
3234
3235 /* Setup tuner */
27d40321
MA		 3236 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3237 goto err;
e415c689 3238
27d40321
MA		 3239 if (state->config->tuner_set_bbgain) {
3240 if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
2c1f750b 3241 goto err_gateoff;
27d40321 3242 }
e415c689 3243
27d40321
MA		 3244 if (state->config->tuner_set_frequency) {
3245 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
2c1f750b 3246 goto err_gateoff;
27d40321 3247 }
e415c689 3248
27d40321
MA		 3249 if (state->config->tuner_set_bandwidth) {
3250 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 3251 goto err_gateoff;
27d40321 3252 }
e415c689 3253
27d40321
MA		 3254 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3255 goto err;
e415c689
MA		 3256
3257 msleep(50);
3258
27d40321
MA		 3259 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3260 goto err;
e415c689 3261
27d40321
MA		 3262 if (state->config->tuner_get_status) {
3263 if (state->config->tuner_get_status(fe, &reg) < 0)
2c1f750b 3264 goto err_gateoff;
27d40321 3265 }
e415c689
MA		 3266
3267 if (reg)
3268 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3269 else
3270 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3271
27d40321 3272 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
e415c689 3273 goto err;
e415c689 3274
27d40321
MA		 3275 msleep(10);
3276 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3277 STV090x_READ_DEMOD(state, AGCIQIN0));
3278
3279 if (agc1_power == 0) {
3280 /* If AGC1 integrator value is 0
3281 * then read POWERI, POWERQ
3282 */
3283 for (i = 0; i < 5; i++) {
3284 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3285 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3286 }
3287 power_iq /= 5;
3288 }
3289
3290 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3291 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3292 lock = 0;
c4fa649a 3293 signal_state = STV090x_NOAGC1;
27d40321
MA		 3294 } else {
3295 reg = STV090x_READ_DEMOD(state, DEMOD);
3296 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3297
97f7a2ae 3298 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 3299 /* rolloff to auto mode if DVBS2 */
3300 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3301 } else {
3302 /* DVB-S2 rolloff to auto mode if DVBS2 */
3303 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3304 }
3305 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
e415c689 3306 goto err;
27d40321
MA		 3307
3308 if (stv090x_delivery_search(state) < 0)
e415c689 3309 goto err;
27d40321
MA		 3310
3311 if (state->algo != STV090x_BLIND_SEARCH) {
3312 if (stv090x_start_search(state) < 0)
3313 goto err;
3314 }
e415c689
MA		 3315 }
3316
c4fa649a
AR		 3317 if (signal_state == STV090x_NOAGC1)
3318 return signal_state;
27d40321 3319
e415c689
MA		 3320 if (state->algo == STV090x_BLIND_SEARCH)
3321 lock = stv090x_blind_search(state);
27d40321 3322
e415c689 3323 else if (state->algo == STV090x_COLD_SEARCH)
a4978a83 3324 lock = stv090x_get_coldlock(state, state->DemodTimeout);
27d40321 3325
e415c689 3326 else if (state->algo == STV090x_WARM_SEARCH)
a4978a83 3327 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
e415c689
MA		 3328
3329 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3330 if (!low_sr) {
3331 if (stv090x_chk_tmg(state))
3332 lock = stv090x_sw_algo(state);
3333 }
3334 }
3335
3336 if (lock)
3337 signal_state = stv090x_get_sig_params(state);
3338
3339 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3340 stv090x_optimize_track(state);
27d40321 3341
97f7a2ae 3342 if (state->internal->dev_ver >= 0x20) {
27d40321
MA		 3343 /* >= Cut 2.0 :release TS reset after
3344 * demod lock and optimized Tracking
3345 */
e415c689
MA		 3346 reg = STV090x_READ_DEMOD(state, TSCFGH);
3347 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3348 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3349 goto err;
27d40321 3350
e415c689 3351 msleep(3);
27d40321 3352
e415c689
MA		 3353 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3354 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3355 goto err;
3356
3357 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3358 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3359 goto err;
3360 }
3361
a4978a83
AR		 3362 lock = stv090x_get_lock(state, state->FecTimeout,
3363 state->FecTimeout);
3364 if (lock) {
e415c689
MA		 3365 if (state->delsys == STV090x_DVBS2) {
3366 stv090x_set_s2rolloff(state);
27d40321
MA		 3367
3368 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3369 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3370 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
e415c689 3371 goto err;
27d40321
MA		 3372 /* Reset DVBS2 packet delinator error counter */
3373 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3374 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3375 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
e415c689 3376 goto err;
27d40321 3377
e415c689
MA		 3378 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3379 goto err;
3380 } else {
3381 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3382 goto err;
3383 }
27d40321 3384 /* Reset the Total packet counter */
e415c689
MA		 3385 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3386 goto err;
27d40321 3387 /* Reset the packet Error counter2 */
e415c689
MA		 3388 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3389 goto err;
3390 } else {
e415c689
MA		 3391 signal_state = STV090x_NODATA;
3392 no_signal = stv090x_chk_signal(state);
3393 }
3394 }
e415c689
MA		 3395 return signal_state;
3396
2c1f750b
OE		 3397err_gateoff:
3398 stv090x_i2c_gate_ctrl(fe, 0);
e415c689
MA		 3399err:
3400 dprintk(FE_ERROR, 1, "I/O error");
3401 return -1;
3402}
3403
3404static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3405{
3406 struct stv090x_state *state = fe->demodulator_priv;
3407 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3408
729cbafa
AR		 3409 if (p->frequency == 0)
3410 return DVBFE_ALGO_SEARCH_INVALID;
3411
e415c689
MA		 3412 state->delsys = props->delivery_system;
3413 state->frequency = p->frequency;
3414 state->srate = p->u.qpsk.symbol_rate;
4e58a682
AR		 3415 state->search_mode = STV090x_SEARCH_AUTO;
3416 state->algo = STV090x_COLD_SEARCH;
3417 state->fec = STV090x_PRERR;
c879d8ce
AR		 3418 if (state->srate > 10000000) {
3419 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3420 state->search_range = 10000000;
3421 } else {
3422 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3423 state->search_range = 5000000;
3424 }
e415c689 3425
2f5914be 3426 if (stv090x_algo(state) == STV090x_RANGEOK) {
e415c689
MA		 3427 dprintk(FE_DEBUG, 1, "Search success!");
3428 return DVBFE_ALGO_SEARCH_SUCCESS;
3429 } else {
3430 dprintk(FE_DEBUG, 1, "Search failed!");
3431 return DVBFE_ALGO_SEARCH_FAILED;
3432 }
3433
3434 return DVBFE_ALGO_SEARCH_ERROR;
3435}
3436
e415c689
MA		 3437static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3438{
3439 struct stv090x_state *state = fe->demodulator_priv;
3440 u32 reg;
3441 u8 search_state;
e415c689
MA		 3442
3443 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3444 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3445
3446 switch (search_state) {
3447 case 0: /* searching */
3448 case 1: /* first PLH detected */
3449 default:
3450 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
9629c5b6 3451 *status = 0;
e415c689
MA		 3452 break;
3453
3454 case 2: /* DVB-S2 mode */
3455 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3456 reg = STV090x_READ_DEMOD(state, DSTATUS);
3457 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
1d436171
AR		 3458 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3459 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3460 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3461 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
c369b7c2
AR		 3462 *status = FE_HAS_SIGNAL |
3463 FE_HAS_CARRIER |
1d436171
AR		 3464 FE_HAS_VITERBI |
3465 FE_HAS_SYNC |
3466 FE_HAS_LOCK;
3467 }
e415c689
MA		 3468 }
3469 }
3470 break;
3471
3472 case 3: /* DVB-S1/legacy mode */
3473 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3474 reg = STV090x_READ_DEMOD(state, DSTATUS);
3475 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3476 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3477 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3478 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3479 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
c369b7c2
AR		 3480 *status = FE_HAS_SIGNAL |
3481 FE_HAS_CARRIER |
3482 FE_HAS_VITERBI |
3483 FE_HAS_SYNC |
3484 FE_HAS_LOCK;
e415c689
MA		 3485 }
3486 }
3487 }
3488 break;
3489 }
3490
9629c5b6 3491 return 0;
e415c689
MA		 3492}
3493
3494static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3495{
3496 struct stv090x_state *state = fe->demodulator_priv;
3497
3498 s32 count_4, count_3, count_2, count_1, count_0, count;
3499 u32 reg, h, m, l;
3500 enum fe_status status;
3501
9629c5b6
AR		 3502 stv090x_read_status(fe, &status);
3503 if (!(status & FE_HAS_LOCK)) {
e415c689
MA		 3504 *per = 1 << 23; /* Max PER */
3505 } else {
3506 /* Counter 2 */
3507 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3508 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3509
3510 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3511 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3512
3513 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3514 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3515
3516 *per = ((h << 16) | (m << 8) | l);
3517
3518 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3519 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3520 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3521 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3522 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3523
3524 if ((!count_4) && (!count_3)) {
3525 count = (count_2 & 0xff) << 16;
3526 count |= (count_1 & 0xff) << 8;
3527 count |= count_0 & 0xff;
3528 } else {
3529 count = 1 << 24;
3530 }
3531 if (count == 0)
3532 *per = 1;
3533 }
3534 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3535 goto err;
3536 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3537 goto err;
3538
3539 return 0;
3540err:
3541 dprintk(FE_ERROR, 1, "I/O error");
3542 return -1;
3543}
3544
3545static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3546{
3547 int res = 0;
3548 int min = 0, med;
3549
dbeb7dbf
AR		 3550 if ((val >= tab[min].read && val < tab[max].read) ||
3551 (val >= tab[max].read && val < tab[min].read)) {
e415c689
MA		 3552 while ((max - min) > 1) {
3553 med = (max + min) / 2;
dbeb7dbf
AR		 3554 if ((val >= tab[min].read && val < tab[med].read) ||
3555 (val >= tab[med].read && val < tab[min].read))
e415c689
MA		 3556 max = med;
3557 else
3558 min = med;
3559 }
3560 res = ((val - tab[min].read) *
3561 (tab[max].real - tab[min].real) /
3562 (tab[max].read - tab[min].read)) +
3563 tab[min].real;
dbeb7dbf
AR		 3564 } else {
3565 if (tab[min].read < tab[max].read) {
3566 if (val < tab[min].read)
3567 res = tab[min].real;
3568 else if (val >= tab[max].read)
3569 res = tab[max].real;
3570 } else {
3571 if (val >= tab[min].read)
3572 res = tab[min].real;
3573 else if (val < tab[max].read)
3574 res = tab[max].real;
3575 }
e415c689
MA		 3576 }
3577
3578 return res;
3579}
3580
3581static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3582{
3583 struct stv090x_state *state = fe->demodulator_priv;
3584 u32 reg;
dbeb7dbf
AR		 3585 s32 agc_0, agc_1, agc;
3586 s32 str;
e415c689
MA		 3587
3588 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
dbeb7dbf
AR		 3589 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3590 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3591 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3592 agc = MAKEWORD16(agc_1, agc_0);
e415c689 3593
dbeb7dbf
AR		 3594 str = stv090x_table_lookup(stv090x_rf_tab,
3595 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
e415c689 3596 if (agc > stv090x_rf_tab[0].read)
dbeb7dbf 3597 str = 0;
e415c689 3598 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
dbeb7dbf
AR		 3599 str = -100;
3600 *strength = (str + 100) * 0xFFFF / 100;
e415c689
MA		 3601
3602 return 0;
3603}
3604
3605static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3606{
3607 struct stv090x_state *state = fe->demodulator_priv;
3608 u32 reg_0, reg_1, reg, i;
3609 s32 val_0, val_1, val = 0;
3610 u8 lock_f;
dbeb7dbf
AR		 3611 s32 div;
3612 u32 last;
e415c689
MA		 3613
3614 switch (state->delsys) {
3615 case STV090x_DVBS2:
3616 reg = STV090x_READ_DEMOD(state, DSTATUS);
3617 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3618 if (lock_f) {
3619 msleep(5);
3620 for (i = 0; i < 16; i++) {
3621 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3622 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3623 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
dbeb7dbf 3624 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
e415c689
MA		 3625 val += MAKEWORD16(val_1, val_0);
3626 msleep(1);
3627 }
3628 val /= 16;
dbeb7dbf
AR		 3629 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3630 div = stv090x_s2cn_tab[0].read -
3631 stv090x_s2cn_tab[last].read;
3632 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
e415c689
MA		 3633 }
3634 break;
3635
3636 case STV090x_DVBS1:
3637 case STV090x_DSS:
3638 reg = STV090x_READ_DEMOD(state, DSTATUS);
3639 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3640 if (lock_f) {
3641 msleep(5);
3642 for (i = 0; i < 16; i++) {
3643 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3644 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3645 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
dbeb7dbf 3646 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
e415c689
MA		 3647 val += MAKEWORD16(val_1, val_0);
3648 msleep(1);
3649 }
3650 val /= 16;
dbeb7dbf
AR		 3651 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3652 div = stv090x_s1cn_tab[0].read -
3653 stv090x_s1cn_tab[last].read;
3654 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
e415c689
MA		 3655 }
3656 break;
3657 default:
3658 break;
3659 }
3660
3661 return 0;
3662}
3663
3664static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3665{
3666 struct stv090x_state *state = fe->demodulator_priv;
3667 u32 reg;
3668
3669 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3670 switch (tone) {
3671 case SEC_TONE_ON:
3672 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3673 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3674 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3675 goto err;
3676 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3677 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3678 goto err;
3679 break;
3680
3681 case SEC_TONE_OFF:
3682 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3683 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3684 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3685 goto err;
3686 break;
3687 default:
3688 return -EINVAL;
3689 }
3690
3691 return 0;
3692err:
3693 dprintk(FE_ERROR, 1, "I/O error");
3694 return -1;
3695}
3696
3697
3698static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3699{
3700 return DVBFE_ALGO_CUSTOM;
3701}
3702
3703static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3704{
3705 struct stv090x_state *state = fe->demodulator_priv;
3706 u32 reg, idle = 0, fifo_full = 1;
3707 int i;
3708
3709 reg = STV090x_READ_DEMOD(state, DISTXCTL);
f9ed95d0 3710
30e8ca2c
OE		 3711 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3712 (state->config->diseqc_envelope_mode) ? 4 : 2);
f9ed95d0
AR		 3713 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3714 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3715 goto err;
3716 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3717 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3718 goto err;
3719
e415c689
MA		 3720 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3721 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3722 goto err;
3723
3724 for (i = 0; i < cmd->msg_len; i++) {
3725
3726 while (fifo_full) {
3727 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3728 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3729 }
3730
3731 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3732 goto err;
f9ed95d0
AR		 3733 }
3734 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3735 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3736 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3737 goto err;
3738
3739 i = 0;
3740
3741 while ((!idle) && (i < 10)) {
3742 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3743 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3744 msleep(10);
e415c689
MA		 3745 i++;
3746 }
f9ed95d0
AR		 3747
3748 return 0;
3749err:
3750 dprintk(FE_ERROR, 1, "I/O error");
3751 return -1;
3752}
3753
3754static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3755{
3756 struct stv090x_state *state = fe->demodulator_priv;
3757 u32 reg, idle = 0, fifo_full = 1;
3758 u8 mode, value;
3759 int i;
3760
3761 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3762
3763 if (burst == SEC_MINI_A) {
30e8ca2c 3764 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
f9ed95d0
AR		 3765 value = 0x00;
3766 } else {
30e8ca2c 3767 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
f9ed95d0
AR		 3768 value = 0xFF;
3769 }
3770
3771 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3772 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3773 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3774 goto err;
3775 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3776 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3777 goto err;
3778
3779 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3780 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3781 goto err;
3782
3783 while (fifo_full) {
3784 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3785 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3786 }
3787
3788 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3789 goto err;
3790
e415c689
MA		 3791 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3792 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3793 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3794 goto err;
3795
3796 i = 0;
3797
3798 while ((!idle) && (i < 10)) {
3799 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3800 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3801 msleep(10);
3802 i++;
3803 }
3804
3805 return 0;
3806err:
3807 dprintk(FE_ERROR, 1, "I/O error");
3808 return -1;
3809}
3810
3811static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3812{
3813 struct stv090x_state *state = fe->demodulator_priv;
3814 u32 reg = 0, i = 0, rx_end = 0;
3815
3816 while ((rx_end != 1) && (i < 10)) {
3817 msleep(10);
3818 i++;
3819 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3820 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3821 }
3822
3823 if (rx_end) {
3824 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3825 for (i = 0; i < reply->msg_len; i++)
3826 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3827 }
3828
3829 return 0;
3830}
3831
3832static int stv090x_sleep(struct dvb_frontend *fe)
3833{
3834 struct stv090x_state *state = fe->demodulator_priv;
3835 u32 reg;
3836
3837 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3838 state->device == STV0900 ? "STV0900" : "STV0903");
3839
3840 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3841 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3842 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3843 goto err;
3844
26b03bc6
MA		 3845 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3846 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3847 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3848 goto err;
3849
e415c689
MA		 3850 return 0;
3851err:
3852 dprintk(FE_ERROR, 1, "I/O error");
3853 return -1;
3854}
3855
3856static int stv090x_wakeup(struct dvb_frontend *fe)
3857{
3858 struct stv090x_state *state = fe->demodulator_priv;
3859 u32 reg;
3860
3861 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3862 state->device == STV0900 ? "STV0900" : "STV0903");
3863
3864 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3865 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3866 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3867 goto err;
3868
26b03bc6
MA		 3869 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3870 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3871 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3872 goto err;
3873
e415c689
MA		 3874 return 0;
3875err:
3876 dprintk(FE_ERROR, 1, "I/O error");
3877 return -1;
3878}
3879
3880static void stv090x_release(struct dvb_frontend *fe)
3881{
3882 struct stv090x_state *state = fe->demodulator_priv;
3883
97f7a2ae
AR		 3884 state->internal->num_used--;
3885 if (state->internal->num_used <= 0) {
3886
3887 dprintk(FE_ERROR, 1, "Actually removing");
3888
3889 remove_dev(state->internal);
3890 kfree(state->internal);
3891 }
3892
e415c689
MA		 3893 kfree(state);
3894}
3895
3896static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3897{
27d40321 3898 u32 reg = 0;
e415c689 3899
a4978a83
AR		 3900 reg = stv090x_read_reg(state, STV090x_GENCFG);
3901
e415c689
MA		 3902 switch (ldpc_mode) {
3903 case STV090x_DUAL:
3904 default:
e415c689 3905 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
27d40321
MA		 3906 /* set LDPC to dual mode */
3907 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
e415c689 3908 goto err;
27d40321 3909
e415c689 3910 state->demod_mode = STV090x_DUAL;
27d40321 3911
e415c689
MA		 3912 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3913 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3914 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3915 goto err;
3916 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3917 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3918 goto err;
27d40321
MA		 3919
3920 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
3921 goto err;
3922 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
3923 goto err;
3924 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
3925 goto err;
3926 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
3927 goto err;
3928 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
3929 goto err;
3930 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
3931 goto err;
3932 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
3933 goto err;
3934
3935 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
3936 goto err;
3937 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
3938 goto err;
3939 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
3940 goto err;
3941 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
3942 goto err;
3943 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
3944 goto err;
3945 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
3946 goto err;
3947 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
3948 goto err;
3949
3950 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
3951 goto err;
3952 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
3953 goto err;
e415c689
MA		 3954 }
3955 break;
3956
3957 case STV090x_SINGLE:
27d40321
MA		 3958 if (stv090x_stop_modcod(state) < 0)
3959 goto err;
3960 if (stv090x_activate_modcod_single(state) < 0)
3961 goto err;
3962
e415c689
MA		 3963 if (state->demod == STV090x_DEMODULATOR_1) {
3964 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3965 goto err;
3966 } else {
3967 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3968 goto err;
3969 }
3970
3971 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3972 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3973 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3974 goto err;
3975 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3976 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3977 goto err;
3978
3979 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3980 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3981 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3982 goto err;
3983 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3984 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3985 goto err;
3986 break;
3987 }
3988
3989 return 0;
3990err:
3991 dprintk(FE_ERROR, 1, "I/O error");
3992 return -1;
3993}
3994
3995/* return (Hz), clk in Hz*/
3996static u32 stv090x_get_mclk(struct stv090x_state *state)
3997{
3998 const struct stv090x_config *config = state->config;
3999 u32 div, reg;
4000 u8 ratio;
4001
4002 div = stv090x_read_reg(state, STV090x_NCOARSE);
4003 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4004 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4005
4006 return (div + 1) * config->xtal / ratio; /* kHz */
4007}
4008
4009static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4010{
4011 const struct stv090x_config *config = state->config;
4012 u32 reg, div, clk_sel;
4013
4014 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4015 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4016
4017 div = ((clk_sel * mclk) / config->xtal) - 1;
4018
4019 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4020 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4021 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4022 goto err;
4023
97f7a2ae 4024 state->internal->mclk = stv090x_get_mclk(state);
e415c689 4025
94a80914 4026 /*Set the DiseqC frequency to 22KHz */
97f7a2ae 4027 div = state->internal->mclk / 704000;
94a80914
MA		 4028 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4029 goto err;
4030 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4031 goto err;
4032
e415c689
MA		 4033 return 0;
4034err:
4035 dprintk(FE_ERROR, 1, "I/O error");
4036 return -1;
4037}
4038
4039static int stv090x_set_tspath(struct stv090x_state *state)
4040{
4041 u32 reg;
4042
97f7a2ae 4043 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 4044 switch (state->config->ts1_mode) {
4045 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4046 case STV090x_TSMODE_DVBCI:
4047 switch (state->config->ts2_mode) {
4048 case STV090x_TSMODE_SERIAL_PUNCTURED:
4049 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4050 default:
4051 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4052 break;
4053
4054 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4055 case STV090x_TSMODE_DVBCI:
4056 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4057 goto err;
4058 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4059 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4060 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4061 goto err;
4062 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4063 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4064 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4065 goto err;
4066 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4067 goto err;
4068 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4069 goto err;
4070 break;
4071 }
4072 break;
4073
4074 case STV090x_TSMODE_SERIAL_PUNCTURED:
4075 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4076 default:
4077 switch (state->config->ts2_mode) {
4078 case STV090x_TSMODE_SERIAL_PUNCTURED:
4079 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4080 default:
4081 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4082 goto err;
4083 break;
4084
4085 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4086 case STV090x_TSMODE_DVBCI:
4087 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4088 goto err;
4089 break;
4090 }
4091 break;
4092 }
4093 } else {
4094 switch (state->config->ts1_mode) {
4095 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4096 case STV090x_TSMODE_DVBCI:
4097 switch (state->config->ts2_mode) {
4098 case STV090x_TSMODE_SERIAL_PUNCTURED:
4099 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4100 default:
56571507 4101 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
e415c689
MA		 4102 break;
4103
4104 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4105 case STV090x_TSMODE_DVBCI:
56571507 4106 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
e415c689
MA		 4107 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4108 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4109 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4110 goto err;
4111 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4112 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4113 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4114 goto err;
4115 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4116 goto err;
4117 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4118 goto err;
4119 break;
4120 }
4121 break;
4122
4123 case STV090x_TSMODE_SERIAL_PUNCTURED:
4124 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4125 default:
4126 switch (state->config->ts2_mode) {
4127 case STV090x_TSMODE_SERIAL_PUNCTURED:
4128 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4129 default:
56571507 4130 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
e415c689
MA		 4131 break;
4132
4133 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4134 case STV090x_TSMODE_DVBCI:
56571507 4135 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
e415c689
MA		 4136 break;
4137 }
4138 break;
4139 }
4140 }
4141
4142 switch (state->config->ts1_mode) {
4143 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4144 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4145 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4146 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4147 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4148 goto err;
4149 break;
4150
4151 case STV090x_TSMODE_DVBCI:
4152 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4153 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4154 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4155 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4156 goto err;
4157 break;
4158
4159 case STV090x_TSMODE_SERIAL_PUNCTURED:
4160 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4161 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4162 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4163 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4164 goto err;
4165 break;
4166
4167 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4168 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4169 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4170 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4171 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4172 goto err;
4173 break;
4174
4175 default:
4176 break;
4177 }
4178
4179 switch (state->config->ts2_mode) {
4180 case STV090x_TSMODE_PARALLEL_PUNCTURED:
64104dc9 4181 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4182 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4183 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
64104dc9 4184 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4185 goto err;
4186 break;
4187
4188 case STV090x_TSMODE_DVBCI:
64104dc9 4189 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4190 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4191 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
64104dc9 4192 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4193 goto err;
4194 break;
4195
4196 case STV090x_TSMODE_SERIAL_PUNCTURED:
64104dc9 4197 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4198 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4199 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
64104dc9 4200 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4201 goto err;
4202 break;
4203
4204 case STV090x_TSMODE_SERIAL_CONTINUOUS:
64104dc9 4205 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4206 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4207 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
64104dc9 4208 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4209 goto err;
4210 break;
4211
4212 default:
4213 break;
4214 }
f91e59cb
AR		 4215
4216 if (state->config->ts1_clk > 0) {
4217 u32 speed;
4218
4219 switch (state->config->ts1_mode) {
4220 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4221 case STV090x_TSMODE_DVBCI:
4222 default:
4223 speed = state->internal->mclk /
4224 (state->config->ts1_clk / 4);
4225 if (speed < 0x08)
4226 speed = 0x08;
4227 if (speed > 0xFF)
4228 speed = 0xFF;
4229 break;
4230 case STV090x_TSMODE_SERIAL_PUNCTURED:
4231 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4232 speed = state->internal->mclk /
4233 (state->config->ts1_clk / 32);
4234 if (speed < 0x20)
4235 speed = 0x20;
4236 if (speed > 0xFF)
4237 speed = 0xFF;
4238 break;
4239 }
4240 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4241 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4242 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4243 goto err;
4244 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4245 goto err;
4246 }
4247
4248 if (state->config->ts2_clk > 0) {
4249 u32 speed;
4250
4251 switch (state->config->ts2_mode) {
4252 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4253 case STV090x_TSMODE_DVBCI:
4254 default:
4255 speed = state->internal->mclk /
4256 (state->config->ts2_clk / 4);
4257 if (speed < 0x08)
4258 speed = 0x08;
4259 if (speed > 0xFF)
4260 speed = 0xFF;
4261 break;
4262 case STV090x_TSMODE_SERIAL_PUNCTURED:
4263 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4264 speed = state->internal->mclk /
4265 (state->config->ts2_clk / 32);
4266 if (speed < 0x20)
4267 speed = 0x20;
4268 if (speed > 0xFF)
4269 speed = 0xFF;
4270 break;
4271 }
4272 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4273 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4274 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4275 goto err;
4276 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4277 goto err;
4278 }
4279
e415c689
MA		 4280 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4281 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4282 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4283 goto err;
4284 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4285 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4286 goto err;
4287
4288 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4289 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4290 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4291 goto err;
4292 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4293 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4294 goto err;
4295
4296 return 0;
4297err:
4298 dprintk(FE_ERROR, 1, "I/O error");
4299 return -1;
4300}
4301
4302static int stv090x_init(struct dvb_frontend *fe)
4303{
4304 struct stv090x_state *state = fe->demodulator_priv;
4305 const struct stv090x_config *config = state->config;
4306 u32 reg;
4307
9045e729
AR		 4308 if (state->internal->mclk == 0) {
4309 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4310 msleep(5);
4311 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4312 0x20 | config->clk_mode) < 0)
4313 goto err;
4314 stv090x_get_mclk(state);
4315 }
4316
cbc320d2
AR		 4317 if (stv090x_wakeup(fe) < 0) {
4318 dprintk(FE_ERROR, 1, "Error waking device");
4319 goto err;
4320 }
4321
27d40321
MA		 4322 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4323 goto err;
e415c689
MA		 4324
4325 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4326 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4327 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4328 goto err;
4329 reg = STV090x_READ_DEMOD(state, DEMOD);
4330 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4331 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4332 goto err;
4333
27d40321
MA		 4334 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
4335 goto err;
e415c689 4336
27d40321
MA		 4337 if (config->tuner_set_mode) {
4338 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
2c1f750b 4339 goto err_gateoff;
27d40321 4340 }
e415c689 4341
27d40321
MA		 4342 if (config->tuner_init) {
4343 if (config->tuner_init(fe) < 0)
2c1f750b 4344 goto err_gateoff;
27d40321
MA		 4345 }
4346
4347 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
4348 goto err;
e415c689 4349
27d40321
MA		 4350 if (stv090x_set_tspath(state) < 0)
4351 goto err;
e415c689
MA		 4352
4353 return 0;
2c1f750b
OE		 4354
4355err_gateoff:
4356 stv090x_i2c_gate_ctrl(fe, 0);
e415c689
MA		 4357err:
4358 dprintk(FE_ERROR, 1, "I/O error");
4359 return -1;
4360}
4361
4362static int stv090x_setup(struct dvb_frontend *fe)
4363{
4364 struct stv090x_state *state = fe->demodulator_priv;
4365 const struct stv090x_config *config = state->config;
4366 const struct stv090x_reg *stv090x_initval = NULL;
4367 const struct stv090x_reg *stv090x_cut20_val = NULL;
4368 unsigned long t1_size = 0, t2_size = 0;
017eb038 4369 u32 reg = 0;
e415c689
MA		 4370
4371 int i;
4372
4373 if (state->device == STV0900) {
4374 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4375 stv090x_initval = stv0900_initval;
4376 t1_size = ARRAY_SIZE(stv0900_initval);
4377 stv090x_cut20_val = stv0900_cut20_val;
4378 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4379 } else if (state->device == STV0903) {
4380 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4381 stv090x_initval = stv0903_initval;
4382 t1_size = ARRAY_SIZE(stv0903_initval);
4383 stv090x_cut20_val = stv0903_cut20_val;
4384 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4385 }
4386
4387 /* STV090x init */
97f7a2ae
AR		 4388
4389 /* Stop Demod */
4390 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4391 goto err;
4392 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
e415c689
MA		 4393 goto err;
4394
4395 msleep(5);
4396
97f7a2ae
AR		 4397 /* Set No Tuner Mode */
4398 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4399 goto err;
4400 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
e415c689
MA		 4401 goto err;
4402
97f7a2ae 4403 /* I2C repeater OFF */
017eb038 4404 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
97f7a2ae
AR		 4405 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4406 goto err;
4407 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
e415c689
MA		 4408 goto err;
4409
4410 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4411 goto err;
4412 msleep(5);
4413 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4414 goto err;
4415 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4416 goto err;
4417 msleep(5);
4418
4419 /* write initval */
2f5914be 4420 dprintk(FE_DEBUG, 1, "Setting up initial values");
e415c689 4421 for (i = 0; i < t1_size; i++) {
e415c689
MA		 4422 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4423 goto err;
4424 }
4425
97f7a2ae
AR		 4426 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4427 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 4428 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4429 goto err;
4430
4431 /* write cut20_val*/
4432 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4433 for (i = 0; i < t2_size; i++) {
4434 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4435 goto err;
4436 }
27d40321 4437
97f7a2ae 4438 } else if (state->internal->dev_ver < 0x20) {
27d40321 4439 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
97f7a2ae 4440 state->internal->dev_ver);
27d40321
MA		 4441
4442 goto err;
97f7a2ae 4443 } else if (state->internal->dev_ver > 0x30) {
27d40321
MA		 4444 /* we shouldn't bail out from here */
4445 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
97f7a2ae 4446 state->internal->dev_ver);
e415c689
MA		 4447 }
4448
4449 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4450 goto err;
4451 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4452 goto err;
4453
e415c689
MA		 4454 return 0;
4455err:
4456 dprintk(FE_ERROR, 1, "I/O error");
4457 return -1;
4458}
4459
4460static struct dvb_frontend_ops stv090x_ops = {
4461
4462 .info = {
4463 .name = "STV090x Multistandard",
7fc08bbb
AR		 4464 .type = FE_QPSK,
4465 .frequency_min = 950000,
4466 .frequency_max = 2150000,
4467 .frequency_stepsize = 0,
4468 .frequency_tolerance = 0,
4469 .symbol_rate_min = 1000000,
4470 .symbol_rate_max = 45000000,
4471 .caps = FE_CAN_INVERSION_AUTO |
4472 FE_CAN_FEC_AUTO |
4473 FE_CAN_QPSK |
4474 FE_CAN_2G_MODULATION
e415c689
MA		 4475 },
4476
4477 .release = stv090x_release,
4478 .init = stv090x_init,
4479
4480 .sleep = stv090x_sleep,
4481 .get_frontend_algo = stv090x_frontend_algo,
4482
4483 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
4484
4485 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
f9ed95d0 4486 .diseqc_send_burst = stv090x_send_diseqc_burst,
e415c689
MA		 4487 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4488 .set_tone = stv090x_set_tone,
4489
4490 .search = stv090x_search,
4491 .read_status = stv090x_read_status,
4492 .read_ber = stv090x_read_per,
4493 .read_signal_strength = stv090x_read_signal_strength,
4494 .read_snr = stv090x_read_cnr
4495};
4496
4497
4498struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4499 struct i2c_adapter *i2c,
4500 enum stv090x_demodulator demod)
4501{
4502 struct stv090x_state *state = NULL;
97f7a2ae 4503 struct stv090x_dev *temp_int;
e415c689
MA		 4504
4505 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4506 if (state == NULL)
4507 goto error;
4508
4509 state->verbose = &verbose;
4510 state->config = config;
4511 state->i2c = i2c;
4512 state->frontend.ops = stv090x_ops;
4513 state->frontend.demodulator_priv = state;
56571507 4514 state->demod = demod;
e415c689
MA		 4515 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4516 state->device = config->device;
4e58a682 4517 state->rolloff = STV090x_RO_35; /* default */
e415c689 4518
97f7a2ae
AR		 4519 temp_int = find_dev(state->i2c,
4520 state->config->address);
4521
4522 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4523 state->internal = temp_int->internal;
4524 state->internal->num_used++;
4525 dprintk(FE_INFO, 1, "Found Internal Structure!");
4526 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4527 state->device == STV0900 ? "STV0900" : "STV0903",
4528 demod,
4529 state->internal->dev_ver);
4530 return &state->frontend;
4531 } else {
4532 state->internal = kmalloc(sizeof(struct stv090x_internal),
4533 GFP_KERNEL);
4534 temp_int = append_internal(state->internal);
4535 state->internal->num_used = 1;
76b9ef97
AR		 4536 state->internal->mclk = 0;
4537 state->internal->dev_ver = 0;
97f7a2ae
AR		 4538 state->internal->i2c_adap = state->i2c;
4539 state->internal->i2c_addr = state->config->address;
4540 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4541 }
4542
4543 mutex_init(&state->internal->demod_lock);
96506a50 4544 mutex_init(&state->internal->tuner_lock);
e415c689
MA		 4545
4546 if (stv090x_sleep(&state->frontend) < 0) {
4547 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4548 goto error;
4549 }
4550
4551 if (stv090x_setup(&state->frontend) < 0) {
4552 dprintk(FE_ERROR, 1, "Error setting up device");
4553 goto error;
4554 }
4555 if (stv090x_wakeup(&state->frontend) < 0) {
4556 dprintk(FE_ERROR, 1, "Error waking device");
4557 goto error;
4558 }
e415c689 4559
97f7a2ae 4560 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
e415c689
MA		 4561 state->device == STV0900 ? "STV0900" : "STV0903",
4562 demod,
97f7a2ae 4563 state->internal->dev_ver);
e415c689
MA		 4564
4565 return &state->frontend;
4566
4567error:
4568 kfree(state);
4569 return NULL;
4570}
4571EXPORT_SYMBOL(stv090x_attach);
4572MODULE_PARM_DESC(verbose, "Set Verbosity level");
4573MODULE_AUTHOR("Manu Abraham");
4574MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4575MODULE_LICENSE("GPL");
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