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V4L/DVB (11593): stv090x: Fix Rolloff
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb / frontends / stv090x.c
CommitLineData
e415c689
MA		 1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/mutex.h>
27
28#include <linux/dvb/frontend.h>
29#include "dvb_frontend.h"
30
31#include "stv6110x.h" /* for demodulator internal modes */
32
33#include "stv090x_reg.h"
34#include "stv090x.h"
35#include "stv090x_priv.h"
36
37static unsigned int verbose;
38module_param(verbose, int, 0644);
39
40struct mutex demod_lock;
41
42/* DVBS1 and DSS C/N Lookup table */
43static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
96};
97
98/* DVBS2 C/N Lookup table */
99static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
155};
156
157/* RF level C/N lookup table */
158static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
173};
174
175
176static struct stv090x_reg stv0900_initval[] = {
177
178 { STV090x_OUTCFG, 0x00 },
56571507 179 { STV090x_MODECFG, 0xff },
e415c689
MA		 180 { STV090x_AGCRF1CFG, 0x11 },
181 { STV090x_AGCRF2CFG, 0x13 },
56571507 182 { STV090x_TSGENERAL1X, 0x14 },
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MA		 183 { STV090x_TSTTNR2, 0x21 },
184 { STV090x_TSTTNR4, 0x21 },
185 { STV090x_P2_DISTXCTL, 0x22 },
186 { STV090x_P2_F22TX, 0xc0 },
187 { STV090x_P2_F22RX, 0xc0 },
188 { STV090x_P2_DISRXCTL, 0x00 },
189 { STV090x_P2_DMDCFGMD, 0xF9 },
190 { STV090x_P2_DEMOD, 0x08 },
191 { STV090x_P2_DMDCFG3, 0xc4 },
192 { STV090x_P2_CARFREQ, 0xed },
193 { STV090x_P2_LDT, 0xd0 },
194 { STV090x_P2_LDT2, 0xb8 },
195 { STV090x_P2_TMGCFG, 0xd2 },
196 { STV090x_P2_TMGTHRISE, 0x20 },
197 { STV090x_P1_TMGCFG, 0xd2 },
198
199 { STV090x_P2_TMGTHFALL, 0x00 },
200 { STV090x_P2_FECSPY, 0x88 },
201 { STV090x_P2_FSPYDATA, 0x3a },
202 { STV090x_P2_FBERCPT4, 0x00 },
203 { STV090x_P2_FSPYBER, 0x10 },
204 { STV090x_P2_ERRCTRL1, 0x35 },
205 { STV090x_P2_ERRCTRL2, 0xc1 },
206 { STV090x_P2_CFRICFG, 0xf8 },
207 { STV090x_P2_NOSCFG, 0x1c },
56571507 208 { STV090x_P2_DMDTOM, 0x20 },
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MA		 209 { STV090x_P2_CORRELMANT, 0x70 },
210 { STV090x_P2_CORRELABS, 0x88 },
56571507 211 { STV090x_P2_AGC2O, 0x5b },
e415c689
MA		 212 { STV090x_P2_AGC2REF, 0x38 },
213 { STV090x_P2_CARCFG, 0xe4 },
214 { STV090x_P2_ACLC, 0x1A },
215 { STV090x_P2_BCLC, 0x09 },
216 { STV090x_P2_CARHDR, 0x08 },
217 { STV090x_P2_KREFTMG, 0xc1 },
218 { STV090x_P2_SFRUPRATIO, 0xf0 },
219 { STV090x_P2_SFRLOWRATIO, 0x70 },
220 { STV090x_P2_SFRSTEP, 0x58 },
221 { STV090x_P2_TMGCFG2, 0x01 },
222 { STV090x_P2_CAR2CFG, 0x26 },
223 { STV090x_P2_BCLC2S2Q, 0x86 },
224 { STV090x_P2_BCLC2S28, 0x86 },
225 { STV090x_P2_SMAPCOEF7, 0x77 },
226 { STV090x_P2_SMAPCOEF6, 0x85 },
227 { STV090x_P2_SMAPCOEF5, 0x77 },
228 { STV090x_P2_TSCFGL, 0x20 },
229 { STV090x_P2_DMDCFG2, 0x3b },
230 { STV090x_P2_MODCODLST0, 0xff },
231 { STV090x_P2_MODCODLST1, 0xff },
232 { STV090x_P2_MODCODLST2, 0xff },
233 { STV090x_P2_MODCODLST3, 0xff },
234 { STV090x_P2_MODCODLST4, 0xff },
235 { STV090x_P2_MODCODLST5, 0xff },
236 { STV090x_P2_MODCODLST6, 0xff },
237 { STV090x_P2_MODCODLST7, 0xcc },
238 { STV090x_P2_MODCODLST8, 0xcc },
239 { STV090x_P2_MODCODLST9, 0xcc },
240 { STV090x_P2_MODCODLSTA, 0xcc },
241 { STV090x_P2_MODCODLSTB, 0xcc },
242 { STV090x_P2_MODCODLSTC, 0xcc },
243 { STV090x_P2_MODCODLSTD, 0xcc },
244 { STV090x_P2_MODCODLSTE, 0xcc },
245 { STV090x_P2_MODCODLSTF, 0xcf },
246 { STV090x_P1_DISTXCTL, 0x22 },
247 { STV090x_P1_F22TX, 0xc0 },
248 { STV090x_P1_F22RX, 0xc0 },
249 { STV090x_P1_DISRXCTL, 0x00 },
250 { STV090x_P1_DMDCFGMD, 0xf9 },
251 { STV090x_P1_DEMOD, 0x08 },
252 { STV090x_P1_DMDCFG3, 0xc4 },
56571507 253 { STV090x_P1_DMDTOM, 0x20 },
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MA		 254 { STV090x_P1_CARFREQ, 0xed },
255 { STV090x_P1_LDT, 0xd0 },
256 { STV090x_P1_LDT2, 0xb8 },
257 { STV090x_P1_TMGCFG, 0xd2 },
258 { STV090x_P1_TMGTHRISE, 0x20 },
259 { STV090x_P1_TMGTHFALL, 0x00 },
260 { STV090x_P1_SFRUPRATIO, 0xf0 },
261 { STV090x_P1_SFRLOWRATIO, 0x70 },
262 { STV090x_P1_TSCFGL, 0x20 },
263 { STV090x_P1_FECSPY, 0x88 },
264 { STV090x_P1_FSPYDATA, 0x3a },
265 { STV090x_P1_FBERCPT4, 0x00 },
266 { STV090x_P1_FSPYBER, 0x10 },
267 { STV090x_P1_ERRCTRL1, 0x35 },
268 { STV090x_P1_ERRCTRL2, 0xc1 },
269 { STV090x_P1_CFRICFG, 0xf8 },
270 { STV090x_P1_NOSCFG, 0x1c },
271 { STV090x_P1_CORRELMANT, 0x70 },
272 { STV090x_P1_CORRELABS, 0x88 },
56571507 273 { STV090x_P1_AGC2O, 0x5b },
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MA		 274 { STV090x_P1_AGC2REF, 0x38 },
275 { STV090x_P1_CARCFG, 0xe4 },
276 { STV090x_P1_ACLC, 0x1A },
277 { STV090x_P1_BCLC, 0x09 },
278 { STV090x_P1_CARHDR, 0x08 },
279 { STV090x_P1_KREFTMG, 0xc1 },
280 { STV090x_P1_SFRSTEP, 0x58 },
281 { STV090x_P1_TMGCFG2, 0x01 },
282 { STV090x_P1_CAR2CFG, 0x26 },
283 { STV090x_P1_BCLC2S2Q, 0x86 },
284 { STV090x_P1_BCLC2S28, 0x86 },
285 { STV090x_P1_SMAPCOEF7, 0x77 },
286 { STV090x_P1_SMAPCOEF6, 0x85 },
287 { STV090x_P1_SMAPCOEF5, 0x77 },
288 { STV090x_P1_DMDCFG2, 0x3b },
289 { STV090x_P1_MODCODLST0, 0xff },
290 { STV090x_P1_MODCODLST1, 0xff },
291 { STV090x_P1_MODCODLST2, 0xff },
292 { STV090x_P1_MODCODLST3, 0xff },
293 { STV090x_P1_MODCODLST4, 0xff },
294 { STV090x_P1_MODCODLST5, 0xff },
295 { STV090x_P1_MODCODLST6, 0xff },
296 { STV090x_P1_MODCODLST7, 0xcc },
297 { STV090x_P1_MODCODLST8, 0xcc },
298 { STV090x_P1_MODCODLST9, 0xcc },
299 { STV090x_P1_MODCODLSTA, 0xcc },
300 { STV090x_P1_MODCODLSTB, 0xcc },
301 { STV090x_P1_MODCODLSTC, 0xcc },
302 { STV090x_P1_MODCODLSTD, 0xcc },
303 { STV090x_P1_MODCODLSTE, 0xcc },
304 { STV090x_P1_MODCODLSTF, 0xcf },
305 { STV090x_GENCFG, 0x1d },
306 { STV090x_NBITER_NF4, 0x37 },
307 { STV090x_NBITER_NF5, 0x29 },
308 { STV090x_NBITER_NF6, 0x37 },
309 { STV090x_NBITER_NF7, 0x33 },
310 { STV090x_NBITER_NF8, 0x31 },
311 { STV090x_NBITER_NF9, 0x2f },
312 { STV090x_NBITER_NF10, 0x39 },
313 { STV090x_NBITER_NF11, 0x3a },
314 { STV090x_NBITER_NF12, 0x29 },
315 { STV090x_NBITER_NF13, 0x37 },
316 { STV090x_NBITER_NF14, 0x33 },
317 { STV090x_NBITER_NF15, 0x2f },
318 { STV090x_NBITER_NF16, 0x39 },
319 { STV090x_NBITER_NF17, 0x3a },
320 { STV090x_NBITERNOERR, 0x04 },
321 { STV090x_GAINLLR_NF4, 0x0C },
322 { STV090x_GAINLLR_NF5, 0x0F },
323 { STV090x_GAINLLR_NF6, 0x11 },
324 { STV090x_GAINLLR_NF7, 0x14 },
325 { STV090x_GAINLLR_NF8, 0x17 },
326 { STV090x_GAINLLR_NF9, 0x19 },
327 { STV090x_GAINLLR_NF10, 0x20 },
328 { STV090x_GAINLLR_NF11, 0x21 },
329 { STV090x_GAINLLR_NF12, 0x0D },
330 { STV090x_GAINLLR_NF13, 0x0F },
331 { STV090x_GAINLLR_NF14, 0x13 },
332 { STV090x_GAINLLR_NF15, 0x1A },
333 { STV090x_GAINLLR_NF16, 0x1F },
334 { STV090x_GAINLLR_NF17, 0x21 },
56571507 335 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 336 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
337 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
338 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
339 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
340};
341
342static struct stv090x_reg stv0903_initval[] = {
343 { STV090x_OUTCFG, 0x00 },
344 { STV090x_AGCRF1CFG, 0x11 },
345 { STV090x_STOPCLK1, 0x48 },
346 { STV090x_STOPCLK2, 0x14 },
347 { STV090x_TSTTNR1, 0x27 },
348 { STV090x_TSTTNR2, 0x21 },
349 { STV090x_P1_DISTXCTL, 0x22 },
350 { STV090x_P1_F22TX, 0xc0 },
351 { STV090x_P1_F22RX, 0xc0 },
352 { STV090x_P1_DISRXCTL, 0x00 },
353 { STV090x_P1_DMDCFGMD, 0xF9 },
354 { STV090x_P1_DEMOD, 0x08 },
355 { STV090x_P1_DMDCFG3, 0xc4 },
356 { STV090x_P1_CARFREQ, 0xed },
357 { STV090x_P1_TNRCFG2, 0x82 },
358 { STV090x_P1_LDT, 0xd0 },
359 { STV090x_P1_LDT2, 0xb8 },
360 { STV090x_P1_TMGCFG, 0xd2 },
361 { STV090x_P1_TMGTHRISE, 0x20 },
362 { STV090x_P1_TMGTHFALL, 0x00 },
363 { STV090x_P1_SFRUPRATIO, 0xf0 },
364 { STV090x_P1_SFRLOWRATIO, 0x70 },
365 { STV090x_P1_TSCFGL, 0x20 },
366 { STV090x_P1_FECSPY, 0x88 },
367 { STV090x_P1_FSPYDATA, 0x3a },
368 { STV090x_P1_FBERCPT4, 0x00 },
369 { STV090x_P1_FSPYBER, 0x10 },
370 { STV090x_P1_ERRCTRL1, 0x35 },
371 { STV090x_P1_ERRCTRL2, 0xc1 },
372 { STV090x_P1_CFRICFG, 0xf8 },
373 { STV090x_P1_NOSCFG, 0x1c },
56571507 374 { STV090x_P1_DMDTOM, 0x20 },
e415c689
MA		 375 { STV090x_P1_CORRELMANT, 0x70 },
376 { STV090x_P1_CORRELABS, 0x88 },
56571507
MA		 377 { STV090x_P1_AGC2O, 0x5b },
378 { STV090x_P1_AGC2REF, 0x38 },
e415c689
MA		 379 { STV090x_P1_CARCFG, 0xe4 },
380 { STV090x_P1_ACLC, 0x1A },
56571507 381 { STV090x_P1_BCLC, 0x09 },
e415c689
MA		 382 { STV090x_P1_CARHDR, 0x08 },
383 { STV090x_P1_KREFTMG, 0xc1 },
384 { STV090x_P1_SFRSTEP, 0x58 },
385 { STV090x_P1_TMGCFG2, 0x01 },
386 { STV090x_P1_CAR2CFG, 0x26 },
387 { STV090x_P1_BCLC2S2Q, 0x86 },
388 { STV090x_P1_BCLC2S28, 0x86 },
389 { STV090x_P1_SMAPCOEF7, 0x77 },
390 { STV090x_P1_SMAPCOEF6, 0x85 },
391 { STV090x_P1_SMAPCOEF5, 0x77 },
392 { STV090x_P1_DMDCFG2, 0x3b },
393 { STV090x_P1_MODCODLST0, 0xff },
394 { STV090x_P1_MODCODLST1, 0xff },
395 { STV090x_P1_MODCODLST2, 0xff },
396 { STV090x_P1_MODCODLST3, 0xff },
397 { STV090x_P1_MODCODLST4, 0xff },
398 { STV090x_P1_MODCODLST5, 0xff },
399 { STV090x_P1_MODCODLST6, 0xff },
400 { STV090x_P1_MODCODLST7, 0xcc },
401 { STV090x_P1_MODCODLST8, 0xcc },
402 { STV090x_P1_MODCODLST9, 0xcc },
403 { STV090x_P1_MODCODLSTA, 0xcc },
404 { STV090x_P1_MODCODLSTB, 0xcc },
405 { STV090x_P1_MODCODLSTC, 0xcc },
406 { STV090x_P1_MODCODLSTD, 0xcc },
407 { STV090x_P1_MODCODLSTE, 0xcc },
408 { STV090x_P1_MODCODLSTF, 0xcf },
409 { STV090x_GENCFG, 0x1c },
410 { STV090x_NBITER_NF4, 0x37 },
411 { STV090x_NBITER_NF5, 0x29 },
412 { STV090x_NBITER_NF6, 0x37 },
413 { STV090x_NBITER_NF7, 0x33 },
414 { STV090x_NBITER_NF8, 0x31 },
415 { STV090x_NBITER_NF9, 0x2f },
416 { STV090x_NBITER_NF10, 0x39 },
417 { STV090x_NBITER_NF11, 0x3a },
418 { STV090x_NBITER_NF12, 0x29 },
419 { STV090x_NBITER_NF13, 0x37 },
420 { STV090x_NBITER_NF14, 0x33 },
421 { STV090x_NBITER_NF15, 0x2f },
422 { STV090x_NBITER_NF16, 0x39 },
423 { STV090x_NBITER_NF17, 0x3a },
424 { STV090x_NBITERNOERR, 0x04 },
425 { STV090x_GAINLLR_NF4, 0x0C },
426 { STV090x_GAINLLR_NF5, 0x0F },
427 { STV090x_GAINLLR_NF6, 0x11 },
428 { STV090x_GAINLLR_NF7, 0x14 },
429 { STV090x_GAINLLR_NF8, 0x17 },
430 { STV090x_GAINLLR_NF9, 0x19 },
431 { STV090x_GAINLLR_NF10, 0x20 },
432 { STV090x_GAINLLR_NF11, 0x21 },
433 { STV090x_GAINLLR_NF12, 0x0D },
434 { STV090x_GAINLLR_NF13, 0x0F },
435 { STV090x_GAINLLR_NF14, 0x13 },
436 { STV090x_GAINLLR_NF15, 0x1A },
437 { STV090x_GAINLLR_NF16, 0x1F },
438 { STV090x_GAINLLR_NF17, 0x21 },
56571507 439 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 440 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
441 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
442};
443
444static struct stv090x_reg stv0900_cut20_val[] = {
445
446 { STV090x_P2_DMDCFG3, 0xe8 },
56571507 447 { STV090x_P2_DMDCFG4, 0x10 },
e415c689
MA		 448 { STV090x_P2_CARFREQ, 0x38 },
449 { STV090x_P2_CARHDR, 0x20 },
450 { STV090x_P2_KREFTMG, 0x5a },
451 { STV090x_P2_SMAPCOEF7, 0x06 },
452 { STV090x_P2_SMAPCOEF6, 0x00 },
453 { STV090x_P2_SMAPCOEF5, 0x04 },
454 { STV090x_P2_NOSCFG, 0x0c },
455 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 456 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 457 { STV090x_P1_CARFREQ, 0x38 },
458 { STV090x_P1_CARHDR, 0x20 },
459 { STV090x_P1_KREFTMG, 0x5a },
460 { STV090x_P1_SMAPCOEF7, 0x06 },
461 { STV090x_P1_SMAPCOEF6, 0x00 },
462 { STV090x_P1_SMAPCOEF5, 0x04 },
463 { STV090x_P1_NOSCFG, 0x0c },
464 { STV090x_GAINLLR_NF4, 0x21 },
465 { STV090x_GAINLLR_NF5, 0x21 },
466 { STV090x_GAINLLR_NF6, 0x20 },
467 { STV090x_GAINLLR_NF7, 0x1F },
468 { STV090x_GAINLLR_NF8, 0x1E },
469 { STV090x_GAINLLR_NF9, 0x1E },
470 { STV090x_GAINLLR_NF10, 0x1D },
471 { STV090x_GAINLLR_NF11, 0x1B },
472 { STV090x_GAINLLR_NF12, 0x20 },
473 { STV090x_GAINLLR_NF13, 0x20 },
474 { STV090x_GAINLLR_NF14, 0x20 },
475 { STV090x_GAINLLR_NF15, 0x20 },
476 { STV090x_GAINLLR_NF16, 0x20 },
477 { STV090x_GAINLLR_NF17, 0x21 },
478};
479
480static struct stv090x_reg stv0903_cut20_val[] = {
481 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 482 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 483 { STV090x_P1_CARFREQ, 0x38 },
484 { STV090x_P1_CARHDR, 0x20 },
485 { STV090x_P1_KREFTMG, 0x5a },
486 { STV090x_P1_SMAPCOEF7, 0x06 },
487 { STV090x_P1_SMAPCOEF6, 0x00 },
488 { STV090x_P1_SMAPCOEF5, 0x04 },
489 { STV090x_P1_NOSCFG, 0x0c },
490 { STV090x_GAINLLR_NF4, 0x21 },
491 { STV090x_GAINLLR_NF5, 0x21 },
492 { STV090x_GAINLLR_NF6, 0x20 },
493 { STV090x_GAINLLR_NF7, 0x1F },
494 { STV090x_GAINLLR_NF8, 0x1E },
495 { STV090x_GAINLLR_NF9, 0x1E },
496 { STV090x_GAINLLR_NF10, 0x1D },
497 { STV090x_GAINLLR_NF11, 0x1B },
498 { STV090x_GAINLLR_NF12, 0x20 },
499 { STV090x_GAINLLR_NF13, 0x20 },
500 { STV090x_GAINLLR_NF14, 0x20 },
501 { STV090x_GAINLLR_NF15, 0x20 },
502 { STV090x_GAINLLR_NF16, 0x20 },
503 { STV090x_GAINLLR_NF17, 0x21 }
504};
505
506/* Cut 1.x Long Frame Tracking CR loop */
507static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
508 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
509 { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
510 { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
511 { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
512 { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
513 { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
514 { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
515 { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
516 { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
517 { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
518 { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
519 { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
520 { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
521 { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
522 { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
523};
524
525/* Cut 2.0 Long Frame Tracking CR loop */
526static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
527 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
528 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
529 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
530 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
531 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
532 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
533 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
534 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
535 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
536 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
537 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
538 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
539 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
540 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
541 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
542};
543
544
545/* Cut 2.0 Long Frame Tracking CR Loop */
546static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
547 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
548 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
549 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
550 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
551 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
552 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
553 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
554 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
555 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
556 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
557 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
558 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
559};
560
561
562static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
563 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
564 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
565 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
566 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
567};
568
569
570/* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
571static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
572 /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
573 { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
574 { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
575 { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
576 { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
577};
578
579
580static inline s32 comp2(s32 __x, s32 __width)
581{
582 if (__width == 32)
583 return __x;
584 else
585 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
586}
587
588static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
589{
590 const struct stv090x_config *config = state->config;
591 int ret;
592
593 u8 b0[] = { reg >> 8, reg & 0xff };
594 u8 buf;
595
596 struct i2c_msg msg[] = {
597 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
598 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
599 };
600
601 ret = i2c_transfer(state->i2c, msg, 2);
602 if (ret != 2) {
603 if (ret != -ERESTARTSYS)
604 dprintk(FE_ERROR, 1,
605 "Read error, Reg=[0x%02x], Status=%d",
606 reg, ret);
607
608 return ret < 0 ? ret : -EREMOTEIO;
609 }
610 if (unlikely(*state->verbose >= FE_DEBUGREG))
611 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
612 reg, buf);
613
614 return (unsigned int) buf;
615}
616
617static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
618{
619 const struct stv090x_config *config = state->config;
620 int ret;
621 u8 buf[2 + count];
622 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
623
624 buf[0] = reg >> 8;
625 buf[1] = reg & 0xff;
626 memcpy(&buf[2], data, count);
627
628 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
629 int i;
630
631 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
632 for (i = 0; i < count; i++)
633 printk(" %02x", data[i]);
634 printk("\n");
635 }
636
637 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
638 if (ret != 1) {
639 if (ret != -ERESTARTSYS)
640 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
641 reg, data[0], count, ret);
642 return ret < 0 ? ret : -EREMOTEIO;
643 }
644
645 return 0;
646}
647
648static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
649{
650 return stv090x_write_regs(state, reg, &data, 1);
651}
652
653static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
654{
655 struct stv090x_state *state = fe->demodulator_priv;
656 u32 reg;
657
658 reg = STV090x_READ_DEMOD(state, I2CRPT);
e415c689 659 if (enable) {
017eb038 660 dprintk(FE_DEBUG, 1, "Enable Gate");
e415c689
MA		 661 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
662 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
663 goto err;
664
665 } else {
017eb038 666 dprintk(FE_DEBUG, 1, "Disable Gate");
e415c689
MA		 667 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
668 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
669 goto err;
670 }
671 return 0;
672err:
673 dprintk(FE_ERROR, 1, "I/O error");
674 return -1;
675}
676
677static void stv090x_get_lock_tmg(struct stv090x_state *state)
678{
679 switch (state->algo) {
680 case STV090x_BLIND_SEARCH:
681 dprintk(FE_DEBUG, 1, "Blind Search");
682 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
683 state->DemodTimeout = 1500;
684 state->FecTimeout = 400;
685 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
686 state->DemodTimeout = 1000;
687 state->FecTimeout = 300;
688 } else { /*SR >20Msps*/
689 state->DemodTimeout = 700;
690 state->FecTimeout = 100;
691 }
692 break;
693
694 case STV090x_COLD_SEARCH:
695 case STV090x_WARM_SEARCH:
696 default:
697 dprintk(FE_DEBUG, 1, "Normal Search");
698 if (state->srate <= 1000000) { /*SR <=1Msps*/
699 state->DemodTimeout = 4500;
700 state->FecTimeout = 1700;
701 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
702 state->DemodTimeout = 2500;
703 state->FecTimeout = 1100;
704 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
705 state->DemodTimeout = 1000;
706 state->FecTimeout = 550;
707 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
708 state->DemodTimeout = 700;
709 state->FecTimeout = 250;
710 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
711 state->DemodTimeout = 400;
712 state->FecTimeout = 130;
713 } else { /*SR >20Msps*/
714 state->DemodTimeout = 300;
715 state->FecTimeout = 100;
716 }
717 break;
718 }
719
720 if (state->algo == STV090x_WARM_SEARCH)
721 state->DemodTimeout /= 2;
722}
723
724static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
725{
726 u32 sym;
727
15bb366e
MA		 728 if (srate > 60000000) {
729 sym = (srate << 4); /* SR * 2^16 / master_clk */
730 sym /= (state->mclk >> 12);
731 } else if (srate > 6000000) {
732 sym = (srate << 6);
733 sym /= (state->mclk >> 10);
e415c689 734 } else {
15bb366e
MA		 735 sym = (srate << 9);
736 sym /= (state->mclk >> 7);
e415c689
MA		 737 }
738
15bb366e 739 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
e415c689
MA		 740 goto err;
741 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
742 goto err;
15bb366e 743
e415c689
MA		 744 return 0;
745err:
746 dprintk(FE_ERROR, 1, "I/O error");
747 return -1;
748}
749
750static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
751{
752 u32 sym;
753
754 srate = 105 * (srate / 100);
15bb366e
MA		 755 if (srate > 60000000) {
756 sym = (srate << 4); /* SR * 2^16 / master_clk */
757 sym /= (state->mclk >> 12);
758 } else if (srate > 6000000) {
759 sym = (srate << 6);
760 sym /= (state->mclk >> 10);
e415c689 761 } else {
15bb366e
MA		 762 sym = (srate << 9);
763 sym /= (state->mclk >> 7);
e415c689 764 }
15bb366e
MA		 765
766 if (sym < 0x7fff) {
767 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
768 goto err;
769 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
770 goto err;
771 } else {
772 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
773 goto err;
774 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
775 goto err;
776 }
777
e415c689
MA		 778 return 0;
779err:
780 dprintk(FE_ERROR, 1, "I/O error");
781 return -1;
782}
783
784static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
785{
786 u32 sym;
787
788 srate = 95 * (srate / 100);
15bb366e
MA		 789 if (srate > 60000000) {
790 sym = (srate << 4); /* SR * 2^16 / master_clk */
791 sym /= (state->mclk >> 12);
792 } else if (srate > 6000000) {
793 sym = (srate << 6);
794 sym /= (state->mclk >> 10);
e415c689 795 } else {
15bb366e
MA		 796 sym = (srate << 9);
797 sym /= (state->mclk >> 7);
e415c689 798 }
15bb366e 799
e415c689
MA		 800 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
801 goto err;
802 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
803 goto err;
804 return 0;
805err:
806 dprintk(FE_ERROR, 1, "I/O error");
807 return -1;
808}
809
4e58a682 810static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
e415c689 811{
4e58a682
AR		 812 u32 ro;
813
814 switch (rolloff) {
815 case STV090x_RO_20:
816 ro = 20;
817 break;
818 case STV090x_RO_25:
819 ro = 25;
820 break;
821 case STV090x_RO_35:
822 default:
823 ro = 35;
824 break;
825 }
826
827 return srate + (srate * ro) / 100;
e415c689
MA		 828}
829
830static int stv090x_set_vit_thacq(struct stv090x_state *state)
831{
832 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
833 goto err;
834 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
835 goto err;
836 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
837 goto err;
838 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
839 goto err;
840 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
841 goto err;
842 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
843 goto err;
844 return 0;
845err:
846 dprintk(FE_ERROR, 1, "I/O error");
847 return -1;
848}
849
850static int stv090x_set_vit_thtracq(struct stv090x_state *state)
851{
852 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
853 goto err;
854 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
855 goto err;
856 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
857 goto err;
858 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
859 goto err;
860 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
861 goto err;
862 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
863 goto err;
864 return 0;
865err:
866 dprintk(FE_ERROR, 1, "I/O error");
867 return -1;
868}
869
870static int stv090x_set_viterbi(struct stv090x_state *state)
871{
872 switch (state->search_mode) {
873 case STV090x_SEARCH_AUTO:
874 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
875 goto err;
876 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
877 goto err;
878 break;
879 case STV090x_SEARCH_DVBS1:
880 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
881 goto err;
882 switch (state->fec) {
883 case STV090x_PR12:
884 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
885 goto err;
886 break;
887
888 case STV090x_PR23:
889 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
890 goto err;
891 break;
892
893 case STV090x_PR34:
894 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
895 goto err;
896 break;
897
898 case STV090x_PR56:
899 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
900 goto err;
901 break;
902
903 case STV090x_PR78:
904 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
905 goto err;
906 break;
907
908 default:
909 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
910 goto err;
911 break;
912 }
913 break;
914 case STV090x_SEARCH_DSS:
915 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
916 goto err;
917 switch (state->fec) {
918 case STV090x_PR12:
919 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
920 goto err;
921 break;
922
923 case STV090x_PR23:
924 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
925 goto err;
926 break;
927
928 case STV090x_PR67:
929 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
930 goto err;
931 break;
932
933 default:
934 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
935 goto err;
936 break;
937 }
938 break;
939 default:
940 break;
941 }
942 return 0;
943err:
944 dprintk(FE_ERROR, 1, "I/O error");
945 return -1;
946}
947
948static int stv090x_stop_modcod(struct stv090x_state *state)
949{
950 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
951 goto err;
952 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
953 goto err;
954 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
955 goto err;
956 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
957 goto err;
958 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
959 goto err;
960 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
961 goto err;
962 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
963 goto err;
964 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
965 goto err;
966 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
967 goto err;
968 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
969 goto err;
970 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
971 goto err;
972 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
973 goto err;
974 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
975 goto err;
976 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
977 goto err;
978 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
979 goto err;
980 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
981 goto err;
982 return 0;
983err:
984 dprintk(FE_ERROR, 1, "I/O error");
985 return -1;
986}
987
988static int stv090x_activate_modcod(struct stv090x_state *state)
989{
990 u32 matype, modcod, f_mod, index;
991
992 if (state->dev_ver <= 0x11) {
993 msleep(5);
994 modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
995 matype = modcod & 0x03;
996 modcod = (modcod & 0x7f) >> 2;
997 index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
998
999 switch (matype) {
1000 default:
1001 case 0:
1002 f_mod = 14;
1003 break;
1004 case 1:
1005 f_mod = 13;
1006 break;
1007 case 2:
1008 f_mod = 11;
1009 break;
1010 case 3:
1011 f_mod = 7;
1012 break;
1013 }
1014 if (matype <= 1) {
1015 if (modcod % 2) {
1016 if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
1017 goto err;
1018 } else {
1019 if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
1020 goto err;
1021 }
1022 }
1023 } else if (state->dev_ver >= 0x12) {
1024 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1025 goto err;
1026 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1027 goto err;
1028 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1029 goto err;
1030 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1031 goto err;
1032 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1033 goto err;
1034 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1035 goto err;
1036 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1037 goto err;
1038 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1039 goto err;
1040 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1041 goto err;
1042 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1043 goto err;
1044 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1045 goto err;
1046 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1047 goto err;
1048 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1049 goto err;
1050 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1051 goto err;
1052 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1053 goto err;
1054 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1055 goto err;
1056 }
1057 return 0;
1058err:
1059 dprintk(FE_ERROR, 1, "I/O error");
1060 return -1;
1061}
1062
1063static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1064{
1065 u32 reg;
1066
1067 switch (state->demod) {
1068 case STV090x_DEMODULATOR_0:
1069 mutex_lock(&demod_lock);
1070 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1071 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1072 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1073 goto err;
1074 mutex_unlock(&demod_lock);
1075 break;
1076
1077 case STV090x_DEMODULATOR_1:
1078 mutex_lock(&demod_lock);
1079 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1080 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1081 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1082 goto err;
1083 mutex_unlock(&demod_lock);
1084 break;
1085
1086 default:
1087 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1088 break;
1089 }
1090 return 0;
1091err:
1092 mutex_unlock(&demod_lock);
1093 dprintk(FE_ERROR, 1, "I/O error");
1094 return -1;
1095}
1096
1097static int stv090x_delivery_search(struct stv090x_state *state)
1098{
1099 u32 reg;
1100
1101 switch (state->search_mode) {
1102 case STV090x_SEARCH_DVBS1:
1103 case STV090x_SEARCH_DSS:
1104 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1105 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1106 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1107 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1108 goto err;
1109
1110 /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
1111 if (stv090x_vitclk_ctl(state, 0) < 0)
1112 goto err;
1113
1114 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1115 goto err;
1116 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1117 goto err;
1118 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1119 goto err;
1120
1121 stv090x_set_vit_thacq(state);
1122 stv090x_set_viterbi(state);
1123 break;
1124
1125 case STV090x_SEARCH_DVBS2:
1126 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1127 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1128 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1129 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1130 goto err;
1131 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1132 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1133 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1134 goto err;
1135
1136 if (stv090x_vitclk_ctl(state, 1) < 0)
1137 goto err;
1138
1139 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1140 goto err;
1141 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1142 goto err;
1143 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1144 goto err;
1145
1146 if (state->demod_mode != STV090x_SINGLE) {
1147 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1148 stv090x_stop_modcod(state);
1149 else
1150 stv090x_activate_modcod(state);
1151 }
1152 break;
1153
1154 case STV090x_SEARCH_AUTO:
1155 default:
1156 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1157 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1158 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1159 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1160 goto err;
1161 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1162 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1163 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1164 goto err;
1165
4e58a682 1166 if (stv090x_vitclk_ctl(state, 0) < 0)
e415c689
MA		 1167 goto err;
1168
1169 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1170 goto err;
4e58a682 1171 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
e415c689
MA		 1172 goto err;
1173 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1174 goto err;
1175
1176 if (state->demod_mode != STV090x_SINGLE) {
1177 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1178 stv090x_stop_modcod(state);
1179 else
1180 stv090x_activate_modcod(state);
1181 }
1182 stv090x_set_vit_thacq(state);
1183 stv090x_set_viterbi(state);
1184 break;
1185 }
1186 return 0;
1187err:
1188 dprintk(FE_ERROR, 1, "I/O error");
1189 return -1;
1190}
1191
1192static int stv090x_start_search(struct stv090x_state *state)
1193{
1194 u32 reg;
1195
1196 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1197 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1198 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1199 goto err;
1200
1201 if (state->dev_ver == 0x10) {
1202 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1203 goto err;
1204 }
1205 if (state->dev_ver < 0x20) {
1206 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1207 goto err;
1208 }
1209 if (state->srate <= 5000000) {
1210 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1211 goto err;
1212 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1213 goto err;
1214 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
1215 goto err;
1216 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1217 goto err;
1218 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1219 goto err;
1220
1221 /*enlarge the timing bandwith for Low SR*/
1222 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1223 goto err;
1224 } else {
1225 /* If the symbol rate is >5 Msps
1226 Set The carrier search up and low to auto mode */
1227 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1228 goto err;
1229 /*reduce the timing bandwith for high SR*/
1230 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1231 goto err;
1232 }
1233 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1234 goto err;
1235 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1236 goto err;
1237
1238 if (state->dev_ver >= 0x20) {
1239 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1240 goto err;
1241 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1242 goto err;
1243
1244 if ((state->search_mode == STV090x_DVBS1) ||
1245 (state->search_mode == STV090x_DSS) ||
1246 (state->search_mode == STV090x_SEARCH_AUTO)) {
1247
1248 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1249 goto err;
1250 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1251 goto err;
1252 }
1253 }
1254
1255 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1256 goto err;
1257 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1258 goto err;
1259 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1260 goto err;
1261
1262 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1263 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1264 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1265 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1266 goto err;
1267 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1268 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1269 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1270 goto err;
1271
1272 if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
1273 if (state->srate < 10000000) {
1274 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1275 goto err;
1276 } else {
1277 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1278 goto err;
1279 }
1280 } else {
1281 if (state->srate < 10000000) {
1282 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1283 goto err;
1284 } else {
1285 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1286 goto err;
1287 }
1288 }
1289
1290 switch (state->algo) {
1291 case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
1292 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1293 goto err;
1294 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1295 goto err;
1296 break;
1297
1298 case STV090x_COLD_SEARCH:/*The symbol rate is known*/
1299 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1300 goto err;
1301 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1302 goto err;
1303 break;
1304
1305 default:
1306 break;
1307 }
1308 return 0;
1309err:
1310 dprintk(FE_ERROR, 1, "I/O error");
1311 return -1;
1312}
1313
1314static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1315{
1316 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
1317 s32 i, j, steps, dir;
1318
1319 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1320 goto err;
1321 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1322 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1323 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1324 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1325 goto err;
1326
1327 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1328 goto err;
1329 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1330 goto err;
1331 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1332 goto err;
1333 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1334 goto err;
1335 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1336 goto err;
1337 stv090x_set_srate(state, 1000000);
1338
1339 steps = -1 + state->search_range / 1000000;
1340 steps /= 2;
1341 steps = (2 * steps) + 1;
1342 if (steps < 0)
1343 steps = 1;
1344
1345 dir = 1;
1346 freq_step = (1000000 * 256) / (state->mclk / 256);
1347 freq_init = 0;
1348
1349 for (i = 0; i < steps; i++) {
1350 if (dir > 0)
1351 freq_init = freq_init + (freq_step * i);
1352 else
1353 freq_init = freq_init - (freq_step * i);
1354
1355 dir = -1;
1356
1357 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1358 goto err;
1359 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1360 goto err;
1361 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1362 goto err;
1363 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1364 goto err;
1365 msleep(10);
1366 for (j = 0; j < 10; j++) {
1367 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1368 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1369 }
1370 agc2 /= 10;
1371 agc2_min = 0xffff;
1372 if (agc2 < 0xffff)
1373 agc2_min = agc2;
1374 }
1375
1376 return agc2_min;
1377err:
1378 dprintk(FE_ERROR, 1, "I/O error");
1379 return -1;
1380}
1381
1382static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1383{
1384 u8 r3, r2, r1, r0;
1385 s32 srate, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 1386
1387 r3 = STV090x_READ_DEMOD(state, SFR3);
1388 r2 = STV090x_READ_DEMOD(state, SFR2);
1389 r1 = STV090x_READ_DEMOD(state, SFR1);
1390 r0 = STV090x_READ_DEMOD(state, SFR0);
1391
1392 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1393
f430fff1
MA		 1394 int_1 = clk >> 16;
1395 int_2 = srate >> 16;
e415c689 1396
f430fff1
MA		 1397 tmp_1 = clk % 0x10000;
1398 tmp_2 = srate % 0x10000;
e415c689
MA		 1399
1400 srate = (int_1 * int_2) +
f430fff1
MA		 1401 ((int_1 * tmp_2) >> 16) +
1402 ((int_2 * tmp_1) >> 16);
e415c689
MA		 1403
1404 return srate;
1405}
1406
1407static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1408{
1409 struct dvb_frontend *fe = &state->frontend;
1410
1411 int tmg_lock = 0, i;
1412 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1413 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1414
1415 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1416 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1417 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1418 goto err;
1419 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1420 goto err;
1421 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1422 goto err;
1423 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1424 goto err;
1425 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1426 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1427 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1428 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1429 goto err;
1430
1431 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1432 goto err;
1433 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1434 goto err;
1435 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1436 goto err;
1437 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1438 goto err;
1439 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1440 goto err;
1441 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
1442 goto err;
1443
1444 if (state->dev_ver >= 0x20) {
1445 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1446 goto err;
1447 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1448 goto err;
1449 } else {
1450 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1451 goto err;
1452 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
1453 goto err;
1454 }
1455
1456 if (state->srate <= 2000000)
1457 car_step = 1000;
1458 else if (state->srate <= 5000000)
1459 car_step = 2000;
1460 else if (state->srate <= 12000000)
1461 car_step = 3000;
1462 else
1463 car_step = 5000;
1464
1465 steps = -1 + ((state->search_range / 1000) / car_step);
1466 steps /= 2;
1467 steps = (2 * steps) + 1;
1468 if (steps < 0)
1469 steps = 1;
1470 else if (steps > 10) {
1471 steps = 11;
1472 car_step = (state->search_range / 1000) / 10;
1473 }
1474 cur_step = 0;
1475 dir = 1;
1476 freq = state->frequency;
1477
1478 while ((!tmg_lock) && (cur_step < steps)) {
1479 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1480 goto err;
1481 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1482 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1483 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1484 goto err;
1485 msleep(50);
1486 for (i = 0; i < 10; i++) {
1487 reg = STV090x_READ_DEMOD(state, DSTATUS);
1488 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1489 tmg_cpt++;
1490 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1491 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1492 }
1493 agc2 /= 10;
1494 srate_coarse = stv090x_get_srate(state, state->mclk);
1495 cur_step++;
1496 dir *= -1;
1497 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
1498 tmg_lock = 1;
1499 else if (cur_step < steps) {
1500 if (dir > 0)
1501 freq += cur_step * car_step;
1502 else
1503 freq -= cur_step * car_step;
1504
1505 /* Setup tuner */
1506 stv090x_i2c_gate_ctrl(fe, 1);
1507
1508 if (state->config->tuner_set_frequency)
1509 state->config->tuner_set_frequency(fe, state->frequency);
1510
1511 if (state->config->tuner_set_bandwidth)
1512 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1513
1514 stv090x_i2c_gate_ctrl(fe, 0);
1515 msleep(50);
1516 stv090x_i2c_gate_ctrl(fe, 1);
1517
1518 if (state->config->tuner_get_status)
1519 state->config->tuner_get_status(fe, &reg);
1520
1521 if (reg)
1522 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1523 else
1524 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1525
1526 stv090x_i2c_gate_ctrl(fe, 0);
1527
1528 }
1529 }
1530 if (!tmg_lock)
1531 srate_coarse = 0;
1532 else
1533 srate_coarse = stv090x_get_srate(state, state->mclk);
1534
1535 return srate_coarse;
1536err:
1537 dprintk(FE_ERROR, 1, "I/O error");
1538 return -1;
1539}
1540
1541static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1542{
1543 u32 srate_coarse, freq_coarse, sym, reg;
1544
1545 srate_coarse = stv090x_get_srate(state, state->mclk);
1546 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1547 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1548 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1549
1550 if (sym < state->srate)
1551 srate_coarse = 0;
1552 else {
1553 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1554 goto err;
1555 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1556 goto err;
1557 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1558 goto err;
1559 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1560 goto err;
1561 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1562 goto err;
1563 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1564 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1565 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1566 goto err;
1567
1568 if (state->dev_ver >= 0x20) {
1569 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1570 goto err;
1571 } else {
1572 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1573 goto err;
1574 }
1575
1576 if (srate_coarse > 3000000) {
1577 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1578 sym = (sym / 1000) * 65536;
1579 sym /= (state->mclk / 1000);
1580 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1581 goto err;
1582 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1583 goto err;
1584 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1585 sym = (sym / 1000) * 65536;
1586 sym /= (state->mclk / 1000);
1587 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1588 goto err;
1589 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1590 goto err;
1591 sym = (srate_coarse / 1000) * 65536;
1592 sym /= (state->mclk / 1000);
1593 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1594 goto err;
1595 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1596 goto err;
1597 } else {
1598 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1599 sym = (sym / 100) * 65536;
1600 sym /= (state->mclk / 100);
1601 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1602 goto err;
1603 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1604 goto err;
1605 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1606 sym = (sym / 100) * 65536;
1607 sym /= (state->mclk / 100);
1608 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1609 goto err;
1610 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1611 goto err;
1612 sym = (srate_coarse / 100) * 65536;
1613 sym /= (state->mclk / 100);
1614 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1615 goto err;
1616 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1617 goto err;
1618 }
1619 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1620 goto err;
1621 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1622 goto err;
1623 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1624 goto err;
1625 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1626 goto err;
1627 }
1628
1629 return srate_coarse;
1630
1631err:
1632 dprintk(FE_ERROR, 1, "I/O error");
1633 return -1;
1634}
1635
1636static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1637{
1638 s32 timer = 0, lock = 0;
1639 u32 reg;
1640 u8 stat;
1641
1642 while ((timer < timeout) && (!lock)) {
1643 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1644 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1645
1646 switch (stat) {
1647 case 0: /* searching */
1648 case 1: /* first PLH detected */
1649 default:
1650 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1651 lock = 0;
1652 break;
1653 case 2: /* DVB-S2 mode */
1654 case 3: /* DVB-S1/legacy mode */
1655 reg = STV090x_READ_DEMOD(state, DSTATUS);
1656 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1657 break;
1658 }
1659
1660 if (!lock)
1661 msleep(10);
1662 else
1663 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1664
1665 timer += 10;
1666 }
1667 return lock;
1668}
1669
1670static int stv090x_blind_search(struct stv090x_state *state)
1671{
1672 u32 agc2, reg, srate_coarse;
1673 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1674 u8 k_ref, k_max, k_min;
1675 int coarse_fail, lock;
1676
1677 if (state->dev_ver < 0x20) {
1678 k_max = 233;
1679 k_min = 143;
1680 } else {
1681 k_max = 120;
1682 k_min = 30;
1683 }
1684
1685 agc2 = stv090x_get_agc2_min_level(state);
1686
1687 if (agc2 > STV090x_SEARCH_AGC2_TH) {
1688 lock = 0;
1689 } else {
1690 if (state->dev_ver == 0x10) {
1691 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1692 goto err;
1693 }
1694 if (state->dev_ver < 0x20) {
1695 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1696 goto err;
1697 }
1698
1699 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1700 goto err;
1701 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1702 goto err;
1703 if (state->dev_ver >= 0x20) {
1704 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1705 goto err;
1706 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1707 goto err;
1708 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1709 goto err;
1710 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1711 goto err;
1712 }
1713
1714 k_ref = k_max;
1715 do {
1716 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1717 goto err;
1718 if (stv090x_srate_srch_coarse(state) != 0) {
1719 srate_coarse = stv090x_srate_srch_fine(state);
1720 if (srate_coarse != 0) {
1721 stv090x_get_lock_tmg(state);
1722 lock = stv090x_get_dmdlock(state, timeout_dmd);
1723 } else {
1724 lock = 0;
1725 }
1726 } else {
1727 cpt_fail = 0;
1728 agc2_ovflw = 0;
1729 for (i = 0; i < 10; i++) {
1730 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1731 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1732 if (agc2 >= 0xff00)
1733 agc2_ovflw++;
1734 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1735 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1736 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1737
1738 cpt_fail++;
1739 }
1740 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1741 coarse_fail = 1;
1742
1743 lock = 0;
1744 }
1745 k_ref -= 30;
1746 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1747 }
1748
1749 return lock;
1750
1751err:
1752 dprintk(FE_ERROR, 1, "I/O error");
1753 return -1;
1754}
1755
1756static int stv090x_chk_tmg(struct stv090x_state *state)
1757{
1758 u32 reg;
1759 s32 tmg_cpt, i;
1760 u8 freq, tmg_thh, tmg_thl;
1761 int tmg_lock;
1762
1763 freq = STV090x_READ_DEMOD(state, CARFREQ);
1764 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1765 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1766 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1767 goto err;
1768 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1769 goto err;
1770
1771 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1772 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1773 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1774 goto err;
1775 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1776 goto err;
1777
1778 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1779 goto err;
1780 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1781 goto err;
1782
1783 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1784 goto err;
1785 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1786 goto err;
1787 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1788 goto err;
1789
1790 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1791 goto err;
1792 msleep(10);
1793
1794 for (i = 0; i < 10; i++) {
1795 reg = STV090x_READ_DEMOD(state, DSTATUS);
1796 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1797 tmg_cpt++;
1798 msleep(1);
1799 }
1800 if (tmg_cpt >= 3)
1801 tmg_lock = 1;
1802
1803 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1804 goto err;
1805 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1806 goto err;
1807 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
1808 goto err;
1809
1810 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
1811 goto err;
1812 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
1813 goto err;
1814 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
1815 goto err;
1816
1817 return tmg_lock;
1818
1819err:
1820 dprintk(FE_ERROR, 1, "I/O error");
1821 return -1;
1822}
1823
1824static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
1825{
1826 struct dvb_frontend *fe = &state->frontend;
1827
1828 u32 reg;
1829 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
1830 int lock = 0;
1831
1832 if (state->srate >= 10000000)
1833 timeout_lock = timeout_dmd / 3;
1834 else
1835 timeout_lock = timeout_dmd / 2;
1836
1837 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
1838 if (!lock) {
1839 if (state->srate >= 10000000) {
1840 if (stv090x_chk_tmg(state)) {
1841 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1842 goto err;
1843 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1844 goto err;
1845 lock = stv090x_get_dmdlock(state, timeout_dmd);
1846 } else {
1847 lock = 0;
1848 }
1849 } else {
1850 if (state->srate <= 4000000)
1851 car_step = 1000;
1852 else if (state->srate <= 7000000)
1853 car_step = 2000;
1854 else if (state->srate <= 10000000)
1855 car_step = 3000;
1856 else
1857 car_step = 5000;
1858
1859 steps = (state->search_range / 1000) / car_step;
1860 steps /= 2;
1861 steps = 2 * (steps + 1);
1862 if (steps < 0)
1863 steps = 2;
1864 else if (steps > 12)
1865 steps = 12;
1866
1867 cur_step = 1;
1868 dir = 1;
1869
1870 if (!lock) {
1871 freq = state->frequency;
1872 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
1873 while ((cur_step <= steps) && (!lock)) {
1874 if (dir > 0)
1875 freq += cur_step * car_step;
1876 else
1877 freq -= cur_step * car_step;
1878
1879 /* Setup tuner */
1880 stv090x_i2c_gate_ctrl(fe, 1);
1881
1882 if (state->config->tuner_set_frequency)
1883 state->config->tuner_set_frequency(fe, state->frequency);
1884
1885 if (state->config->tuner_set_bandwidth)
1886 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1887
1888 stv090x_i2c_gate_ctrl(fe, 0);
1889
1890 msleep(50);
1891
1892 stv090x_i2c_gate_ctrl(fe, 1);
1893
1894 if (state->config->tuner_get_status)
1895 state->config->tuner_get_status(fe, &reg);
1896
1897 if (reg)
1898 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1899 else
1900 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1901
1902 stv090x_i2c_gate_ctrl(fe, 0);
1903
1904 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
1905 if (state->delsys == STV090x_DVBS2) {
1906 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1907 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1908 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1909 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1910 goto err;
1911 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1912 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1913 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1914 goto err;
1915 }
1916 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1917 goto err;
1918 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1919 goto err;
1920 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1921 goto err;
1922 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1923 goto err;
1924 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
1925
1926 dir *= -1;
1927 cur_step++;
1928 }
1929 }
1930 }
1931 }
1932
1933 return lock;
1934
1935err:
1936 dprintk(FE_ERROR, 1, "I/O error");
1937 return -1;
1938}
1939
1940static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
1941{
1942 s32 timeout, inc, steps_max, srate, car_max;
1943
1944 srate = state->srate;
1945 car_max = state->search_range / 1000;
1946 car_max = 65536 * (car_max / 2);
1947 car_max /= (state->mclk / 1000);
1948
1949 if (car_max > 0x4000)
1950 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
1951
1952 inc = srate;
1953 inc /= state->mclk / 1000;
1954 inc *= 256;
1955 inc *= 256;
1956 inc /= 1000;
1957
72982f76 1958 switch (state->search_mode) {
e415c689
MA		 1959 case STV090x_SEARCH_DVBS1:
1960 case STV090x_SEARCH_DSS:
1961 inc *= 3; /* freq step = 3% of srate */
1962 timeout = 20;
1963 break;
1964
1965 case STV090x_SEARCH_DVBS2:
1966 inc *= 4;
1967 timeout = 25;
1968 break;
1969
1970 case STV090x_SEARCH_AUTO:
1971 default:
1972 inc *= 3;
1973 timeout = 25;
1974 break;
1975 }
1976 inc /= 100;
1977 if ((inc > car_max) || (inc < 0))
1978 inc = car_max / 2; /* increment <= 1/8 Mclk */
1979
1980 timeout *= 27500; /* 27.5 Msps reference */
1981 if (srate > 0)
1982 timeout /= (srate / 1000);
1983
1984 if ((timeout > 100) || (timeout < 0))
1985 timeout = 100;
1986
1987 steps_max = (car_max / inc) + 1; /* min steps = 3 */
1988 if ((steps_max > 100) || (steps_max < 0)) {
1989 steps_max = 100; /* max steps <= 100 */
1990 inc = car_max / steps_max;
1991 }
1992 *freq_inc = inc;
1993 *timeout_sw = timeout;
1994 *steps = steps_max;
1995
1996 return 0;
1997}
1998
1999static int stv090x_chk_signal(struct stv090x_state *state)
2000{
2001 s32 offst_car, agc2, car_max;
2002 int no_signal;
2003
2004 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2005 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2006
2007 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2008 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2009 car_max = state->search_range / 1000;
2010
2011 car_max += (car_max / 10); /* 10% margin */
2012 car_max = (65536 * car_max / 2);
2013 car_max /= state->mclk / 1000;
2014
2015 if (car_max > 0x4000)
2016 car_max = 0x4000;
2017
2018 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2019 no_signal = 1;
2020 dprintk(FE_DEBUG, 1, "No Signal");
2021 } else {
2022 no_signal = 0;
2023 dprintk(FE_DEBUG, 1, "Found Signal");
2024 }
2025
2026 return no_signal;
2027}
2028
2029static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2030{
2031 int no_signal, lock = 0;
2032 s32 cpt_step, offst_freq, car_max;
2033 u32 reg;
2034
2035 car_max = state->search_range / 1000;
2036 car_max += (car_max / 10);
2037 car_max = (65536 * car_max / 2);
2038 car_max /= (state->mclk / 1000);
2039 if (car_max > 0x4000)
2040 car_max = 0x4000;
2041
2042 if (zigzag)
2043 offst_freq = 0;
2044 else
2045 offst_freq = -car_max + inc;
2046
2047 cpt_step = 0;
2048 do {
2049 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2050 goto err;
2051 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2052 goto err;
2053 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2054 goto err;
2055 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2056 goto err;
2057
2058 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2059 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2060 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2061 goto err;
2062
2063 if (state->dev_ver == 0x12) {
2064 reg = STV090x_READ_DEMOD(state, TSCFGH);
2065 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
2066 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2067 goto err;
2068 }
2069
2070 if (zigzag) {
2071 if (offst_freq >= 0)
2072 offst_freq = -offst_freq - 2 * inc;
2073 else
2074 offst_freq = -offst_freq;
2075 } else {
2076 offst_freq += 2 * inc;
2077 }
2078
2079 lock = stv090x_get_dmdlock(state, timeout);
2080 no_signal = stv090x_chk_signal(state);
2081
2082 } while ((!lock) &&
2083 (!no_signal) &&
2084 ((offst_freq - inc) < car_max) &&
2085 ((offst_freq + inc) > -car_max) &&
2086 (cpt_step < steps_max));
2087
2088 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2089 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2090 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2091 goto err;
2092
2093 return lock;
2094err:
2095 dprintk(FE_ERROR, 1, "I/O error");
2096 return -1;
2097}
2098
2099static int stv090x_sw_algo(struct stv090x_state *state)
2100{
2101 int no_signal, zigzag, lock = 0;
2102 u32 reg;
2103
2104 s32 dvbs2_fly_wheel;
2105 s32 inc, timeout_step, trials, steps_max;
2106
2107 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
2108
72982f76 2109 switch (state->search_mode) {
e415c689
MA		 2110 case STV090x_SEARCH_DVBS1:
2111 case STV090x_SEARCH_DSS:
2112 /* accelerate the frequency detector */
2113 if (state->dev_ver >= 0x20) {
2114 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2115 goto err;
2116 } else {
2117 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2118 goto err;
2119 }
2120 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2121 goto err;
2122 zigzag = 0;
2123 break;
2124
2125 case STV090x_SEARCH_DVBS2:
2126 if (state->dev_ver >= 0x20) {
2127 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2128 goto err;
2129 } else {
2130 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2131 goto err;
2132 }
2133 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2134 goto err;
2135 zigzag = 1;
2136 break;
2137
2138 case STV090x_SEARCH_AUTO:
2139 default:
2140 /* accelerate the frequency detector */
2141 if (state->dev_ver >= 0x20) {
2142 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2143 goto err;
2144 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2145 goto err;
2146 } else {
2147 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2148 goto err;
2149 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2150 goto err;
2151 }
2152 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
2153 goto err;
2154 zigzag = 0;
2155 break;
2156 }
2157
2158 trials = 0;
2159 do {
2160 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2161 no_signal = stv090x_chk_signal(state);
2162 trials++;
2163
2164 /*run the SW search 2 times maximum*/
2165 if (lock || no_signal || (trials == 2)) {
2166 /*Check if the demod is not losing lock in DVBS2*/
2167 if (state->dev_ver >= 0x20) {
2168 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2169 goto err;
2170 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2171 goto err;
2172 } else {
2173 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
2174 goto err;
2175 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
2176 goto err;
2177 }
2178
2179 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2180 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2181 /*Check if the demod is not losing lock in DVBS2*/
2182 msleep(timeout_step);
2183 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2184 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2185 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2186 msleep(timeout_step);
2187 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2188 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2189 }
2190 if (dvbs2_fly_wheel < 0xd) {
2191 /*FALSE lock, The demod is loosing lock */
2192 lock = 0;
2193 if (trials < 2) {
2194 if (state->dev_ver >= 0x20) {
2195 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2196 goto err;
2197 } else {
2198 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2199 goto err;
2200 }
2201 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2202 goto err;
2203 }
2204 }
2205 }
2206 }
2207 } while ((!lock) && (trials < 2) && (!no_signal));
2208
2209 return lock;
2210err:
2211 dprintk(FE_ERROR, 1, "I/O error");
2212 return -1;
2213}
2214
2215static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2216{
2217 u32 reg;
2218 enum stv090x_delsys delsys;
2219
2220 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2221 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2222 delsys = STV090x_DVBS2;
2223 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2224 reg = STV090x_READ_DEMOD(state, FECM);
2225 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2226 delsys = STV090x_DSS;
2227 else
2228 delsys = STV090x_DVBS1;
2229 } else {
2230 delsys = STV090x_ERROR;
2231 }
2232
2233 return delsys;
2234}
2235
2236/* in Hz */
2237static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2238{
2239 s32 derot, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 2240
2241 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2242 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2243 derot |= STV090x_READ_DEMOD(state, CFR0);
2244
2245 derot = comp2(derot, 24);
da4b9059
MA		 2246 int_1 = state->mclk >> 12;
2247 int_2 = derot >> 12;
e415c689 2248
da4b9059
MA		 2249 /* carrier_frequency = MasterClock * Reg / 2^24 */
2250 tmp_1 = state->mclk % 0x1000;
2251 tmp_2 = derot % 0x1000;
e415c689
MA		 2252
2253 derot = (int_1 * int_2) +
da4b9059
MA		 2254 ((int_1 * tmp_2) >> 12) +
2255 ((int_1 * tmp_1) >> 12);
e415c689
MA		 2256
2257 return derot;
2258}
2259
2260static int stv090x_get_viterbi(struct stv090x_state *state)
2261{
2262 u32 reg, rate;
2263
2264 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2265 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2266
2267 switch (rate) {
2268 case 13:
2269 state->fec = STV090x_PR12;
2270 break;
2271
2272 case 18:
2273 state->fec = STV090x_PR23;
2274 break;
2275
2276 case 21:
2277 state->fec = STV090x_PR34;
2278 break;
2279
2280 case 24:
2281 state->fec = STV090x_PR56;
2282 break;
2283
2284 case 25:
2285 state->fec = STV090x_PR67;
2286 break;
2287
2288 case 26:
2289 state->fec = STV090x_PR78;
2290 break;
2291
2292 default:
2293 state->fec = STV090x_PRERR;
2294 break;
2295 }
2296
2297 return 0;
2298}
2299
2300static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2301{
2302 struct dvb_frontend *fe = &state->frontend;
2303
2304 u8 tmg;
2305 u32 reg;
2306 s32 i = 0, offst_freq;
2307
2308 msleep(5);
2309
2310 if (state->algo == STV090x_BLIND_SEARCH) {
2311 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2312 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2313 while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
2314 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2315 msleep(5);
2316 i += 5;
2317 }
2318 }
2319 state->delsys = stv090x_get_std(state);
2320
2321 stv090x_i2c_gate_ctrl(fe, 1);
2322
2323 if (state->config->tuner_get_frequency)
2324 state->config->tuner_get_frequency(fe, &state->frequency);
2325
2326 stv090x_i2c_gate_ctrl(fe, 0);
2327
2328 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2329 state->frequency += offst_freq;
2330 stv090x_get_viterbi(state);
2331 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2332 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2333 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2334 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2335 reg = STV090x_READ_DEMOD(state, TMGOBS);
2336 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2337 reg = STV090x_READ_DEMOD(state, FECM);
2338 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2339
2340 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2341
2342 stv090x_i2c_gate_ctrl(fe, 1);
2343
2344 if (state->config->tuner_get_frequency)
2345 state->config->tuner_get_frequency(fe, &state->frequency);
2346
2347 stv090x_i2c_gate_ctrl(fe, 0);
2348
2349 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2350 return STV090x_RANGEOK;
2351 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2352 return STV090x_RANGEOK;
2353 else
2354 return STV090x_OUTOFRANGE; /* Out of Range */
2355 } else {
2356 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2357 return STV090x_RANGEOK;
2358 else
2359 return STV090x_OUTOFRANGE;
2360 }
2361
2362 return STV090x_OUTOFRANGE;
2363}
2364
2365static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2366{
2367 s32 offst_tmg;
e415c689
MA		 2368
2369 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2370 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2371 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2372
e415c689
MA		 2373 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2374 if (!offst_tmg)
2375 offst_tmg = 1;
2376
5f99feff 2377 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
e415c689
MA		 2378 offst_tmg /= 320;
2379
2380 return offst_tmg;
2381}
2382
2383static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2384{
2385 u8 aclc = 0x29;
2386 s32 i;
2387 struct stv090x_long_frame_crloop *car_loop;
2388
2389 if (state->dev_ver <= 0x12)
2390 car_loop = stv090x_s2_crl;
2391 else if (state->dev_ver == 0x20)
2392 car_loop = stv090x_s2_crl_cut20;
2393 else
2394 car_loop = stv090x_s2_crl;
2395
2396
2397 if (modcod < STV090x_QPSK_12) {
2398 i = 0;
2399 while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2400 i++;
2401
2402 if (i >= 3)
2403 i = 2;
2404
2405 } else {
2406 i = 0;
2407 while ((i < 14) && (modcod != car_loop[i].modcod))
2408 i++;
2409
2410 if (i >= 14) {
2411 i = 0;
2412 while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2413 i++;
2414
2415 if (i >= 11)
2416 i = 10;
2417 }
2418 }
2419
2420 if (modcod <= STV090x_QPSK_25) {
2421 if (pilots) {
2422 if (state->srate <= 3000000)
2423 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
2424 else if (state->srate <= 7000000)
2425 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
2426 else if (state->srate <= 15000000)
2427 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
2428 else if (state->srate <= 25000000)
2429 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
2430 else
2431 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
2432 } else {
2433 if (state->srate <= 3000000)
2434 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
2435 else if (state->srate <= 7000000)
2436 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
2437 else if (state->srate <= 15000000)
2438 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
2439 else if (state->srate <= 25000000)
2440 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
2441 else
2442 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
2443 }
2444
2445 } else if (modcod <= STV090x_8PSK_910) {
2446 if (pilots) {
2447 if (state->srate <= 3000000)
2448 aclc = car_loop[i].crl_pilots_on_2;
2449 else if (state->srate <= 7000000)
2450 aclc = car_loop[i].crl_pilots_on_5;
2451 else if (state->srate <= 15000000)
2452 aclc = car_loop[i].crl_pilots_on_10;
2453 else if (state->srate <= 25000000)
2454 aclc = car_loop[i].crl_pilots_on_20;
2455 else
2456 aclc = car_loop[i].crl_pilots_on_30;
2457 } else {
2458 if (state->srate <= 3000000)
2459 aclc = car_loop[i].crl_pilots_off_2;
2460 else if (state->srate <= 7000000)
2461 aclc = car_loop[i].crl_pilots_off_5;
2462 else if (state->srate <= 15000000)
2463 aclc = car_loop[i].crl_pilots_off_10;
2464 else if (state->srate <= 25000000)
2465 aclc = car_loop[i].crl_pilots_off_20;
2466 else
2467 aclc = car_loop[i].crl_pilots_off_30;
2468 }
2469 } else { /* 16APSK and 32APSK */
2470 if (state->srate <= 3000000)
2471 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
2472 else if (state->srate <= 7000000)
2473 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
2474 else if (state->srate <= 15000000)
2475 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
2476 else if (state->srate <= 25000000)
2477 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
2478 else
2479 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
2480 }
2481
2482 return aclc;
2483}
2484
2485static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2486{
2487 s32 index = 0;
2488 u8 aclc = 0x0b;
2489
2490 switch (state->modulation) {
2491 case STV090x_QPSK:
2492 default:
2493 index = 0;
2494 break;
2495 case STV090x_8PSK:
2496 index = 1;
2497 break;
2498 case STV090x_16APSK:
2499 index = 2;
2500 break;
2501 case STV090x_32APSK:
2502 index = 3;
2503 break;
2504 }
2505
2506 switch (state->dev_ver) {
2507 case 0x20:
2508 if (state->srate <= 3000000)
2509 aclc = stv090x_s2_short_crl[index].crl_cut20_2;
2510 else if (state->srate <= 7000000)
2511 aclc = stv090x_s2_short_crl[index].crl_cut20_5;
2512 else if (state->srate <= 15000000)
2513 aclc = stv090x_s2_short_crl[index].crl_cut20_10;
2514 else if (state->srate <= 25000000)
2515 aclc = stv090x_s2_short_crl[index].crl_cut20_20;
2516 else
2517 aclc = stv090x_s2_short_crl[index].crl_cut20_30;
2518 break;
2519
2520 case 0x12:
2521 default:
2522 if (state->srate <= 3000000)
2523 aclc = stv090x_s2_short_crl[index].crl_cut12_2;
2524 else if (state->srate <= 7000000)
2525 aclc = stv090x_s2_short_crl[index].crl_cut12_5;
2526 else if (state->srate <= 15000000)
2527 aclc = stv090x_s2_short_crl[index].crl_cut12_10;
2528 else if (state->srate <= 25000000)
2529 aclc = stv090x_s2_short_crl[index].crl_cut12_20;
2530 else
2531 aclc = stv090x_s2_short_crl[index].crl_cut12_30;
2532 break;
2533 }
2534
2535 return aclc;
2536}
2537
2538static int stv090x_optimize_track(struct stv090x_state *state)
2539{
2540 struct dvb_frontend *fe = &state->frontend;
2541
2542 enum stv090x_rolloff rolloff;
2543 enum stv090x_modcod modcod;
2544
2545 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2546 u32 reg;
2547
2548 srate = stv090x_get_srate(state, state->mclk);
2549 srate += stv090x_get_tmgoffst(state, srate);
2550
2551 switch (state->delsys) {
2552 case STV090x_DVBS1:
2553 case STV090x_DSS:
2554 if (state->algo == STV090x_SEARCH_AUTO) {
2555 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2556 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2557 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2558 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2559 goto err;
2560 }
2561 reg = STV090x_READ_DEMOD(state, DEMOD);
2562 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2563 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2564 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2565 goto err;
2566 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2567 goto err;
2568 break;
2569
2570 case STV090x_DVBS2:
2571 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2572 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2573 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2574 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2575 goto err;
2576 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2577 goto err;
2578 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2579 goto err;
2580 if (state->frame_len == STV090x_LONG_FRAME) {
2581 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2582 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2583 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2584 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2585 if (modcod <= STV090x_QPSK_910) {
2586 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2587 } else if (modcod <= STV090x_8PSK_910) {
2588 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2589 goto err;
2590 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2591 goto err;
2592 }
2593 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2594 if (modcod <= STV090x_16APSK_910) {
2595 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2596 goto err;
2597 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2598 goto err;
2599 } else {
2600 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2601 goto err;
2602 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2603 goto err;
2604 }
2605 }
2606 } else {
2607 /*Carrier loop setting for short frame*/
2608 aclc = stv090x_optimize_carloop_short(state);
2609 if (state->modulation == STV090x_QPSK) {
2610 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2611 goto err;
2612 } else if (state->modulation == STV090x_8PSK) {
2613 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2614 goto err;
2615 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2616 goto err;
2617 } else if (state->modulation == STV090x_16APSK) {
2618 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2619 goto err;
2620 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2621 goto err;
2622 } else if (state->modulation == STV090x_32APSK) {
2623 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2624 goto err;
2625 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2626 goto err;
2627 }
2628 }
2629 if (state->dev_ver <= 0x11) {
2630 if (state->demod_mode != STV090x_SINGLE)
2631 stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
2632 }
2633 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2634 break;
2635
2636 case STV090x_UNKNOWN:
2637 default:
2638 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2639 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2640 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2641 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2642 goto err;
2643 break;
2644 }
2645
2646 f_1 = STV090x_READ_DEMOD(state, CFR2);
2647 f_0 = STV090x_READ_DEMOD(state, CFR1);
2648 reg = STV090x_READ_DEMOD(state, TMGOBS);
2649 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2650
2651 if (state->algo == STV090x_BLIND_SEARCH) {
2652 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2653 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2654 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2655 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2656 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2657 goto err;
2658 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
2659 goto err;
2660 stv090x_set_srate(state, srate);
2661 stv090x_set_max_srate(state, state->mclk, srate);
2662 stv090x_set_min_srate(state, state->mclk, srate);
2663 blind_tune = 1;
2664 }
2665
2666 if (state->dev_ver >= 0x20) {
2667 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2668 (state->search_mode == STV090x_SEARCH_DSS) ||
2669 (state->search_mode == STV090x_SEARCH_AUTO)) {
2670
2671 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2672 goto err;
2673 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2674 goto err;
2675 }
2676 }
2677
2678 if (state->dev_ver < 0x20) {
2679 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
2680 goto err;
2681 }
2682 if (state->dev_ver == 0x10) {
2683 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
2684 goto err;
2685 }
2686
2687 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2688 goto err;
2689
2690 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2691
2692 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2693 goto err;
2694 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2695 goto err;
2696 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2697
2698 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2699
2700 if (state->algo != STV090x_WARM_SEARCH) {
2701
2702 stv090x_i2c_gate_ctrl(fe, 1);
2703
2704 if (state->config->tuner_set_bandwidth)
2705 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2706
2707 stv090x_i2c_gate_ctrl(fe, 0);
2708
2709 }
2710 }
2711 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2712 msleep(50); /* blind search: wait 50ms for SR stabilization */
2713 else
2714 msleep(5);
2715
2716 stv090x_get_lock_tmg(state);
2717
2718 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2719 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2720 goto err;
2721 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2722 goto err;
2723 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2724 goto err;
2725 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2726 goto err;
2727
2728 i = 0;
2729
2730 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2731
2732 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2733 goto err;
2734 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2735 goto err;
2736 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2737 goto err;
2738 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2739 goto err;
2740 i++;
2741 }
2742 }
2743
2744 }
2745
2746 if (state->dev_ver >= 0x20) {
2747 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2748 goto err;
2749 }
2750 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2751 stv090x_set_vit_thtracq(state);
2752
2753 return 0;
2754err:
2755 dprintk(FE_ERROR, 1, "I/O error");
2756 return -1;
2757}
2758
2759static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2760{
2761 s32 timer = 0, lock = 0, stat;
2762 u32 reg;
2763
2764 while ((timer < timeout) && (!lock)) {
2765 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2766 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2767
2768 switch (stat) {
2769 case 0: /* searching */
2770 case 1: /* first PLH detected */
2771 default:
2772 lock = 0;
2773 break;
2774
2775 case 2: /* DVB-S2 mode */
2776 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2777 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2778 break;
2779
2780 case 3: /* DVB-S1/legacy mode */
2781 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2782 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
2783 break;
2784 }
2785 if (!lock) {
2786 msleep(10);
2787 timer += 10;
2788 }
2789 }
2790 return lock;
2791}
2792
2793static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
2794{
2795 u32 reg;
2796 s32 timer = 0;
2797 int lock;
2798
2799 lock = stv090x_get_dmdlock(state, timeout_dmd);
2800 if (lock)
2801 lock = stv090x_get_feclock(state, timeout_fec);
2802
2803 if (lock) {
2804 lock = 0;
2805
2806 while ((timer < timeout_fec) && (!lock)) {
2807 reg = STV090x_READ_DEMOD(state, TSSTATUS);
2808 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
2809 msleep(1);
2810 timer++;
2811 }
2812 }
2813
2814 return lock;
2815}
2816
2817static int stv090x_set_s2rolloff(struct stv090x_state *state)
2818{
2819 s32 rolloff;
2820 u32 reg;
2821
2822 if (state->dev_ver == 0x10) {
2823 reg = STV090x_READ_DEMOD(state, DEMOD);
2824 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2825 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2826 goto err;
2827 rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
2828 reg = STV090x_READ_DEMOD(state, DEMOD);
2829 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
2830 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2831 goto err;
2832 } else {
2833 reg = STV090x_READ_DEMOD(state, DEMOD);
2834 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
2835 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2836 goto err;
2837 }
2838 return 0;
2839err:
2840 dprintk(FE_ERROR, 1, "I/O error");
2841 return -1;
2842}
2843
2844static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
2845{
2846 s32 srate, f_1, f_2;
2847 enum stv090x_signal_state signal_state = STV090x_NODATA;
2848 u32 reg;
2849 int lock;
2850
2851 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2852 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
2853 srate = stv090x_get_srate(state, state->mclk);
2854 srate += stv090x_get_tmgoffst(state, state->srate);
2855
2856 if (state->algo == STV090x_BLIND_SEARCH)
2857 stv090x_set_srate(state, state->srate);
2858
2859 stv090x_get_lock_tmg(state);
2860
2861 f_1 = STV090x_READ_DEMOD(state, CFR2);
2862 f_2 = STV090x_READ_DEMOD(state, CFR1);
2863
2864 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2865 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
2866 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2867 goto err;
2868
2869 reg = STV090x_READ_DEMOD(state, DEMOD);
2870 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
2871 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2872 goto err;
2873 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
2874 goto err;
2875 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2876 goto err;
2877 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2878 goto err;
2879 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2880 goto err;
2881
2882 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2883 lock = 1;
2884 stv090x_get_sig_params(state);
2885 stv090x_optimize_track(state);
2886 } else {
2887 reg = STV090x_READ_DEMOD(state, DEMOD);
2888 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
2889 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2890 goto err;
2891 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2892 goto err;
2893 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2894 goto err;
2895 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2896 goto err;
2897 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2898 goto err;
2899 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2900 lock = 1;
2901 signal_state = stv090x_get_sig_params(state);
2902 stv090x_optimize_track(state);
2903 }
2904 }
2905 } else {
2906 lock = 0;
2907 }
2908
2909 return signal_state;
2910
2911err:
2912 dprintk(FE_ERROR, 1, "I/O error");
2913 return -1;
2914}
2915
2916static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
2917{
2918 struct dvb_frontend *fe = &state->frontend;
2919 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
2920 u32 reg;
2921 s32 timeout_dmd = 500, timeout_fec = 50;
4e58a682 2922 int lock = 0, low_sr = 0, no_signal = 0;
e415c689
MA		 2923
2924 reg = STV090x_READ_DEMOD(state, TSCFGH);
2925 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
2926 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2927 goto err;
2928
2929 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
2930 goto err;
2931
2932 if (state->dev_ver >= 0x20) {
2933 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
2934 goto err;
2935 } else {
2936 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
2937 goto err;
2938 }
2939
2940 stv090x_get_lock_tmg(state);
2941
2942 if (state->algo == STV090x_BLIND_SEARCH) {
2943 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
2944 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
2945 goto err;
2946 stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
2947 } else {
2948 /* known srate */
2949 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
2950 goto err;
2951 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
2952 goto err;
2953
2954 if (state->srate >= 10000000) {
2955 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
2956 goto err;
2957 } else {
2958 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
2959 goto err;
2960 }
2961
2962 if (state->dev_ver >= 0x20) {
2963 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
2964 goto err;
2965 if (state->algo == STV090x_COLD_SEARCH)
4e58a682 2966 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
e415c689
MA		 2967 else if (state->algo == STV090x_WARM_SEARCH)
2968 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
2969 } else {
2970 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
2971 goto err;
2972 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
2973 }
2974 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
2975 goto err;
2976 stv090x_set_srate(state, state->srate);
2977 stv090x_set_max_srate(state, state->mclk, state->srate);
2978 stv090x_set_min_srate(state, state->mclk, state->srate);
2979
2980 if (state->srate >= 10000000)
4e58a682
AR		 2981 low_sr = 0;
2982 else
e415c689
MA		 2983 low_sr = 1;
2984 }
2985
2986 /* Setup tuner */
2987 stv090x_i2c_gate_ctrl(fe, 1);
2988
2989 if (state->config->tuner_set_bbgain)
2990 state->config->tuner_set_bbgain(fe, 10); /* 10dB */
2991
2992 if (state->config->tuner_set_frequency)
2993 state->config->tuner_set_frequency(fe, state->frequency);
2994
2995 if (state->config->tuner_set_bandwidth)
2996 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2997
2998 stv090x_i2c_gate_ctrl(fe, 0);
2999
3000 msleep(50);
3001
3002 stv090x_i2c_gate_ctrl(fe, 1);
3003
3004 if (state->config->tuner_get_status)
3005 state->config->tuner_get_status(fe, &reg);
3006
3007 if (reg)
3008 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3009 else
3010 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3011
3012 stv090x_i2c_gate_ctrl(fe, 0);
3013
3014 reg = STV090x_READ_DEMOD(state, DEMOD);
3015 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3016 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
3017 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3018 goto err;
3019 stv090x_delivery_search(state);
4e58a682 3020 if (state->algo != STV090x_BLIND_SEARCH)
e415c689
MA		 3021 stv090x_start_search(state);
3022
3023 if (state->dev_ver == 0x12) {
3024 reg = STV090x_READ_DEMOD(state, TSCFGH);
3025 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3026 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3027 goto err;
3028 msleep(3);
3029 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3030 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3031 goto err;
3032 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3033 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3034 goto err;
3035 }
3036
3037 if (state->algo == STV090x_BLIND_SEARCH)
3038 lock = stv090x_blind_search(state);
3039 else if (state->algo == STV090x_COLD_SEARCH)
3040 lock = stv090x_get_coldlock(state, timeout_dmd);
3041 else if (state->algo == STV090x_WARM_SEARCH)
3042 lock = stv090x_get_dmdlock(state, timeout_dmd);
3043
3044 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3045 if (!low_sr) {
3046 if (stv090x_chk_tmg(state))
3047 lock = stv090x_sw_algo(state);
3048 }
3049 }
3050
3051 if (lock)
3052 signal_state = stv090x_get_sig_params(state);
3053
3054 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3055 stv090x_optimize_track(state);
3056 if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
3057 if (stv090x_get_std(state) == STV090x_DVBS1) {
3058 msleep(20);
3059 reg = STV090x_READ_DEMOD(state, TSCFGH);
3060 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3061 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3062 goto err;
3063 } else {
3064 reg = STV090x_READ_DEMOD(state, TSCFGH);
3065 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3066 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3067 goto err;
3068 msleep(3);
3069 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3070 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3071 goto err;
3072 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3073 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3074 goto err;
3075 }
3076 } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
3077 reg = STV090x_READ_DEMOD(state, TSCFGH);
3078 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3079 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3080 goto err;
3081 msleep(3);
3082 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3083 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3084 goto err;
3085
3086 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3087 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3088 goto err;
3089 }
3090
3091 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3092 lock = 1;
3093 if (state->delsys == STV090x_DVBS2) {
3094 stv090x_set_s2rolloff(state);
3095 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
3096 goto err;
3097 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
3098 goto err;
3099 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3100 goto err;
3101 } else {
3102 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3103 goto err;
3104 }
3105 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3106 goto err;
3107 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3108 goto err;
3109 } else {
3110 lock = 0;
3111 signal_state = STV090x_NODATA;
3112 no_signal = stv090x_chk_signal(state);
3113 }
3114 }
3115 if ((signal_state == STV090x_NODATA) && (!no_signal)) {
3116 if (state->dev_ver <= 0x11) {
3117 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3118 if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
3119 signal_state = stv090x_acq_fixs1(state);
3120 }
3121 }
3122 return signal_state;
3123
3124err:
3125 dprintk(FE_ERROR, 1, "I/O error");
3126 return -1;
3127}
3128
3129static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3130{
3131 struct stv090x_state *state = fe->demodulator_priv;
3132 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3133
3134 state->delsys = props->delivery_system;
3135 state->frequency = p->frequency;
3136 state->srate = p->u.qpsk.symbol_rate;
4e58a682
AR		 3137 state->search_mode = STV090x_SEARCH_AUTO;
3138 state->algo = STV090x_COLD_SEARCH;
3139 state->fec = STV090x_PRERR;
3140 state->search_range = 2000000;
e415c689
MA		 3141
3142 if (!stv090x_algo(state)) {
3143 dprintk(FE_DEBUG, 1, "Search success!");
3144 return DVBFE_ALGO_SEARCH_SUCCESS;
3145 } else {
3146 dprintk(FE_DEBUG, 1, "Search failed!");
3147 return DVBFE_ALGO_SEARCH_FAILED;
3148 }
3149
3150 return DVBFE_ALGO_SEARCH_ERROR;
3151}
3152
3153/* FIXME! */
3154static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3155{
3156 struct stv090x_state *state = fe->demodulator_priv;
3157 u32 reg;
3158 u8 search_state;
3159 int locked = 0;
3160
3161 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3162 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3163
3164 switch (search_state) {
3165 case 0: /* searching */
3166 case 1: /* first PLH detected */
3167 default:
3168 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3169 locked = 0;
3170 break;
3171
3172 case 2: /* DVB-S2 mode */
3173 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3174 reg = STV090x_READ_DEMOD(state, DSTATUS);
3175 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3176 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3177 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3178 locked = 1;
3179 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3180 }
3181 }
3182 break;
3183
3184 case 3: /* DVB-S1/legacy mode */
3185 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3186 reg = STV090x_READ_DEMOD(state, DSTATUS);
3187 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3188 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3189 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3190 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3191 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3192 locked = 1;
3193 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3194 }
3195 }
3196 }
3197 break;
3198 }
3199
3200 return locked;
3201}
3202
3203static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3204{
3205 struct stv090x_state *state = fe->demodulator_priv;
3206
3207 s32 count_4, count_3, count_2, count_1, count_0, count;
3208 u32 reg, h, m, l;
3209 enum fe_status status;
3210
3211 if (!stv090x_read_status(fe, &status)) {
3212 *per = 1 << 23; /* Max PER */
3213 } else {
3214 /* Counter 2 */
3215 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3216 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3217
3218 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3219 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3220
3221 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3222 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3223
3224 *per = ((h << 16) | (m << 8) | l);
3225
3226 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3227 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3228 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3229 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3230 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3231
3232 if ((!count_4) && (!count_3)) {
3233 count = (count_2 & 0xff) << 16;
3234 count |= (count_1 & 0xff) << 8;
3235 count |= count_0 & 0xff;
3236 } else {
3237 count = 1 << 24;
3238 }
3239 if (count == 0)
3240 *per = 1;
3241 }
3242 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3243 goto err;
3244 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3245 goto err;
3246
3247 return 0;
3248err:
3249 dprintk(FE_ERROR, 1, "I/O error");
3250 return -1;
3251}
3252
3253static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3254{
3255 int res = 0;
3256 int min = 0, med;
3257
3258 if (val < tab[min].read)
3259 res = tab[min].real;
3260 else if (val >= tab[max].read)
3261 res = tab[max].real;
3262 else {
3263 while ((max - min) > 1) {
3264 med = (max + min) / 2;
3265 if (val >= tab[min].read && val < tab[med].read)
3266 max = med;
3267 else
3268 min = med;
3269 }
3270 res = ((val - tab[min].read) *
3271 (tab[max].real - tab[min].real) /
3272 (tab[max].read - tab[min].read)) +
3273 tab[min].real;
3274 }
3275
3276 return res;
3277}
3278
3279static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3280{
3281 struct stv090x_state *state = fe->demodulator_priv;
3282 u32 reg;
3283 s32 agc;
3284
3285 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3286 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3287
3288 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3289 if (agc > stv090x_rf_tab[0].read)
3290 *strength = 5;
3291 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3292 *strength = -100;
3293
3294 return 0;
3295}
3296
3297static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3298{
3299 struct stv090x_state *state = fe->demodulator_priv;
3300 u32 reg_0, reg_1, reg, i;
3301 s32 val_0, val_1, val = 0;
3302 u8 lock_f;
3303
3304 switch (state->delsys) {
3305 case STV090x_DVBS2:
3306 reg = STV090x_READ_DEMOD(state, DSTATUS);
3307 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3308 if (lock_f) {
3309 msleep(5);
3310 for (i = 0; i < 16; i++) {
3311 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3312 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3313 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3314 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3315 val += MAKEWORD16(val_1, val_0);
3316 msleep(1);
3317 }
3318 val /= 16;
3319 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
3320 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
3321 *cnr = 1000;
3322 }
3323 break;
3324
3325 case STV090x_DVBS1:
3326 case STV090x_DSS:
3327 reg = STV090x_READ_DEMOD(state, DSTATUS);
3328 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3329 if (lock_f) {
3330 msleep(5);
3331 for (i = 0; i < 16; i++) {
3332 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3333 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3334 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3335 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3336 val += MAKEWORD16(val_1, val_0);
3337 msleep(1);
3338 }
3339 val /= 16;
3340 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
3341 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
3342 *cnr = 1000;
3343 }
3344 break;
3345 default:
3346 break;
3347 }
3348
3349 return 0;
3350}
3351
3352static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3353{
3354 struct stv090x_state *state = fe->demodulator_priv;
3355 u32 reg;
3356
3357 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3358 switch (tone) {
3359 case SEC_TONE_ON:
3360 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3361 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3362 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3363 goto err;
3364 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3365 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3366 goto err;
3367 break;
3368
3369 case SEC_TONE_OFF:
3370 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3371 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3372 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3373 goto err;
3374 break;
3375 default:
3376 return -EINVAL;
3377 }
3378
3379 return 0;
3380err:
3381 dprintk(FE_ERROR, 1, "I/O error");
3382 return -1;
3383}
3384
3385
3386static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3387{
3388 return DVBFE_ALGO_CUSTOM;
3389}
3390
3391static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3392{
3393 struct stv090x_state *state = fe->demodulator_priv;
3394 u32 reg, idle = 0, fifo_full = 1;
3395 int i;
3396
3397 reg = STV090x_READ_DEMOD(state, DISTXCTL);
f9ed95d0
AR		 3398
3399 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
3400 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3401 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3402 goto err;
3403 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3404 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3405 goto err;
3406
e415c689
MA		 3407 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3408 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3409 goto err;
3410
3411 for (i = 0; i < cmd->msg_len; i++) {
3412
3413 while (fifo_full) {
3414 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3415 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3416 }
3417
3418 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3419 goto err;
f9ed95d0
AR		 3420 }
3421 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3422 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3423 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3424 goto err;
3425
3426 i = 0;
3427
3428 while ((!idle) && (i < 10)) {
3429 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3430 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3431 msleep(10);
e415c689
MA		 3432 i++;
3433 }
f9ed95d0
AR		 3434
3435 return 0;
3436err:
3437 dprintk(FE_ERROR, 1, "I/O error");
3438 return -1;
3439}
3440
3441static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3442{
3443 struct stv090x_state *state = fe->demodulator_priv;
3444 u32 reg, idle = 0, fifo_full = 1;
3445 u8 mode, value;
3446 int i;
3447
3448 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3449
3450 if (burst == SEC_MINI_A) {
3451 mode = 3;
3452 value = 0x00;
3453 } else {
3454 mode = 2;
3455 value = 0xFF;
3456 }
3457
3458 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3459 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3460 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3461 goto err;
3462 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3463 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3464 goto err;
3465
3466 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3467 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3468 goto err;
3469
3470 while (fifo_full) {
3471 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3472 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3473 }
3474
3475 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3476 goto err;
3477
e415c689
MA		 3478 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3479 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3480 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3481 goto err;
3482
3483 i = 0;
3484
3485 while ((!idle) && (i < 10)) {
3486 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3487 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3488 msleep(10);
3489 i++;
3490 }
3491
3492 return 0;
3493err:
3494 dprintk(FE_ERROR, 1, "I/O error");
3495 return -1;
3496}
3497
3498static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3499{
3500 struct stv090x_state *state = fe->demodulator_priv;
3501 u32 reg = 0, i = 0, rx_end = 0;
3502
3503 while ((rx_end != 1) && (i < 10)) {
3504 msleep(10);
3505 i++;
3506 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3507 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3508 }
3509
3510 if (rx_end) {
3511 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3512 for (i = 0; i < reply->msg_len; i++)
3513 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3514 }
3515
3516 return 0;
3517}
3518
3519static int stv090x_sleep(struct dvb_frontend *fe)
3520{
3521 struct stv090x_state *state = fe->demodulator_priv;
3522 u32 reg;
3523
3524 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3525 state->device == STV0900 ? "STV0900" : "STV0903");
3526
3527 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3528 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3529 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3530 goto err;
3531
26b03bc6
MA		 3532 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3533 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3534 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3535 goto err;
3536
e415c689
MA		 3537 return 0;
3538err:
3539 dprintk(FE_ERROR, 1, "I/O error");
3540 return -1;
3541}
3542
3543static int stv090x_wakeup(struct dvb_frontend *fe)
3544{
3545 struct stv090x_state *state = fe->demodulator_priv;
3546 u32 reg;
3547
3548 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3549 state->device == STV0900 ? "STV0900" : "STV0903");
3550
3551 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3552 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3553 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3554 goto err;
3555
26b03bc6
MA		 3556 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3557 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3558 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3559 goto err;
3560
e415c689
MA		 3561 return 0;
3562err:
3563 dprintk(FE_ERROR, 1, "I/O error");
3564 return -1;
3565}
3566
3567static void stv090x_release(struct dvb_frontend *fe)
3568{
3569 struct stv090x_state *state = fe->demodulator_priv;
3570
3571 kfree(state);
3572}
3573
3574static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3575{
3576 u32 reg;
3577
3578 switch (ldpc_mode) {
3579 case STV090x_DUAL:
3580 default:
3581 reg = stv090x_read_reg(state, STV090x_GENCFG);
3582 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3583 /* follow LDPC default state */
3584 if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
3585 goto err;
3586 state->demod_mode = STV090x_DUAL;
3587 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3588 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3589 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3590 goto err;
3591 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3592 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3593 goto err;
3594 }
3595 break;
3596
3597 case STV090x_SINGLE:
3598 if (state->demod == STV090x_DEMODULATOR_1) {
3599 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3600 goto err;
3601 } else {
3602 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3603 goto err;
3604 }
3605
3606 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3607 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3608 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3609 goto err;
3610 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3611 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3612 goto err;
3613
3614 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3615 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3616 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3617 goto err;
3618 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3619 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3620 goto err;
3621 break;
3622 }
3623
3624 return 0;
3625err:
3626 dprintk(FE_ERROR, 1, "I/O error");
3627 return -1;
3628}
3629
3630/* return (Hz), clk in Hz*/
3631static u32 stv090x_get_mclk(struct stv090x_state *state)
3632{
3633 const struct stv090x_config *config = state->config;
3634 u32 div, reg;
3635 u8 ratio;
3636
3637 div = stv090x_read_reg(state, STV090x_NCOARSE);
3638 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3639 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3640
3641 return (div + 1) * config->xtal / ratio; /* kHz */
3642}
3643
3644static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3645{
3646 const struct stv090x_config *config = state->config;
3647 u32 reg, div, clk_sel;
3648
3649 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3650 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3651
3652 div = ((clk_sel * mclk) / config->xtal) - 1;
3653
3654 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3655 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3656 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3657 goto err;
3658
3659 state->mclk = stv090x_get_mclk(state);
3660
94a80914
MA		 3661 /*Set the DiseqC frequency to 22KHz */
3662 div = state->mclk / 704000;
3663 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
3664 goto err;
3665 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
3666 goto err;
3667
e415c689
MA		 3668 return 0;
3669err:
3670 dprintk(FE_ERROR, 1, "I/O error");
3671 return -1;
3672}
3673
3674static int stv090x_set_tspath(struct stv090x_state *state)
3675{
3676 u32 reg;
3677
3678 if (state->dev_ver >= 0x20) {
3679 switch (state->config->ts1_mode) {
3680 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3681 case STV090x_TSMODE_DVBCI:
3682 switch (state->config->ts2_mode) {
3683 case STV090x_TSMODE_SERIAL_PUNCTURED:
3684 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3685 default:
3686 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3687 break;
3688
3689 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3690 case STV090x_TSMODE_DVBCI:
3691 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3692 goto err;
3693 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3694 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3695 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3696 goto err;
3697 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3698 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3699 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3700 goto err;
3701 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3702 goto err;
3703 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3704 goto err;
3705 break;
3706 }
3707 break;
3708
3709 case STV090x_TSMODE_SERIAL_PUNCTURED:
3710 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3711 default:
3712 switch (state->config->ts2_mode) {
3713 case STV090x_TSMODE_SERIAL_PUNCTURED:
3714 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3715 default:
3716 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3717 goto err;
3718 break;
3719
3720 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3721 case STV090x_TSMODE_DVBCI:
3722 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3723 goto err;
3724 break;
3725 }
3726 break;
3727 }
3728 } else {
3729 switch (state->config->ts1_mode) {
3730 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3731 case STV090x_TSMODE_DVBCI:
3732 switch (state->config->ts2_mode) {
3733 case STV090x_TSMODE_SERIAL_PUNCTURED:
3734 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3735 default:
56571507 3736 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
e415c689
MA		 3737 break;
3738
3739 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3740 case STV090x_TSMODE_DVBCI:
56571507 3741 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
e415c689
MA		 3742 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3743 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3744 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3745 goto err;
3746 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3747 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3748 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3749 goto err;
3750 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3751 goto err;
3752 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3753 goto err;
3754 break;
3755 }
3756 break;
3757
3758 case STV090x_TSMODE_SERIAL_PUNCTURED:
3759 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3760 default:
3761 switch (state->config->ts2_mode) {
3762 case STV090x_TSMODE_SERIAL_PUNCTURED:
3763 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3764 default:
56571507 3765 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
e415c689
MA		 3766 break;
3767
3768 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3769 case STV090x_TSMODE_DVBCI:
56571507 3770 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
e415c689
MA		 3771 break;
3772 }
3773 break;
3774 }
3775 }
3776
3777 switch (state->config->ts1_mode) {
3778 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3779 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3780 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3781 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3782 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3783 goto err;
3784 break;
3785
3786 case STV090x_TSMODE_DVBCI:
3787 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3788 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3789 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3790 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3791 goto err;
3792 break;
3793
3794 case STV090x_TSMODE_SERIAL_PUNCTURED:
3795 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3796 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3797 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3798 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3799 goto err;
3800 break;
3801
3802 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3803 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3804 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3805 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3806 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3807 goto err;
3808 break;
3809
3810 default:
3811 break;
3812 }
3813
3814 switch (state->config->ts2_mode) {
3815 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3816 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3817 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3818 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3819 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3820 goto err;
3821 break;
3822
3823 case STV090x_TSMODE_DVBCI:
3824 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3825 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3826 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3827 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3828 goto err;
3829 break;
3830
3831 case STV090x_TSMODE_SERIAL_PUNCTURED:
3832 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3833 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3834 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3835 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3836 goto err;
3837 break;
3838
3839 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3840 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3841 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3842 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3843 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3844 goto err;
3845 break;
3846
3847 default:
3848 break;
3849 }
3850 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
3851 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3852 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3853 goto err;
3854 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3855 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3856 goto err;
3857
3858 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3859 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3860 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3861 goto err;
3862 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3863 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3864 goto err;
3865
3866 return 0;
3867err:
3868 dprintk(FE_ERROR, 1, "I/O error");
3869 return -1;
3870}
3871
3872static int stv090x_init(struct dvb_frontend *fe)
3873{
3874 struct stv090x_state *state = fe->demodulator_priv;
3875 const struct stv090x_config *config = state->config;
3876 u32 reg;
3877
3878 stv090x_ldpc_mode(state, state->demod_mode);
3879
3880 reg = STV090x_READ_DEMOD(state, TNRCFG2);
3881 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
3882 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
3883 goto err;
3884 reg = STV090x_READ_DEMOD(state, DEMOD);
3885 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
3886 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3887 goto err;
3888
3889 stv090x_i2c_gate_ctrl(fe, 1);
3890
3891 if (config->tuner_init)
3892 config->tuner_init(fe);
3893
3894 stv090x_i2c_gate_ctrl(fe, 0);
3895
3896 stv090x_set_tspath(state);
3897
3898 return 0;
3899err:
3900 dprintk(FE_ERROR, 1, "I/O error");
3901 return -1;
3902}
3903
3904static int stv090x_setup(struct dvb_frontend *fe)
3905{
3906 struct stv090x_state *state = fe->demodulator_priv;
3907 const struct stv090x_config *config = state->config;
3908 const struct stv090x_reg *stv090x_initval = NULL;
3909 const struct stv090x_reg *stv090x_cut20_val = NULL;
3910 unsigned long t1_size = 0, t2_size = 0;
017eb038 3911 u32 reg = 0;
e415c689
MA		 3912
3913 int i;
3914
3915 if (state->device == STV0900) {
3916 dprintk(FE_DEBUG, 1, "Initializing STV0900");
3917 stv090x_initval = stv0900_initval;
3918 t1_size = ARRAY_SIZE(stv0900_initval);
3919 stv090x_cut20_val = stv0900_cut20_val;
3920 t2_size = ARRAY_SIZE(stv0900_cut20_val);
3921 } else if (state->device == STV0903) {
3922 dprintk(FE_DEBUG, 1, "Initializing STV0903");
3923 stv090x_initval = stv0903_initval;
3924 t1_size = ARRAY_SIZE(stv0903_initval);
3925 stv090x_cut20_val = stv0903_cut20_val;
3926 t2_size = ARRAY_SIZE(stv0903_cut20_val);
3927 }
3928
3929 /* STV090x init */
3930 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
3931 goto err;
3932
3933 msleep(5);
3934
3935 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
3936 goto err;
3937
017eb038
MA		 3938 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
3939 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
e415c689
MA		 3940 goto err;
3941
3942 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
3943 goto err;
3944 msleep(5);
3945 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
3946 goto err;
3947 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
3948 goto err;
3949 msleep(5);
3950
3951 /* write initval */
3952 for (i = 0; i < t1_size; i++) {
3953 dprintk(FE_DEBUG, 1, "Setting up initial values");
3954 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
3955 goto err;
3956 }
3957
3958 if (state->dev_ver >= 0x20) {
3959 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3960 goto err;
3961
3962 /* write cut20_val*/
3963 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
3964 for (i = 0; i < t2_size; i++) {
3965 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
3966 goto err;
3967 }
3968 }
3969
3970 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
3971 goto err;
3972 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
3973 goto err;
3974
3975 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
3976 msleep(5);
3977 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
3978 goto err;
3979 stv090x_get_mclk(state);
3980
3981 return 0;
3982err:
3983 dprintk(FE_ERROR, 1, "I/O error");
3984 return -1;
3985}
3986
3987static struct dvb_frontend_ops stv090x_ops = {
3988
3989 .info = {
3990 .name = "STV090x Multistandard",
3991 },
3992
3993 .release = stv090x_release,
3994 .init = stv090x_init,
3995
3996 .sleep = stv090x_sleep,
3997 .get_frontend_algo = stv090x_frontend_algo,
3998
3999 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
4000
4001 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
f9ed95d0 4002 .diseqc_send_burst = stv090x_send_diseqc_burst,
e415c689
MA		 4003 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4004 .set_tone = stv090x_set_tone,
4005
4006 .search = stv090x_search,
4007 .read_status = stv090x_read_status,
4008 .read_ber = stv090x_read_per,
4009 .read_signal_strength = stv090x_read_signal_strength,
4010 .read_snr = stv090x_read_cnr
4011};
4012
4013
4014struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4015 struct i2c_adapter *i2c,
4016 enum stv090x_demodulator demod)
4017{
4018 struct stv090x_state *state = NULL;
4019
4020 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4021 if (state == NULL)
4022 goto error;
4023
4024 state->verbose = &verbose;
4025 state->config = config;
4026 state->i2c = i2c;
4027 state->frontend.ops = stv090x_ops;
4028 state->frontend.demodulator_priv = state;
56571507 4029 state->demod = demod;
e415c689
MA		 4030 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4031 state->device = config->device;
4e58a682 4032 state->rolloff = STV090x_RO_35; /* default */
e415c689
MA		 4033
4034 if (state->demod == STV090x_DEMODULATOR_0)
4035 mutex_init(&demod_lock);
4036
4037 if (stv090x_sleep(&state->frontend) < 0) {
4038 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4039 goto error;
4040 }
4041
4042 if (stv090x_setup(&state->frontend) < 0) {
4043 dprintk(FE_ERROR, 1, "Error setting up device");
4044 goto error;
4045 }
4046 if (stv090x_wakeup(&state->frontend) < 0) {
4047 dprintk(FE_ERROR, 1, "Error waking device");
4048 goto error;
4049 }
4050 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
4051
4052 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
4053 state->device == STV0900 ? "STV0900" : "STV0903",
4054 demod,
4055 state->dev_ver);
4056
4057 return &state->frontend;
4058
4059error:
4060 kfree(state);
4061 return NULL;
4062}
4063EXPORT_SYMBOL(stv090x_attach);
4064MODULE_PARM_DESC(verbose, "Set Verbosity level");
4065MODULE_AUTHOR("Manu Abraham");
4066MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4067MODULE_LICENSE("GPL");
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