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V4L/DVB: [STV090x] Use gate control, while tuner is being accessed
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb / frontends / stv090x.c
CommitLineData
e415c689
MA		 1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
5a0e3ad6 26#include <linux/slab.h>
e415c689
MA		 27#include <linux/mutex.h>
28
29#include <linux/dvb/frontend.h>
30#include "dvb_frontend.h"
31
32#include "stv6110x.h" /* for demodulator internal modes */
33
34#include "stv090x_reg.h"
35#include "stv090x.h"
36#include "stv090x_priv.h"
37
38static unsigned int verbose;
39module_param(verbose, int, 0644);
40
97f7a2ae
AR		 41/* internal params node */
42struct stv090x_dev {
43 /* pointer for internal params, one for each pair of demods */
44 struct stv090x_internal *internal;
45 struct stv090x_dev *next_dev;
46};
47
48/* first internal params */
49static struct stv090x_dev *stv090x_first_dev;
50
51/* find chip by i2c adapter and i2c address */
52static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
53 u8 i2c_addr)
54{
55 struct stv090x_dev *temp_dev = stv090x_first_dev;
56
57 /*
58 Search of the last stv0900 chip or
59 find it by i2c adapter and i2c address */
60 while ((temp_dev != NULL) &&
61 ((temp_dev->internal->i2c_adap != i2c_adap) ||
62 (temp_dev->internal->i2c_addr != i2c_addr))) {
63
64 temp_dev = temp_dev->next_dev;
65 }
66
67 return temp_dev;
68}
69
70/* deallocating chip */
71static void remove_dev(struct stv090x_internal *internal)
72{
73 struct stv090x_dev *prev_dev = stv090x_first_dev;
74 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
75 internal->i2c_addr);
76
77 if (del_dev != NULL) {
78 if (del_dev == stv090x_first_dev) {
79 stv090x_first_dev = del_dev->next_dev;
80 } else {
81 while (prev_dev->next_dev != del_dev)
82 prev_dev = prev_dev->next_dev;
83
84 prev_dev->next_dev = del_dev->next_dev;
85 }
86
87 kfree(del_dev);
88 }
89}
90
91/* allocating new chip */
92static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
93{
94 struct stv090x_dev *new_dev;
95 struct stv090x_dev *temp_dev;
96
97 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
98 if (new_dev != NULL) {
99 new_dev->internal = internal;
100 new_dev->next_dev = NULL;
101
102 /* append to list */
103 if (stv090x_first_dev == NULL) {
104 stv090x_first_dev = new_dev;
105 } else {
106 temp_dev = stv090x_first_dev;
107 while (temp_dev->next_dev != NULL)
108 temp_dev = temp_dev->next_dev;
109
110 temp_dev->next_dev = new_dev;
111 }
112 }
113
114 return new_dev;
115}
116
e415c689
MA		 117
118/* DVBS1 and DSS C/N Lookup table */
119static const struct stv090x_tab stv090x_s1cn_tab[] = {
120 { 0, 8917 }, /* 0.0dB */
121 { 5, 8801 }, /* 0.5dB */
122 { 10, 8667 }, /* 1.0dB */
123 { 15, 8522 }, /* 1.5dB */
124 { 20, 8355 }, /* 2.0dB */
125 { 25, 8175 }, /* 2.5dB */
126 { 30, 7979 }, /* 3.0dB */
127 { 35, 7763 }, /* 3.5dB */
128 { 40, 7530 }, /* 4.0dB */
129 { 45, 7282 }, /* 4.5dB */
130 { 50, 7026 }, /* 5.0dB */
131 { 55, 6781 }, /* 5.5dB */
132 { 60, 6514 }, /* 6.0dB */
133 { 65, 6241 }, /* 6.5dB */
134 { 70, 5965 }, /* 7.0dB */
135 { 75, 5690 }, /* 7.5dB */
136 { 80, 5424 }, /* 8.0dB */
137 { 85, 5161 }, /* 8.5dB */
138 { 90, 4902 }, /* 9.0dB */
139 { 95, 4654 }, /* 9.5dB */
140 { 100, 4417 }, /* 10.0dB */
141 { 105, 4186 }, /* 10.5dB */
142 { 110, 3968 }, /* 11.0dB */
143 { 115, 3757 }, /* 11.5dB */
144 { 120, 3558 }, /* 12.0dB */
145 { 125, 3366 }, /* 12.5dB */
146 { 130, 3185 }, /* 13.0dB */
147 { 135, 3012 }, /* 13.5dB */
148 { 140, 2850 }, /* 14.0dB */
149 { 145, 2698 }, /* 14.5dB */
150 { 150, 2550 }, /* 15.0dB */
151 { 160, 2283 }, /* 16.0dB */
152 { 170, 2042 }, /* 17.0dB */
153 { 180, 1827 }, /* 18.0dB */
154 { 190, 1636 }, /* 19.0dB */
155 { 200, 1466 }, /* 20.0dB */
156 { 210, 1315 }, /* 21.0dB */
157 { 220, 1181 }, /* 22.0dB */
158 { 230, 1064 }, /* 23.0dB */
159 { 240, 960 }, /* 24.0dB */
160 { 250, 869 }, /* 25.0dB */
161 { 260, 792 }, /* 26.0dB */
162 { 270, 724 }, /* 27.0dB */
163 { 280, 665 }, /* 28.0dB */
164 { 290, 616 }, /* 29.0dB */
165 { 300, 573 }, /* 30.0dB */
166 { 310, 537 }, /* 31.0dB */
167 { 320, 507 }, /* 32.0dB */
168 { 330, 483 }, /* 33.0dB */
169 { 400, 398 }, /* 40.0dB */
170 { 450, 381 }, /* 45.0dB */
171 { 500, 377 } /* 50.0dB */
172};
173
174/* DVBS2 C/N Lookup table */
175static const struct stv090x_tab stv090x_s2cn_tab[] = {
176 { -30, 13348 }, /* -3.0dB */
177 { -20, 12640 }, /* -2d.0B */
178 { -10, 11883 }, /* -1.0dB */
179 { 0, 11101 }, /* -0.0dB */
180 { 5, 10718 }, /* 0.5dB */
181 { 10, 10339 }, /* 1.0dB */
182 { 15, 9947 }, /* 1.5dB */
183 { 20, 9552 }, /* 2.0dB */
184 { 25, 9183 }, /* 2.5dB */
185 { 30, 8799 }, /* 3.0dB */
186 { 35, 8422 }, /* 3.5dB */
187 { 40, 8062 }, /* 4.0dB */
188 { 45, 7707 }, /* 4.5dB */
189 { 50, 7353 }, /* 5.0dB */
190 { 55, 7025 }, /* 5.5dB */
191 { 60, 6684 }, /* 6.0dB */
192 { 65, 6331 }, /* 6.5dB */
193 { 70, 6036 }, /* 7.0dB */
194 { 75, 5727 }, /* 7.5dB */
195 { 80, 5437 }, /* 8.0dB */
196 { 85, 5164 }, /* 8.5dB */
197 { 90, 4902 }, /* 9.0dB */
198 { 95, 4653 }, /* 9.5dB */
199 { 100, 4408 }, /* 10.0dB */
200 { 105, 4187 }, /* 10.5dB */
201 { 110, 3961 }, /* 11.0dB */
202 { 115, 3751 }, /* 11.5dB */
203 { 120, 3558 }, /* 12.0dB */
204 { 125, 3368 }, /* 12.5dB */
205 { 130, 3191 }, /* 13.0dB */
206 { 135, 3017 }, /* 13.5dB */
207 { 140, 2862 }, /* 14.0dB */
208 { 145, 2710 }, /* 14.5dB */
209 { 150, 2565 }, /* 15.0dB */
210 { 160, 2300 }, /* 16.0dB */
211 { 170, 2058 }, /* 17.0dB */
212 { 180, 1849 }, /* 18.0dB */
213 { 190, 1663 }, /* 19.0dB */
214 { 200, 1495 }, /* 20.0dB */
215 { 210, 1349 }, /* 21.0dB */
216 { 220, 1222 }, /* 22.0dB */
217 { 230, 1110 }, /* 23.0dB */
218 { 240, 1011 }, /* 24.0dB */
219 { 250, 925 }, /* 25.0dB */
220 { 260, 853 }, /* 26.0dB */
221 { 270, 789 }, /* 27.0dB */
222 { 280, 734 }, /* 28.0dB */
223 { 290, 690 }, /* 29.0dB */
224 { 300, 650 }, /* 30.0dB */
225 { 310, 619 }, /* 31.0dB */
226 { 320, 593 }, /* 32.0dB */
227 { 330, 571 }, /* 33.0dB */
228 { 400, 498 }, /* 40.0dB */
229 { 450, 484 }, /* 45.0dB */
230 { 500, 481 } /* 50.0dB */
231};
232
233/* RF level C/N lookup table */
234static const struct stv090x_tab stv090x_rf_tab[] = {
235 { -5, 0xcaa1 }, /* -5dBm */
236 { -10, 0xc229 }, /* -10dBm */
237 { -15, 0xbb08 }, /* -15dBm */
238 { -20, 0xb4bc }, /* -20dBm */
239 { -25, 0xad5a }, /* -25dBm */
240 { -30, 0xa298 }, /* -30dBm */
241 { -35, 0x98a8 }, /* -35dBm */
242 { -40, 0x8389 }, /* -40dBm */
243 { -45, 0x59be }, /* -45dBm */
244 { -50, 0x3a14 }, /* -50dBm */
245 { -55, 0x2d11 }, /* -55dBm */
246 { -60, 0x210d }, /* -60dBm */
247 { -65, 0xa14f }, /* -65dBm */
248 { -70, 0x07aa } /* -70dBm */
249};
250
251
252static struct stv090x_reg stv0900_initval[] = {
253
254 { STV090x_OUTCFG, 0x00 },
56571507 255 { STV090x_MODECFG, 0xff },
e415c689
MA		 256 { STV090x_AGCRF1CFG, 0x11 },
257 { STV090x_AGCRF2CFG, 0x13 },
56571507 258 { STV090x_TSGENERAL1X, 0x14 },
e415c689
MA		 259 { STV090x_TSTTNR2, 0x21 },
260 { STV090x_TSTTNR4, 0x21 },
261 { STV090x_P2_DISTXCTL, 0x22 },
262 { STV090x_P2_F22TX, 0xc0 },
263 { STV090x_P2_F22RX, 0xc0 },
264 { STV090x_P2_DISRXCTL, 0x00 },
265 { STV090x_P2_DMDCFGMD, 0xF9 },
266 { STV090x_P2_DEMOD, 0x08 },
267 { STV090x_P2_DMDCFG3, 0xc4 },
268 { STV090x_P2_CARFREQ, 0xed },
269 { STV090x_P2_LDT, 0xd0 },
270 { STV090x_P2_LDT2, 0xb8 },
271 { STV090x_P2_TMGCFG, 0xd2 },
272 { STV090x_P2_TMGTHRISE, 0x20 },
273 { STV090x_P1_TMGCFG, 0xd2 },
274
275 { STV090x_P2_TMGTHFALL, 0x00 },
276 { STV090x_P2_FECSPY, 0x88 },
277 { STV090x_P2_FSPYDATA, 0x3a },
278 { STV090x_P2_FBERCPT4, 0x00 },
279 { STV090x_P2_FSPYBER, 0x10 },
280 { STV090x_P2_ERRCTRL1, 0x35 },
281 { STV090x_P2_ERRCTRL2, 0xc1 },
282 { STV090x_P2_CFRICFG, 0xf8 },
283 { STV090x_P2_NOSCFG, 0x1c },
56571507 284 { STV090x_P2_DMDTOM, 0x20 },
e415c689
MA		 285 { STV090x_P2_CORRELMANT, 0x70 },
286 { STV090x_P2_CORRELABS, 0x88 },
56571507 287 { STV090x_P2_AGC2O, 0x5b },
e415c689
MA		 288 { STV090x_P2_AGC2REF, 0x38 },
289 { STV090x_P2_CARCFG, 0xe4 },
290 { STV090x_P2_ACLC, 0x1A },
291 { STV090x_P2_BCLC, 0x09 },
292 { STV090x_P2_CARHDR, 0x08 },
293 { STV090x_P2_KREFTMG, 0xc1 },
294 { STV090x_P2_SFRUPRATIO, 0xf0 },
295 { STV090x_P2_SFRLOWRATIO, 0x70 },
296 { STV090x_P2_SFRSTEP, 0x58 },
297 { STV090x_P2_TMGCFG2, 0x01 },
298 { STV090x_P2_CAR2CFG, 0x26 },
299 { STV090x_P2_BCLC2S2Q, 0x86 },
300 { STV090x_P2_BCLC2S28, 0x86 },
301 { STV090x_P2_SMAPCOEF7, 0x77 },
302 { STV090x_P2_SMAPCOEF6, 0x85 },
303 { STV090x_P2_SMAPCOEF5, 0x77 },
304 { STV090x_P2_TSCFGL, 0x20 },
305 { STV090x_P2_DMDCFG2, 0x3b },
306 { STV090x_P2_MODCODLST0, 0xff },
307 { STV090x_P2_MODCODLST1, 0xff },
308 { STV090x_P2_MODCODLST2, 0xff },
309 { STV090x_P2_MODCODLST3, 0xff },
310 { STV090x_P2_MODCODLST4, 0xff },
311 { STV090x_P2_MODCODLST5, 0xff },
312 { STV090x_P2_MODCODLST6, 0xff },
313 { STV090x_P2_MODCODLST7, 0xcc },
314 { STV090x_P2_MODCODLST8, 0xcc },
315 { STV090x_P2_MODCODLST9, 0xcc },
316 { STV090x_P2_MODCODLSTA, 0xcc },
317 { STV090x_P2_MODCODLSTB, 0xcc },
318 { STV090x_P2_MODCODLSTC, 0xcc },
319 { STV090x_P2_MODCODLSTD, 0xcc },
320 { STV090x_P2_MODCODLSTE, 0xcc },
321 { STV090x_P2_MODCODLSTF, 0xcf },
322 { STV090x_P1_DISTXCTL, 0x22 },
323 { STV090x_P1_F22TX, 0xc0 },
324 { STV090x_P1_F22RX, 0xc0 },
325 { STV090x_P1_DISRXCTL, 0x00 },
326 { STV090x_P1_DMDCFGMD, 0xf9 },
327 { STV090x_P1_DEMOD, 0x08 },
328 { STV090x_P1_DMDCFG3, 0xc4 },
56571507 329 { STV090x_P1_DMDTOM, 0x20 },
e415c689
MA		 330 { STV090x_P1_CARFREQ, 0xed },
331 { STV090x_P1_LDT, 0xd0 },
332 { STV090x_P1_LDT2, 0xb8 },
333 { STV090x_P1_TMGCFG, 0xd2 },
334 { STV090x_P1_TMGTHRISE, 0x20 },
335 { STV090x_P1_TMGTHFALL, 0x00 },
336 { STV090x_P1_SFRUPRATIO, 0xf0 },
337 { STV090x_P1_SFRLOWRATIO, 0x70 },
338 { STV090x_P1_TSCFGL, 0x20 },
339 { STV090x_P1_FECSPY, 0x88 },
340 { STV090x_P1_FSPYDATA, 0x3a },
341 { STV090x_P1_FBERCPT4, 0x00 },
342 { STV090x_P1_FSPYBER, 0x10 },
343 { STV090x_P1_ERRCTRL1, 0x35 },
344 { STV090x_P1_ERRCTRL2, 0xc1 },
345 { STV090x_P1_CFRICFG, 0xf8 },
346 { STV090x_P1_NOSCFG, 0x1c },
347 { STV090x_P1_CORRELMANT, 0x70 },
348 { STV090x_P1_CORRELABS, 0x88 },
56571507 349 { STV090x_P1_AGC2O, 0x5b },
e415c689
MA		 350 { STV090x_P1_AGC2REF, 0x38 },
351 { STV090x_P1_CARCFG, 0xe4 },
352 { STV090x_P1_ACLC, 0x1A },
353 { STV090x_P1_BCLC, 0x09 },
354 { STV090x_P1_CARHDR, 0x08 },
355 { STV090x_P1_KREFTMG, 0xc1 },
356 { STV090x_P1_SFRSTEP, 0x58 },
357 { STV090x_P1_TMGCFG2, 0x01 },
358 { STV090x_P1_CAR2CFG, 0x26 },
359 { STV090x_P1_BCLC2S2Q, 0x86 },
360 { STV090x_P1_BCLC2S28, 0x86 },
361 { STV090x_P1_SMAPCOEF7, 0x77 },
362 { STV090x_P1_SMAPCOEF6, 0x85 },
363 { STV090x_P1_SMAPCOEF5, 0x77 },
364 { STV090x_P1_DMDCFG2, 0x3b },
365 { STV090x_P1_MODCODLST0, 0xff },
366 { STV090x_P1_MODCODLST1, 0xff },
367 { STV090x_P1_MODCODLST2, 0xff },
368 { STV090x_P1_MODCODLST3, 0xff },
369 { STV090x_P1_MODCODLST4, 0xff },
370 { STV090x_P1_MODCODLST5, 0xff },
371 { STV090x_P1_MODCODLST6, 0xff },
372 { STV090x_P1_MODCODLST7, 0xcc },
373 { STV090x_P1_MODCODLST8, 0xcc },
374 { STV090x_P1_MODCODLST9, 0xcc },
375 { STV090x_P1_MODCODLSTA, 0xcc },
376 { STV090x_P1_MODCODLSTB, 0xcc },
377 { STV090x_P1_MODCODLSTC, 0xcc },
378 { STV090x_P1_MODCODLSTD, 0xcc },
379 { STV090x_P1_MODCODLSTE, 0xcc },
380 { STV090x_P1_MODCODLSTF, 0xcf },
381 { STV090x_GENCFG, 0x1d },
382 { STV090x_NBITER_NF4, 0x37 },
383 { STV090x_NBITER_NF5, 0x29 },
384 { STV090x_NBITER_NF6, 0x37 },
385 { STV090x_NBITER_NF7, 0x33 },
386 { STV090x_NBITER_NF8, 0x31 },
387 { STV090x_NBITER_NF9, 0x2f },
388 { STV090x_NBITER_NF10, 0x39 },
389 { STV090x_NBITER_NF11, 0x3a },
390 { STV090x_NBITER_NF12, 0x29 },
391 { STV090x_NBITER_NF13, 0x37 },
392 { STV090x_NBITER_NF14, 0x33 },
393 { STV090x_NBITER_NF15, 0x2f },
394 { STV090x_NBITER_NF16, 0x39 },
395 { STV090x_NBITER_NF17, 0x3a },
396 { STV090x_NBITERNOERR, 0x04 },
397 { STV090x_GAINLLR_NF4, 0x0C },
398 { STV090x_GAINLLR_NF5, 0x0F },
399 { STV090x_GAINLLR_NF6, 0x11 },
400 { STV090x_GAINLLR_NF7, 0x14 },
401 { STV090x_GAINLLR_NF8, 0x17 },
402 { STV090x_GAINLLR_NF9, 0x19 },
403 { STV090x_GAINLLR_NF10, 0x20 },
404 { STV090x_GAINLLR_NF11, 0x21 },
405 { STV090x_GAINLLR_NF12, 0x0D },
406 { STV090x_GAINLLR_NF13, 0x0F },
407 { STV090x_GAINLLR_NF14, 0x13 },
408 { STV090x_GAINLLR_NF15, 0x1A },
409 { STV090x_GAINLLR_NF16, 0x1F },
410 { STV090x_GAINLLR_NF17, 0x21 },
56571507 411 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 412 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
413 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
414 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
415 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
416};
417
418static struct stv090x_reg stv0903_initval[] = {
419 { STV090x_OUTCFG, 0x00 },
420 { STV090x_AGCRF1CFG, 0x11 },
421 { STV090x_STOPCLK1, 0x48 },
422 { STV090x_STOPCLK2, 0x14 },
423 { STV090x_TSTTNR1, 0x27 },
424 { STV090x_TSTTNR2, 0x21 },
425 { STV090x_P1_DISTXCTL, 0x22 },
426 { STV090x_P1_F22TX, 0xc0 },
427 { STV090x_P1_F22RX, 0xc0 },
428 { STV090x_P1_DISRXCTL, 0x00 },
429 { STV090x_P1_DMDCFGMD, 0xF9 },
430 { STV090x_P1_DEMOD, 0x08 },
431 { STV090x_P1_DMDCFG3, 0xc4 },
432 { STV090x_P1_CARFREQ, 0xed },
433 { STV090x_P1_TNRCFG2, 0x82 },
434 { STV090x_P1_LDT, 0xd0 },
435 { STV090x_P1_LDT2, 0xb8 },
436 { STV090x_P1_TMGCFG, 0xd2 },
437 { STV090x_P1_TMGTHRISE, 0x20 },
438 { STV090x_P1_TMGTHFALL, 0x00 },
439 { STV090x_P1_SFRUPRATIO, 0xf0 },
440 { STV090x_P1_SFRLOWRATIO, 0x70 },
441 { STV090x_P1_TSCFGL, 0x20 },
442 { STV090x_P1_FECSPY, 0x88 },
443 { STV090x_P1_FSPYDATA, 0x3a },
444 { STV090x_P1_FBERCPT4, 0x00 },
445 { STV090x_P1_FSPYBER, 0x10 },
446 { STV090x_P1_ERRCTRL1, 0x35 },
447 { STV090x_P1_ERRCTRL2, 0xc1 },
448 { STV090x_P1_CFRICFG, 0xf8 },
449 { STV090x_P1_NOSCFG, 0x1c },
56571507 450 { STV090x_P1_DMDTOM, 0x20 },
e415c689
MA		 451 { STV090x_P1_CORRELMANT, 0x70 },
452 { STV090x_P1_CORRELABS, 0x88 },
56571507
MA		 453 { STV090x_P1_AGC2O, 0x5b },
454 { STV090x_P1_AGC2REF, 0x38 },
e415c689
MA		 455 { STV090x_P1_CARCFG, 0xe4 },
456 { STV090x_P1_ACLC, 0x1A },
56571507 457 { STV090x_P1_BCLC, 0x09 },
e415c689
MA		 458 { STV090x_P1_CARHDR, 0x08 },
459 { STV090x_P1_KREFTMG, 0xc1 },
460 { STV090x_P1_SFRSTEP, 0x58 },
461 { STV090x_P1_TMGCFG2, 0x01 },
462 { STV090x_P1_CAR2CFG, 0x26 },
463 { STV090x_P1_BCLC2S2Q, 0x86 },
464 { STV090x_P1_BCLC2S28, 0x86 },
465 { STV090x_P1_SMAPCOEF7, 0x77 },
466 { STV090x_P1_SMAPCOEF6, 0x85 },
467 { STV090x_P1_SMAPCOEF5, 0x77 },
468 { STV090x_P1_DMDCFG2, 0x3b },
469 { STV090x_P1_MODCODLST0, 0xff },
470 { STV090x_P1_MODCODLST1, 0xff },
471 { STV090x_P1_MODCODLST2, 0xff },
472 { STV090x_P1_MODCODLST3, 0xff },
473 { STV090x_P1_MODCODLST4, 0xff },
474 { STV090x_P1_MODCODLST5, 0xff },
475 { STV090x_P1_MODCODLST6, 0xff },
476 { STV090x_P1_MODCODLST7, 0xcc },
477 { STV090x_P1_MODCODLST8, 0xcc },
478 { STV090x_P1_MODCODLST9, 0xcc },
479 { STV090x_P1_MODCODLSTA, 0xcc },
480 { STV090x_P1_MODCODLSTB, 0xcc },
481 { STV090x_P1_MODCODLSTC, 0xcc },
482 { STV090x_P1_MODCODLSTD, 0xcc },
483 { STV090x_P1_MODCODLSTE, 0xcc },
484 { STV090x_P1_MODCODLSTF, 0xcf },
485 { STV090x_GENCFG, 0x1c },
486 { STV090x_NBITER_NF4, 0x37 },
487 { STV090x_NBITER_NF5, 0x29 },
488 { STV090x_NBITER_NF6, 0x37 },
489 { STV090x_NBITER_NF7, 0x33 },
490 { STV090x_NBITER_NF8, 0x31 },
491 { STV090x_NBITER_NF9, 0x2f },
492 { STV090x_NBITER_NF10, 0x39 },
493 { STV090x_NBITER_NF11, 0x3a },
494 { STV090x_NBITER_NF12, 0x29 },
495 { STV090x_NBITER_NF13, 0x37 },
496 { STV090x_NBITER_NF14, 0x33 },
497 { STV090x_NBITER_NF15, 0x2f },
498 { STV090x_NBITER_NF16, 0x39 },
499 { STV090x_NBITER_NF17, 0x3a },
500 { STV090x_NBITERNOERR, 0x04 },
501 { STV090x_GAINLLR_NF4, 0x0C },
502 { STV090x_GAINLLR_NF5, 0x0F },
503 { STV090x_GAINLLR_NF6, 0x11 },
504 { STV090x_GAINLLR_NF7, 0x14 },
505 { STV090x_GAINLLR_NF8, 0x17 },
506 { STV090x_GAINLLR_NF9, 0x19 },
507 { STV090x_GAINLLR_NF10, 0x20 },
508 { STV090x_GAINLLR_NF11, 0x21 },
509 { STV090x_GAINLLR_NF12, 0x0D },
510 { STV090x_GAINLLR_NF13, 0x0F },
511 { STV090x_GAINLLR_NF14, 0x13 },
512 { STV090x_GAINLLR_NF15, 0x1A },
513 { STV090x_GAINLLR_NF16, 0x1F },
514 { STV090x_GAINLLR_NF17, 0x21 },
56571507 515 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 516 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
517 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
518};
519
520static struct stv090x_reg stv0900_cut20_val[] = {
521
522 { STV090x_P2_DMDCFG3, 0xe8 },
56571507 523 { STV090x_P2_DMDCFG4, 0x10 },
e415c689
MA		 524 { STV090x_P2_CARFREQ, 0x38 },
525 { STV090x_P2_CARHDR, 0x20 },
526 { STV090x_P2_KREFTMG, 0x5a },
527 { STV090x_P2_SMAPCOEF7, 0x06 },
528 { STV090x_P2_SMAPCOEF6, 0x00 },
529 { STV090x_P2_SMAPCOEF5, 0x04 },
530 { STV090x_P2_NOSCFG, 0x0c },
531 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 532 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 533 { STV090x_P1_CARFREQ, 0x38 },
534 { STV090x_P1_CARHDR, 0x20 },
535 { STV090x_P1_KREFTMG, 0x5a },
536 { STV090x_P1_SMAPCOEF7, 0x06 },
537 { STV090x_P1_SMAPCOEF6, 0x00 },
538 { STV090x_P1_SMAPCOEF5, 0x04 },
539 { STV090x_P1_NOSCFG, 0x0c },
540 { STV090x_GAINLLR_NF4, 0x21 },
541 { STV090x_GAINLLR_NF5, 0x21 },
542 { STV090x_GAINLLR_NF6, 0x20 },
543 { STV090x_GAINLLR_NF7, 0x1F },
544 { STV090x_GAINLLR_NF8, 0x1E },
545 { STV090x_GAINLLR_NF9, 0x1E },
546 { STV090x_GAINLLR_NF10, 0x1D },
547 { STV090x_GAINLLR_NF11, 0x1B },
548 { STV090x_GAINLLR_NF12, 0x20 },
549 { STV090x_GAINLLR_NF13, 0x20 },
550 { STV090x_GAINLLR_NF14, 0x20 },
551 { STV090x_GAINLLR_NF15, 0x20 },
552 { STV090x_GAINLLR_NF16, 0x20 },
553 { STV090x_GAINLLR_NF17, 0x21 },
554};
555
556static struct stv090x_reg stv0903_cut20_val[] = {
557 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 558 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 559 { STV090x_P1_CARFREQ, 0x38 },
560 { STV090x_P1_CARHDR, 0x20 },
561 { STV090x_P1_KREFTMG, 0x5a },
562 { STV090x_P1_SMAPCOEF7, 0x06 },
563 { STV090x_P1_SMAPCOEF6, 0x00 },
564 { STV090x_P1_SMAPCOEF5, 0x04 },
565 { STV090x_P1_NOSCFG, 0x0c },
566 { STV090x_GAINLLR_NF4, 0x21 },
567 { STV090x_GAINLLR_NF5, 0x21 },
568 { STV090x_GAINLLR_NF6, 0x20 },
569 { STV090x_GAINLLR_NF7, 0x1F },
570 { STV090x_GAINLLR_NF8, 0x1E },
571 { STV090x_GAINLLR_NF9, 0x1E },
572 { STV090x_GAINLLR_NF10, 0x1D },
573 { STV090x_GAINLLR_NF11, 0x1B },
574 { STV090x_GAINLLR_NF12, 0x20 },
575 { STV090x_GAINLLR_NF13, 0x20 },
576 { STV090x_GAINLLR_NF14, 0x20 },
577 { STV090x_GAINLLR_NF15, 0x20 },
578 { STV090x_GAINLLR_NF16, 0x20 },
579 { STV090x_GAINLLR_NF17, 0x21 }
580};
581
e415c689
MA		 582/* Cut 2.0 Long Frame Tracking CR loop */
583static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
584 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
585 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
586 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
587 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
588 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
589 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
590 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
593 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
594 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
595 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
596 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
597 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
598 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
599};
600
27d40321
MA		 601/* Cut 3.0 Long Frame Tracking CR loop */
602static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
603 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
604 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
605 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
606 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
607 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
608 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
609 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
610 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
611 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
612 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
613 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
614 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
615 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
616 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
617 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
618};
e415c689
MA		 619
620/* Cut 2.0 Long Frame Tracking CR Loop */
621static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
622 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
623 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
624 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
625 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
626 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
627 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
628 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
629 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
630 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
631 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
632 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
633 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
634};
635
27d40321
MA		 636/* Cut 3.0 Long Frame Tracking CR Loop */
637static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
638 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
639 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
640 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
641 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
642 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
643 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
644 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
645 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
646 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
647 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
648 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
649 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
650};
e415c689
MA		 651
652static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
653 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
654 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
655 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
656 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
657};
658
27d40321
MA		 659static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
660 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
661 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
662 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
663 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
664};
e415c689 665
27d40321
MA		 666/* Cut 2.0 Short Frame Tracking CR Loop */
667static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
668 /* MODCOD 2M 5M 10M 20M 30M */
669 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
670 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
671 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
672 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
e415c689
MA		 673};
674
27d40321
MA		 675/* Cut 3.0 Short Frame Tracking CR Loop */
676static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
677 /* MODCOD 2M 5M 10M 20M 30M */
678 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
679 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
680 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
681 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
682};
e415c689
MA		 683
684static inline s32 comp2(s32 __x, s32 __width)
685{
686 if (__width == 32)
687 return __x;
688 else
689 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
690}
691
692static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
693{
694 const struct stv090x_config *config = state->config;
695 int ret;
696
697 u8 b0[] = { reg >> 8, reg & 0xff };
698 u8 buf;
699
700 struct i2c_msg msg[] = {
701 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
702 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
703 };
704
705 ret = i2c_transfer(state->i2c, msg, 2);
706 if (ret != 2) {
707 if (ret != -ERESTARTSYS)
708 dprintk(FE_ERROR, 1,
709 "Read error, Reg=[0x%02x], Status=%d",
710 reg, ret);
711
712 return ret < 0 ? ret : -EREMOTEIO;
713 }
714 if (unlikely(*state->verbose >= FE_DEBUGREG))
715 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
716 reg, buf);
717
718 return (unsigned int) buf;
719}
720
721static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
722{
723 const struct stv090x_config *config = state->config;
724 int ret;
725 u8 buf[2 + count];
726 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
727
728 buf[0] = reg >> 8;
729 buf[1] = reg & 0xff;
730 memcpy(&buf[2], data, count);
731
732 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
733 int i;
734
735 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
736 for (i = 0; i < count; i++)
737 printk(" %02x", data[i]);
738 printk("\n");
739 }
740
741 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
742 if (ret != 1) {
743 if (ret != -ERESTARTSYS)
744 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
745 reg, data[0], count, ret);
746 return ret < 0 ? ret : -EREMOTEIO;
747 }
748
749 return 0;
750}
751
752static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
753{
754 return stv090x_write_regs(state, reg, &data, 1);
755}
756
19c4ee58 757static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
e415c689 758{
e415c689
MA		 759 u32 reg;
760
96506a50
AR		 761 if (enable)
762 mutex_lock(&state->internal->tuner_lock);
763
e415c689 764 reg = STV090x_READ_DEMOD(state, I2CRPT);
e415c689 765 if (enable) {
017eb038 766 dprintk(FE_DEBUG, 1, "Enable Gate");
e415c689
MA		 767 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
768 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
769 goto err;
770
771 } else {
017eb038 772 dprintk(FE_DEBUG, 1, "Disable Gate");
e415c689
MA		 773 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
774 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
775 goto err;
776 }
96506a50
AR		 777
778 if (!enable)
779 mutex_unlock(&state->internal->tuner_lock);
780
e415c689
MA		 781 return 0;
782err:
783 dprintk(FE_ERROR, 1, "I/O error");
96506a50 784 mutex_unlock(&state->internal->tuner_lock);
e415c689
MA		 785 return -1;
786}
787
788static void stv090x_get_lock_tmg(struct stv090x_state *state)
789{
790 switch (state->algo) {
791 case STV090x_BLIND_SEARCH:
792 dprintk(FE_DEBUG, 1, "Blind Search");
793 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
794 state->DemodTimeout = 1500;
795 state->FecTimeout = 400;
796 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
797 state->DemodTimeout = 1000;
798 state->FecTimeout = 300;
799 } else { /*SR >20Msps*/
800 state->DemodTimeout = 700;
801 state->FecTimeout = 100;
802 }
803 break;
804
805 case STV090x_COLD_SEARCH:
806 case STV090x_WARM_SEARCH:
807 default:
808 dprintk(FE_DEBUG, 1, "Normal Search");
809 if (state->srate <= 1000000) { /*SR <=1Msps*/
810 state->DemodTimeout = 4500;
811 state->FecTimeout = 1700;
812 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
813 state->DemodTimeout = 2500;
814 state->FecTimeout = 1100;
815 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
816 state->DemodTimeout = 1000;
817 state->FecTimeout = 550;
818 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
819 state->DemodTimeout = 700;
820 state->FecTimeout = 250;
821 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
822 state->DemodTimeout = 400;
823 state->FecTimeout = 130;
824 } else { /*SR >20Msps*/
825 state->DemodTimeout = 300;
826 state->FecTimeout = 100;
827 }
828 break;
829 }
830
831 if (state->algo == STV090x_WARM_SEARCH)
832 state->DemodTimeout /= 2;
833}
834
835static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
836{
837 u32 sym;
838
15bb366e
MA		 839 if (srate > 60000000) {
840 sym = (srate << 4); /* SR * 2^16 / master_clk */
97f7a2ae 841 sym /= (state->internal->mclk >> 12);
15bb366e
MA		 842 } else if (srate > 6000000) {
843 sym = (srate << 6);
97f7a2ae 844 sym /= (state->internal->mclk >> 10);
e415c689 845 } else {
15bb366e 846 sym = (srate << 9);
97f7a2ae 847 sym /= (state->internal->mclk >> 7);
e415c689
MA		 848 }
849
15bb366e 850 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
e415c689
MA		 851 goto err;
852 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
853 goto err;
15bb366e 854
e415c689
MA		 855 return 0;
856err:
857 dprintk(FE_ERROR, 1, "I/O error");
858 return -1;
859}
860
861static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
862{
863 u32 sym;
864
865 srate = 105 * (srate / 100);
15bb366e
MA		 866 if (srate > 60000000) {
867 sym = (srate << 4); /* SR * 2^16 / master_clk */
97f7a2ae 868 sym /= (state->internal->mclk >> 12);
15bb366e
MA		 869 } else if (srate > 6000000) {
870 sym = (srate << 6);
97f7a2ae 871 sym /= (state->internal->mclk >> 10);
e415c689 872 } else {
15bb366e 873 sym = (srate << 9);
97f7a2ae 874 sym /= (state->internal->mclk >> 7);
e415c689 875 }
15bb366e
MA		 876
877 if (sym < 0x7fff) {
878 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
879 goto err;
880 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
881 goto err;
882 } else {
883 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
884 goto err;
885 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
886 goto err;
887 }
888
e415c689
MA		 889 return 0;
890err:
891 dprintk(FE_ERROR, 1, "I/O error");
892 return -1;
893}
894
895static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
896{
897 u32 sym;
898
899 srate = 95 * (srate / 100);
15bb366e
MA		 900 if (srate > 60000000) {
901 sym = (srate << 4); /* SR * 2^16 / master_clk */
97f7a2ae 902 sym /= (state->internal->mclk >> 12);
15bb366e
MA		 903 } else if (srate > 6000000) {
904 sym = (srate << 6);
97f7a2ae 905 sym /= (state->internal->mclk >> 10);
e415c689 906 } else {
15bb366e 907 sym = (srate << 9);
97f7a2ae 908 sym /= (state->internal->mclk >> 7);
e415c689 909 }
15bb366e 910
b671a8d4 911 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
e415c689
MA		 912 goto err;
913 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
914 goto err;
915 return 0;
916err:
917 dprintk(FE_ERROR, 1, "I/O error");
918 return -1;
919}
920
4e58a682 921static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
e415c689 922{
4e58a682
AR		 923 u32 ro;
924
925 switch (rolloff) {
926 case STV090x_RO_20:
927 ro = 20;
928 break;
929 case STV090x_RO_25:
930 ro = 25;
931 break;
932 case STV090x_RO_35:
933 default:
934 ro = 35;
935 break;
936 }
937
938 return srate + (srate * ro) / 100;
e415c689
MA		 939}
940
941static int stv090x_set_vit_thacq(struct stv090x_state *state)
942{
943 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
944 goto err;
945 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
946 goto err;
947 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
948 goto err;
949 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
950 goto err;
951 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
952 goto err;
953 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
954 goto err;
955 return 0;
956err:
957 dprintk(FE_ERROR, 1, "I/O error");
958 return -1;
959}
960
961static int stv090x_set_vit_thtracq(struct stv090x_state *state)
962{
963 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
964 goto err;
965 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
966 goto err;
967 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
968 goto err;
969 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
970 goto err;
971 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
972 goto err;
973 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
974 goto err;
975 return 0;
976err:
977 dprintk(FE_ERROR, 1, "I/O error");
978 return -1;
979}
980
981static int stv090x_set_viterbi(struct stv090x_state *state)
982{
983 switch (state->search_mode) {
984 case STV090x_SEARCH_AUTO:
985 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
986 goto err;
987 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
988 goto err;
989 break;
990 case STV090x_SEARCH_DVBS1:
991 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
992 goto err;
993 switch (state->fec) {
994 case STV090x_PR12:
995 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
996 goto err;
997 break;
998
999 case STV090x_PR23:
1000 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1001 goto err;
1002 break;
1003
1004 case STV090x_PR34:
1005 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1006 goto err;
1007 break;
1008
1009 case STV090x_PR56:
1010 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1011 goto err;
1012 break;
1013
1014 case STV090x_PR78:
1015 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1016 goto err;
1017 break;
1018
1019 default:
1020 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1021 goto err;
1022 break;
1023 }
1024 break;
1025 case STV090x_SEARCH_DSS:
1026 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1027 goto err;
1028 switch (state->fec) {
1029 case STV090x_PR12:
1030 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1031 goto err;
1032 break;
1033
1034 case STV090x_PR23:
1035 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1036 goto err;
1037 break;
1038
1039 case STV090x_PR67:
1040 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1041 goto err;
1042 break;
1043
1044 default:
1045 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1046 goto err;
1047 break;
1048 }
1049 break;
1050 default:
1051 break;
1052 }
1053 return 0;
1054err:
1055 dprintk(FE_ERROR, 1, "I/O error");
1056 return -1;
1057}
1058
1059static int stv090x_stop_modcod(struct stv090x_state *state)
1060{
1061 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1062 goto err;
1063 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1064 goto err;
1065 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1066 goto err;
1067 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1068 goto err;
1069 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1070 goto err;
1071 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1072 goto err;
1073 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1074 goto err;
1075 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1076 goto err;
1077 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1078 goto err;
1079 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1080 goto err;
1081 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1082 goto err;
1083 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1084 goto err;
1085 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1086 goto err;
1087 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1088 goto err;
1089 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1090 goto err;
1091 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1092 goto err;
1093 return 0;
1094err:
1095 dprintk(FE_ERROR, 1, "I/O error");
1096 return -1;
1097}
1098
1099static int stv090x_activate_modcod(struct stv090x_state *state)
1100{
27d40321
MA		 1101 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1102 goto err;
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1104 goto err;
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1106 goto err;
1107 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1108 goto err;
1109 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1110 goto err;
1111 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1112 goto err;
1113 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1114 goto err;
1115 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1116 goto err;
1117 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1118 goto err;
1119 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1120 goto err;
1121 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1122 goto err;
1123 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1124 goto err;
1125 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1126 goto err;
1127 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1128 goto err;
1129 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1130 goto err;
1131 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1132 goto err;
e415c689 1133
27d40321
MA		 1134 return 0;
1135err:
1136 dprintk(FE_ERROR, 1, "I/O error");
1137 return -1;
1138}
1139
1140static int stv090x_activate_modcod_single(struct stv090x_state *state)
1141{
1142
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1144 goto err;
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1146 goto err;
1147 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1148 goto err;
1149 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1150 goto err;
1151 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1152 goto err;
1153 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1154 goto err;
1155 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1156 goto err;
1157 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1158 goto err;
1159 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1160 goto err;
1161 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1162 goto err;
1163 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1164 goto err;
1165 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1166 goto err;
1167 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1168 goto err;
1169 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1170 goto err;
1171 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1172 goto err;
1173 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1174 goto err;
e415c689 1175
e415c689 1176 return 0;
27d40321 1177
e415c689
MA		 1178err:
1179 dprintk(FE_ERROR, 1, "I/O error");
1180 return -1;
1181}
1182
1183static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1184{
1185 u32 reg;
1186
1187 switch (state->demod) {
1188 case STV090x_DEMODULATOR_0:
97f7a2ae 1189 mutex_lock(&state->internal->demod_lock);
e415c689
MA		 1190 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1191 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1192 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1193 goto err;
97f7a2ae 1194 mutex_unlock(&state->internal->demod_lock);
e415c689
MA		 1195 break;
1196
1197 case STV090x_DEMODULATOR_1:
97f7a2ae 1198 mutex_lock(&state->internal->demod_lock);
e415c689
MA		 1199 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1200 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1201 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1202 goto err;
97f7a2ae 1203 mutex_unlock(&state->internal->demod_lock);
e415c689
MA		 1204 break;
1205
1206 default:
1207 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1208 break;
1209 }
1210 return 0;
1211err:
97f7a2ae 1212 mutex_unlock(&state->internal->demod_lock);
e415c689
MA		 1213 dprintk(FE_ERROR, 1, "I/O error");
1214 return -1;
1215}
1216
27d40321
MA		 1217static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1218{
97f7a2ae 1219 if (state->internal->dev_ver >= 0x30) {
27d40321
MA		 1220 /* Set ACLC BCLC optimised value vs SR */
1221 if (state->srate >= 15000000) {
1222 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1223 goto err;
1224 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1225 goto err;
1226 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1227 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1228 goto err;
1229 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1230 goto err;
1231 } else if (state->srate < 7000000) {
1232 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1233 goto err;
1234 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1235 goto err;
1236 }
1237
1238 } else {
1239 /* Cut 2.0 */
1240 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1241 goto err;
1242 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1243 goto err;
1244 }
1245 return 0;
1246err:
1247 dprintk(FE_ERROR, 1, "I/O error");
1248 return -1;
1249}
1250
e415c689
MA		 1251static int stv090x_delivery_search(struct stv090x_state *state)
1252{
1253 u32 reg;
1254
1255 switch (state->search_mode) {
1256 case STV090x_SEARCH_DVBS1:
1257 case STV090x_SEARCH_DSS:
1258 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1259 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1260 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1261 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1262 goto err;
1263
27d40321
MA		 1264 /* Activate Viterbi decoder in legacy search,
1265 * do not use FRESVIT1, might impact VITERBI2
1266 */
e415c689
MA		 1267 if (stv090x_vitclk_ctl(state, 0) < 0)
1268 goto err;
1269
27d40321 1270 if (stv090x_dvbs_track_crl(state) < 0)
e415c689 1271 goto err;
27d40321 1272
e415c689
MA		 1273 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1274 goto err;
1275
27d40321
MA		 1276 if (stv090x_set_vit_thacq(state) < 0)
1277 goto err;
1278 if (stv090x_set_viterbi(state) < 0)
1279 goto err;
e415c689
MA		 1280 break;
1281
1282 case STV090x_SEARCH_DVBS2:
1283 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1284 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1285 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1286 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1287 goto err;
1288 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1289 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1290 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1291 goto err;
1292
1293 if (stv090x_vitclk_ctl(state, 1) < 0)
1294 goto err;
1295
1296 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1297 goto err;
1298 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1299 goto err;
27d40321 1300
97f7a2ae 1301 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1302 /* enable S2 carrier loop */
1303 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1304 goto err;
1305 } else {
1306 /* > Cut 3: Stop carrier 3 */
1307 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1308 goto err;
1309 }
e415c689
MA		 1310
1311 if (state->demod_mode != STV090x_SINGLE) {
27d40321
MA		 1312 /* Cut 2: enable link during search */
1313 if (stv090x_activate_modcod(state) < 0)
1314 goto err;
1315 } else {
1316 /* Single demodulator
1317 * Authorize SHORT and LONG frames,
1318 * QPSK, 8PSK, 16APSK and 32APSK
1319 */
1320 if (stv090x_activate_modcod_single(state) < 0)
1321 goto err;
e415c689 1322 }
27d40321 1323
7b035da9
AR		 1324 if (stv090x_set_vit_thtracq(state) < 0)
1325 goto err;
e415c689
MA		 1326 break;
1327
1328 case STV090x_SEARCH_AUTO:
1329 default:
27d40321 1330 /* enable DVB-S2 and DVB-S2 in Auto MODE */
e415c689 1331 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
b79c6df7
AR		 1332 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1333 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1334 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1335 goto err;
e415c689
MA		 1336 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1337 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1338 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1339 goto err;
1340
4e58a682 1341 if (stv090x_vitclk_ctl(state, 0) < 0)
e415c689
MA		 1342 goto err;
1343
27d40321 1344 if (stv090x_dvbs_track_crl(state) < 0)
e415c689
MA		 1345 goto err;
1346
97f7a2ae 1347 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1348 /* enable S2 carrier loop */
1349 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1350 goto err;
1351 } else {
1352 /* > Cut 3: Stop carrier 3 */
1353 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1354 goto err;
1355 }
1356
e415c689 1357 if (state->demod_mode != STV090x_SINGLE) {
27d40321
MA		 1358 /* Cut 2: enable link during search */
1359 if (stv090x_activate_modcod(state) < 0)
1360 goto err;
1361 } else {
1362 /* Single demodulator
1363 * Authorize SHORT and LONG frames,
1364 * QPSK, 8PSK, 16APSK and 32APSK
1365 */
1366 if (stv090x_activate_modcod_single(state) < 0)
1367 goto err;
e415c689 1368 }
27d40321 1369
7b035da9
AR		 1370 if (stv090x_set_vit_thacq(state) < 0)
1371 goto err;
27d40321
MA		 1372
1373 if (stv090x_set_viterbi(state) < 0)
1374 goto err;
e415c689
MA		 1375 break;
1376 }
1377 return 0;
1378err:
1379 dprintk(FE_ERROR, 1, "I/O error");
1380 return -1;
1381}
1382
1383static int stv090x_start_search(struct stv090x_state *state)
1384{
27d40321
MA		 1385 u32 reg, freq_abs;
1386 s16 freq;
e415c689 1387
27d40321 1388 /* Reset demodulator */
e415c689
MA		 1389 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1390 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1391 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1392 goto err;
1393
97f7a2ae 1394 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1395 if (state->srate <= 5000000) {
1396 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1397 goto err;
1398 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1399 goto err;
b671a8d4 1400 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
27d40321
MA		 1401 goto err;
1402 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1403 goto err;
1404 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1405 goto err;
1406
1407 /*enlarge the timing bandwith for Low SR*/
1408 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1409 goto err;
1410 } else {
1411 /* If the symbol rate is >5 Msps
1412 Set The carrier search up and low to auto mode */
1413 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1414 goto err;
1415 /*reduce the timing bandwith for high SR*/
1416 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1417 goto err;
1418 }
1419 } else {
1420 /* >= Cut 3 */
1421 if (state->srate <= 5000000) {
1422 /* enlarge the timing bandwith for Low SR */
1423 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1424 } else {
1425 /* reduce timing bandwith for high SR */
1426 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1427 }
1428
1429 /* Set CFR min and max to manual mode */
1430 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1431
1432 if (state->algo == STV090x_WARM_SEARCH) {
1433 /* WARM Start
1434 * CFR min = -1MHz,
1435 * CFR max = +1MHz
1436 */
1437 freq_abs = 1000 << 16;
97f7a2ae 1438 freq_abs /= (state->internal->mclk / 1000);
27d40321
MA		 1439 freq = (s16) freq_abs;
1440 } else {
1441 /* COLD Start
1442 * CFR min =- (SearchRange / 2 + 600KHz)
1443 * CFR max = +(SearchRange / 2 + 600KHz)
1444 * (600KHz for the tuner step size)
1445 */
1446 freq_abs = (state->search_range / 2000) + 600;
1447 freq_abs = freq_abs << 16;
97f7a2ae 1448 freq_abs /= (state->internal->mclk / 1000);
27d40321
MA		 1449 freq = (s16) freq_abs;
1450 }
1451
1452 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
e415c689 1453 goto err;
b671a8d4 1454 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
e415c689
MA		 1455 goto err;
1456
27d40321
MA		 1457 freq *= -1;
1458
1459 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
e415c689 1460 goto err;
27d40321 1461 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
e415c689 1462 goto err;
27d40321 1463
e415c689 1464 }
27d40321 1465
e415c689
MA		 1466 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1467 goto err;
1468 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1469 goto err;
1470
97f7a2ae 1471 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 1472 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1473 goto err;
1474 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1475 goto err;
1476
1477 if ((state->search_mode == STV090x_DVBS1) ||
1478 (state->search_mode == STV090x_DSS) ||
1479 (state->search_mode == STV090x_SEARCH_AUTO)) {
1480
1481 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1482 goto err;
1483 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1484 goto err;
1485 }
1486 }
1487
1488 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1489 goto err;
1490 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1491 goto err;
1492 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1493 goto err;
1494
1495 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1496 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1497 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1498 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1499 goto err;
1500 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1501 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1502 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1503 goto err;
1504
7b035da9
AR		 1505 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1506 goto err;
1507
97f7a2ae 1508 if (state->internal->dev_ver >= 0x20) {
27d40321
MA		 1509 /*Frequency offset detector setting*/
1510 if (state->srate < 2000000) {
97f7a2ae 1511 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 1512 /* Cut 2 */
1513 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1514 goto err;
1515 } else {
7b035da9 1516 /* Cut 3 */
27d40321
MA		 1517 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1518 goto err;
1519 }
1520 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1521 goto err;
a4978a83 1522 } else if (state->srate < 10000000) {
e415c689
MA		 1523 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1524 goto err;
7b035da9
AR		 1525 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1526 goto err;
e415c689
MA		 1527 } else {
1528 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1529 goto err;
7b035da9
AR		 1530 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1531 goto err;
e415c689
MA		 1532 }
1533 } else {
1534 if (state->srate < 10000000) {
1535 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1536 goto err;
1537 } else {
1538 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1539 goto err;
1540 }
1541 }
1542
1543 switch (state->algo) {
27d40321
MA		 1544 case STV090x_WARM_SEARCH:
1545 /* The symbol rate and the exact
1546 * carrier Frequency are known
1547 */
e415c689
MA		 1548 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1549 goto err;
1550 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1551 goto err;
1552 break;
1553
27d40321
MA		 1554 case STV090x_COLD_SEARCH:
1555 /* The symbol rate is known */
e415c689
MA		 1556 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1557 goto err;
1558 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1559 goto err;
1560 break;
1561
1562 default:
1563 break;
1564 }
1565 return 0;
1566err:
1567 dprintk(FE_ERROR, 1, "I/O error");
1568 return -1;
1569}
1570
1571static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1572{
b4a4248d 1573 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
e415c689
MA		 1574 s32 i, j, steps, dir;
1575
1576 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1577 goto err;
1578 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
7b035da9
AR		 1579 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1580 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
e415c689
MA		 1581 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1582 goto err;
1583
1584 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1585 goto err;
1586 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1587 goto err;
1588 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1589 goto err;
1590 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1591 goto err;
1592 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1593 goto err;
27d40321
MA		 1594 if (stv090x_set_srate(state, 1000000) < 0)
1595 goto err;
e415c689 1596
7b035da9
AR		 1597 steps = state->search_range / 1000000;
1598 if (steps <= 0)
e415c689
MA		 1599 steps = 1;
1600
1601 dir = 1;
97f7a2ae 1602 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
e415c689
MA		 1603 freq_init = 0;
1604
1605 for (i = 0; i < steps; i++) {
1606 if (dir > 0)
1607 freq_init = freq_init + (freq_step * i);
1608 else
1609 freq_init = freq_init - (freq_step * i);
1610
b671a8d4 1611 dir *= -1;
e415c689
MA		 1612
1613 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1614 goto err;
1615 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1616 goto err;
1617 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1618 goto err;
1619 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1620 goto err;
1621 msleep(10);
b4a4248d
AR		 1622
1623 agc2 = 0;
e415c689 1624 for (j = 0; j < 10; j++) {
b4a4248d
AR		 1625 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1626 STV090x_READ_DEMOD(state, AGC2I0);
e415c689
MA		 1627 }
1628 agc2 /= 10;
b4a4248d 1629 if (agc2 < agc2_min)
e415c689
MA		 1630 agc2_min = agc2;
1631 }
1632
1633 return agc2_min;
1634err:
1635 dprintk(FE_ERROR, 1, "I/O error");
1636 return -1;
1637}
1638
1639static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1640{
1641 u8 r3, r2, r1, r0;
1642 s32 srate, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 1643
1644 r3 = STV090x_READ_DEMOD(state, SFR3);
1645 r2 = STV090x_READ_DEMOD(state, SFR2);
1646 r1 = STV090x_READ_DEMOD(state, SFR1);
1647 r0 = STV090x_READ_DEMOD(state, SFR0);
1648
1649 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1650
f430fff1
MA		 1651 int_1 = clk >> 16;
1652 int_2 = srate >> 16;
e415c689 1653
f430fff1
MA		 1654 tmp_1 = clk % 0x10000;
1655 tmp_2 = srate % 0x10000;
e415c689
MA		 1656
1657 srate = (int_1 * int_2) +
f430fff1
MA		 1658 ((int_1 * tmp_2) >> 16) +
1659 ((int_2 * tmp_1) >> 16);
e415c689
MA		 1660
1661 return srate;
1662}
1663
1664static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1665{
1666 struct dvb_frontend *fe = &state->frontend;
1667
1668 int tmg_lock = 0, i;
1669 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1670 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
b4a4248d
AR		 1671 u32 agc2th;
1672
97f7a2ae 1673 if (state->internal->dev_ver >= 0x30)
b4a4248d
AR		 1674 agc2th = 0x2e00;
1675 else
1676 agc2th = 0x1f00;
e415c689
MA		 1677
1678 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1679 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1680 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1681 goto err;
1682 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1683 goto err;
7b035da9
AR		 1684 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1685 goto err;
e415c689
MA		 1686 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1687 goto err;
1688 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1689 goto err;
1690 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1691 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
7b035da9 1692 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
e415c689
MA		 1693 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1694 goto err;
1695
1696 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1697 goto err;
1698 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1699 goto err;
1700 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1701 goto err;
1702 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1703 goto err;
1704 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1705 goto err;
b4a4248d 1706 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
e415c689
MA		 1707 goto err;
1708
97f7a2ae 1709 if (state->internal->dev_ver >= 0x30) {
27d40321 1710 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
e415c689 1711 goto err;
7b035da9 1712 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
e415c689 1713 goto err;
27d40321 1714
97f7a2ae 1715 } else if (state->internal->dev_ver >= 0x20) {
27d40321 1716 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
e415c689 1717 goto err;
27d40321 1718 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
e415c689
MA		 1719 goto err;
1720 }
1721
1722 if (state->srate <= 2000000)
1723 car_step = 1000;
1724 else if (state->srate <= 5000000)
1725 car_step = 2000;
1726 else if (state->srate <= 12000000)
1727 car_step = 3000;
1728 else
1729 car_step = 5000;
1730
1731 steps = -1 + ((state->search_range / 1000) / car_step);
1732 steps /= 2;
1733 steps = (2 * steps) + 1;
1734 if (steps < 0)
1735 steps = 1;
1736 else if (steps > 10) {
1737 steps = 11;
1738 car_step = (state->search_range / 1000) / 10;
1739 }
1740 cur_step = 0;
1741 dir = 1;
1742 freq = state->frequency;
1743
1744 while ((!tmg_lock) && (cur_step < steps)) {
1745 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1746 goto err;
7b035da9
AR		 1747 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1748 goto err;
1749 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1750 goto err;
1751 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1752 goto err;
1753 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1754 goto err;
1755 /* trigger acquisition */
1756 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
e415c689
MA		 1757 goto err;
1758 msleep(50);
1759 for (i = 0; i < 10; i++) {
1760 reg = STV090x_READ_DEMOD(state, DSTATUS);
1761 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1762 tmg_cpt++;
b4a4248d
AR		 1763 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1764 STV090x_READ_DEMOD(state, AGC2I0);
e415c689
MA		 1765 }
1766 agc2 /= 10;
97f7a2ae 1767 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 1768 cur_step++;
1769 dir *= -1;
b4a4248d
AR		 1770 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1771 (srate_coarse < 50000000) && (srate_coarse > 850000))
e415c689
MA		 1772 tmg_lock = 1;
1773 else if (cur_step < steps) {
1774 if (dir > 0)
1775 freq += cur_step * car_step;
1776 else
1777 freq -= cur_step * car_step;
1778
1779 /* Setup tuner */
19c4ee58 1780 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 1781 goto err;
e415c689 1782
27d40321 1783 if (state->config->tuner_set_frequency) {
a4978a83 1784 if (state->config->tuner_set_frequency(fe, freq) < 0)
2c1f750b 1785 goto err_gateoff;
27d40321 1786 }
e415c689 1787
27d40321
MA		 1788 if (state->config->tuner_set_bandwidth) {
1789 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 1790 goto err_gateoff;
27d40321
MA		 1791 }
1792
19c4ee58 1793 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 1794 goto err;
e415c689 1795
e415c689 1796 msleep(50);
e415c689 1797
19c4ee58 1798 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321
MA		 1799 goto err;
1800
1801 if (state->config->tuner_get_status) {
1802 if (state->config->tuner_get_status(fe, &reg) < 0)
2c1f750b 1803 goto err_gateoff;
27d40321 1804 }
e415c689
MA		 1805
1806 if (reg)
1807 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1808 else
1809 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1810
19c4ee58 1811 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 1812 goto err;
e415c689
MA		 1813
1814 }
1815 }
1816 if (!tmg_lock)
1817 srate_coarse = 0;
1818 else
97f7a2ae 1819 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 1820
1821 return srate_coarse;
2c1f750b
OE		 1822
1823err_gateoff:
19c4ee58 1824 stv090x_i2c_gate_ctrl(state, 0);
e415c689
MA		 1825err:
1826 dprintk(FE_ERROR, 1, "I/O error");
1827 return -1;
1828}
1829
1830static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1831{
1832 u32 srate_coarse, freq_coarse, sym, reg;
1833
97f7a2ae 1834 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 1835 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1836 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1837 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1838
1839 if (sym < state->srate)
1840 srate_coarse = 0;
1841 else {
1842 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1843 goto err;
7b035da9 1844 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
e415c689
MA		 1845 goto err;
1846 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1847 goto err;
1848 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1849 goto err;
1850 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1851 goto err;
1852 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1853 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1854 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1855 goto err;
1856
b4a4248d
AR		 1857 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1858 goto err;
1859
97f7a2ae 1860 if (state->internal->dev_ver >= 0x30) {
27d40321 1861 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
e415c689 1862 goto err;
97f7a2ae 1863 } else if (state->internal->dev_ver >= 0x20) {
27d40321 1864 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
e415c689
MA		 1865 goto err;
1866 }
1867
1868 if (srate_coarse > 3000000) {
1869 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1870 sym = (sym / 1000) * 65536;
97f7a2ae 1871 sym /= (state->internal->mclk / 1000);
e415c689
MA		 1872 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1873 goto err;
1874 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1875 goto err;
1876 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1877 sym = (sym / 1000) * 65536;
97f7a2ae 1878 sym /= (state->internal->mclk / 1000);
e415c689
MA		 1879 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1880 goto err;
1881 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1882 goto err;
1883 sym = (srate_coarse / 1000) * 65536;
97f7a2ae 1884 sym /= (state->internal->mclk / 1000);
e415c689
MA		 1885 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1886 goto err;
1887 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1888 goto err;
1889 } else {
1890 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1891 sym = (sym / 100) * 65536;
97f7a2ae 1892 sym /= (state->internal->mclk / 100);
e415c689
MA		 1893 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1894 goto err;
1895 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1896 goto err;
1897 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1898 sym = (sym / 100) * 65536;
97f7a2ae 1899 sym /= (state->internal->mclk / 100);
e415c689
MA		 1900 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1901 goto err;
1902 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1903 goto err;
1904 sym = (srate_coarse / 100) * 65536;
97f7a2ae 1905 sym /= (state->internal->mclk / 100);
e415c689
MA		 1906 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1907 goto err;
1908 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1909 goto err;
1910 }
1911 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1912 goto err;
1913 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1914 goto err;
1915 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1916 goto err;
1917 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1918 goto err;
1919 }
1920
1921 return srate_coarse;
1922
1923err:
1924 dprintk(FE_ERROR, 1, "I/O error");
1925 return -1;
1926}
1927
1928static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1929{
1930 s32 timer = 0, lock = 0;
1931 u32 reg;
1932 u8 stat;
1933
1934 while ((timer < timeout) && (!lock)) {
1935 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1936 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1937
1938 switch (stat) {
1939 case 0: /* searching */
1940 case 1: /* first PLH detected */
1941 default:
1942 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1943 lock = 0;
1944 break;
1945 case 2: /* DVB-S2 mode */
1946 case 3: /* DVB-S1/legacy mode */
1947 reg = STV090x_READ_DEMOD(state, DSTATUS);
1948 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1949 break;
1950 }
1951
1952 if (!lock)
1953 msleep(10);
1954 else
1955 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1956
1957 timer += 10;
1958 }
1959 return lock;
1960}
1961
1962static int stv090x_blind_search(struct stv090x_state *state)
1963{
1964 u32 agc2, reg, srate_coarse;
a4978a83 1965 s32 cpt_fail, agc2_ovflw, i;
e415c689 1966 u8 k_ref, k_max, k_min;
690c79ae
AM		 1967 int coarse_fail = 0;
1968 int lock;
e415c689 1969
7b035da9
AR		 1970 k_max = 110;
1971 k_min = 10;
e415c689
MA		 1972
1973 agc2 = stv090x_get_agc2_min_level(state);
1974
97f7a2ae 1975 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
e415c689
MA		 1976 lock = 0;
1977 } else {
27d40321 1978
97f7a2ae 1979 if (state->internal->dev_ver <= 0x20) {
27d40321 1980 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
e415c689 1981 goto err;
27d40321
MA		 1982 } else {
1983 /* > Cut 3 */
1984 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
e415c689
MA		 1985 goto err;
1986 }
1987
e415c689
MA		 1988 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1989 goto err;
27d40321 1990
97f7a2ae 1991 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 1992 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1993 goto err;
1994 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1995 goto err;
1996 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1997 goto err;
1998 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1999 goto err;
2000 }
2001
2002 k_ref = k_max;
2003 do {
2004 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2005 goto err;
2006 if (stv090x_srate_srch_coarse(state) != 0) {
2007 srate_coarse = stv090x_srate_srch_fine(state);
2008 if (srate_coarse != 0) {
2009 stv090x_get_lock_tmg(state);
a4978a83
AR		 2010 lock = stv090x_get_dmdlock(state,
2011 state->DemodTimeout);
e415c689
MA		 2012 } else {
2013 lock = 0;
2014 }
2015 } else {
2016 cpt_fail = 0;
2017 agc2_ovflw = 0;
2018 for (i = 0; i < 10; i++) {
b4a4248d
AR		 2019 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2020 STV090x_READ_DEMOD(state, AGC2I0);
e415c689
MA		 2021 if (agc2 >= 0xff00)
2022 agc2_ovflw++;
2023 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2024 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2025 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2026
2027 cpt_fail++;
2028 }
2029 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2030 coarse_fail = 1;
2031
2032 lock = 0;
2033 }
7b035da9 2034 k_ref -= 20;
e415c689
MA		 2035 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2036 }
2037
2038 return lock;
2039
2040err:
2041 dprintk(FE_ERROR, 1, "I/O error");
2042 return -1;
2043}
2044
2045static int stv090x_chk_tmg(struct stv090x_state *state)
2046{
2047 u32 reg;
27d40321 2048 s32 tmg_cpt = 0, i;
e415c689 2049 u8 freq, tmg_thh, tmg_thl;
08c45cd5 2050 int tmg_lock = 0;
e415c689
MA		 2051
2052 freq = STV090x_READ_DEMOD(state, CARFREQ);
2053 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2054 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2055 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2056 goto err;
2057 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2058 goto err;
2059
2060 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2061 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2062 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2063 goto err;
2064 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2065 goto err;
2066
2067 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2068 goto err;
2069 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2070 goto err;
2071
2072 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2073 goto err;
2074 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2075 goto err;
2076 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2077 goto err;
2078
2079 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2080 goto err;
2081 msleep(10);
2082
2083 for (i = 0; i < 10; i++) {
2084 reg = STV090x_READ_DEMOD(state, DSTATUS);
2085 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2086 tmg_cpt++;
2087 msleep(1);
2088 }
2089 if (tmg_cpt >= 3)
2090 tmg_lock = 1;
2091
2092 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2093 goto err;
2094 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2095 goto err;
2096 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2097 goto err;
2098
2099 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2100 goto err;
2101 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2102 goto err;
2103 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2104 goto err;
2105
2106 return tmg_lock;
2107
2108err:
2109 dprintk(FE_ERROR, 1, "I/O error");
2110 return -1;
2111}
2112
2113static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2114{
2115 struct dvb_frontend *fe = &state->frontend;
2116
2117 u32 reg;
2118 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2119 int lock = 0;
2120
2121 if (state->srate >= 10000000)
2122 timeout_lock = timeout_dmd / 3;
2123 else
2124 timeout_lock = timeout_dmd / 2;
2125
2126 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2127 if (!lock) {
2128 if (state->srate >= 10000000) {
2129 if (stv090x_chk_tmg(state)) {
2130 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2131 goto err;
2132 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2133 goto err;
2134 lock = stv090x_get_dmdlock(state, timeout_dmd);
2135 } else {
2136 lock = 0;
2137 }
2138 } else {
2139 if (state->srate <= 4000000)
2140 car_step = 1000;
2141 else if (state->srate <= 7000000)
2142 car_step = 2000;
2143 else if (state->srate <= 10000000)
2144 car_step = 3000;
2145 else
2146 car_step = 5000;
2147
2148 steps = (state->search_range / 1000) / car_step;
2149 steps /= 2;
2150 steps = 2 * (steps + 1);
2151 if (steps < 0)
2152 steps = 2;
2153 else if (steps > 12)
2154 steps = 12;
2155
2156 cur_step = 1;
2157 dir = 1;
2158
2159 if (!lock) {
2160 freq = state->frequency;
2161 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2162 while ((cur_step <= steps) && (!lock)) {
2163 if (dir > 0)
2164 freq += cur_step * car_step;
2165 else
2166 freq -= cur_step * car_step;
2167
2168 /* Setup tuner */
19c4ee58 2169 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 2170 goto err;
e415c689 2171
27d40321 2172 if (state->config->tuner_set_frequency) {
a4978a83 2173 if (state->config->tuner_set_frequency(fe, freq) < 0)
2c1f750b 2174 goto err_gateoff;
27d40321 2175 }
e415c689 2176
27d40321
MA		 2177 if (state->config->tuner_set_bandwidth) {
2178 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 2179 goto err_gateoff;
27d40321 2180 }
e415c689 2181
19c4ee58 2182 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 2183 goto err;
e415c689
MA		 2184
2185 msleep(50);
2186
19c4ee58 2187 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 2188 goto err;
e415c689 2189
27d40321
MA		 2190 if (state->config->tuner_get_status) {
2191 if (state->config->tuner_get_status(fe, &reg) < 0)
2c1f750b 2192 goto err_gateoff;
27d40321 2193 }
e415c689
MA		 2194
2195 if (reg)
2196 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2197 else
2198 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2199
19c4ee58 2200 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 2201 goto err;
e415c689
MA		 2202
2203 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
e415c689
MA		 2204 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2205 goto err;
2206 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2207 goto err;
2208 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2209 goto err;
2210 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2211 goto err;
2212 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2213
2214 dir *= -1;
2215 cur_step++;
2216 }
2217 }
2218 }
2219 }
2220
2221 return lock;
2222
2c1f750b 2223err_gateoff:
19c4ee58 2224 stv090x_i2c_gate_ctrl(state, 0);
e415c689
MA		 2225err:
2226 dprintk(FE_ERROR, 1, "I/O error");
2227 return -1;
2228}
2229
2230static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2231{
2232 s32 timeout, inc, steps_max, srate, car_max;
2233
2234 srate = state->srate;
2235 car_max = state->search_range / 1000;
2f5914be 2236 car_max += car_max / 10;
e415c689 2237 car_max = 65536 * (car_max / 2);
97f7a2ae 2238 car_max /= (state->internal->mclk / 1000);
e415c689
MA		 2239
2240 if (car_max > 0x4000)
2241 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2242
2243 inc = srate;
97f7a2ae 2244 inc /= state->internal->mclk / 1000;
e415c689
MA		 2245 inc *= 256;
2246 inc *= 256;
2247 inc /= 1000;
2248
72982f76 2249 switch (state->search_mode) {
e415c689
MA		 2250 case STV090x_SEARCH_DVBS1:
2251 case STV090x_SEARCH_DSS:
2252 inc *= 3; /* freq step = 3% of srate */
2253 timeout = 20;
2254 break;
2255
2256 case STV090x_SEARCH_DVBS2:
2257 inc *= 4;
2258 timeout = 25;
2259 break;
2260
2261 case STV090x_SEARCH_AUTO:
2262 default:
2263 inc *= 3;
2264 timeout = 25;
2265 break;
2266 }
2267 inc /= 100;
2268 if ((inc > car_max) || (inc < 0))
2269 inc = car_max / 2; /* increment <= 1/8 Mclk */
2270
2271 timeout *= 27500; /* 27.5 Msps reference */
2272 if (srate > 0)
2273 timeout /= (srate / 1000);
2274
2275 if ((timeout > 100) || (timeout < 0))
2276 timeout = 100;
2277
2278 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2279 if ((steps_max > 100) || (steps_max < 0)) {
2280 steps_max = 100; /* max steps <= 100 */
2281 inc = car_max / steps_max;
2282 }
2283 *freq_inc = inc;
2284 *timeout_sw = timeout;
2285 *steps = steps_max;
2286
2287 return 0;
2288}
2289
2290static int stv090x_chk_signal(struct stv090x_state *state)
2291{
2292 s32 offst_car, agc2, car_max;
2293 int no_signal;
2294
2295 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2296 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2f5914be 2297 offst_car = comp2(offst_car, 16);
e415c689
MA		 2298
2299 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2300 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2301 car_max = state->search_range / 1000;
2302
2303 car_max += (car_max / 10); /* 10% margin */
2304 car_max = (65536 * car_max / 2);
97f7a2ae 2305 car_max /= state->internal->mclk / 1000;
e415c689
MA		 2306
2307 if (car_max > 0x4000)
2308 car_max = 0x4000;
2309
2310 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2311 no_signal = 1;
2312 dprintk(FE_DEBUG, 1, "No Signal");
2313 } else {
2314 no_signal = 0;
2315 dprintk(FE_DEBUG, 1, "Found Signal");
2316 }
2317
2318 return no_signal;
2319}
2320
2321static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2322{
2323 int no_signal, lock = 0;
27d40321 2324 s32 cpt_step = 0, offst_freq, car_max;
e415c689
MA		 2325 u32 reg;
2326
2327 car_max = state->search_range / 1000;
2328 car_max += (car_max / 10);
2329 car_max = (65536 * car_max / 2);
97f7a2ae 2330 car_max /= (state->internal->mclk / 1000);
e415c689
MA		 2331 if (car_max > 0x4000)
2332 car_max = 0x4000;
2333
2334 if (zigzag)
2335 offst_freq = 0;
2336 else
2337 offst_freq = -car_max + inc;
2338
e415c689
MA		 2339 do {
2340 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2341 goto err;
2342 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2343 goto err;
2344 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2345 goto err;
2346 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2347 goto err;
2348
2349 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2350 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2351 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2352 goto err;
2353
e415c689
MA		 2354 if (zigzag) {
2355 if (offst_freq >= 0)
2356 offst_freq = -offst_freq - 2 * inc;
2357 else
2358 offst_freq = -offst_freq;
2359 } else {
2360 offst_freq += 2 * inc;
2361 }
2362
2f5914be
AR		 2363 cpt_step++;
2364
e415c689
MA		 2365 lock = stv090x_get_dmdlock(state, timeout);
2366 no_signal = stv090x_chk_signal(state);
2367
2368 } while ((!lock) &&
2369 (!no_signal) &&
2370 ((offst_freq - inc) < car_max) &&
2371 ((offst_freq + inc) > -car_max) &&
2372 (cpt_step < steps_max));
2373
2374 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2375 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2376 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2377 goto err;
2378
2379 return lock;
2380err:
2381 dprintk(FE_ERROR, 1, "I/O error");
2382 return -1;
2383}
2384
2385static int stv090x_sw_algo(struct stv090x_state *state)
2386{
2387 int no_signal, zigzag, lock = 0;
2388 u32 reg;
2389
2390 s32 dvbs2_fly_wheel;
2391 s32 inc, timeout_step, trials, steps_max;
2392
27d40321
MA		 2393 /* get params */
2394 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
e415c689 2395
72982f76 2396 switch (state->search_mode) {
e415c689
MA		 2397 case STV090x_SEARCH_DVBS1:
2398 case STV090x_SEARCH_DSS:
2399 /* accelerate the frequency detector */
97f7a2ae 2400 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2401 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2402 goto err;
e415c689 2403 }
27d40321 2404
e415c689
MA		 2405 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2406 goto err;
2407 zigzag = 0;
2408 break;
2409
2410 case STV090x_SEARCH_DVBS2:
97f7a2ae 2411 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2412 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2413 goto err;
e415c689 2414 }
27d40321 2415
e415c689
MA		 2416 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2417 goto err;
2418 zigzag = 1;
2419 break;
2420
2421 case STV090x_SEARCH_AUTO:
2422 default:
2423 /* accelerate the frequency detector */
97f7a2ae 2424 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2425 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2426 goto err;
2427 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2428 goto err;
e415c689 2429 }
27d40321 2430
2f5914be 2431 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
e415c689
MA		 2432 goto err;
2433 zigzag = 0;
2434 break;
2435 }
2436
2437 trials = 0;
2438 do {
2439 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2440 no_signal = stv090x_chk_signal(state);
2441 trials++;
2442
2443 /*run the SW search 2 times maximum*/
2444 if (lock || no_signal || (trials == 2)) {
2445 /*Check if the demod is not losing lock in DVBS2*/
97f7a2ae 2446 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2447 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2448 goto err;
2449 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2450 goto err;
e415c689
MA		 2451 }
2452
2453 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2454 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2455 /*Check if the demod is not losing lock in DVBS2*/
2456 msleep(timeout_step);
2457 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2458 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2459 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2460 msleep(timeout_step);
2461 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2462 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2463 }
2464 if (dvbs2_fly_wheel < 0xd) {
2465 /*FALSE lock, The demod is loosing lock */
2466 lock = 0;
2467 if (trials < 2) {
97f7a2ae 2468 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2469 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2470 goto err;
e415c689 2471 }
27d40321 2472
e415c689
MA		 2473 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2474 goto err;
2475 }
2476 }
2477 }
2478 }
2479 } while ((!lock) && (trials < 2) && (!no_signal));
2480
2481 return lock;
2482err:
2483 dprintk(FE_ERROR, 1, "I/O error");
2484 return -1;
2485}
2486
2487static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2488{
2489 u32 reg;
2490 enum stv090x_delsys delsys;
2491
2492 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2493 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2494 delsys = STV090x_DVBS2;
2495 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2496 reg = STV090x_READ_DEMOD(state, FECM);
2497 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2498 delsys = STV090x_DSS;
2499 else
2500 delsys = STV090x_DVBS1;
2501 } else {
2502 delsys = STV090x_ERROR;
2503 }
2504
2505 return delsys;
2506}
2507
2508/* in Hz */
2509static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2510{
2511 s32 derot, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 2512
2513 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2514 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2515 derot |= STV090x_READ_DEMOD(state, CFR0);
2516
2517 derot = comp2(derot, 24);
97f7a2ae 2518 int_1 = mclk >> 12;
da4b9059 2519 int_2 = derot >> 12;
e415c689 2520
da4b9059 2521 /* carrier_frequency = MasterClock * Reg / 2^24 */
97f7a2ae 2522 tmp_1 = mclk % 0x1000;
da4b9059 2523 tmp_2 = derot % 0x1000;
e415c689
MA		 2524
2525 derot = (int_1 * int_2) +
da4b9059 2526 ((int_1 * tmp_2) >> 12) +
b671a8d4 2527 ((int_2 * tmp_1) >> 12);
e415c689
MA		 2528
2529 return derot;
2530}
2531
2532static int stv090x_get_viterbi(struct stv090x_state *state)
2533{
2534 u32 reg, rate;
2535
2536 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2537 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2538
2539 switch (rate) {
2540 case 13:
2541 state->fec = STV090x_PR12;
2542 break;
2543
2544 case 18:
2545 state->fec = STV090x_PR23;
2546 break;
2547
2548 case 21:
2549 state->fec = STV090x_PR34;
2550 break;
2551
2552 case 24:
2553 state->fec = STV090x_PR56;
2554 break;
2555
2556 case 25:
2557 state->fec = STV090x_PR67;
2558 break;
2559
2560 case 26:
2561 state->fec = STV090x_PR78;
2562 break;
2563
2564 default:
2565 state->fec = STV090x_PRERR;
2566 break;
2567 }
2568
2569 return 0;
2570}
2571
2572static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2573{
2574 struct dvb_frontend *fe = &state->frontend;
2575
2576 u8 tmg;
2577 u32 reg;
2578 s32 i = 0, offst_freq;
2579
2580 msleep(5);
2581
2582 if (state->algo == STV090x_BLIND_SEARCH) {
2583 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2584 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2f5914be 2585 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
e415c689
MA		 2586 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2587 msleep(5);
2588 i += 5;
2589 }
2590 }
2591 state->delsys = stv090x_get_std(state);
2592
19c4ee58 2593 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 2594 goto err;
e415c689 2595
27d40321
MA		 2596 if (state->config->tuner_get_frequency) {
2597 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2c1f750b 2598 goto err_gateoff;
27d40321 2599 }
e415c689 2600
19c4ee58 2601 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 2602 goto err;
e415c689 2603
97f7a2ae 2604 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
e415c689 2605 state->frequency += offst_freq;
27d40321
MA		 2606
2607 if (stv090x_get_viterbi(state) < 0)
2608 goto err;
2609
e415c689
MA		 2610 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2611 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2612 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2613 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2614 reg = STV090x_READ_DEMOD(state, TMGOBS);
2615 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2616 reg = STV090x_READ_DEMOD(state, FECM);
2617 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2618
2619 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2620
19c4ee58 2621 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 2622 goto err;
e415c689 2623
27d40321
MA		 2624 if (state->config->tuner_get_frequency) {
2625 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2c1f750b 2626 goto err_gateoff;
27d40321 2627 }
e415c689 2628
19c4ee58 2629 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 2630 goto err;
e415c689
MA		 2631
2632 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2f5914be 2633 return STV090x_RANGEOK;
e415c689
MA		 2634 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2635 return STV090x_RANGEOK;
2636 else
2637 return STV090x_OUTOFRANGE; /* Out of Range */
2638 } else {
2639 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2640 return STV090x_RANGEOK;
2641 else
2642 return STV090x_OUTOFRANGE;
2643 }
2644
2645 return STV090x_OUTOFRANGE;
2c1f750b
OE		 2646
2647err_gateoff:
19c4ee58 2648 stv090x_i2c_gate_ctrl(state, 0);
27d40321
MA		 2649err:
2650 dprintk(FE_ERROR, 1, "I/O error");
2651 return -1;
e415c689
MA		 2652}
2653
2654static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2655{
2656 s32 offst_tmg;
e415c689
MA		 2657
2658 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2659 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2660 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2661
e415c689
MA		 2662 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2663 if (!offst_tmg)
2664 offst_tmg = 1;
2665
5f99feff 2666 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
e415c689
MA		 2667 offst_tmg /= 320;
2668
2669 return offst_tmg;
2670}
2671
2672static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2673{
2674 u8 aclc = 0x29;
2675 s32 i;
27d40321 2676 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
e415c689 2677
97f7a2ae 2678 if (state->internal->dev_ver == 0x20) {
27d40321
MA		 2679 car_loop = stv090x_s2_crl_cut20;
2680 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2681 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2682 } else {
2683 /* >= Cut 3 */
2684 car_loop = stv090x_s2_crl_cut30;
2685 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2686 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2687 }
e415c689
MA		 2688
2689 if (modcod < STV090x_QPSK_12) {
2690 i = 0;
27d40321 2691 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
e415c689
MA		 2692 i++;
2693
2694 if (i >= 3)
2695 i = 2;
2696
2697 } else {
2698 i = 0;
2699 while ((i < 14) && (modcod != car_loop[i].modcod))
2700 i++;
2701
2702 if (i >= 14) {
2703 i = 0;
27d40321 2704 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
e415c689
MA		 2705 i++;
2706
2707 if (i >= 11)
2708 i = 10;
2709 }
2710 }
2711
2712 if (modcod <= STV090x_QPSK_25) {
2713 if (pilots) {
2714 if (state->srate <= 3000000)
27d40321 2715 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
e415c689 2716 else if (state->srate <= 7000000)
27d40321 2717 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
e415c689 2718 else if (state->srate <= 15000000)
27d40321 2719 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
e415c689 2720 else if (state->srate <= 25000000)
27d40321 2721 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
e415c689 2722 else
27d40321 2723 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
e415c689
MA		 2724 } else {
2725 if (state->srate <= 3000000)
27d40321 2726 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
e415c689 2727 else if (state->srate <= 7000000)
27d40321 2728 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
e415c689 2729 else if (state->srate <= 15000000)
27d40321 2730 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
e415c689 2731 else if (state->srate <= 25000000)
27d40321 2732 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
e415c689 2733 else
27d40321 2734 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
e415c689
MA		 2735 }
2736
2737 } else if (modcod <= STV090x_8PSK_910) {
2738 if (pilots) {
2739 if (state->srate <= 3000000)
2740 aclc = car_loop[i].crl_pilots_on_2;
2741 else if (state->srate <= 7000000)
2742 aclc = car_loop[i].crl_pilots_on_5;
2743 else if (state->srate <= 15000000)
2744 aclc = car_loop[i].crl_pilots_on_10;
2745 else if (state->srate <= 25000000)
2746 aclc = car_loop[i].crl_pilots_on_20;
2747 else
2748 aclc = car_loop[i].crl_pilots_on_30;
2749 } else {
2750 if (state->srate <= 3000000)
2751 aclc = car_loop[i].crl_pilots_off_2;
2752 else if (state->srate <= 7000000)
2753 aclc = car_loop[i].crl_pilots_off_5;
2754 else if (state->srate <= 15000000)
2755 aclc = car_loop[i].crl_pilots_off_10;
2756 else if (state->srate <= 25000000)
2757 aclc = car_loop[i].crl_pilots_off_20;
2758 else
2759 aclc = car_loop[i].crl_pilots_off_30;
2760 }
2761 } else { /* 16APSK and 32APSK */
2762 if (state->srate <= 3000000)
27d40321 2763 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
e415c689 2764 else if (state->srate <= 7000000)
27d40321 2765 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
e415c689 2766 else if (state->srate <= 15000000)
27d40321 2767 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
e415c689 2768 else if (state->srate <= 25000000)
27d40321 2769 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
e415c689 2770 else
27d40321 2771 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
e415c689
MA		 2772 }
2773
2774 return aclc;
2775}
2776
2777static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2778{
0a5ded56 2779 struct stv090x_short_frame_crloop *short_crl = NULL;
e415c689
MA		 2780 s32 index = 0;
2781 u8 aclc = 0x0b;
2782
2783 switch (state->modulation) {
2784 case STV090x_QPSK:
2785 default:
2786 index = 0;
2787 break;
2788 case STV090x_8PSK:
2789 index = 1;
2790 break;
2791 case STV090x_16APSK:
2792 index = 2;
2793 break;
2794 case STV090x_32APSK:
2795 index = 3;
2796 break;
2797 }
2798
97f7a2ae 2799 if (state->internal->dev_ver >= 0x30) {
eebf8d86 2800 /* Cut 3.0 and up */
27d40321 2801 short_crl = stv090x_s2_short_crl_cut30;
eebf8d86
MA		 2802 } else {
2803 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2804 short_crl = stv090x_s2_short_crl_cut20;
2805 }
27d40321
MA		 2806
2807 if (state->srate <= 3000000)
2808 aclc = short_crl[index].crl_2;
2809 else if (state->srate <= 7000000)
2810 aclc = short_crl[index].crl_5;
2811 else if (state->srate <= 15000000)
2812 aclc = short_crl[index].crl_10;
2813 else if (state->srate <= 25000000)
2814 aclc = short_crl[index].crl_20;
2815 else
2816 aclc = short_crl[index].crl_30;
e415c689
MA		 2817
2818 return aclc;
2819}
2820
2821static int stv090x_optimize_track(struct stv090x_state *state)
2822{
2823 struct dvb_frontend *fe = &state->frontend;
2824
2825 enum stv090x_rolloff rolloff;
2826 enum stv090x_modcod modcod;
2827
2828 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2829 u32 reg;
2830
97f7a2ae 2831 srate = stv090x_get_srate(state, state->internal->mclk);
e415c689
MA		 2832 srate += stv090x_get_tmgoffst(state, srate);
2833
2834 switch (state->delsys) {
2835 case STV090x_DVBS1:
2836 case STV090x_DSS:
b671a8d4 2837 if (state->search_mode == STV090x_SEARCH_AUTO) {
e415c689
MA		 2838 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2839 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2840 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2841 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2842 goto err;
2843 }
2844 reg = STV090x_READ_DEMOD(state, DEMOD);
2845 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
27d40321 2846 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
e415c689
MA		 2847 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2848 goto err;
27d40321 2849
97f7a2ae 2850 if (state->internal->dev_ver >= 0x30) {
27d40321
MA		 2851 if (stv090x_get_viterbi(state) < 0)
2852 goto err;
2853
2854 if (state->fec == STV090x_PR12) {
2855 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2856 goto err;
2857 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2858 goto err;
2859 } else {
2860 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2861 goto err;
2862 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2863 goto err;
2864 }
2865 }
2866
e415c689
MA		 2867 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2868 goto err;
2869 break;
2870
2871 case STV090x_DVBS2:
2872 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2f5914be
AR		 2873 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2874 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
e415c689
MA		 2875 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2876 goto err;
2877 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2878 goto err;
2879 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2880 goto err;
2881 if (state->frame_len == STV090x_LONG_FRAME) {
2882 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2883 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2884 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2885 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2886 if (modcod <= STV090x_QPSK_910) {
2887 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2888 } else if (modcod <= STV090x_8PSK_910) {
2889 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2890 goto err;
2891 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2892 goto err;
2893 }
2894 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2895 if (modcod <= STV090x_16APSK_910) {
2896 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2897 goto err;
2898 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2899 goto err;
2900 } else {
2901 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2902 goto err;
2903 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2904 goto err;
2905 }
2906 }
2907 } else {
2908 /*Carrier loop setting for short frame*/
2909 aclc = stv090x_optimize_carloop_short(state);
2910 if (state->modulation == STV090x_QPSK) {
2911 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2912 goto err;
2913 } else if (state->modulation == STV090x_8PSK) {
2914 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2915 goto err;
2916 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2917 goto err;
2918 } else if (state->modulation == STV090x_16APSK) {
2919 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2920 goto err;
2921 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2922 goto err;
2923 } else if (state->modulation == STV090x_32APSK) {
2924 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2925 goto err;
2926 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2927 goto err;
2928 }
2929 }
27d40321 2930
e415c689
MA		 2931 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2932 break;
2933
2934 case STV090x_UNKNOWN:
2935 default:
2936 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2937 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2938 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2939 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2940 goto err;
2941 break;
2942 }
2943
2944 f_1 = STV090x_READ_DEMOD(state, CFR2);
2945 f_0 = STV090x_READ_DEMOD(state, CFR1);
2946 reg = STV090x_READ_DEMOD(state, TMGOBS);
2947 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2948
2949 if (state->algo == STV090x_BLIND_SEARCH) {
2950 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2951 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2952 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2953 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2954 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2955 goto err;
27d40321
MA		 2956 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2957 goto err;
2958
2959 if (stv090x_set_srate(state, srate) < 0)
e415c689 2960 goto err;
e415c689 2961 blind_tune = 1;
7b035da9
AR		 2962
2963 if (stv090x_dvbs_track_crl(state) < 0)
2964 goto err;
e415c689
MA		 2965 }
2966
97f7a2ae 2967 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 2968 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2969 (state->search_mode == STV090x_SEARCH_DSS) ||
2970 (state->search_mode == STV090x_SEARCH_AUTO)) {
2971
2972 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2973 goto err;
2974 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2975 goto err;
2976 }
2977 }
2978
e415c689
MA		 2979 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2980 goto err;
2981
27d40321
MA		 2982 /* AUTO tracking MODE */
2983 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2984 goto err;
2985 /* AUTO tracking MODE */
2986 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
2987 goto err;
e415c689 2988
97f7a2ae
AR		 2989 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
2990 (state->srate < 10000000)) {
27d40321 2991 /* update initial carrier freq with the found freq offset */
e415c689
MA		 2992 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2993 goto err;
2994 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2995 goto err;
2996 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2997
97f7a2ae 2998 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
e415c689
MA		 2999
3000 if (state->algo != STV090x_WARM_SEARCH) {
3001
19c4ee58 3002 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 3003 goto err;
e415c689 3004
27d40321
MA		 3005 if (state->config->tuner_set_bandwidth) {
3006 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 3007 goto err_gateoff;
27d40321 3008 }
e415c689 3009
19c4ee58 3010 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 3011 goto err;
e415c689
MA		 3012
3013 }
3014 }
3015 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3016 msleep(50); /* blind search: wait 50ms for SR stabilization */
3017 else
3018 msleep(5);
3019
3020 stv090x_get_lock_tmg(state);
3021
3022 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3023 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3024 goto err;
3025 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3026 goto err;
3027 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3028 goto err;
3029 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3030 goto err;
3031
3032 i = 0;
3033
3034 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3035
3036 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3037 goto err;
3038 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3039 goto err;
3040 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3041 goto err;
3042 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3043 goto err;
3044 i++;
3045 }
3046 }
3047
3048 }
3049
97f7a2ae 3050 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 3051 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3052 goto err;
3053 }
27d40321 3054
e415c689
MA		 3055 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3056 stv090x_set_vit_thtracq(state);
3057
3058 return 0;
2c1f750b
OE		 3059
3060err_gateoff:
19c4ee58 3061 stv090x_i2c_gate_ctrl(state, 0);
e415c689
MA		 3062err:
3063 dprintk(FE_ERROR, 1, "I/O error");
3064 return -1;
3065}
3066
3067static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3068{
3069 s32 timer = 0, lock = 0, stat;
3070 u32 reg;
3071
3072 while ((timer < timeout) && (!lock)) {
3073 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3074 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3075
3076 switch (stat) {
3077 case 0: /* searching */
3078 case 1: /* first PLH detected */
3079 default:
3080 lock = 0;
3081 break;
3082
3083 case 2: /* DVB-S2 mode */
3084 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3085 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3086 break;
3087
3088 case 3: /* DVB-S1/legacy mode */
3089 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3090 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3091 break;
3092 }
3093 if (!lock) {
3094 msleep(10);
3095 timer += 10;
3096 }
3097 }
3098 return lock;
3099}
3100
3101static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3102{
3103 u32 reg;
3104 s32 timer = 0;
3105 int lock;
3106
3107 lock = stv090x_get_dmdlock(state, timeout_dmd);
3108 if (lock)
3109 lock = stv090x_get_feclock(state, timeout_fec);
3110
3111 if (lock) {
3112 lock = 0;
3113
3114 while ((timer < timeout_fec) && (!lock)) {
3115 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3116 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3117 msleep(1);
3118 timer++;
3119 }
3120 }
3121
3122 return lock;
3123}
3124
3125static int stv090x_set_s2rolloff(struct stv090x_state *state)
3126{
e415c689
MA		 3127 u32 reg;
3128
97f7a2ae 3129 if (state->internal->dev_ver <= 0x20) {
27d40321 3130 /* rolloff to auto mode if DVBS2 */
e415c689 3131 reg = STV090x_READ_DEMOD(state, DEMOD);
27d40321 3132 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
e415c689
MA		 3133 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3134 goto err;
3135 } else {
27d40321 3136 /* DVB-S2 rolloff to auto mode if DVBS2 */
e415c689 3137 reg = STV090x_READ_DEMOD(state, DEMOD);
27d40321 3138 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
e415c689
MA		 3139 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3140 goto err;
3141 }
3142 return 0;
3143err:
3144 dprintk(FE_ERROR, 1, "I/O error");
3145 return -1;
3146}
3147
e415c689
MA		 3148
3149static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3150{
3151 struct dvb_frontend *fe = &state->frontend;
3152 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3153 u32 reg;
a4978a83 3154 s32 agc1_power, power_iq = 0, i;
4e58a682 3155 int lock = 0, low_sr = 0, no_signal = 0;
e415c689
MA		 3156
3157 reg = STV090x_READ_DEMOD(state, TSCFGH);
3158 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3159 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3160 goto err;
3161
3162 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3163 goto err;
3164
97f7a2ae 3165 if (state->internal->dev_ver >= 0x20) {
7b035da9
AR		 3166 if (state->srate > 5000000) {
3167 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3168 goto err;
3169 } else {
3170 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3171 goto err;
3172 }
e415c689
MA		 3173 }
3174
3175 stv090x_get_lock_tmg(state);
3176
3177 if (state->algo == STV090x_BLIND_SEARCH) {
3178 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
27d40321
MA		 3179 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3180 goto err;
3181 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3182 goto err;
3183 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
e415c689 3184 goto err;
e415c689
MA		 3185 } else {
3186 /* known srate */
3187 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3188 goto err;
3189 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3190 goto err;
3191
27d40321
MA		 3192 if (state->srate < 2000000) {
3193 /* SR < 2MSPS */
3194 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
e415c689
MA		 3195 goto err;
3196 } else {
27d40321
MA		 3197 /* SR >= 2Msps */
3198 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
e415c689
MA		 3199 goto err;
3200 }
3201
27d40321
MA		 3202 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3203 goto err;
3204
97f7a2ae 3205 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 3206 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3207 goto err;
3208 if (state->algo == STV090x_COLD_SEARCH)
4e58a682 3209 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
e415c689
MA		 3210 else if (state->algo == STV090x_WARM_SEARCH)
3211 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
e415c689 3212 }
27d40321
MA		 3213
3214 /* if cold start or warm (Symbolrate is known)
3215 * use a Narrow symbol rate scan range
3216 */
3217 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3218 goto err;
3219
3220 if (stv090x_set_srate(state, state->srate) < 0)
3221 goto err;
3222
97f7a2ae
AR		 3223 if (stv090x_set_max_srate(state, state->internal->mclk,
3224 state->srate) < 0)
27d40321 3225 goto err;
97f7a2ae
AR		 3226 if (stv090x_set_min_srate(state, state->internal->mclk,
3227 state->srate) < 0)
e415c689 3228 goto err;
e415c689
MA		 3229
3230 if (state->srate >= 10000000)
4e58a682
AR		 3231 low_sr = 0;
3232 else
e415c689
MA		 3233 low_sr = 1;
3234 }
3235
3236 /* Setup tuner */
19c4ee58 3237 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 3238 goto err;
e415c689 3239
27d40321 3240 if (state->config->tuner_set_bbgain) {
d8b5a8e4
OE		 3241 reg = state->config->tuner_bbgain;
3242 if (reg == 0)
3243 reg = 10; /* default: 10dB */
3244 if (state->config->tuner_set_bbgain(fe, reg) < 0)
2c1f750b 3245 goto err_gateoff;
27d40321 3246 }
e415c689 3247
27d40321
MA		 3248 if (state->config->tuner_set_frequency) {
3249 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
2c1f750b 3250 goto err_gateoff;
27d40321 3251 }
e415c689 3252
27d40321
MA		 3253 if (state->config->tuner_set_bandwidth) {
3254 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2c1f750b 3255 goto err_gateoff;
27d40321 3256 }
e415c689 3257
19c4ee58 3258 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 3259 goto err;
e415c689
MA		 3260
3261 msleep(50);
3262
27d40321 3263 if (state->config->tuner_get_status) {
19c4ee58 3264 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
41894b97 3265 goto err;
27d40321 3266 if (state->config->tuner_get_status(fe, &reg) < 0)
2c1f750b 3267 goto err_gateoff;
19c4ee58 3268 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
41894b97 3269 goto err;
e415c689 3270
41894b97
OE		 3271 if (reg)
3272 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3273 else {
3274 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3275 return STV090x_NOCARRIER;
3276 }
3277 }
e415c689 3278
27d40321
MA		 3279 msleep(10);
3280 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3281 STV090x_READ_DEMOD(state, AGCIQIN0));
3282
3283 if (agc1_power == 0) {
3284 /* If AGC1 integrator value is 0
3285 * then read POWERI, POWERQ
3286 */
3287 for (i = 0; i < 5; i++) {
3288 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3289 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3290 }
3291 power_iq /= 5;
3292 }
3293
3294 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3295 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3296 lock = 0;
c4fa649a 3297 signal_state = STV090x_NOAGC1;
27d40321
MA		 3298 } else {
3299 reg = STV090x_READ_DEMOD(state, DEMOD);
3300 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3301
97f7a2ae 3302 if (state->internal->dev_ver <= 0x20) {
27d40321
MA		 3303 /* rolloff to auto mode if DVBS2 */
3304 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3305 } else {
3306 /* DVB-S2 rolloff to auto mode if DVBS2 */
3307 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3308 }
3309 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
e415c689 3310 goto err;
27d40321
MA		 3311
3312 if (stv090x_delivery_search(state) < 0)
e415c689 3313 goto err;
27d40321
MA		 3314
3315 if (state->algo != STV090x_BLIND_SEARCH) {
3316 if (stv090x_start_search(state) < 0)
3317 goto err;
3318 }
e415c689
MA		 3319 }
3320
c4fa649a
AR		 3321 if (signal_state == STV090x_NOAGC1)
3322 return signal_state;
27d40321 3323
e415c689
MA		 3324 if (state->algo == STV090x_BLIND_SEARCH)
3325 lock = stv090x_blind_search(state);
27d40321 3326
e415c689 3327 else if (state->algo == STV090x_COLD_SEARCH)
a4978a83 3328 lock = stv090x_get_coldlock(state, state->DemodTimeout);
27d40321 3329
e415c689 3330 else if (state->algo == STV090x_WARM_SEARCH)
a4978a83 3331 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
e415c689
MA		 3332
3333 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3334 if (!low_sr) {
3335 if (stv090x_chk_tmg(state))
3336 lock = stv090x_sw_algo(state);
3337 }
3338 }
3339
3340 if (lock)
3341 signal_state = stv090x_get_sig_params(state);
3342
3343 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3344 stv090x_optimize_track(state);
27d40321 3345
97f7a2ae 3346 if (state->internal->dev_ver >= 0x20) {
27d40321
MA		 3347 /* >= Cut 2.0 :release TS reset after
3348 * demod lock and optimized Tracking
3349 */
e415c689
MA		 3350 reg = STV090x_READ_DEMOD(state, TSCFGH);
3351 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3352 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3353 goto err;
27d40321 3354
e415c689 3355 msleep(3);
27d40321 3356
e415c689
MA		 3357 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3358 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3359 goto err;
3360
3361 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3362 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3363 goto err;
3364 }
3365
a4978a83
AR		 3366 lock = stv090x_get_lock(state, state->FecTimeout,
3367 state->FecTimeout);
3368 if (lock) {
e415c689
MA		 3369 if (state->delsys == STV090x_DVBS2) {
3370 stv090x_set_s2rolloff(state);
27d40321
MA		 3371
3372 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3373 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3374 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
e415c689 3375 goto err;
27d40321
MA		 3376 /* Reset DVBS2 packet delinator error counter */
3377 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3378 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3379 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
e415c689 3380 goto err;
27d40321 3381
e415c689
MA		 3382 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3383 goto err;
3384 } else {
3385 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3386 goto err;
3387 }
27d40321 3388 /* Reset the Total packet counter */
e415c689
MA		 3389 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3390 goto err;
27d40321 3391 /* Reset the packet Error counter2 */
e415c689
MA		 3392 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3393 goto err;
3394 } else {
e415c689
MA		 3395 signal_state = STV090x_NODATA;
3396 no_signal = stv090x_chk_signal(state);
3397 }
3398 }
e415c689
MA		 3399 return signal_state;
3400
2c1f750b 3401err_gateoff:
19c4ee58 3402 stv090x_i2c_gate_ctrl(state, 0);
e415c689
MA		 3403err:
3404 dprintk(FE_ERROR, 1, "I/O error");
3405 return -1;
3406}
3407
3408static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3409{
3410 struct stv090x_state *state = fe->demodulator_priv;
3411 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3412
729cbafa
AR		 3413 if (p->frequency == 0)
3414 return DVBFE_ALGO_SEARCH_INVALID;
3415
e415c689
MA		 3416 state->delsys = props->delivery_system;
3417 state->frequency = p->frequency;
3418 state->srate = p->u.qpsk.symbol_rate;
4e58a682
AR		 3419 state->search_mode = STV090x_SEARCH_AUTO;
3420 state->algo = STV090x_COLD_SEARCH;
3421 state->fec = STV090x_PRERR;
c879d8ce
AR		 3422 if (state->srate > 10000000) {
3423 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3424 state->search_range = 10000000;
3425 } else {
3426 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3427 state->search_range = 5000000;
3428 }
e415c689 3429
2f5914be 3430 if (stv090x_algo(state) == STV090x_RANGEOK) {
e415c689
MA		 3431 dprintk(FE_DEBUG, 1, "Search success!");
3432 return DVBFE_ALGO_SEARCH_SUCCESS;
3433 } else {
3434 dprintk(FE_DEBUG, 1, "Search failed!");
3435 return DVBFE_ALGO_SEARCH_FAILED;
3436 }
3437
3438 return DVBFE_ALGO_SEARCH_ERROR;
3439}
3440
e415c689
MA		 3441static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3442{
3443 struct stv090x_state *state = fe->demodulator_priv;
3444 u32 reg;
3445 u8 search_state;
e415c689
MA		 3446
3447 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3448 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3449
3450 switch (search_state) {
3451 case 0: /* searching */
3452 case 1: /* first PLH detected */
3453 default:
3454 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
9629c5b6 3455 *status = 0;
e415c689
MA		 3456 break;
3457
3458 case 2: /* DVB-S2 mode */
3459 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3460 reg = STV090x_READ_DEMOD(state, DSTATUS);
3461 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
1d436171
AR		 3462 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3463 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3464 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3465 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
c369b7c2
AR		 3466 *status = FE_HAS_SIGNAL |
3467 FE_HAS_CARRIER |
1d436171
AR		 3468 FE_HAS_VITERBI |
3469 FE_HAS_SYNC |
3470 FE_HAS_LOCK;
3471 }
e415c689
MA		 3472 }
3473 }
3474 break;
3475
3476 case 3: /* DVB-S1/legacy mode */
3477 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3478 reg = STV090x_READ_DEMOD(state, DSTATUS);
3479 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3480 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3481 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3482 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3483 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
c369b7c2
AR		 3484 *status = FE_HAS_SIGNAL |
3485 FE_HAS_CARRIER |
3486 FE_HAS_VITERBI |
3487 FE_HAS_SYNC |
3488 FE_HAS_LOCK;
e415c689
MA		 3489 }
3490 }
3491 }
3492 break;
3493 }
3494
9629c5b6 3495 return 0;
e415c689
MA		 3496}
3497
3498static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3499{
3500 struct stv090x_state *state = fe->demodulator_priv;
3501
3502 s32 count_4, count_3, count_2, count_1, count_0, count;
3503 u32 reg, h, m, l;
3504 enum fe_status status;
3505
9629c5b6
AR		 3506 stv090x_read_status(fe, &status);
3507 if (!(status & FE_HAS_LOCK)) {
e415c689
MA		 3508 *per = 1 << 23; /* Max PER */
3509 } else {
3510 /* Counter 2 */
3511 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3512 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3513
3514 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3515 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3516
3517 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3518 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3519
3520 *per = ((h << 16) | (m << 8) | l);
3521
3522 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3523 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3524 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3525 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3526 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3527
3528 if ((!count_4) && (!count_3)) {
3529 count = (count_2 & 0xff) << 16;
3530 count |= (count_1 & 0xff) << 8;
3531 count |= count_0 & 0xff;
3532 } else {
3533 count = 1 << 24;
3534 }
3535 if (count == 0)
3536 *per = 1;
3537 }
3538 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3539 goto err;
3540 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3541 goto err;
3542
3543 return 0;
3544err:
3545 dprintk(FE_ERROR, 1, "I/O error");
3546 return -1;
3547}
3548
3549static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3550{
3551 int res = 0;
3552 int min = 0, med;
3553
dbeb7dbf
AR		 3554 if ((val >= tab[min].read && val < tab[max].read) ||
3555 (val >= tab[max].read && val < tab[min].read)) {
e415c689
MA		 3556 while ((max - min) > 1) {
3557 med = (max + min) / 2;
dbeb7dbf
AR		 3558 if ((val >= tab[min].read && val < tab[med].read) ||
3559 (val >= tab[med].read && val < tab[min].read))
e415c689
MA		 3560 max = med;
3561 else
3562 min = med;
3563 }
3564 res = ((val - tab[min].read) *
3565 (tab[max].real - tab[min].real) /
3566 (tab[max].read - tab[min].read)) +
3567 tab[min].real;
dbeb7dbf
AR		 3568 } else {
3569 if (tab[min].read < tab[max].read) {
3570 if (val < tab[min].read)
3571 res = tab[min].real;
3572 else if (val >= tab[max].read)
3573 res = tab[max].real;
3574 } else {
3575 if (val >= tab[min].read)
3576 res = tab[min].real;
3577 else if (val < tab[max].read)
3578 res = tab[max].real;
3579 }
e415c689
MA		 3580 }
3581
3582 return res;
3583}
3584
3585static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3586{
3587 struct stv090x_state *state = fe->demodulator_priv;
3588 u32 reg;
dbeb7dbf
AR		 3589 s32 agc_0, agc_1, agc;
3590 s32 str;
e415c689
MA		 3591
3592 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
dbeb7dbf
AR		 3593 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3594 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3595 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3596 agc = MAKEWORD16(agc_1, agc_0);
e415c689 3597
dbeb7dbf
AR		 3598 str = stv090x_table_lookup(stv090x_rf_tab,
3599 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
e415c689 3600 if (agc > stv090x_rf_tab[0].read)
dbeb7dbf 3601 str = 0;
e415c689 3602 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
dbeb7dbf
AR		 3603 str = -100;
3604 *strength = (str + 100) * 0xFFFF / 100;
e415c689
MA		 3605
3606 return 0;
3607}
3608
3609static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3610{
3611 struct stv090x_state *state = fe->demodulator_priv;
3612 u32 reg_0, reg_1, reg, i;
3613 s32 val_0, val_1, val = 0;
3614 u8 lock_f;
dbeb7dbf
AR		 3615 s32 div;
3616 u32 last;
e415c689
MA		 3617
3618 switch (state->delsys) {
3619 case STV090x_DVBS2:
3620 reg = STV090x_READ_DEMOD(state, DSTATUS);
3621 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3622 if (lock_f) {
3623 msleep(5);
3624 for (i = 0; i < 16; i++) {
3625 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3626 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3627 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
dbeb7dbf 3628 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
e415c689
MA		 3629 val += MAKEWORD16(val_1, val_0);
3630 msleep(1);
3631 }
3632 val /= 16;
dbeb7dbf
AR		 3633 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3634 div = stv090x_s2cn_tab[0].read -
3635 stv090x_s2cn_tab[last].read;
3636 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
e415c689
MA		 3637 }
3638 break;
3639
3640 case STV090x_DVBS1:
3641 case STV090x_DSS:
3642 reg = STV090x_READ_DEMOD(state, DSTATUS);
3643 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3644 if (lock_f) {
3645 msleep(5);
3646 for (i = 0; i < 16; i++) {
3647 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3648 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3649 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
dbeb7dbf 3650 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
e415c689
MA		 3651 val += MAKEWORD16(val_1, val_0);
3652 msleep(1);
3653 }
3654 val /= 16;
dbeb7dbf
AR		 3655 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3656 div = stv090x_s1cn_tab[0].read -
3657 stv090x_s1cn_tab[last].read;
3658 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
e415c689
MA		 3659 }
3660 break;
3661 default:
3662 break;
3663 }
3664
3665 return 0;
3666}
3667
3668static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3669{
3670 struct stv090x_state *state = fe->demodulator_priv;
3671 u32 reg;
3672
3673 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3674 switch (tone) {
3675 case SEC_TONE_ON:
3676 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3677 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3678 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3679 goto err;
3680 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3681 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3682 goto err;
3683 break;
3684
3685 case SEC_TONE_OFF:
3686 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3687 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3688 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3689 goto err;
3690 break;
3691 default:
3692 return -EINVAL;
3693 }
3694
3695 return 0;
3696err:
3697 dprintk(FE_ERROR, 1, "I/O error");
3698 return -1;
3699}
3700
3701
3702static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3703{
3704 return DVBFE_ALGO_CUSTOM;
3705}
3706
3707static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3708{
3709 struct stv090x_state *state = fe->demodulator_priv;
3710 u32 reg, idle = 0, fifo_full = 1;
3711 int i;
3712
3713 reg = STV090x_READ_DEMOD(state, DISTXCTL);
f9ed95d0 3714
30e8ca2c
OE		 3715 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3716 (state->config->diseqc_envelope_mode) ? 4 : 2);
f9ed95d0
AR		 3717 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3718 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3719 goto err;
3720 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3721 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3722 goto err;
3723
e415c689
MA		 3724 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3725 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3726 goto err;
3727
3728 for (i = 0; i < cmd->msg_len; i++) {
3729
3730 while (fifo_full) {
3731 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3732 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3733 }
3734
3735 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3736 goto err;
f9ed95d0
AR		 3737 }
3738 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3739 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3740 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3741 goto err;
3742
3743 i = 0;
3744
3745 while ((!idle) && (i < 10)) {
3746 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3747 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3748 msleep(10);
e415c689
MA		 3749 i++;
3750 }
f9ed95d0
AR		 3751
3752 return 0;
3753err:
3754 dprintk(FE_ERROR, 1, "I/O error");
3755 return -1;
3756}
3757
3758static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3759{
3760 struct stv090x_state *state = fe->demodulator_priv;
3761 u32 reg, idle = 0, fifo_full = 1;
3762 u8 mode, value;
3763 int i;
3764
3765 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3766
3767 if (burst == SEC_MINI_A) {
30e8ca2c 3768 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
f9ed95d0
AR		 3769 value = 0x00;
3770 } else {
30e8ca2c 3771 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
f9ed95d0
AR		 3772 value = 0xFF;
3773 }
3774
3775 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3776 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3777 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3778 goto err;
3779 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3780 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3781 goto err;
3782
3783 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3784 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3785 goto err;
3786
3787 while (fifo_full) {
3788 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3789 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3790 }
3791
3792 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3793 goto err;
3794
e415c689
MA		 3795 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3796 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3797 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3798 goto err;
3799
3800 i = 0;
3801
3802 while ((!idle) && (i < 10)) {
3803 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3804 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3805 msleep(10);
3806 i++;
3807 }
3808
3809 return 0;
3810err:
3811 dprintk(FE_ERROR, 1, "I/O error");
3812 return -1;
3813}
3814
3815static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3816{
3817 struct stv090x_state *state = fe->demodulator_priv;
3818 u32 reg = 0, i = 0, rx_end = 0;
3819
3820 while ((rx_end != 1) && (i < 10)) {
3821 msleep(10);
3822 i++;
3823 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3824 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3825 }
3826
3827 if (rx_end) {
3828 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3829 for (i = 0; i < reply->msg_len; i++)
3830 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3831 }
3832
3833 return 0;
3834}
3835
3836static int stv090x_sleep(struct dvb_frontend *fe)
3837{
3838 struct stv090x_state *state = fe->demodulator_priv;
3839 u32 reg;
3840
85532d14
MA		 3841 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3842 goto err;
3843
3844 if (state->config->tuner_sleep) {
c5b74b0f
MA		 3845 if (state->config->tuner_sleep(fe) < 0)
3846 goto err_gateoff;
3847 }
3848
85532d14
MA		 3849 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3850 goto err;
3851
e415c689
MA		 3852 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3853 state->device == STV0900 ? "STV0900" : "STV0903");
3854
3855 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3856 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3857 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3858 goto err;
3859
26b03bc6
MA		 3860 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3861 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3862 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3863 goto err;
3864
e415c689 3865 return 0;
c5b74b0f
MA		 3866
3867err_gateoff:
3868 stv090x_i2c_gate_ctrl(state, 0);
e415c689
MA		 3869err:
3870 dprintk(FE_ERROR, 1, "I/O error");
3871 return -1;
3872}
3873
3874static int stv090x_wakeup(struct dvb_frontend *fe)
3875{
3876 struct stv090x_state *state = fe->demodulator_priv;
3877 u32 reg;
3878
3879 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3880 state->device == STV0900 ? "STV0900" : "STV0903");
3881
3882 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3883 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3884 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3885 goto err;
3886
26b03bc6
MA		 3887 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3888 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3889 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3890 goto err;
3891
e415c689
MA		 3892 return 0;
3893err:
3894 dprintk(FE_ERROR, 1, "I/O error");
3895 return -1;
3896}
3897
3898static void stv090x_release(struct dvb_frontend *fe)
3899{
3900 struct stv090x_state *state = fe->demodulator_priv;
3901
97f7a2ae
AR		 3902 state->internal->num_used--;
3903 if (state->internal->num_used <= 0) {
3904
3905 dprintk(FE_ERROR, 1, "Actually removing");
3906
3907 remove_dev(state->internal);
3908 kfree(state->internal);
3909 }
3910
e415c689
MA		 3911 kfree(state);
3912}
3913
3914static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3915{
27d40321 3916 u32 reg = 0;
e415c689 3917
a4978a83
AR		 3918 reg = stv090x_read_reg(state, STV090x_GENCFG);
3919
e415c689
MA		 3920 switch (ldpc_mode) {
3921 case STV090x_DUAL:
3922 default:
e415c689 3923 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
27d40321
MA		 3924 /* set LDPC to dual mode */
3925 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
e415c689 3926 goto err;
27d40321 3927
e415c689 3928 state->demod_mode = STV090x_DUAL;
27d40321 3929
e415c689
MA		 3930 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3931 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3932 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3933 goto err;
3934 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3935 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3936 goto err;
27d40321
MA		 3937
3938 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
3939 goto err;
3940 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
3941 goto err;
3942 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
3943 goto err;
3944 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
3945 goto err;
3946 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
3947 goto err;
3948 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
3949 goto err;
3950 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
3951 goto err;
3952
3953 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
3954 goto err;
3955 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
3956 goto err;
3957 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
3958 goto err;
3959 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
3960 goto err;
3961 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
3962 goto err;
3963 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
3964 goto err;
3965 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
3966 goto err;
3967
3968 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
3969 goto err;
3970 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
3971 goto err;
e415c689
MA		 3972 }
3973 break;
3974
3975 case STV090x_SINGLE:
27d40321
MA		 3976 if (stv090x_stop_modcod(state) < 0)
3977 goto err;
3978 if (stv090x_activate_modcod_single(state) < 0)
3979 goto err;
3980
e415c689
MA		 3981 if (state->demod == STV090x_DEMODULATOR_1) {
3982 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3983 goto err;
3984 } else {
3985 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3986 goto err;
3987 }
3988
3989 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3990 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3991 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3992 goto err;
3993 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3994 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3995 goto err;
3996
3997 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3998 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3999 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4000 goto err;
4001 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
4002 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4003 goto err;
4004 break;
4005 }
4006
4007 return 0;
4008err:
4009 dprintk(FE_ERROR, 1, "I/O error");
4010 return -1;
4011}
4012
4013/* return (Hz), clk in Hz*/
4014static u32 stv090x_get_mclk(struct stv090x_state *state)
4015{
4016 const struct stv090x_config *config = state->config;
4017 u32 div, reg;
4018 u8 ratio;
4019
4020 div = stv090x_read_reg(state, STV090x_NCOARSE);
4021 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4022 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4023
4024 return (div + 1) * config->xtal / ratio; /* kHz */
4025}
4026
4027static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4028{
4029 const struct stv090x_config *config = state->config;
4030 u32 reg, div, clk_sel;
4031
4032 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4033 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4034
4035 div = ((clk_sel * mclk) / config->xtal) - 1;
4036
4037 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4038 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4039 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4040 goto err;
4041
97f7a2ae 4042 state->internal->mclk = stv090x_get_mclk(state);
e415c689 4043
94a80914 4044 /*Set the DiseqC frequency to 22KHz */
97f7a2ae 4045 div = state->internal->mclk / 704000;
94a80914
MA		 4046 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4047 goto err;
4048 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4049 goto err;
4050
e415c689
MA		 4051 return 0;
4052err:
4053 dprintk(FE_ERROR, 1, "I/O error");
4054 return -1;
4055}
4056
4057static int stv090x_set_tspath(struct stv090x_state *state)
4058{
4059 u32 reg;
4060
97f7a2ae 4061 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 4062 switch (state->config->ts1_mode) {
4063 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4064 case STV090x_TSMODE_DVBCI:
4065 switch (state->config->ts2_mode) {
4066 case STV090x_TSMODE_SERIAL_PUNCTURED:
4067 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4068 default:
4069 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4070 break;
4071
4072 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4073 case STV090x_TSMODE_DVBCI:
4074 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4075 goto err;
4076 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4077 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4078 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4079 goto err;
4080 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4081 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4082 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4083 goto err;
4084 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4085 goto err;
4086 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4087 goto err;
4088 break;
4089 }
4090 break;
4091
4092 case STV090x_TSMODE_SERIAL_PUNCTURED:
4093 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4094 default:
4095 switch (state->config->ts2_mode) {
4096 case STV090x_TSMODE_SERIAL_PUNCTURED:
4097 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4098 default:
4099 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4100 goto err;
4101 break;
4102
4103 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4104 case STV090x_TSMODE_DVBCI:
4105 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4106 goto err;
4107 break;
4108 }
4109 break;
4110 }
4111 } else {
4112 switch (state->config->ts1_mode) {
4113 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4114 case STV090x_TSMODE_DVBCI:
4115 switch (state->config->ts2_mode) {
4116 case STV090x_TSMODE_SERIAL_PUNCTURED:
4117 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4118 default:
56571507 4119 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
e415c689
MA		 4120 break;
4121
4122 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4123 case STV090x_TSMODE_DVBCI:
56571507 4124 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
e415c689
MA		 4125 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4126 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4127 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4128 goto err;
4129 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4130 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4131 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4132 goto err;
4133 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4134 goto err;
4135 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4136 goto err;
4137 break;
4138 }
4139 break;
4140
4141 case STV090x_TSMODE_SERIAL_PUNCTURED:
4142 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4143 default:
4144 switch (state->config->ts2_mode) {
4145 case STV090x_TSMODE_SERIAL_PUNCTURED:
4146 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4147 default:
56571507 4148 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
e415c689
MA		 4149 break;
4150
4151 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4152 case STV090x_TSMODE_DVBCI:
56571507 4153 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
e415c689
MA		 4154 break;
4155 }
4156 break;
4157 }
4158 }
4159
4160 switch (state->config->ts1_mode) {
4161 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4162 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4163 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4164 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4165 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4166 goto err;
4167 break;
4168
4169 case STV090x_TSMODE_DVBCI:
4170 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4171 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4172 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4173 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4174 goto err;
4175 break;
4176
4177 case STV090x_TSMODE_SERIAL_PUNCTURED:
4178 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4179 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4180 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4181 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4182 goto err;
4183 break;
4184
4185 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4186 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4187 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4188 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4189 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4190 goto err;
4191 break;
4192
4193 default:
4194 break;
4195 }
4196
4197 switch (state->config->ts2_mode) {
4198 case STV090x_TSMODE_PARALLEL_PUNCTURED:
64104dc9 4199 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4200 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4201 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
64104dc9 4202 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4203 goto err;
4204 break;
4205
4206 case STV090x_TSMODE_DVBCI:
64104dc9 4207 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4208 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4209 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
64104dc9 4210 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4211 goto err;
4212 break;
4213
4214 case STV090x_TSMODE_SERIAL_PUNCTURED:
64104dc9 4215 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4216 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4217 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
64104dc9 4218 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4219 goto err;
4220 break;
4221
4222 case STV090x_TSMODE_SERIAL_CONTINUOUS:
64104dc9 4223 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
e415c689
MA		 4224 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4225 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
64104dc9 4226 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
e415c689
MA		 4227 goto err;
4228 break;
4229
4230 default:
4231 break;
4232 }
f91e59cb
AR		 4233
4234 if (state->config->ts1_clk > 0) {
4235 u32 speed;
4236
4237 switch (state->config->ts1_mode) {
4238 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4239 case STV090x_TSMODE_DVBCI:
4240 default:
4241 speed = state->internal->mclk /
4242 (state->config->ts1_clk / 4);
4243 if (speed < 0x08)
4244 speed = 0x08;
4245 if (speed > 0xFF)
4246 speed = 0xFF;
4247 break;
4248 case STV090x_TSMODE_SERIAL_PUNCTURED:
4249 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4250 speed = state->internal->mclk /
4251 (state->config->ts1_clk / 32);
4252 if (speed < 0x20)
4253 speed = 0x20;
4254 if (speed > 0xFF)
4255 speed = 0xFF;
4256 break;
4257 }
4258 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4259 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4260 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4261 goto err;
4262 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4263 goto err;
4264 }
4265
4266 if (state->config->ts2_clk > 0) {
4267 u32 speed;
4268
4269 switch (state->config->ts2_mode) {
4270 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4271 case STV090x_TSMODE_DVBCI:
4272 default:
4273 speed = state->internal->mclk /
4274 (state->config->ts2_clk / 4);
4275 if (speed < 0x08)
4276 speed = 0x08;
4277 if (speed > 0xFF)
4278 speed = 0xFF;
4279 break;
4280 case STV090x_TSMODE_SERIAL_PUNCTURED:
4281 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4282 speed = state->internal->mclk /
4283 (state->config->ts2_clk / 32);
4284 if (speed < 0x20)
4285 speed = 0x20;
4286 if (speed > 0xFF)
4287 speed = 0xFF;
4288 break;
4289 }
4290 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4291 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4292 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4293 goto err;
4294 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4295 goto err;
4296 }
4297
e415c689
MA		 4298 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4299 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4300 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4301 goto err;
4302 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4303 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4304 goto err;
4305
4306 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4307 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4308 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4309 goto err;
4310 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4311 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4312 goto err;
4313
4314 return 0;
4315err:
4316 dprintk(FE_ERROR, 1, "I/O error");
4317 return -1;
4318}
4319
4320static int stv090x_init(struct dvb_frontend *fe)
4321{
4322 struct stv090x_state *state = fe->demodulator_priv;
4323 const struct stv090x_config *config = state->config;
4324 u32 reg;
4325
9045e729
AR		 4326 if (state->internal->mclk == 0) {
4327 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4328 msleep(5);
4329 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4330 0x20 | config->clk_mode) < 0)
4331 goto err;
4332 stv090x_get_mclk(state);
4333 }
4334
cbc320d2
AR		 4335 if (stv090x_wakeup(fe) < 0) {
4336 dprintk(FE_ERROR, 1, "Error waking device");
4337 goto err;
4338 }
4339
27d40321
MA		 4340 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4341 goto err;
e415c689
MA		 4342
4343 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4344 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4345 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4346 goto err;
4347 reg = STV090x_READ_DEMOD(state, DEMOD);
4348 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4349 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4350 goto err;
4351
19c4ee58 4352 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
27d40321 4353 goto err;
e415c689 4354
27d40321
MA		 4355 if (config->tuner_set_mode) {
4356 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
2c1f750b 4357 goto err_gateoff;
27d40321 4358 }
e415c689 4359
27d40321
MA		 4360 if (config->tuner_init) {
4361 if (config->tuner_init(fe) < 0)
2c1f750b 4362 goto err_gateoff;
27d40321
MA		 4363 }
4364
19c4ee58 4365 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
27d40321 4366 goto err;
e415c689 4367
27d40321
MA		 4368 if (stv090x_set_tspath(state) < 0)
4369 goto err;
e415c689
MA		 4370
4371 return 0;
2c1f750b
OE		 4372
4373err_gateoff:
19c4ee58 4374 stv090x_i2c_gate_ctrl(state, 0);
e415c689
MA		 4375err:
4376 dprintk(FE_ERROR, 1, "I/O error");
4377 return -1;
4378}
4379
4380static int stv090x_setup(struct dvb_frontend *fe)
4381{
4382 struct stv090x_state *state = fe->demodulator_priv;
4383 const struct stv090x_config *config = state->config;
4384 const struct stv090x_reg *stv090x_initval = NULL;
4385 const struct stv090x_reg *stv090x_cut20_val = NULL;
4386 unsigned long t1_size = 0, t2_size = 0;
017eb038 4387 u32 reg = 0;
e415c689
MA		 4388
4389 int i;
4390
4391 if (state->device == STV0900) {
4392 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4393 stv090x_initval = stv0900_initval;
4394 t1_size = ARRAY_SIZE(stv0900_initval);
4395 stv090x_cut20_val = stv0900_cut20_val;
4396 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4397 } else if (state->device == STV0903) {
4398 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4399 stv090x_initval = stv0903_initval;
4400 t1_size = ARRAY_SIZE(stv0903_initval);
4401 stv090x_cut20_val = stv0903_cut20_val;
4402 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4403 }
4404
4405 /* STV090x init */
97f7a2ae
AR		 4406
4407 /* Stop Demod */
4408 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4409 goto err;
4410 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
e415c689
MA		 4411 goto err;
4412
4413 msleep(5);
4414
97f7a2ae
AR		 4415 /* Set No Tuner Mode */
4416 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4417 goto err;
4418 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
e415c689
MA		 4419 goto err;
4420
97f7a2ae 4421 /* I2C repeater OFF */
017eb038 4422 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
97f7a2ae
AR		 4423 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4424 goto err;
4425 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
e415c689
MA		 4426 goto err;
4427
4428 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4429 goto err;
4430 msleep(5);
4431 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4432 goto err;
4433 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4434 goto err;
4435 msleep(5);
4436
4437 /* write initval */
2f5914be 4438 dprintk(FE_DEBUG, 1, "Setting up initial values");
e415c689 4439 for (i = 0; i < t1_size; i++) {
e415c689
MA		 4440 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4441 goto err;
4442 }
4443
97f7a2ae
AR		 4444 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4445 if (state->internal->dev_ver >= 0x20) {
e415c689
MA		 4446 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4447 goto err;
4448
4449 /* write cut20_val*/
4450 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4451 for (i = 0; i < t2_size; i++) {
4452 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4453 goto err;
4454 }
27d40321 4455
97f7a2ae 4456 } else if (state->internal->dev_ver < 0x20) {
27d40321 4457 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
97f7a2ae 4458 state->internal->dev_ver);
27d40321
MA		 4459
4460 goto err;
97f7a2ae 4461 } else if (state->internal->dev_ver > 0x30) {
27d40321
MA		 4462 /* we shouldn't bail out from here */
4463 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
97f7a2ae 4464 state->internal->dev_ver);
e415c689
MA		 4465 }
4466
d8b5a8e4
OE		 4467 /* ADC1 range */
4468 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4469 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4470 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
4471 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4472 goto err;
4473
4474 /* ADC2 range */
4475 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4476 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4477 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
4478 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4479 goto err;
4480
e415c689
MA		 4481 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4482 goto err;
4483 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4484 goto err;
4485
5dd92c1f
OE		 4486 /* workaround for stuck DiSEqC output */
4487 if (config->diseqc_envelope_mode)
4488 stv090x_send_diseqc_burst(fe, SEC_MINI_A);
4489
e415c689
MA		 4490 return 0;
4491err:
4492 dprintk(FE_ERROR, 1, "I/O error");
4493 return -1;
4494}
4495
4496static struct dvb_frontend_ops stv090x_ops = {
4497
4498 .info = {
4499 .name = "STV090x Multistandard",
7fc08bbb
AR		 4500 .type = FE_QPSK,
4501 .frequency_min = 950000,
4502 .frequency_max = 2150000,
4503 .frequency_stepsize = 0,
4504 .frequency_tolerance = 0,
4505 .symbol_rate_min = 1000000,
4506 .symbol_rate_max = 45000000,
4507 .caps = FE_CAN_INVERSION_AUTO |
4508 FE_CAN_FEC_AUTO |
4509 FE_CAN_QPSK |
4510 FE_CAN_2G_MODULATION
e415c689
MA		 4511 },
4512
4513 .release = stv090x_release,
4514 .init = stv090x_init,
4515
4516 .sleep = stv090x_sleep,
4517 .get_frontend_algo = stv090x_frontend_algo,
4518
e415c689 4519 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
f9ed95d0 4520 .diseqc_send_burst = stv090x_send_diseqc_burst,
e415c689
MA		 4521 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4522 .set_tone = stv090x_set_tone,
4523
4524 .search = stv090x_search,
4525 .read_status = stv090x_read_status,
4526 .read_ber = stv090x_read_per,
4527 .read_signal_strength = stv090x_read_signal_strength,
4528 .read_snr = stv090x_read_cnr
4529};
4530
4531
4532struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4533 struct i2c_adapter *i2c,
4534 enum stv090x_demodulator demod)
4535{
4536 struct stv090x_state *state = NULL;
97f7a2ae 4537 struct stv090x_dev *temp_int;
e415c689
MA		 4538
4539 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4540 if (state == NULL)
4541 goto error;
4542
4543 state->verbose = &verbose;
4544 state->config = config;
4545 state->i2c = i2c;
4546 state->frontend.ops = stv090x_ops;
4547 state->frontend.demodulator_priv = state;
56571507 4548 state->demod = demod;
e415c689
MA		 4549 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4550 state->device = config->device;
4e58a682 4551 state->rolloff = STV090x_RO_35; /* default */
e415c689 4552
97f7a2ae
AR		 4553 temp_int = find_dev(state->i2c,
4554 state->config->address);
4555
4556 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4557 state->internal = temp_int->internal;
4558 state->internal->num_used++;
4559 dprintk(FE_INFO, 1, "Found Internal Structure!");
4560 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4561 state->device == STV0900 ? "STV0900" : "STV0903",
4562 demod,
4563 state->internal->dev_ver);
4564 return &state->frontend;
4565 } else {
4566 state->internal = kmalloc(sizeof(struct stv090x_internal),
4567 GFP_KERNEL);
4568 temp_int = append_internal(state->internal);
4569 state->internal->num_used = 1;
76b9ef97
AR		 4570 state->internal->mclk = 0;
4571 state->internal->dev_ver = 0;
97f7a2ae
AR		 4572 state->internal->i2c_adap = state->i2c;
4573 state->internal->i2c_addr = state->config->address;
4574 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4575 }
4576
4577 mutex_init(&state->internal->demod_lock);
96506a50 4578 mutex_init(&state->internal->tuner_lock);
e415c689
MA		 4579
4580 if (stv090x_sleep(&state->frontend) < 0) {
4581 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4582 goto error;
4583 }
4584
4585 if (stv090x_setup(&state->frontend) < 0) {
4586 dprintk(FE_ERROR, 1, "Error setting up device");
4587 goto error;
4588 }
4589 if (stv090x_wakeup(&state->frontend) < 0) {
4590 dprintk(FE_ERROR, 1, "Error waking device");
4591 goto error;
4592 }
e415c689 4593
97f7a2ae 4594 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
e415c689
MA		 4595 state->device == STV0900 ? "STV0900" : "STV0903",
4596 demod,
97f7a2ae 4597 state->internal->dev_ver);
e415c689
MA		 4598
4599 return &state->frontend;
4600
4601error:
4602 kfree(state);
4603 return NULL;
4604}
4605EXPORT_SYMBOL(stv090x_attach);
4606MODULE_PARM_DESC(verbose, "Set Verbosity level");
4607MODULE_AUTHOR("Manu Abraham");
4608MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4609MODULE_LICENSE("GPL");
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