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e415c689 MA |
1 | /* |
2 | STV0900/0903 Multistandard Broadcast Frontend driver | |
3 | Copyright (C) Manu Abraham <abraham.manu@gmail.com> | |
4 | ||
5 | Copyright (C) ST Microelectronics | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/string.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
e415c689 MA |
27 | #include <linux/mutex.h> |
28 | ||
29 | #include <linux/dvb/frontend.h> | |
30 | #include "dvb_frontend.h" | |
31 | ||
32 | #include "stv6110x.h" /* for demodulator internal modes */ | |
33 | ||
34 | #include "stv090x_reg.h" | |
35 | #include "stv090x.h" | |
36 | #include "stv090x_priv.h" | |
37 | ||
38 | static unsigned int verbose; | |
39 | module_param(verbose, int, 0644); | |
40 | ||
97f7a2ae AR |
41 | /* internal params node */ |
42 | struct stv090x_dev { | |
43 | /* pointer for internal params, one for each pair of demods */ | |
44 | struct stv090x_internal *internal; | |
45 | struct stv090x_dev *next_dev; | |
46 | }; | |
47 | ||
48 | /* first internal params */ | |
49 | static struct stv090x_dev *stv090x_first_dev; | |
50 | ||
51 | /* find chip by i2c adapter and i2c address */ | |
52 | static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, | |
53 | u8 i2c_addr) | |
54 | { | |
55 | struct stv090x_dev *temp_dev = stv090x_first_dev; | |
56 | ||
57 | /* | |
58 | Search of the last stv0900 chip or | |
59 | find it by i2c adapter and i2c address */ | |
60 | while ((temp_dev != NULL) && | |
61 | ((temp_dev->internal->i2c_adap != i2c_adap) || | |
62 | (temp_dev->internal->i2c_addr != i2c_addr))) { | |
63 | ||
64 | temp_dev = temp_dev->next_dev; | |
65 | } | |
66 | ||
67 | return temp_dev; | |
68 | } | |
69 | ||
70 | /* deallocating chip */ | |
71 | static void remove_dev(struct stv090x_internal *internal) | |
72 | { | |
73 | struct stv090x_dev *prev_dev = stv090x_first_dev; | |
74 | struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, | |
75 | internal->i2c_addr); | |
76 | ||
77 | if (del_dev != NULL) { | |
78 | if (del_dev == stv090x_first_dev) { | |
79 | stv090x_first_dev = del_dev->next_dev; | |
80 | } else { | |
81 | while (prev_dev->next_dev != del_dev) | |
82 | prev_dev = prev_dev->next_dev; | |
83 | ||
84 | prev_dev->next_dev = del_dev->next_dev; | |
85 | } | |
86 | ||
87 | kfree(del_dev); | |
88 | } | |
89 | } | |
90 | ||
91 | /* allocating new chip */ | |
92 | static struct stv090x_dev *append_internal(struct stv090x_internal *internal) | |
93 | { | |
94 | struct stv090x_dev *new_dev; | |
95 | struct stv090x_dev *temp_dev; | |
96 | ||
97 | new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); | |
98 | if (new_dev != NULL) { | |
99 | new_dev->internal = internal; | |
100 | new_dev->next_dev = NULL; | |
101 | ||
102 | /* append to list */ | |
103 | if (stv090x_first_dev == NULL) { | |
104 | stv090x_first_dev = new_dev; | |
105 | } else { | |
106 | temp_dev = stv090x_first_dev; | |
107 | while (temp_dev->next_dev != NULL) | |
108 | temp_dev = temp_dev->next_dev; | |
109 | ||
110 | temp_dev->next_dev = new_dev; | |
111 | } | |
112 | } | |
113 | ||
114 | return new_dev; | |
115 | } | |
116 | ||
e415c689 MA |
117 | |
118 | /* DVBS1 and DSS C/N Lookup table */ | |
119 | static const struct stv090x_tab stv090x_s1cn_tab[] = { | |
120 | { 0, 8917 }, /* 0.0dB */ | |
121 | { 5, 8801 }, /* 0.5dB */ | |
122 | { 10, 8667 }, /* 1.0dB */ | |
123 | { 15, 8522 }, /* 1.5dB */ | |
124 | { 20, 8355 }, /* 2.0dB */ | |
125 | { 25, 8175 }, /* 2.5dB */ | |
126 | { 30, 7979 }, /* 3.0dB */ | |
127 | { 35, 7763 }, /* 3.5dB */ | |
128 | { 40, 7530 }, /* 4.0dB */ | |
129 | { 45, 7282 }, /* 4.5dB */ | |
130 | { 50, 7026 }, /* 5.0dB */ | |
131 | { 55, 6781 }, /* 5.5dB */ | |
132 | { 60, 6514 }, /* 6.0dB */ | |
133 | { 65, 6241 }, /* 6.5dB */ | |
134 | { 70, 5965 }, /* 7.0dB */ | |
135 | { 75, 5690 }, /* 7.5dB */ | |
136 | { 80, 5424 }, /* 8.0dB */ | |
137 | { 85, 5161 }, /* 8.5dB */ | |
138 | { 90, 4902 }, /* 9.0dB */ | |
139 | { 95, 4654 }, /* 9.5dB */ | |
140 | { 100, 4417 }, /* 10.0dB */ | |
141 | { 105, 4186 }, /* 10.5dB */ | |
142 | { 110, 3968 }, /* 11.0dB */ | |
143 | { 115, 3757 }, /* 11.5dB */ | |
144 | { 120, 3558 }, /* 12.0dB */ | |
145 | { 125, 3366 }, /* 12.5dB */ | |
146 | { 130, 3185 }, /* 13.0dB */ | |
147 | { 135, 3012 }, /* 13.5dB */ | |
148 | { 140, 2850 }, /* 14.0dB */ | |
149 | { 145, 2698 }, /* 14.5dB */ | |
150 | { 150, 2550 }, /* 15.0dB */ | |
151 | { 160, 2283 }, /* 16.0dB */ | |
152 | { 170, 2042 }, /* 17.0dB */ | |
153 | { 180, 1827 }, /* 18.0dB */ | |
154 | { 190, 1636 }, /* 19.0dB */ | |
155 | { 200, 1466 }, /* 20.0dB */ | |
156 | { 210, 1315 }, /* 21.0dB */ | |
157 | { 220, 1181 }, /* 22.0dB */ | |
158 | { 230, 1064 }, /* 23.0dB */ | |
159 | { 240, 960 }, /* 24.0dB */ | |
160 | { 250, 869 }, /* 25.0dB */ | |
161 | { 260, 792 }, /* 26.0dB */ | |
162 | { 270, 724 }, /* 27.0dB */ | |
163 | { 280, 665 }, /* 28.0dB */ | |
164 | { 290, 616 }, /* 29.0dB */ | |
165 | { 300, 573 }, /* 30.0dB */ | |
166 | { 310, 537 }, /* 31.0dB */ | |
167 | { 320, 507 }, /* 32.0dB */ | |
168 | { 330, 483 }, /* 33.0dB */ | |
169 | { 400, 398 }, /* 40.0dB */ | |
170 | { 450, 381 }, /* 45.0dB */ | |
171 | { 500, 377 } /* 50.0dB */ | |
172 | }; | |
173 | ||
174 | /* DVBS2 C/N Lookup table */ | |
175 | static const struct stv090x_tab stv090x_s2cn_tab[] = { | |
176 | { -30, 13348 }, /* -3.0dB */ | |
177 | { -20, 12640 }, /* -2d.0B */ | |
178 | { -10, 11883 }, /* -1.0dB */ | |
179 | { 0, 11101 }, /* -0.0dB */ | |
180 | { 5, 10718 }, /* 0.5dB */ | |
181 | { 10, 10339 }, /* 1.0dB */ | |
182 | { 15, 9947 }, /* 1.5dB */ | |
183 | { 20, 9552 }, /* 2.0dB */ | |
184 | { 25, 9183 }, /* 2.5dB */ | |
185 | { 30, 8799 }, /* 3.0dB */ | |
186 | { 35, 8422 }, /* 3.5dB */ | |
187 | { 40, 8062 }, /* 4.0dB */ | |
188 | { 45, 7707 }, /* 4.5dB */ | |
189 | { 50, 7353 }, /* 5.0dB */ | |
190 | { 55, 7025 }, /* 5.5dB */ | |
191 | { 60, 6684 }, /* 6.0dB */ | |
192 | { 65, 6331 }, /* 6.5dB */ | |
193 | { 70, 6036 }, /* 7.0dB */ | |
194 | { 75, 5727 }, /* 7.5dB */ | |
195 | { 80, 5437 }, /* 8.0dB */ | |
196 | { 85, 5164 }, /* 8.5dB */ | |
197 | { 90, 4902 }, /* 9.0dB */ | |
198 | { 95, 4653 }, /* 9.5dB */ | |
199 | { 100, 4408 }, /* 10.0dB */ | |
200 | { 105, 4187 }, /* 10.5dB */ | |
201 | { 110, 3961 }, /* 11.0dB */ | |
202 | { 115, 3751 }, /* 11.5dB */ | |
203 | { 120, 3558 }, /* 12.0dB */ | |
204 | { 125, 3368 }, /* 12.5dB */ | |
205 | { 130, 3191 }, /* 13.0dB */ | |
206 | { 135, 3017 }, /* 13.5dB */ | |
207 | { 140, 2862 }, /* 14.0dB */ | |
208 | { 145, 2710 }, /* 14.5dB */ | |
209 | { 150, 2565 }, /* 15.0dB */ | |
210 | { 160, 2300 }, /* 16.0dB */ | |
211 | { 170, 2058 }, /* 17.0dB */ | |
212 | { 180, 1849 }, /* 18.0dB */ | |
213 | { 190, 1663 }, /* 19.0dB */ | |
214 | { 200, 1495 }, /* 20.0dB */ | |
215 | { 210, 1349 }, /* 21.0dB */ | |
216 | { 220, 1222 }, /* 22.0dB */ | |
217 | { 230, 1110 }, /* 23.0dB */ | |
218 | { 240, 1011 }, /* 24.0dB */ | |
219 | { 250, 925 }, /* 25.0dB */ | |
220 | { 260, 853 }, /* 26.0dB */ | |
221 | { 270, 789 }, /* 27.0dB */ | |
222 | { 280, 734 }, /* 28.0dB */ | |
223 | { 290, 690 }, /* 29.0dB */ | |
224 | { 300, 650 }, /* 30.0dB */ | |
225 | { 310, 619 }, /* 31.0dB */ | |
226 | { 320, 593 }, /* 32.0dB */ | |
227 | { 330, 571 }, /* 33.0dB */ | |
228 | { 400, 498 }, /* 40.0dB */ | |
229 | { 450, 484 }, /* 45.0dB */ | |
230 | { 500, 481 } /* 50.0dB */ | |
231 | }; | |
232 | ||
233 | /* RF level C/N lookup table */ | |
234 | static const struct stv090x_tab stv090x_rf_tab[] = { | |
235 | { -5, 0xcaa1 }, /* -5dBm */ | |
236 | { -10, 0xc229 }, /* -10dBm */ | |
237 | { -15, 0xbb08 }, /* -15dBm */ | |
238 | { -20, 0xb4bc }, /* -20dBm */ | |
239 | { -25, 0xad5a }, /* -25dBm */ | |
240 | { -30, 0xa298 }, /* -30dBm */ | |
241 | { -35, 0x98a8 }, /* -35dBm */ | |
242 | { -40, 0x8389 }, /* -40dBm */ | |
243 | { -45, 0x59be }, /* -45dBm */ | |
244 | { -50, 0x3a14 }, /* -50dBm */ | |
245 | { -55, 0x2d11 }, /* -55dBm */ | |
246 | { -60, 0x210d }, /* -60dBm */ | |
247 | { -65, 0xa14f }, /* -65dBm */ | |
248 | { -70, 0x07aa } /* -70dBm */ | |
249 | }; | |
250 | ||
251 | ||
252 | static struct stv090x_reg stv0900_initval[] = { | |
253 | ||
254 | { STV090x_OUTCFG, 0x00 }, | |
56571507 | 255 | { STV090x_MODECFG, 0xff }, |
e415c689 MA |
256 | { STV090x_AGCRF1CFG, 0x11 }, |
257 | { STV090x_AGCRF2CFG, 0x13 }, | |
56571507 | 258 | { STV090x_TSGENERAL1X, 0x14 }, |
e415c689 MA |
259 | { STV090x_TSTTNR2, 0x21 }, |
260 | { STV090x_TSTTNR4, 0x21 }, | |
261 | { STV090x_P2_DISTXCTL, 0x22 }, | |
262 | { STV090x_P2_F22TX, 0xc0 }, | |
263 | { STV090x_P2_F22RX, 0xc0 }, | |
264 | { STV090x_P2_DISRXCTL, 0x00 }, | |
265 | { STV090x_P2_DMDCFGMD, 0xF9 }, | |
266 | { STV090x_P2_DEMOD, 0x08 }, | |
267 | { STV090x_P2_DMDCFG3, 0xc4 }, | |
268 | { STV090x_P2_CARFREQ, 0xed }, | |
269 | { STV090x_P2_LDT, 0xd0 }, | |
270 | { STV090x_P2_LDT2, 0xb8 }, | |
271 | { STV090x_P2_TMGCFG, 0xd2 }, | |
272 | { STV090x_P2_TMGTHRISE, 0x20 }, | |
273 | { STV090x_P1_TMGCFG, 0xd2 }, | |
274 | ||
275 | { STV090x_P2_TMGTHFALL, 0x00 }, | |
276 | { STV090x_P2_FECSPY, 0x88 }, | |
277 | { STV090x_P2_FSPYDATA, 0x3a }, | |
278 | { STV090x_P2_FBERCPT4, 0x00 }, | |
279 | { STV090x_P2_FSPYBER, 0x10 }, | |
280 | { STV090x_P2_ERRCTRL1, 0x35 }, | |
281 | { STV090x_P2_ERRCTRL2, 0xc1 }, | |
282 | { STV090x_P2_CFRICFG, 0xf8 }, | |
283 | { STV090x_P2_NOSCFG, 0x1c }, | |
56571507 | 284 | { STV090x_P2_DMDTOM, 0x20 }, |
e415c689 MA |
285 | { STV090x_P2_CORRELMANT, 0x70 }, |
286 | { STV090x_P2_CORRELABS, 0x88 }, | |
56571507 | 287 | { STV090x_P2_AGC2O, 0x5b }, |
e415c689 MA |
288 | { STV090x_P2_AGC2REF, 0x38 }, |
289 | { STV090x_P2_CARCFG, 0xe4 }, | |
290 | { STV090x_P2_ACLC, 0x1A }, | |
291 | { STV090x_P2_BCLC, 0x09 }, | |
292 | { STV090x_P2_CARHDR, 0x08 }, | |
293 | { STV090x_P2_KREFTMG, 0xc1 }, | |
294 | { STV090x_P2_SFRUPRATIO, 0xf0 }, | |
295 | { STV090x_P2_SFRLOWRATIO, 0x70 }, | |
296 | { STV090x_P2_SFRSTEP, 0x58 }, | |
297 | { STV090x_P2_TMGCFG2, 0x01 }, | |
298 | { STV090x_P2_CAR2CFG, 0x26 }, | |
299 | { STV090x_P2_BCLC2S2Q, 0x86 }, | |
300 | { STV090x_P2_BCLC2S28, 0x86 }, | |
301 | { STV090x_P2_SMAPCOEF7, 0x77 }, | |
302 | { STV090x_P2_SMAPCOEF6, 0x85 }, | |
303 | { STV090x_P2_SMAPCOEF5, 0x77 }, | |
304 | { STV090x_P2_TSCFGL, 0x20 }, | |
305 | { STV090x_P2_DMDCFG2, 0x3b }, | |
306 | { STV090x_P2_MODCODLST0, 0xff }, | |
307 | { STV090x_P2_MODCODLST1, 0xff }, | |
308 | { STV090x_P2_MODCODLST2, 0xff }, | |
309 | { STV090x_P2_MODCODLST3, 0xff }, | |
310 | { STV090x_P2_MODCODLST4, 0xff }, | |
311 | { STV090x_P2_MODCODLST5, 0xff }, | |
312 | { STV090x_P2_MODCODLST6, 0xff }, | |
313 | { STV090x_P2_MODCODLST7, 0xcc }, | |
314 | { STV090x_P2_MODCODLST8, 0xcc }, | |
315 | { STV090x_P2_MODCODLST9, 0xcc }, | |
316 | { STV090x_P2_MODCODLSTA, 0xcc }, | |
317 | { STV090x_P2_MODCODLSTB, 0xcc }, | |
318 | { STV090x_P2_MODCODLSTC, 0xcc }, | |
319 | { STV090x_P2_MODCODLSTD, 0xcc }, | |
320 | { STV090x_P2_MODCODLSTE, 0xcc }, | |
321 | { STV090x_P2_MODCODLSTF, 0xcf }, | |
322 | { STV090x_P1_DISTXCTL, 0x22 }, | |
323 | { STV090x_P1_F22TX, 0xc0 }, | |
324 | { STV090x_P1_F22RX, 0xc0 }, | |
325 | { STV090x_P1_DISRXCTL, 0x00 }, | |
326 | { STV090x_P1_DMDCFGMD, 0xf9 }, | |
327 | { STV090x_P1_DEMOD, 0x08 }, | |
328 | { STV090x_P1_DMDCFG3, 0xc4 }, | |
56571507 | 329 | { STV090x_P1_DMDTOM, 0x20 }, |
e415c689 MA |
330 | { STV090x_P1_CARFREQ, 0xed }, |
331 | { STV090x_P1_LDT, 0xd0 }, | |
332 | { STV090x_P1_LDT2, 0xb8 }, | |
333 | { STV090x_P1_TMGCFG, 0xd2 }, | |
334 | { STV090x_P1_TMGTHRISE, 0x20 }, | |
335 | { STV090x_P1_TMGTHFALL, 0x00 }, | |
336 | { STV090x_P1_SFRUPRATIO, 0xf0 }, | |
337 | { STV090x_P1_SFRLOWRATIO, 0x70 }, | |
338 | { STV090x_P1_TSCFGL, 0x20 }, | |
339 | { STV090x_P1_FECSPY, 0x88 }, | |
340 | { STV090x_P1_FSPYDATA, 0x3a }, | |
341 | { STV090x_P1_FBERCPT4, 0x00 }, | |
342 | { STV090x_P1_FSPYBER, 0x10 }, | |
343 | { STV090x_P1_ERRCTRL1, 0x35 }, | |
344 | { STV090x_P1_ERRCTRL2, 0xc1 }, | |
345 | { STV090x_P1_CFRICFG, 0xf8 }, | |
346 | { STV090x_P1_NOSCFG, 0x1c }, | |
347 | { STV090x_P1_CORRELMANT, 0x70 }, | |
348 | { STV090x_P1_CORRELABS, 0x88 }, | |
56571507 | 349 | { STV090x_P1_AGC2O, 0x5b }, |
e415c689 MA |
350 | { STV090x_P1_AGC2REF, 0x38 }, |
351 | { STV090x_P1_CARCFG, 0xe4 }, | |
352 | { STV090x_P1_ACLC, 0x1A }, | |
353 | { STV090x_P1_BCLC, 0x09 }, | |
354 | { STV090x_P1_CARHDR, 0x08 }, | |
355 | { STV090x_P1_KREFTMG, 0xc1 }, | |
356 | { STV090x_P1_SFRSTEP, 0x58 }, | |
357 | { STV090x_P1_TMGCFG2, 0x01 }, | |
358 | { STV090x_P1_CAR2CFG, 0x26 }, | |
359 | { STV090x_P1_BCLC2S2Q, 0x86 }, | |
360 | { STV090x_P1_BCLC2S28, 0x86 }, | |
361 | { STV090x_P1_SMAPCOEF7, 0x77 }, | |
362 | { STV090x_P1_SMAPCOEF6, 0x85 }, | |
363 | { STV090x_P1_SMAPCOEF5, 0x77 }, | |
364 | { STV090x_P1_DMDCFG2, 0x3b }, | |
365 | { STV090x_P1_MODCODLST0, 0xff }, | |
366 | { STV090x_P1_MODCODLST1, 0xff }, | |
367 | { STV090x_P1_MODCODLST2, 0xff }, | |
368 | { STV090x_P1_MODCODLST3, 0xff }, | |
369 | { STV090x_P1_MODCODLST4, 0xff }, | |
370 | { STV090x_P1_MODCODLST5, 0xff }, | |
371 | { STV090x_P1_MODCODLST6, 0xff }, | |
372 | { STV090x_P1_MODCODLST7, 0xcc }, | |
373 | { STV090x_P1_MODCODLST8, 0xcc }, | |
374 | { STV090x_P1_MODCODLST9, 0xcc }, | |
375 | { STV090x_P1_MODCODLSTA, 0xcc }, | |
376 | { STV090x_P1_MODCODLSTB, 0xcc }, | |
377 | { STV090x_P1_MODCODLSTC, 0xcc }, | |
378 | { STV090x_P1_MODCODLSTD, 0xcc }, | |
379 | { STV090x_P1_MODCODLSTE, 0xcc }, | |
380 | { STV090x_P1_MODCODLSTF, 0xcf }, | |
381 | { STV090x_GENCFG, 0x1d }, | |
382 | { STV090x_NBITER_NF4, 0x37 }, | |
383 | { STV090x_NBITER_NF5, 0x29 }, | |
384 | { STV090x_NBITER_NF6, 0x37 }, | |
385 | { STV090x_NBITER_NF7, 0x33 }, | |
386 | { STV090x_NBITER_NF8, 0x31 }, | |
387 | { STV090x_NBITER_NF9, 0x2f }, | |
388 | { STV090x_NBITER_NF10, 0x39 }, | |
389 | { STV090x_NBITER_NF11, 0x3a }, | |
390 | { STV090x_NBITER_NF12, 0x29 }, | |
391 | { STV090x_NBITER_NF13, 0x37 }, | |
392 | { STV090x_NBITER_NF14, 0x33 }, | |
393 | { STV090x_NBITER_NF15, 0x2f }, | |
394 | { STV090x_NBITER_NF16, 0x39 }, | |
395 | { STV090x_NBITER_NF17, 0x3a }, | |
396 | { STV090x_NBITERNOERR, 0x04 }, | |
397 | { STV090x_GAINLLR_NF4, 0x0C }, | |
398 | { STV090x_GAINLLR_NF5, 0x0F }, | |
399 | { STV090x_GAINLLR_NF6, 0x11 }, | |
400 | { STV090x_GAINLLR_NF7, 0x14 }, | |
401 | { STV090x_GAINLLR_NF8, 0x17 }, | |
402 | { STV090x_GAINLLR_NF9, 0x19 }, | |
403 | { STV090x_GAINLLR_NF10, 0x20 }, | |
404 | { STV090x_GAINLLR_NF11, 0x21 }, | |
405 | { STV090x_GAINLLR_NF12, 0x0D }, | |
406 | { STV090x_GAINLLR_NF13, 0x0F }, | |
407 | { STV090x_GAINLLR_NF14, 0x13 }, | |
408 | { STV090x_GAINLLR_NF15, 0x1A }, | |
409 | { STV090x_GAINLLR_NF16, 0x1F }, | |
410 | { STV090x_GAINLLR_NF17, 0x21 }, | |
56571507 | 411 | { STV090x_RCCFGH, 0x20 }, |
e415c689 MA |
412 | { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ |
413 | { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ | |
414 | { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ | |
415 | { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */ | |
416 | }; | |
417 | ||
418 | static struct stv090x_reg stv0903_initval[] = { | |
419 | { STV090x_OUTCFG, 0x00 }, | |
420 | { STV090x_AGCRF1CFG, 0x11 }, | |
421 | { STV090x_STOPCLK1, 0x48 }, | |
422 | { STV090x_STOPCLK2, 0x14 }, | |
423 | { STV090x_TSTTNR1, 0x27 }, | |
424 | { STV090x_TSTTNR2, 0x21 }, | |
425 | { STV090x_P1_DISTXCTL, 0x22 }, | |
426 | { STV090x_P1_F22TX, 0xc0 }, | |
427 | { STV090x_P1_F22RX, 0xc0 }, | |
428 | { STV090x_P1_DISRXCTL, 0x00 }, | |
429 | { STV090x_P1_DMDCFGMD, 0xF9 }, | |
430 | { STV090x_P1_DEMOD, 0x08 }, | |
431 | { STV090x_P1_DMDCFG3, 0xc4 }, | |
432 | { STV090x_P1_CARFREQ, 0xed }, | |
433 | { STV090x_P1_TNRCFG2, 0x82 }, | |
434 | { STV090x_P1_LDT, 0xd0 }, | |
435 | { STV090x_P1_LDT2, 0xb8 }, | |
436 | { STV090x_P1_TMGCFG, 0xd2 }, | |
437 | { STV090x_P1_TMGTHRISE, 0x20 }, | |
438 | { STV090x_P1_TMGTHFALL, 0x00 }, | |
439 | { STV090x_P1_SFRUPRATIO, 0xf0 }, | |
440 | { STV090x_P1_SFRLOWRATIO, 0x70 }, | |
441 | { STV090x_P1_TSCFGL, 0x20 }, | |
442 | { STV090x_P1_FECSPY, 0x88 }, | |
443 | { STV090x_P1_FSPYDATA, 0x3a }, | |
444 | { STV090x_P1_FBERCPT4, 0x00 }, | |
445 | { STV090x_P1_FSPYBER, 0x10 }, | |
446 | { STV090x_P1_ERRCTRL1, 0x35 }, | |
447 | { STV090x_P1_ERRCTRL2, 0xc1 }, | |
448 | { STV090x_P1_CFRICFG, 0xf8 }, | |
449 | { STV090x_P1_NOSCFG, 0x1c }, | |
56571507 | 450 | { STV090x_P1_DMDTOM, 0x20 }, |
e415c689 MA |
451 | { STV090x_P1_CORRELMANT, 0x70 }, |
452 | { STV090x_P1_CORRELABS, 0x88 }, | |
56571507 MA |
453 | { STV090x_P1_AGC2O, 0x5b }, |
454 | { STV090x_P1_AGC2REF, 0x38 }, | |
e415c689 MA |
455 | { STV090x_P1_CARCFG, 0xe4 }, |
456 | { STV090x_P1_ACLC, 0x1A }, | |
56571507 | 457 | { STV090x_P1_BCLC, 0x09 }, |
e415c689 MA |
458 | { STV090x_P1_CARHDR, 0x08 }, |
459 | { STV090x_P1_KREFTMG, 0xc1 }, | |
460 | { STV090x_P1_SFRSTEP, 0x58 }, | |
461 | { STV090x_P1_TMGCFG2, 0x01 }, | |
462 | { STV090x_P1_CAR2CFG, 0x26 }, | |
463 | { STV090x_P1_BCLC2S2Q, 0x86 }, | |
464 | { STV090x_P1_BCLC2S28, 0x86 }, | |
465 | { STV090x_P1_SMAPCOEF7, 0x77 }, | |
466 | { STV090x_P1_SMAPCOEF6, 0x85 }, | |
467 | { STV090x_P1_SMAPCOEF5, 0x77 }, | |
468 | { STV090x_P1_DMDCFG2, 0x3b }, | |
469 | { STV090x_P1_MODCODLST0, 0xff }, | |
470 | { STV090x_P1_MODCODLST1, 0xff }, | |
471 | { STV090x_P1_MODCODLST2, 0xff }, | |
472 | { STV090x_P1_MODCODLST3, 0xff }, | |
473 | { STV090x_P1_MODCODLST4, 0xff }, | |
474 | { STV090x_P1_MODCODLST5, 0xff }, | |
475 | { STV090x_P1_MODCODLST6, 0xff }, | |
476 | { STV090x_P1_MODCODLST7, 0xcc }, | |
477 | { STV090x_P1_MODCODLST8, 0xcc }, | |
478 | { STV090x_P1_MODCODLST9, 0xcc }, | |
479 | { STV090x_P1_MODCODLSTA, 0xcc }, | |
480 | { STV090x_P1_MODCODLSTB, 0xcc }, | |
481 | { STV090x_P1_MODCODLSTC, 0xcc }, | |
482 | { STV090x_P1_MODCODLSTD, 0xcc }, | |
483 | { STV090x_P1_MODCODLSTE, 0xcc }, | |
484 | { STV090x_P1_MODCODLSTF, 0xcf }, | |
485 | { STV090x_GENCFG, 0x1c }, | |
486 | { STV090x_NBITER_NF4, 0x37 }, | |
487 | { STV090x_NBITER_NF5, 0x29 }, | |
488 | { STV090x_NBITER_NF6, 0x37 }, | |
489 | { STV090x_NBITER_NF7, 0x33 }, | |
490 | { STV090x_NBITER_NF8, 0x31 }, | |
491 | { STV090x_NBITER_NF9, 0x2f }, | |
492 | { STV090x_NBITER_NF10, 0x39 }, | |
493 | { STV090x_NBITER_NF11, 0x3a }, | |
494 | { STV090x_NBITER_NF12, 0x29 }, | |
495 | { STV090x_NBITER_NF13, 0x37 }, | |
496 | { STV090x_NBITER_NF14, 0x33 }, | |
497 | { STV090x_NBITER_NF15, 0x2f }, | |
498 | { STV090x_NBITER_NF16, 0x39 }, | |
499 | { STV090x_NBITER_NF17, 0x3a }, | |
500 | { STV090x_NBITERNOERR, 0x04 }, | |
501 | { STV090x_GAINLLR_NF4, 0x0C }, | |
502 | { STV090x_GAINLLR_NF5, 0x0F }, | |
503 | { STV090x_GAINLLR_NF6, 0x11 }, | |
504 | { STV090x_GAINLLR_NF7, 0x14 }, | |
505 | { STV090x_GAINLLR_NF8, 0x17 }, | |
506 | { STV090x_GAINLLR_NF9, 0x19 }, | |
507 | { STV090x_GAINLLR_NF10, 0x20 }, | |
508 | { STV090x_GAINLLR_NF11, 0x21 }, | |
509 | { STV090x_GAINLLR_NF12, 0x0D }, | |
510 | { STV090x_GAINLLR_NF13, 0x0F }, | |
511 | { STV090x_GAINLLR_NF14, 0x13 }, | |
512 | { STV090x_GAINLLR_NF15, 0x1A }, | |
513 | { STV090x_GAINLLR_NF16, 0x1F }, | |
514 | { STV090x_GAINLLR_NF17, 0x21 }, | |
56571507 | 515 | { STV090x_RCCFGH, 0x20 }, |
e415c689 MA |
516 | { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ |
517 | { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ | |
518 | }; | |
519 | ||
520 | static struct stv090x_reg stv0900_cut20_val[] = { | |
521 | ||
522 | { STV090x_P2_DMDCFG3, 0xe8 }, | |
56571507 | 523 | { STV090x_P2_DMDCFG4, 0x10 }, |
e415c689 MA |
524 | { STV090x_P2_CARFREQ, 0x38 }, |
525 | { STV090x_P2_CARHDR, 0x20 }, | |
526 | { STV090x_P2_KREFTMG, 0x5a }, | |
527 | { STV090x_P2_SMAPCOEF7, 0x06 }, | |
528 | { STV090x_P2_SMAPCOEF6, 0x00 }, | |
529 | { STV090x_P2_SMAPCOEF5, 0x04 }, | |
530 | { STV090x_P2_NOSCFG, 0x0c }, | |
531 | { STV090x_P1_DMDCFG3, 0xe8 }, | |
56571507 | 532 | { STV090x_P1_DMDCFG4, 0x10 }, |
e415c689 MA |
533 | { STV090x_P1_CARFREQ, 0x38 }, |
534 | { STV090x_P1_CARHDR, 0x20 }, | |
535 | { STV090x_P1_KREFTMG, 0x5a }, | |
536 | { STV090x_P1_SMAPCOEF7, 0x06 }, | |
537 | { STV090x_P1_SMAPCOEF6, 0x00 }, | |
538 | { STV090x_P1_SMAPCOEF5, 0x04 }, | |
539 | { STV090x_P1_NOSCFG, 0x0c }, | |
540 | { STV090x_GAINLLR_NF4, 0x21 }, | |
541 | { STV090x_GAINLLR_NF5, 0x21 }, | |
542 | { STV090x_GAINLLR_NF6, 0x20 }, | |
543 | { STV090x_GAINLLR_NF7, 0x1F }, | |
544 | { STV090x_GAINLLR_NF8, 0x1E }, | |
545 | { STV090x_GAINLLR_NF9, 0x1E }, | |
546 | { STV090x_GAINLLR_NF10, 0x1D }, | |
547 | { STV090x_GAINLLR_NF11, 0x1B }, | |
548 | { STV090x_GAINLLR_NF12, 0x20 }, | |
549 | { STV090x_GAINLLR_NF13, 0x20 }, | |
550 | { STV090x_GAINLLR_NF14, 0x20 }, | |
551 | { STV090x_GAINLLR_NF15, 0x20 }, | |
552 | { STV090x_GAINLLR_NF16, 0x20 }, | |
553 | { STV090x_GAINLLR_NF17, 0x21 }, | |
554 | }; | |
555 | ||
556 | static struct stv090x_reg stv0903_cut20_val[] = { | |
557 | { STV090x_P1_DMDCFG3, 0xe8 }, | |
56571507 | 558 | { STV090x_P1_DMDCFG4, 0x10 }, |
e415c689 MA |
559 | { STV090x_P1_CARFREQ, 0x38 }, |
560 | { STV090x_P1_CARHDR, 0x20 }, | |
561 | { STV090x_P1_KREFTMG, 0x5a }, | |
562 | { STV090x_P1_SMAPCOEF7, 0x06 }, | |
563 | { STV090x_P1_SMAPCOEF6, 0x00 }, | |
564 | { STV090x_P1_SMAPCOEF5, 0x04 }, | |
565 | { STV090x_P1_NOSCFG, 0x0c }, | |
566 | { STV090x_GAINLLR_NF4, 0x21 }, | |
567 | { STV090x_GAINLLR_NF5, 0x21 }, | |
568 | { STV090x_GAINLLR_NF6, 0x20 }, | |
569 | { STV090x_GAINLLR_NF7, 0x1F }, | |
570 | { STV090x_GAINLLR_NF8, 0x1E }, | |
571 | { STV090x_GAINLLR_NF9, 0x1E }, | |
572 | { STV090x_GAINLLR_NF10, 0x1D }, | |
573 | { STV090x_GAINLLR_NF11, 0x1B }, | |
574 | { STV090x_GAINLLR_NF12, 0x20 }, | |
575 | { STV090x_GAINLLR_NF13, 0x20 }, | |
576 | { STV090x_GAINLLR_NF14, 0x20 }, | |
577 | { STV090x_GAINLLR_NF15, 0x20 }, | |
578 | { STV090x_GAINLLR_NF16, 0x20 }, | |
579 | { STV090x_GAINLLR_NF17, 0x21 } | |
580 | }; | |
581 | ||
e415c689 MA |
582 | /* Cut 2.0 Long Frame Tracking CR loop */ |
583 | static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { | |
584 | /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ | |
585 | { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, | |
586 | { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, | |
587 | { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, | |
588 | { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, | |
589 | { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, | |
590 | { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, | |
591 | { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, | |
592 | { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, | |
593 | { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, | |
594 | { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, | |
595 | { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, | |
596 | { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, | |
597 | { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, | |
598 | { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } | |
599 | }; | |
600 | ||
27d40321 MA |
601 | /* Cut 3.0 Long Frame Tracking CR loop */ |
602 | static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { | |
603 | /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ | |
604 | { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, | |
605 | { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, | |
606 | { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, | |
607 | { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, | |
608 | { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, | |
609 | { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, | |
610 | { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, | |
611 | { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, | |
612 | { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, | |
613 | { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, | |
614 | { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, | |
615 | { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, | |
616 | { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, | |
617 | { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } | |
618 | }; | |
e415c689 MA |
619 | |
620 | /* Cut 2.0 Long Frame Tracking CR Loop */ | |
621 | static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { | |
622 | /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ | |
623 | { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, | |
624 | { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, | |
625 | { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, | |
626 | { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, | |
627 | { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, | |
628 | { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, | |
629 | { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, | |
630 | { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, | |
631 | { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, | |
632 | { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, | |
633 | { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } | |
634 | }; | |
635 | ||
27d40321 MA |
636 | /* Cut 3.0 Long Frame Tracking CR Loop */ |
637 | static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { | |
638 | /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ | |
639 | { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, | |
640 | { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, | |
641 | { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, | |
642 | { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, | |
643 | { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, | |
644 | { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, | |
645 | { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, | |
646 | { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, | |
647 | { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, | |
648 | { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, | |
649 | { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } | |
650 | }; | |
e415c689 MA |
651 | |
652 | static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { | |
653 | /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ | |
654 | { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, | |
655 | { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, | |
656 | { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } | |
657 | }; | |
658 | ||
27d40321 MA |
659 | static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { |
660 | /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ | |
661 | { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, | |
662 | { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, | |
663 | { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } | |
664 | }; | |
e415c689 | 665 | |
27d40321 MA |
666 | /* Cut 2.0 Short Frame Tracking CR Loop */ |
667 | static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { | |
668 | /* MODCOD 2M 5M 10M 20M 30M */ | |
669 | { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, | |
670 | { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, | |
671 | { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, | |
672 | { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } | |
e415c689 MA |
673 | }; |
674 | ||
27d40321 MA |
675 | /* Cut 3.0 Short Frame Tracking CR Loop */ |
676 | static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { | |
677 | /* MODCOD 2M 5M 10M 20M 30M */ | |
678 | { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, | |
679 | { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, | |
680 | { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, | |
681 | { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } | |
682 | }; | |
e415c689 MA |
683 | |
684 | static inline s32 comp2(s32 __x, s32 __width) | |
685 | { | |
686 | if (__width == 32) | |
687 | return __x; | |
688 | else | |
689 | return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; | |
690 | } | |
691 | ||
692 | static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) | |
693 | { | |
694 | const struct stv090x_config *config = state->config; | |
695 | int ret; | |
696 | ||
697 | u8 b0[] = { reg >> 8, reg & 0xff }; | |
698 | u8 buf; | |
699 | ||
700 | struct i2c_msg msg[] = { | |
701 | { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, | |
702 | { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } | |
703 | }; | |
704 | ||
705 | ret = i2c_transfer(state->i2c, msg, 2); | |
706 | if (ret != 2) { | |
707 | if (ret != -ERESTARTSYS) | |
708 | dprintk(FE_ERROR, 1, | |
709 | "Read error, Reg=[0x%02x], Status=%d", | |
710 | reg, ret); | |
711 | ||
712 | return ret < 0 ? ret : -EREMOTEIO; | |
713 | } | |
714 | if (unlikely(*state->verbose >= FE_DEBUGREG)) | |
715 | dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", | |
716 | reg, buf); | |
717 | ||
718 | return (unsigned int) buf; | |
719 | } | |
720 | ||
721 | static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) | |
722 | { | |
723 | const struct stv090x_config *config = state->config; | |
724 | int ret; | |
725 | u8 buf[2 + count]; | |
726 | struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; | |
727 | ||
728 | buf[0] = reg >> 8; | |
729 | buf[1] = reg & 0xff; | |
730 | memcpy(&buf[2], data, count); | |
731 | ||
732 | if (unlikely(*state->verbose >= FE_DEBUGREG)) { | |
733 | int i; | |
734 | ||
735 | printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); | |
736 | for (i = 0; i < count; i++) | |
737 | printk(" %02x", data[i]); | |
738 | printk("\n"); | |
739 | } | |
740 | ||
741 | ret = i2c_transfer(state->i2c, &i2c_msg, 1); | |
742 | if (ret != 1) { | |
743 | if (ret != -ERESTARTSYS) | |
744 | dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", | |
745 | reg, data[0], count, ret); | |
746 | return ret < 0 ? ret : -EREMOTEIO; | |
747 | } | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) | |
753 | { | |
754 | return stv090x_write_regs(state, reg, &data, 1); | |
755 | } | |
756 | ||
19c4ee58 | 757 | static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) |
e415c689 | 758 | { |
e415c689 MA |
759 | u32 reg; |
760 | ||
c8382c8e MA |
761 | /* |
762 | * NOTE! A lock is used as a FSM to control the state in which | |
763 | * access is serialized between two tuners on the same demod. | |
764 | * This has nothing to do with a lock to protect a critical section | |
765 | * which may in some other cases be confused with protecting I/O | |
766 | * access to the demodulator gate. | |
767 | * In case of any error, the lock is unlocked and exit within the | |
768 | * relevant operations themselves. | |
769 | */ | |
f790bdd0 OE |
770 | if (enable) { |
771 | if (state->config->tuner_i2c_lock) | |
772 | state->config->tuner_i2c_lock(&state->frontend, 1); | |
773 | else | |
774 | mutex_lock(&state->internal->tuner_lock); | |
775 | } | |
96506a50 | 776 | |
e415c689 | 777 | reg = STV090x_READ_DEMOD(state, I2CRPT); |
e415c689 | 778 | if (enable) { |
017eb038 | 779 | dprintk(FE_DEBUG, 1, "Enable Gate"); |
e415c689 MA |
780 | STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); |
781 | if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) | |
782 | goto err; | |
783 | ||
784 | } else { | |
017eb038 | 785 | dprintk(FE_DEBUG, 1, "Disable Gate"); |
e415c689 MA |
786 | STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); |
787 | if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) | |
788 | goto err; | |
789 | } | |
96506a50 | 790 | |
f790bdd0 OE |
791 | if (!enable) { |
792 | if (state->config->tuner_i2c_lock) | |
793 | state->config->tuner_i2c_lock(&state->frontend, 0); | |
794 | else | |
795 | mutex_unlock(&state->internal->tuner_lock); | |
796 | } | |
96506a50 | 797 | |
e415c689 MA |
798 | return 0; |
799 | err: | |
800 | dprintk(FE_ERROR, 1, "I/O error"); | |
f790bdd0 OE |
801 | if (state->config->tuner_i2c_lock) |
802 | state->config->tuner_i2c_lock(&state->frontend, 0); | |
803 | else | |
804 | mutex_unlock(&state->internal->tuner_lock); | |
e415c689 MA |
805 | return -1; |
806 | } | |
807 | ||
808 | static void stv090x_get_lock_tmg(struct stv090x_state *state) | |
809 | { | |
810 | switch (state->algo) { | |
811 | case STV090x_BLIND_SEARCH: | |
812 | dprintk(FE_DEBUG, 1, "Blind Search"); | |
813 | if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ | |
814 | state->DemodTimeout = 1500; | |
815 | state->FecTimeout = 400; | |
816 | } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ | |
817 | state->DemodTimeout = 1000; | |
818 | state->FecTimeout = 300; | |
819 | } else { /*SR >20Msps*/ | |
820 | state->DemodTimeout = 700; | |
821 | state->FecTimeout = 100; | |
822 | } | |
823 | break; | |
824 | ||
825 | case STV090x_COLD_SEARCH: | |
826 | case STV090x_WARM_SEARCH: | |
827 | default: | |
828 | dprintk(FE_DEBUG, 1, "Normal Search"); | |
829 | if (state->srate <= 1000000) { /*SR <=1Msps*/ | |
830 | state->DemodTimeout = 4500; | |
831 | state->FecTimeout = 1700; | |
832 | } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ | |
833 | state->DemodTimeout = 2500; | |
834 | state->FecTimeout = 1100; | |
835 | } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ | |
836 | state->DemodTimeout = 1000; | |
837 | state->FecTimeout = 550; | |
838 | } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ | |
839 | state->DemodTimeout = 700; | |
840 | state->FecTimeout = 250; | |
841 | } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ | |
842 | state->DemodTimeout = 400; | |
843 | state->FecTimeout = 130; | |
844 | } else { /*SR >20Msps*/ | |
845 | state->DemodTimeout = 300; | |
846 | state->FecTimeout = 100; | |
847 | } | |
848 | break; | |
849 | } | |
850 | ||
851 | if (state->algo == STV090x_WARM_SEARCH) | |
852 | state->DemodTimeout /= 2; | |
853 | } | |
854 | ||
855 | static int stv090x_set_srate(struct stv090x_state *state, u32 srate) | |
856 | { | |
857 | u32 sym; | |
858 | ||
15bb366e MA |
859 | if (srate > 60000000) { |
860 | sym = (srate << 4); /* SR * 2^16 / master_clk */ | |
97f7a2ae | 861 | sym /= (state->internal->mclk >> 12); |
15bb366e MA |
862 | } else if (srate > 6000000) { |
863 | sym = (srate << 6); | |
97f7a2ae | 864 | sym /= (state->internal->mclk >> 10); |
e415c689 | 865 | } else { |
15bb366e | 866 | sym = (srate << 9); |
97f7a2ae | 867 | sym /= (state->internal->mclk >> 7); |
e415c689 MA |
868 | } |
869 | ||
15bb366e | 870 | if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ |
e415c689 MA |
871 | goto err; |
872 | if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ | |
873 | goto err; | |
15bb366e | 874 | |
e415c689 MA |
875 | return 0; |
876 | err: | |
877 | dprintk(FE_ERROR, 1, "I/O error"); | |
878 | return -1; | |
879 | } | |
880 | ||
881 | static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) | |
882 | { | |
883 | u32 sym; | |
884 | ||
885 | srate = 105 * (srate / 100); | |
15bb366e MA |
886 | if (srate > 60000000) { |
887 | sym = (srate << 4); /* SR * 2^16 / master_clk */ | |
97f7a2ae | 888 | sym /= (state->internal->mclk >> 12); |
15bb366e MA |
889 | } else if (srate > 6000000) { |
890 | sym = (srate << 6); | |
97f7a2ae | 891 | sym /= (state->internal->mclk >> 10); |
e415c689 | 892 | } else { |
15bb366e | 893 | sym = (srate << 9); |
97f7a2ae | 894 | sym /= (state->internal->mclk >> 7); |
e415c689 | 895 | } |
15bb366e MA |
896 | |
897 | if (sym < 0x7fff) { | |
898 | if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ | |
899 | goto err; | |
900 | if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ | |
901 | goto err; | |
902 | } else { | |
903 | if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ | |
904 | goto err; | |
905 | if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ | |
906 | goto err; | |
907 | } | |
908 | ||
e415c689 MA |
909 | return 0; |
910 | err: | |
911 | dprintk(FE_ERROR, 1, "I/O error"); | |
912 | return -1; | |
913 | } | |
914 | ||
915 | static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) | |
916 | { | |
917 | u32 sym; | |
918 | ||
919 | srate = 95 * (srate / 100); | |
15bb366e MA |
920 | if (srate > 60000000) { |
921 | sym = (srate << 4); /* SR * 2^16 / master_clk */ | |
97f7a2ae | 922 | sym /= (state->internal->mclk >> 12); |
15bb366e MA |
923 | } else if (srate > 6000000) { |
924 | sym = (srate << 6); | |
97f7a2ae | 925 | sym /= (state->internal->mclk >> 10); |
e415c689 | 926 | } else { |
15bb366e | 927 | sym = (srate << 9); |
97f7a2ae | 928 | sym /= (state->internal->mclk >> 7); |
e415c689 | 929 | } |
15bb366e | 930 | |
b671a8d4 | 931 | if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ |
e415c689 MA |
932 | goto err; |
933 | if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ | |
934 | goto err; | |
935 | return 0; | |
936 | err: | |
937 | dprintk(FE_ERROR, 1, "I/O error"); | |
938 | return -1; | |
939 | } | |
940 | ||
4e58a682 | 941 | static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) |
e415c689 | 942 | { |
4e58a682 AR |
943 | u32 ro; |
944 | ||
945 | switch (rolloff) { | |
946 | case STV090x_RO_20: | |
947 | ro = 20; | |
948 | break; | |
949 | case STV090x_RO_25: | |
950 | ro = 25; | |
951 | break; | |
952 | case STV090x_RO_35: | |
953 | default: | |
954 | ro = 35; | |
955 | break; | |
956 | } | |
957 | ||
958 | return srate + (srate * ro) / 100; | |
e415c689 MA |
959 | } |
960 | ||
961 | static int stv090x_set_vit_thacq(struct stv090x_state *state) | |
962 | { | |
963 | if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) | |
964 | goto err; | |
965 | if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) | |
966 | goto err; | |
967 | if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) | |
968 | goto err; | |
969 | if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) | |
970 | goto err; | |
971 | if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) | |
972 | goto err; | |
973 | if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) | |
974 | goto err; | |
975 | return 0; | |
976 | err: | |
977 | dprintk(FE_ERROR, 1, "I/O error"); | |
978 | return -1; | |
979 | } | |
980 | ||
981 | static int stv090x_set_vit_thtracq(struct stv090x_state *state) | |
982 | { | |
983 | if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) | |
984 | goto err; | |
985 | if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) | |
986 | goto err; | |
987 | if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) | |
988 | goto err; | |
989 | if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) | |
990 | goto err; | |
991 | if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) | |
992 | goto err; | |
993 | if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) | |
994 | goto err; | |
995 | return 0; | |
996 | err: | |
997 | dprintk(FE_ERROR, 1, "I/O error"); | |
998 | return -1; | |
999 | } | |
1000 | ||
1001 | static int stv090x_set_viterbi(struct stv090x_state *state) | |
1002 | { | |
1003 | switch (state->search_mode) { | |
1004 | case STV090x_SEARCH_AUTO: | |
1005 | if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ | |
1006 | goto err; | |
1007 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ | |
1008 | goto err; | |
1009 | break; | |
1010 | case STV090x_SEARCH_DVBS1: | |
1011 | if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ | |
1012 | goto err; | |
1013 | switch (state->fec) { | |
1014 | case STV090x_PR12: | |
1015 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) | |
1016 | goto err; | |
1017 | break; | |
1018 | ||
1019 | case STV090x_PR23: | |
1020 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) | |
1021 | goto err; | |
1022 | break; | |
1023 | ||
1024 | case STV090x_PR34: | |
1025 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) | |
1026 | goto err; | |
1027 | break; | |
1028 | ||
1029 | case STV090x_PR56: | |
1030 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) | |
1031 | goto err; | |
1032 | break; | |
1033 | ||
1034 | case STV090x_PR78: | |
1035 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) | |
1036 | goto err; | |
1037 | break; | |
1038 | ||
1039 | default: | |
1040 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ | |
1041 | goto err; | |
1042 | break; | |
1043 | } | |
1044 | break; | |
1045 | case STV090x_SEARCH_DSS: | |
1046 | if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) | |
1047 | goto err; | |
1048 | switch (state->fec) { | |
1049 | case STV090x_PR12: | |
1050 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) | |
1051 | goto err; | |
1052 | break; | |
1053 | ||
1054 | case STV090x_PR23: | |
1055 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) | |
1056 | goto err; | |
1057 | break; | |
1058 | ||
1059 | case STV090x_PR67: | |
1060 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) | |
1061 | goto err; | |
1062 | break; | |
1063 | ||
1064 | default: | |
1065 | if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ | |
1066 | goto err; | |
1067 | break; | |
1068 | } | |
1069 | break; | |
1070 | default: | |
1071 | break; | |
1072 | } | |
1073 | return 0; | |
1074 | err: | |
1075 | dprintk(FE_ERROR, 1, "I/O error"); | |
1076 | return -1; | |
1077 | } | |
1078 | ||
1079 | static int stv090x_stop_modcod(struct stv090x_state *state) | |
1080 | { | |
1081 | if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) | |
1082 | goto err; | |
1083 | if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) | |
1084 | goto err; | |
1085 | if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) | |
1086 | goto err; | |
1087 | if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) | |
1088 | goto err; | |
1089 | if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) | |
1090 | goto err; | |
1091 | if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) | |
1092 | goto err; | |
1093 | if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) | |
1094 | goto err; | |
1095 | if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) | |
1096 | goto err; | |
1097 | if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) | |
1098 | goto err; | |
1099 | if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) | |
1100 | goto err; | |
1101 | if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) | |
1102 | goto err; | |
1103 | if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) | |
1104 | goto err; | |
1105 | if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) | |
1106 | goto err; | |
1107 | if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) | |
1108 | goto err; | |
1109 | if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) | |
1110 | goto err; | |
1111 | if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) | |
1112 | goto err; | |
1113 | return 0; | |
1114 | err: | |
1115 | dprintk(FE_ERROR, 1, "I/O error"); | |
1116 | return -1; | |
1117 | } | |
1118 | ||
1119 | static int stv090x_activate_modcod(struct stv090x_state *state) | |
1120 | { | |
27d40321 MA |
1121 | if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) |
1122 | goto err; | |
1123 | if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) | |
1124 | goto err; | |
1125 | if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) | |
1126 | goto err; | |
1127 | if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) | |
1128 | goto err; | |
1129 | if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) | |
1130 | goto err; | |
1131 | if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) | |
1132 | goto err; | |
1133 | if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) | |
1134 | goto err; | |
1135 | if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) | |
1136 | goto err; | |
1137 | if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) | |
1138 | goto err; | |
1139 | if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) | |
1140 | goto err; | |
1141 | if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) | |
1142 | goto err; | |
1143 | if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) | |
1144 | goto err; | |
1145 | if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) | |
1146 | goto err; | |
1147 | if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) | |
1148 | goto err; | |
1149 | if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) | |
1150 | goto err; | |
1151 | if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) | |
1152 | goto err; | |
e415c689 | 1153 | |
27d40321 MA |
1154 | return 0; |
1155 | err: | |
1156 | dprintk(FE_ERROR, 1, "I/O error"); | |
1157 | return -1; | |
1158 | } | |
1159 | ||
1160 | static int stv090x_activate_modcod_single(struct stv090x_state *state) | |
1161 | { | |
1162 | ||
1163 | if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) | |
1164 | goto err; | |
1165 | if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) | |
1166 | goto err; | |
1167 | if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) | |
1168 | goto err; | |
1169 | if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) | |
1170 | goto err; | |
1171 | if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) | |
1172 | goto err; | |
1173 | if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) | |
1174 | goto err; | |
1175 | if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) | |
1176 | goto err; | |
1177 | if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) | |
1178 | goto err; | |
1179 | if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) | |
1180 | goto err; | |
1181 | if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) | |
1182 | goto err; | |
1183 | if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) | |
1184 | goto err; | |
1185 | if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) | |
1186 | goto err; | |
1187 | if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) | |
1188 | goto err; | |
1189 | if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) | |
1190 | goto err; | |
1191 | if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) | |
1192 | goto err; | |
1193 | if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) | |
1194 | goto err; | |
e415c689 | 1195 | |
e415c689 | 1196 | return 0; |
27d40321 | 1197 | |
e415c689 MA |
1198 | err: |
1199 | dprintk(FE_ERROR, 1, "I/O error"); | |
1200 | return -1; | |
1201 | } | |
1202 | ||
1203 | static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) | |
1204 | { | |
1205 | u32 reg; | |
1206 | ||
1207 | switch (state->demod) { | |
1208 | case STV090x_DEMODULATOR_0: | |
97f7a2ae | 1209 | mutex_lock(&state->internal->demod_lock); |
e415c689 MA |
1210 | reg = stv090x_read_reg(state, STV090x_STOPCLK2); |
1211 | STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); | |
1212 | if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) | |
1213 | goto err; | |
97f7a2ae | 1214 | mutex_unlock(&state->internal->demod_lock); |
e415c689 MA |
1215 | break; |
1216 | ||
1217 | case STV090x_DEMODULATOR_1: | |
97f7a2ae | 1218 | mutex_lock(&state->internal->demod_lock); |
e415c689 MA |
1219 | reg = stv090x_read_reg(state, STV090x_STOPCLK2); |
1220 | STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); | |
1221 | if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) | |
1222 | goto err; | |
97f7a2ae | 1223 | mutex_unlock(&state->internal->demod_lock); |
e415c689 MA |
1224 | break; |
1225 | ||
1226 | default: | |
1227 | dprintk(FE_ERROR, 1, "Wrong demodulator!"); | |
1228 | break; | |
1229 | } | |
1230 | return 0; | |
1231 | err: | |
97f7a2ae | 1232 | mutex_unlock(&state->internal->demod_lock); |
e415c689 MA |
1233 | dprintk(FE_ERROR, 1, "I/O error"); |
1234 | return -1; | |
1235 | } | |
1236 | ||
27d40321 MA |
1237 | static int stv090x_dvbs_track_crl(struct stv090x_state *state) |
1238 | { | |
97f7a2ae | 1239 | if (state->internal->dev_ver >= 0x30) { |
27d40321 MA |
1240 | /* Set ACLC BCLC optimised value vs SR */ |
1241 | if (state->srate >= 15000000) { | |
1242 | if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) | |
1243 | goto err; | |
1244 | if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) | |
1245 | goto err; | |
1246 | } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { | |
1247 | if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) | |
1248 | goto err; | |
1249 | if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) | |
1250 | goto err; | |
1251 | } else if (state->srate < 7000000) { | |
1252 | if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) | |
1253 | goto err; | |
1254 | if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) | |
1255 | goto err; | |
1256 | } | |
1257 | ||
1258 | } else { | |
1259 | /* Cut 2.0 */ | |
1260 | if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) | |
1261 | goto err; | |
1262 | if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) | |
1263 | goto err; | |
1264 | } | |
1265 | return 0; | |
1266 | err: | |
1267 | dprintk(FE_ERROR, 1, "I/O error"); | |
1268 | return -1; | |
1269 | } | |
1270 | ||
e415c689 MA |
1271 | static int stv090x_delivery_search(struct stv090x_state *state) |
1272 | { | |
1273 | u32 reg; | |
1274 | ||
1275 | switch (state->search_mode) { | |
1276 | case STV090x_SEARCH_DVBS1: | |
1277 | case STV090x_SEARCH_DSS: | |
1278 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
1279 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); | |
1280 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); | |
1281 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1282 | goto err; | |
1283 | ||
27d40321 MA |
1284 | /* Activate Viterbi decoder in legacy search, |
1285 | * do not use FRESVIT1, might impact VITERBI2 | |
1286 | */ | |
e415c689 MA |
1287 | if (stv090x_vitclk_ctl(state, 0) < 0) |
1288 | goto err; | |
1289 | ||
27d40321 | 1290 | if (stv090x_dvbs_track_crl(state) < 0) |
e415c689 | 1291 | goto err; |
27d40321 | 1292 | |
e415c689 MA |
1293 | if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ |
1294 | goto err; | |
1295 | ||
27d40321 MA |
1296 | if (stv090x_set_vit_thacq(state) < 0) |
1297 | goto err; | |
1298 | if (stv090x_set_viterbi(state) < 0) | |
1299 | goto err; | |
e415c689 MA |
1300 | break; |
1301 | ||
1302 | case STV090x_SEARCH_DVBS2: | |
1303 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
1304 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); | |
1305 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); | |
1306 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1307 | goto err; | |
1308 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); | |
1309 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); | |
1310 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1311 | goto err; | |
1312 | ||
1313 | if (stv090x_vitclk_ctl(state, 1) < 0) | |
1314 | goto err; | |
1315 | ||
1316 | if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ | |
1317 | goto err; | |
1318 | if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) | |
1319 | goto err; | |
27d40321 | 1320 | |
97f7a2ae | 1321 | if (state->internal->dev_ver <= 0x20) { |
27d40321 MA |
1322 | /* enable S2 carrier loop */ |
1323 | if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) | |
1324 | goto err; | |
1325 | } else { | |
1326 | /* > Cut 3: Stop carrier 3 */ | |
1327 | if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) | |
1328 | goto err; | |
1329 | } | |
e415c689 MA |
1330 | |
1331 | if (state->demod_mode != STV090x_SINGLE) { | |
27d40321 MA |
1332 | /* Cut 2: enable link during search */ |
1333 | if (stv090x_activate_modcod(state) < 0) | |
1334 | goto err; | |
1335 | } else { | |
1336 | /* Single demodulator | |
1337 | * Authorize SHORT and LONG frames, | |
1338 | * QPSK, 8PSK, 16APSK and 32APSK | |
1339 | */ | |
1340 | if (stv090x_activate_modcod_single(state) < 0) | |
1341 | goto err; | |
e415c689 | 1342 | } |
27d40321 | 1343 | |
7b035da9 AR |
1344 | if (stv090x_set_vit_thtracq(state) < 0) |
1345 | goto err; | |
e415c689 MA |
1346 | break; |
1347 | ||
1348 | case STV090x_SEARCH_AUTO: | |
1349 | default: | |
27d40321 | 1350 | /* enable DVB-S2 and DVB-S2 in Auto MODE */ |
e415c689 | 1351 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); |
b79c6df7 AR |
1352 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); |
1353 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); | |
1354 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1355 | goto err; | |
e415c689 MA |
1356 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); |
1357 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); | |
1358 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1359 | goto err; | |
1360 | ||
4e58a682 | 1361 | if (stv090x_vitclk_ctl(state, 0) < 0) |
e415c689 MA |
1362 | goto err; |
1363 | ||
27d40321 | 1364 | if (stv090x_dvbs_track_crl(state) < 0) |
e415c689 MA |
1365 | goto err; |
1366 | ||
97f7a2ae | 1367 | if (state->internal->dev_ver <= 0x20) { |
27d40321 MA |
1368 | /* enable S2 carrier loop */ |
1369 | if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) | |
1370 | goto err; | |
1371 | } else { | |
1372 | /* > Cut 3: Stop carrier 3 */ | |
1373 | if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) | |
1374 | goto err; | |
1375 | } | |
1376 | ||
e415c689 | 1377 | if (state->demod_mode != STV090x_SINGLE) { |
27d40321 MA |
1378 | /* Cut 2: enable link during search */ |
1379 | if (stv090x_activate_modcod(state) < 0) | |
1380 | goto err; | |
1381 | } else { | |
1382 | /* Single demodulator | |
1383 | * Authorize SHORT and LONG frames, | |
1384 | * QPSK, 8PSK, 16APSK and 32APSK | |
1385 | */ | |
1386 | if (stv090x_activate_modcod_single(state) < 0) | |
1387 | goto err; | |
e415c689 | 1388 | } |
27d40321 | 1389 | |
7b035da9 AR |
1390 | if (stv090x_set_vit_thacq(state) < 0) |
1391 | goto err; | |
27d40321 MA |
1392 | |
1393 | if (stv090x_set_viterbi(state) < 0) | |
1394 | goto err; | |
e415c689 MA |
1395 | break; |
1396 | } | |
1397 | return 0; | |
1398 | err: | |
1399 | dprintk(FE_ERROR, 1, "I/O error"); | |
1400 | return -1; | |
1401 | } | |
1402 | ||
1403 | static int stv090x_start_search(struct stv090x_state *state) | |
1404 | { | |
27d40321 MA |
1405 | u32 reg, freq_abs; |
1406 | s16 freq; | |
e415c689 | 1407 | |
27d40321 | 1408 | /* Reset demodulator */ |
e415c689 MA |
1409 | reg = STV090x_READ_DEMOD(state, DMDISTATE); |
1410 | STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); | |
1411 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) | |
1412 | goto err; | |
1413 | ||
97f7a2ae | 1414 | if (state->internal->dev_ver <= 0x20) { |
27d40321 MA |
1415 | if (state->srate <= 5000000) { |
1416 | if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) | |
1417 | goto err; | |
1418 | if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) | |
1419 | goto err; | |
b671a8d4 | 1420 | if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) |
27d40321 MA |
1421 | goto err; |
1422 | if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) | |
1423 | goto err; | |
1424 | if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) | |
1425 | goto err; | |
1426 | ||
25985edc | 1427 | /*enlarge the timing bandwidth for Low SR*/ |
27d40321 MA |
1428 | if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) |
1429 | goto err; | |
1430 | } else { | |
1431 | /* If the symbol rate is >5 Msps | |
1432 | Set The carrier search up and low to auto mode */ | |
1433 | if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) | |
1434 | goto err; | |
25985edc | 1435 | /*reduce the timing bandwidth for high SR*/ |
27d40321 MA |
1436 | if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) |
1437 | goto err; | |
1438 | } | |
1439 | } else { | |
1440 | /* >= Cut 3 */ | |
1441 | if (state->srate <= 5000000) { | |
25985edc | 1442 | /* enlarge the timing bandwidth for Low SR */ |
27d40321 MA |
1443 | STV090x_WRITE_DEMOD(state, RTCS2, 0x68); |
1444 | } else { | |
25985edc | 1445 | /* reduce timing bandwidth for high SR */ |
27d40321 MA |
1446 | STV090x_WRITE_DEMOD(state, RTCS2, 0x44); |
1447 | } | |
1448 | ||
1449 | /* Set CFR min and max to manual mode */ | |
1450 | STV090x_WRITE_DEMOD(state, CARCFG, 0x46); | |
1451 | ||
1452 | if (state->algo == STV090x_WARM_SEARCH) { | |
1453 | /* WARM Start | |
1454 | * CFR min = -1MHz, | |
1455 | * CFR max = +1MHz | |
1456 | */ | |
1457 | freq_abs = 1000 << 16; | |
97f7a2ae | 1458 | freq_abs /= (state->internal->mclk / 1000); |
27d40321 MA |
1459 | freq = (s16) freq_abs; |
1460 | } else { | |
1461 | /* COLD Start | |
1462 | * CFR min =- (SearchRange / 2 + 600KHz) | |
1463 | * CFR max = +(SearchRange / 2 + 600KHz) | |
1464 | * (600KHz for the tuner step size) | |
1465 | */ | |
1466 | freq_abs = (state->search_range / 2000) + 600; | |
1467 | freq_abs = freq_abs << 16; | |
97f7a2ae | 1468 | freq_abs /= (state->internal->mclk / 1000); |
27d40321 MA |
1469 | freq = (s16) freq_abs; |
1470 | } | |
1471 | ||
1472 | if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) | |
e415c689 | 1473 | goto err; |
b671a8d4 | 1474 | if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) |
e415c689 MA |
1475 | goto err; |
1476 | ||
27d40321 MA |
1477 | freq *= -1; |
1478 | ||
1479 | if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) | |
e415c689 | 1480 | goto err; |
27d40321 | 1481 | if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) |
e415c689 | 1482 | goto err; |
27d40321 | 1483 | |
e415c689 | 1484 | } |
27d40321 | 1485 | |
e415c689 MA |
1486 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) |
1487 | goto err; | |
1488 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) | |
1489 | goto err; | |
1490 | ||
97f7a2ae | 1491 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
1492 | if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) |
1493 | goto err; | |
1494 | if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) | |
1495 | goto err; | |
1496 | ||
187e7d3b MCC |
1497 | if ((state->search_mode == STV090x_SEARCH_DVBS1) || |
1498 | (state->search_mode == STV090x_SEARCH_DSS) || | |
e415c689 MA |
1499 | (state->search_mode == STV090x_SEARCH_AUTO)) { |
1500 | ||
1501 | if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) | |
1502 | goto err; | |
1503 | if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) | |
1504 | goto err; | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) | |
1509 | goto err; | |
1510 | if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) | |
1511 | goto err; | |
1512 | if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) | |
1513 | goto err; | |
1514 | ||
1515 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
1516 | STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); | |
1517 | STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); | |
1518 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1519 | goto err; | |
1520 | reg = STV090x_READ_DEMOD(state, DMDCFG2); | |
1521 | STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); | |
1522 | if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) | |
1523 | goto err; | |
1524 | ||
7b035da9 AR |
1525 | if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) |
1526 | goto err; | |
1527 | ||
97f7a2ae | 1528 | if (state->internal->dev_ver >= 0x20) { |
27d40321 MA |
1529 | /*Frequency offset detector setting*/ |
1530 | if (state->srate < 2000000) { | |
97f7a2ae | 1531 | if (state->internal->dev_ver <= 0x20) { |
27d40321 MA |
1532 | /* Cut 2 */ |
1533 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) | |
1534 | goto err; | |
1535 | } else { | |
7b035da9 | 1536 | /* Cut 3 */ |
27d40321 MA |
1537 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) |
1538 | goto err; | |
1539 | } | |
1540 | if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) | |
1541 | goto err; | |
a4978a83 | 1542 | } else if (state->srate < 10000000) { |
e415c689 MA |
1543 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) |
1544 | goto err; | |
7b035da9 AR |
1545 | if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) |
1546 | goto err; | |
e415c689 MA |
1547 | } else { |
1548 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) | |
1549 | goto err; | |
7b035da9 AR |
1550 | if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) |
1551 | goto err; | |
e415c689 MA |
1552 | } |
1553 | } else { | |
1554 | if (state->srate < 10000000) { | |
1555 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) | |
1556 | goto err; | |
1557 | } else { | |
1558 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) | |
1559 | goto err; | |
1560 | } | |
1561 | } | |
1562 | ||
1563 | switch (state->algo) { | |
27d40321 MA |
1564 | case STV090x_WARM_SEARCH: |
1565 | /* The symbol rate and the exact | |
1566 | * carrier Frequency are known | |
1567 | */ | |
e415c689 MA |
1568 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) |
1569 | goto err; | |
1570 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) | |
1571 | goto err; | |
1572 | break; | |
1573 | ||
27d40321 MA |
1574 | case STV090x_COLD_SEARCH: |
1575 | /* The symbol rate is known */ | |
e415c689 MA |
1576 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) |
1577 | goto err; | |
1578 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) | |
1579 | goto err; | |
1580 | break; | |
1581 | ||
1582 | default: | |
1583 | break; | |
1584 | } | |
1585 | return 0; | |
1586 | err: | |
1587 | dprintk(FE_ERROR, 1, "I/O error"); | |
1588 | return -1; | |
1589 | } | |
1590 | ||
1591 | static int stv090x_get_agc2_min_level(struct stv090x_state *state) | |
1592 | { | |
b4a4248d | 1593 | u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; |
e415c689 MA |
1594 | s32 i, j, steps, dir; |
1595 | ||
1596 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) | |
1597 | goto err; | |
1598 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
7b035da9 AR |
1599 | STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); |
1600 | STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); | |
e415c689 MA |
1601 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) |
1602 | goto err; | |
1603 | ||
1604 | if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ | |
1605 | goto err; | |
1606 | if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) | |
1607 | goto err; | |
1608 | if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ | |
1609 | goto err; | |
1610 | if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) | |
1611 | goto err; | |
1612 | if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ | |
1613 | goto err; | |
27d40321 MA |
1614 | if (stv090x_set_srate(state, 1000000) < 0) |
1615 | goto err; | |
e415c689 | 1616 | |
7b035da9 AR |
1617 | steps = state->search_range / 1000000; |
1618 | if (steps <= 0) | |
e415c689 MA |
1619 | steps = 1; |
1620 | ||
1621 | dir = 1; | |
97f7a2ae | 1622 | freq_step = (1000000 * 256) / (state->internal->mclk / 256); |
e415c689 MA |
1623 | freq_init = 0; |
1624 | ||
1625 | for (i = 0; i < steps; i++) { | |
1626 | if (dir > 0) | |
1627 | freq_init = freq_init + (freq_step * i); | |
1628 | else | |
1629 | freq_init = freq_init - (freq_step * i); | |
1630 | ||
b671a8d4 | 1631 | dir *= -1; |
e415c689 MA |
1632 | |
1633 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ | |
1634 | goto err; | |
1635 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) | |
1636 | goto err; | |
1637 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) | |
1638 | goto err; | |
1639 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ | |
1640 | goto err; | |
1641 | msleep(10); | |
b4a4248d AR |
1642 | |
1643 | agc2 = 0; | |
e415c689 | 1644 | for (j = 0; j < 10; j++) { |
b4a4248d AR |
1645 | agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | |
1646 | STV090x_READ_DEMOD(state, AGC2I0); | |
e415c689 MA |
1647 | } |
1648 | agc2 /= 10; | |
b4a4248d | 1649 | if (agc2 < agc2_min) |
e415c689 MA |
1650 | agc2_min = agc2; |
1651 | } | |
1652 | ||
1653 | return agc2_min; | |
1654 | err: | |
1655 | dprintk(FE_ERROR, 1, "I/O error"); | |
1656 | return -1; | |
1657 | } | |
1658 | ||
1659 | static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) | |
1660 | { | |
1661 | u8 r3, r2, r1, r0; | |
1662 | s32 srate, int_1, int_2, tmp_1, tmp_2; | |
e415c689 MA |
1663 | |
1664 | r3 = STV090x_READ_DEMOD(state, SFR3); | |
1665 | r2 = STV090x_READ_DEMOD(state, SFR2); | |
1666 | r1 = STV090x_READ_DEMOD(state, SFR1); | |
1667 | r0 = STV090x_READ_DEMOD(state, SFR0); | |
1668 | ||
1669 | srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); | |
1670 | ||
f430fff1 MA |
1671 | int_1 = clk >> 16; |
1672 | int_2 = srate >> 16; | |
e415c689 | 1673 | |
f430fff1 MA |
1674 | tmp_1 = clk % 0x10000; |
1675 | tmp_2 = srate % 0x10000; | |
e415c689 MA |
1676 | |
1677 | srate = (int_1 * int_2) + | |
f430fff1 MA |
1678 | ((int_1 * tmp_2) >> 16) + |
1679 | ((int_2 * tmp_1) >> 16); | |
e415c689 MA |
1680 | |
1681 | return srate; | |
1682 | } | |
1683 | ||
1684 | static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) | |
1685 | { | |
1686 | struct dvb_frontend *fe = &state->frontend; | |
1687 | ||
1688 | int tmg_lock = 0, i; | |
1689 | s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; | |
1690 | u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; | |
b4a4248d AR |
1691 | u32 agc2th; |
1692 | ||
97f7a2ae | 1693 | if (state->internal->dev_ver >= 0x30) |
b4a4248d AR |
1694 | agc2th = 0x2e00; |
1695 | else | |
1696 | agc2th = 0x1f00; | |
e415c689 MA |
1697 | |
1698 | reg = STV090x_READ_DEMOD(state, DMDISTATE); | |
1699 | STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ | |
1700 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) | |
1701 | goto err; | |
1702 | if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) | |
1703 | goto err; | |
7b035da9 AR |
1704 | if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) |
1705 | goto err; | |
e415c689 MA |
1706 | if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) |
1707 | goto err; | |
1708 | if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) | |
1709 | goto err; | |
1710 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
1711 | STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); | |
7b035da9 | 1712 | STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); |
e415c689 MA |
1713 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) |
1714 | goto err; | |
1715 | ||
1716 | if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) | |
1717 | goto err; | |
1718 | if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) | |
1719 | goto err; | |
1720 | if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) | |
1721 | goto err; | |
1722 | if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) | |
1723 | goto err; | |
1724 | if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) | |
1725 | goto err; | |
b4a4248d | 1726 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) |
e415c689 MA |
1727 | goto err; |
1728 | ||
97f7a2ae | 1729 | if (state->internal->dev_ver >= 0x30) { |
27d40321 | 1730 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) |
e415c689 | 1731 | goto err; |
7b035da9 | 1732 | if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) |
e415c689 | 1733 | goto err; |
27d40321 | 1734 | |
97f7a2ae | 1735 | } else if (state->internal->dev_ver >= 0x20) { |
27d40321 | 1736 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) |
e415c689 | 1737 | goto err; |
27d40321 | 1738 | if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) |
e415c689 MA |
1739 | goto err; |
1740 | } | |
1741 | ||
1742 | if (state->srate <= 2000000) | |
1743 | car_step = 1000; | |
1744 | else if (state->srate <= 5000000) | |
1745 | car_step = 2000; | |
1746 | else if (state->srate <= 12000000) | |
1747 | car_step = 3000; | |
1748 | else | |
1749 | car_step = 5000; | |
1750 | ||
1751 | steps = -1 + ((state->search_range / 1000) / car_step); | |
1752 | steps /= 2; | |
1753 | steps = (2 * steps) + 1; | |
1754 | if (steps < 0) | |
1755 | steps = 1; | |
1756 | else if (steps > 10) { | |
1757 | steps = 11; | |
1758 | car_step = (state->search_range / 1000) / 10; | |
1759 | } | |
1760 | cur_step = 0; | |
1761 | dir = 1; | |
1762 | freq = state->frequency; | |
1763 | ||
1764 | while ((!tmg_lock) && (cur_step < steps)) { | |
1765 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ | |
1766 | goto err; | |
7b035da9 AR |
1767 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) |
1768 | goto err; | |
1769 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) | |
1770 | goto err; | |
1771 | if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) | |
1772 | goto err; | |
1773 | if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) | |
1774 | goto err; | |
1775 | /* trigger acquisition */ | |
1776 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) | |
e415c689 MA |
1777 | goto err; |
1778 | msleep(50); | |
1779 | for (i = 0; i < 10; i++) { | |
1780 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
1781 | if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) | |
1782 | tmg_cpt++; | |
b4a4248d AR |
1783 | agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | |
1784 | STV090x_READ_DEMOD(state, AGC2I0); | |
e415c689 MA |
1785 | } |
1786 | agc2 /= 10; | |
97f7a2ae | 1787 | srate_coarse = stv090x_get_srate(state, state->internal->mclk); |
e415c689 MA |
1788 | cur_step++; |
1789 | dir *= -1; | |
b4a4248d AR |
1790 | if ((tmg_cpt >= 5) && (agc2 < agc2th) && |
1791 | (srate_coarse < 50000000) && (srate_coarse > 850000)) | |
e415c689 MA |
1792 | tmg_lock = 1; |
1793 | else if (cur_step < steps) { | |
1794 | if (dir > 0) | |
1795 | freq += cur_step * car_step; | |
1796 | else | |
1797 | freq -= cur_step * car_step; | |
1798 | ||
1799 | /* Setup tuner */ | |
19c4ee58 | 1800 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 1801 | goto err; |
e415c689 | 1802 | |
27d40321 | 1803 | if (state->config->tuner_set_frequency) { |
a4978a83 | 1804 | if (state->config->tuner_set_frequency(fe, freq) < 0) |
2c1f750b | 1805 | goto err_gateoff; |
27d40321 | 1806 | } |
e415c689 | 1807 | |
27d40321 MA |
1808 | if (state->config->tuner_set_bandwidth) { |
1809 | if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) | |
2c1f750b | 1810 | goto err_gateoff; |
27d40321 MA |
1811 | } |
1812 | ||
19c4ee58 | 1813 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 1814 | goto err; |
e415c689 | 1815 | |
e415c689 | 1816 | msleep(50); |
e415c689 | 1817 | |
19c4ee58 | 1818 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 MA |
1819 | goto err; |
1820 | ||
1821 | if (state->config->tuner_get_status) { | |
1822 | if (state->config->tuner_get_status(fe, ®) < 0) | |
2c1f750b | 1823 | goto err_gateoff; |
27d40321 | 1824 | } |
e415c689 MA |
1825 | |
1826 | if (reg) | |
1827 | dprintk(FE_DEBUG, 1, "Tuner phase locked"); | |
1828 | else | |
1829 | dprintk(FE_DEBUG, 1, "Tuner unlocked"); | |
1830 | ||
19c4ee58 | 1831 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 1832 | goto err; |
e415c689 MA |
1833 | |
1834 | } | |
1835 | } | |
1836 | if (!tmg_lock) | |
1837 | srate_coarse = 0; | |
1838 | else | |
97f7a2ae | 1839 | srate_coarse = stv090x_get_srate(state, state->internal->mclk); |
e415c689 MA |
1840 | |
1841 | return srate_coarse; | |
2c1f750b OE |
1842 | |
1843 | err_gateoff: | |
19c4ee58 | 1844 | stv090x_i2c_gate_ctrl(state, 0); |
e415c689 MA |
1845 | err: |
1846 | dprintk(FE_ERROR, 1, "I/O error"); | |
1847 | return -1; | |
1848 | } | |
1849 | ||
1850 | static u32 stv090x_srate_srch_fine(struct stv090x_state *state) | |
1851 | { | |
1852 | u32 srate_coarse, freq_coarse, sym, reg; | |
1853 | ||
97f7a2ae | 1854 | srate_coarse = stv090x_get_srate(state, state->internal->mclk); |
e415c689 MA |
1855 | freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; |
1856 | freq_coarse |= STV090x_READ_DEMOD(state, CFR1); | |
1857 | sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ | |
1858 | ||
1859 | if (sym < state->srate) | |
1860 | srate_coarse = 0; | |
1861 | else { | |
1862 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ | |
1863 | goto err; | |
7b035da9 | 1864 | if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) |
e415c689 MA |
1865 | goto err; |
1866 | if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) | |
1867 | goto err; | |
1868 | if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) | |
1869 | goto err; | |
1870 | if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) | |
1871 | goto err; | |
1872 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
1873 | STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); | |
1874 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
1875 | goto err; | |
1876 | ||
b4a4248d AR |
1877 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) |
1878 | goto err; | |
1879 | ||
97f7a2ae | 1880 | if (state->internal->dev_ver >= 0x30) { |
27d40321 | 1881 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) |
e415c689 | 1882 | goto err; |
97f7a2ae | 1883 | } else if (state->internal->dev_ver >= 0x20) { |
27d40321 | 1884 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) |
e415c689 MA |
1885 | goto err; |
1886 | } | |
1887 | ||
1888 | if (srate_coarse > 3000000) { | |
1889 | sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ | |
1890 | sym = (sym / 1000) * 65536; | |
97f7a2ae | 1891 | sym /= (state->internal->mclk / 1000); |
e415c689 MA |
1892 | if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) |
1893 | goto err; | |
1894 | if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) | |
1895 | goto err; | |
1896 | sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ | |
1897 | sym = (sym / 1000) * 65536; | |
97f7a2ae | 1898 | sym /= (state->internal->mclk / 1000); |
e415c689 MA |
1899 | if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) |
1900 | goto err; | |
1901 | if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) | |
1902 | goto err; | |
1903 | sym = (srate_coarse / 1000) * 65536; | |
97f7a2ae | 1904 | sym /= (state->internal->mclk / 1000); |
e415c689 MA |
1905 | if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) |
1906 | goto err; | |
1907 | if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) | |
1908 | goto err; | |
1909 | } else { | |
1910 | sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ | |
1911 | sym = (sym / 100) * 65536; | |
97f7a2ae | 1912 | sym /= (state->internal->mclk / 100); |
e415c689 MA |
1913 | if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) |
1914 | goto err; | |
1915 | if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) | |
1916 | goto err; | |
1917 | sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ | |
1918 | sym = (sym / 100) * 65536; | |
97f7a2ae | 1919 | sym /= (state->internal->mclk / 100); |
e415c689 MA |
1920 | if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) |
1921 | goto err; | |
1922 | if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) | |
1923 | goto err; | |
1924 | sym = (srate_coarse / 100) * 65536; | |
97f7a2ae | 1925 | sym /= (state->internal->mclk / 100); |
e415c689 MA |
1926 | if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) |
1927 | goto err; | |
1928 | if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) | |
1929 | goto err; | |
1930 | } | |
1931 | if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) | |
1932 | goto err; | |
1933 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) | |
1934 | goto err; | |
1935 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) | |
1936 | goto err; | |
1937 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ | |
1938 | goto err; | |
1939 | } | |
1940 | ||
1941 | return srate_coarse; | |
1942 | ||
1943 | err: | |
1944 | dprintk(FE_ERROR, 1, "I/O error"); | |
1945 | return -1; | |
1946 | } | |
1947 | ||
1948 | static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) | |
1949 | { | |
1950 | s32 timer = 0, lock = 0; | |
1951 | u32 reg; | |
1952 | u8 stat; | |
1953 | ||
1954 | while ((timer < timeout) && (!lock)) { | |
1955 | reg = STV090x_READ_DEMOD(state, DMDSTATE); | |
1956 | stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); | |
1957 | ||
1958 | switch (stat) { | |
1959 | case 0: /* searching */ | |
1960 | case 1: /* first PLH detected */ | |
1961 | default: | |
1962 | dprintk(FE_DEBUG, 1, "Demodulator searching .."); | |
1963 | lock = 0; | |
1964 | break; | |
1965 | case 2: /* DVB-S2 mode */ | |
1966 | case 3: /* DVB-S1/legacy mode */ | |
1967 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
1968 | lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); | |
1969 | break; | |
1970 | } | |
1971 | ||
1972 | if (!lock) | |
1973 | msleep(10); | |
1974 | else | |
1975 | dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); | |
1976 | ||
1977 | timer += 10; | |
1978 | } | |
1979 | return lock; | |
1980 | } | |
1981 | ||
1982 | static int stv090x_blind_search(struct stv090x_state *state) | |
1983 | { | |
1984 | u32 agc2, reg, srate_coarse; | |
a4978a83 | 1985 | s32 cpt_fail, agc2_ovflw, i; |
e415c689 | 1986 | u8 k_ref, k_max, k_min; |
690c79ae AM |
1987 | int coarse_fail = 0; |
1988 | int lock; | |
e415c689 | 1989 | |
7b035da9 AR |
1990 | k_max = 110; |
1991 | k_min = 10; | |
e415c689 MA |
1992 | |
1993 | agc2 = stv090x_get_agc2_min_level(state); | |
1994 | ||
97f7a2ae | 1995 | if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { |
e415c689 MA |
1996 | lock = 0; |
1997 | } else { | |
27d40321 | 1998 | |
97f7a2ae | 1999 | if (state->internal->dev_ver <= 0x20) { |
27d40321 | 2000 | if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) |
e415c689 | 2001 | goto err; |
27d40321 MA |
2002 | } else { |
2003 | /* > Cut 3 */ | |
2004 | if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) | |
e415c689 MA |
2005 | goto err; |
2006 | } | |
2007 | ||
e415c689 MA |
2008 | if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) |
2009 | goto err; | |
27d40321 | 2010 | |
97f7a2ae | 2011 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2012 | if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) |
2013 | goto err; | |
2014 | if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) | |
2015 | goto err; | |
2016 | if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) | |
2017 | goto err; | |
2018 | if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ | |
2019 | goto err; | |
2020 | } | |
2021 | ||
2022 | k_ref = k_max; | |
2023 | do { | |
2024 | if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) | |
2025 | goto err; | |
2026 | if (stv090x_srate_srch_coarse(state) != 0) { | |
2027 | srate_coarse = stv090x_srate_srch_fine(state); | |
2028 | if (srate_coarse != 0) { | |
2029 | stv090x_get_lock_tmg(state); | |
a4978a83 AR |
2030 | lock = stv090x_get_dmdlock(state, |
2031 | state->DemodTimeout); | |
e415c689 MA |
2032 | } else { |
2033 | lock = 0; | |
2034 | } | |
2035 | } else { | |
2036 | cpt_fail = 0; | |
2037 | agc2_ovflw = 0; | |
2038 | for (i = 0; i < 10; i++) { | |
b4a4248d AR |
2039 | agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | |
2040 | STV090x_READ_DEMOD(state, AGC2I0); | |
e415c689 MA |
2041 | if (agc2 >= 0xff00) |
2042 | agc2_ovflw++; | |
2043 | reg = STV090x_READ_DEMOD(state, DSTATUS2); | |
2044 | if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && | |
2045 | (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) | |
2046 | ||
2047 | cpt_fail++; | |
2048 | } | |
2049 | if ((cpt_fail > 7) || (agc2_ovflw > 7)) | |
2050 | coarse_fail = 1; | |
2051 | ||
2052 | lock = 0; | |
2053 | } | |
7b035da9 | 2054 | k_ref -= 20; |
e415c689 MA |
2055 | } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); |
2056 | } | |
2057 | ||
2058 | return lock; | |
2059 | ||
2060 | err: | |
2061 | dprintk(FE_ERROR, 1, "I/O error"); | |
2062 | return -1; | |
2063 | } | |
2064 | ||
2065 | static int stv090x_chk_tmg(struct stv090x_state *state) | |
2066 | { | |
2067 | u32 reg; | |
27d40321 | 2068 | s32 tmg_cpt = 0, i; |
e415c689 | 2069 | u8 freq, tmg_thh, tmg_thl; |
08c45cd5 | 2070 | int tmg_lock = 0; |
e415c689 MA |
2071 | |
2072 | freq = STV090x_READ_DEMOD(state, CARFREQ); | |
2073 | tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); | |
2074 | tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); | |
2075 | if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) | |
2076 | goto err; | |
2077 | if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) | |
2078 | goto err; | |
2079 | ||
2080 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
2081 | STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ | |
2082 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
2083 | goto err; | |
2084 | if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) | |
2085 | goto err; | |
2086 | ||
2087 | if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) | |
2088 | goto err; | |
2089 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) | |
2090 | goto err; | |
2091 | ||
2092 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ | |
2093 | goto err; | |
2094 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) | |
2095 | goto err; | |
2096 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) | |
2097 | goto err; | |
2098 | ||
2099 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ | |
2100 | goto err; | |
2101 | msleep(10); | |
2102 | ||
2103 | for (i = 0; i < 10; i++) { | |
2104 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
2105 | if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) | |
2106 | tmg_cpt++; | |
2107 | msleep(1); | |
2108 | } | |
2109 | if (tmg_cpt >= 3) | |
2110 | tmg_lock = 1; | |
2111 | ||
2112 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) | |
2113 | goto err; | |
2114 | if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ | |
2115 | goto err; | |
2116 | if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ | |
2117 | goto err; | |
2118 | ||
2119 | if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) | |
2120 | goto err; | |
2121 | if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) | |
2122 | goto err; | |
2123 | if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) | |
2124 | goto err; | |
2125 | ||
2126 | return tmg_lock; | |
2127 | ||
2128 | err: | |
2129 | dprintk(FE_ERROR, 1, "I/O error"); | |
2130 | return -1; | |
2131 | } | |
2132 | ||
2133 | static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) | |
2134 | { | |
2135 | struct dvb_frontend *fe = &state->frontend; | |
2136 | ||
2137 | u32 reg; | |
2138 | s32 car_step, steps, cur_step, dir, freq, timeout_lock; | |
2139 | int lock = 0; | |
2140 | ||
2141 | if (state->srate >= 10000000) | |
2142 | timeout_lock = timeout_dmd / 3; | |
2143 | else | |
2144 | timeout_lock = timeout_dmd / 2; | |
2145 | ||
2146 | lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ | |
2147 | if (!lock) { | |
2148 | if (state->srate >= 10000000) { | |
2149 | if (stv090x_chk_tmg(state)) { | |
2150 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) | |
2151 | goto err; | |
2152 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) | |
2153 | goto err; | |
2154 | lock = stv090x_get_dmdlock(state, timeout_dmd); | |
2155 | } else { | |
2156 | lock = 0; | |
2157 | } | |
2158 | } else { | |
2159 | if (state->srate <= 4000000) | |
2160 | car_step = 1000; | |
2161 | else if (state->srate <= 7000000) | |
2162 | car_step = 2000; | |
2163 | else if (state->srate <= 10000000) | |
2164 | car_step = 3000; | |
2165 | else | |
2166 | car_step = 5000; | |
2167 | ||
2168 | steps = (state->search_range / 1000) / car_step; | |
2169 | steps /= 2; | |
2170 | steps = 2 * (steps + 1); | |
2171 | if (steps < 0) | |
2172 | steps = 2; | |
2173 | else if (steps > 12) | |
2174 | steps = 12; | |
2175 | ||
2176 | cur_step = 1; | |
2177 | dir = 1; | |
2178 | ||
2179 | if (!lock) { | |
2180 | freq = state->frequency; | |
2181 | state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; | |
2182 | while ((cur_step <= steps) && (!lock)) { | |
2183 | if (dir > 0) | |
2184 | freq += cur_step * car_step; | |
2185 | else | |
2186 | freq -= cur_step * car_step; | |
2187 | ||
2188 | /* Setup tuner */ | |
19c4ee58 | 2189 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 2190 | goto err; |
e415c689 | 2191 | |
27d40321 | 2192 | if (state->config->tuner_set_frequency) { |
a4978a83 | 2193 | if (state->config->tuner_set_frequency(fe, freq) < 0) |
2c1f750b | 2194 | goto err_gateoff; |
27d40321 | 2195 | } |
e415c689 | 2196 | |
27d40321 MA |
2197 | if (state->config->tuner_set_bandwidth) { |
2198 | if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) | |
2c1f750b | 2199 | goto err_gateoff; |
27d40321 | 2200 | } |
e415c689 | 2201 | |
19c4ee58 | 2202 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 2203 | goto err; |
e415c689 MA |
2204 | |
2205 | msleep(50); | |
2206 | ||
19c4ee58 | 2207 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 2208 | goto err; |
e415c689 | 2209 | |
27d40321 MA |
2210 | if (state->config->tuner_get_status) { |
2211 | if (state->config->tuner_get_status(fe, ®) < 0) | |
2c1f750b | 2212 | goto err_gateoff; |
27d40321 | 2213 | } |
e415c689 MA |
2214 | |
2215 | if (reg) | |
2216 | dprintk(FE_DEBUG, 1, "Tuner phase locked"); | |
2217 | else | |
2218 | dprintk(FE_DEBUG, 1, "Tuner unlocked"); | |
2219 | ||
19c4ee58 | 2220 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 2221 | goto err; |
e415c689 MA |
2222 | |
2223 | STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); | |
e415c689 MA |
2224 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) |
2225 | goto err; | |
2226 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) | |
2227 | goto err; | |
2228 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) | |
2229 | goto err; | |
2230 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) | |
2231 | goto err; | |
2232 | lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); | |
2233 | ||
2234 | dir *= -1; | |
2235 | cur_step++; | |
2236 | } | |
2237 | } | |
2238 | } | |
2239 | } | |
2240 | ||
2241 | return lock; | |
2242 | ||
2c1f750b | 2243 | err_gateoff: |
19c4ee58 | 2244 | stv090x_i2c_gate_ctrl(state, 0); |
e415c689 MA |
2245 | err: |
2246 | dprintk(FE_ERROR, 1, "I/O error"); | |
2247 | return -1; | |
2248 | } | |
2249 | ||
2250 | static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) | |
2251 | { | |
2252 | s32 timeout, inc, steps_max, srate, car_max; | |
2253 | ||
2254 | srate = state->srate; | |
2255 | car_max = state->search_range / 1000; | |
2f5914be | 2256 | car_max += car_max / 10; |
e415c689 | 2257 | car_max = 65536 * (car_max / 2); |
97f7a2ae | 2258 | car_max /= (state->internal->mclk / 1000); |
e415c689 MA |
2259 | |
2260 | if (car_max > 0x4000) | |
2261 | car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ | |
2262 | ||
2263 | inc = srate; | |
97f7a2ae | 2264 | inc /= state->internal->mclk / 1000; |
e415c689 MA |
2265 | inc *= 256; |
2266 | inc *= 256; | |
2267 | inc /= 1000; | |
2268 | ||
72982f76 | 2269 | switch (state->search_mode) { |
e415c689 MA |
2270 | case STV090x_SEARCH_DVBS1: |
2271 | case STV090x_SEARCH_DSS: | |
2272 | inc *= 3; /* freq step = 3% of srate */ | |
2273 | timeout = 20; | |
2274 | break; | |
2275 | ||
2276 | case STV090x_SEARCH_DVBS2: | |
2277 | inc *= 4; | |
2278 | timeout = 25; | |
2279 | break; | |
2280 | ||
2281 | case STV090x_SEARCH_AUTO: | |
2282 | default: | |
2283 | inc *= 3; | |
2284 | timeout = 25; | |
2285 | break; | |
2286 | } | |
2287 | inc /= 100; | |
2288 | if ((inc > car_max) || (inc < 0)) | |
2289 | inc = car_max / 2; /* increment <= 1/8 Mclk */ | |
2290 | ||
2291 | timeout *= 27500; /* 27.5 Msps reference */ | |
2292 | if (srate > 0) | |
2293 | timeout /= (srate / 1000); | |
2294 | ||
2295 | if ((timeout > 100) || (timeout < 0)) | |
2296 | timeout = 100; | |
2297 | ||
2298 | steps_max = (car_max / inc) + 1; /* min steps = 3 */ | |
2299 | if ((steps_max > 100) || (steps_max < 0)) { | |
2300 | steps_max = 100; /* max steps <= 100 */ | |
2301 | inc = car_max / steps_max; | |
2302 | } | |
2303 | *freq_inc = inc; | |
2304 | *timeout_sw = timeout; | |
2305 | *steps = steps_max; | |
2306 | ||
2307 | return 0; | |
2308 | } | |
2309 | ||
2310 | static int stv090x_chk_signal(struct stv090x_state *state) | |
2311 | { | |
2312 | s32 offst_car, agc2, car_max; | |
2313 | int no_signal; | |
2314 | ||
2315 | offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; | |
2316 | offst_car |= STV090x_READ_DEMOD(state, CFR1); | |
2f5914be | 2317 | offst_car = comp2(offst_car, 16); |
e415c689 MA |
2318 | |
2319 | agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; | |
2320 | agc2 |= STV090x_READ_DEMOD(state, AGC2I0); | |
2321 | car_max = state->search_range / 1000; | |
2322 | ||
2323 | car_max += (car_max / 10); /* 10% margin */ | |
2324 | car_max = (65536 * car_max / 2); | |
97f7a2ae | 2325 | car_max /= state->internal->mclk / 1000; |
e415c689 MA |
2326 | |
2327 | if (car_max > 0x4000) | |
2328 | car_max = 0x4000; | |
2329 | ||
2330 | if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { | |
2331 | no_signal = 1; | |
2332 | dprintk(FE_DEBUG, 1, "No Signal"); | |
2333 | } else { | |
2334 | no_signal = 0; | |
2335 | dprintk(FE_DEBUG, 1, "Found Signal"); | |
2336 | } | |
2337 | ||
2338 | return no_signal; | |
2339 | } | |
2340 | ||
2341 | static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) | |
2342 | { | |
2343 | int no_signal, lock = 0; | |
27d40321 | 2344 | s32 cpt_step = 0, offst_freq, car_max; |
e415c689 MA |
2345 | u32 reg; |
2346 | ||
2347 | car_max = state->search_range / 1000; | |
2348 | car_max += (car_max / 10); | |
2349 | car_max = (65536 * car_max / 2); | |
97f7a2ae | 2350 | car_max /= (state->internal->mclk / 1000); |
e415c689 MA |
2351 | if (car_max > 0x4000) |
2352 | car_max = 0x4000; | |
2353 | ||
2354 | if (zigzag) | |
2355 | offst_freq = 0; | |
2356 | else | |
2357 | offst_freq = -car_max + inc; | |
2358 | ||
e415c689 MA |
2359 | do { |
2360 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) | |
2361 | goto err; | |
2362 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) | |
2363 | goto err; | |
2364 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) | |
2365 | goto err; | |
2366 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) | |
2367 | goto err; | |
2368 | ||
2369 | reg = STV090x_READ_DEMOD(state, PDELCTRL1); | |
2370 | STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ | |
2371 | if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) | |
2372 | goto err; | |
2373 | ||
e415c689 MA |
2374 | if (zigzag) { |
2375 | if (offst_freq >= 0) | |
2376 | offst_freq = -offst_freq - 2 * inc; | |
2377 | else | |
2378 | offst_freq = -offst_freq; | |
2379 | } else { | |
2380 | offst_freq += 2 * inc; | |
2381 | } | |
2382 | ||
2f5914be AR |
2383 | cpt_step++; |
2384 | ||
e415c689 MA |
2385 | lock = stv090x_get_dmdlock(state, timeout); |
2386 | no_signal = stv090x_chk_signal(state); | |
2387 | ||
2388 | } while ((!lock) && | |
2389 | (!no_signal) && | |
2390 | ((offst_freq - inc) < car_max) && | |
2391 | ((offst_freq + inc) > -car_max) && | |
2392 | (cpt_step < steps_max)); | |
2393 | ||
2394 | reg = STV090x_READ_DEMOD(state, PDELCTRL1); | |
2395 | STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); | |
2396 | if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) | |
2397 | goto err; | |
2398 | ||
2399 | return lock; | |
2400 | err: | |
2401 | dprintk(FE_ERROR, 1, "I/O error"); | |
2402 | return -1; | |
2403 | } | |
2404 | ||
2405 | static int stv090x_sw_algo(struct stv090x_state *state) | |
2406 | { | |
2407 | int no_signal, zigzag, lock = 0; | |
2408 | u32 reg; | |
2409 | ||
2410 | s32 dvbs2_fly_wheel; | |
2411 | s32 inc, timeout_step, trials, steps_max; | |
2412 | ||
27d40321 MA |
2413 | /* get params */ |
2414 | stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); | |
e415c689 | 2415 | |
72982f76 | 2416 | switch (state->search_mode) { |
e415c689 MA |
2417 | case STV090x_SEARCH_DVBS1: |
2418 | case STV090x_SEARCH_DSS: | |
2419 | /* accelerate the frequency detector */ | |
97f7a2ae | 2420 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2421 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) |
2422 | goto err; | |
e415c689 | 2423 | } |
27d40321 | 2424 | |
e415c689 MA |
2425 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) |
2426 | goto err; | |
2427 | zigzag = 0; | |
2428 | break; | |
2429 | ||
2430 | case STV090x_SEARCH_DVBS2: | |
97f7a2ae | 2431 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2432 | if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) |
2433 | goto err; | |
e415c689 | 2434 | } |
27d40321 | 2435 | |
e415c689 MA |
2436 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) |
2437 | goto err; | |
2438 | zigzag = 1; | |
2439 | break; | |
2440 | ||
2441 | case STV090x_SEARCH_AUTO: | |
2442 | default: | |
2443 | /* accelerate the frequency detector */ | |
97f7a2ae | 2444 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2445 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) |
2446 | goto err; | |
2447 | if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) | |
2448 | goto err; | |
e415c689 | 2449 | } |
27d40321 | 2450 | |
2f5914be | 2451 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) |
e415c689 MA |
2452 | goto err; |
2453 | zigzag = 0; | |
2454 | break; | |
2455 | } | |
2456 | ||
2457 | trials = 0; | |
2458 | do { | |
2459 | lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); | |
2460 | no_signal = stv090x_chk_signal(state); | |
2461 | trials++; | |
2462 | ||
2463 | /*run the SW search 2 times maximum*/ | |
2464 | if (lock || no_signal || (trials == 2)) { | |
2465 | /*Check if the demod is not losing lock in DVBS2*/ | |
97f7a2ae | 2466 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2467 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) |
2468 | goto err; | |
2469 | if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) | |
2470 | goto err; | |
e415c689 MA |
2471 | } |
2472 | ||
2473 | reg = STV090x_READ_DEMOD(state, DMDSTATE); | |
2474 | if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { | |
2475 | /*Check if the demod is not losing lock in DVBS2*/ | |
2476 | msleep(timeout_step); | |
2477 | reg = STV090x_READ_DEMOD(state, DMDFLYW); | |
2478 | dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); | |
2479 | if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ | |
2480 | msleep(timeout_step); | |
2481 | reg = STV090x_READ_DEMOD(state, DMDFLYW); | |
2482 | dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); | |
2483 | } | |
2484 | if (dvbs2_fly_wheel < 0xd) { | |
25985edc | 2485 | /*FALSE lock, The demod is losing lock */ |
e415c689 MA |
2486 | lock = 0; |
2487 | if (trials < 2) { | |
97f7a2ae | 2488 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2489 | if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) |
2490 | goto err; | |
e415c689 | 2491 | } |
27d40321 | 2492 | |
e415c689 MA |
2493 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) |
2494 | goto err; | |
2495 | } | |
2496 | } | |
2497 | } | |
2498 | } | |
2499 | } while ((!lock) && (trials < 2) && (!no_signal)); | |
2500 | ||
2501 | return lock; | |
2502 | err: | |
2503 | dprintk(FE_ERROR, 1, "I/O error"); | |
2504 | return -1; | |
2505 | } | |
2506 | ||
2507 | static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) | |
2508 | { | |
2509 | u32 reg; | |
2510 | enum stv090x_delsys delsys; | |
2511 | ||
2512 | reg = STV090x_READ_DEMOD(state, DMDSTATE); | |
2513 | if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) | |
2514 | delsys = STV090x_DVBS2; | |
2515 | else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { | |
2516 | reg = STV090x_READ_DEMOD(state, FECM); | |
2517 | if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) | |
2518 | delsys = STV090x_DSS; | |
2519 | else | |
2520 | delsys = STV090x_DVBS1; | |
2521 | } else { | |
2522 | delsys = STV090x_ERROR; | |
2523 | } | |
2524 | ||
2525 | return delsys; | |
2526 | } | |
2527 | ||
2528 | /* in Hz */ | |
2529 | static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) | |
2530 | { | |
2531 | s32 derot, int_1, int_2, tmp_1, tmp_2; | |
e415c689 MA |
2532 | |
2533 | derot = STV090x_READ_DEMOD(state, CFR2) << 16; | |
2534 | derot |= STV090x_READ_DEMOD(state, CFR1) << 8; | |
2535 | derot |= STV090x_READ_DEMOD(state, CFR0); | |
2536 | ||
2537 | derot = comp2(derot, 24); | |
97f7a2ae | 2538 | int_1 = mclk >> 12; |
da4b9059 | 2539 | int_2 = derot >> 12; |
e415c689 | 2540 | |
da4b9059 | 2541 | /* carrier_frequency = MasterClock * Reg / 2^24 */ |
97f7a2ae | 2542 | tmp_1 = mclk % 0x1000; |
da4b9059 | 2543 | tmp_2 = derot % 0x1000; |
e415c689 MA |
2544 | |
2545 | derot = (int_1 * int_2) + | |
da4b9059 | 2546 | ((int_1 * tmp_2) >> 12) + |
b671a8d4 | 2547 | ((int_2 * tmp_1) >> 12); |
e415c689 MA |
2548 | |
2549 | return derot; | |
2550 | } | |
2551 | ||
2552 | static int stv090x_get_viterbi(struct stv090x_state *state) | |
2553 | { | |
2554 | u32 reg, rate; | |
2555 | ||
2556 | reg = STV090x_READ_DEMOD(state, VITCURPUN); | |
2557 | rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); | |
2558 | ||
2559 | switch (rate) { | |
2560 | case 13: | |
2561 | state->fec = STV090x_PR12; | |
2562 | break; | |
2563 | ||
2564 | case 18: | |
2565 | state->fec = STV090x_PR23; | |
2566 | break; | |
2567 | ||
2568 | case 21: | |
2569 | state->fec = STV090x_PR34; | |
2570 | break; | |
2571 | ||
2572 | case 24: | |
2573 | state->fec = STV090x_PR56; | |
2574 | break; | |
2575 | ||
2576 | case 25: | |
2577 | state->fec = STV090x_PR67; | |
2578 | break; | |
2579 | ||
2580 | case 26: | |
2581 | state->fec = STV090x_PR78; | |
2582 | break; | |
2583 | ||
2584 | default: | |
2585 | state->fec = STV090x_PRERR; | |
2586 | break; | |
2587 | } | |
2588 | ||
2589 | return 0; | |
2590 | } | |
2591 | ||
2592 | static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) | |
2593 | { | |
2594 | struct dvb_frontend *fe = &state->frontend; | |
2595 | ||
2596 | u8 tmg; | |
2597 | u32 reg; | |
2598 | s32 i = 0, offst_freq; | |
2599 | ||
2600 | msleep(5); | |
2601 | ||
2602 | if (state->algo == STV090x_BLIND_SEARCH) { | |
2603 | tmg = STV090x_READ_DEMOD(state, TMGREG2); | |
2604 | STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); | |
2f5914be | 2605 | while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { |
e415c689 MA |
2606 | tmg = STV090x_READ_DEMOD(state, TMGREG2); |
2607 | msleep(5); | |
2608 | i += 5; | |
2609 | } | |
2610 | } | |
2611 | state->delsys = stv090x_get_std(state); | |
2612 | ||
19c4ee58 | 2613 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 2614 | goto err; |
e415c689 | 2615 | |
27d40321 MA |
2616 | if (state->config->tuner_get_frequency) { |
2617 | if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) | |
2c1f750b | 2618 | goto err_gateoff; |
27d40321 | 2619 | } |
e415c689 | 2620 | |
19c4ee58 | 2621 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 2622 | goto err; |
e415c689 | 2623 | |
97f7a2ae | 2624 | offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; |
e415c689 | 2625 | state->frequency += offst_freq; |
27d40321 MA |
2626 | |
2627 | if (stv090x_get_viterbi(state) < 0) | |
2628 | goto err; | |
2629 | ||
e415c689 MA |
2630 | reg = STV090x_READ_DEMOD(state, DMDMODCOD); |
2631 | state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); | |
2632 | state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; | |
2633 | state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; | |
2634 | reg = STV090x_READ_DEMOD(state, TMGOBS); | |
2635 | state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); | |
2636 | reg = STV090x_READ_DEMOD(state, FECM); | |
2637 | state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); | |
2638 | ||
2639 | if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { | |
2640 | ||
19c4ee58 | 2641 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 2642 | goto err; |
e415c689 | 2643 | |
27d40321 MA |
2644 | if (state->config->tuner_get_frequency) { |
2645 | if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) | |
2c1f750b | 2646 | goto err_gateoff; |
27d40321 | 2647 | } |
e415c689 | 2648 | |
19c4ee58 | 2649 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 2650 | goto err; |
e415c689 MA |
2651 | |
2652 | if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) | |
2f5914be | 2653 | return STV090x_RANGEOK; |
e415c689 MA |
2654 | else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) |
2655 | return STV090x_RANGEOK; | |
2656 | else | |
2657 | return STV090x_OUTOFRANGE; /* Out of Range */ | |
2658 | } else { | |
2659 | if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) | |
2660 | return STV090x_RANGEOK; | |
2661 | else | |
2662 | return STV090x_OUTOFRANGE; | |
2663 | } | |
2664 | ||
2665 | return STV090x_OUTOFRANGE; | |
2c1f750b OE |
2666 | |
2667 | err_gateoff: | |
19c4ee58 | 2668 | stv090x_i2c_gate_ctrl(state, 0); |
27d40321 MA |
2669 | err: |
2670 | dprintk(FE_ERROR, 1, "I/O error"); | |
2671 | return -1; | |
e415c689 MA |
2672 | } |
2673 | ||
2674 | static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) | |
2675 | { | |
2676 | s32 offst_tmg; | |
e415c689 MA |
2677 | |
2678 | offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; | |
2679 | offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; | |
2680 | offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); | |
2681 | ||
e415c689 MA |
2682 | offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ |
2683 | if (!offst_tmg) | |
2684 | offst_tmg = 1; | |
2685 | ||
5f99feff | 2686 | offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); |
e415c689 MA |
2687 | offst_tmg /= 320; |
2688 | ||
2689 | return offst_tmg; | |
2690 | } | |
2691 | ||
2692 | static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) | |
2693 | { | |
2694 | u8 aclc = 0x29; | |
2695 | s32 i; | |
27d40321 | 2696 | struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; |
e415c689 | 2697 | |
97f7a2ae | 2698 | if (state->internal->dev_ver == 0x20) { |
27d40321 MA |
2699 | car_loop = stv090x_s2_crl_cut20; |
2700 | car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; | |
2701 | car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; | |
2702 | } else { | |
2703 | /* >= Cut 3 */ | |
2704 | car_loop = stv090x_s2_crl_cut30; | |
2705 | car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; | |
2706 | car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; | |
2707 | } | |
e415c689 MA |
2708 | |
2709 | if (modcod < STV090x_QPSK_12) { | |
2710 | i = 0; | |
27d40321 | 2711 | while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) |
e415c689 MA |
2712 | i++; |
2713 | ||
2714 | if (i >= 3) | |
2715 | i = 2; | |
2716 | ||
2717 | } else { | |
2718 | i = 0; | |
2719 | while ((i < 14) && (modcod != car_loop[i].modcod)) | |
2720 | i++; | |
2721 | ||
2722 | if (i >= 14) { | |
2723 | i = 0; | |
27d40321 | 2724 | while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) |
e415c689 MA |
2725 | i++; |
2726 | ||
2727 | if (i >= 11) | |
2728 | i = 10; | |
2729 | } | |
2730 | } | |
2731 | ||
2732 | if (modcod <= STV090x_QPSK_25) { | |
2733 | if (pilots) { | |
2734 | if (state->srate <= 3000000) | |
27d40321 | 2735 | aclc = car_loop_qpsk_low[i].crl_pilots_on_2; |
e415c689 | 2736 | else if (state->srate <= 7000000) |
27d40321 | 2737 | aclc = car_loop_qpsk_low[i].crl_pilots_on_5; |
e415c689 | 2738 | else if (state->srate <= 15000000) |
27d40321 | 2739 | aclc = car_loop_qpsk_low[i].crl_pilots_on_10; |
e415c689 | 2740 | else if (state->srate <= 25000000) |
27d40321 | 2741 | aclc = car_loop_qpsk_low[i].crl_pilots_on_20; |
e415c689 | 2742 | else |
27d40321 | 2743 | aclc = car_loop_qpsk_low[i].crl_pilots_on_30; |
e415c689 MA |
2744 | } else { |
2745 | if (state->srate <= 3000000) | |
27d40321 | 2746 | aclc = car_loop_qpsk_low[i].crl_pilots_off_2; |
e415c689 | 2747 | else if (state->srate <= 7000000) |
27d40321 | 2748 | aclc = car_loop_qpsk_low[i].crl_pilots_off_5; |
e415c689 | 2749 | else if (state->srate <= 15000000) |
27d40321 | 2750 | aclc = car_loop_qpsk_low[i].crl_pilots_off_10; |
e415c689 | 2751 | else if (state->srate <= 25000000) |
27d40321 | 2752 | aclc = car_loop_qpsk_low[i].crl_pilots_off_20; |
e415c689 | 2753 | else |
27d40321 | 2754 | aclc = car_loop_qpsk_low[i].crl_pilots_off_30; |
e415c689 MA |
2755 | } |
2756 | ||
2757 | } else if (modcod <= STV090x_8PSK_910) { | |
2758 | if (pilots) { | |
2759 | if (state->srate <= 3000000) | |
2760 | aclc = car_loop[i].crl_pilots_on_2; | |
2761 | else if (state->srate <= 7000000) | |
2762 | aclc = car_loop[i].crl_pilots_on_5; | |
2763 | else if (state->srate <= 15000000) | |
2764 | aclc = car_loop[i].crl_pilots_on_10; | |
2765 | else if (state->srate <= 25000000) | |
2766 | aclc = car_loop[i].crl_pilots_on_20; | |
2767 | else | |
2768 | aclc = car_loop[i].crl_pilots_on_30; | |
2769 | } else { | |
2770 | if (state->srate <= 3000000) | |
2771 | aclc = car_loop[i].crl_pilots_off_2; | |
2772 | else if (state->srate <= 7000000) | |
2773 | aclc = car_loop[i].crl_pilots_off_5; | |
2774 | else if (state->srate <= 15000000) | |
2775 | aclc = car_loop[i].crl_pilots_off_10; | |
2776 | else if (state->srate <= 25000000) | |
2777 | aclc = car_loop[i].crl_pilots_off_20; | |
2778 | else | |
2779 | aclc = car_loop[i].crl_pilots_off_30; | |
2780 | } | |
2781 | } else { /* 16APSK and 32APSK */ | |
2782 | if (state->srate <= 3000000) | |
27d40321 | 2783 | aclc = car_loop_apsk_low[i].crl_pilots_on_2; |
e415c689 | 2784 | else if (state->srate <= 7000000) |
27d40321 | 2785 | aclc = car_loop_apsk_low[i].crl_pilots_on_5; |
e415c689 | 2786 | else if (state->srate <= 15000000) |
27d40321 | 2787 | aclc = car_loop_apsk_low[i].crl_pilots_on_10; |
e415c689 | 2788 | else if (state->srate <= 25000000) |
27d40321 | 2789 | aclc = car_loop_apsk_low[i].crl_pilots_on_20; |
e415c689 | 2790 | else |
27d40321 | 2791 | aclc = car_loop_apsk_low[i].crl_pilots_on_30; |
e415c689 MA |
2792 | } |
2793 | ||
2794 | return aclc; | |
2795 | } | |
2796 | ||
2797 | static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) | |
2798 | { | |
0a5ded56 | 2799 | struct stv090x_short_frame_crloop *short_crl = NULL; |
e415c689 MA |
2800 | s32 index = 0; |
2801 | u8 aclc = 0x0b; | |
2802 | ||
2803 | switch (state->modulation) { | |
2804 | case STV090x_QPSK: | |
2805 | default: | |
2806 | index = 0; | |
2807 | break; | |
2808 | case STV090x_8PSK: | |
2809 | index = 1; | |
2810 | break; | |
2811 | case STV090x_16APSK: | |
2812 | index = 2; | |
2813 | break; | |
2814 | case STV090x_32APSK: | |
2815 | index = 3; | |
2816 | break; | |
2817 | } | |
2818 | ||
97f7a2ae | 2819 | if (state->internal->dev_ver >= 0x30) { |
eebf8d86 | 2820 | /* Cut 3.0 and up */ |
27d40321 | 2821 | short_crl = stv090x_s2_short_crl_cut30; |
eebf8d86 MA |
2822 | } else { |
2823 | /* Cut 2.0 and up: we don't support cuts older than 2.0 */ | |
2824 | short_crl = stv090x_s2_short_crl_cut20; | |
2825 | } | |
27d40321 MA |
2826 | |
2827 | if (state->srate <= 3000000) | |
2828 | aclc = short_crl[index].crl_2; | |
2829 | else if (state->srate <= 7000000) | |
2830 | aclc = short_crl[index].crl_5; | |
2831 | else if (state->srate <= 15000000) | |
2832 | aclc = short_crl[index].crl_10; | |
2833 | else if (state->srate <= 25000000) | |
2834 | aclc = short_crl[index].crl_20; | |
2835 | else | |
2836 | aclc = short_crl[index].crl_30; | |
e415c689 MA |
2837 | |
2838 | return aclc; | |
2839 | } | |
2840 | ||
2841 | static int stv090x_optimize_track(struct stv090x_state *state) | |
2842 | { | |
2843 | struct dvb_frontend *fe = &state->frontend; | |
2844 | ||
2845 | enum stv090x_rolloff rolloff; | |
2846 | enum stv090x_modcod modcod; | |
2847 | ||
2848 | s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; | |
2849 | u32 reg; | |
2850 | ||
97f7a2ae | 2851 | srate = stv090x_get_srate(state, state->internal->mclk); |
e415c689 MA |
2852 | srate += stv090x_get_tmgoffst(state, srate); |
2853 | ||
2854 | switch (state->delsys) { | |
2855 | case STV090x_DVBS1: | |
2856 | case STV090x_DSS: | |
b671a8d4 | 2857 | if (state->search_mode == STV090x_SEARCH_AUTO) { |
e415c689 MA |
2858 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); |
2859 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); | |
2860 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); | |
2861 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
2862 | goto err; | |
2863 | } | |
2864 | reg = STV090x_READ_DEMOD(state, DEMOD); | |
2865 | STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); | |
27d40321 | 2866 | STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); |
e415c689 MA |
2867 | if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) |
2868 | goto err; | |
27d40321 | 2869 | |
97f7a2ae | 2870 | if (state->internal->dev_ver >= 0x30) { |
27d40321 MA |
2871 | if (stv090x_get_viterbi(state) < 0) |
2872 | goto err; | |
2873 | ||
2874 | if (state->fec == STV090x_PR12) { | |
2875 | if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) | |
2876 | goto err; | |
2877 | if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) | |
2878 | goto err; | |
2879 | } else { | |
2880 | if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) | |
2881 | goto err; | |
2882 | if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) | |
2883 | goto err; | |
2884 | } | |
2885 | } | |
2886 | ||
e415c689 MA |
2887 | if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) |
2888 | goto err; | |
2889 | break; | |
2890 | ||
2891 | case STV090x_DVBS2: | |
2892 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
2f5914be AR |
2893 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); |
2894 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); | |
e415c689 MA |
2895 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) |
2896 | goto err; | |
179fd15a OE |
2897 | if (state->internal->dev_ver >= 0x30) { |
2898 | if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) | |
2899 | goto err; | |
2900 | if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) | |
2901 | goto err; | |
2902 | } | |
e415c689 MA |
2903 | if (state->frame_len == STV090x_LONG_FRAME) { |
2904 | reg = STV090x_READ_DEMOD(state, DMDMODCOD); | |
2905 | modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); | |
2906 | pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; | |
2907 | aclc = stv090x_optimize_carloop(state, modcod, pilots); | |
2908 | if (modcod <= STV090x_QPSK_910) { | |
2909 | STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); | |
2910 | } else if (modcod <= STV090x_8PSK_910) { | |
2911 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) | |
2912 | goto err; | |
2913 | if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) | |
2914 | goto err; | |
2915 | } | |
2916 | if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { | |
2917 | if (modcod <= STV090x_16APSK_910) { | |
2918 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) | |
2919 | goto err; | |
2920 | if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) | |
2921 | goto err; | |
2922 | } else { | |
2923 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) | |
2924 | goto err; | |
2925 | if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) | |
2926 | goto err; | |
2927 | } | |
2928 | } | |
2929 | } else { | |
2930 | /*Carrier loop setting for short frame*/ | |
2931 | aclc = stv090x_optimize_carloop_short(state); | |
2932 | if (state->modulation == STV090x_QPSK) { | |
2933 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) | |
2934 | goto err; | |
2935 | } else if (state->modulation == STV090x_8PSK) { | |
2936 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) | |
2937 | goto err; | |
2938 | if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) | |
2939 | goto err; | |
2940 | } else if (state->modulation == STV090x_16APSK) { | |
2941 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) | |
2942 | goto err; | |
2943 | if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) | |
2944 | goto err; | |
2945 | } else if (state->modulation == STV090x_32APSK) { | |
2946 | if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) | |
2947 | goto err; | |
2948 | if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) | |
2949 | goto err; | |
2950 | } | |
2951 | } | |
27d40321 | 2952 | |
e415c689 MA |
2953 | STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */ |
2954 | break; | |
2955 | ||
187e7d3b | 2956 | case STV090x_ERROR: |
e415c689 MA |
2957 | default: |
2958 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
2959 | STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); | |
2960 | STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); | |
2961 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
2962 | goto err; | |
2963 | break; | |
2964 | } | |
2965 | ||
2966 | f_1 = STV090x_READ_DEMOD(state, CFR2); | |
2967 | f_0 = STV090x_READ_DEMOD(state, CFR1); | |
2968 | reg = STV090x_READ_DEMOD(state, TMGOBS); | |
2969 | rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); | |
2970 | ||
2971 | if (state->algo == STV090x_BLIND_SEARCH) { | |
2972 | STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); | |
2973 | reg = STV090x_READ_DEMOD(state, DMDCFGMD); | |
2974 | STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); | |
2975 | STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); | |
2976 | if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) | |
2977 | goto err; | |
27d40321 MA |
2978 | if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) |
2979 | goto err; | |
2980 | ||
2981 | if (stv090x_set_srate(state, srate) < 0) | |
e415c689 | 2982 | goto err; |
e415c689 | 2983 | blind_tune = 1; |
7b035da9 AR |
2984 | |
2985 | if (stv090x_dvbs_track_crl(state) < 0) | |
2986 | goto err; | |
e415c689 MA |
2987 | } |
2988 | ||
97f7a2ae | 2989 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
2990 | if ((state->search_mode == STV090x_SEARCH_DVBS1) || |
2991 | (state->search_mode == STV090x_SEARCH_DSS) || | |
2992 | (state->search_mode == STV090x_SEARCH_AUTO)) { | |
2993 | ||
2994 | if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) | |
2995 | goto err; | |
2996 | if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) | |
2997 | goto err; | |
2998 | } | |
2999 | } | |
3000 | ||
e415c689 MA |
3001 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) |
3002 | goto err; | |
3003 | ||
27d40321 MA |
3004 | /* AUTO tracking MODE */ |
3005 | if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) | |
3006 | goto err; | |
3007 | /* AUTO tracking MODE */ | |
3008 | if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) | |
3009 | goto err; | |
e415c689 | 3010 | |
97f7a2ae AR |
3011 | if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || |
3012 | (state->srate < 10000000)) { | |
27d40321 | 3013 | /* update initial carrier freq with the found freq offset */ |
e415c689 MA |
3014 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) |
3015 | goto err; | |
3016 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) | |
3017 | goto err; | |
3018 | state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; | |
3019 | ||
97f7a2ae | 3020 | if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { |
e415c689 MA |
3021 | |
3022 | if (state->algo != STV090x_WARM_SEARCH) { | |
3023 | ||
19c4ee58 | 3024 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 3025 | goto err; |
e415c689 | 3026 | |
27d40321 MA |
3027 | if (state->config->tuner_set_bandwidth) { |
3028 | if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) | |
2c1f750b | 3029 | goto err_gateoff; |
27d40321 | 3030 | } |
e415c689 | 3031 | |
19c4ee58 | 3032 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 3033 | goto err; |
e415c689 MA |
3034 | |
3035 | } | |
3036 | } | |
3037 | if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) | |
3038 | msleep(50); /* blind search: wait 50ms for SR stabilization */ | |
3039 | else | |
3040 | msleep(5); | |
3041 | ||
3042 | stv090x_get_lock_tmg(state); | |
3043 | ||
3044 | if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { | |
3045 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) | |
3046 | goto err; | |
3047 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) | |
3048 | goto err; | |
3049 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) | |
3050 | goto err; | |
3051 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) | |
3052 | goto err; | |
3053 | ||
3054 | i = 0; | |
3055 | ||
3056 | while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { | |
3057 | ||
3058 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) | |
3059 | goto err; | |
3060 | if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) | |
3061 | goto err; | |
3062 | if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) | |
3063 | goto err; | |
3064 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) | |
3065 | goto err; | |
3066 | i++; | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | } | |
3071 | ||
97f7a2ae | 3072 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
3073 | if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) |
3074 | goto err; | |
3075 | } | |
27d40321 | 3076 | |
e415c689 MA |
3077 | if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) |
3078 | stv090x_set_vit_thtracq(state); | |
3079 | ||
3080 | return 0; | |
2c1f750b OE |
3081 | |
3082 | err_gateoff: | |
19c4ee58 | 3083 | stv090x_i2c_gate_ctrl(state, 0); |
e415c689 MA |
3084 | err: |
3085 | dprintk(FE_ERROR, 1, "I/O error"); | |
3086 | return -1; | |
3087 | } | |
3088 | ||
3089 | static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) | |
3090 | { | |
3091 | s32 timer = 0, lock = 0, stat; | |
3092 | u32 reg; | |
3093 | ||
3094 | while ((timer < timeout) && (!lock)) { | |
3095 | reg = STV090x_READ_DEMOD(state, DMDSTATE); | |
3096 | stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); | |
3097 | ||
3098 | switch (stat) { | |
3099 | case 0: /* searching */ | |
3100 | case 1: /* first PLH detected */ | |
3101 | default: | |
3102 | lock = 0; | |
3103 | break; | |
3104 | ||
3105 | case 2: /* DVB-S2 mode */ | |
3106 | reg = STV090x_READ_DEMOD(state, PDELSTATUS1); | |
3107 | lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); | |
3108 | break; | |
3109 | ||
3110 | case 3: /* DVB-S1/legacy mode */ | |
3111 | reg = STV090x_READ_DEMOD(state, VSTATUSVIT); | |
3112 | lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); | |
3113 | break; | |
3114 | } | |
3115 | if (!lock) { | |
3116 | msleep(10); | |
3117 | timer += 10; | |
3118 | } | |
3119 | } | |
3120 | return lock; | |
3121 | } | |
3122 | ||
3123 | static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) | |
3124 | { | |
3125 | u32 reg; | |
3126 | s32 timer = 0; | |
3127 | int lock; | |
3128 | ||
3129 | lock = stv090x_get_dmdlock(state, timeout_dmd); | |
3130 | if (lock) | |
3131 | lock = stv090x_get_feclock(state, timeout_fec); | |
3132 | ||
3133 | if (lock) { | |
3134 | lock = 0; | |
3135 | ||
3136 | while ((timer < timeout_fec) && (!lock)) { | |
3137 | reg = STV090x_READ_DEMOD(state, TSSTATUS); | |
3138 | lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); | |
3139 | msleep(1); | |
3140 | timer++; | |
3141 | } | |
3142 | } | |
3143 | ||
3144 | return lock; | |
3145 | } | |
3146 | ||
3147 | static int stv090x_set_s2rolloff(struct stv090x_state *state) | |
3148 | { | |
e415c689 MA |
3149 | u32 reg; |
3150 | ||
97f7a2ae | 3151 | if (state->internal->dev_ver <= 0x20) { |
27d40321 | 3152 | /* rolloff to auto mode if DVBS2 */ |
e415c689 | 3153 | reg = STV090x_READ_DEMOD(state, DEMOD); |
27d40321 | 3154 | STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); |
e415c689 MA |
3155 | if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) |
3156 | goto err; | |
3157 | } else { | |
27d40321 | 3158 | /* DVB-S2 rolloff to auto mode if DVBS2 */ |
e415c689 | 3159 | reg = STV090x_READ_DEMOD(state, DEMOD); |
27d40321 | 3160 | STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); |
e415c689 MA |
3161 | if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) |
3162 | goto err; | |
3163 | } | |
3164 | return 0; | |
3165 | err: | |
3166 | dprintk(FE_ERROR, 1, "I/O error"); | |
3167 | return -1; | |
3168 | } | |
3169 | ||
e415c689 MA |
3170 | |
3171 | static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) | |
3172 | { | |
3173 | struct dvb_frontend *fe = &state->frontend; | |
3174 | enum stv090x_signal_state signal_state = STV090x_NOCARRIER; | |
3175 | u32 reg; | |
a4978a83 | 3176 | s32 agc1_power, power_iq = 0, i; |
4e58a682 | 3177 | int lock = 0, low_sr = 0, no_signal = 0; |
e415c689 MA |
3178 | |
3179 | reg = STV090x_READ_DEMOD(state, TSCFGH); | |
3180 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ | |
3181 | if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) | |
3182 | goto err; | |
3183 | ||
3184 | if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ | |
3185 | goto err; | |
3186 | ||
97f7a2ae | 3187 | if (state->internal->dev_ver >= 0x20) { |
7b035da9 AR |
3188 | if (state->srate > 5000000) { |
3189 | if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) | |
3190 | goto err; | |
3191 | } else { | |
3192 | if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) | |
3193 | goto err; | |
3194 | } | |
e415c689 MA |
3195 | } |
3196 | ||
3197 | stv090x_get_lock_tmg(state); | |
3198 | ||
3199 | if (state->algo == STV090x_BLIND_SEARCH) { | |
3200 | state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ | |
27d40321 MA |
3201 | if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ |
3202 | goto err; | |
3203 | if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) | |
3204 | goto err; | |
25985edc | 3205 | if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */ |
e415c689 | 3206 | goto err; |
e415c689 MA |
3207 | } else { |
3208 | /* known srate */ | |
3209 | if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) | |
3210 | goto err; | |
3211 | if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) | |
3212 | goto err; | |
3213 | ||
27d40321 MA |
3214 | if (state->srate < 2000000) { |
3215 | /* SR < 2MSPS */ | |
3216 | if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) | |
e415c689 MA |
3217 | goto err; |
3218 | } else { | |
27d40321 MA |
3219 | /* SR >= 2Msps */ |
3220 | if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) | |
e415c689 MA |
3221 | goto err; |
3222 | } | |
3223 | ||
27d40321 MA |
3224 | if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) |
3225 | goto err; | |
3226 | ||
97f7a2ae | 3227 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
3228 | if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) |
3229 | goto err; | |
3230 | if (state->algo == STV090x_COLD_SEARCH) | |
4e58a682 | 3231 | state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; |
e415c689 MA |
3232 | else if (state->algo == STV090x_WARM_SEARCH) |
3233 | state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; | |
e415c689 | 3234 | } |
27d40321 MA |
3235 | |
3236 | /* if cold start or warm (Symbolrate is known) | |
3237 | * use a Narrow symbol rate scan range | |
3238 | */ | |
3239 | if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ | |
3240 | goto err; | |
3241 | ||
3242 | if (stv090x_set_srate(state, state->srate) < 0) | |
3243 | goto err; | |
3244 | ||
97f7a2ae AR |
3245 | if (stv090x_set_max_srate(state, state->internal->mclk, |
3246 | state->srate) < 0) | |
27d40321 | 3247 | goto err; |
97f7a2ae AR |
3248 | if (stv090x_set_min_srate(state, state->internal->mclk, |
3249 | state->srate) < 0) | |
e415c689 | 3250 | goto err; |
e415c689 MA |
3251 | |
3252 | if (state->srate >= 10000000) | |
4e58a682 AR |
3253 | low_sr = 0; |
3254 | else | |
e415c689 MA |
3255 | low_sr = 1; |
3256 | } | |
3257 | ||
3258 | /* Setup tuner */ | |
19c4ee58 | 3259 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 3260 | goto err; |
e415c689 | 3261 | |
27d40321 | 3262 | if (state->config->tuner_set_bbgain) { |
d8b5a8e4 OE |
3263 | reg = state->config->tuner_bbgain; |
3264 | if (reg == 0) | |
3265 | reg = 10; /* default: 10dB */ | |
3266 | if (state->config->tuner_set_bbgain(fe, reg) < 0) | |
2c1f750b | 3267 | goto err_gateoff; |
27d40321 | 3268 | } |
e415c689 | 3269 | |
27d40321 MA |
3270 | if (state->config->tuner_set_frequency) { |
3271 | if (state->config->tuner_set_frequency(fe, state->frequency) < 0) | |
2c1f750b | 3272 | goto err_gateoff; |
27d40321 | 3273 | } |
e415c689 | 3274 | |
27d40321 MA |
3275 | if (state->config->tuner_set_bandwidth) { |
3276 | if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) | |
2c1f750b | 3277 | goto err_gateoff; |
27d40321 | 3278 | } |
e415c689 | 3279 | |
19c4ee58 | 3280 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 3281 | goto err; |
e415c689 MA |
3282 | |
3283 | msleep(50); | |
3284 | ||
27d40321 | 3285 | if (state->config->tuner_get_status) { |
19c4ee58 | 3286 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
41894b97 | 3287 | goto err; |
27d40321 | 3288 | if (state->config->tuner_get_status(fe, ®) < 0) |
2c1f750b | 3289 | goto err_gateoff; |
19c4ee58 | 3290 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
41894b97 | 3291 | goto err; |
e415c689 | 3292 | |
41894b97 OE |
3293 | if (reg) |
3294 | dprintk(FE_DEBUG, 1, "Tuner phase locked"); | |
3295 | else { | |
3296 | dprintk(FE_DEBUG, 1, "Tuner unlocked"); | |
3297 | return STV090x_NOCARRIER; | |
3298 | } | |
3299 | } | |
e415c689 | 3300 | |
27d40321 MA |
3301 | msleep(10); |
3302 | agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), | |
3303 | STV090x_READ_DEMOD(state, AGCIQIN0)); | |
3304 | ||
3305 | if (agc1_power == 0) { | |
3306 | /* If AGC1 integrator value is 0 | |
3307 | * then read POWERI, POWERQ | |
3308 | */ | |
3309 | for (i = 0; i < 5; i++) { | |
3310 | power_iq += (STV090x_READ_DEMOD(state, POWERI) + | |
3311 | STV090x_READ_DEMOD(state, POWERQ)) >> 1; | |
3312 | } | |
3313 | power_iq /= 5; | |
3314 | } | |
3315 | ||
3316 | if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { | |
3317 | dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); | |
3318 | lock = 0; | |
c4fa649a | 3319 | signal_state = STV090x_NOAGC1; |
27d40321 MA |
3320 | } else { |
3321 | reg = STV090x_READ_DEMOD(state, DEMOD); | |
3322 | STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); | |
3323 | ||
97f7a2ae | 3324 | if (state->internal->dev_ver <= 0x20) { |
27d40321 MA |
3325 | /* rolloff to auto mode if DVBS2 */ |
3326 | STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); | |
3327 | } else { | |
3328 | /* DVB-S2 rolloff to auto mode if DVBS2 */ | |
3329 | STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); | |
3330 | } | |
3331 | if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) | |
e415c689 | 3332 | goto err; |
27d40321 MA |
3333 | |
3334 | if (stv090x_delivery_search(state) < 0) | |
e415c689 | 3335 | goto err; |
27d40321 MA |
3336 | |
3337 | if (state->algo != STV090x_BLIND_SEARCH) { | |
3338 | if (stv090x_start_search(state) < 0) | |
3339 | goto err; | |
3340 | } | |
e415c689 MA |
3341 | } |
3342 | ||
c4fa649a AR |
3343 | if (signal_state == STV090x_NOAGC1) |
3344 | return signal_state; | |
27d40321 | 3345 | |
e415c689 MA |
3346 | if (state->algo == STV090x_BLIND_SEARCH) |
3347 | lock = stv090x_blind_search(state); | |
27d40321 | 3348 | |
e415c689 | 3349 | else if (state->algo == STV090x_COLD_SEARCH) |
a4978a83 | 3350 | lock = stv090x_get_coldlock(state, state->DemodTimeout); |
27d40321 | 3351 | |
e415c689 | 3352 | else if (state->algo == STV090x_WARM_SEARCH) |
a4978a83 | 3353 | lock = stv090x_get_dmdlock(state, state->DemodTimeout); |
e415c689 MA |
3354 | |
3355 | if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { | |
3356 | if (!low_sr) { | |
3357 | if (stv090x_chk_tmg(state)) | |
3358 | lock = stv090x_sw_algo(state); | |
3359 | } | |
3360 | } | |
3361 | ||
3362 | if (lock) | |
3363 | signal_state = stv090x_get_sig_params(state); | |
3364 | ||
3365 | if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ | |
3366 | stv090x_optimize_track(state); | |
27d40321 | 3367 | |
97f7a2ae | 3368 | if (state->internal->dev_ver >= 0x20) { |
27d40321 MA |
3369 | /* >= Cut 2.0 :release TS reset after |
3370 | * demod lock and optimized Tracking | |
3371 | */ | |
e415c689 MA |
3372 | reg = STV090x_READ_DEMOD(state, TSCFGH); |
3373 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ | |
3374 | if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) | |
3375 | goto err; | |
27d40321 | 3376 | |
e415c689 | 3377 | msleep(3); |
27d40321 | 3378 | |
e415c689 MA |
3379 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ |
3380 | if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) | |
3381 | goto err; | |
3382 | ||
3383 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ | |
3384 | if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) | |
3385 | goto err; | |
3386 | } | |
3387 | ||
a4978a83 AR |
3388 | lock = stv090x_get_lock(state, state->FecTimeout, |
3389 | state->FecTimeout); | |
3390 | if (lock) { | |
e415c689 MA |
3391 | if (state->delsys == STV090x_DVBS2) { |
3392 | stv090x_set_s2rolloff(state); | |
27d40321 MA |
3393 | |
3394 | reg = STV090x_READ_DEMOD(state, PDELCTRL2); | |
3395 | STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); | |
3396 | if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) | |
e415c689 | 3397 | goto err; |
27d40321 MA |
3398 | /* Reset DVBS2 packet delinator error counter */ |
3399 | reg = STV090x_READ_DEMOD(state, PDELCTRL2); | |
3400 | STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); | |
3401 | if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) | |
e415c689 | 3402 | goto err; |
27d40321 | 3403 | |
e415c689 MA |
3404 | if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */ |
3405 | goto err; | |
3406 | } else { | |
3407 | if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) | |
3408 | goto err; | |
3409 | } | |
27d40321 | 3410 | /* Reset the Total packet counter */ |
e415c689 MA |
3411 | if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) |
3412 | goto err; | |
27d40321 | 3413 | /* Reset the packet Error counter2 */ |
e415c689 MA |
3414 | if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) |
3415 | goto err; | |
3416 | } else { | |
e415c689 MA |
3417 | signal_state = STV090x_NODATA; |
3418 | no_signal = stv090x_chk_signal(state); | |
3419 | } | |
3420 | } | |
e415c689 MA |
3421 | return signal_state; |
3422 | ||
2c1f750b | 3423 | err_gateoff: |
19c4ee58 | 3424 | stv090x_i2c_gate_ctrl(state, 0); |
e415c689 MA |
3425 | err: |
3426 | dprintk(FE_ERROR, 1, "I/O error"); | |
3427 | return -1; | |
3428 | } | |
3429 | ||
3430 | static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) | |
3431 | { | |
3432 | struct stv090x_state *state = fe->demodulator_priv; | |
3433 | struct dtv_frontend_properties *props = &fe->dtv_property_cache; | |
3434 | ||
729cbafa AR |
3435 | if (p->frequency == 0) |
3436 | return DVBFE_ALGO_SEARCH_INVALID; | |
3437 | ||
e415c689 MA |
3438 | state->delsys = props->delivery_system; |
3439 | state->frequency = p->frequency; | |
3440 | state->srate = p->u.qpsk.symbol_rate; | |
4e58a682 AR |
3441 | state->search_mode = STV090x_SEARCH_AUTO; |
3442 | state->algo = STV090x_COLD_SEARCH; | |
3443 | state->fec = STV090x_PRERR; | |
c879d8ce AR |
3444 | if (state->srate > 10000000) { |
3445 | dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); | |
3446 | state->search_range = 10000000; | |
3447 | } else { | |
3448 | dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); | |
3449 | state->search_range = 5000000; | |
3450 | } | |
e415c689 | 3451 | |
2f5914be | 3452 | if (stv090x_algo(state) == STV090x_RANGEOK) { |
e415c689 MA |
3453 | dprintk(FE_DEBUG, 1, "Search success!"); |
3454 | return DVBFE_ALGO_SEARCH_SUCCESS; | |
3455 | } else { | |
3456 | dprintk(FE_DEBUG, 1, "Search failed!"); | |
3457 | return DVBFE_ALGO_SEARCH_FAILED; | |
3458 | } | |
3459 | ||
3460 | return DVBFE_ALGO_SEARCH_ERROR; | |
3461 | } | |
3462 | ||
e415c689 MA |
3463 | static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) |
3464 | { | |
3465 | struct stv090x_state *state = fe->demodulator_priv; | |
3466 | u32 reg; | |
3467 | u8 search_state; | |
e415c689 MA |
3468 | |
3469 | reg = STV090x_READ_DEMOD(state, DMDSTATE); | |
3470 | search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); | |
3471 | ||
3472 | switch (search_state) { | |
3473 | case 0: /* searching */ | |
3474 | case 1: /* first PLH detected */ | |
3475 | default: | |
3476 | dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); | |
9629c5b6 | 3477 | *status = 0; |
e415c689 MA |
3478 | break; |
3479 | ||
3480 | case 2: /* DVB-S2 mode */ | |
3481 | dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); | |
3482 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
3483 | if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) { | |
1d436171 AR |
3484 | reg = STV090x_READ_DEMOD(state, PDELSTATUS1); |
3485 | if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { | |
3486 | reg = STV090x_READ_DEMOD(state, TSSTATUS); | |
3487 | if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) { | |
c369b7c2 AR |
3488 | *status = FE_HAS_SIGNAL | |
3489 | FE_HAS_CARRIER | | |
1d436171 AR |
3490 | FE_HAS_VITERBI | |
3491 | FE_HAS_SYNC | | |
3492 | FE_HAS_LOCK; | |
3493 | } | |
e415c689 MA |
3494 | } |
3495 | } | |
3496 | break; | |
3497 | ||
3498 | case 3: /* DVB-S1/legacy mode */ | |
3499 | dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); | |
3500 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
3501 | if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) { | |
3502 | reg = STV090x_READ_DEMOD(state, VSTATUSVIT); | |
3503 | if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { | |
3504 | reg = STV090x_READ_DEMOD(state, TSSTATUS); | |
3505 | if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) { | |
c369b7c2 AR |
3506 | *status = FE_HAS_SIGNAL | |
3507 | FE_HAS_CARRIER | | |
3508 | FE_HAS_VITERBI | | |
3509 | FE_HAS_SYNC | | |
3510 | FE_HAS_LOCK; | |
e415c689 MA |
3511 | } |
3512 | } | |
3513 | } | |
3514 | break; | |
3515 | } | |
3516 | ||
9629c5b6 | 3517 | return 0; |
e415c689 MA |
3518 | } |
3519 | ||
3520 | static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) | |
3521 | { | |
3522 | struct stv090x_state *state = fe->demodulator_priv; | |
3523 | ||
3524 | s32 count_4, count_3, count_2, count_1, count_0, count; | |
3525 | u32 reg, h, m, l; | |
3526 | enum fe_status status; | |
3527 | ||
9629c5b6 AR |
3528 | stv090x_read_status(fe, &status); |
3529 | if (!(status & FE_HAS_LOCK)) { | |
e415c689 MA |
3530 | *per = 1 << 23; /* Max PER */ |
3531 | } else { | |
3532 | /* Counter 2 */ | |
3533 | reg = STV090x_READ_DEMOD(state, ERRCNT22); | |
3534 | h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); | |
3535 | ||
3536 | reg = STV090x_READ_DEMOD(state, ERRCNT21); | |
3537 | m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); | |
3538 | ||
3539 | reg = STV090x_READ_DEMOD(state, ERRCNT20); | |
3540 | l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); | |
3541 | ||
3542 | *per = ((h << 16) | (m << 8) | l); | |
3543 | ||
3544 | count_4 = STV090x_READ_DEMOD(state, FBERCPT4); | |
3545 | count_3 = STV090x_READ_DEMOD(state, FBERCPT3); | |
3546 | count_2 = STV090x_READ_DEMOD(state, FBERCPT2); | |
3547 | count_1 = STV090x_READ_DEMOD(state, FBERCPT1); | |
3548 | count_0 = STV090x_READ_DEMOD(state, FBERCPT0); | |
3549 | ||
3550 | if ((!count_4) && (!count_3)) { | |
3551 | count = (count_2 & 0xff) << 16; | |
3552 | count |= (count_1 & 0xff) << 8; | |
3553 | count |= count_0 & 0xff; | |
3554 | } else { | |
3555 | count = 1 << 24; | |
3556 | } | |
3557 | if (count == 0) | |
3558 | *per = 1; | |
3559 | } | |
3560 | if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) | |
3561 | goto err; | |
3562 | if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) | |
3563 | goto err; | |
3564 | ||
3565 | return 0; | |
3566 | err: | |
3567 | dprintk(FE_ERROR, 1, "I/O error"); | |
3568 | return -1; | |
3569 | } | |
3570 | ||
3571 | static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) | |
3572 | { | |
3573 | int res = 0; | |
3574 | int min = 0, med; | |
3575 | ||
dbeb7dbf AR |
3576 | if ((val >= tab[min].read && val < tab[max].read) || |
3577 | (val >= tab[max].read && val < tab[min].read)) { | |
e415c689 MA |
3578 | while ((max - min) > 1) { |
3579 | med = (max + min) / 2; | |
dbeb7dbf AR |
3580 | if ((val >= tab[min].read && val < tab[med].read) || |
3581 | (val >= tab[med].read && val < tab[min].read)) | |
e415c689 MA |
3582 | max = med; |
3583 | else | |
3584 | min = med; | |
3585 | } | |
3586 | res = ((val - tab[min].read) * | |
3587 | (tab[max].real - tab[min].real) / | |
3588 | (tab[max].read - tab[min].read)) + | |
3589 | tab[min].real; | |
dbeb7dbf AR |
3590 | } else { |
3591 | if (tab[min].read < tab[max].read) { | |
3592 | if (val < tab[min].read) | |
3593 | res = tab[min].real; | |
3594 | else if (val >= tab[max].read) | |
3595 | res = tab[max].real; | |
3596 | } else { | |
3597 | if (val >= tab[min].read) | |
3598 | res = tab[min].real; | |
3599 | else if (val < tab[max].read) | |
3600 | res = tab[max].real; | |
3601 | } | |
e415c689 MA |
3602 | } |
3603 | ||
3604 | return res; | |
3605 | } | |
3606 | ||
3607 | static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
3608 | { | |
3609 | struct stv090x_state *state = fe->demodulator_priv; | |
3610 | u32 reg; | |
dbeb7dbf AR |
3611 | s32 agc_0, agc_1, agc; |
3612 | s32 str; | |
e415c689 MA |
3613 | |
3614 | reg = STV090x_READ_DEMOD(state, AGCIQIN1); | |
dbeb7dbf AR |
3615 | agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); |
3616 | reg = STV090x_READ_DEMOD(state, AGCIQIN0); | |
3617 | agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); | |
3618 | agc = MAKEWORD16(agc_1, agc_0); | |
e415c689 | 3619 | |
dbeb7dbf AR |
3620 | str = stv090x_table_lookup(stv090x_rf_tab, |
3621 | ARRAY_SIZE(stv090x_rf_tab) - 1, agc); | |
e415c689 | 3622 | if (agc > stv090x_rf_tab[0].read) |
dbeb7dbf | 3623 | str = 0; |
e415c689 | 3624 | else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) |
dbeb7dbf AR |
3625 | str = -100; |
3626 | *strength = (str + 100) * 0xFFFF / 100; | |
e415c689 MA |
3627 | |
3628 | return 0; | |
3629 | } | |
3630 | ||
3631 | static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) | |
3632 | { | |
3633 | struct stv090x_state *state = fe->demodulator_priv; | |
3634 | u32 reg_0, reg_1, reg, i; | |
3635 | s32 val_0, val_1, val = 0; | |
3636 | u8 lock_f; | |
dbeb7dbf AR |
3637 | s32 div; |
3638 | u32 last; | |
e415c689 MA |
3639 | |
3640 | switch (state->delsys) { | |
3641 | case STV090x_DVBS2: | |
3642 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
3643 | lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); | |
3644 | if (lock_f) { | |
3645 | msleep(5); | |
3646 | for (i = 0; i < 16; i++) { | |
3647 | reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); | |
3648 | val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); | |
3649 | reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); | |
dbeb7dbf | 3650 | val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); |
e415c689 MA |
3651 | val += MAKEWORD16(val_1, val_0); |
3652 | msleep(1); | |
3653 | } | |
3654 | val /= 16; | |
dbeb7dbf AR |
3655 | last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; |
3656 | div = stv090x_s2cn_tab[0].read - | |
3657 | stv090x_s2cn_tab[last].read; | |
3658 | *cnr = 0xFFFF - ((val * 0xFFFF) / div); | |
e415c689 MA |
3659 | } |
3660 | break; | |
3661 | ||
3662 | case STV090x_DVBS1: | |
3663 | case STV090x_DSS: | |
3664 | reg = STV090x_READ_DEMOD(state, DSTATUS); | |
3665 | lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); | |
3666 | if (lock_f) { | |
3667 | msleep(5); | |
3668 | for (i = 0; i < 16; i++) { | |
3669 | reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); | |
3670 | val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); | |
3671 | reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); | |
dbeb7dbf | 3672 | val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); |
e415c689 MA |
3673 | val += MAKEWORD16(val_1, val_0); |
3674 | msleep(1); | |
3675 | } | |
3676 | val /= 16; | |
dbeb7dbf AR |
3677 | last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; |
3678 | div = stv090x_s1cn_tab[0].read - | |
3679 | stv090x_s1cn_tab[last].read; | |
3680 | *cnr = 0xFFFF - ((val * 0xFFFF) / div); | |
e415c689 MA |
3681 | } |
3682 | break; | |
3683 | default: | |
3684 | break; | |
3685 | } | |
3686 | ||
3687 | return 0; | |
3688 | } | |
3689 | ||
3690 | static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) | |
3691 | { | |
3692 | struct stv090x_state *state = fe->demodulator_priv; | |
3693 | u32 reg; | |
3694 | ||
3695 | reg = STV090x_READ_DEMOD(state, DISTXCTL); | |
3696 | switch (tone) { | |
3697 | case SEC_TONE_ON: | |
3698 | STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); | |
3699 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); | |
3700 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3701 | goto err; | |
3702 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); | |
3703 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3704 | goto err; | |
3705 | break; | |
3706 | ||
3707 | case SEC_TONE_OFF: | |
3708 | STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); | |
3709 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); | |
3710 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3711 | goto err; | |
3712 | break; | |
3713 | default: | |
3714 | return -EINVAL; | |
3715 | } | |
3716 | ||
3717 | return 0; | |
3718 | err: | |
3719 | dprintk(FE_ERROR, 1, "I/O error"); | |
3720 | return -1; | |
3721 | } | |
3722 | ||
3723 | ||
3724 | static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) | |
3725 | { | |
3726 | return DVBFE_ALGO_CUSTOM; | |
3727 | } | |
3728 | ||
3729 | static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) | |
3730 | { | |
3731 | struct stv090x_state *state = fe->demodulator_priv; | |
3732 | u32 reg, idle = 0, fifo_full = 1; | |
3733 | int i; | |
3734 | ||
3735 | reg = STV090x_READ_DEMOD(state, DISTXCTL); | |
f9ed95d0 | 3736 | |
30e8ca2c OE |
3737 | STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, |
3738 | (state->config->diseqc_envelope_mode) ? 4 : 2); | |
f9ed95d0 AR |
3739 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); |
3740 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3741 | goto err; | |
3742 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); | |
3743 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3744 | goto err; | |
3745 | ||
e415c689 MA |
3746 | STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); |
3747 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3748 | goto err; | |
3749 | ||
3750 | for (i = 0; i < cmd->msg_len; i++) { | |
3751 | ||
3752 | while (fifo_full) { | |
3753 | reg = STV090x_READ_DEMOD(state, DISTXSTATUS); | |
3754 | fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); | |
3755 | } | |
3756 | ||
3757 | if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) | |
3758 | goto err; | |
f9ed95d0 AR |
3759 | } |
3760 | reg = STV090x_READ_DEMOD(state, DISTXCTL); | |
3761 | STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); | |
3762 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3763 | goto err; | |
3764 | ||
3765 | i = 0; | |
3766 | ||
3767 | while ((!idle) && (i < 10)) { | |
3768 | reg = STV090x_READ_DEMOD(state, DISTXSTATUS); | |
3769 | idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); | |
3770 | msleep(10); | |
e415c689 MA |
3771 | i++; |
3772 | } | |
f9ed95d0 AR |
3773 | |
3774 | return 0; | |
3775 | err: | |
3776 | dprintk(FE_ERROR, 1, "I/O error"); | |
3777 | return -1; | |
3778 | } | |
3779 | ||
3780 | static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) | |
3781 | { | |
3782 | struct stv090x_state *state = fe->demodulator_priv; | |
3783 | u32 reg, idle = 0, fifo_full = 1; | |
3784 | u8 mode, value; | |
3785 | int i; | |
3786 | ||
3787 | reg = STV090x_READ_DEMOD(state, DISTXCTL); | |
3788 | ||
3789 | if (burst == SEC_MINI_A) { | |
30e8ca2c | 3790 | mode = (state->config->diseqc_envelope_mode) ? 5 : 3; |
f9ed95d0 AR |
3791 | value = 0x00; |
3792 | } else { | |
30e8ca2c | 3793 | mode = (state->config->diseqc_envelope_mode) ? 4 : 2; |
f9ed95d0 AR |
3794 | value = 0xFF; |
3795 | } | |
3796 | ||
3797 | STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); | |
3798 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); | |
3799 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3800 | goto err; | |
3801 | STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); | |
3802 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3803 | goto err; | |
3804 | ||
3805 | STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); | |
3806 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3807 | goto err; | |
3808 | ||
3809 | while (fifo_full) { | |
3810 | reg = STV090x_READ_DEMOD(state, DISTXSTATUS); | |
3811 | fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); | |
3812 | } | |
3813 | ||
3814 | if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) | |
3815 | goto err; | |
3816 | ||
e415c689 MA |
3817 | reg = STV090x_READ_DEMOD(state, DISTXCTL); |
3818 | STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); | |
3819 | if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) | |
3820 | goto err; | |
3821 | ||
3822 | i = 0; | |
3823 | ||
3824 | while ((!idle) && (i < 10)) { | |
3825 | reg = STV090x_READ_DEMOD(state, DISTXSTATUS); | |
3826 | idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); | |
3827 | msleep(10); | |
3828 | i++; | |
3829 | } | |
3830 | ||
3831 | return 0; | |
3832 | err: | |
3833 | dprintk(FE_ERROR, 1, "I/O error"); | |
3834 | return -1; | |
3835 | } | |
3836 | ||
3837 | static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) | |
3838 | { | |
3839 | struct stv090x_state *state = fe->demodulator_priv; | |
3840 | u32 reg = 0, i = 0, rx_end = 0; | |
3841 | ||
3842 | while ((rx_end != 1) && (i < 10)) { | |
3843 | msleep(10); | |
3844 | i++; | |
3845 | reg = STV090x_READ_DEMOD(state, DISRX_ST0); | |
3846 | rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); | |
3847 | } | |
3848 | ||
3849 | if (rx_end) { | |
3850 | reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); | |
3851 | for (i = 0; i < reply->msg_len; i++) | |
3852 | reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); | |
3853 | } | |
3854 | ||
3855 | return 0; | |
3856 | } | |
3857 | ||
3858 | static int stv090x_sleep(struct dvb_frontend *fe) | |
3859 | { | |
3860 | struct stv090x_state *state = fe->demodulator_priv; | |
3861 | u32 reg; | |
5bd0dc2d | 3862 | u8 full_standby = 0; |
e415c689 | 3863 | |
85532d14 MA |
3864 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
3865 | goto err; | |
3866 | ||
3867 | if (state->config->tuner_sleep) { | |
c5b74b0f MA |
3868 | if (state->config->tuner_sleep(fe) < 0) |
3869 | goto err_gateoff; | |
3870 | } | |
3871 | ||
85532d14 MA |
3872 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
3873 | goto err; | |
3874 | ||
5bd0dc2d AR |
3875 | dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep", |
3876 | state->device == STV0900 ? "STV0900" : "STV0903", | |
3877 | state->demod); | |
e415c689 | 3878 | |
5bd0dc2d | 3879 | mutex_lock(&state->internal->demod_lock); |
e415c689 | 3880 | |
5bd0dc2d AR |
3881 | switch (state->demod) { |
3882 | case STV090x_DEMODULATOR_0: | |
3883 | /* power off ADC 1 */ | |
3884 | reg = stv090x_read_reg(state, STV090x_TSTTNR1); | |
3885 | STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); | |
3886 | if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) | |
3887 | goto err; | |
3888 | /* power off DiSEqC 1 */ | |
3889 | reg = stv090x_read_reg(state, STV090x_TSTTNR2); | |
3890 | STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); | |
3891 | if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) | |
3892 | goto err; | |
3893 | ||
3894 | /* check whether path 2 is already sleeping, that is when | |
3895 | ADC2 is off */ | |
3896 | reg = stv090x_read_reg(state, STV090x_TSTTNR3); | |
3897 | if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) | |
3898 | full_standby = 1; | |
3899 | ||
3900 | /* stop clocks */ | |
3901 | reg = stv090x_read_reg(state, STV090x_STOPCLK1); | |
3902 | /* packet delineator 1 clock */ | |
3903 | STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); | |
3904 | /* ADC 1 clock */ | |
3905 | STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); | |
3906 | /* FEC clock is shared between the two paths, only stop it | |
3907 | when full standby is possible */ | |
3908 | if (full_standby) | |
3909 | STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); | |
3910 | if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) | |
3911 | goto err; | |
3912 | reg = stv090x_read_reg(state, STV090x_STOPCLK2); | |
3913 | /* sampling 1 clock */ | |
3914 | STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); | |
3915 | /* viterbi 1 clock */ | |
3916 | STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); | |
3917 | /* TS clock is shared between the two paths, only stop it | |
3918 | when full standby is possible */ | |
3919 | if (full_standby) | |
3920 | STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); | |
3921 | if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) | |
3922 | goto err; | |
3923 | break; | |
26b03bc6 | 3924 | |
5bd0dc2d AR |
3925 | case STV090x_DEMODULATOR_1: |
3926 | /* power off ADC 2 */ | |
3927 | reg = stv090x_read_reg(state, STV090x_TSTTNR3); | |
3928 | STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); | |
3929 | if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) | |
3930 | goto err; | |
3931 | /* power off DiSEqC 2 */ | |
3932 | reg = stv090x_read_reg(state, STV090x_TSTTNR4); | |
3933 | STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); | |
3934 | if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) | |
3935 | goto err; | |
3936 | ||
3937 | /* check whether path 1 is already sleeping, that is when | |
3938 | ADC1 is off */ | |
3939 | reg = stv090x_read_reg(state, STV090x_TSTTNR1); | |
3940 | if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) | |
3941 | full_standby = 1; | |
3942 | ||
3943 | /* stop clocks */ | |
3944 | reg = stv090x_read_reg(state, STV090x_STOPCLK1); | |
3945 | /* packet delineator 2 clock */ | |
3946 | STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); | |
3947 | /* ADC 2 clock */ | |
3948 | STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); | |
3949 | /* FEC clock is shared between the two paths, only stop it | |
3950 | when full standby is possible */ | |
3951 | if (full_standby) | |
3952 | STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); | |
3953 | if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) | |
3954 | goto err; | |
3955 | reg = stv090x_read_reg(state, STV090x_STOPCLK2); | |
3956 | /* sampling 2 clock */ | |
3957 | STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); | |
3958 | /* viterbi 2 clock */ | |
3959 | STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); | |
3960 | /* TS clock is shared between the two paths, only stop it | |
3961 | when full standby is possible */ | |
3962 | if (full_standby) | |
3963 | STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); | |
3964 | if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) | |
3965 | goto err; | |
3966 | break; | |
3967 | ||
3968 | default: | |
3969 | dprintk(FE_ERROR, 1, "Wrong demodulator!"); | |
3970 | break; | |
3971 | } | |
3972 | ||
3973 | if (full_standby) { | |
3974 | /* general power off */ | |
3975 | reg = stv090x_read_reg(state, STV090x_SYNTCTRL); | |
3976 | STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); | |
3977 | if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) | |
3978 | goto err; | |
3979 | } | |
3980 | ||
3981 | mutex_unlock(&state->internal->demod_lock); | |
e415c689 | 3982 | return 0; |
c5b74b0f MA |
3983 | |
3984 | err_gateoff: | |
3985 | stv090x_i2c_gate_ctrl(state, 0); | |
e415c689 | 3986 | err: |
5bd0dc2d | 3987 | mutex_unlock(&state->internal->demod_lock); |
e415c689 MA |
3988 | dprintk(FE_ERROR, 1, "I/O error"); |
3989 | return -1; | |
3990 | } | |
3991 | ||
3992 | static int stv090x_wakeup(struct dvb_frontend *fe) | |
3993 | { | |
3994 | struct stv090x_state *state = fe->demodulator_priv; | |
3995 | u32 reg; | |
3996 | ||
5bd0dc2d AR |
3997 | dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby", |
3998 | state->device == STV0900 ? "STV0900" : "STV0903", | |
3999 | state->demod); | |
4000 | ||
4001 | mutex_lock(&state->internal->demod_lock); | |
e415c689 | 4002 | |
5bd0dc2d | 4003 | /* general power on */ |
e415c689 MA |
4004 | reg = stv090x_read_reg(state, STV090x_SYNTCTRL); |
4005 | STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); | |
4006 | if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) | |
4007 | goto err; | |
4008 | ||
5bd0dc2d AR |
4009 | switch (state->demod) { |
4010 | case STV090x_DEMODULATOR_0: | |
4011 | /* power on ADC 1 */ | |
4012 | reg = stv090x_read_reg(state, STV090x_TSTTNR1); | |
4013 | STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); | |
4014 | if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) | |
4015 | goto err; | |
4016 | /* power on DiSEqC 1 */ | |
4017 | reg = stv090x_read_reg(state, STV090x_TSTTNR2); | |
4018 | STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); | |
4019 | if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) | |
4020 | goto err; | |
4021 | ||
4022 | /* activate clocks */ | |
4023 | reg = stv090x_read_reg(state, STV090x_STOPCLK1); | |
4024 | /* packet delineator 1 clock */ | |
4025 | STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); | |
4026 | /* ADC 1 clock */ | |
4027 | STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); | |
4028 | /* FEC clock */ | |
4029 | STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); | |
4030 | if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) | |
4031 | goto err; | |
4032 | reg = stv090x_read_reg(state, STV090x_STOPCLK2); | |
4033 | /* sampling 1 clock */ | |
4034 | STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); | |
4035 | /* viterbi 1 clock */ | |
4036 | STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); | |
4037 | /* TS clock */ | |
4038 | STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); | |
4039 | if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) | |
4040 | goto err; | |
4041 | break; | |
26b03bc6 | 4042 | |
5bd0dc2d AR |
4043 | case STV090x_DEMODULATOR_1: |
4044 | /* power on ADC 2 */ | |
4045 | reg = stv090x_read_reg(state, STV090x_TSTTNR3); | |
4046 | STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); | |
4047 | if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) | |
4048 | goto err; | |
4049 | /* power on DiSEqC 2 */ | |
4050 | reg = stv090x_read_reg(state, STV090x_TSTTNR4); | |
4051 | STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); | |
4052 | if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) | |
4053 | goto err; | |
4054 | ||
4055 | /* activate clocks */ | |
4056 | reg = stv090x_read_reg(state, STV090x_STOPCLK1); | |
4057 | /* packet delineator 2 clock */ | |
4058 | STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); | |
4059 | /* ADC 2 clock */ | |
4060 | STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); | |
4061 | /* FEC clock */ | |
4062 | STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); | |
4063 | if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) | |
4064 | goto err; | |
4065 | reg = stv090x_read_reg(state, STV090x_STOPCLK2); | |
4066 | /* sampling 2 clock */ | |
4067 | STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); | |
4068 | /* viterbi 2 clock */ | |
4069 | STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); | |
4070 | /* TS clock */ | |
4071 | STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); | |
4072 | if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) | |
4073 | goto err; | |
4074 | break; | |
4075 | ||
4076 | default: | |
4077 | dprintk(FE_ERROR, 1, "Wrong demodulator!"); | |
4078 | break; | |
4079 | } | |
4080 | ||
4081 | mutex_unlock(&state->internal->demod_lock); | |
e415c689 MA |
4082 | return 0; |
4083 | err: | |
5bd0dc2d | 4084 | mutex_unlock(&state->internal->demod_lock); |
e415c689 MA |
4085 | dprintk(FE_ERROR, 1, "I/O error"); |
4086 | return -1; | |
4087 | } | |
4088 | ||
4089 | static void stv090x_release(struct dvb_frontend *fe) | |
4090 | { | |
4091 | struct stv090x_state *state = fe->demodulator_priv; | |
4092 | ||
97f7a2ae AR |
4093 | state->internal->num_used--; |
4094 | if (state->internal->num_used <= 0) { | |
4095 | ||
4096 | dprintk(FE_ERROR, 1, "Actually removing"); | |
4097 | ||
4098 | remove_dev(state->internal); | |
4099 | kfree(state->internal); | |
4100 | } | |
4101 | ||
e415c689 MA |
4102 | kfree(state); |
4103 | } | |
4104 | ||
4105 | static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) | |
4106 | { | |
27d40321 | 4107 | u32 reg = 0; |
e415c689 | 4108 | |
a4978a83 AR |
4109 | reg = stv090x_read_reg(state, STV090x_GENCFG); |
4110 | ||
e415c689 MA |
4111 | switch (ldpc_mode) { |
4112 | case STV090x_DUAL: | |
4113 | default: | |
e415c689 | 4114 | if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { |
27d40321 MA |
4115 | /* set LDPC to dual mode */ |
4116 | if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) | |
e415c689 | 4117 | goto err; |
27d40321 | 4118 | |
e415c689 | 4119 | state->demod_mode = STV090x_DUAL; |
27d40321 | 4120 | |
e415c689 MA |
4121 | reg = stv090x_read_reg(state, STV090x_TSTRES0); |
4122 | STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); | |
4123 | if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) | |
4124 | goto err; | |
4125 | STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); | |
4126 | if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) | |
4127 | goto err; | |
27d40321 MA |
4128 | |
4129 | if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) | |
4130 | goto err; | |
4131 | if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) | |
4132 | goto err; | |
4133 | if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) | |
4134 | goto err; | |
4135 | if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) | |
4136 | goto err; | |
4137 | if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) | |
4138 | goto err; | |
4139 | if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) | |
4140 | goto err; | |
4141 | if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) | |
4142 | goto err; | |
4143 | ||
4144 | if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) | |
4145 | goto err; | |
4146 | if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) | |
4147 | goto err; | |
4148 | if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) | |
4149 | goto err; | |
4150 | if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) | |
4151 | goto err; | |
4152 | if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) | |
4153 | goto err; | |
4154 | if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) | |
4155 | goto err; | |
4156 | if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) | |
4157 | goto err; | |
4158 | ||
4159 | if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) | |
4160 | goto err; | |
4161 | if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) | |
4162 | goto err; | |
e415c689 MA |
4163 | } |
4164 | break; | |
4165 | ||
4166 | case STV090x_SINGLE: | |
27d40321 MA |
4167 | if (stv090x_stop_modcod(state) < 0) |
4168 | goto err; | |
4169 | if (stv090x_activate_modcod_single(state) < 0) | |
4170 | goto err; | |
4171 | ||
e415c689 MA |
4172 | if (state->demod == STV090x_DEMODULATOR_1) { |
4173 | if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ | |
4174 | goto err; | |
4175 | } else { | |
4176 | if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ | |
4177 | goto err; | |
4178 | } | |
4179 | ||
4180 | reg = stv090x_read_reg(state, STV090x_TSTRES0); | |
4181 | STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); | |
4182 | if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) | |
4183 | goto err; | |
4184 | STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); | |
4185 | if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) | |
4186 | goto err; | |
4187 | ||
4188 | reg = STV090x_READ_DEMOD(state, PDELCTRL1); | |
4189 | STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); | |
4190 | if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) | |
4191 | goto err; | |
4192 | STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); | |
4193 | if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) | |
4194 | goto err; | |
4195 | break; | |
4196 | } | |
4197 | ||
4198 | return 0; | |
4199 | err: | |
4200 | dprintk(FE_ERROR, 1, "I/O error"); | |
4201 | return -1; | |
4202 | } | |
4203 | ||
4204 | /* return (Hz), clk in Hz*/ | |
4205 | static u32 stv090x_get_mclk(struct stv090x_state *state) | |
4206 | { | |
4207 | const struct stv090x_config *config = state->config; | |
4208 | u32 div, reg; | |
4209 | u8 ratio; | |
4210 | ||
4211 | div = stv090x_read_reg(state, STV090x_NCOARSE); | |
4212 | reg = stv090x_read_reg(state, STV090x_SYNTCTRL); | |
4213 | ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; | |
4214 | ||
4215 | return (div + 1) * config->xtal / ratio; /* kHz */ | |
4216 | } | |
4217 | ||
4218 | static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) | |
4219 | { | |
4220 | const struct stv090x_config *config = state->config; | |
4221 | u32 reg, div, clk_sel; | |
4222 | ||
4223 | reg = stv090x_read_reg(state, STV090x_SYNTCTRL); | |
4224 | clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); | |
4225 | ||
4226 | div = ((clk_sel * mclk) / config->xtal) - 1; | |
4227 | ||
4228 | reg = stv090x_read_reg(state, STV090x_NCOARSE); | |
4229 | STV090x_SETFIELD(reg, M_DIV_FIELD, div); | |
4230 | if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) | |
4231 | goto err; | |
4232 | ||
97f7a2ae | 4233 | state->internal->mclk = stv090x_get_mclk(state); |
e415c689 | 4234 | |
94a80914 | 4235 | /*Set the DiseqC frequency to 22KHz */ |
97f7a2ae | 4236 | div = state->internal->mclk / 704000; |
94a80914 MA |
4237 | if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) |
4238 | goto err; | |
4239 | if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) | |
4240 | goto err; | |
4241 | ||
e415c689 MA |
4242 | return 0; |
4243 | err: | |
4244 | dprintk(FE_ERROR, 1, "I/O error"); | |
4245 | return -1; | |
4246 | } | |
4247 | ||
4248 | static int stv090x_set_tspath(struct stv090x_state *state) | |
4249 | { | |
4250 | u32 reg; | |
4251 | ||
97f7a2ae | 4252 | if (state->internal->dev_ver >= 0x20) { |
e415c689 MA |
4253 | switch (state->config->ts1_mode) { |
4254 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4255 | case STV090x_TSMODE_DVBCI: | |
4256 | switch (state->config->ts2_mode) { | |
4257 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4258 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4259 | default: | |
4260 | stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); | |
4261 | break; | |
4262 | ||
4263 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4264 | case STV090x_TSMODE_DVBCI: | |
4265 | if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ | |
4266 | goto err; | |
4267 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); | |
4268 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); | |
4269 | if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) | |
4270 | goto err; | |
4271 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); | |
4272 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); | |
4273 | if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) | |
4274 | goto err; | |
4275 | if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) | |
4276 | goto err; | |
4277 | if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) | |
4278 | goto err; | |
4279 | break; | |
4280 | } | |
4281 | break; | |
4282 | ||
4283 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4284 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4285 | default: | |
4286 | switch (state->config->ts2_mode) { | |
4287 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4288 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4289 | default: | |
4290 | if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) | |
4291 | goto err; | |
4292 | break; | |
4293 | ||
4294 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4295 | case STV090x_TSMODE_DVBCI: | |
4296 | if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) | |
4297 | goto err; | |
4298 | break; | |
4299 | } | |
4300 | break; | |
4301 | } | |
4302 | } else { | |
4303 | switch (state->config->ts1_mode) { | |
4304 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4305 | case STV090x_TSMODE_DVBCI: | |
4306 | switch (state->config->ts2_mode) { | |
4307 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4308 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4309 | default: | |
56571507 | 4310 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); |
e415c689 MA |
4311 | break; |
4312 | ||
4313 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4314 | case STV090x_TSMODE_DVBCI: | |
56571507 | 4315 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); |
e415c689 MA |
4316 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); |
4317 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); | |
4318 | if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) | |
4319 | goto err; | |
4320 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); | |
4321 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); | |
4322 | if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) | |
4323 | goto err; | |
4324 | if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) | |
4325 | goto err; | |
4326 | if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) | |
4327 | goto err; | |
4328 | break; | |
4329 | } | |
4330 | break; | |
4331 | ||
4332 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4333 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4334 | default: | |
4335 | switch (state->config->ts2_mode) { | |
4336 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4337 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4338 | default: | |
56571507 | 4339 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); |
e415c689 MA |
4340 | break; |
4341 | ||
4342 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4343 | case STV090x_TSMODE_DVBCI: | |
56571507 | 4344 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); |
e415c689 MA |
4345 | break; |
4346 | } | |
4347 | break; | |
4348 | } | |
4349 | } | |
4350 | ||
4351 | switch (state->config->ts1_mode) { | |
4352 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4353 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); | |
4f7200a8 | 4354 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); |
e415c689 MA |
4355 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); |
4356 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); | |
4357 | if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) | |
4358 | goto err; | |
4359 | break; | |
4360 | ||
4361 | case STV090x_TSMODE_DVBCI: | |
4362 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); | |
4f7200a8 | 4363 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); |
e415c689 MA |
4364 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); |
4365 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); | |
4366 | if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) | |
4367 | goto err; | |
4368 | break; | |
4369 | ||
4370 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4371 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); | |
4f7200a8 | 4372 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); |
e415c689 MA |
4373 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); |
4374 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); | |
4375 | if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) | |
4376 | goto err; | |
4377 | break; | |
4378 | ||
4379 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4380 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); | |
4f7200a8 | 4381 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); |
e415c689 MA |
4382 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); |
4383 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); | |
4384 | if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) | |
4385 | goto err; | |
4386 | break; | |
4387 | ||
4388 | default: | |
4389 | break; | |
4390 | } | |
4391 | ||
4392 | switch (state->config->ts2_mode) { | |
4393 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
64104dc9 | 4394 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); |
4f7200a8 | 4395 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); |
e415c689 MA |
4396 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); |
4397 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); | |
64104dc9 | 4398 | if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) |
e415c689 MA |
4399 | goto err; |
4400 | break; | |
4401 | ||
4402 | case STV090x_TSMODE_DVBCI: | |
64104dc9 | 4403 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); |
4f7200a8 | 4404 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); |
e415c689 MA |
4405 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); |
4406 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); | |
64104dc9 | 4407 | if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) |
e415c689 MA |
4408 | goto err; |
4409 | break; | |
4410 | ||
4411 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
64104dc9 | 4412 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); |
4f7200a8 | 4413 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); |
e415c689 MA |
4414 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); |
4415 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); | |
64104dc9 | 4416 | if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) |
e415c689 MA |
4417 | goto err; |
4418 | break; | |
4419 | ||
4420 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
64104dc9 | 4421 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); |
4f7200a8 | 4422 | STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); |
e415c689 MA |
4423 | STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); |
4424 | STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); | |
64104dc9 | 4425 | if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) |
e415c689 MA |
4426 | goto err; |
4427 | break; | |
4428 | ||
4429 | default: | |
4430 | break; | |
4431 | } | |
f91e59cb AR |
4432 | |
4433 | if (state->config->ts1_clk > 0) { | |
4434 | u32 speed; | |
4435 | ||
4436 | switch (state->config->ts1_mode) { | |
4437 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4438 | case STV090x_TSMODE_DVBCI: | |
4439 | default: | |
4440 | speed = state->internal->mclk / | |
4441 | (state->config->ts1_clk / 4); | |
4442 | if (speed < 0x08) | |
4443 | speed = 0x08; | |
4444 | if (speed > 0xFF) | |
4445 | speed = 0xFF; | |
4446 | break; | |
4447 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4448 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4449 | speed = state->internal->mclk / | |
4450 | (state->config->ts1_clk / 32); | |
4451 | if (speed < 0x20) | |
4452 | speed = 0x20; | |
4453 | if (speed > 0xFF) | |
4454 | speed = 0xFF; | |
4455 | break; | |
4456 | } | |
4457 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); | |
4458 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); | |
4459 | if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) | |
4460 | goto err; | |
4461 | if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) | |
4462 | goto err; | |
4463 | } | |
4464 | ||
4465 | if (state->config->ts2_clk > 0) { | |
4466 | u32 speed; | |
4467 | ||
4468 | switch (state->config->ts2_mode) { | |
4469 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | |
4470 | case STV090x_TSMODE_DVBCI: | |
4471 | default: | |
4472 | speed = state->internal->mclk / | |
4473 | (state->config->ts2_clk / 4); | |
4474 | if (speed < 0x08) | |
4475 | speed = 0x08; | |
4476 | if (speed > 0xFF) | |
4477 | speed = 0xFF; | |
4478 | break; | |
4479 | case STV090x_TSMODE_SERIAL_PUNCTURED: | |
4480 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | |
4481 | speed = state->internal->mclk / | |
4482 | (state->config->ts2_clk / 32); | |
4483 | if (speed < 0x20) | |
4484 | speed = 0x20; | |
4485 | if (speed > 0xFF) | |
4486 | speed = 0xFF; | |
4487 | break; | |
4488 | } | |
4489 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); | |
4490 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); | |
4491 | if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) | |
4492 | goto err; | |
4493 | if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) | |
4494 | goto err; | |
4495 | } | |
4496 | ||
e415c689 MA |
4497 | reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); |
4498 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); | |
4499 | if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) | |
4500 | goto err; | |
4501 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); | |
4502 | if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) | |
4503 | goto err; | |
4504 | ||
4505 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); | |
4506 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); | |
4507 | if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) | |
4508 | goto err; | |
4509 | STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); | |
4510 | if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) | |
4511 | goto err; | |
4512 | ||
4513 | return 0; | |
4514 | err: | |
4515 | dprintk(FE_ERROR, 1, "I/O error"); | |
4516 | return -1; | |
4517 | } | |
4518 | ||
4519 | static int stv090x_init(struct dvb_frontend *fe) | |
4520 | { | |
4521 | struct stv090x_state *state = fe->demodulator_priv; | |
4522 | const struct stv090x_config *config = state->config; | |
4523 | u32 reg; | |
4524 | ||
9045e729 | 4525 | if (state->internal->mclk == 0) { |
5817ea0c AR |
4526 | /* call tuner init to configure the tuner's clock output |
4527 | divider directly before setting up the master clock of | |
4528 | the stv090x. */ | |
4529 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) | |
4530 | goto err; | |
4531 | ||
4532 | if (config->tuner_init) { | |
4533 | if (config->tuner_init(fe) < 0) | |
4534 | goto err_gateoff; | |
4535 | } | |
4536 | ||
4537 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) | |
4538 | goto err; | |
4539 | ||
9045e729 AR |
4540 | stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ |
4541 | msleep(5); | |
4542 | if (stv090x_write_reg(state, STV090x_SYNTCTRL, | |
4543 | 0x20 | config->clk_mode) < 0) | |
4544 | goto err; | |
4545 | stv090x_get_mclk(state); | |
4546 | } | |
4547 | ||
cbc320d2 AR |
4548 | if (stv090x_wakeup(fe) < 0) { |
4549 | dprintk(FE_ERROR, 1, "Error waking device"); | |
4550 | goto err; | |
4551 | } | |
4552 | ||
27d40321 MA |
4553 | if (stv090x_ldpc_mode(state, state->demod_mode) < 0) |
4554 | goto err; | |
e415c689 MA |
4555 | |
4556 | reg = STV090x_READ_DEMOD(state, TNRCFG2); | |
4557 | STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); | |
4558 | if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) | |
4559 | goto err; | |
4560 | reg = STV090x_READ_DEMOD(state, DEMOD); | |
4561 | STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); | |
4562 | if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) | |
4563 | goto err; | |
4564 | ||
19c4ee58 | 4565 | if (stv090x_i2c_gate_ctrl(state, 1) < 0) |
27d40321 | 4566 | goto err; |
e415c689 | 4567 | |
27d40321 MA |
4568 | if (config->tuner_set_mode) { |
4569 | if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) | |
2c1f750b | 4570 | goto err_gateoff; |
27d40321 | 4571 | } |
e415c689 | 4572 | |
27d40321 MA |
4573 | if (config->tuner_init) { |
4574 | if (config->tuner_init(fe) < 0) | |
2c1f750b | 4575 | goto err_gateoff; |
27d40321 MA |
4576 | } |
4577 | ||
19c4ee58 | 4578 | if (stv090x_i2c_gate_ctrl(state, 0) < 0) |
27d40321 | 4579 | goto err; |
e415c689 | 4580 | |
27d40321 MA |
4581 | if (stv090x_set_tspath(state) < 0) |
4582 | goto err; | |
e415c689 MA |
4583 | |
4584 | return 0; | |
2c1f750b OE |
4585 | |
4586 | err_gateoff: | |
19c4ee58 | 4587 | stv090x_i2c_gate_ctrl(state, 0); |
e415c689 MA |
4588 | err: |
4589 | dprintk(FE_ERROR, 1, "I/O error"); | |
4590 | return -1; | |
4591 | } | |
4592 | ||
4593 | static int stv090x_setup(struct dvb_frontend *fe) | |
4594 | { | |
4595 | struct stv090x_state *state = fe->demodulator_priv; | |
4596 | const struct stv090x_config *config = state->config; | |
4597 | const struct stv090x_reg *stv090x_initval = NULL; | |
4598 | const struct stv090x_reg *stv090x_cut20_val = NULL; | |
4599 | unsigned long t1_size = 0, t2_size = 0; | |
017eb038 | 4600 | u32 reg = 0; |
e415c689 MA |
4601 | |
4602 | int i; | |
4603 | ||
4604 | if (state->device == STV0900) { | |
4605 | dprintk(FE_DEBUG, 1, "Initializing STV0900"); | |
4606 | stv090x_initval = stv0900_initval; | |
4607 | t1_size = ARRAY_SIZE(stv0900_initval); | |
4608 | stv090x_cut20_val = stv0900_cut20_val; | |
4609 | t2_size = ARRAY_SIZE(stv0900_cut20_val); | |
4610 | } else if (state->device == STV0903) { | |
4611 | dprintk(FE_DEBUG, 1, "Initializing STV0903"); | |
4612 | stv090x_initval = stv0903_initval; | |
4613 | t1_size = ARRAY_SIZE(stv0903_initval); | |
4614 | stv090x_cut20_val = stv0903_cut20_val; | |
4615 | t2_size = ARRAY_SIZE(stv0903_cut20_val); | |
4616 | } | |
4617 | ||
4618 | /* STV090x init */ | |
97f7a2ae AR |
4619 | |
4620 | /* Stop Demod */ | |
4621 | if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) | |
4622 | goto err; | |
4623 | if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) | |
e415c689 MA |
4624 | goto err; |
4625 | ||
4626 | msleep(5); | |
4627 | ||
97f7a2ae AR |
4628 | /* Set No Tuner Mode */ |
4629 | if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) | |
4630 | goto err; | |
4631 | if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) | |
e415c689 MA |
4632 | goto err; |
4633 | ||
97f7a2ae | 4634 | /* I2C repeater OFF */ |
017eb038 | 4635 | STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); |
97f7a2ae AR |
4636 | if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) |
4637 | goto err; | |
4638 | if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) | |
e415c689 MA |
4639 | goto err; |
4640 | ||
4641 | if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ | |
4642 | goto err; | |
4643 | msleep(5); | |
4644 | if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ | |
4645 | goto err; | |
4646 | if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ | |
4647 | goto err; | |
4648 | msleep(5); | |
4649 | ||
4650 | /* write initval */ | |
2f5914be | 4651 | dprintk(FE_DEBUG, 1, "Setting up initial values"); |
e415c689 | 4652 | for (i = 0; i < t1_size; i++) { |
e415c689 MA |
4653 | if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) |
4654 | goto err; | |
4655 | } | |
4656 | ||
97f7a2ae AR |
4657 | state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); |
4658 | if (state->internal->dev_ver >= 0x20) { | |
e415c689 MA |
4659 | if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) |
4660 | goto err; | |
4661 | ||
4662 | /* write cut20_val*/ | |
4663 | dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); | |
4664 | for (i = 0; i < t2_size; i++) { | |
4665 | if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) | |
4666 | goto err; | |
4667 | } | |
27d40321 | 4668 | |
97f7a2ae | 4669 | } else if (state->internal->dev_ver < 0x20) { |
27d40321 | 4670 | dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", |
97f7a2ae | 4671 | state->internal->dev_ver); |
27d40321 MA |
4672 | |
4673 | goto err; | |
97f7a2ae | 4674 | } else if (state->internal->dev_ver > 0x30) { |
27d40321 MA |
4675 | /* we shouldn't bail out from here */ |
4676 | dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", | |
97f7a2ae | 4677 | state->internal->dev_ver); |
e415c689 MA |
4678 | } |
4679 | ||
d8b5a8e4 OE |
4680 | /* ADC1 range */ |
4681 | reg = stv090x_read_reg(state, STV090x_TSTTNR1); | |
4682 | STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, | |
4683 | (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); | |
4684 | if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) | |
4685 | goto err; | |
4686 | ||
4687 | /* ADC2 range */ | |
4688 | reg = stv090x_read_reg(state, STV090x_TSTTNR3); | |
4689 | STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, | |
4690 | (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); | |
4691 | if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) | |
4692 | goto err; | |
4693 | ||
e415c689 MA |
4694 | if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) |
4695 | goto err; | |
4696 | if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) | |
4697 | goto err; | |
4698 | ||
e415c689 MA |
4699 | return 0; |
4700 | err: | |
4701 | dprintk(FE_ERROR, 1, "I/O error"); | |
4702 | return -1; | |
4703 | } | |
4704 | ||
b4797048 PB |
4705 | int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value, |
4706 | u8 xor_value) | |
4707 | { | |
4708 | struct stv090x_state *state = fe->demodulator_priv; | |
4709 | u8 reg = 0; | |
4710 | ||
4711 | STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); | |
4712 | STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); | |
4713 | STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); | |
4714 | ||
4715 | return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); | |
4716 | } | |
4717 | EXPORT_SYMBOL(stv090x_set_gpio); | |
4718 | ||
e415c689 MA |
4719 | static struct dvb_frontend_ops stv090x_ops = { |
4720 | ||
4721 | .info = { | |
4722 | .name = "STV090x Multistandard", | |
7fc08bbb AR |
4723 | .type = FE_QPSK, |
4724 | .frequency_min = 950000, | |
4725 | .frequency_max = 2150000, | |
4726 | .frequency_stepsize = 0, | |
4727 | .frequency_tolerance = 0, | |
4728 | .symbol_rate_min = 1000000, | |
4729 | .symbol_rate_max = 45000000, | |
4730 | .caps = FE_CAN_INVERSION_AUTO | | |
4731 | FE_CAN_FEC_AUTO | | |
4732 | FE_CAN_QPSK | | |
4733 | FE_CAN_2G_MODULATION | |
e415c689 MA |
4734 | }, |
4735 | ||
4736 | .release = stv090x_release, | |
4737 | .init = stv090x_init, | |
4738 | ||
4739 | .sleep = stv090x_sleep, | |
4740 | .get_frontend_algo = stv090x_frontend_algo, | |
4741 | ||
e415c689 | 4742 | .diseqc_send_master_cmd = stv090x_send_diseqc_msg, |
f9ed95d0 | 4743 | .diseqc_send_burst = stv090x_send_diseqc_burst, |
e415c689 MA |
4744 | .diseqc_recv_slave_reply = stv090x_recv_slave_reply, |
4745 | .set_tone = stv090x_set_tone, | |
4746 | ||
4747 | .search = stv090x_search, | |
4748 | .read_status = stv090x_read_status, | |
4749 | .read_ber = stv090x_read_per, | |
4750 | .read_signal_strength = stv090x_read_signal_strength, | |
4751 | .read_snr = stv090x_read_cnr | |
4752 | }; | |
4753 | ||
4754 | ||
4755 | struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, | |
4756 | struct i2c_adapter *i2c, | |
4757 | enum stv090x_demodulator demod) | |
4758 | { | |
4759 | struct stv090x_state *state = NULL; | |
97f7a2ae | 4760 | struct stv090x_dev *temp_int; |
e415c689 MA |
4761 | |
4762 | state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); | |
4763 | if (state == NULL) | |
4764 | goto error; | |
4765 | ||
4766 | state->verbose = &verbose; | |
4767 | state->config = config; | |
4768 | state->i2c = i2c; | |
4769 | state->frontend.ops = stv090x_ops; | |
4770 | state->frontend.demodulator_priv = state; | |
56571507 | 4771 | state->demod = demod; |
e415c689 MA |
4772 | state->demod_mode = config->demod_mode; /* Single or Dual mode */ |
4773 | state->device = config->device; | |
4e58a682 | 4774 | state->rolloff = STV090x_RO_35; /* default */ |
e415c689 | 4775 | |
97f7a2ae AR |
4776 | temp_int = find_dev(state->i2c, |
4777 | state->config->address); | |
4778 | ||
4779 | if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { | |
4780 | state->internal = temp_int->internal; | |
4781 | state->internal->num_used++; | |
4782 | dprintk(FE_INFO, 1, "Found Internal Structure!"); | |
97f7a2ae AR |
4783 | } else { |
4784 | state->internal = kmalloc(sizeof(struct stv090x_internal), | |
4785 | GFP_KERNEL); | |
07988007 DC |
4786 | if (!state->internal) |
4787 | goto error; | |
97f7a2ae | 4788 | temp_int = append_internal(state->internal); |
07988007 DC |
4789 | if (!temp_int) { |
4790 | kfree(state->internal); | |
4791 | goto error; | |
4792 | } | |
97f7a2ae | 4793 | state->internal->num_used = 1; |
76b9ef97 AR |
4794 | state->internal->mclk = 0; |
4795 | state->internal->dev_ver = 0; | |
97f7a2ae AR |
4796 | state->internal->i2c_adap = state->i2c; |
4797 | state->internal->i2c_addr = state->config->address; | |
4798 | dprintk(FE_INFO, 1, "Create New Internal Structure!"); | |
97f7a2ae | 4799 | |
4862d6b2 OE |
4800 | mutex_init(&state->internal->demod_lock); |
4801 | mutex_init(&state->internal->tuner_lock); | |
e415c689 | 4802 | |
4862d6b2 OE |
4803 | if (stv090x_setup(&state->frontend) < 0) { |
4804 | dprintk(FE_ERROR, 1, "Error setting up device"); | |
07988007 | 4805 | goto err_remove; |
4862d6b2 | 4806 | } |
e415c689 | 4807 | } |
4862d6b2 OE |
4808 | |
4809 | /* workaround for stuck DiSEqC output */ | |
4810 | if (config->diseqc_envelope_mode) | |
4811 | stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A); | |
4812 | ||
97f7a2ae | 4813 | dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", |
e415c689 MA |
4814 | state->device == STV0900 ? "STV0900" : "STV0903", |
4815 | demod, | |
97f7a2ae | 4816 | state->internal->dev_ver); |
e415c689 MA |
4817 | |
4818 | return &state->frontend; | |
4819 | ||
07988007 DC |
4820 | err_remove: |
4821 | remove_dev(state->internal); | |
4822 | kfree(state->internal); | |
e415c689 MA |
4823 | error: |
4824 | kfree(state); | |
4825 | return NULL; | |
4826 | } | |
4827 | EXPORT_SYMBOL(stv090x_attach); | |
4828 | MODULE_PARM_DESC(verbose, "Set Verbosity level"); | |
4829 | MODULE_AUTHOR("Manu Abraham"); | |
4830 | MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); | |
4831 | MODULE_LICENSE("GPL"); |