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V4L/DVB (11589): stv090x: code simplification
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb / frontends / stv090x.c
CommitLineData
e415c689
MA		 1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/mutex.h>
27
28#include <linux/dvb/frontend.h>
29#include "dvb_frontend.h"
30
31#include "stv6110x.h" /* for demodulator internal modes */
32
33#include "stv090x_reg.h"
34#include "stv090x.h"
35#include "stv090x_priv.h"
36
37static unsigned int verbose;
38module_param(verbose, int, 0644);
39
40struct mutex demod_lock;
41
42/* DVBS1 and DSS C/N Lookup table */
43static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
96};
97
98/* DVBS2 C/N Lookup table */
99static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
155};
156
157/* RF level C/N lookup table */
158static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
173};
174
175
176static struct stv090x_reg stv0900_initval[] = {
177
178 { STV090x_OUTCFG, 0x00 },
56571507 179 { STV090x_MODECFG, 0xff },
e415c689
MA		 180 { STV090x_AGCRF1CFG, 0x11 },
181 { STV090x_AGCRF2CFG, 0x13 },
56571507 182 { STV090x_TSGENERAL1X, 0x14 },
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MA		 183 { STV090x_TSTTNR2, 0x21 },
184 { STV090x_TSTTNR4, 0x21 },
185 { STV090x_P2_DISTXCTL, 0x22 },
186 { STV090x_P2_F22TX, 0xc0 },
187 { STV090x_P2_F22RX, 0xc0 },
188 { STV090x_P2_DISRXCTL, 0x00 },
189 { STV090x_P2_DMDCFGMD, 0xF9 },
190 { STV090x_P2_DEMOD, 0x08 },
191 { STV090x_P2_DMDCFG3, 0xc4 },
192 { STV090x_P2_CARFREQ, 0xed },
193 { STV090x_P2_LDT, 0xd0 },
194 { STV090x_P2_LDT2, 0xb8 },
195 { STV090x_P2_TMGCFG, 0xd2 },
196 { STV090x_P2_TMGTHRISE, 0x20 },
197 { STV090x_P1_TMGCFG, 0xd2 },
198
199 { STV090x_P2_TMGTHFALL, 0x00 },
200 { STV090x_P2_FECSPY, 0x88 },
201 { STV090x_P2_FSPYDATA, 0x3a },
202 { STV090x_P2_FBERCPT4, 0x00 },
203 { STV090x_P2_FSPYBER, 0x10 },
204 { STV090x_P2_ERRCTRL1, 0x35 },
205 { STV090x_P2_ERRCTRL2, 0xc1 },
206 { STV090x_P2_CFRICFG, 0xf8 },
207 { STV090x_P2_NOSCFG, 0x1c },
56571507 208 { STV090x_P2_DMDTOM, 0x20 },
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MA		 209 { STV090x_P2_CORRELMANT, 0x70 },
210 { STV090x_P2_CORRELABS, 0x88 },
56571507 211 { STV090x_P2_AGC2O, 0x5b },
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MA		 212 { STV090x_P2_AGC2REF, 0x38 },
213 { STV090x_P2_CARCFG, 0xe4 },
214 { STV090x_P2_ACLC, 0x1A },
215 { STV090x_P2_BCLC, 0x09 },
216 { STV090x_P2_CARHDR, 0x08 },
217 { STV090x_P2_KREFTMG, 0xc1 },
218 { STV090x_P2_SFRUPRATIO, 0xf0 },
219 { STV090x_P2_SFRLOWRATIO, 0x70 },
220 { STV090x_P2_SFRSTEP, 0x58 },
221 { STV090x_P2_TMGCFG2, 0x01 },
222 { STV090x_P2_CAR2CFG, 0x26 },
223 { STV090x_P2_BCLC2S2Q, 0x86 },
224 { STV090x_P2_BCLC2S28, 0x86 },
225 { STV090x_P2_SMAPCOEF7, 0x77 },
226 { STV090x_P2_SMAPCOEF6, 0x85 },
227 { STV090x_P2_SMAPCOEF5, 0x77 },
228 { STV090x_P2_TSCFGL, 0x20 },
229 { STV090x_P2_DMDCFG2, 0x3b },
230 { STV090x_P2_MODCODLST0, 0xff },
231 { STV090x_P2_MODCODLST1, 0xff },
232 { STV090x_P2_MODCODLST2, 0xff },
233 { STV090x_P2_MODCODLST3, 0xff },
234 { STV090x_P2_MODCODLST4, 0xff },
235 { STV090x_P2_MODCODLST5, 0xff },
236 { STV090x_P2_MODCODLST6, 0xff },
237 { STV090x_P2_MODCODLST7, 0xcc },
238 { STV090x_P2_MODCODLST8, 0xcc },
239 { STV090x_P2_MODCODLST9, 0xcc },
240 { STV090x_P2_MODCODLSTA, 0xcc },
241 { STV090x_P2_MODCODLSTB, 0xcc },
242 { STV090x_P2_MODCODLSTC, 0xcc },
243 { STV090x_P2_MODCODLSTD, 0xcc },
244 { STV090x_P2_MODCODLSTE, 0xcc },
245 { STV090x_P2_MODCODLSTF, 0xcf },
246 { STV090x_P1_DISTXCTL, 0x22 },
247 { STV090x_P1_F22TX, 0xc0 },
248 { STV090x_P1_F22RX, 0xc0 },
249 { STV090x_P1_DISRXCTL, 0x00 },
250 { STV090x_P1_DMDCFGMD, 0xf9 },
251 { STV090x_P1_DEMOD, 0x08 },
252 { STV090x_P1_DMDCFG3, 0xc4 },
56571507 253 { STV090x_P1_DMDTOM, 0x20 },
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MA		 254 { STV090x_P1_CARFREQ, 0xed },
255 { STV090x_P1_LDT, 0xd0 },
256 { STV090x_P1_LDT2, 0xb8 },
257 { STV090x_P1_TMGCFG, 0xd2 },
258 { STV090x_P1_TMGTHRISE, 0x20 },
259 { STV090x_P1_TMGTHFALL, 0x00 },
260 { STV090x_P1_SFRUPRATIO, 0xf0 },
261 { STV090x_P1_SFRLOWRATIO, 0x70 },
262 { STV090x_P1_TSCFGL, 0x20 },
263 { STV090x_P1_FECSPY, 0x88 },
264 { STV090x_P1_FSPYDATA, 0x3a },
265 { STV090x_P1_FBERCPT4, 0x00 },
266 { STV090x_P1_FSPYBER, 0x10 },
267 { STV090x_P1_ERRCTRL1, 0x35 },
268 { STV090x_P1_ERRCTRL2, 0xc1 },
269 { STV090x_P1_CFRICFG, 0xf8 },
270 { STV090x_P1_NOSCFG, 0x1c },
271 { STV090x_P1_CORRELMANT, 0x70 },
272 { STV090x_P1_CORRELABS, 0x88 },
56571507 273 { STV090x_P1_AGC2O, 0x5b },
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MA		 274 { STV090x_P1_AGC2REF, 0x38 },
275 { STV090x_P1_CARCFG, 0xe4 },
276 { STV090x_P1_ACLC, 0x1A },
277 { STV090x_P1_BCLC, 0x09 },
278 { STV090x_P1_CARHDR, 0x08 },
279 { STV090x_P1_KREFTMG, 0xc1 },
280 { STV090x_P1_SFRSTEP, 0x58 },
281 { STV090x_P1_TMGCFG2, 0x01 },
282 { STV090x_P1_CAR2CFG, 0x26 },
283 { STV090x_P1_BCLC2S2Q, 0x86 },
284 { STV090x_P1_BCLC2S28, 0x86 },
285 { STV090x_P1_SMAPCOEF7, 0x77 },
286 { STV090x_P1_SMAPCOEF6, 0x85 },
287 { STV090x_P1_SMAPCOEF5, 0x77 },
288 { STV090x_P1_DMDCFG2, 0x3b },
289 { STV090x_P1_MODCODLST0, 0xff },
290 { STV090x_P1_MODCODLST1, 0xff },
291 { STV090x_P1_MODCODLST2, 0xff },
292 { STV090x_P1_MODCODLST3, 0xff },
293 { STV090x_P1_MODCODLST4, 0xff },
294 { STV090x_P1_MODCODLST5, 0xff },
295 { STV090x_P1_MODCODLST6, 0xff },
296 { STV090x_P1_MODCODLST7, 0xcc },
297 { STV090x_P1_MODCODLST8, 0xcc },
298 { STV090x_P1_MODCODLST9, 0xcc },
299 { STV090x_P1_MODCODLSTA, 0xcc },
300 { STV090x_P1_MODCODLSTB, 0xcc },
301 { STV090x_P1_MODCODLSTC, 0xcc },
302 { STV090x_P1_MODCODLSTD, 0xcc },
303 { STV090x_P1_MODCODLSTE, 0xcc },
304 { STV090x_P1_MODCODLSTF, 0xcf },
305 { STV090x_GENCFG, 0x1d },
306 { STV090x_NBITER_NF4, 0x37 },
307 { STV090x_NBITER_NF5, 0x29 },
308 { STV090x_NBITER_NF6, 0x37 },
309 { STV090x_NBITER_NF7, 0x33 },
310 { STV090x_NBITER_NF8, 0x31 },
311 { STV090x_NBITER_NF9, 0x2f },
312 { STV090x_NBITER_NF10, 0x39 },
313 { STV090x_NBITER_NF11, 0x3a },
314 { STV090x_NBITER_NF12, 0x29 },
315 { STV090x_NBITER_NF13, 0x37 },
316 { STV090x_NBITER_NF14, 0x33 },
317 { STV090x_NBITER_NF15, 0x2f },
318 { STV090x_NBITER_NF16, 0x39 },
319 { STV090x_NBITER_NF17, 0x3a },
320 { STV090x_NBITERNOERR, 0x04 },
321 { STV090x_GAINLLR_NF4, 0x0C },
322 { STV090x_GAINLLR_NF5, 0x0F },
323 { STV090x_GAINLLR_NF6, 0x11 },
324 { STV090x_GAINLLR_NF7, 0x14 },
325 { STV090x_GAINLLR_NF8, 0x17 },
326 { STV090x_GAINLLR_NF9, 0x19 },
327 { STV090x_GAINLLR_NF10, 0x20 },
328 { STV090x_GAINLLR_NF11, 0x21 },
329 { STV090x_GAINLLR_NF12, 0x0D },
330 { STV090x_GAINLLR_NF13, 0x0F },
331 { STV090x_GAINLLR_NF14, 0x13 },
332 { STV090x_GAINLLR_NF15, 0x1A },
333 { STV090x_GAINLLR_NF16, 0x1F },
334 { STV090x_GAINLLR_NF17, 0x21 },
56571507 335 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 336 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
337 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
338 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
339 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
340};
341
342static struct stv090x_reg stv0903_initval[] = {
343 { STV090x_OUTCFG, 0x00 },
344 { STV090x_AGCRF1CFG, 0x11 },
345 { STV090x_STOPCLK1, 0x48 },
346 { STV090x_STOPCLK2, 0x14 },
347 { STV090x_TSTTNR1, 0x27 },
348 { STV090x_TSTTNR2, 0x21 },
349 { STV090x_P1_DISTXCTL, 0x22 },
350 { STV090x_P1_F22TX, 0xc0 },
351 { STV090x_P1_F22RX, 0xc0 },
352 { STV090x_P1_DISRXCTL, 0x00 },
353 { STV090x_P1_DMDCFGMD, 0xF9 },
354 { STV090x_P1_DEMOD, 0x08 },
355 { STV090x_P1_DMDCFG3, 0xc4 },
356 { STV090x_P1_CARFREQ, 0xed },
357 { STV090x_P1_TNRCFG2, 0x82 },
358 { STV090x_P1_LDT, 0xd0 },
359 { STV090x_P1_LDT2, 0xb8 },
360 { STV090x_P1_TMGCFG, 0xd2 },
361 { STV090x_P1_TMGTHRISE, 0x20 },
362 { STV090x_P1_TMGTHFALL, 0x00 },
363 { STV090x_P1_SFRUPRATIO, 0xf0 },
364 { STV090x_P1_SFRLOWRATIO, 0x70 },
365 { STV090x_P1_TSCFGL, 0x20 },
366 { STV090x_P1_FECSPY, 0x88 },
367 { STV090x_P1_FSPYDATA, 0x3a },
368 { STV090x_P1_FBERCPT4, 0x00 },
369 { STV090x_P1_FSPYBER, 0x10 },
370 { STV090x_P1_ERRCTRL1, 0x35 },
371 { STV090x_P1_ERRCTRL2, 0xc1 },
372 { STV090x_P1_CFRICFG, 0xf8 },
373 { STV090x_P1_NOSCFG, 0x1c },
56571507 374 { STV090x_P1_DMDTOM, 0x20 },
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MA		 375 { STV090x_P1_CORRELMANT, 0x70 },
376 { STV090x_P1_CORRELABS, 0x88 },
56571507
MA		 377 { STV090x_P1_AGC2O, 0x5b },
378 { STV090x_P1_AGC2REF, 0x38 },
e415c689
MA		 379 { STV090x_P1_CARCFG, 0xe4 },
380 { STV090x_P1_ACLC, 0x1A },
56571507 381 { STV090x_P1_BCLC, 0x09 },
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MA		 382 { STV090x_P1_CARHDR, 0x08 },
383 { STV090x_P1_KREFTMG, 0xc1 },
384 { STV090x_P1_SFRSTEP, 0x58 },
385 { STV090x_P1_TMGCFG2, 0x01 },
386 { STV090x_P1_CAR2CFG, 0x26 },
387 { STV090x_P1_BCLC2S2Q, 0x86 },
388 { STV090x_P1_BCLC2S28, 0x86 },
389 { STV090x_P1_SMAPCOEF7, 0x77 },
390 { STV090x_P1_SMAPCOEF6, 0x85 },
391 { STV090x_P1_SMAPCOEF5, 0x77 },
392 { STV090x_P1_DMDCFG2, 0x3b },
393 { STV090x_P1_MODCODLST0, 0xff },
394 { STV090x_P1_MODCODLST1, 0xff },
395 { STV090x_P1_MODCODLST2, 0xff },
396 { STV090x_P1_MODCODLST3, 0xff },
397 { STV090x_P1_MODCODLST4, 0xff },
398 { STV090x_P1_MODCODLST5, 0xff },
399 { STV090x_P1_MODCODLST6, 0xff },
400 { STV090x_P1_MODCODLST7, 0xcc },
401 { STV090x_P1_MODCODLST8, 0xcc },
402 { STV090x_P1_MODCODLST9, 0xcc },
403 { STV090x_P1_MODCODLSTA, 0xcc },
404 { STV090x_P1_MODCODLSTB, 0xcc },
405 { STV090x_P1_MODCODLSTC, 0xcc },
406 { STV090x_P1_MODCODLSTD, 0xcc },
407 { STV090x_P1_MODCODLSTE, 0xcc },
408 { STV090x_P1_MODCODLSTF, 0xcf },
409 { STV090x_GENCFG, 0x1c },
410 { STV090x_NBITER_NF4, 0x37 },
411 { STV090x_NBITER_NF5, 0x29 },
412 { STV090x_NBITER_NF6, 0x37 },
413 { STV090x_NBITER_NF7, 0x33 },
414 { STV090x_NBITER_NF8, 0x31 },
415 { STV090x_NBITER_NF9, 0x2f },
416 { STV090x_NBITER_NF10, 0x39 },
417 { STV090x_NBITER_NF11, 0x3a },
418 { STV090x_NBITER_NF12, 0x29 },
419 { STV090x_NBITER_NF13, 0x37 },
420 { STV090x_NBITER_NF14, 0x33 },
421 { STV090x_NBITER_NF15, 0x2f },
422 { STV090x_NBITER_NF16, 0x39 },
423 { STV090x_NBITER_NF17, 0x3a },
424 { STV090x_NBITERNOERR, 0x04 },
425 { STV090x_GAINLLR_NF4, 0x0C },
426 { STV090x_GAINLLR_NF5, 0x0F },
427 { STV090x_GAINLLR_NF6, 0x11 },
428 { STV090x_GAINLLR_NF7, 0x14 },
429 { STV090x_GAINLLR_NF8, 0x17 },
430 { STV090x_GAINLLR_NF9, 0x19 },
431 { STV090x_GAINLLR_NF10, 0x20 },
432 { STV090x_GAINLLR_NF11, 0x21 },
433 { STV090x_GAINLLR_NF12, 0x0D },
434 { STV090x_GAINLLR_NF13, 0x0F },
435 { STV090x_GAINLLR_NF14, 0x13 },
436 { STV090x_GAINLLR_NF15, 0x1A },
437 { STV090x_GAINLLR_NF16, 0x1F },
438 { STV090x_GAINLLR_NF17, 0x21 },
56571507 439 { STV090x_RCCFGH, 0x20 },
e415c689
MA		 440 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
441 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
442};
443
444static struct stv090x_reg stv0900_cut20_val[] = {
445
446 { STV090x_P2_DMDCFG3, 0xe8 },
56571507 447 { STV090x_P2_DMDCFG4, 0x10 },
e415c689
MA		 448 { STV090x_P2_CARFREQ, 0x38 },
449 { STV090x_P2_CARHDR, 0x20 },
450 { STV090x_P2_KREFTMG, 0x5a },
451 { STV090x_P2_SMAPCOEF7, 0x06 },
452 { STV090x_P2_SMAPCOEF6, 0x00 },
453 { STV090x_P2_SMAPCOEF5, 0x04 },
454 { STV090x_P2_NOSCFG, 0x0c },
455 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 456 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 457 { STV090x_P1_CARFREQ, 0x38 },
458 { STV090x_P1_CARHDR, 0x20 },
459 { STV090x_P1_KREFTMG, 0x5a },
460 { STV090x_P1_SMAPCOEF7, 0x06 },
461 { STV090x_P1_SMAPCOEF6, 0x00 },
462 { STV090x_P1_SMAPCOEF5, 0x04 },
463 { STV090x_P1_NOSCFG, 0x0c },
464 { STV090x_GAINLLR_NF4, 0x21 },
465 { STV090x_GAINLLR_NF5, 0x21 },
466 { STV090x_GAINLLR_NF6, 0x20 },
467 { STV090x_GAINLLR_NF7, 0x1F },
468 { STV090x_GAINLLR_NF8, 0x1E },
469 { STV090x_GAINLLR_NF9, 0x1E },
470 { STV090x_GAINLLR_NF10, 0x1D },
471 { STV090x_GAINLLR_NF11, 0x1B },
472 { STV090x_GAINLLR_NF12, 0x20 },
473 { STV090x_GAINLLR_NF13, 0x20 },
474 { STV090x_GAINLLR_NF14, 0x20 },
475 { STV090x_GAINLLR_NF15, 0x20 },
476 { STV090x_GAINLLR_NF16, 0x20 },
477 { STV090x_GAINLLR_NF17, 0x21 },
478};
479
480static struct stv090x_reg stv0903_cut20_val[] = {
481 { STV090x_P1_DMDCFG3, 0xe8 },
56571507 482 { STV090x_P1_DMDCFG4, 0x10 },
e415c689
MA		 483 { STV090x_P1_CARFREQ, 0x38 },
484 { STV090x_P1_CARHDR, 0x20 },
485 { STV090x_P1_KREFTMG, 0x5a },
486 { STV090x_P1_SMAPCOEF7, 0x06 },
487 { STV090x_P1_SMAPCOEF6, 0x00 },
488 { STV090x_P1_SMAPCOEF5, 0x04 },
489 { STV090x_P1_NOSCFG, 0x0c },
490 { STV090x_GAINLLR_NF4, 0x21 },
491 { STV090x_GAINLLR_NF5, 0x21 },
492 { STV090x_GAINLLR_NF6, 0x20 },
493 { STV090x_GAINLLR_NF7, 0x1F },
494 { STV090x_GAINLLR_NF8, 0x1E },
495 { STV090x_GAINLLR_NF9, 0x1E },
496 { STV090x_GAINLLR_NF10, 0x1D },
497 { STV090x_GAINLLR_NF11, 0x1B },
498 { STV090x_GAINLLR_NF12, 0x20 },
499 { STV090x_GAINLLR_NF13, 0x20 },
500 { STV090x_GAINLLR_NF14, 0x20 },
501 { STV090x_GAINLLR_NF15, 0x20 },
502 { STV090x_GAINLLR_NF16, 0x20 },
503 { STV090x_GAINLLR_NF17, 0x21 }
504};
505
506/* Cut 1.x Long Frame Tracking CR loop */
507static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
508 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
509 { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
510 { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
511 { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
512 { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
513 { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
514 { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
515 { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
516 { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
517 { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
518 { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
519 { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
520 { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
521 { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
522 { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
523};
524
525/* Cut 2.0 Long Frame Tracking CR loop */
526static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
527 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
528 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
529 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
530 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
531 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
532 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
533 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
534 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
535 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
536 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
537 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
538 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
539 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
540 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
541 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
542};
543
544
545/* Cut 2.0 Long Frame Tracking CR Loop */
546static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
547 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
548 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
549 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
550 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
551 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
552 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
553 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
554 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
555 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
556 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
557 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
558 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
559};
560
561
562static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
563 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
564 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
565 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
566 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
567};
568
569
570/* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
571static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
572 /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
573 { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
574 { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
575 { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
576 { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
577};
578
579
580static inline s32 comp2(s32 __x, s32 __width)
581{
582 if (__width == 32)
583 return __x;
584 else
585 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
586}
587
588static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
589{
590 const struct stv090x_config *config = state->config;
591 int ret;
592
593 u8 b0[] = { reg >> 8, reg & 0xff };
594 u8 buf;
595
596 struct i2c_msg msg[] = {
597 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
598 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
599 };
600
601 ret = i2c_transfer(state->i2c, msg, 2);
602 if (ret != 2) {
603 if (ret != -ERESTARTSYS)
604 dprintk(FE_ERROR, 1,
605 "Read error, Reg=[0x%02x], Status=%d",
606 reg, ret);
607
608 return ret < 0 ? ret : -EREMOTEIO;
609 }
610 if (unlikely(*state->verbose >= FE_DEBUGREG))
611 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
612 reg, buf);
613
614 return (unsigned int) buf;
615}
616
617static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
618{
619 const struct stv090x_config *config = state->config;
620 int ret;
621 u8 buf[2 + count];
622 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
623
624 buf[0] = reg >> 8;
625 buf[1] = reg & 0xff;
626 memcpy(&buf[2], data, count);
627
628 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
629 int i;
630
631 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
632 for (i = 0; i < count; i++)
633 printk(" %02x", data[i]);
634 printk("\n");
635 }
636
637 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
638 if (ret != 1) {
639 if (ret != -ERESTARTSYS)
640 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
641 reg, data[0], count, ret);
642 return ret < 0 ? ret : -EREMOTEIO;
643 }
644
645 return 0;
646}
647
648static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
649{
650 return stv090x_write_regs(state, reg, &data, 1);
651}
652
653static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
654{
655 struct stv090x_state *state = fe->demodulator_priv;
656 u32 reg;
657
658 reg = STV090x_READ_DEMOD(state, I2CRPT);
e415c689 659 if (enable) {
017eb038 660 dprintk(FE_DEBUG, 1, "Enable Gate");
e415c689
MA		 661 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
662 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
663 goto err;
664
665 } else {
017eb038 666 dprintk(FE_DEBUG, 1, "Disable Gate");
e415c689
MA		 667 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
668 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
669 goto err;
670 }
671 return 0;
672err:
673 dprintk(FE_ERROR, 1, "I/O error");
674 return -1;
675}
676
677static void stv090x_get_lock_tmg(struct stv090x_state *state)
678{
679 switch (state->algo) {
680 case STV090x_BLIND_SEARCH:
681 dprintk(FE_DEBUG, 1, "Blind Search");
682 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
683 state->DemodTimeout = 1500;
684 state->FecTimeout = 400;
685 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
686 state->DemodTimeout = 1000;
687 state->FecTimeout = 300;
688 } else { /*SR >20Msps*/
689 state->DemodTimeout = 700;
690 state->FecTimeout = 100;
691 }
692 break;
693
694 case STV090x_COLD_SEARCH:
695 case STV090x_WARM_SEARCH:
696 default:
697 dprintk(FE_DEBUG, 1, "Normal Search");
698 if (state->srate <= 1000000) { /*SR <=1Msps*/
699 state->DemodTimeout = 4500;
700 state->FecTimeout = 1700;
701 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
702 state->DemodTimeout = 2500;
703 state->FecTimeout = 1100;
704 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
705 state->DemodTimeout = 1000;
706 state->FecTimeout = 550;
707 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
708 state->DemodTimeout = 700;
709 state->FecTimeout = 250;
710 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
711 state->DemodTimeout = 400;
712 state->FecTimeout = 130;
713 } else { /*SR >20Msps*/
714 state->DemodTimeout = 300;
715 state->FecTimeout = 100;
716 }
717 break;
718 }
719
720 if (state->algo == STV090x_WARM_SEARCH)
721 state->DemodTimeout /= 2;
722}
723
724static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
725{
726 u32 sym;
727
15bb366e
MA		 728 if (srate > 60000000) {
729 sym = (srate << 4); /* SR * 2^16 / master_clk */
730 sym /= (state->mclk >> 12);
731 } else if (srate > 6000000) {
732 sym = (srate << 6);
733 sym /= (state->mclk >> 10);
e415c689 734 } else {
15bb366e
MA		 735 sym = (srate << 9);
736 sym /= (state->mclk >> 7);
e415c689
MA		 737 }
738
15bb366e 739 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
e415c689
MA		 740 goto err;
741 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
742 goto err;
15bb366e 743
e415c689
MA		 744 return 0;
745err:
746 dprintk(FE_ERROR, 1, "I/O error");
747 return -1;
748}
749
750static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
751{
752 u32 sym;
753
754 srate = 105 * (srate / 100);
15bb366e
MA		 755 if (srate > 60000000) {
756 sym = (srate << 4); /* SR * 2^16 / master_clk */
757 sym /= (state->mclk >> 12);
758 } else if (srate > 6000000) {
759 sym = (srate << 6);
760 sym /= (state->mclk >> 10);
e415c689 761 } else {
15bb366e
MA		 762 sym = (srate << 9);
763 sym /= (state->mclk >> 7);
e415c689 764 }
15bb366e
MA		 765
766 if (sym < 0x7fff) {
767 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
768 goto err;
769 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
770 goto err;
771 } else {
772 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
773 goto err;
774 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
775 goto err;
776 }
777
e415c689
MA		 778 return 0;
779err:
780 dprintk(FE_ERROR, 1, "I/O error");
781 return -1;
782}
783
784static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
785{
786 u32 sym;
787
788 srate = 95 * (srate / 100);
15bb366e
MA		 789 if (srate > 60000000) {
790 sym = (srate << 4); /* SR * 2^16 / master_clk */
791 sym /= (state->mclk >> 12);
792 } else if (srate > 6000000) {
793 sym = (srate << 6);
794 sym /= (state->mclk >> 10);
e415c689 795 } else {
15bb366e
MA		 796 sym = (srate << 9);
797 sym /= (state->mclk >> 7);
e415c689 798 }
15bb366e 799
e415c689
MA		 800 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
801 goto err;
802 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
803 goto err;
804 return 0;
805err:
806 dprintk(FE_ERROR, 1, "I/O error");
807 return -1;
808}
809
810static u32 stv090x_car_width(u32 srate, u32 rolloff)
811{
812 return srate + (srate * rolloff) / 100;
813}
814
815static int stv090x_set_vit_thacq(struct stv090x_state *state)
816{
817 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
818 goto err;
819 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
820 goto err;
821 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
822 goto err;
823 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
824 goto err;
825 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
826 goto err;
827 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
828 goto err;
829 return 0;
830err:
831 dprintk(FE_ERROR, 1, "I/O error");
832 return -1;
833}
834
835static int stv090x_set_vit_thtracq(struct stv090x_state *state)
836{
837 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
838 goto err;
839 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
840 goto err;
841 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
842 goto err;
843 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
844 goto err;
845 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
846 goto err;
847 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
848 goto err;
849 return 0;
850err:
851 dprintk(FE_ERROR, 1, "I/O error");
852 return -1;
853}
854
855static int stv090x_set_viterbi(struct stv090x_state *state)
856{
857 switch (state->search_mode) {
858 case STV090x_SEARCH_AUTO:
859 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
860 goto err;
861 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
862 goto err;
863 break;
864 case STV090x_SEARCH_DVBS1:
865 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
866 goto err;
867 switch (state->fec) {
868 case STV090x_PR12:
869 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
870 goto err;
871 break;
872
873 case STV090x_PR23:
874 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
875 goto err;
876 break;
877
878 case STV090x_PR34:
879 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
880 goto err;
881 break;
882
883 case STV090x_PR56:
884 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
885 goto err;
886 break;
887
888 case STV090x_PR78:
889 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
890 goto err;
891 break;
892
893 default:
894 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
895 goto err;
896 break;
897 }
898 break;
899 case STV090x_SEARCH_DSS:
900 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
901 goto err;
902 switch (state->fec) {
903 case STV090x_PR12:
904 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
905 goto err;
906 break;
907
908 case STV090x_PR23:
909 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
910 goto err;
911 break;
912
913 case STV090x_PR67:
914 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
915 goto err;
916 break;
917
918 default:
919 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
920 goto err;
921 break;
922 }
923 break;
924 default:
925 break;
926 }
927 return 0;
928err:
929 dprintk(FE_ERROR, 1, "I/O error");
930 return -1;
931}
932
933static int stv090x_stop_modcod(struct stv090x_state *state)
934{
935 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
936 goto err;
937 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
938 goto err;
939 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
940 goto err;
941 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
942 goto err;
943 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
944 goto err;
945 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
946 goto err;
947 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
948 goto err;
949 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
950 goto err;
951 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
952 goto err;
953 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
954 goto err;
955 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
956 goto err;
957 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
958 goto err;
959 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
960 goto err;
961 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
962 goto err;
963 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
964 goto err;
965 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
966 goto err;
967 return 0;
968err:
969 dprintk(FE_ERROR, 1, "I/O error");
970 return -1;
971}
972
973static int stv090x_activate_modcod(struct stv090x_state *state)
974{
975 u32 matype, modcod, f_mod, index;
976
977 if (state->dev_ver <= 0x11) {
978 msleep(5);
979 modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
980 matype = modcod & 0x03;
981 modcod = (modcod & 0x7f) >> 2;
982 index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
983
984 switch (matype) {
985 default:
986 case 0:
987 f_mod = 14;
988 break;
989 case 1:
990 f_mod = 13;
991 break;
992 case 2:
993 f_mod = 11;
994 break;
995 case 3:
996 f_mod = 7;
997 break;
998 }
999 if (matype <= 1) {
1000 if (modcod % 2) {
1001 if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
1002 goto err;
1003 } else {
1004 if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
1005 goto err;
1006 }
1007 }
1008 } else if (state->dev_ver >= 0x12) {
1009 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1010 goto err;
1011 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1012 goto err;
1013 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1014 goto err;
1015 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1016 goto err;
1017 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1018 goto err;
1019 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1020 goto err;
1021 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1022 goto err;
1023 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1024 goto err;
1025 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1026 goto err;
1027 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1028 goto err;
1029 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1030 goto err;
1031 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1032 goto err;
1033 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1034 goto err;
1035 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1036 goto err;
1037 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1038 goto err;
1039 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1040 goto err;
1041 }
1042 return 0;
1043err:
1044 dprintk(FE_ERROR, 1, "I/O error");
1045 return -1;
1046}
1047
1048static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1049{
1050 u32 reg;
1051
1052 switch (state->demod) {
1053 case STV090x_DEMODULATOR_0:
1054 mutex_lock(&demod_lock);
1055 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1056 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1057 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1058 goto err;
1059 mutex_unlock(&demod_lock);
1060 break;
1061
1062 case STV090x_DEMODULATOR_1:
1063 mutex_lock(&demod_lock);
1064 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1065 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1066 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1067 goto err;
1068 mutex_unlock(&demod_lock);
1069 break;
1070
1071 default:
1072 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1073 break;
1074 }
1075 return 0;
1076err:
1077 mutex_unlock(&demod_lock);
1078 dprintk(FE_ERROR, 1, "I/O error");
1079 return -1;
1080}
1081
1082static int stv090x_delivery_search(struct stv090x_state *state)
1083{
1084 u32 reg;
1085
1086 switch (state->search_mode) {
1087 case STV090x_SEARCH_DVBS1:
1088 case STV090x_SEARCH_DSS:
1089 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1090 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1091 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1092 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1093 goto err;
1094
1095 /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
1096 if (stv090x_vitclk_ctl(state, 0) < 0)
1097 goto err;
1098
1099 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1100 goto err;
1101 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1102 goto err;
1103 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1104 goto err;
1105
1106 stv090x_set_vit_thacq(state);
1107 stv090x_set_viterbi(state);
1108 break;
1109
1110 case STV090x_SEARCH_DVBS2:
1111 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1112 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1113 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1114 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1115 goto err;
1116 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1117 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1118 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1119 goto err;
1120
1121 if (stv090x_vitclk_ctl(state, 1) < 0)
1122 goto err;
1123
1124 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1125 goto err;
1126 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1127 goto err;
1128 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1129 goto err;
1130
1131 if (state->demod_mode != STV090x_SINGLE) {
1132 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1133 stv090x_stop_modcod(state);
1134 else
1135 stv090x_activate_modcod(state);
1136 }
1137 break;
1138
1139 case STV090x_SEARCH_AUTO:
1140 default:
1141 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1142 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1143 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1144 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1145 goto err;
1146 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1147 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1148 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1149 goto err;
1150
1151 if (stv090x_vitclk_ctl(state, 1) < 0)
1152 goto err;
1153
1154 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1155 goto err;
1156 if (STV090x_WRITE_DEMOD(state, ACLC, 0x09) < 0)
1157 goto err;
1158 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1159 goto err;
1160
1161 if (state->demod_mode != STV090x_SINGLE) {
1162 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1163 stv090x_stop_modcod(state);
1164 else
1165 stv090x_activate_modcod(state);
1166 }
1167 stv090x_set_vit_thacq(state);
1168 stv090x_set_viterbi(state);
1169 break;
1170 }
1171 return 0;
1172err:
1173 dprintk(FE_ERROR, 1, "I/O error");
1174 return -1;
1175}
1176
1177static int stv090x_start_search(struct stv090x_state *state)
1178{
1179 u32 reg;
1180
1181 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1182 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1183 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1184 goto err;
1185
1186 if (state->dev_ver == 0x10) {
1187 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1188 goto err;
1189 }
1190 if (state->dev_ver < 0x20) {
1191 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1192 goto err;
1193 }
1194 if (state->srate <= 5000000) {
1195 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1196 goto err;
1197 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1198 goto err;
1199 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
1200 goto err;
1201 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1202 goto err;
1203 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1204 goto err;
1205
1206 /*enlarge the timing bandwith for Low SR*/
1207 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1208 goto err;
1209 } else {
1210 /* If the symbol rate is >5 Msps
1211 Set The carrier search up and low to auto mode */
1212 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1213 goto err;
1214 /*reduce the timing bandwith for high SR*/
1215 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1216 goto err;
1217 }
1218 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1219 goto err;
1220 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1221 goto err;
1222
1223 if (state->dev_ver >= 0x20) {
1224 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1225 goto err;
1226 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1227 goto err;
1228
1229 if ((state->search_mode == STV090x_DVBS1) ||
1230 (state->search_mode == STV090x_DSS) ||
1231 (state->search_mode == STV090x_SEARCH_AUTO)) {
1232
1233 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1234 goto err;
1235 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1236 goto err;
1237 }
1238 }
1239
1240 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1241 goto err;
1242 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1243 goto err;
1244 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1245 goto err;
1246
1247 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1248 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1249 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1250 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1251 goto err;
1252 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1253 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1254 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1255 goto err;
1256
1257 if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
1258 if (state->srate < 10000000) {
1259 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1260 goto err;
1261 } else {
1262 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1263 goto err;
1264 }
1265 } else {
1266 if (state->srate < 10000000) {
1267 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1268 goto err;
1269 } else {
1270 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1271 goto err;
1272 }
1273 }
1274
1275 switch (state->algo) {
1276 case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
1277 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1278 goto err;
1279 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1280 goto err;
1281 break;
1282
1283 case STV090x_COLD_SEARCH:/*The symbol rate is known*/
1284 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1285 goto err;
1286 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1287 goto err;
1288 break;
1289
1290 default:
1291 break;
1292 }
1293 return 0;
1294err:
1295 dprintk(FE_ERROR, 1, "I/O error");
1296 return -1;
1297}
1298
1299static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1300{
1301 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
1302 s32 i, j, steps, dir;
1303
1304 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1305 goto err;
1306 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1307 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1308 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1309 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1310 goto err;
1311
1312 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1313 goto err;
1314 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1315 goto err;
1316 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1317 goto err;
1318 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1319 goto err;
1320 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1321 goto err;
1322 stv090x_set_srate(state, 1000000);
1323
1324 steps = -1 + state->search_range / 1000000;
1325 steps /= 2;
1326 steps = (2 * steps) + 1;
1327 if (steps < 0)
1328 steps = 1;
1329
1330 dir = 1;
1331 freq_step = (1000000 * 256) / (state->mclk / 256);
1332 freq_init = 0;
1333
1334 for (i = 0; i < steps; i++) {
1335 if (dir > 0)
1336 freq_init = freq_init + (freq_step * i);
1337 else
1338 freq_init = freq_init - (freq_step * i);
1339
1340 dir = -1;
1341
1342 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1343 goto err;
1344 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1345 goto err;
1346 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1347 goto err;
1348 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1349 goto err;
1350 msleep(10);
1351 for (j = 0; j < 10; j++) {
1352 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1353 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1354 }
1355 agc2 /= 10;
1356 agc2_min = 0xffff;
1357 if (agc2 < 0xffff)
1358 agc2_min = agc2;
1359 }
1360
1361 return agc2_min;
1362err:
1363 dprintk(FE_ERROR, 1, "I/O error");
1364 return -1;
1365}
1366
1367static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1368{
1369 u8 r3, r2, r1, r0;
1370 s32 srate, int_1, int_2, tmp_1, tmp_2;
e415c689
MA		 1371
1372 r3 = STV090x_READ_DEMOD(state, SFR3);
1373 r2 = STV090x_READ_DEMOD(state, SFR2);
1374 r1 = STV090x_READ_DEMOD(state, SFR1);
1375 r0 = STV090x_READ_DEMOD(state, SFR0);
1376
1377 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1378
f430fff1
MA		 1379 int_1 = clk >> 16;
1380 int_2 = srate >> 16;
e415c689 1381
f430fff1
MA		 1382 tmp_1 = clk % 0x10000;
1383 tmp_2 = srate % 0x10000;
e415c689
MA		 1384
1385 srate = (int_1 * int_2) +
f430fff1
MA		 1386 ((int_1 * tmp_2) >> 16) +
1387 ((int_2 * tmp_1) >> 16);
e415c689
MA		 1388
1389 return srate;
1390}
1391
1392static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1393{
1394 struct dvb_frontend *fe = &state->frontend;
1395
1396 int tmg_lock = 0, i;
1397 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1398 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1399
1400 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1401 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1402 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1403 goto err;
1404 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1405 goto err;
1406 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1407 goto err;
1408 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1409 goto err;
1410 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1411 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1412 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1413 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1414 goto err;
1415
1416 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1417 goto err;
1418 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1419 goto err;
1420 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1421 goto err;
1422 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1423 goto err;
1424 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1425 goto err;
1426 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
1427 goto err;
1428
1429 if (state->dev_ver >= 0x20) {
1430 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1431 goto err;
1432 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1433 goto err;
1434 } else {
1435 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1436 goto err;
1437 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
1438 goto err;
1439 }
1440
1441 if (state->srate <= 2000000)
1442 car_step = 1000;
1443 else if (state->srate <= 5000000)
1444 car_step = 2000;
1445 else if (state->srate <= 12000000)
1446 car_step = 3000;
1447 else
1448 car_step = 5000;
1449
1450 steps = -1 + ((state->search_range / 1000) / car_step);
1451 steps /= 2;
1452 steps = (2 * steps) + 1;
1453 if (steps < 0)
1454 steps = 1;
1455 else if (steps > 10) {
1456 steps = 11;
1457 car_step = (state->search_range / 1000) / 10;
1458 }
1459 cur_step = 0;
1460 dir = 1;
1461 freq = state->frequency;
1462
1463 while ((!tmg_lock) && (cur_step < steps)) {
1464 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1465 goto err;
1466 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1467 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1468 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1469 goto err;
1470 msleep(50);
1471 for (i = 0; i < 10; i++) {
1472 reg = STV090x_READ_DEMOD(state, DSTATUS);
1473 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1474 tmg_cpt++;
1475 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1476 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1477 }
1478 agc2 /= 10;
1479 srate_coarse = stv090x_get_srate(state, state->mclk);
1480 cur_step++;
1481 dir *= -1;
1482 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
1483 tmg_lock = 1;
1484 else if (cur_step < steps) {
1485 if (dir > 0)
1486 freq += cur_step * car_step;
1487 else
1488 freq -= cur_step * car_step;
1489
1490 /* Setup tuner */
1491 stv090x_i2c_gate_ctrl(fe, 1);
1492
1493 if (state->config->tuner_set_frequency)
1494 state->config->tuner_set_frequency(fe, state->frequency);
1495
1496 if (state->config->tuner_set_bandwidth)
1497 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1498
1499 stv090x_i2c_gate_ctrl(fe, 0);
1500 msleep(50);
1501 stv090x_i2c_gate_ctrl(fe, 1);
1502
1503 if (state->config->tuner_get_status)
1504 state->config->tuner_get_status(fe, &reg);
1505
1506 if (reg)
1507 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1508 else
1509 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1510
1511 stv090x_i2c_gate_ctrl(fe, 0);
1512
1513 }
1514 }
1515 if (!tmg_lock)
1516 srate_coarse = 0;
1517 else
1518 srate_coarse = stv090x_get_srate(state, state->mclk);
1519
1520 return srate_coarse;
1521err:
1522 dprintk(FE_ERROR, 1, "I/O error");
1523 return -1;
1524}
1525
1526static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1527{
1528 u32 srate_coarse, freq_coarse, sym, reg;
1529
1530 srate_coarse = stv090x_get_srate(state, state->mclk);
1531 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1532 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1533 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1534
1535 if (sym < state->srate)
1536 srate_coarse = 0;
1537 else {
1538 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1539 goto err;
1540 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1541 goto err;
1542 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1543 goto err;
1544 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1545 goto err;
1546 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1547 goto err;
1548 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1549 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1550 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1551 goto err;
1552
1553 if (state->dev_ver >= 0x20) {
1554 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1555 goto err;
1556 } else {
1557 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1558 goto err;
1559 }
1560
1561 if (srate_coarse > 3000000) {
1562 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1563 sym = (sym / 1000) * 65536;
1564 sym /= (state->mclk / 1000);
1565 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1566 goto err;
1567 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1568 goto err;
1569 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1570 sym = (sym / 1000) * 65536;
1571 sym /= (state->mclk / 1000);
1572 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1573 goto err;
1574 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1575 goto err;
1576 sym = (srate_coarse / 1000) * 65536;
1577 sym /= (state->mclk / 1000);
1578 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1579 goto err;
1580 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1581 goto err;
1582 } else {
1583 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1584 sym = (sym / 100) * 65536;
1585 sym /= (state->mclk / 100);
1586 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1587 goto err;
1588 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1589 goto err;
1590 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1591 sym = (sym / 100) * 65536;
1592 sym /= (state->mclk / 100);
1593 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1594 goto err;
1595 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1596 goto err;
1597 sym = (srate_coarse / 100) * 65536;
1598 sym /= (state->mclk / 100);
1599 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1600 goto err;
1601 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1602 goto err;
1603 }
1604 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1605 goto err;
1606 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1607 goto err;
1608 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1609 goto err;
1610 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1611 goto err;
1612 }
1613
1614 return srate_coarse;
1615
1616err:
1617 dprintk(FE_ERROR, 1, "I/O error");
1618 return -1;
1619}
1620
1621static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1622{
1623 s32 timer = 0, lock = 0;
1624 u32 reg;
1625 u8 stat;
1626
1627 while ((timer < timeout) && (!lock)) {
1628 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1629 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1630
1631 switch (stat) {
1632 case 0: /* searching */
1633 case 1: /* first PLH detected */
1634 default:
1635 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1636 lock = 0;
1637 break;
1638 case 2: /* DVB-S2 mode */
1639 case 3: /* DVB-S1/legacy mode */
1640 reg = STV090x_READ_DEMOD(state, DSTATUS);
1641 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1642 break;
1643 }
1644
1645 if (!lock)
1646 msleep(10);
1647 else
1648 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1649
1650 timer += 10;
1651 }
1652 return lock;
1653}
1654
1655static int stv090x_blind_search(struct stv090x_state *state)
1656{
1657 u32 agc2, reg, srate_coarse;
1658 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1659 u8 k_ref, k_max, k_min;
1660 int coarse_fail, lock;
1661
1662 if (state->dev_ver < 0x20) {
1663 k_max = 233;
1664 k_min = 143;
1665 } else {
1666 k_max = 120;
1667 k_min = 30;
1668 }
1669
1670 agc2 = stv090x_get_agc2_min_level(state);
1671
1672 if (agc2 > STV090x_SEARCH_AGC2_TH) {
1673 lock = 0;
1674 } else {
1675 if (state->dev_ver == 0x10) {
1676 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1677 goto err;
1678 }
1679 if (state->dev_ver < 0x20) {
1680 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1681 goto err;
1682 }
1683
1684 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1685 goto err;
1686 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1687 goto err;
1688 if (state->dev_ver >= 0x20) {
1689 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1690 goto err;
1691 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1692 goto err;
1693 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1694 goto err;
1695 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1696 goto err;
1697 }
1698
1699 k_ref = k_max;
1700 do {
1701 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1702 goto err;
1703 if (stv090x_srate_srch_coarse(state) != 0) {
1704 srate_coarse = stv090x_srate_srch_fine(state);
1705 if (srate_coarse != 0) {
1706 stv090x_get_lock_tmg(state);
1707 lock = stv090x_get_dmdlock(state, timeout_dmd);
1708 } else {
1709 lock = 0;
1710 }
1711 } else {
1712 cpt_fail = 0;
1713 agc2_ovflw = 0;
1714 for (i = 0; i < 10; i++) {
1715 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1716 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1717 if (agc2 >= 0xff00)
1718 agc2_ovflw++;
1719 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1720 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1721 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1722
1723 cpt_fail++;
1724 }
1725 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1726 coarse_fail = 1;
1727
1728 lock = 0;
1729 }
1730 k_ref -= 30;
1731 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1732 }
1733
1734 return lock;
1735
1736err:
1737 dprintk(FE_ERROR, 1, "I/O error");
1738 return -1;
1739}
1740
1741static int stv090x_chk_tmg(struct stv090x_state *state)
1742{
1743 u32 reg;
1744 s32 tmg_cpt, i;
1745 u8 freq, tmg_thh, tmg_thl;
1746 int tmg_lock;
1747
1748 freq = STV090x_READ_DEMOD(state, CARFREQ);
1749 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1750 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1751 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1752 goto err;
1753 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1754 goto err;
1755
1756 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1757 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1758 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1759 goto err;
1760 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1761 goto err;
1762
1763 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1764 goto err;
1765 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1766 goto err;
1767
1768 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1769 goto err;
1770 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1771 goto err;
1772 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1773 goto err;
1774
1775 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1776 goto err;
1777 msleep(10);
1778
1779 for (i = 0; i < 10; i++) {
1780 reg = STV090x_READ_DEMOD(state, DSTATUS);
1781 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1782 tmg_cpt++;
1783 msleep(1);
1784 }
1785 if (tmg_cpt >= 3)
1786 tmg_lock = 1;
1787
1788 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1789 goto err;
1790 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1791 goto err;
1792 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
1793 goto err;
1794
1795 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
1796 goto err;
1797 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
1798 goto err;
1799 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
1800 goto err;
1801
1802 return tmg_lock;
1803
1804err:
1805 dprintk(FE_ERROR, 1, "I/O error");
1806 return -1;
1807}
1808
1809static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
1810{
1811 struct dvb_frontend *fe = &state->frontend;
1812
1813 u32 reg;
1814 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
1815 int lock = 0;
1816
1817 if (state->srate >= 10000000)
1818 timeout_lock = timeout_dmd / 3;
1819 else
1820 timeout_lock = timeout_dmd / 2;
1821
1822 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
1823 if (!lock) {
1824 if (state->srate >= 10000000) {
1825 if (stv090x_chk_tmg(state)) {
1826 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1827 goto err;
1828 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1829 goto err;
1830 lock = stv090x_get_dmdlock(state, timeout_dmd);
1831 } else {
1832 lock = 0;
1833 }
1834 } else {
1835 if (state->srate <= 4000000)
1836 car_step = 1000;
1837 else if (state->srate <= 7000000)
1838 car_step = 2000;
1839 else if (state->srate <= 10000000)
1840 car_step = 3000;
1841 else
1842 car_step = 5000;
1843
1844 steps = (state->search_range / 1000) / car_step;
1845 steps /= 2;
1846 steps = 2 * (steps + 1);
1847 if (steps < 0)
1848 steps = 2;
1849 else if (steps > 12)
1850 steps = 12;
1851
1852 cur_step = 1;
1853 dir = 1;
1854
1855 if (!lock) {
1856 freq = state->frequency;
1857 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
1858 while ((cur_step <= steps) && (!lock)) {
1859 if (dir > 0)
1860 freq += cur_step * car_step;
1861 else
1862 freq -= cur_step * car_step;
1863
1864 /* Setup tuner */
1865 stv090x_i2c_gate_ctrl(fe, 1);
1866
1867 if (state->config->tuner_set_frequency)
1868 state->config->tuner_set_frequency(fe, state->frequency);
1869
1870 if (state->config->tuner_set_bandwidth)
1871 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1872
1873 stv090x_i2c_gate_ctrl(fe, 0);
1874
1875 msleep(50);
1876
1877 stv090x_i2c_gate_ctrl(fe, 1);
1878
1879 if (state->config->tuner_get_status)
1880 state->config->tuner_get_status(fe, &reg);
1881
1882 if (reg)
1883 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1884 else
1885 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1886
1887 stv090x_i2c_gate_ctrl(fe, 0);
1888
1889 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
1890 if (state->delsys == STV090x_DVBS2) {
1891 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1892 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1893 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1894 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1895 goto err;
1896 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1897 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1898 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1899 goto err;
1900 }
1901 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1902 goto err;
1903 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1904 goto err;
1905 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1906 goto err;
1907 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1908 goto err;
1909 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
1910
1911 dir *= -1;
1912 cur_step++;
1913 }
1914 }
1915 }
1916 }
1917
1918 return lock;
1919
1920err:
1921 dprintk(FE_ERROR, 1, "I/O error");
1922 return -1;
1923}
1924
1925static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
1926{
1927 s32 timeout, inc, steps_max, srate, car_max;
1928
1929 srate = state->srate;
1930 car_max = state->search_range / 1000;
1931 car_max = 65536 * (car_max / 2);
1932 car_max /= (state->mclk / 1000);
1933
1934 if (car_max > 0x4000)
1935 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
1936
1937 inc = srate;
1938 inc /= state->mclk / 1000;
1939 inc *= 256;
1940 inc *= 256;
1941 inc /= 1000;
1942
72982f76 1943 switch (state->search_mode) {
e415c689
MA		 1944 case STV090x_SEARCH_DVBS1:
1945 case STV090x_SEARCH_DSS:
1946 inc *= 3; /* freq step = 3% of srate */
1947 timeout = 20;
1948 break;
1949
1950 case STV090x_SEARCH_DVBS2:
1951 inc *= 4;
1952 timeout = 25;
1953 break;
1954
1955 case STV090x_SEARCH_AUTO:
1956 default:
1957 inc *= 3;
1958 timeout = 25;
1959 break;
1960 }
1961 inc /= 100;
1962 if ((inc > car_max) || (inc < 0))
1963 inc = car_max / 2; /* increment <= 1/8 Mclk */
1964
1965 timeout *= 27500; /* 27.5 Msps reference */
1966 if (srate > 0)
1967 timeout /= (srate / 1000);
1968
1969 if ((timeout > 100) || (timeout < 0))
1970 timeout = 100;
1971
1972 steps_max = (car_max / inc) + 1; /* min steps = 3 */
1973 if ((steps_max > 100) || (steps_max < 0)) {
1974 steps_max = 100; /* max steps <= 100 */
1975 inc = car_max / steps_max;
1976 }
1977 *freq_inc = inc;
1978 *timeout_sw = timeout;
1979 *steps = steps_max;
1980
1981 return 0;
1982}
1983
1984static int stv090x_chk_signal(struct stv090x_state *state)
1985{
1986 s32 offst_car, agc2, car_max;
1987 int no_signal;
1988
1989 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
1990 offst_car |= STV090x_READ_DEMOD(state, CFR1);
1991
1992 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1993 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1994 car_max = state->search_range / 1000;
1995
1996 car_max += (car_max / 10); /* 10% margin */
1997 car_max = (65536 * car_max / 2);
1998 car_max /= state->mclk / 1000;
1999
2000 if (car_max > 0x4000)
2001 car_max = 0x4000;
2002
2003 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2004 no_signal = 1;
2005 dprintk(FE_DEBUG, 1, "No Signal");
2006 } else {
2007 no_signal = 0;
2008 dprintk(FE_DEBUG, 1, "Found Signal");
2009 }
2010
2011 return no_signal;
2012}
2013
2014static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2015{
2016 int no_signal, lock = 0;
2017 s32 cpt_step, offst_freq, car_max;
2018 u32 reg;
2019
2020 car_max = state->search_range / 1000;
2021 car_max += (car_max / 10);
2022 car_max = (65536 * car_max / 2);
2023 car_max /= (state->mclk / 1000);
2024 if (car_max > 0x4000)
2025 car_max = 0x4000;
2026
2027 if (zigzag)
2028 offst_freq = 0;
2029 else
2030 offst_freq = -car_max + inc;
2031
2032 cpt_step = 0;
2033 do {
2034 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2035 goto err;
2036 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2037 goto err;
2038 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2039 goto err;
2040 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2041 goto err;
2042
2043 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2044 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2045 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2046 goto err;
2047
2048 if (state->dev_ver == 0x12) {
2049 reg = STV090x_READ_DEMOD(state, TSCFGH);
2050 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
2051 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2052 goto err;
2053 }
2054
2055 if (zigzag) {
2056 if (offst_freq >= 0)
2057 offst_freq = -offst_freq - 2 * inc;
2058 else
2059 offst_freq = -offst_freq;
2060 } else {
2061 offst_freq += 2 * inc;
2062 }
2063
2064 lock = stv090x_get_dmdlock(state, timeout);
2065 no_signal = stv090x_chk_signal(state);
2066
2067 } while ((!lock) &&
2068 (!no_signal) &&
2069 ((offst_freq - inc) < car_max) &&
2070 ((offst_freq + inc) > -car_max) &&
2071 (cpt_step < steps_max));
2072
2073 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2074 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2075 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2076 goto err;
2077
2078 return lock;
2079err:
2080 dprintk(FE_ERROR, 1, "I/O error");
2081 return -1;
2082}
2083
2084static int stv090x_sw_algo(struct stv090x_state *state)
2085{
2086 int no_signal, zigzag, lock = 0;
2087 u32 reg;
2088
2089 s32 dvbs2_fly_wheel;
2090 s32 inc, timeout_step, trials, steps_max;
2091
2092 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
2093
72982f76 2094 switch (state->search_mode) {
e415c689
MA		 2095 case STV090x_SEARCH_DVBS1:
2096 case STV090x_SEARCH_DSS:
2097 /* accelerate the frequency detector */
2098 if (state->dev_ver >= 0x20) {
2099 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2100 goto err;
2101 } else {
2102 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2103 goto err;
2104 }
2105 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2106 goto err;
2107 zigzag = 0;
2108 break;
2109
2110 case STV090x_SEARCH_DVBS2:
2111 if (state->dev_ver >= 0x20) {
2112 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2113 goto err;
2114 } else {
2115 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2116 goto err;
2117 }
2118 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2119 goto err;
2120 zigzag = 1;
2121 break;
2122
2123 case STV090x_SEARCH_AUTO:
2124 default:
2125 /* accelerate the frequency detector */
2126 if (state->dev_ver >= 0x20) {
2127 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2128 goto err;
2129 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2130 goto err;
2131 } else {
2132 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2133 goto err;
2134 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2135 goto err;
2136 }
2137 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
2138 goto err;
2139 zigzag = 0;
2140 break;
2141 }
2142
2143 trials = 0;
2144 do {
2145 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2146 no_signal = stv090x_chk_signal(state);
2147 trials++;
2148
2149 /*run the SW search 2 times maximum*/
2150 if (lock || no_signal || (trials == 2)) {
2151 /*Check if the demod is not losing lock in DVBS2*/
2152 if (state->dev_ver >= 0x20) {
2153 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2154 goto err;
2155 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2156 goto err;
2157 } else {
2158 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
2159 goto err;
2160 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
2161 goto err;
2162 }
2163
2164 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2165 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2166 /*Check if the demod is not losing lock in DVBS2*/
2167 msleep(timeout_step);
2168 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2169 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2170 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2171 msleep(timeout_step);
2172 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2173 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2174 }
2175 if (dvbs2_fly_wheel < 0xd) {
2176 /*FALSE lock, The demod is loosing lock */
2177 lock = 0;
2178 if (trials < 2) {
2179 if (state->dev_ver >= 0x20) {
2180 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2181 goto err;
2182 } else {
2183 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2184 goto err;
2185 }
2186 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2187 goto err;
2188 }
2189 }
2190 }
2191 }
2192 } while ((!lock) && (trials < 2) && (!no_signal));
2193
2194 return lock;
2195err:
2196 dprintk(FE_ERROR, 1, "I/O error");
2197 return -1;
2198}
2199
2200static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2201{
2202 u32 reg;
2203 enum stv090x_delsys delsys;
2204
2205 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2206 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2207 delsys = STV090x_DVBS2;
2208 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2209 reg = STV090x_READ_DEMOD(state, FECM);
2210 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2211 delsys = STV090x_DSS;
2212 else
2213 delsys = STV090x_DVBS1;
2214 } else {
2215 delsys = STV090x_ERROR;
2216 }
2217
2218 return delsys;
2219}
2220
2221/* in Hz */
2222static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2223{
2224 s32 derot, int_1, int_2, tmp_1, tmp_2;
2225 u32 pow2;
2226
2227 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2228 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2229 derot |= STV090x_READ_DEMOD(state, CFR0);
2230
2231 derot = comp2(derot, 24);
2232 pow2 = 1 << 12;
2233 int_1 = state->mclk / pow2;
2234 int_2 = derot / pow2;
2235
2236 tmp_1 = state->mclk % pow2;
2237 tmp_2 = derot % pow2;
2238
2239 derot = (int_1 * int_2) +
2240 ((int_1 * tmp_2) / pow2) +
2241 ((int_1 * tmp_1) / pow2);
2242
2243 return derot;
2244}
2245
2246static int stv090x_get_viterbi(struct stv090x_state *state)
2247{
2248 u32 reg, rate;
2249
2250 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2251 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2252
2253 switch (rate) {
2254 case 13:
2255 state->fec = STV090x_PR12;
2256 break;
2257
2258 case 18:
2259 state->fec = STV090x_PR23;
2260 break;
2261
2262 case 21:
2263 state->fec = STV090x_PR34;
2264 break;
2265
2266 case 24:
2267 state->fec = STV090x_PR56;
2268 break;
2269
2270 case 25:
2271 state->fec = STV090x_PR67;
2272 break;
2273
2274 case 26:
2275 state->fec = STV090x_PR78;
2276 break;
2277
2278 default:
2279 state->fec = STV090x_PRERR;
2280 break;
2281 }
2282
2283 return 0;
2284}
2285
2286static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2287{
2288 struct dvb_frontend *fe = &state->frontend;
2289
2290 u8 tmg;
2291 u32 reg;
2292 s32 i = 0, offst_freq;
2293
2294 msleep(5);
2295
2296 if (state->algo == STV090x_BLIND_SEARCH) {
2297 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2298 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2299 while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
2300 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2301 msleep(5);
2302 i += 5;
2303 }
2304 }
2305 state->delsys = stv090x_get_std(state);
2306
2307 stv090x_i2c_gate_ctrl(fe, 1);
2308
2309 if (state->config->tuner_get_frequency)
2310 state->config->tuner_get_frequency(fe, &state->frequency);
2311
2312 stv090x_i2c_gate_ctrl(fe, 0);
2313
2314 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2315 state->frequency += offst_freq;
2316 stv090x_get_viterbi(state);
2317 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2318 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2319 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2320 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2321 reg = STV090x_READ_DEMOD(state, TMGOBS);
2322 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2323 reg = STV090x_READ_DEMOD(state, FECM);
2324 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2325
2326 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2327
2328 stv090x_i2c_gate_ctrl(fe, 1);
2329
2330 if (state->config->tuner_get_frequency)
2331 state->config->tuner_get_frequency(fe, &state->frequency);
2332
2333 stv090x_i2c_gate_ctrl(fe, 0);
2334
2335 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2336 return STV090x_RANGEOK;
2337 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2338 return STV090x_RANGEOK;
2339 else
2340 return STV090x_OUTOFRANGE; /* Out of Range */
2341 } else {
2342 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2343 return STV090x_RANGEOK;
2344 else
2345 return STV090x_OUTOFRANGE;
2346 }
2347
2348 return STV090x_OUTOFRANGE;
2349}
2350
2351static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2352{
2353 s32 offst_tmg;
2354 s32 pow2;
2355
2356 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2357 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2358 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2359
2360 pow2 = 1 << 24;
2361
2362 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2363 if (!offst_tmg)
2364 offst_tmg = 1;
2365
2366 offst_tmg = ((s32) srate * 10) / (pow2 / offst_tmg);
2367 offst_tmg /= 320;
2368
2369 return offst_tmg;
2370}
2371
2372static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2373{
2374 u8 aclc = 0x29;
2375 s32 i;
2376 struct stv090x_long_frame_crloop *car_loop;
2377
2378 if (state->dev_ver <= 0x12)
2379 car_loop = stv090x_s2_crl;
2380 else if (state->dev_ver == 0x20)
2381 car_loop = stv090x_s2_crl_cut20;
2382 else
2383 car_loop = stv090x_s2_crl;
2384
2385
2386 if (modcod < STV090x_QPSK_12) {
2387 i = 0;
2388 while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2389 i++;
2390
2391 if (i >= 3)
2392 i = 2;
2393
2394 } else {
2395 i = 0;
2396 while ((i < 14) && (modcod != car_loop[i].modcod))
2397 i++;
2398
2399 if (i >= 14) {
2400 i = 0;
2401 while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2402 i++;
2403
2404 if (i >= 11)
2405 i = 10;
2406 }
2407 }
2408
2409 if (modcod <= STV090x_QPSK_25) {
2410 if (pilots) {
2411 if (state->srate <= 3000000)
2412 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
2413 else if (state->srate <= 7000000)
2414 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
2415 else if (state->srate <= 15000000)
2416 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
2417 else if (state->srate <= 25000000)
2418 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
2419 else
2420 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
2421 } else {
2422 if (state->srate <= 3000000)
2423 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
2424 else if (state->srate <= 7000000)
2425 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
2426 else if (state->srate <= 15000000)
2427 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
2428 else if (state->srate <= 25000000)
2429 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
2430 else
2431 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
2432 }
2433
2434 } else if (modcod <= STV090x_8PSK_910) {
2435 if (pilots) {
2436 if (state->srate <= 3000000)
2437 aclc = car_loop[i].crl_pilots_on_2;
2438 else if (state->srate <= 7000000)
2439 aclc = car_loop[i].crl_pilots_on_5;
2440 else if (state->srate <= 15000000)
2441 aclc = car_loop[i].crl_pilots_on_10;
2442 else if (state->srate <= 25000000)
2443 aclc = car_loop[i].crl_pilots_on_20;
2444 else
2445 aclc = car_loop[i].crl_pilots_on_30;
2446 } else {
2447 if (state->srate <= 3000000)
2448 aclc = car_loop[i].crl_pilots_off_2;
2449 else if (state->srate <= 7000000)
2450 aclc = car_loop[i].crl_pilots_off_5;
2451 else if (state->srate <= 15000000)
2452 aclc = car_loop[i].crl_pilots_off_10;
2453 else if (state->srate <= 25000000)
2454 aclc = car_loop[i].crl_pilots_off_20;
2455 else
2456 aclc = car_loop[i].crl_pilots_off_30;
2457 }
2458 } else { /* 16APSK and 32APSK */
2459 if (state->srate <= 3000000)
2460 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
2461 else if (state->srate <= 7000000)
2462 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
2463 else if (state->srate <= 15000000)
2464 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
2465 else if (state->srate <= 25000000)
2466 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
2467 else
2468 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
2469 }
2470
2471 return aclc;
2472}
2473
2474static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2475{
2476 s32 index = 0;
2477 u8 aclc = 0x0b;
2478
2479 switch (state->modulation) {
2480 case STV090x_QPSK:
2481 default:
2482 index = 0;
2483 break;
2484 case STV090x_8PSK:
2485 index = 1;
2486 break;
2487 case STV090x_16APSK:
2488 index = 2;
2489 break;
2490 case STV090x_32APSK:
2491 index = 3;
2492 break;
2493 }
2494
2495 switch (state->dev_ver) {
2496 case 0x20:
2497 if (state->srate <= 3000000)
2498 aclc = stv090x_s2_short_crl[index].crl_cut20_2;
2499 else if (state->srate <= 7000000)
2500 aclc = stv090x_s2_short_crl[index].crl_cut20_5;
2501 else if (state->srate <= 15000000)
2502 aclc = stv090x_s2_short_crl[index].crl_cut20_10;
2503 else if (state->srate <= 25000000)
2504 aclc = stv090x_s2_short_crl[index].crl_cut20_20;
2505 else
2506 aclc = stv090x_s2_short_crl[index].crl_cut20_30;
2507 break;
2508
2509 case 0x12:
2510 default:
2511 if (state->srate <= 3000000)
2512 aclc = stv090x_s2_short_crl[index].crl_cut12_2;
2513 else if (state->srate <= 7000000)
2514 aclc = stv090x_s2_short_crl[index].crl_cut12_5;
2515 else if (state->srate <= 15000000)
2516 aclc = stv090x_s2_short_crl[index].crl_cut12_10;
2517 else if (state->srate <= 25000000)
2518 aclc = stv090x_s2_short_crl[index].crl_cut12_20;
2519 else
2520 aclc = stv090x_s2_short_crl[index].crl_cut12_30;
2521 break;
2522 }
2523
2524 return aclc;
2525}
2526
2527static int stv090x_optimize_track(struct stv090x_state *state)
2528{
2529 struct dvb_frontend *fe = &state->frontend;
2530
2531 enum stv090x_rolloff rolloff;
2532 enum stv090x_modcod modcod;
2533
2534 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2535 u32 reg;
2536
2537 srate = stv090x_get_srate(state, state->mclk);
2538 srate += stv090x_get_tmgoffst(state, srate);
2539
2540 switch (state->delsys) {
2541 case STV090x_DVBS1:
2542 case STV090x_DSS:
2543 if (state->algo == STV090x_SEARCH_AUTO) {
2544 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2545 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2546 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2547 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2548 goto err;
2549 }
2550 reg = STV090x_READ_DEMOD(state, DEMOD);
2551 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2552 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2553 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2554 goto err;
2555 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2556 goto err;
2557 break;
2558
2559 case STV090x_DVBS2:
2560 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2561 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2562 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2563 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2564 goto err;
2565 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2566 goto err;
2567 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2568 goto err;
2569 if (state->frame_len == STV090x_LONG_FRAME) {
2570 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2571 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2572 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2573 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2574 if (modcod <= STV090x_QPSK_910) {
2575 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2576 } else if (modcod <= STV090x_8PSK_910) {
2577 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2578 goto err;
2579 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2580 goto err;
2581 }
2582 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2583 if (modcod <= STV090x_16APSK_910) {
2584 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2585 goto err;
2586 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2587 goto err;
2588 } else {
2589 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2590 goto err;
2591 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2592 goto err;
2593 }
2594 }
2595 } else {
2596 /*Carrier loop setting for short frame*/
2597 aclc = stv090x_optimize_carloop_short(state);
2598 if (state->modulation == STV090x_QPSK) {
2599 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2600 goto err;
2601 } else if (state->modulation == STV090x_8PSK) {
2602 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2603 goto err;
2604 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2605 goto err;
2606 } else if (state->modulation == STV090x_16APSK) {
2607 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2608 goto err;
2609 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2610 goto err;
2611 } else if (state->modulation == STV090x_32APSK) {
2612 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2613 goto err;
2614 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2615 goto err;
2616 }
2617 }
2618 if (state->dev_ver <= 0x11) {
2619 if (state->demod_mode != STV090x_SINGLE)
2620 stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
2621 }
2622 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2623 break;
2624
2625 case STV090x_UNKNOWN:
2626 default:
2627 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2628 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2629 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2630 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2631 goto err;
2632 break;
2633 }
2634
2635 f_1 = STV090x_READ_DEMOD(state, CFR2);
2636 f_0 = STV090x_READ_DEMOD(state, CFR1);
2637 reg = STV090x_READ_DEMOD(state, TMGOBS);
2638 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2639
2640 if (state->algo == STV090x_BLIND_SEARCH) {
2641 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2642 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2643 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2644 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2645 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2646 goto err;
2647 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
2648 goto err;
2649 stv090x_set_srate(state, srate);
2650 stv090x_set_max_srate(state, state->mclk, srate);
2651 stv090x_set_min_srate(state, state->mclk, srate);
2652 blind_tune = 1;
2653 }
2654
2655 if (state->dev_ver >= 0x20) {
2656 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2657 (state->search_mode == STV090x_SEARCH_DSS) ||
2658 (state->search_mode == STV090x_SEARCH_AUTO)) {
2659
2660 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2661 goto err;
2662 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2663 goto err;
2664 }
2665 }
2666
2667 if (state->dev_ver < 0x20) {
2668 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
2669 goto err;
2670 }
2671 if (state->dev_ver == 0x10) {
2672 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
2673 goto err;
2674 }
2675
2676 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2677 goto err;
2678
2679 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2680
2681 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2682 goto err;
2683 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2684 goto err;
2685 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2686
2687 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2688
2689 if (state->algo != STV090x_WARM_SEARCH) {
2690
2691 stv090x_i2c_gate_ctrl(fe, 1);
2692
2693 if (state->config->tuner_set_bandwidth)
2694 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2695
2696 stv090x_i2c_gate_ctrl(fe, 0);
2697
2698 }
2699 }
2700 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2701 msleep(50); /* blind search: wait 50ms for SR stabilization */
2702 else
2703 msleep(5);
2704
2705 stv090x_get_lock_tmg(state);
2706
2707 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2708 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2709 goto err;
2710 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2711 goto err;
2712 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2713 goto err;
2714 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2715 goto err;
2716
2717 i = 0;
2718
2719 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2720
2721 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2722 goto err;
2723 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2724 goto err;
2725 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2726 goto err;
2727 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2728 goto err;
2729 i++;
2730 }
2731 }
2732
2733 }
2734
2735 if (state->dev_ver >= 0x20) {
2736 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2737 goto err;
2738 }
2739 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2740 stv090x_set_vit_thtracq(state);
2741
2742 return 0;
2743err:
2744 dprintk(FE_ERROR, 1, "I/O error");
2745 return -1;
2746}
2747
2748static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2749{
2750 s32 timer = 0, lock = 0, stat;
2751 u32 reg;
2752
2753 while ((timer < timeout) && (!lock)) {
2754 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2755 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2756
2757 switch (stat) {
2758 case 0: /* searching */
2759 case 1: /* first PLH detected */
2760 default:
2761 lock = 0;
2762 break;
2763
2764 case 2: /* DVB-S2 mode */
2765 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2766 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2767 break;
2768
2769 case 3: /* DVB-S1/legacy mode */
2770 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2771 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
2772 break;
2773 }
2774 if (!lock) {
2775 msleep(10);
2776 timer += 10;
2777 }
2778 }
2779 return lock;
2780}
2781
2782static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
2783{
2784 u32 reg;
2785 s32 timer = 0;
2786 int lock;
2787
2788 lock = stv090x_get_dmdlock(state, timeout_dmd);
2789 if (lock)
2790 lock = stv090x_get_feclock(state, timeout_fec);
2791
2792 if (lock) {
2793 lock = 0;
2794
2795 while ((timer < timeout_fec) && (!lock)) {
2796 reg = STV090x_READ_DEMOD(state, TSSTATUS);
2797 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
2798 msleep(1);
2799 timer++;
2800 }
2801 }
2802
2803 return lock;
2804}
2805
2806static int stv090x_set_s2rolloff(struct stv090x_state *state)
2807{
2808 s32 rolloff;
2809 u32 reg;
2810
2811 if (state->dev_ver == 0x10) {
2812 reg = STV090x_READ_DEMOD(state, DEMOD);
2813 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2814 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2815 goto err;
2816 rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
2817 reg = STV090x_READ_DEMOD(state, DEMOD);
2818 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
2819 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2820 goto err;
2821 } else {
2822 reg = STV090x_READ_DEMOD(state, DEMOD);
2823 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
2824 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2825 goto err;
2826 }
2827 return 0;
2828err:
2829 dprintk(FE_ERROR, 1, "I/O error");
2830 return -1;
2831}
2832
2833static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
2834{
2835 s32 srate, f_1, f_2;
2836 enum stv090x_signal_state signal_state = STV090x_NODATA;
2837 u32 reg;
2838 int lock;
2839
2840 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2841 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
2842 srate = stv090x_get_srate(state, state->mclk);
2843 srate += stv090x_get_tmgoffst(state, state->srate);
2844
2845 if (state->algo == STV090x_BLIND_SEARCH)
2846 stv090x_set_srate(state, state->srate);
2847
2848 stv090x_get_lock_tmg(state);
2849
2850 f_1 = STV090x_READ_DEMOD(state, CFR2);
2851 f_2 = STV090x_READ_DEMOD(state, CFR1);
2852
2853 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2854 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
2855 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2856 goto err;
2857
2858 reg = STV090x_READ_DEMOD(state, DEMOD);
2859 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
2860 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2861 goto err;
2862 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
2863 goto err;
2864 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2865 goto err;
2866 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2867 goto err;
2868 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2869 goto err;
2870
2871 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2872 lock = 1;
2873 stv090x_get_sig_params(state);
2874 stv090x_optimize_track(state);
2875 } else {
2876 reg = STV090x_READ_DEMOD(state, DEMOD);
2877 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
2878 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2879 goto err;
2880 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2881 goto err;
2882 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2883 goto err;
2884 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2885 goto err;
2886 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2887 goto err;
2888 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2889 lock = 1;
2890 signal_state = stv090x_get_sig_params(state);
2891 stv090x_optimize_track(state);
2892 }
2893 }
2894 } else {
2895 lock = 0;
2896 }
2897
2898 return signal_state;
2899
2900err:
2901 dprintk(FE_ERROR, 1, "I/O error");
2902 return -1;
2903}
2904
2905static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
2906{
2907 struct dvb_frontend *fe = &state->frontend;
2908 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
2909 u32 reg;
2910 s32 timeout_dmd = 500, timeout_fec = 50;
2911 int lock = 0, low_sr, no_signal = 0;
2912
2913 reg = STV090x_READ_DEMOD(state, TSCFGH);
2914 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
2915 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2916 goto err;
2917
2918 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
2919 goto err;
2920
2921 if (state->dev_ver >= 0x20) {
2922 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
2923 goto err;
2924 } else {
2925 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
2926 goto err;
2927 }
2928
2929 stv090x_get_lock_tmg(state);
2930
2931 if (state->algo == STV090x_BLIND_SEARCH) {
2932 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
2933 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
2934 goto err;
2935 stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
2936 } else {
2937 /* known srate */
2938 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
2939 goto err;
2940 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
2941 goto err;
2942
2943 if (state->srate >= 10000000) {
2944 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
2945 goto err;
2946 } else {
2947 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
2948 goto err;
2949 }
2950
2951 if (state->dev_ver >= 0x20) {
2952 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
2953 goto err;
2954 if (state->algo == STV090x_COLD_SEARCH)
2955 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 1000000)) / 10;
2956 else if (state->algo == STV090x_WARM_SEARCH)
2957 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
2958 } else {
2959 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
2960 goto err;
2961 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
2962 }
2963 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
2964 goto err;
2965 stv090x_set_srate(state, state->srate);
2966 stv090x_set_max_srate(state, state->mclk, state->srate);
2967 stv090x_set_min_srate(state, state->mclk, state->srate);
2968
2969 if (state->srate >= 10000000)
2970 low_sr = 1;
2971 }
2972
2973 /* Setup tuner */
2974 stv090x_i2c_gate_ctrl(fe, 1);
2975
2976 if (state->config->tuner_set_bbgain)
2977 state->config->tuner_set_bbgain(fe, 10); /* 10dB */
2978
2979 if (state->config->tuner_set_frequency)
2980 state->config->tuner_set_frequency(fe, state->frequency);
2981
2982 if (state->config->tuner_set_bandwidth)
2983 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2984
2985 stv090x_i2c_gate_ctrl(fe, 0);
2986
2987 msleep(50);
2988
2989 stv090x_i2c_gate_ctrl(fe, 1);
2990
2991 if (state->config->tuner_get_status)
2992 state->config->tuner_get_status(fe, &reg);
2993
2994 if (reg)
2995 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2996 else
2997 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2998
2999 stv090x_i2c_gate_ctrl(fe, 0);
3000
3001 reg = STV090x_READ_DEMOD(state, DEMOD);
3002 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3003 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
3004 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3005 goto err;
3006 stv090x_delivery_search(state);
3007 if (state->algo == STV090x_BLIND_SEARCH)
3008 stv090x_start_search(state);
3009
3010 if (state->dev_ver == 0x12) {
3011 reg = STV090x_READ_DEMOD(state, TSCFGH);
3012 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3013 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3014 goto err;
3015 msleep(3);
3016 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3017 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3018 goto err;
3019 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3020 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3021 goto err;
3022 }
3023
3024 if (state->algo == STV090x_BLIND_SEARCH)
3025 lock = stv090x_blind_search(state);
3026 else if (state->algo == STV090x_COLD_SEARCH)
3027 lock = stv090x_get_coldlock(state, timeout_dmd);
3028 else if (state->algo == STV090x_WARM_SEARCH)
3029 lock = stv090x_get_dmdlock(state, timeout_dmd);
3030
3031 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3032 if (!low_sr) {
3033 if (stv090x_chk_tmg(state))
3034 lock = stv090x_sw_algo(state);
3035 }
3036 }
3037
3038 if (lock)
3039 signal_state = stv090x_get_sig_params(state);
3040
3041 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3042 stv090x_optimize_track(state);
3043 if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
3044 if (stv090x_get_std(state) == STV090x_DVBS1) {
3045 msleep(20);
3046 reg = STV090x_READ_DEMOD(state, TSCFGH);
3047 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3048 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3049 goto err;
3050 } else {
3051 reg = STV090x_READ_DEMOD(state, TSCFGH);
3052 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3053 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3054 goto err;
3055 msleep(3);
3056 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3057 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3058 goto err;
3059 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3060 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3061 goto err;
3062 }
3063 } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
3064 reg = STV090x_READ_DEMOD(state, TSCFGH);
3065 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3066 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3067 goto err;
3068 msleep(3);
3069 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3070 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3071 goto err;
3072
3073 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3074 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3075 goto err;
3076 }
3077
3078 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3079 lock = 1;
3080 if (state->delsys == STV090x_DVBS2) {
3081 stv090x_set_s2rolloff(state);
3082 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
3083 goto err;
3084 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
3085 goto err;
3086 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3087 goto err;
3088 } else {
3089 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3090 goto err;
3091 }
3092 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3093 goto err;
3094 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3095 goto err;
3096 } else {
3097 lock = 0;
3098 signal_state = STV090x_NODATA;
3099 no_signal = stv090x_chk_signal(state);
3100 }
3101 }
3102 if ((signal_state == STV090x_NODATA) && (!no_signal)) {
3103 if (state->dev_ver <= 0x11) {
3104 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3105 if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
3106 signal_state = stv090x_acq_fixs1(state);
3107 }
3108 }
3109 return signal_state;
3110
3111err:
3112 dprintk(FE_ERROR, 1, "I/O error");
3113 return -1;
3114}
3115
3116static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3117{
3118 struct stv090x_state *state = fe->demodulator_priv;
3119 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3120
3121 state->delsys = props->delivery_system;
3122 state->frequency = p->frequency;
3123 state->srate = p->u.qpsk.symbol_rate;
3124
3125 if (!stv090x_algo(state)) {
3126 dprintk(FE_DEBUG, 1, "Search success!");
3127 return DVBFE_ALGO_SEARCH_SUCCESS;
3128 } else {
3129 dprintk(FE_DEBUG, 1, "Search failed!");
3130 return DVBFE_ALGO_SEARCH_FAILED;
3131 }
3132
3133 return DVBFE_ALGO_SEARCH_ERROR;
3134}
3135
3136/* FIXME! */
3137static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3138{
3139 struct stv090x_state *state = fe->demodulator_priv;
3140 u32 reg;
3141 u8 search_state;
3142 int locked = 0;
3143
3144 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3145 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3146
3147 switch (search_state) {
3148 case 0: /* searching */
3149 case 1: /* first PLH detected */
3150 default:
3151 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3152 locked = 0;
3153 break;
3154
3155 case 2: /* DVB-S2 mode */
3156 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3157 reg = STV090x_READ_DEMOD(state, DSTATUS);
3158 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3159 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3160 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3161 locked = 1;
3162 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3163 }
3164 }
3165 break;
3166
3167 case 3: /* DVB-S1/legacy mode */
3168 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3169 reg = STV090x_READ_DEMOD(state, DSTATUS);
3170 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3171 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3172 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3173 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3174 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3175 locked = 1;
3176 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3177 }
3178 }
3179 }
3180 break;
3181 }
3182
3183 return locked;
3184}
3185
3186static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3187{
3188 struct stv090x_state *state = fe->demodulator_priv;
3189
3190 s32 count_4, count_3, count_2, count_1, count_0, count;
3191 u32 reg, h, m, l;
3192 enum fe_status status;
3193
3194 if (!stv090x_read_status(fe, &status)) {
3195 *per = 1 << 23; /* Max PER */
3196 } else {
3197 /* Counter 2 */
3198 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3199 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3200
3201 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3202 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3203
3204 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3205 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3206
3207 *per = ((h << 16) | (m << 8) | l);
3208
3209 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3210 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3211 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3212 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3213 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3214
3215 if ((!count_4) && (!count_3)) {
3216 count = (count_2 & 0xff) << 16;
3217 count |= (count_1 & 0xff) << 8;
3218 count |= count_0 & 0xff;
3219 } else {
3220 count = 1 << 24;
3221 }
3222 if (count == 0)
3223 *per = 1;
3224 }
3225 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3226 goto err;
3227 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3228 goto err;
3229
3230 return 0;
3231err:
3232 dprintk(FE_ERROR, 1, "I/O error");
3233 return -1;
3234}
3235
3236static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3237{
3238 int res = 0;
3239 int min = 0, med;
3240
3241 if (val < tab[min].read)
3242 res = tab[min].real;
3243 else if (val >= tab[max].read)
3244 res = tab[max].real;
3245 else {
3246 while ((max - min) > 1) {
3247 med = (max + min) / 2;
3248 if (val >= tab[min].read && val < tab[med].read)
3249 max = med;
3250 else
3251 min = med;
3252 }
3253 res = ((val - tab[min].read) *
3254 (tab[max].real - tab[min].real) /
3255 (tab[max].read - tab[min].read)) +
3256 tab[min].real;
3257 }
3258
3259 return res;
3260}
3261
3262static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3263{
3264 struct stv090x_state *state = fe->demodulator_priv;
3265 u32 reg;
3266 s32 agc;
3267
3268 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3269 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3270
3271 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3272 if (agc > stv090x_rf_tab[0].read)
3273 *strength = 5;
3274 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3275 *strength = -100;
3276
3277 return 0;
3278}
3279
3280static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3281{
3282 struct stv090x_state *state = fe->demodulator_priv;
3283 u32 reg_0, reg_1, reg, i;
3284 s32 val_0, val_1, val = 0;
3285 u8 lock_f;
3286
3287 switch (state->delsys) {
3288 case STV090x_DVBS2:
3289 reg = STV090x_READ_DEMOD(state, DSTATUS);
3290 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3291 if (lock_f) {
3292 msleep(5);
3293 for (i = 0; i < 16; i++) {
3294 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3295 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3296 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3297 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3298 val += MAKEWORD16(val_1, val_0);
3299 msleep(1);
3300 }
3301 val /= 16;
3302 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
3303 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
3304 *cnr = 1000;
3305 }
3306 break;
3307
3308 case STV090x_DVBS1:
3309 case STV090x_DSS:
3310 reg = STV090x_READ_DEMOD(state, DSTATUS);
3311 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3312 if (lock_f) {
3313 msleep(5);
3314 for (i = 0; i < 16; i++) {
3315 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3316 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3317 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3318 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3319 val += MAKEWORD16(val_1, val_0);
3320 msleep(1);
3321 }
3322 val /= 16;
3323 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
3324 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
3325 *cnr = 1000;
3326 }
3327 break;
3328 default:
3329 break;
3330 }
3331
3332 return 0;
3333}
3334
3335static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3336{
3337 struct stv090x_state *state = fe->demodulator_priv;
3338 u32 reg;
3339
3340 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3341 switch (tone) {
3342 case SEC_TONE_ON:
3343 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3344 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3345 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3346 goto err;
3347 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3348 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3349 goto err;
3350 break;
3351
3352 case SEC_TONE_OFF:
3353 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3354 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3355 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3356 goto err;
3357 break;
3358 default:
3359 return -EINVAL;
3360 }
3361
3362 return 0;
3363err:
3364 dprintk(FE_ERROR, 1, "I/O error");
3365 return -1;
3366}
3367
3368
3369static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3370{
3371 return DVBFE_ALGO_CUSTOM;
3372}
3373
3374static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3375{
3376 struct stv090x_state *state = fe->demodulator_priv;
3377 u32 reg, idle = 0, fifo_full = 1;
3378 int i;
3379
3380 reg = STV090x_READ_DEMOD(state, DISTXCTL);
f9ed95d0
AR		 3381
3382 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
3383 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3384 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3385 goto err;
3386 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3387 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3388 goto err;
3389
e415c689
MA		 3390 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3391 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3392 goto err;
3393
3394 for (i = 0; i < cmd->msg_len; i++) {
3395
3396 while (fifo_full) {
3397 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3398 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3399 }
3400
3401 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3402 goto err;
f9ed95d0
AR		 3403 }
3404 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3405 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3406 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3407 goto err;
3408
3409 i = 0;
3410
3411 while ((!idle) && (i < 10)) {
3412 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3413 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3414 msleep(10);
e415c689
MA		 3415 i++;
3416 }
f9ed95d0
AR		 3417
3418 return 0;
3419err:
3420 dprintk(FE_ERROR, 1, "I/O error");
3421 return -1;
3422}
3423
3424static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3425{
3426 struct stv090x_state *state = fe->demodulator_priv;
3427 u32 reg, idle = 0, fifo_full = 1;
3428 u8 mode, value;
3429 int i;
3430
3431 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3432
3433 if (burst == SEC_MINI_A) {
3434 mode = 3;
3435 value = 0x00;
3436 } else {
3437 mode = 2;
3438 value = 0xFF;
3439 }
3440
3441 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3442 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3443 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3444 goto err;
3445 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3446 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3447 goto err;
3448
3449 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3450 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3451 goto err;
3452
3453 while (fifo_full) {
3454 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3455 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3456 }
3457
3458 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3459 goto err;
3460
e415c689
MA		 3461 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3462 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3463 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3464 goto err;
3465
3466 i = 0;
3467
3468 while ((!idle) && (i < 10)) {
3469 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3470 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3471 msleep(10);
3472 i++;
3473 }
3474
3475 return 0;
3476err:
3477 dprintk(FE_ERROR, 1, "I/O error");
3478 return -1;
3479}
3480
3481static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3482{
3483 struct stv090x_state *state = fe->demodulator_priv;
3484 u32 reg = 0, i = 0, rx_end = 0;
3485
3486 while ((rx_end != 1) && (i < 10)) {
3487 msleep(10);
3488 i++;
3489 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3490 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3491 }
3492
3493 if (rx_end) {
3494 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3495 for (i = 0; i < reply->msg_len; i++)
3496 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3497 }
3498
3499 return 0;
3500}
3501
3502static int stv090x_sleep(struct dvb_frontend *fe)
3503{
3504 struct stv090x_state *state = fe->demodulator_priv;
3505 u32 reg;
3506
3507 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3508 state->device == STV0900 ? "STV0900" : "STV0903");
3509
3510 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3511 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3512 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3513 goto err;
3514
26b03bc6
MA		 3515 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3516 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3517 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3518 goto err;
3519
e415c689
MA		 3520 return 0;
3521err:
3522 dprintk(FE_ERROR, 1, "I/O error");
3523 return -1;
3524}
3525
3526static int stv090x_wakeup(struct dvb_frontend *fe)
3527{
3528 struct stv090x_state *state = fe->demodulator_priv;
3529 u32 reg;
3530
3531 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3532 state->device == STV0900 ? "STV0900" : "STV0903");
3533
3534 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3535 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3536 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3537 goto err;
3538
26b03bc6
MA		 3539 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3540 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3541 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3542 goto err;
3543
e415c689
MA		 3544 return 0;
3545err:
3546 dprintk(FE_ERROR, 1, "I/O error");
3547 return -1;
3548}
3549
3550static void stv090x_release(struct dvb_frontend *fe)
3551{
3552 struct stv090x_state *state = fe->demodulator_priv;
3553
3554 kfree(state);
3555}
3556
3557static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3558{
3559 u32 reg;
3560
3561 switch (ldpc_mode) {
3562 case STV090x_DUAL:
3563 default:
3564 reg = stv090x_read_reg(state, STV090x_GENCFG);
3565 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3566 /* follow LDPC default state */
3567 if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
3568 goto err;
3569 state->demod_mode = STV090x_DUAL;
3570 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3571 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3572 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3573 goto err;
3574 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3575 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3576 goto err;
3577 }
3578 break;
3579
3580 case STV090x_SINGLE:
3581 if (state->demod == STV090x_DEMODULATOR_1) {
3582 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3583 goto err;
3584 } else {
3585 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3586 goto err;
3587 }
3588
3589 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3590 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3591 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3592 goto err;
3593 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3594 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3595 goto err;
3596
3597 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3598 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3599 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3600 goto err;
3601 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3602 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3603 goto err;
3604 break;
3605 }
3606
3607 return 0;
3608err:
3609 dprintk(FE_ERROR, 1, "I/O error");
3610 return -1;
3611}
3612
3613/* return (Hz), clk in Hz*/
3614static u32 stv090x_get_mclk(struct stv090x_state *state)
3615{
3616 const struct stv090x_config *config = state->config;
3617 u32 div, reg;
3618 u8 ratio;
3619
3620 div = stv090x_read_reg(state, STV090x_NCOARSE);
3621 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3622 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3623
3624 return (div + 1) * config->xtal / ratio; /* kHz */
3625}
3626
3627static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3628{
3629 const struct stv090x_config *config = state->config;
3630 u32 reg, div, clk_sel;
3631
3632 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3633 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3634
3635 div = ((clk_sel * mclk) / config->xtal) - 1;
3636
3637 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3638 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3639 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3640 goto err;
3641
3642 state->mclk = stv090x_get_mclk(state);
3643
94a80914
MA		 3644 /*Set the DiseqC frequency to 22KHz */
3645 div = state->mclk / 704000;
3646 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
3647 goto err;
3648 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
3649 goto err;
3650
e415c689
MA		 3651 return 0;
3652err:
3653 dprintk(FE_ERROR, 1, "I/O error");
3654 return -1;
3655}
3656
3657static int stv090x_set_tspath(struct stv090x_state *state)
3658{
3659 u32 reg;
3660
3661 if (state->dev_ver >= 0x20) {
3662 switch (state->config->ts1_mode) {
3663 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3664 case STV090x_TSMODE_DVBCI:
3665 switch (state->config->ts2_mode) {
3666 case STV090x_TSMODE_SERIAL_PUNCTURED:
3667 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3668 default:
3669 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3670 break;
3671
3672 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3673 case STV090x_TSMODE_DVBCI:
3674 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3675 goto err;
3676 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3677 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3678 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3679 goto err;
3680 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3681 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3682 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3683 goto err;
3684 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3685 goto err;
3686 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3687 goto err;
3688 break;
3689 }
3690 break;
3691
3692 case STV090x_TSMODE_SERIAL_PUNCTURED:
3693 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3694 default:
3695 switch (state->config->ts2_mode) {
3696 case STV090x_TSMODE_SERIAL_PUNCTURED:
3697 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3698 default:
3699 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3700 goto err;
3701 break;
3702
3703 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3704 case STV090x_TSMODE_DVBCI:
3705 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3706 goto err;
3707 break;
3708 }
3709 break;
3710 }
3711 } else {
3712 switch (state->config->ts1_mode) {
3713 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3714 case STV090x_TSMODE_DVBCI:
3715 switch (state->config->ts2_mode) {
3716 case STV090x_TSMODE_SERIAL_PUNCTURED:
3717 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3718 default:
56571507 3719 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
e415c689
MA		 3720 break;
3721
3722 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3723 case STV090x_TSMODE_DVBCI:
56571507 3724 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
e415c689
MA		 3725 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3726 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3727 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3728 goto err;
3729 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3730 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3731 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3732 goto err;
3733 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3734 goto err;
3735 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3736 goto err;
3737 break;
3738 }
3739 break;
3740
3741 case STV090x_TSMODE_SERIAL_PUNCTURED:
3742 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3743 default:
3744 switch (state->config->ts2_mode) {
3745 case STV090x_TSMODE_SERIAL_PUNCTURED:
3746 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3747 default:
56571507 3748 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
e415c689
MA		 3749 break;
3750
3751 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3752 case STV090x_TSMODE_DVBCI:
56571507 3753 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
e415c689
MA		 3754 break;
3755 }
3756 break;
3757 }
3758 }
3759
3760 switch (state->config->ts1_mode) {
3761 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3762 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3763 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3764 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3765 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3766 goto err;
3767 break;
3768
3769 case STV090x_TSMODE_DVBCI:
3770 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3771 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3772 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3773 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3774 goto err;
3775 break;
3776
3777 case STV090x_TSMODE_SERIAL_PUNCTURED:
3778 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3779 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3780 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3781 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3782 goto err;
3783 break;
3784
3785 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3786 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3787 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3788 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3789 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3790 goto err;
3791 break;
3792
3793 default:
3794 break;
3795 }
3796
3797 switch (state->config->ts2_mode) {
3798 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3799 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3800 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3801 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3802 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3803 goto err;
3804 break;
3805
3806 case STV090x_TSMODE_DVBCI:
3807 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3808 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3809 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3810 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3811 goto err;
3812 break;
3813
3814 case STV090x_TSMODE_SERIAL_PUNCTURED:
3815 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3816 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3817 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3818 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3819 goto err;
3820 break;
3821
3822 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3823 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3824 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3825 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3826 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3827 goto err;
3828 break;
3829
3830 default:
3831 break;
3832 }
3833 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
3834 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3835 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3836 goto err;
3837 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3838 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3839 goto err;
3840
3841 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3842 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3843 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3844 goto err;
3845 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3846 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3847 goto err;
3848
3849 return 0;
3850err:
3851 dprintk(FE_ERROR, 1, "I/O error");
3852 return -1;
3853}
3854
3855static int stv090x_init(struct dvb_frontend *fe)
3856{
3857 struct stv090x_state *state = fe->demodulator_priv;
3858 const struct stv090x_config *config = state->config;
3859 u32 reg;
3860
3861 stv090x_ldpc_mode(state, state->demod_mode);
3862
3863 reg = STV090x_READ_DEMOD(state, TNRCFG2);
3864 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
3865 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
3866 goto err;
3867 reg = STV090x_READ_DEMOD(state, DEMOD);
3868 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
3869 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3870 goto err;
3871
3872 stv090x_i2c_gate_ctrl(fe, 1);
3873
3874 if (config->tuner_init)
3875 config->tuner_init(fe);
3876
3877 stv090x_i2c_gate_ctrl(fe, 0);
3878
3879 stv090x_set_tspath(state);
3880
3881 return 0;
3882err:
3883 dprintk(FE_ERROR, 1, "I/O error");
3884 return -1;
3885}
3886
3887static int stv090x_setup(struct dvb_frontend *fe)
3888{
3889 struct stv090x_state *state = fe->demodulator_priv;
3890 const struct stv090x_config *config = state->config;
3891 const struct stv090x_reg *stv090x_initval = NULL;
3892 const struct stv090x_reg *stv090x_cut20_val = NULL;
3893 unsigned long t1_size = 0, t2_size = 0;
017eb038 3894 u32 reg = 0;
e415c689
MA		 3895
3896 int i;
3897
3898 if (state->device == STV0900) {
3899 dprintk(FE_DEBUG, 1, "Initializing STV0900");
3900 stv090x_initval = stv0900_initval;
3901 t1_size = ARRAY_SIZE(stv0900_initval);
3902 stv090x_cut20_val = stv0900_cut20_val;
3903 t2_size = ARRAY_SIZE(stv0900_cut20_val);
3904 } else if (state->device == STV0903) {
3905 dprintk(FE_DEBUG, 1, "Initializing STV0903");
3906 stv090x_initval = stv0903_initval;
3907 t1_size = ARRAY_SIZE(stv0903_initval);
3908 stv090x_cut20_val = stv0903_cut20_val;
3909 t2_size = ARRAY_SIZE(stv0903_cut20_val);
3910 }
3911
3912 /* STV090x init */
3913 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
3914 goto err;
3915
3916 msleep(5);
3917
3918 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
3919 goto err;
3920
017eb038
MA		 3921 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
3922 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
e415c689
MA		 3923 goto err;
3924
3925 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
3926 goto err;
3927 msleep(5);
3928 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
3929 goto err;
3930 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
3931 goto err;
3932 msleep(5);
3933
3934 /* write initval */
3935 for (i = 0; i < t1_size; i++) {
3936 dprintk(FE_DEBUG, 1, "Setting up initial values");
3937 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
3938 goto err;
3939 }
3940
3941 if (state->dev_ver >= 0x20) {
3942 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3943 goto err;
3944
3945 /* write cut20_val*/
3946 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
3947 for (i = 0; i < t2_size; i++) {
3948 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
3949 goto err;
3950 }
3951 }
3952
3953 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
3954 goto err;
3955 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
3956 goto err;
3957
3958 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
3959 msleep(5);
3960 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
3961 goto err;
3962 stv090x_get_mclk(state);
3963
3964 return 0;
3965err:
3966 dprintk(FE_ERROR, 1, "I/O error");
3967 return -1;
3968}
3969
3970static struct dvb_frontend_ops stv090x_ops = {
3971
3972 .info = {
3973 .name = "STV090x Multistandard",
3974 },
3975
3976 .release = stv090x_release,
3977 .init = stv090x_init,
3978
3979 .sleep = stv090x_sleep,
3980 .get_frontend_algo = stv090x_frontend_algo,
3981
3982 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
3983
3984 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
f9ed95d0 3985 .diseqc_send_burst = stv090x_send_diseqc_burst,
e415c689
MA		 3986 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
3987 .set_tone = stv090x_set_tone,
3988
3989 .search = stv090x_search,
3990 .read_status = stv090x_read_status,
3991 .read_ber = stv090x_read_per,
3992 .read_signal_strength = stv090x_read_signal_strength,
3993 .read_snr = stv090x_read_cnr
3994};
3995
3996
3997struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
3998 struct i2c_adapter *i2c,
3999 enum stv090x_demodulator demod)
4000{
4001 struct stv090x_state *state = NULL;
4002
4003 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4004 if (state == NULL)
4005 goto error;
4006
4007 state->verbose = &verbose;
4008 state->config = config;
4009 state->i2c = i2c;
4010 state->frontend.ops = stv090x_ops;
4011 state->frontend.demodulator_priv = state;
56571507 4012 state->demod = demod;
e415c689
MA		 4013 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4014 state->device = config->device;
4015 state->rolloff = 35; /* default */
4016
4017 if (state->demod == STV090x_DEMODULATOR_0)
4018 mutex_init(&demod_lock);
4019
4020 if (stv090x_sleep(&state->frontend) < 0) {
4021 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4022 goto error;
4023 }
4024
4025 if (stv090x_setup(&state->frontend) < 0) {
4026 dprintk(FE_ERROR, 1, "Error setting up device");
4027 goto error;
4028 }
4029 if (stv090x_wakeup(&state->frontend) < 0) {
4030 dprintk(FE_ERROR, 1, "Error waking device");
4031 goto error;
4032 }
4033 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
4034
4035 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
4036 state->device == STV0900 ? "STV0900" : "STV0903",
4037 demod,
4038 state->dev_ver);
4039
4040 return &state->frontend;
4041
4042error:
4043 kfree(state);
4044 return NULL;
4045}
4046EXPORT_SYMBOL(stv090x_attach);
4047MODULE_PARM_DESC(verbose, "Set Verbosity level");
4048MODULE_AUTHOR("Manu Abraham");
4049MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4050MODULE_LICENSE("GPL");
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