]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/media/dvb/ngene/ngene.h
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] ngene: CXD2099AR Common Interface driver
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb / ngene / ngene.h
CommitLineData
dae52d00
MB		 1/*
2 * ngene.h: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _NGENE_H_
25#define _NGENE_H_
26
dae52d00
MB		 27#include <linux/types.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/i2c.h>
31#include <asm/dma.h>
684688d8 32#include <linux/scatterlist.h>
dae52d00
MB		 33
34#include <linux/dvb/frontend.h>
dae52d00
MB		 35
36#include "dmxdev.h"
37#include "dvbdev.h"
38#include "dvb_demux.h"
0f0b270f 39#include "dvb_ca_en50221.h"
dae52d00
MB		 40#include "dvb_frontend.h"
41#include "dvb_ringbuffer.h"
0f0b270f 42#include "cxd2099.h"
dae52d00 43
cbddcba6
DH		 44#define DEVICE_NAME "ngene"
45
dae52d00
MB		 46#define NGENE_VID 0x18c3
47#define NGENE_PID 0x0720
48
49#ifndef VIDEO_CAP_VC1
50#define VIDEO_CAP_AVC 128
51#define VIDEO_CAP_H264 128
52#define VIDEO_CAP_VC1 256
53#define VIDEO_CAP_WMV9 256
54#define VIDEO_CAP_MPEG4 512
55#endif
56
57enum STREAM {
58 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
59 STREAM_VIDEOIN2,
60 STREAM_AUDIOIN1, /* I2S or SPI Input */
61 STREAM_AUDIOIN2,
62 STREAM_AUDIOOUT,
63 MAX_STREAM
64};
65
66enum SMODE_BITS {
67 SMODE_AUDIO_SPDIF = 0x20,
68 SMODE_AVSYNC = 0x10,
69 SMODE_TRANSPORT_STREAM = 0x08,
70 SMODE_AUDIO_CAPTURE = 0x04,
71 SMODE_VBI_CAPTURE = 0x02,
72 SMODE_VIDEO_CAPTURE = 0x01
73};
74
75enum STREAM_FLAG_BITS {
76 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
77 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
78 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
79 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
80 SFLAG_COLORBAR = 0x04, /* Select colorbar */
81};
82
83#define PROGRAM_ROM 0x0000
84#define PROGRAM_SRAM 0x1000
85#define PERIPHERALS0 0x8000
86#define PERIPHERALS1 0x9000
87#define SHARED_BUFFER 0xC000
88
89#define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
90#define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
91#define NGENE_COMMAND (SHARED_BUFFER+0x0200)
92#define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
93#define NGENE_STATUS (SHARED_BUFFER+0x0208)
94#define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
95#define NGENE_EVENT (SHARED_BUFFER+0x0210)
96#define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
97#define VARIABLES (SHARED_BUFFER+0x0210)
98
99#define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
100#define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
101#define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
102
103#define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
104#define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
105#define EEPROM_AREA (SHARED_BUFFER+0x0A00)
106
107#define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
108#define SG_VBI_1 (SHARED_BUFFER+0x0B00)
109#define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
110#define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
111#define SG_VBI_2 (SHARED_BUFFER+0x0C80)
112#define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
113#define SG_V_OUT (SHARED_BUFFER+0x0D80)
114#define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
115
116#define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
117#define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
118#define DATA_A_OUT (SHARED_BUFFER+0x0F80)
119#define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
120#define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
121#define DATA_V_OUT (SHARED_BUFFER+0x3000)
122
123#define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
124
125#define TIMESTAMPS 0xA000
126#define SCRATCHPAD 0xA080
127#define FORCE_INT 0xA088
128#define FORCE_NMI 0xA090
129#define INT_STATUS 0xA0A0
130
131#define DEV_VER 0x9004
132
133#define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
134
135struct SG_ADDR {
136 u64 start;
137 u64 curr;
138 u16 curr_ptr;
139 u16 elements;
140 u32 pad[3];
141} __attribute__ ((__packed__));
142
143struct SHARED_MEMORY {
144 /* C000 */
145 u32 HostToNgene[64];
146
147 /* C100 */
148 u32 NgeneToHost[64];
149
150 /* C200 */
151 u64 NgeneCommand;
152 u64 NgeneStatus;
153 u64 NgeneEvent;
154
155 /* C210 */
156 u8 pad1[0xc260 - 0xc218];
157
158 /* C260 */
159 u32 IntCounts;
160 u32 IntEnable;
161
162 /* C268 */
163 u8 pad2[0xd000 - 0xc268];
164
165} __attribute__ ((__packed__));
166
167struct BUFFER_STREAM_RESULTS {
168 u32 Clock; /* Stream time in 100ns units */
169 u16 RemainingLines; /* Remaining lines in this field.
170 0 for complete field */
171 u8 FieldCount; /* Video field number */
172 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
173 Bit 0 = FieldID */
174 u16 BlockCount; /* Audio block count (unused) */
175 u8 Reserved[2];
176 u32 DTOUpdate;
177} __attribute__ ((__packed__));
178
179struct HW_SCATTER_GATHER_ELEMENT {
180 u64 Address;
181 u32 Length;
182 u32 Reserved;
183} __attribute__ ((__packed__));
184
185struct BUFFER_HEADER {
186 u64 Next;
187 struct BUFFER_STREAM_RESULTS SR;
188
189 u32 Number_of_entries_1;
190 u32 Reserved5;
191 u64 Address_of_first_entry_1;
192
193 u32 Number_of_entries_2;
194 u32 Reserved7;
195 u64 Address_of_first_entry_2;
196} __attribute__ ((__packed__));
197
198struct EVENT_BUFFER {
199 u32 TimeStamp;
200 u8 GPIOStatus;
201 u8 UARTStatus;
202 u8 RXCharacter;
203 u8 EventStatus;
204 u32 Reserved[2];
205} __attribute__ ((__packed__));
206
dae52d00
MB		 207/* Firmware commands. */
208
209enum OPCODES {
210 CMD_NOP = 0,
211 CMD_FWLOAD_PREPARE = 0x01,
212 CMD_FWLOAD_FINISH = 0x02,
213 CMD_I2C_READ = 0x03,
214 CMD_I2C_WRITE = 0x04,
215
216 CMD_I2C_WRITE_NOSTOP = 0x05,
217 CMD_I2C_CONTINUE_WRITE = 0x06,
218 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
219
220 CMD_DEBUG_OUTPUT = 0x09,
221
222 CMD_CONTROL = 0x10,
223 CMD_CONFIGURE_BUFFER = 0x11,
224 CMD_CONFIGURE_FREE_BUFFER = 0x12,
225
226 CMD_SPI_READ = 0x13,
227 CMD_SPI_WRITE = 0x14,
228
229 CMD_MEM_READ = 0x20,
230 CMD_MEM_WRITE = 0x21,
231 CMD_SFR_READ = 0x22,
232 CMD_SFR_WRITE = 0x23,
233 CMD_IRAM_READ = 0x24,
234 CMD_IRAM_WRITE = 0x25,
235 CMD_SET_GPIO_PIN = 0x26,
236 CMD_SET_GPIO_INT = 0x27,
237 CMD_CONFIGURE_UART = 0x28,
238 CMD_WRITE_UART = 0x29,
239 MAX_CMD
240};
241
242enum RESPONSES {
243 OK = 0,
244 ERROR = 1
245};
246
247struct FW_HEADER {
248 u8 Opcode;
249 u8 Length;
250} __attribute__ ((__packed__));
251
252struct FW_I2C_WRITE {
253 struct FW_HEADER hdr;
254 u8 Device;
255 u8 Data[250];
256} __attribute__ ((__packed__));
257
258struct FW_I2C_CONTINUE_WRITE {
259 struct FW_HEADER hdr;
260 u8 Data[250];
261} __attribute__ ((__packed__));
262
263struct FW_I2C_READ {
264 struct FW_HEADER hdr;
265 u8 Device;
266 u8 Data[252]; /* followed by two bytes of read data count */
267} __attribute__ ((__packed__));
268
269struct FW_SPI_WRITE {
270 struct FW_HEADER hdr;
271 u8 ModeSelect;
272 u8 Data[250];
273} __attribute__ ((__packed__));
274
275struct FW_SPI_READ {
276 struct FW_HEADER hdr;
277 u8 ModeSelect;
278 u8 Data[252]; /* followed by two bytes of read data count */
279} __attribute__ ((__packed__));
280
281struct FW_FWLOAD_PREPARE {
282 struct FW_HEADER hdr;
283} __attribute__ ((__packed__));
284
285struct FW_FWLOAD_FINISH {
286 struct FW_HEADER hdr;
287 u16 Address; /* address of final block */
288 u16 Length;
289} __attribute__ ((__packed__));
290
291/*
292 * Meaning of FW_STREAM_CONTROL::Mode bits:
293 * Bit 7: Loopback PEXin to PEXout using TVOut channel
294 * Bit 6: AVLOOP
295 * Bit 5: Audio select; 0=I2S, 1=SPDIF
296 * Bit 4: AVSYNC
297 * Bit 3: Enable transport stream
298 * Bit 2: Enable audio capture
299 * Bit 1: Enable ITU-Video VBI capture
300 * Bit 0: Enable ITU-Video capture
301 *
302 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
303 * Bit 7: continuous capture
304 * Bit 6: capture one field
305 * Bit 5: capture one frame
306 * Bit 4: unused
307 * Bit 3: starting field; 0=odd, 1=even
308 * Bit 2: sample size; 0=8-bit, 1=10-bit
309 * Bit 1: data format; 0=UYVY, 1=YUY2
310 * Bit 0: resets buffer pointers
311*/
312
313enum FSC_MODE_BITS {
314 SMODE_LOOPBACK = 0x80,
315 SMODE_AVLOOP = 0x40,
316 _SMODE_AUDIO_SPDIF = 0x20,
317 _SMODE_AVSYNC = 0x10,
318 _SMODE_TRANSPORT_STREAM = 0x08,
319 _SMODE_AUDIO_CAPTURE = 0x04,
320 _SMODE_VBI_CAPTURE = 0x02,
321 _SMODE_VIDEO_CAPTURE = 0x01
322};
323
324
325/* Meaning of FW_STREAM_CONTROL::Stream bits:
326 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
327 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
328 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
329 */
330
331struct FW_STREAM_CONTROL {
332 struct FW_HEADER hdr;
333 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
334 u8 Control; /* Value written to UVI1_CTL */
335 u8 Mode; /* Controls clock source */
336 u8 SetupDataLen; /* Length of setup data, MSB=1 write
337 backwards */
338 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
339 for TS and Audio */
340 u64 Buffer_Address; /* Address of first buffer header */
341 u16 BytesPerVideoLine;
342 u16 MaxLinesPerField;
343 u16 MinLinesPerField;
344 u16 Reserved_1;
345 u16 BytesPerVBILine;
346 u16 MaxVBILinesPerField;
347 u16 MinVBILinesPerField;
348 u16 SetupDataAddr; /* ngene relative address of setup data */
349 u8 SetupData[32]; /* setup data */
350} __attribute__((__packed__));
351
352#define AUDIO_BLOCK_SIZE 256
353#define TS_BLOCK_SIZE 256
354
355struct FW_MEM_READ {
356 struct FW_HEADER hdr;
357 u16 address;
358} __attribute__ ((__packed__));
359
360struct FW_MEM_WRITE {
361 struct FW_HEADER hdr;
362 u16 address;
363 u8 data;
364} __attribute__ ((__packed__));
365
366struct FW_SFR_IRAM_READ {
367 struct FW_HEADER hdr;
368 u8 address;
369} __attribute__ ((__packed__));
370
371struct FW_SFR_IRAM_WRITE {
372 struct FW_HEADER hdr;
373 u8 address;
374 u8 data;
375} __attribute__ ((__packed__));
376
377struct FW_SET_GPIO_PIN {
378 struct FW_HEADER hdr;
379 u8 select;
380} __attribute__ ((__packed__));
381
382struct FW_SET_GPIO_INT {
383 struct FW_HEADER hdr;
384 u8 select;
385} __attribute__ ((__packed__));
386
387struct FW_SET_DEBUGMODE {
388 struct FW_HEADER hdr;
389 u8 debug_flags;
390} __attribute__ ((__packed__));
391
392struct FW_CONFIGURE_BUFFERS {
393 struct FW_HEADER hdr;
394 u8 config;
395} __attribute__ ((__packed__));
396
397enum _BUFFER_CONFIGS {
398 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
399 BUFFER_CONFIG_4422 = 0,
400 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
401 BUFFER_CONFIG_3333 = 1,
402 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
403 BUFFER_CONFIG_8022 = 2,
404 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
405};
406
407struct FW_CONFIGURE_FREE_BUFFERS {
408 struct FW_HEADER hdr;
409 u8 UVI1_BufferLength;
410 u8 UVI2_BufferLength;
411 u8 TVO_BufferLength;
412 u8 AUD1_BufferLength;
413 u8 AUD2_BufferLength;
414 u8 TVA_BufferLength;
415} __attribute__ ((__packed__));
416
417struct FW_CONFIGURE_UART {
418 struct FW_HEADER hdr;
419 u8 UartControl;
420} __attribute__ ((__packed__));
421
422enum _UART_CONFIG {
423 _UART_BAUDRATE_19200 = 0,
424 _UART_BAUDRATE_9600 = 1,
425 _UART_BAUDRATE_4800 = 2,
426 _UART_BAUDRATE_2400 = 3,
427 _UART_RX_ENABLE = 0x40,
428 _UART_TX_ENABLE = 0x80,
429};
430
431struct FW_WRITE_UART {
432 struct FW_HEADER hdr;
433 u8 Data[252];
434} __attribute__ ((__packed__));
435
436
437struct ngene_command {
438 u32 in_len;
439 u32 out_len;
440 union {
441 u32 raw[64];
442 u8 raw8[256];
443 struct FW_HEADER hdr;
444 struct FW_I2C_WRITE I2CWrite;
445 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
446 struct FW_I2C_READ I2CRead;
447 struct FW_STREAM_CONTROL StreamControl;
448 struct FW_FWLOAD_PREPARE FWLoadPrepare;
449 struct FW_FWLOAD_FINISH FWLoadFinish;
450 struct FW_MEM_READ MemoryRead;
451 struct FW_MEM_WRITE MemoryWrite;
452 struct FW_SFR_IRAM_READ SfrIramRead;
453 struct FW_SFR_IRAM_WRITE SfrIramWrite;
454 struct FW_SPI_WRITE SPIWrite;
455 struct FW_SPI_READ SPIRead;
456 struct FW_SET_GPIO_PIN SetGpioPin;
457 struct FW_SET_GPIO_INT SetGpioInt;
458 struct FW_SET_DEBUGMODE SetDebugMode;
459 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
460 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
461 struct FW_CONFIGURE_UART ConfigureUart;
462 struct FW_WRITE_UART WriteUart;
463 } cmd;
464} __attribute__ ((__packed__));
465
466#define NGENE_INTERFACE_VERSION 0x103
467#define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
468#define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
469#define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
470#define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
471#define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
472 Max: (1920x1080i60) */
473
474#define OVERFLOW_BUFFER_SIZE (8192)
475
476#define RING_SIZE_VIDEO 4
477#define RING_SIZE_AUDIO 8
478#define RING_SIZE_TS 8
479
480#define NUM_SCATTER_GATHER_ENTRIES 8
481
482#define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
483 RING_SIZE_VIDEO * 2) + \
484 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
485 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
486 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
487 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
488 (RING_SIZE_TS * PAGE_SIZE * 4) + \
489 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
490
491#define EVENT_QUEUE_SIZE 16
492
dae52d00
MB		 493/* Gathers the current state of a single channel. */
494
495struct SBufferHeader {
496 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
497 struct SBufferHeader *Next;
498 void *Buffer1;
684688d8 499 struct HW_SCATTER_GATHER_ELEMENT *scList1;
dae52d00 500 void *Buffer2;
684688d8 501 struct HW_SCATTER_GATHER_ELEMENT *scList2;
dae52d00
MB		 502};
503
504/* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
505#define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
506
507enum HWSTATE {
508 HWSTATE_STOP,
509 HWSTATE_STARTUP,
510 HWSTATE_RUN,
511 HWSTATE_PAUSE,
512};
513
514enum KSSTATE {
515 KSSTATE_STOP,
516 KSSTATE_ACQUIRE,
517 KSSTATE_PAUSE,
518 KSSTATE_RUN,
519};
520
521struct SRingBufferDescriptor {
522 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
523 structure*/
524 u64 PAHead; /* Physical address of first buffer */
525 u32 MemSize; /* Memory size of allocated ring buffers
526 (needed for freeing) */
527 u32 NumBuffers; /* Number of buffers in the ring */
528 u32 Buffer1Length; /* Allocated length of Buffer 1 */
529 u32 Buffer2Length; /* Allocated length of Buffer 2 */
530 void *SCListMem; /* Memory to hold scatter gather lists for this
531 ring */
532 u64 PASCListMem; /* Physical address .. */
533 u32 SCListMemSize; /* Size of this memory */
534};
535
536enum STREAMMODEFLAGS {
537 StreamMode_NONE = 0, /* Stream not used */
538 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
539 StreamMode_TSIN = 2, /* Transport stream input (all) */
540 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
541 (only stream 0) */
542 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
543};
544
545
546enum BufferExchangeFlags {
547 BEF_EVEN_FIELD = 0x00000001,
548 BEF_CONTINUATION = 0x00000002,
549 BEF_MORE_DATA = 0x00000004,
550 BEF_OVERFLOW = 0x00000008,
551 DF_SWAP32 = 0x00010000,
552};
553
554typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
555
684688d8 556struct MICI_STREAMINFO {
dae52d00
MB		 557 IBufferExchange *pExchange;
558 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
559 u8 Stream;
560 u8 Flags;
561 u8 Mode;
562 u8 Reserved;
563 u16 nLinesVideo;
564 u16 nBytesPerLineVideo;
565 u16 nLinesVBI;
566 u16 nBytesPerLineVBI;
567 u32 CaptureLength; /* Used for audio and transport stream */
684688d8 568};
dae52d00
MB		 569
570/****************************************************************************/
571/* STRUCTS ******************************************************************/
572/****************************************************************************/
573
574/* sound hardware definition */
575#define MIXER_ADDR_TVTUNER 0
576#define MIXER_ADDR_LAST 0
577
578struct ngene_channel;
579
580/*struct sound chip*/
581
582struct mychip {
583 struct ngene_channel *chan;
584 struct snd_card *card;
585 struct pci_dev *pci;
586 struct snd_pcm_substream *substream;
587 struct snd_pcm *pcm;
588 unsigned long port;
589 int irq;
590 spinlock_t mixer_lock;
591 spinlock_t lock;
592 int mixer_volume[MIXER_ADDR_LAST + 1][2];
593 int capture_source[MIXER_ADDR_LAST + 1][2];
594};
595
596#ifdef NGENE_V4L
597struct ngene_overlay {
598 int tvnorm;
599 struct v4l2_rect w;
600 enum v4l2_field field;
601 struct v4l2_clip *clips;
602 int nclips;
603 int setup_ok;
604};
605
606struct ngene_tvnorm {
607 int v4l2_id;
608 char *name;
609 u16 swidth, sheight; /* scaled standard width, height */
610 int tuner_norm;
611 int soundstd;
612};
613
614struct ngene_vopen {
615 struct ngene_channel *ch;
616 enum v4l2_priority prio;
617 int width;
618 int height;
619 int depth;
620 struct videobuf_queue vbuf_q;
621 struct videobuf_queue vbi;
622 int fourcc;
623 int picxcount;
624 int resources;
625 enum v4l2_buf_type type;
626 const struct ngene_format *fmt;
627
628 const struct ngene_format *ovfmt;
629 struct ngene_overlay ov;
630};
631#endif
632
633struct ngene_channel {
634 struct device device;
635 struct i2c_adapter i2c_adapter;
636
637 struct ngene *dev;
638 int number;
639 int type;
640 int mode;
641
642 struct dvb_frontend *fe;
643 struct dmxdev dmxdev;
644 struct dvb_demux demux;
645 struct dmx_frontend hw_frontend;
646 struct dmx_frontend mem_frontend;
647 int users;
648 struct video_device *v4l_dev;
0f0b270f 649 struct dvb_device *ci_dev;
dae52d00
MB		 650 struct tasklet_struct demux_tasklet;
651
652 struct SBufferHeader *nextBuffer;
653 enum KSSTATE State;
654 enum HWSTATE HWState;
655 u8 Stream;
656 u8 Flags;
657 u8 Mode;
658 IBufferExchange *pBufferExchange;
659 IBufferExchange *pBufferExchange2;
660
661 spinlock_t state_lock;
662 u16 nLines;
663 u16 nBytesPerLine;
664 u16 nVBILines;
665 u16 nBytesPerVBILine;
666 u16 itumode;
667 u32 Capture1Length;
668 u32 Capture2Length;
669 struct SRingBufferDescriptor RingBuffer;
670 struct SRingBufferDescriptor TSRingBuffer;
671 struct SRingBufferDescriptor TSIdleBuffer;
672
673 u32 DataFormatFlags;
674
675 int AudioDTOUpdated;
676 u32 AudioDTOValue;
677
678 int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
679 u8 lnbh;
680
681 /* stuff from analog driver */
682
683 int minor;
684 struct mychip *mychip;
685 struct snd_card *soundcard;
686 u8 *evenbuffer;
dae52d00
MB		 687 u8 dma_on;
688 int soundstreamon;
689 int audiomute;
690 int soundbuffisallocated;
691 int sndbuffflag;
692 int tun_rdy;
693 int dec_rdy;
694 int tun_dec_rdy;
695 int lastbufferflag;
696
697 struct ngene_tvnorm *tvnorms;
698 int tvnorm_num;
699 int tvnorm;
700
701#ifdef NGENE_V4L
702 int videousers;
703 struct v4l2_prio_state prio;
704 struct ngene_vopen init;
705 int resources;
706 struct v4l2_framebuffer fbuf;
707 struct ngene_buffer *screen; /* overlay */
708 struct list_head capture; /* video capture queue */
709 spinlock_t s_lock;
710 struct semaphore reslock;
711#endif
712
713 int running;
714};
715
0f0b270f
RM		 716
717struct ngene_ci {
718 struct device device;
719 struct i2c_adapter i2c_adapter;
720
721 struct ngene *dev;
722 struct dvb_ca_en50221 *en;
723};
724
dae52d00
MB		 725struct ngene;
726
727typedef void (rx_cb_t)(struct ngene *, u32, u8);
728typedef void (tx_cb_t)(struct ngene *, u32);
729
730struct ngene {
731 int nr;
732 struct pci_dev *pci_dev;
733 unsigned char *iomem;
734
dae52d00
MB		 735 /*struct i2c_adapter i2c_adapter;*/
736
737 u32 device_version;
738 u32 fw_interface_version;
739 u32 icounts;
43874181 740 bool msi_enabled;
5a2a1848 741 bool cmd_timeout_workaround;
dae52d00
MB		 742
743 u8 *CmdDoneByte;
744 int BootFirmware;
745 void *OverflowBuffer;
746 dma_addr_t PAOverflowBuffer;
747 void *FWInterfaceBuffer;
748 dma_addr_t PAFWInterfaceBuffer;
749 u8 *ngenetohost;
750 u8 *hosttongene;
751
752 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
753 int EventQueueOverflowCount;
754 int EventQueueOverflowFlag;
755 struct tasklet_struct event_tasklet;
756 struct EVENT_BUFFER *EventBuffer;
757 int EventQueueWriteIndex;
758 int EventQueueReadIndex;
759
760 wait_queue_head_t cmd_wq;
761 int cmd_done;
762 struct semaphore cmd_mutex;
763 struct semaphore stream_mutex;
764 struct semaphore pll_mutex;
765 struct semaphore i2c_switch_mutex;
766 int i2c_current_channel;
767 int i2c_current_bus;
768 spinlock_t cmd_lock;
769
cf1b12f2 770 struct dvb_adapter adapter[MAX_STREAM];
fdafc96c 771 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
dae52d00
MB		 772 struct ngene_channel channel[MAX_STREAM];
773
774 struct ngene_info *card_info;
775
776 tx_cb_t *TxEventNotify;
777 rx_cb_t *RxEventNotify;
778 int tx_busy;
779 wait_queue_head_t tx_wq;
780 wait_queue_head_t rx_wq;
781#define UART_RBUF_LEN 4096
782 u8 uart_rbuf[UART_RBUF_LEN];
783 int uart_rp, uart_wp;
784
785 u8 *tsout_buf;
786#define TSOUT_BUF_SIZE (512*188*8)
787 struct dvb_ringbuffer tsout_rbuf;
788
0f0b270f
RM		 789 u8 *tsin_buf;
790#define TSIN_BUF_SIZE (512*188*8)
791 struct dvb_ringbuffer tsin_rbuf;
792
dae52d00
MB		 793 u8 *ain_buf;
794#define AIN_BUF_SIZE (128*1024)
795 struct dvb_ringbuffer ain_rbuf;
796
797
798 u8 *vin_buf;
799#define VIN_BUF_SIZE (4*1920*1080)
800 struct dvb_ringbuffer vin_rbuf;
801
802 unsigned long exp_val;
803 int prev_cmd;
0f0b270f
RM		 804
805 struct ngene_ci ci;
dae52d00
MB		 806};
807
dae52d00
MB		 808struct ngene_info {
809 int type;
810#define NGENE_APP 0
811#define NGENE_TERRATEC 1
812#define NGENE_SIDEWINDER 2
813#define NGENE_RACER 3
814#define NGENE_VIPER 4
815#define NGENE_PYTHON 5
816#define NGENE_VBOX_V1 6
817#define NGENE_VBOX_V2 7
818
819 int fw_version;
43874181 820 bool msi_supported;
dae52d00
MB		 821 char *name;
822
823 int io_type[MAX_STREAM];
824#define NGENE_IO_NONE 0
825#define NGENE_IO_TV 1
826#define NGENE_IO_HDTV 2
827#define NGENE_IO_TSIN 4
828#define NGENE_IO_TSOUT 8
829#define NGENE_IO_AIN 16
830
831 void *fe_config[4];
832 void *tuner_config[4];
833
834 int (*demod_attach[4])(struct ngene_channel *);
835 int (*tuner_attach[4])(struct ngene_channel *);
836
837 u8 avf[4];
838 u8 msp[4];
839 u8 demoda[4];
840 u8 lnb[4];
841 int i2c_access;
842 u8 ntsc;
dae52d00
MB		 843 u8 tsf[4];
844 u8 i2s[4];
845
846 int (*gate_ctrl)(struct dvb_frontend *, int);
847 int (*switch_ctrl)(struct ngene_channel *, int, int);
848};
849
850#ifdef NGENE_V4L
851struct ngene_format{
852 char *name;
853 int fourcc; /* video4linux 2 */
854 int btformat; /* BT848_COLOR_FMT_* */
855 int format;
856 int btswap; /* BT848_COLOR_CTL_* */
857 int depth; /* bit/pixel */
858 int flags;
859 int hshift, vshift; /* for planar modes */
860 int palette;
861};
862
863#define RESOURCE_OVERLAY 1
864#define RESOURCE_VIDEO 2
865#define RESOURCE_VBI 4
866
867struct ngene_buffer {
868 /* common v4l buffer stuff -- must be first */
869 struct videobuf_buffer vb;
870
871 /* ngene specific */
872 const struct ngene_format *fmt;
873 int tvnorm;
874 int btformat;
875 int btswap;
876};
877#endif
878
dae52d00 879
cb1c0f8e 880/* Provided by ngene-core.c */
cbddcba6
DH		 881int __devinit ngene_probe(struct pci_dev *pci_dev,
882 const struct pci_device_id *id);
883void __devexit ngene_remove(struct pci_dev *pdev);
cb1c0f8e
DH		 884int ngene_command(struct ngene *dev, struct ngene_command *com);
885int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
1899e97c
DH		 886void set_transfer(struct ngene_channel *chan, int state);
887void FillTSBuffer(void *Buffer, int Length, u32 Flags);
cb1c0f8e
DH		 888
889/* Provided by ngene-i2c.c */
890int ngene_i2c_init(struct ngene *dev, int dev_nr);
891
1899e97c 892/* Provided by ngene-dvb.c */
0f0b270f 893extern struct dvb_device ngene_dvbdev_ci;
1899e97c
DH		 894void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
895void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
896int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
897int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
898int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
899 int (*start_feed)(struct dvb_demux_feed *),
900 int (*stop_feed)(struct dvb_demux_feed *),
901 void *priv);
902int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
903 struct dvb_demux *dvbdemux,
904 struct dmx_frontend *hw_frontend,
905 struct dmx_frontend *mem_frontend,
906 struct dvb_adapter *dvb_adapter);
907
dae52d00
MB		 908#endif
909
910/* LocalWords: Endif
911 */
Ubuntu Artful kernel mirror