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c7cadb3a
AO		 1/*
2 * pluto2.c - Satelco Easywatch Mobile Terrestrial Receiver [DVB-T]
3 *
4 * Copyright (C) 2005 Andreas Oberritter <obi@linuxtv.org>
5 *
6 * based on pluto2.c 1.10 - http://instinct-wp8.no-ip.org/pluto/
7 * by Dany Salman <salmandany@yahoo.fr>
8 * Copyright (c) 2004 TDF
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26#include <linux/i2c.h>
27#include <linux/i2c-algo-bit.h>
28#include <linux/init.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33
34#include "demux.h"
35#include "dmxdev.h"
36#include "dvb_demux.h"
37#include "dvb_frontend.h"
38#include "dvb_net.h"
39#include "dvbdev.h"
40#include "tda1004x.h"
41
78e92006
JG		 42DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
43
c7cadb3a
AO		 44#define DRIVER_NAME "pluto2"
45
46#define REG_PIDn(n) ((n) << 2) /* PID n pattern registers */
47#define REG_PCAR 0x0020 /* PC address register */
48#define REG_TSCR 0x0024 /* TS ctrl & status */
49#define REG_MISC 0x0028 /* miscellaneous */
50#define REG_MMAC 0x002c /* MSB MAC address */
51#define REG_IMAC 0x0030 /* ISB MAC address */
52#define REG_LMAC 0x0034 /* LSB MAC address */
53#define REG_SPID 0x0038 /* SPI data */
54#define REG_SLCS 0x003c /* serial links ctrl/status */
55
56#define PID0_NOFIL (0x0001 << 16)
57#define PIDn_ENP (0x0001 << 15)
58#define PID0_END (0x0001 << 14)
59#define PID0_AFIL (0x0001 << 13)
60#define PIDn_PID (0x1fff << 0)
61
62#define TSCR_NBPACKETS (0x00ff << 24)
63#define TSCR_DEM (0x0001 << 17)
64#define TSCR_DE (0x0001 << 16)
65#define TSCR_RSTN (0x0001 << 15)
66#define TSCR_MSKO (0x0001 << 14)
67#define TSCR_MSKA (0x0001 << 13)
68#define TSCR_MSKL (0x0001 << 12)
69#define TSCR_OVR (0x0001 << 11)
70#define TSCR_AFUL (0x0001 << 10)
71#define TSCR_LOCK (0x0001 << 9)
72#define TSCR_IACK (0x0001 << 8)
73#define TSCR_ADEF (0x007f << 0)
74
75#define MISC_DVR (0x0fff << 4)
76#define MISC_ALED (0x0001 << 3)
77#define MISC_FRST (0x0001 << 2)
78#define MISC_LED1 (0x0001 << 1)
79#define MISC_LED0 (0x0001 << 0)
80
81#define SPID_SPIDR (0x00ff << 0)
82
83#define SLCS_SCL (0x0001 << 7)
84#define SLCS_SDA (0x0001 << 6)
85#define SLCS_CSN (0x0001 << 2)
86#define SLCS_OVR (0x0001 << 1)
87#define SLCS_SWC (0x0001 << 0)
88
89#define TS_DMA_PACKETS (8)
90#define TS_DMA_BYTES (188 * TS_DMA_PACKETS)
91
92#define I2C_ADDR_TDA10046 0x10
93#define I2C_ADDR_TUA6034 0xc2
94#define NHWFILTERS 8
95
96struct pluto {
97 /* pci */
98 struct pci_dev *pdev;
99 u8 __iomem *io_mem;
100
101 /* dvb */
102 struct dmx_frontend hw_frontend;
103 struct dmx_frontend mem_frontend;
104 struct dmxdev dmxdev;
105 struct dvb_adapter dvb_adapter;
106 struct dvb_demux demux;
107 struct dvb_frontend *fe;
108 struct dvb_net dvbnet;
109 unsigned int full_ts_users;
110 unsigned int users;
111
112 /* i2c */
113 struct i2c_algo_bit_data i2c_bit;
114 struct i2c_adapter i2c_adap;
115 unsigned int i2cbug;
116
117 /* irq */
118 unsigned int overflow;
119
120 /* dma */
121 dma_addr_t dma_addr;
122 u8 dma_buf[TS_DMA_BYTES];
123 u8 dummy[4096];
124};
125
126static inline struct pluto *feed_to_pluto(struct dvb_demux_feed *feed)
127{
128 return container_of(feed->demux, struct pluto, demux);
129}
130
131static inline struct pluto *frontend_to_pluto(struct dvb_frontend *fe)
132{
133 return container_of(fe->dvb, struct pluto, dvb_adapter);
134}
135
136static inline u32 pluto_readreg(struct pluto *pluto, u32 reg)
137{
138 return readl(&pluto->io_mem[reg]);
139}
140
141static inline void pluto_writereg(struct pluto *pluto, u32 reg, u32 val)
142{
143 writel(val, &pluto->io_mem[reg]);
144}
145
146static inline void pluto_rw(struct pluto *pluto, u32 reg, u32 mask, u32 bits)
147{
148 u32 val = readl(&pluto->io_mem[reg]);
149 val &= ~mask;
150 val |= bits;
151 writel(val, &pluto->io_mem[reg]);
152}
153
1489f90a
AO		 154static void pluto_write_tscr(struct pluto *pluto, u32 val)
155{
156 /* set the number of packets */
157 val &= ~TSCR_ADEF;
158 val |= TS_DMA_PACKETS / 2;
159
160 pluto_writereg(pluto, REG_TSCR, val);
161}
162
c7cadb3a
AO		 163static void pluto_setsda(void *data, int state)
164{
165 struct pluto *pluto = data;
166
167 if (state)
168 pluto_rw(pluto, REG_SLCS, SLCS_SDA, SLCS_SDA);
169 else
170 pluto_rw(pluto, REG_SLCS, SLCS_SDA, 0);
171}
172
173static void pluto_setscl(void *data, int state)
174{
175 struct pluto *pluto = data;
176
177 if (state)
178 pluto_rw(pluto, REG_SLCS, SLCS_SCL, SLCS_SCL);
179 else
180 pluto_rw(pluto, REG_SLCS, SLCS_SCL, 0);
181
182 /* try to detect i2c_inb() to workaround hardware bug:
183 * reset SDA to high after SCL has been set to low */
184 if ((state) && (pluto->i2cbug == 0)) {
185 pluto->i2cbug = 1;
186 } else {
187 if ((!state) && (pluto->i2cbug == 1))
188 pluto_setsda(pluto, 1);
189 pluto->i2cbug = 0;
190 }
191}
192
193static int pluto_getsda(void *data)
194{
195 struct pluto *pluto = data;
196
197 return pluto_readreg(pluto, REG_SLCS) & SLCS_SDA;
198}
199
200static int pluto_getscl(void *data)
201{
202 struct pluto *pluto = data;
203
204 return pluto_readreg(pluto, REG_SLCS) & SLCS_SCL;
205}
206
207static void pluto_reset_frontend(struct pluto *pluto, int reenable)
208{
209 u32 val = pluto_readreg(pluto, REG_MISC);
210
211 if (val & MISC_FRST) {
212 val &= ~MISC_FRST;
213 pluto_writereg(pluto, REG_MISC, val);
214 }
215 if (reenable) {
216 val |= MISC_FRST;
217 pluto_writereg(pluto, REG_MISC, val);
218 }
219}
220
221static void pluto_reset_ts(struct pluto *pluto, int reenable)
222{
223 u32 val = pluto_readreg(pluto, REG_TSCR);
224
225 if (val & TSCR_RSTN) {
226 val &= ~TSCR_RSTN;
1489f90a 227 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 228 }
229 if (reenable) {
230 val |= TSCR_RSTN;
1489f90a 231 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 232 }
233}
234
235static void pluto_set_dma_addr(struct pluto *pluto)
236{
67778b32 237 pluto_writereg(pluto, REG_PCAR, pluto->dma_addr);
c7cadb3a
AO		 238}
239
240static int __devinit pluto_dma_map(struct pluto *pluto)
241{
242 pluto->dma_addr = pci_map_single(pluto->pdev, pluto->dma_buf,
243 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
244
8d8bb39b 245 return pci_dma_mapping_error(pluto->pdev, pluto->dma_addr);
c7cadb3a
AO		 246}
247
248static void pluto_dma_unmap(struct pluto *pluto)
249{
250 pci_unmap_single(pluto->pdev, pluto->dma_addr,
251 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
252}
253
254static int pluto_start_feed(struct dvb_demux_feed *f)
255{
256 struct pluto *pluto = feed_to_pluto(f);
257
258 /* enable PID filtering */
259 if (pluto->users++ == 0)
260 pluto_rw(pluto, REG_PIDn(0), PID0_AFIL | PID0_NOFIL, 0);
261
262 if ((f->pid < 0x2000) && (f->index < NHWFILTERS))
263 pluto_rw(pluto, REG_PIDn(f->index), PIDn_ENP | PIDn_PID, PIDn_ENP | f->pid);
264 else if (pluto->full_ts_users++ == 0)
265 pluto_rw(pluto, REG_PIDn(0), PID0_NOFIL, PID0_NOFIL);
266
267 return 0;
268}
269
270static int pluto_stop_feed(struct dvb_demux_feed *f)
271{
272 struct pluto *pluto = feed_to_pluto(f);
273
274 /* disable PID filtering */
275 if (--pluto->users == 0)
276 pluto_rw(pluto, REG_PIDn(0), PID0_AFIL, PID0_AFIL);
277
278 if ((f->pid < 0x2000) && (f->index < NHWFILTERS))
279 pluto_rw(pluto, REG_PIDn(f->index), PIDn_ENP | PIDn_PID, 0x1fff);
280 else if (--pluto->full_ts_users == 0)
281 pluto_rw(pluto, REG_PIDn(0), PID0_NOFIL, 0);
282
283 return 0;
284}
285
286static void pluto_dma_end(struct pluto *pluto, unsigned int nbpackets)
287{
288 /* synchronize the DMA transfer with the CPU
289 * first so that we see updated contents. */
290 pci_dma_sync_single_for_cpu(pluto->pdev, pluto->dma_addr,
291 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
292
293 /* Workaround for broken hardware:
294 * [1] On startup NBPACKETS seems to contain an uninitialized value,
295 * but no packets have been transfered.
296 * [2] Sometimes (actually very often) NBPACKETS stays at zero
297 * although one packet has been transfered.
4d845170 298 * [3] Sometimes (actually rarely), the card gets into an erroneous
299 * mode where it continuously generates interrupts, claiming it
300 * has recieved nbpackets>TS_DMA_PACKETS packets, but no packet
301 * has been transfered. Only a reset seems to solve this
c7cadb3a
AO		 302 */
303 if ((nbpackets == 0) || (nbpackets > TS_DMA_PACKETS)) {
6573dd75 304 unsigned int i = 0;
c7cadb3a
AO		 305 while (pluto->dma_buf[i] == 0x47)
306 i += 188;
6573dd75 307 nbpackets = i / 188;
4d845170 308 if (i == 0) {
309 pluto_reset_ts(pluto, 1);
310 dev_printk(KERN_DEBUG, &pluto->pdev->dev, "resetting TS because of invalid packet counter\n");
311 }
c7cadb3a
AO		 312 }
313
314 dvb_dmx_swfilter_packets(&pluto->demux, pluto->dma_buf, nbpackets);
315
316 /* clear the dma buffer. this is needed to be able to identify
317 * new valid ts packets above */
318 memset(pluto->dma_buf, 0, nbpackets * 188);
319
320 /* reset the dma address */
321 pluto_set_dma_addr(pluto);
322
323 /* sync the buffer and give it back to the card */
324 pci_dma_sync_single_for_device(pluto->pdev, pluto->dma_addr,
325 TS_DMA_BYTES, PCI_DMA_FROMDEVICE);
326}
327
7d12e780 328static irqreturn_t pluto_irq(int irq, void *dev_id)
c7cadb3a
AO		 329{
330 struct pluto *pluto = dev_id;
331 u32 tscr;
332
333 /* check whether an interrupt occured on this device */
334 tscr = pluto_readreg(pluto, REG_TSCR);
335 if (!(tscr & (TSCR_DE | TSCR_OVR)))
336 return IRQ_NONE;
337
338 if (tscr == 0xffffffff) {
339 // FIXME: maybe recover somehow
340 dev_err(&pluto->pdev->dev, "card hung up :(\n");
341 return IRQ_HANDLED;
342 }
343
344 /* dma end interrupt */
345 if (tscr & TSCR_DE) {
346 pluto_dma_end(pluto, (tscr & TSCR_NBPACKETS) >> 24);
347 /* overflow interrupt */
348 if (tscr & TSCR_OVR)
349 pluto->overflow++;
350 if (pluto->overflow) {
351 dev_err(&pluto->pdev->dev, "overflow irq (%d)\n",
352 pluto->overflow);
353 pluto_reset_ts(pluto, 1);
354 pluto->overflow = 0;
355 }
356 } else if (tscr & TSCR_OVR) {
357 pluto->overflow++;
358 }
359
360 /* ACK the interrupt */
1489f90a 361 pluto_write_tscr(pluto, tscr | TSCR_IACK);
c7cadb3a
AO		 362
363 return IRQ_HANDLED;
364}
365
366static void __devinit pluto_enable_irqs(struct pluto *pluto)
367{
368 u32 val = pluto_readreg(pluto, REG_TSCR);
369
c7cadb3a
AO		 370 /* disable AFUL and LOCK interrupts */
371 val |= (TSCR_MSKA | TSCR_MSKL);
372 /* enable DMA and OVERFLOW interrupts */
373 val &= ~(TSCR_DEM | TSCR_MSKO);
374 /* clear pending interrupts */
375 val |= TSCR_IACK;
376
1489f90a 377 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 378}
379
380static void pluto_disable_irqs(struct pluto *pluto)
381{
382 u32 val = pluto_readreg(pluto, REG_TSCR);
383
384 /* disable all interrupts */
385 val |= (TSCR_DEM | TSCR_MSKO | TSCR_MSKA | TSCR_MSKL);
386 /* clear pending interrupts */
387 val |= TSCR_IACK;
388
1489f90a 389 pluto_write_tscr(pluto, val);
c7cadb3a
AO		 390}
391
392static int __devinit pluto_hw_init(struct pluto *pluto)
393{
394 pluto_reset_frontend(pluto, 1);
395
396 /* set automatic LED control by FPGA */
397 pluto_rw(pluto, REG_MISC, MISC_ALED, MISC_ALED);
398
399 /* set data endianess */
400#ifdef __LITTLE_ENDIAN
401 pluto_rw(pluto, REG_PIDn(0), PID0_END, PID0_END);
402#else
403 pluto_rw(pluto, REG_PIDn(0), PID0_END, 0);
404#endif
405 /* map DMA and set address */
406 pluto_dma_map(pluto);
407 pluto_set_dma_addr(pluto);
408
409 /* enable interrupts */
410 pluto_enable_irqs(pluto);
411
412 /* reset TS logic */
413 pluto_reset_ts(pluto, 1);
414
415 return 0;
416}
417
418static void pluto_hw_exit(struct pluto *pluto)
419{
420 /* disable interrupts */
421 pluto_disable_irqs(pluto);
422
423 pluto_reset_ts(pluto, 0);
424
425 /* LED: disable automatic control, enable yellow, disable green */
426 pluto_rw(pluto, REG_MISC, MISC_ALED | MISC_LED1 | MISC_LED0, MISC_LED1);
427
428 /* unmap DMA */
429 pluto_dma_unmap(pluto);
430
431 pluto_reset_frontend(pluto, 0);
432}
433
434static inline u32 divide(u32 numerator, u32 denominator)
435{
436 if (denominator == 0)
437 return ~0;
438
439 return (numerator + denominator / 2) / denominator;
440}
441
442/* LG Innotek TDTE-E001P (Infineon TUA6034) */
4b4c9150
AQ		 443static int lg_tdtpe001p_tuner_set_params(struct dvb_frontend *fe,
444 struct dvb_frontend_parameters *p)
c7cadb3a
AO		 445{
446 struct pluto *pluto = frontend_to_pluto(fe);
447 struct i2c_msg msg;
448 int ret;
449 u8 buf[4];
450 u32 div;
451
452 // Fref = 166.667 Hz
453 // Fref * 3 = 500.000 Hz
454 // IF = 36166667
455 // IF / Fref = 217
456 //div = divide(p->frequency + 36166667, 166667);
457 div = divide(p->frequency * 3, 500000) + 217;
458 buf[0] = (div >> 8) & 0x7f;
459 buf[1] = (div >> 0) & 0xff;
460
461 if (p->frequency < 611000000)
462 buf[2] = 0xb4;
463 else if (p->frequency < 811000000)
464 buf[2] = 0xbc;
465 else
466 buf[2] = 0xf4;
467
468 // VHF: 174-230 MHz
469 // center: 350 MHz
470 // UHF: 470-862 MHz
471 if (p->frequency < 350000000)
472 buf[3] = 0x02;
473 else
474 buf[3] = 0x04;
475
476 if (p->u.ofdm.bandwidth == BANDWIDTH_8_MHZ)
477 buf[3] |= 0x08;
478
479 if (sizeof(buf) == 6) {
480 buf[4] = buf[2];
481 buf[4] &= ~0x1c;
482 buf[4] |= 0x18;
483
484 buf[5] = (0 << 7) | (2 << 4);
485 }
486
487 msg.addr = I2C_ADDR_TUA6034 >> 1;
488 msg.flags = 0;
489 msg.buf = buf;
490 msg.len = sizeof(buf);
491
dea74869
PB		 492 if (fe->ops.i2c_gate_ctrl)
493 fe->ops.i2c_gate_ctrl(fe, 1);
c7cadb3a
AO		 494 ret = i2c_transfer(&pluto->i2c_adap, &msg, 1);
495 if (ret < 0)
496 return ret;
497 else if (ret == 0)
498 return -EREMOTEIO;
499
500 return 0;
501}
502
503static int pluto2_request_firmware(struct dvb_frontend *fe,
504 const struct firmware **fw, char *name)
505{
506 struct pluto *pluto = frontend_to_pluto(fe);
507
508 return request_firmware(fw, name, &pluto->pdev->dev);
509}
510
511static struct tda1004x_config pluto2_fe_config __devinitdata = {
512 .demod_address = I2C_ADDR_TDA10046 >> 1,
513 .invert = 1,
514 .invert_oclk = 0,
515 .xtal_freq = TDA10046_XTAL_16M,
516 .agc_config = TDA10046_AGC_DEFAULT,
517 .if_freq = TDA10046_FREQ_3617,
c7cadb3a
AO		 518 .request_firmware = pluto2_request_firmware,
519};
520
521static int __devinit frontend_init(struct pluto *pluto)
522{
523 int ret;
524
525 pluto->fe = tda10046_attach(&pluto2_fe_config, &pluto->i2c_adap);
526 if (!pluto->fe) {
527 dev_err(&pluto->pdev->dev, "could not attach frontend\n");
528 return -ENODEV;
529 }
dea74869 530 pluto->fe->ops.tuner_ops.set_params = lg_tdtpe001p_tuner_set_params;
c7cadb3a
AO		 531
532 ret = dvb_register_frontend(&pluto->dvb_adapter, pluto->fe);
533 if (ret < 0) {
dea74869
PB		 534 if (pluto->fe->ops.release)
535 pluto->fe->ops.release(pluto->fe);
c7cadb3a
AO		 536 return ret;
537 }
538
539 return 0;
540}
541
542static void __devinit pluto_read_rev(struct pluto *pluto)
543{
544 u32 val = pluto_readreg(pluto, REG_MISC) & MISC_DVR;
545 dev_info(&pluto->pdev->dev, "board revision %d.%d\n",
546 (val >> 12) & 0x0f, (val >> 4) & 0xff);
547}
548
549static void __devinit pluto_read_mac(struct pluto *pluto, u8 *mac)
550{
551 u32 val = pluto_readreg(pluto, REG_MMAC);
552 mac[0] = (val >> 8) & 0xff;
553 mac[1] = (val >> 0) & 0xff;
554
555 val = pluto_readreg(pluto, REG_IMAC);
556 mac[2] = (val >> 8) & 0xff;
557 mac[3] = (val >> 0) & 0xff;
558
559 val = pluto_readreg(pluto, REG_LMAC);
560 mac[4] = (val >> 8) & 0xff;
561 mac[5] = (val >> 0) & 0xff;
562
563 dev_info(&pluto->pdev->dev, "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
564 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
565}
566
567static int __devinit pluto_read_serial(struct pluto *pluto)
568{
569 struct pci_dev *pdev = pluto->pdev;
570 unsigned int i, j;
571 u8 __iomem *cis;
572
573 cis = pci_iomap(pdev, 1, 0);
574 if (!cis)
575 return -EIO;
576
577 dev_info(&pdev->dev, "S/N ");
578
579 for (i = 0xe0; i < 0x100; i += 4) {
580 u32 val = readl(&cis[i]);
581 for (j = 0; j < 32; j += 8) {
582 if ((val & 0xff) == 0xff)
583 goto out;
584 printk("%c", val & 0xff);
585 val >>= 8;
586 }
587 }
588out:
589 printk("\n");
590 pci_iounmap(pdev, cis);
591
592 return 0;
593}
594
595static int __devinit pluto2_probe(struct pci_dev *pdev,
596 const struct pci_device_id *ent)
597{
598 struct pluto *pluto;
599 struct dvb_adapter *dvb_adapter;
600 struct dvb_demux *dvbdemux;
601 struct dmx_demux *dmx;
602 int ret = -ENOMEM;
603
7408187d 604 pluto = kzalloc(sizeof(struct pluto), GFP_KERNEL);
c7cadb3a
AO		 605 if (!pluto)
606 goto out;
607
c7cadb3a
AO		 608 pluto->pdev = pdev;
609
610 ret = pci_enable_device(pdev);
611 if (ret < 0)
612 goto err_kfree;
613
614 /* enable interrupts */
615 pci_write_config_dword(pdev, 0x6c, 0x8000);
616
617 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
618 if (ret < 0)
619 goto err_pci_disable_device;
620
621 pci_set_master(pdev);
622
623 ret = pci_request_regions(pdev, DRIVER_NAME);
624 if (ret < 0)
625 goto err_pci_disable_device;
626
627 pluto->io_mem = pci_iomap(pdev, 0, 0x40);
628 if (!pluto->io_mem) {
629 ret = -EIO;
630 goto err_pci_release_regions;
631 }
632
633 pci_set_drvdata(pdev, pluto);
634
8076fe32 635 ret = request_irq(pdev->irq, pluto_irq, IRQF_SHARED, DRIVER_NAME, pluto);
c7cadb3a
AO		 636 if (ret < 0)
637 goto err_pci_iounmap;
638
639 ret = pluto_hw_init(pluto);
640 if (ret < 0)
641 goto err_free_irq;
642
643 /* i2c */
644 i2c_set_adapdata(&pluto->i2c_adap, pluto);
645 strcpy(pluto->i2c_adap.name, DRIVER_NAME);
646 pluto->i2c_adap.owner = THIS_MODULE;
c7cadb3a
AO		 647 pluto->i2c_adap.class = I2C_CLASS_TV_DIGITAL;
648 pluto->i2c_adap.dev.parent = &pdev->dev;
649 pluto->i2c_adap.algo_data = &pluto->i2c_bit;
650 pluto->i2c_bit.data = pluto;
651 pluto->i2c_bit.setsda = pluto_setsda;
652 pluto->i2c_bit.setscl = pluto_setscl;
653 pluto->i2c_bit.getsda = pluto_getsda;
654 pluto->i2c_bit.getscl = pluto_getscl;
655 pluto->i2c_bit.udelay = 10;
656 pluto->i2c_bit.timeout = 10;
657
658 /* Raise SCL and SDA */
659 pluto_setsda(pluto, 1);
660 pluto_setscl(pluto, 1);
661
662 ret = i2c_bit_add_bus(&pluto->i2c_adap);
663 if (ret < 0)
664 goto err_pluto_hw_exit;
665
666 /* dvb */
78e92006
JG		 667 ret = dvb_register_adapter(&pluto->dvb_adapter, DRIVER_NAME,
668 THIS_MODULE, &pdev->dev, adapter_nr);
c7cadb3a 669 if (ret < 0)
3269711b 670 goto err_i2c_del_adapter;
c7cadb3a
AO		 671
672 dvb_adapter = &pluto->dvb_adapter;
673
674 pluto_read_rev(pluto);
675 pluto_read_serial(pluto);
676 pluto_read_mac(pluto, dvb_adapter->proposed_mac);
677
678 dvbdemux = &pluto->demux;
679 dvbdemux->filternum = 256;
680 dvbdemux->feednum = 256;
681 dvbdemux->start_feed = pluto_start_feed;
682 dvbdemux->stop_feed = pluto_stop_feed;
683 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
684 DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
685 ret = dvb_dmx_init(dvbdemux);
686 if (ret < 0)
687 goto err_dvb_unregister_adapter;
688
689 dmx = &dvbdemux->dmx;
690
691 pluto->hw_frontend.source = DMX_FRONTEND_0;
692 pluto->mem_frontend.source = DMX_MEMORY_FE;
693 pluto->dmxdev.filternum = NHWFILTERS;
694 pluto->dmxdev.demux = dmx;
695
696 ret = dvb_dmxdev_init(&pluto->dmxdev, dvb_adapter);
697 if (ret < 0)
698 goto err_dvb_dmx_release;
699
700 ret = dmx->add_frontend(dmx, &pluto->hw_frontend);
701 if (ret < 0)
702 goto err_dvb_dmxdev_release;
703
704 ret = dmx->add_frontend(dmx, &pluto->mem_frontend);
705 if (ret < 0)
706 goto err_remove_hw_frontend;
707
708 ret = dmx->connect_frontend(dmx, &pluto->hw_frontend);
709 if (ret < 0)
710 goto err_remove_mem_frontend;
711
712 ret = frontend_init(pluto);
713 if (ret < 0)
714 goto err_disconnect_frontend;
715
716 dvb_net_init(dvb_adapter, &pluto->dvbnet, dmx);
717out:
718 return ret;
719
720err_disconnect_frontend:
721 dmx->disconnect_frontend(dmx);
722err_remove_mem_frontend:
723 dmx->remove_frontend(dmx, &pluto->mem_frontend);
724err_remove_hw_frontend:
725 dmx->remove_frontend(dmx, &pluto->hw_frontend);
726err_dvb_dmxdev_release:
727 dvb_dmxdev_release(&pluto->dmxdev);
728err_dvb_dmx_release:
729 dvb_dmx_release(dvbdemux);
730err_dvb_unregister_adapter:
731 dvb_unregister_adapter(dvb_adapter);
3269711b
JD		 732err_i2c_del_adapter:
733 i2c_del_adapter(&pluto->i2c_adap);
c7cadb3a
AO		 734err_pluto_hw_exit:
735 pluto_hw_exit(pluto);
736err_free_irq:
737 free_irq(pdev->irq, pluto);
738err_pci_iounmap:
739 pci_iounmap(pdev, pluto->io_mem);
740err_pci_release_regions:
741 pci_release_regions(pdev);
742err_pci_disable_device:
743 pci_disable_device(pdev);
744err_kfree:
745 pci_set_drvdata(pdev, NULL);
746 kfree(pluto);
747 goto out;
748}
749
750static void __devexit pluto2_remove(struct pci_dev *pdev)
751{
752 struct pluto *pluto = pci_get_drvdata(pdev);
753 struct dvb_adapter *dvb_adapter = &pluto->dvb_adapter;
754 struct dvb_demux *dvbdemux = &pluto->demux;
755 struct dmx_demux *dmx = &dvbdemux->dmx;
756
757 dmx->close(dmx);
758 dvb_net_release(&pluto->dvbnet);
759 if (pluto->fe)
760 dvb_unregister_frontend(pluto->fe);
761
762 dmx->disconnect_frontend(dmx);
763 dmx->remove_frontend(dmx, &pluto->mem_frontend);
764 dmx->remove_frontend(dmx, &pluto->hw_frontend);
765 dvb_dmxdev_release(&pluto->dmxdev);
766 dvb_dmx_release(dvbdemux);
767 dvb_unregister_adapter(dvb_adapter);
3269711b 768 i2c_del_adapter(&pluto->i2c_adap);
c7cadb3a
AO		 769 pluto_hw_exit(pluto);
770 free_irq(pdev->irq, pluto);
771 pci_iounmap(pdev, pluto->io_mem);
772 pci_release_regions(pdev);
773 pci_disable_device(pdev);
774 pci_set_drvdata(pdev, NULL);
775 kfree(pluto);
776}
777
778#ifndef PCI_VENDOR_ID_SCM
779#define PCI_VENDOR_ID_SCM 0x0432
780#endif
781#ifndef PCI_DEVICE_ID_PLUTO2
782#define PCI_DEVICE_ID_PLUTO2 0x0001
783#endif
784
785static struct pci_device_id pluto2_id_table[] __devinitdata = {
786 {
787 .vendor = PCI_VENDOR_ID_SCM,
788 .device = PCI_DEVICE_ID_PLUTO2,
789 .subvendor = PCI_ANY_ID,
790 .subdevice = PCI_ANY_ID,
791 }, {
792 /* empty */
793 },
794};
795
796MODULE_DEVICE_TABLE(pci, pluto2_id_table);
797
798static struct pci_driver pluto2_driver = {
799 .name = DRIVER_NAME,
800 .id_table = pluto2_id_table,
801 .probe = pluto2_probe,
802 .remove = __devexit_p(pluto2_remove),
803};
804
805static int __init pluto2_init(void)
806{
807 return pci_register_driver(&pluto2_driver);
808}
809
810static void __exit pluto2_exit(void)
811{
812 pci_unregister_driver(&pluto2_driver);
813}
814
815module_init(pluto2_init);
816module_exit(pluto2_exit);
817
818MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
819MODULE_DESCRIPTION("Pluto2 driver");
820MODULE_LICENSE("GPL");
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