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Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
4b64bb26 AP |
2 | /* |
3 | * Afatech AF9033 demodulator driver | |
4 | * | |
5 | * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> | |
6 | * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> | |
4b64bb26 AP |
7 | */ |
8 | ||
9 | #include "af9033_priv.h" | |
10 | ||
09611caa | 11 | struct af9033_dev { |
f5b00a76 | 12 | struct i2c_client *client; |
bc85d5e2 | 13 | struct regmap *regmap; |
4b64bb26 AP |
14 | struct dvb_frontend fe; |
15 | struct af9033_config cfg; | |
83f11619 AP |
16 | bool is_af9035; |
17 | bool is_it9135; | |
4b64bb26 AP |
18 | |
19 | u32 bandwidth_hz; | |
20 | bool ts_mode_parallel; | |
21 | bool ts_mode_serial; | |
47eafa54 | 22 | |
0df289a2 | 23 | enum fe_status fe_status; |
e53c4744 | 24 | u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */ |
6bb096c9 AP |
25 | u64 post_bit_error; |
26 | u64 post_bit_count; | |
204f4319 AP |
27 | u64 error_block_count; |
28 | u64 total_block_count; | |
4b64bb26 AP |
29 | }; |
30 | ||
81e19912 | 31 | /* Write reg val table using reg addr auto increment */ |
09611caa | 32 | static int af9033_wr_reg_val_tab(struct af9033_dev *dev, |
81e19912 | 33 | const struct reg_val *tab, int tab_len) |
3bf5e552 | 34 | { |
81e19912 | 35 | struct i2c_client *client = dev->client; |
d18a88b1 | 36 | #define MAX_TAB_LEN 212 |
3bf5e552 | 37 | int ret, i, j; |
d18a88b1 AP |
38 | u8 buf[1 + MAX_TAB_LEN]; |
39 | ||
81e19912 | 40 | dev_dbg(&client->dev, "tab_len=%d\n", tab_len); |
37ebaf68 MCC |
41 | |
42 | if (tab_len > sizeof(buf)) { | |
81e19912 | 43 | dev_warn(&client->dev, "tab len %d is too big\n", tab_len); |
37ebaf68 MCC |
44 | return -EINVAL; |
45 | } | |
3bf5e552 | 46 | |
3bf5e552 AP |
47 | for (i = 0, j = 0; i < tab_len; i++) { |
48 | buf[j] = tab[i].val; | |
49 | ||
50 | if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { | |
bc85d5e2 AP |
51 | ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, |
52 | buf, j + 1); | |
53 | if (ret) | |
3bf5e552 AP |
54 | goto err; |
55 | ||
56 | j = 0; | |
57 | } else { | |
58 | j++; | |
59 | } | |
60 | } | |
61 | ||
62 | return 0; | |
3bf5e552 | 63 | err: |
81e19912 | 64 | dev_dbg(&client->dev, "failed=%d\n", ret); |
3bf5e552 AP |
65 | return ret; |
66 | } | |
67 | ||
4b64bb26 AP |
68 | static int af9033_init(struct dvb_frontend *fe) |
69 | { | |
09611caa | 70 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 71 | struct i2c_client *client = dev->client; |
2db4d179 | 72 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
4b64bb26 | 73 | int ret, i, len; |
c2feb9ff | 74 | unsigned int utmp; |
4b64bb26 AP |
75 | const struct reg_val *init; |
76 | u8 buf[4]; | |
4b64bb26 AP |
77 | struct reg_val_mask tab[] = { |
78 | { 0x80fb24, 0x00, 0x08 }, | |
79 | { 0x80004c, 0x00, 0xff }, | |
09611caa | 80 | { 0x00f641, dev->cfg.tuner, 0xff }, |
4b64bb26 AP |
81 | { 0x80f5ca, 0x01, 0x01 }, |
82 | { 0x80f715, 0x01, 0x01 }, | |
83 | { 0x00f41f, 0x04, 0x04 }, | |
84 | { 0x00f41a, 0x01, 0x01 }, | |
85 | { 0x80f731, 0x00, 0x01 }, | |
86 | { 0x00d91e, 0x00, 0x01 }, | |
87 | { 0x00d919, 0x00, 0x01 }, | |
88 | { 0x80f732, 0x00, 0x01 }, | |
89 | { 0x00d91f, 0x00, 0x01 }, | |
90 | { 0x00d91a, 0x00, 0x01 }, | |
91 | { 0x80f730, 0x00, 0x01 }, | |
92 | { 0x80f778, 0x00, 0xff }, | |
93 | { 0x80f73c, 0x01, 0x01 }, | |
94 | { 0x80f776, 0x00, 0x01 }, | |
95 | { 0x00d8fd, 0x01, 0xff }, | |
96 | { 0x00d830, 0x01, 0xff }, | |
97 | { 0x00d831, 0x00, 0xff }, | |
98 | { 0x00d832, 0x00, 0xff }, | |
09611caa AP |
99 | { 0x80f985, dev->ts_mode_serial, 0x01 }, |
100 | { 0x80f986, dev->ts_mode_parallel, 0x01 }, | |
4b64bb26 AP |
101 | { 0x00d827, 0x00, 0xff }, |
102 | { 0x00d829, 0x00, 0xff }, | |
09611caa | 103 | { 0x800045, dev->cfg.adc_multiplier, 0xff }, |
4b64bb26 AP |
104 | }; |
105 | ||
81e19912 AP |
106 | dev_dbg(&client->dev, "\n"); |
107 | ||
108 | /* Main clk control */ | |
c2feb9ff AP |
109 | utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000); |
110 | buf[0] = (utmp >> 0) & 0xff; | |
111 | buf[1] = (utmp >> 8) & 0xff; | |
112 | buf[2] = (utmp >> 16) & 0xff; | |
113 | buf[3] = (utmp >> 24) & 0xff; | |
bc85d5e2 AP |
114 | ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4); |
115 | if (ret) | |
4b64bb26 AP |
116 | goto err; |
117 | ||
81e19912 | 118 | dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp); |
c2feb9ff | 119 | |
81e19912 | 120 | /* ADC clk control */ |
4b64bb26 | 121 | for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { |
09611caa | 122 | if (clock_adc_lut[i].clock == dev->cfg.clock) |
4b64bb26 AP |
123 | break; |
124 | } | |
060f79d5 | 125 | if (i == ARRAY_SIZE(clock_adc_lut)) { |
81e19912 | 126 | dev_err(&client->dev, "Couldn't find ADC config for clock %d\n", |
060f79d5 | 127 | dev->cfg.clock); |
e121993a | 128 | ret = -ENODEV; |
060f79d5 MCC |
129 | goto err; |
130 | } | |
4b64bb26 | 131 | |
c2feb9ff AP |
132 | utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000); |
133 | buf[0] = (utmp >> 0) & 0xff; | |
134 | buf[1] = (utmp >> 8) & 0xff; | |
135 | buf[2] = (utmp >> 16) & 0xff; | |
bc85d5e2 AP |
136 | ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3); |
137 | if (ret) | |
4b64bb26 AP |
138 | goto err; |
139 | ||
81e19912 | 140 | dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n", |
c2feb9ff AP |
141 | clock_adc_lut[i].adc, utmp); |
142 | ||
81e19912 | 143 | /* Config register table */ |
4b64bb26 | 144 | for (i = 0; i < ARRAY_SIZE(tab); i++) { |
bc85d5e2 AP |
145 | ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask, |
146 | tab[i].val); | |
147 | if (ret) | |
4b64bb26 AP |
148 | goto err; |
149 | } | |
150 | ||
81e19912 | 151 | /* Demod clk output */ |
09611caa | 152 | if (dev->cfg.dyn0_clk) { |
bc85d5e2 AP |
153 | ret = regmap_write(dev->regmap, 0x80fba8, 0x00); |
154 | if (ret) | |
9dc0f3fe AP |
155 | goto err; |
156 | } | |
157 | ||
81e19912 | 158 | /* TS interface */ |
09611caa | 159 | if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) { |
bc85d5e2 AP |
160 | ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00); |
161 | if (ret) | |
4b64bb26 | 162 | goto err; |
bc85d5e2 AP |
163 | ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01); |
164 | if (ret) | |
4b64bb26 AP |
165 | goto err; |
166 | } else { | |
bc85d5e2 AP |
167 | ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00); |
168 | if (ret) | |
4b64bb26 | 169 | goto err; |
bc85d5e2 AP |
170 | ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00); |
171 | if (ret) | |
4b64bb26 AP |
172 | goto err; |
173 | } | |
174 | ||
81e19912 AP |
175 | /* Demod core settings */ |
176 | dev_dbg(&client->dev, "load ofsm settings\n"); | |
09611caa | 177 | switch (dev->cfg.tuner) { |
fe8eece1 AP |
178 | case AF9033_TUNER_IT9135_38: |
179 | case AF9033_TUNER_IT9135_51: | |
180 | case AF9033_TUNER_IT9135_52: | |
463c399c AP |
181 | len = ARRAY_SIZE(ofsm_init_it9135_v1); |
182 | init = ofsm_init_it9135_v1; | |
183 | break; | |
fe8eece1 AP |
184 | case AF9033_TUNER_IT9135_60: |
185 | case AF9033_TUNER_IT9135_61: | |
186 | case AF9033_TUNER_IT9135_62: | |
463c399c AP |
187 | len = ARRAY_SIZE(ofsm_init_it9135_v2); |
188 | init = ofsm_init_it9135_v2; | |
fe8eece1 AP |
189 | break; |
190 | default: | |
191 | len = ARRAY_SIZE(ofsm_init); | |
192 | init = ofsm_init; | |
193 | break; | |
194 | } | |
195 | ||
09611caa | 196 | ret = af9033_wr_reg_val_tab(dev, init, len); |
bc85d5e2 | 197 | if (ret) |
3bf5e552 | 198 | goto err; |
4b64bb26 | 199 | |
81e19912 AP |
200 | /* Demod tuner specific settings */ |
201 | dev_dbg(&client->dev, "load tuner specific settings\n"); | |
09611caa | 202 | switch (dev->cfg.tuner) { |
4b64bb26 AP |
203 | case AF9033_TUNER_TUA9001: |
204 | len = ARRAY_SIZE(tuner_init_tua9001); | |
205 | init = tuner_init_tua9001; | |
206 | break; | |
ffc501f6 MB |
207 | case AF9033_TUNER_FC0011: |
208 | len = ARRAY_SIZE(tuner_init_fc0011); | |
209 | init = tuner_init_fc0011; | |
210 | break; | |
540fd4ba HFV |
211 | case AF9033_TUNER_MXL5007T: |
212 | len = ARRAY_SIZE(tuner_init_mxl5007t); | |
213 | init = tuner_init_mxl5007t; | |
214 | break; | |
ce1fe379 GG |
215 | case AF9033_TUNER_TDA18218: |
216 | len = ARRAY_SIZE(tuner_init_tda18218); | |
217 | init = tuner_init_tda18218; | |
218 | break; | |
d67ceb33 OS |
219 | case AF9033_TUNER_FC2580: |
220 | len = ARRAY_SIZE(tuner_init_fc2580); | |
221 | init = tuner_init_fc2580; | |
222 | break; | |
e713ad15 AP |
223 | case AF9033_TUNER_FC0012: |
224 | len = ARRAY_SIZE(tuner_init_fc0012); | |
225 | init = tuner_init_fc0012; | |
226 | break; | |
4902bb39 | 227 | case AF9033_TUNER_IT9135_38: |
a72cbb77 AP |
228 | len = ARRAY_SIZE(tuner_init_it9135_38); |
229 | init = tuner_init_it9135_38; | |
230 | break; | |
4902bb39 | 231 | case AF9033_TUNER_IT9135_51: |
bb2e12a6 AP |
232 | len = ARRAY_SIZE(tuner_init_it9135_51); |
233 | init = tuner_init_it9135_51; | |
234 | break; | |
4902bb39 | 235 | case AF9033_TUNER_IT9135_52: |
22d729f3 AP |
236 | len = ARRAY_SIZE(tuner_init_it9135_52); |
237 | init = tuner_init_it9135_52; | |
238 | break; | |
4902bb39 | 239 | case AF9033_TUNER_IT9135_60: |
a49f53a0 AP |
240 | len = ARRAY_SIZE(tuner_init_it9135_60); |
241 | init = tuner_init_it9135_60; | |
242 | break; | |
4902bb39 | 243 | case AF9033_TUNER_IT9135_61: |
85211323 AP |
244 | len = ARRAY_SIZE(tuner_init_it9135_61); |
245 | init = tuner_init_it9135_61; | |
246 | break; | |
4902bb39 | 247 | case AF9033_TUNER_IT9135_62: |
dc4a2c40 AP |
248 | len = ARRAY_SIZE(tuner_init_it9135_62); |
249 | init = tuner_init_it9135_62; | |
4902bb39 | 250 | break; |
4b64bb26 | 251 | default: |
81e19912 AP |
252 | dev_dbg(&client->dev, "unsupported tuner ID=%d\n", |
253 | dev->cfg.tuner); | |
4b64bb26 AP |
254 | ret = -ENODEV; |
255 | goto err; | |
256 | } | |
257 | ||
09611caa | 258 | ret = af9033_wr_reg_val_tab(dev, init, len); |
bc85d5e2 | 259 | if (ret) |
3bf5e552 | 260 | goto err; |
4b64bb26 | 261 | |
09611caa | 262 | if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { |
bc85d5e2 AP |
263 | ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01); |
264 | if (ret) | |
9805992f | 265 | goto err; |
bc85d5e2 AP |
266 | ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00); |
267 | if (ret) | |
9805992f | 268 | goto err; |
bc85d5e2 AP |
269 | ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00); |
270 | if (ret) | |
9805992f JAR |
271 | goto err; |
272 | } | |
273 | ||
09611caa | 274 | switch (dev->cfg.tuner) { |
086991dd AP |
275 | case AF9033_TUNER_IT9135_60: |
276 | case AF9033_TUNER_IT9135_61: | |
277 | case AF9033_TUNER_IT9135_62: | |
bc85d5e2 AP |
278 | ret = regmap_write(dev->regmap, 0x800000, 0x01); |
279 | if (ret) | |
086991dd AP |
280 | goto err; |
281 | } | |
282 | ||
81e19912 AP |
283 | dev->bandwidth_hz = 0; /* Force to program all parameters */ |
284 | /* Init stats here in order signal app which stats are supported */ | |
2db4d179 AP |
285 | c->strength.len = 1; |
286 | c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
287 | c->cnr.len = 1; | |
288 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
289 | c->block_count.len = 1; | |
290 | c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
291 | c->block_error.len = 1; | |
292 | c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
293 | c->post_bit_count.len = 1; | |
294 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
295 | c->post_bit_error.len = 1; | |
296 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
4b64bb26 AP |
297 | |
298 | return 0; | |
4b64bb26 | 299 | err: |
81e19912 | 300 | dev_dbg(&client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
301 | return ret; |
302 | } | |
303 | ||
304 | static int af9033_sleep(struct dvb_frontend *fe) | |
305 | { | |
09611caa | 306 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 307 | struct i2c_client *client = dev->client; |
bc85d5e2 AP |
308 | int ret; |
309 | unsigned int utmp; | |
4b64bb26 | 310 | |
81e19912 AP |
311 | dev_dbg(&client->dev, "\n"); |
312 | ||
bc85d5e2 AP |
313 | ret = regmap_write(dev->regmap, 0x80004c, 0x01); |
314 | if (ret) | |
4b64bb26 | 315 | goto err; |
bc85d5e2 AP |
316 | ret = regmap_write(dev->regmap, 0x800000, 0x00); |
317 | if (ret) | |
4b64bb26 | 318 | goto err; |
bc85d5e2 AP |
319 | ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0, |
320 | 5000, 1000000); | |
321 | if (ret) | |
4b64bb26 | 322 | goto err; |
bc85d5e2 AP |
323 | ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08); |
324 | if (ret) | |
4b64bb26 AP |
325 | goto err; |
326 | ||
81e19912 | 327 | /* Prevent current leak by setting TS interface to parallel mode */ |
09611caa | 328 | if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) { |
81e19912 | 329 | /* Enable parallel TS */ |
bc85d5e2 AP |
330 | ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00); |
331 | if (ret) | |
4b64bb26 | 332 | goto err; |
bc85d5e2 AP |
333 | ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01); |
334 | if (ret) | |
4b64bb26 AP |
335 | goto err; |
336 | } | |
337 | ||
338 | return 0; | |
4b64bb26 | 339 | err: |
81e19912 | 340 | dev_dbg(&client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
341 | return ret; |
342 | } | |
343 | ||
344 | static int af9033_get_tune_settings(struct dvb_frontend *fe, | |
81e19912 | 345 | struct dvb_frontend_tune_settings *fesettings) |
4b64bb26 | 346 | { |
fe8eece1 AP |
347 | /* 800 => 2000 because IT9135 v2 is slow to gain lock */ |
348 | fesettings->min_delay_ms = 2000; | |
4b64bb26 AP |
349 | fesettings->step_size = 0; |
350 | fesettings->max_drift = 0; | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static int af9033_set_frontend(struct dvb_frontend *fe) | |
356 | { | |
09611caa | 357 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 358 | struct i2c_client *client = dev->client; |
4b64bb26 | 359 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
c2feb9ff AP |
360 | int ret, i; |
361 | unsigned int utmp, adc_freq; | |
4b64bb26 | 362 | u8 tmp, buf[3], bandwidth_reg_val; |
c2feb9ff | 363 | u32 if_frequency; |
4b64bb26 | 364 | |
81e19912 AP |
365 | dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n", |
366 | c->frequency, c->bandwidth_hz); | |
4b64bb26 | 367 | |
81e19912 | 368 | /* Check bandwidth */ |
4b64bb26 AP |
369 | switch (c->bandwidth_hz) { |
370 | case 6000000: | |
371 | bandwidth_reg_val = 0x00; | |
372 | break; | |
373 | case 7000000: | |
374 | bandwidth_reg_val = 0x01; | |
375 | break; | |
376 | case 8000000: | |
377 | bandwidth_reg_val = 0x02; | |
378 | break; | |
379 | default: | |
81e19912 | 380 | dev_dbg(&client->dev, "invalid bandwidth_hz\n"); |
4b64bb26 AP |
381 | ret = -EINVAL; |
382 | goto err; | |
383 | } | |
384 | ||
81e19912 | 385 | /* Program tuner */ |
4b64bb26 AP |
386 | if (fe->ops.tuner_ops.set_params) |
387 | fe->ops.tuner_ops.set_params(fe); | |
388 | ||
81e19912 | 389 | /* Coefficients */ |
09611caa | 390 | if (c->bandwidth_hz != dev->bandwidth_hz) { |
4b64bb26 | 391 | for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) { |
09611caa | 392 | if (coeff_lut[i].clock == dev->cfg.clock && |
81e19912 | 393 | coeff_lut[i].bandwidth_hz == c->bandwidth_hz) { |
4b64bb26 AP |
394 | break; |
395 | } | |
396 | } | |
060f79d5 | 397 | if (i == ARRAY_SIZE(coeff_lut)) { |
81e19912 AP |
398 | dev_err(&client->dev, |
399 | "Couldn't find config for clock %u\n", | |
060f79d5 MCC |
400 | dev->cfg.clock); |
401 | ret = -EINVAL; | |
402 | goto err; | |
403 | } | |
404 | ||
bc85d5e2 AP |
405 | ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val, |
406 | sizeof(coeff_lut[i].val)); | |
407 | if (ret) | |
408 | goto err; | |
4b64bb26 AP |
409 | } |
410 | ||
81e19912 | 411 | /* IF frequency control */ |
09611caa | 412 | if (c->bandwidth_hz != dev->bandwidth_hz) { |
540fd4ba | 413 | for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) { |
09611caa | 414 | if (clock_adc_lut[i].clock == dev->cfg.clock) |
540fd4ba HFV |
415 | break; |
416 | } | |
060f79d5 | 417 | if (i == ARRAY_SIZE(clock_adc_lut)) { |
81e19912 AP |
418 | dev_err(&client->dev, |
419 | "Couldn't find ADC clock for clock %u\n", | |
060f79d5 MCC |
420 | dev->cfg.clock); |
421 | ret = -EINVAL; | |
422 | goto err; | |
423 | } | |
540fd4ba HFV |
424 | adc_freq = clock_adc_lut[i].adc; |
425 | ||
c2feb9ff AP |
426 | if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X) |
427 | adc_freq = 2 * adc_freq; | |
428 | ||
81e19912 | 429 | /* Get used IF frequency */ |
4b64bb26 AP |
430 | if (fe->ops.tuner_ops.get_if_frequency) |
431 | fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency); | |
432 | else | |
433 | if_frequency = 0; | |
434 | ||
c2feb9ff AP |
435 | utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000, |
436 | adc_freq); | |
4b64bb26 | 437 | |
c2feb9ff AP |
438 | if (!dev->cfg.spec_inv && if_frequency) |
439 | utmp = 0x800000 - utmp; | |
fe8eece1 | 440 | |
c2feb9ff AP |
441 | buf[0] = (utmp >> 0) & 0xff; |
442 | buf[1] = (utmp >> 8) & 0xff; | |
443 | buf[2] = (utmp >> 16) & 0xff; | |
bc85d5e2 AP |
444 | ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3); |
445 | if (ret) | |
4b64bb26 AP |
446 | goto err; |
447 | ||
81e19912 | 448 | dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp); |
c2feb9ff | 449 | |
09611caa | 450 | dev->bandwidth_hz = c->bandwidth_hz; |
4b64bb26 AP |
451 | } |
452 | ||
bc85d5e2 AP |
453 | ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03, |
454 | bandwidth_reg_val); | |
455 | if (ret) | |
4b64bb26 | 456 | goto err; |
bc85d5e2 AP |
457 | ret = regmap_write(dev->regmap, 0x800040, 0x00); |
458 | if (ret) | |
4b64bb26 | 459 | goto err; |
bc85d5e2 AP |
460 | ret = regmap_write(dev->regmap, 0x800047, 0x00); |
461 | if (ret) | |
4b64bb26 | 462 | goto err; |
bc85d5e2 AP |
463 | ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00); |
464 | if (ret) | |
4b64bb26 AP |
465 | goto err; |
466 | ||
467 | if (c->frequency <= 230000000) | |
468 | tmp = 0x00; /* VHF */ | |
469 | else | |
470 | tmp = 0x01; /* UHF */ | |
471 | ||
bc85d5e2 AP |
472 | ret = regmap_write(dev->regmap, 0x80004b, tmp); |
473 | if (ret) | |
4b64bb26 | 474 | goto err; |
81e19912 | 475 | /* Reset FSM */ |
bc85d5e2 AP |
476 | ret = regmap_write(dev->regmap, 0x800000, 0x00); |
477 | if (ret) | |
4b64bb26 AP |
478 | goto err; |
479 | ||
480 | return 0; | |
4b64bb26 | 481 | err: |
81e19912 | 482 | dev_dbg(&client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
483 | return ret; |
484 | } | |
485 | ||
7e3e68bc MCC |
486 | static int af9033_get_frontend(struct dvb_frontend *fe, |
487 | struct dtv_frontend_properties *c) | |
0a4df239 | 488 | { |
09611caa | 489 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 490 | struct i2c_client *client = dev->client; |
0a4df239 GG |
491 | int ret; |
492 | u8 buf[8]; | |
493 | ||
81e19912 | 494 | dev_dbg(&client->dev, "\n"); |
0a4df239 | 495 | |
81e19912 | 496 | /* Read all needed TPS registers */ |
bc85d5e2 AP |
497 | ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8); |
498 | if (ret) | |
de7f14fc | 499 | goto err; |
0a4df239 GG |
500 | |
501 | switch ((buf[0] >> 0) & 3) { | |
502 | case 0: | |
de7f14fc | 503 | c->transmission_mode = TRANSMISSION_MODE_2K; |
0a4df239 GG |
504 | break; |
505 | case 1: | |
de7f14fc | 506 | c->transmission_mode = TRANSMISSION_MODE_8K; |
0a4df239 GG |
507 | break; |
508 | } | |
509 | ||
510 | switch ((buf[1] >> 0) & 3) { | |
511 | case 0: | |
de7f14fc | 512 | c->guard_interval = GUARD_INTERVAL_1_32; |
0a4df239 GG |
513 | break; |
514 | case 1: | |
de7f14fc | 515 | c->guard_interval = GUARD_INTERVAL_1_16; |
0a4df239 GG |
516 | break; |
517 | case 2: | |
de7f14fc | 518 | c->guard_interval = GUARD_INTERVAL_1_8; |
0a4df239 GG |
519 | break; |
520 | case 3: | |
de7f14fc | 521 | c->guard_interval = GUARD_INTERVAL_1_4; |
0a4df239 GG |
522 | break; |
523 | } | |
524 | ||
525 | switch ((buf[2] >> 0) & 7) { | |
526 | case 0: | |
de7f14fc | 527 | c->hierarchy = HIERARCHY_NONE; |
0a4df239 GG |
528 | break; |
529 | case 1: | |
de7f14fc | 530 | c->hierarchy = HIERARCHY_1; |
0a4df239 GG |
531 | break; |
532 | case 2: | |
de7f14fc | 533 | c->hierarchy = HIERARCHY_2; |
0a4df239 GG |
534 | break; |
535 | case 3: | |
de7f14fc | 536 | c->hierarchy = HIERARCHY_4; |
0a4df239 GG |
537 | break; |
538 | } | |
539 | ||
540 | switch ((buf[3] >> 0) & 3) { | |
541 | case 0: | |
de7f14fc | 542 | c->modulation = QPSK; |
0a4df239 GG |
543 | break; |
544 | case 1: | |
de7f14fc | 545 | c->modulation = QAM_16; |
0a4df239 GG |
546 | break; |
547 | case 2: | |
de7f14fc | 548 | c->modulation = QAM_64; |
0a4df239 GG |
549 | break; |
550 | } | |
551 | ||
552 | switch ((buf[4] >> 0) & 3) { | |
553 | case 0: | |
de7f14fc | 554 | c->bandwidth_hz = 6000000; |
0a4df239 GG |
555 | break; |
556 | case 1: | |
de7f14fc | 557 | c->bandwidth_hz = 7000000; |
0a4df239 GG |
558 | break; |
559 | case 2: | |
de7f14fc | 560 | c->bandwidth_hz = 8000000; |
0a4df239 GG |
561 | break; |
562 | } | |
563 | ||
564 | switch ((buf[6] >> 0) & 7) { | |
565 | case 0: | |
de7f14fc | 566 | c->code_rate_HP = FEC_1_2; |
0a4df239 GG |
567 | break; |
568 | case 1: | |
de7f14fc | 569 | c->code_rate_HP = FEC_2_3; |
0a4df239 GG |
570 | break; |
571 | case 2: | |
de7f14fc | 572 | c->code_rate_HP = FEC_3_4; |
0a4df239 GG |
573 | break; |
574 | case 3: | |
de7f14fc | 575 | c->code_rate_HP = FEC_5_6; |
0a4df239 GG |
576 | break; |
577 | case 4: | |
de7f14fc | 578 | c->code_rate_HP = FEC_7_8; |
0a4df239 GG |
579 | break; |
580 | case 5: | |
de7f14fc | 581 | c->code_rate_HP = FEC_NONE; |
0a4df239 GG |
582 | break; |
583 | } | |
584 | ||
585 | switch ((buf[7] >> 0) & 7) { | |
586 | case 0: | |
de7f14fc | 587 | c->code_rate_LP = FEC_1_2; |
0a4df239 GG |
588 | break; |
589 | case 1: | |
de7f14fc | 590 | c->code_rate_LP = FEC_2_3; |
0a4df239 GG |
591 | break; |
592 | case 2: | |
de7f14fc | 593 | c->code_rate_LP = FEC_3_4; |
0a4df239 GG |
594 | break; |
595 | case 3: | |
de7f14fc | 596 | c->code_rate_LP = FEC_5_6; |
0a4df239 GG |
597 | break; |
598 | case 4: | |
de7f14fc | 599 | c->code_rate_LP = FEC_7_8; |
0a4df239 GG |
600 | break; |
601 | case 5: | |
de7f14fc | 602 | c->code_rate_LP = FEC_NONE; |
0a4df239 GG |
603 | break; |
604 | } | |
605 | ||
de7f14fc | 606 | return 0; |
de7f14fc | 607 | err: |
81e19912 | 608 | dev_dbg(&client->dev, "failed=%d\n", ret); |
0a4df239 GG |
609 | return ret; |
610 | } | |
611 | ||
0df289a2 | 612 | static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status) |
4b64bb26 | 613 | { |
09611caa | 614 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 615 | struct i2c_client *client = dev->client; |
659a0999 | 616 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
239dd616 | 617 | int ret, tmp = 0; |
bc85d5e2 | 618 | u8 buf[7]; |
239dd616 | 619 | unsigned int utmp, utmp1; |
659a0999 | 620 | |
81e19912 | 621 | dev_dbg(&client->dev, "\n"); |
4b64bb26 AP |
622 | |
623 | *status = 0; | |
624 | ||
81e19912 | 625 | /* Radio channel status: 0=no result, 1=has signal, 2=no signal */ |
bc85d5e2 AP |
626 | ret = regmap_read(dev->regmap, 0x800047, &utmp); |
627 | if (ret) | |
4b64bb26 AP |
628 | goto err; |
629 | ||
81e19912 | 630 | /* Has signal */ |
bc85d5e2 | 631 | if (utmp == 0x01) |
4b64bb26 AP |
632 | *status |= FE_HAS_SIGNAL; |
633 | ||
bc85d5e2 | 634 | if (utmp != 0x02) { |
4b64bb26 | 635 | /* TPS lock */ |
bc85d5e2 AP |
636 | ret = regmap_read(dev->regmap, 0x80f5a9, &utmp); |
637 | if (ret) | |
4b64bb26 AP |
638 | goto err; |
639 | ||
bc85d5e2 | 640 | if ((utmp >> 0) & 0x01) |
4b64bb26 AP |
641 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | |
642 | FE_HAS_VITERBI; | |
643 | ||
81e19912 | 644 | /* Full lock */ |
bc85d5e2 AP |
645 | ret = regmap_read(dev->regmap, 0x80f999, &utmp); |
646 | if (ret) | |
4b64bb26 AP |
647 | goto err; |
648 | ||
bc85d5e2 | 649 | if ((utmp >> 0) & 0x01) |
4b64bb26 AP |
650 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | |
651 | FE_HAS_VITERBI | FE_HAS_SYNC | | |
652 | FE_HAS_LOCK; | |
653 | } | |
654 | ||
83f11619 AP |
655 | dev->fe_status = *status; |
656 | ||
81e19912 | 657 | /* Signal strength */ |
659a0999 AP |
658 | if (dev->fe_status & FE_HAS_SIGNAL) { |
659 | if (dev->is_af9035) { | |
bc85d5e2 | 660 | ret = regmap_read(dev->regmap, 0x80004a, &utmp); |
659a0999 AP |
661 | if (ret) |
662 | goto err; | |
bc85d5e2 | 663 | tmp = -utmp * 1000; |
659a0999 | 664 | } else { |
bc85d5e2 | 665 | ret = regmap_read(dev->regmap, 0x8000f7, &utmp); |
659a0999 AP |
666 | if (ret) |
667 | goto err; | |
bc85d5e2 | 668 | tmp = (utmp - 100) * 1000; |
659a0999 AP |
669 | } |
670 | ||
671 | c->strength.len = 1; | |
672 | c->strength.stat[0].scale = FE_SCALE_DECIBEL; | |
673 | c->strength.stat[0].svalue = tmp; | |
674 | } else { | |
675 | c->strength.len = 1; | |
676 | c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
677 | } | |
678 | ||
679 | /* CNR */ | |
680 | if (dev->fe_status & FE_HAS_VITERBI) { | |
81e19912 | 681 | /* Read raw SNR value */ |
bc85d5e2 | 682 | ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3); |
659a0999 AP |
683 | if (ret) |
684 | goto err; | |
685 | ||
239dd616 | 686 | utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0; |
659a0999 | 687 | |
81e19912 | 688 | /* Read superframe number */ |
bc85d5e2 | 689 | ret = regmap_read(dev->regmap, 0x80f78b, &utmp); |
659a0999 AP |
690 | if (ret) |
691 | goto err; | |
692 | ||
bc85d5e2 | 693 | if (utmp) |
239dd616 | 694 | utmp1 /= utmp; |
659a0999 | 695 | |
81e19912 | 696 | /* Read current transmission mode */ |
bc85d5e2 | 697 | ret = regmap_read(dev->regmap, 0x80f900, &utmp); |
659a0999 AP |
698 | if (ret) |
699 | goto err; | |
700 | ||
bc85d5e2 | 701 | switch ((utmp >> 0) & 3) { |
659a0999 | 702 | case 0: |
239dd616 AP |
703 | /* 2k */ |
704 | utmp1 *= 4; | |
659a0999 AP |
705 | break; |
706 | case 1: | |
239dd616 AP |
707 | /* 8k */ |
708 | utmp1 *= 1; | |
659a0999 AP |
709 | break; |
710 | case 2: | |
239dd616 AP |
711 | /* 4k */ |
712 | utmp1 *= 2; | |
659a0999 AP |
713 | break; |
714 | default: | |
239dd616 | 715 | utmp1 *= 0; |
659a0999 AP |
716 | break; |
717 | } | |
718 | ||
81e19912 | 719 | /* Read current modulation */ |
bc85d5e2 | 720 | ret = regmap_read(dev->regmap, 0x80f903, &utmp); |
659a0999 AP |
721 | if (ret) |
722 | goto err; | |
723 | ||
bc85d5e2 | 724 | switch ((utmp >> 0) & 3) { |
659a0999 | 725 | case 0: |
239dd616 AP |
726 | /* |
727 | * QPSK | |
728 | * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6 | |
729 | * value [653799, 1689999], 2.6 / 13 = 3355443 | |
730 | */ | |
731 | utmp1 = clamp(utmp1, 653799U, 1689999U); | |
732 | utmp1 = ((u64)(intlog10(utmp1) | |
733 | - intlog10(1690000 - utmp1) | |
734 | + 3355443) * 13 * 1000) >> 24; | |
659a0999 AP |
735 | break; |
736 | case 1: | |
239dd616 AP |
737 | /* |
738 | * QAM-16 | |
739 | * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7 | |
740 | * value [371105, 827999], 15.7 / 6 = 43900382 | |
741 | */ | |
742 | utmp1 = clamp(utmp1, 371105U, 827999U); | |
743 | utmp1 = ((u64)(intlog10(utmp1 - 370000) | |
744 | - intlog10(828000 - utmp1) | |
745 | + 43900382) * 6 * 1000) >> 24; | |
659a0999 AP |
746 | break; |
747 | case 2: | |
239dd616 AP |
748 | /* |
749 | * QAM-64 | |
750 | * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8 | |
751 | * value [193246, 424999], 23.8 / 8 = 49912218 | |
752 | */ | |
753 | utmp1 = clamp(utmp1, 193246U, 424999U); | |
754 | utmp1 = ((u64)(intlog10(utmp1 - 193000) | |
755 | - intlog10(425000 - utmp1) | |
756 | + 49912218) * 8 * 1000) >> 24; | |
659a0999 AP |
757 | break; |
758 | default: | |
239dd616 | 759 | utmp1 = 0; |
659a0999 AP |
760 | break; |
761 | } | |
762 | ||
239dd616 | 763 | dev_dbg(&client->dev, "cnr=%u\n", utmp1); |
659a0999 | 764 | |
659a0999 | 765 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; |
239dd616 | 766 | c->cnr.stat[0].svalue = utmp1; |
659a0999 | 767 | } else { |
659a0999 AP |
768 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
769 | } | |
770 | ||
771 | /* UCB/PER/BER */ | |
772 | if (dev->fe_status & FE_HAS_LOCK) { | |
81e19912 | 773 | /* Outer FEC, 204 byte packets */ |
659a0999 | 774 | u16 abort_packet_count, rsd_packet_count; |
81e19912 | 775 | /* Inner FEC, bits */ |
659a0999 AP |
776 | u32 rsd_bit_err_count; |
777 | ||
778 | /* | |
779 | * Packet count used for measurement is 10000 | |
780 | * (rsd_packet_count). Maybe it should be increased? | |
781 | */ | |
782 | ||
bc85d5e2 | 783 | ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7); |
659a0999 AP |
784 | if (ret) |
785 | goto err; | |
786 | ||
787 | abort_packet_count = (buf[1] << 8) | (buf[0] << 0); | |
788 | rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2]; | |
789 | rsd_packet_count = (buf[6] << 8) | (buf[5] << 0); | |
790 | ||
791 | dev->error_block_count += abort_packet_count; | |
792 | dev->total_block_count += rsd_packet_count; | |
793 | dev->post_bit_error += rsd_bit_err_count; | |
794 | dev->post_bit_count += rsd_packet_count * 204 * 8; | |
795 | ||
796 | c->block_count.len = 1; | |
797 | c->block_count.stat[0].scale = FE_SCALE_COUNTER; | |
798 | c->block_count.stat[0].uvalue = dev->total_block_count; | |
799 | ||
800 | c->block_error.len = 1; | |
801 | c->block_error.stat[0].scale = FE_SCALE_COUNTER; | |
802 | c->block_error.stat[0].uvalue = dev->error_block_count; | |
803 | ||
804 | c->post_bit_count.len = 1; | |
805 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
806 | c->post_bit_count.stat[0].uvalue = dev->post_bit_count; | |
807 | ||
808 | c->post_bit_error.len = 1; | |
809 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
810 | c->post_bit_error.stat[0].uvalue = dev->post_bit_error; | |
811 | } | |
812 | ||
4b64bb26 | 813 | return 0; |
4b64bb26 | 814 | err: |
81e19912 | 815 | dev_dbg(&client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
816 | return ret; |
817 | } | |
818 | ||
819 | static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) | |
820 | { | |
09611caa | 821 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 822 | struct i2c_client *client = dev->client; |
6b457786 | 823 | struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; |
6d03f6a8 | 824 | int ret; |
bc85d5e2 | 825 | unsigned int utmp; |
e898ef62 | 826 | |
81e19912 AP |
827 | dev_dbg(&client->dev, "\n"); |
828 | ||
829 | /* Use DVBv5 CNR */ | |
6d03f6a8 | 830 | if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) { |
c3a80cd0 AP |
831 | /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */ |
832 | if (dev->is_af9035) { | |
833 | /* 1000x => 10x (0.1 dB) */ | |
834 | *snr = div_s64(c->cnr.stat[0].svalue, 100); | |
835 | } else { | |
836 | /* 1000x => 1x (1 dB) */ | |
837 | *snr = div_s64(c->cnr.stat[0].svalue, 1000); | |
6d03f6a8 | 838 | |
81e19912 | 839 | /* Read current modulation */ |
bc85d5e2 | 840 | ret = regmap_read(dev->regmap, 0x80f903, &utmp); |
c3a80cd0 AP |
841 | if (ret) |
842 | goto err; | |
6d03f6a8 | 843 | |
c3a80cd0 | 844 | /* scale value to 0x0000-0xffff */ |
bc85d5e2 | 845 | switch ((utmp >> 0) & 3) { |
c3a80cd0 AP |
846 | case 0: |
847 | *snr = *snr * 0xffff / 23; | |
848 | break; | |
849 | case 1: | |
850 | *snr = *snr * 0xffff / 26; | |
851 | break; | |
852 | case 2: | |
853 | *snr = *snr * 0xffff / 32; | |
854 | break; | |
855 | default: | |
e121993a | 856 | ret = -EINVAL; |
c3a80cd0 AP |
857 | goto err; |
858 | } | |
6d03f6a8 BC |
859 | } |
860 | } else { | |
6b457786 | 861 | *snr = 0; |
6d03f6a8 | 862 | } |
4b64bb26 AP |
863 | |
864 | return 0; | |
6d03f6a8 | 865 | err: |
81e19912 | 866 | dev_dbg(&client->dev, "failed=%d\n", ret); |
6d03f6a8 | 867 | return ret; |
4b64bb26 AP |
868 | } |
869 | ||
870 | static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
871 | { | |
09611caa | 872 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 873 | struct i2c_client *client = dev->client; |
3adec272 BC |
874 | struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache; |
875 | int ret, tmp, power_real; | |
bc85d5e2 AP |
876 | unsigned int utmp; |
877 | u8 gain_offset, buf[7]; | |
4b64bb26 | 878 | |
81e19912 AP |
879 | dev_dbg(&client->dev, "\n"); |
880 | ||
3adec272 | 881 | if (dev->is_af9035) { |
81e19912 | 882 | /* Read signal strength of 0-100 scale */ |
bc85d5e2 AP |
883 | ret = regmap_read(dev->regmap, 0x800048, &utmp); |
884 | if (ret) | |
0b0d9628 AP |
885 | goto err; |
886 | ||
81e19912 | 887 | /* Scale value to 0x0000-0xffff */ |
bc85d5e2 | 888 | *strength = utmp * 0xffff / 100; |
3adec272 | 889 | } else { |
bc85d5e2 AP |
890 | ret = regmap_read(dev->regmap, 0x8000f7, &utmp); |
891 | if (ret) | |
1620d221 AP |
892 | goto err; |
893 | ||
bc85d5e2 AP |
894 | ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7); |
895 | if (ret) | |
1620d221 | 896 | goto err; |
3adec272 BC |
897 | |
898 | if (c->frequency <= 300000000) | |
899 | gain_offset = 7; /* VHF */ | |
900 | else | |
901 | gain_offset = 4; /* UHF */ | |
902 | ||
bc85d5e2 | 903 | power_real = (utmp - 100 - gain_offset) - |
3adec272 BC |
904 | power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)]; |
905 | ||
906 | if (power_real < -15) | |
907 | tmp = 0; | |
908 | else if ((power_real >= -15) && (power_real < 0)) | |
909 | tmp = (2 * (power_real + 15)) / 3; | |
910 | else if ((power_real >= 0) && (power_real < 20)) | |
911 | tmp = 4 * power_real + 10; | |
912 | else if ((power_real >= 20) && (power_real < 35)) | |
913 | tmp = (2 * (power_real - 20)) / 3 + 90; | |
914 | else | |
915 | tmp = 100; | |
916 | ||
81e19912 | 917 | /* Scale value to 0x0000-0xffff */ |
3adec272 BC |
918 | *strength = tmp * 0xffff / 100; |
919 | } | |
4b64bb26 | 920 | |
4b64bb26 | 921 | return 0; |
4b64bb26 | 922 | err: |
81e19912 | 923 | dev_dbg(&client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
924 | return ret; |
925 | } | |
926 | ||
927 | static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber) | |
928 | { | |
09611caa | 929 | struct af9033_dev *dev = fe->demodulator_priv; |
47eafa54 | 930 | |
e53c4744 AP |
931 | *ber = (dev->post_bit_error - dev->post_bit_error_prev); |
932 | dev->post_bit_error_prev = dev->post_bit_error; | |
4b64bb26 AP |
933 | |
934 | return 0; | |
935 | } | |
936 | ||
937 | static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
938 | { | |
09611caa | 939 | struct af9033_dev *dev = fe->demodulator_priv; |
4b64bb26 | 940 | |
1d0ceae4 | 941 | *ucblocks = dev->error_block_count; |
81e19912 | 942 | |
4b64bb26 AP |
943 | return 0; |
944 | } | |
945 | ||
946 | static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) | |
947 | { | |
09611caa | 948 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 949 | struct i2c_client *client = dev->client; |
4b64bb26 AP |
950 | int ret; |
951 | ||
81e19912 | 952 | dev_dbg(&client->dev, "enable=%d\n", enable); |
4b64bb26 | 953 | |
bc85d5e2 AP |
954 | ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable); |
955 | if (ret) | |
4b64bb26 AP |
956 | goto err; |
957 | ||
958 | return 0; | |
4b64bb26 | 959 | err: |
81e19912 | 960 | dev_dbg(&client->dev, "failed=%d\n", ret); |
4b64bb26 AP |
961 | return ret; |
962 | } | |
963 | ||
ed97a6fe | 964 | static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff) |
040cf86c | 965 | { |
09611caa | 966 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 967 | struct i2c_client *client = dev->client; |
040cf86c AP |
968 | int ret; |
969 | ||
81e19912 | 970 | dev_dbg(&client->dev, "onoff=%d\n", onoff); |
040cf86c | 971 | |
bc85d5e2 AP |
972 | ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff); |
973 | if (ret) | |
040cf86c AP |
974 | goto err; |
975 | ||
976 | return 0; | |
040cf86c | 977 | err: |
81e19912 | 978 | dev_dbg(&client->dev, "failed=%d\n", ret); |
040cf86c AP |
979 | return ret; |
980 | } | |
040cf86c | 981 | |
24e419a0 | 982 | static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid, |
81e19912 | 983 | int onoff) |
040cf86c | 984 | { |
09611caa | 985 | struct af9033_dev *dev = fe->demodulator_priv; |
81e19912 | 986 | struct i2c_client *client = dev->client; |
040cf86c AP |
987 | int ret; |
988 | u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff}; | |
989 | ||
81e19912 AP |
990 | dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n", |
991 | index, pid, onoff); | |
040cf86c AP |
992 | |
993 | if (pid > 0x1fff) | |
994 | return 0; | |
995 | ||
bc85d5e2 AP |
996 | ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2); |
997 | if (ret) | |
040cf86c | 998 | goto err; |
bc85d5e2 AP |
999 | ret = regmap_write(dev->regmap, 0x80f994, onoff); |
1000 | if (ret) | |
040cf86c | 1001 | goto err; |
bc85d5e2 AP |
1002 | ret = regmap_write(dev->regmap, 0x80f995, index); |
1003 | if (ret) | |
040cf86c AP |
1004 | goto err; |
1005 | ||
1006 | return 0; | |
040cf86c | 1007 | err: |
81e19912 | 1008 | dev_dbg(&client->dev, "failed=%d\n", ret); |
040cf86c AP |
1009 | return ret; |
1010 | } | |
040cf86c | 1011 | |
bd336e63 | 1012 | static const struct dvb_frontend_ops af9033_ops = { |
81e19912 | 1013 | .delsys = {SYS_DVBT}, |
f5b00a76 AP |
1014 | .info = { |
1015 | .name = "Afatech AF9033 (DVB-T)", | |
f1b1eabf MCC |
1016 | .frequency_min_hz = 174 * MHz, |
1017 | .frequency_max_hz = 862 * MHz, | |
1018 | .frequency_stepsize_hz = 250 * kHz, | |
f5b00a76 AP |
1019 | .caps = FE_CAN_FEC_1_2 | |
1020 | FE_CAN_FEC_2_3 | | |
1021 | FE_CAN_FEC_3_4 | | |
1022 | FE_CAN_FEC_5_6 | | |
1023 | FE_CAN_FEC_7_8 | | |
1024 | FE_CAN_FEC_AUTO | | |
1025 | FE_CAN_QPSK | | |
1026 | FE_CAN_QAM_16 | | |
1027 | FE_CAN_QAM_64 | | |
1028 | FE_CAN_QAM_AUTO | | |
1029 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
1030 | FE_CAN_GUARD_INTERVAL_AUTO | | |
1031 | FE_CAN_HIERARCHY_AUTO | | |
1032 | FE_CAN_RECOVER | | |
1033 | FE_CAN_MUTE_TS | |
1034 | }, | |
1035 | ||
1036 | .init = af9033_init, | |
1037 | .sleep = af9033_sleep, | |
1038 | ||
1039 | .get_tune_settings = af9033_get_tune_settings, | |
1040 | .set_frontend = af9033_set_frontend, | |
1041 | .get_frontend = af9033_get_frontend, | |
1042 | ||
1043 | .read_status = af9033_read_status, | |
1044 | .read_snr = af9033_read_snr, | |
1045 | .read_signal_strength = af9033_read_signal_strength, | |
1046 | .read_ber = af9033_read_ber, | |
1047 | .read_ucblocks = af9033_read_ucblocks, | |
1048 | ||
1049 | .i2c_gate_ctrl = af9033_i2c_gate_ctrl, | |
1050 | }; | |
4b64bb26 | 1051 | |
f5b00a76 | 1052 | static int af9033_probe(struct i2c_client *client, |
81e19912 | 1053 | const struct i2c_device_id *id) |
4b64bb26 | 1054 | { |
f5b00a76 | 1055 | struct af9033_config *cfg = client->dev.platform_data; |
09611caa | 1056 | struct af9033_dev *dev; |
f5b00a76 | 1057 | int ret; |
4b64bb26 | 1058 | u8 buf[8]; |
ef5211fd | 1059 | u32 reg; |
bc85d5e2 AP |
1060 | static const struct regmap_config regmap_config = { |
1061 | .reg_bits = 24, | |
1062 | .val_bits = 8, | |
1063 | }; | |
1064 | ||
81e19912 AP |
1065 | /* Allocate memory for the internal state */ |
1066 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1067 | if (!dev) { | |
f5b00a76 | 1068 | ret = -ENOMEM; |
4b64bb26 | 1069 | goto err; |
f5b00a76 | 1070 | } |
4b64bb26 | 1071 | |
81e19912 | 1072 | /* Setup the state */ |
f5b00a76 | 1073 | dev->client = client; |
81e19912 AP |
1074 | memcpy(&dev->cfg, cfg, sizeof(dev->cfg)); |
1075 | switch (dev->cfg.ts_mode) { | |
1076 | case AF9033_TS_MODE_PARALLEL: | |
1077 | dev->ts_mode_parallel = true; | |
1078 | break; | |
1079 | case AF9033_TS_MODE_SERIAL: | |
1080 | dev->ts_mode_serial = true; | |
1081 | break; | |
1082 | case AF9033_TS_MODE_USB: | |
1083 | /* USB mode for AF9035 */ | |
1084 | default: | |
1085 | break; | |
1086 | } | |
4b64bb26 | 1087 | |
09611caa | 1088 | if (dev->cfg.clock != 12000000) { |
f5b00a76 | 1089 | ret = -ENODEV; |
81e19912 AP |
1090 | dev_err(&client->dev, |
1091 | "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n", | |
1092 | dev->cfg.clock); | |
f5b00a76 | 1093 | goto err_kfree; |
8e8a5ac7 AP |
1094 | } |
1095 | ||
bc85d5e2 AP |
1096 | /* Create regmap */ |
1097 | dev->regmap = regmap_init_i2c(client, ®map_config); | |
1098 | if (IS_ERR(dev->regmap)) { | |
1099 | ret = PTR_ERR(dev->regmap); | |
1100 | goto err_kfree; | |
1101 | } | |
1102 | ||
81e19912 | 1103 | /* Firmware version */ |
09611caa | 1104 | switch (dev->cfg.tuner) { |
ef5211fd AP |
1105 | case AF9033_TUNER_IT9135_38: |
1106 | case AF9033_TUNER_IT9135_51: | |
1107 | case AF9033_TUNER_IT9135_52: | |
1108 | case AF9033_TUNER_IT9135_60: | |
1109 | case AF9033_TUNER_IT9135_61: | |
1110 | case AF9033_TUNER_IT9135_62: | |
83f11619 | 1111 | dev->is_it9135 = true; |
ef5211fd AP |
1112 | reg = 0x004bfc; |
1113 | break; | |
1114 | default: | |
83f11619 | 1115 | dev->is_af9035 = true; |
ef5211fd AP |
1116 | reg = 0x0083e9; |
1117 | break; | |
1118 | } | |
1119 | ||
bc85d5e2 AP |
1120 | ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4); |
1121 | if (ret) | |
1122 | goto err_regmap_exit; | |
1123 | ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4); | |
1124 | if (ret) | |
1125 | goto err_regmap_exit; | |
4b64bb26 | 1126 | |
81e19912 AP |
1127 | dev_info(&client->dev, |
1128 | "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n", | |
1129 | buf[0], buf[1], buf[2], buf[3], | |
1130 | buf[4], buf[5], buf[6], buf[7]); | |
4b64bb26 | 1131 | |
81e19912 | 1132 | /* Sleep as chip seems to be partly active by default */ |
09a446d2 VT |
1133 | /* IT9135 did not like to sleep at that early */ |
1134 | if (dev->is_af9035) { | |
bc85d5e2 AP |
1135 | ret = regmap_write(dev->regmap, 0x80004c, 0x01); |
1136 | if (ret) | |
1137 | goto err_regmap_exit; | |
1138 | ret = regmap_write(dev->regmap, 0x800000, 0x00); | |
1139 | if (ret) | |
1140 | goto err_regmap_exit; | |
4902bb39 | 1141 | } |
12897dc3 | 1142 | |
81e19912 AP |
1143 | /* Create dvb frontend */ |
1144 | memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops)); | |
09611caa | 1145 | dev->fe.demodulator_priv = dev; |
f5b00a76 AP |
1146 | *cfg->fe = &dev->fe; |
1147 | if (cfg->ops) { | |
1148 | cfg->ops->pid_filter = af9033_pid_filter; | |
1149 | cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl; | |
ed97a6fe | 1150 | } |
3461831a | 1151 | cfg->regmap = dev->regmap; |
f5b00a76 | 1152 | i2c_set_clientdata(client, dev); |
ed97a6fe | 1153 | |
81e19912 AP |
1154 | dev_info(&client->dev, "Afatech AF9033 successfully attached\n"); |
1155 | ||
f5b00a76 | 1156 | return 0; |
bc85d5e2 AP |
1157 | err_regmap_exit: |
1158 | regmap_exit(dev->regmap); | |
f5b00a76 | 1159 | err_kfree: |
09611caa | 1160 | kfree(dev); |
f5b00a76 | 1161 | err: |
6a087f1f | 1162 | dev_dbg(&client->dev, "failed=%d\n", ret); |
f5b00a76 | 1163 | return ret; |
4b64bb26 | 1164 | } |
4b64bb26 | 1165 | |
f5b00a76 AP |
1166 | static int af9033_remove(struct i2c_client *client) |
1167 | { | |
1168 | struct af9033_dev *dev = i2c_get_clientdata(client); | |
4b64bb26 | 1169 | |
81e19912 | 1170 | dev_dbg(&client->dev, "\n"); |
4b64bb26 | 1171 | |
bc85d5e2 | 1172 | regmap_exit(dev->regmap); |
f5b00a76 | 1173 | kfree(dev); |
4b64bb26 | 1174 | |
f5b00a76 AP |
1175 | return 0; |
1176 | } | |
4b64bb26 | 1177 | |
f5b00a76 AP |
1178 | static const struct i2c_device_id af9033_id_table[] = { |
1179 | {"af9033", 0}, | |
1180 | {} | |
1181 | }; | |
1182 | MODULE_DEVICE_TABLE(i2c, af9033_id_table); | |
4b64bb26 | 1183 | |
f5b00a76 AP |
1184 | static struct i2c_driver af9033_driver = { |
1185 | .driver = { | |
f5b00a76 | 1186 | .name = "af9033", |
72812175 | 1187 | .suppress_bind_attrs = true, |
f5b00a76 AP |
1188 | }, |
1189 | .probe = af9033_probe, | |
1190 | .remove = af9033_remove, | |
1191 | .id_table = af9033_id_table, | |
4b64bb26 AP |
1192 | }; |
1193 | ||
f5b00a76 AP |
1194 | module_i2c_driver(af9033_driver); |
1195 | ||
4b64bb26 AP |
1196 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); |
1197 | MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver"); | |
1198 | MODULE_LICENSE("GPL"); |