[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / au8522_priv.h

/*
    Auvitek AU8522 QAM/8VSB demodulator driver

    Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
    Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>
    Copyright (C) 2005-2008 Auvitek International, Ltd.

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <linux/i2c.h>
#include "dvb_frontend.h"
#include "au8522.h"
#include "tuner-i2c.h"

#define AU8522_ANALOG_MODE 0
#define AU8522_DIGITAL_MODE 1
#define AU8522_SUSPEND_MODE 2

enum au8522_media_pads {
	AU8522_PAD_INPUT,
	AU8522_PAD_VID_OUT,
	AU8522_PAD_VBI_OUT,

	AU8522_NUM_PADS
};

struct au8522_state {
	struct i2c_client *c;
	struct i2c_adapter *i2c;

	u8 operational_mode;

	/* Used for sharing of the state between analog and digital mode */
	struct tuner_i2c_props i2c_props;
	struct list_head hybrid_tuner_instance_list;

	/* configuration settings */
	struct au8522_config config;

	struct dvb_frontend frontend;

	u32 current_frequency;
	enum fe_modulation current_modulation;

	u32 fe_status;
	unsigned int led_state;

	/* Analog settings */
	struct v4l2_subdev sd;
	v4l2_std_id std;
	int vid_input;
	int aud_input;
	u32 id;
	u32 rev;
	struct v4l2_ctrl_handler hdl;

#ifdef CONFIG_MEDIA_CONTROLLER
	struct media_pad pads[AU8522_NUM_PADS];
#endif
};

/* These are routines shared by both the VSB/QAM demodulator and the analog
   decoder */
int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);
u8 au8522_readreg(struct au8522_state *state, u16 reg);
int au8522_init(struct dvb_frontend *fe);
int au8522_sleep(struct dvb_frontend *fe);

int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,
		     u8 client_address);
void au8522_release_state(struct au8522_state *state);
int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
int au8522_led_ctrl(struct au8522_state *state, int led);

/* REGISTERS */
#define AU8522_INPUT_CONTROL_REG081H			0x081
#define AU8522_PGA_CONTROL_REG082H			0x082
#define AU8522_CLAMPING_CONTROL_REG083H			0x083

#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H		0x0A3
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H		0x0A4
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H		0x0A5
#define AU8522_AGC_CONTROL_RANGE_REG0A6H		0x0A6
#define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H		0x0A7
#define AU8522_TUNER_AGC_RF_STOP_REG0A8H  		0x0A8
#define AU8522_TUNER_AGC_RF_START_REG0A9H		0x0A9
#define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH		0x0AA
#define AU8522_TUNER_AGC_IF_STOP_REG0ABH		0x0AB
#define AU8522_TUNER_AGC_IF_START_REG0ACH		0x0AC
#define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH		0x0AD
#define AU8522_TUNER_AGC_STEP_REG0AEH			0x0AE
#define AU8522_TUNER_GAIN_STEP_REG0AFH			0x0AF

/* Receiver registers */
#define AU8522_FRMREGTHRD1_REG0B0H			0x0B0
#define AU8522_FRMREGAGC1H_REG0B1H 			0x0B1
#define AU8522_FRMREGSHIFT1_REG0B2H 			0x0B2
#define AU8522_TOREGAGC1_REG0B3H 			0x0B3
#define AU8522_TOREGASHIFT1_REG0B4H 			0x0B4
#define AU8522_FRMREGBBH_REG0B5H			0x0B5
#define AU8522_FRMREGBBM_REG0B6H 			0x0B6
#define AU8522_FRMREGBBL_REG0B7H     			0x0B7
/* 0xB8 TO 0xD7 are the filter coefficients */
#define AU8522_FRMREGTHRD2_REG0D8H 			0x0D8
#define AU8522_FRMREGAGC2H_REG0D9H 			0x0D9
#define AU8522_TOREGAGC2_REG0DAH 			0x0DA
#define AU8522_TOREGSHIFT2_REG0DBH 			0x0DB
#define AU8522_FRMREGPILOTH_REG0DCH			0x0DC
#define AU8522_FRMREGPILOTM_REG0DDH			0x0DD
#define AU8522_FRMREGPILOTL_REG0DEH			0x0DE
#define AU8522_TOREGFREQ_REG0DFH			0x0DF

#define AU8522_RX_PGA_RFOUT_REG0EBH			0x0EB
#define AU8522_RX_PGA_IFOUT_REG0ECH			0x0EC
#define AU8522_RX_PGA_PGAOUT_REG0EDH			0x0ED

#define AU8522_CHIP_MODE_REG0FEH			0x0FE

/* I2C bus control registers */
#define AU8522_I2C_CONTROL_REG0_REG090H    		0x090
#define AU8522_I2C_CONTROL_REG1_REG091H    		0x091
#define AU8522_I2C_STATUS_REG092H          		0x092
#define AU8522_I2C_WR_DATA0_REG093H			0x093
#define AU8522_I2C_WR_DATA1_REG094H			0x094
#define AU8522_I2C_WR_DATA2_REG095H			0x095
#define AU8522_I2C_WR_DATA3_REG096H			0x096
#define AU8522_I2C_WR_DATA4_REG097H			0x097
#define AU8522_I2C_WR_DATA5_REG098H			0x098
#define AU8522_I2C_WR_DATA6_REG099H			0x099
#define AU8522_I2C_WR_DATA7_REG09AH			0x09A
#define AU8522_I2C_RD_DATA0_REG09BH			0x09B
#define AU8522_I2C_RD_DATA1_REG09CH			0x09C
#define AU8522_I2C_RD_DATA2_REG09DH			0x09D
#define AU8522_I2C_RD_DATA3_REG09EH			0x09E
#define AU8522_I2C_RD_DATA4_REG09FH			0x09F
#define AU8522_I2C_RD_DATA5_REG0A0H			0x0A0
#define AU8522_I2C_RD_DATA6_REG0A1H			0x0A1
#define AU8522_I2C_RD_DATA7_REG0A2H			0x0A2

#define AU8522_ENA_USB_REG101H				0x101

#define AU8522_I2S_CTRL_0_REG110H  			0x110
#define AU8522_I2S_CTRL_1_REG111H 			0x111
#define AU8522_I2S_CTRL_2_REG112H 			0x112

#define AU8522_FRMREGFFECONTROL_REG121H    		0x121
#define AU8522_FRMREGDFECONTROL_REG122H    		0x122

#define AU8522_CARRFREQOFFSET0_REG201H 			0x201
#define AU8522_CARRFREQOFFSET1_REG202H			0x202

#define AU8522_DECIMATION_GAIN_REG21AH			0x21A
#define AU8522_FRMREGIFSLP_REG21BH 			0x21B
#define AU8522_FRMREGTHRDL2_REG21CH 			0x21C
#define AU8522_FRMREGSTEP3DB_REG21DH 			0x21D
#define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH		0x21E
#define AU8522_FRMREGPLLMODE_REG21FH 			0x21F
#define AU8522_FRMREGCSTHRD_REG220H 			0x220
#define AU8522_FRMREGCRLOCKDMAX_REG221H 		0x221
#define AU8522_FRMREGCRPERIODMASK_REG222H 		0x222
#define AU8522_FRMREGCRLOCK0THH_REG223H 		0x223
#define AU8522_FRMREGCRLOCK1THH_REG224H 		0x224
#define AU8522_FRMREGCRLOCK0THL_REG225H 		0x225
#define AU8522_FRMREGCRLOCK1THL_REG226H 		0x226
#define AU_FRMREGPLLACQPHASESCL_REG227H			0x227
#define AU8522_FRMREGFREQFBCTRL_REG228H 		0x228

/* Analog TV Decoder */
#define AU8522_TVDEC_STATUS_REG000H			0x000
#define AU8522_TVDEC_INT_STATUS_REG001H			0x001
#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 	0x002
#define AU8522_TVDEC_SHARPNESSREG009H			0x009
#define AU8522_TVDEC_BRIGHTNESS_REG00AH			0x00A
#define AU8522_TVDEC_CONTRAST_REG00BH			0x00B
#define AU8522_TVDEC_SATURATION_CB_REG00CH		0x00C
#define AU8522_TVDEC_SATURATION_CR_REG00DH		0x00D
#define AU8522_TVDEC_HUE_H_REG00EH			0x00E
#define AU8522_TVDEC_HUE_L_REG00FH                   	0x00F
#define AU8522_TVDEC_INT_MASK_REG010H			0x010
#define AU8522_VIDEO_MODE_REG011H			0x011
#define AU8522_TVDEC_PGA_REG012H			0x012
#define AU8522_TVDEC_COMB_MODE_REG015H			0x015
#define AU8522_REG016H                            	0x016
#define AU8522_TVDED_DBG_MODE_REG060H			0x060
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H		0x061
#define AU8522_TVDEC_FORMAT_CTRL2_REG062H		0x062
#define AU8522_TVDEC_VCR_DET_LLIM_REG063H		0x063
#define AU8522_TVDEC_VCR_DET_HLIM_REG064H		0x064
#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H		0x065
#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H		0x066
#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H		0x067
#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H		0x068
#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H   		0x069
#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH		0x06A
#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH   		0x06B
#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH  		0x06C
#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 		0x06D
#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH       	0x06E
#define AU8522_TVDEC_UV_SEP_THR_REG06FH  		0x06F
#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H		0x070
#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H		0x073
#define AU8522_TVDEC_DCAGC_CTRL_REG077H			0x077
#define AU8522_TVDEC_PIC_START_ADJ_REG078H		0x078
#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H		0x079
#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH	0x07A
#define AU8522_TVDEC_INTRP_CTRL_REG07BH			0x07B
#define AU8522_TVDEC_PLL_STATUS_REG07EH			0x07E
#define AU8522_TVDEC_FSC_FREQ_REG07FH			0x07F

#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H		0x0E4
#define AU8522_TOREGAAGC_REG0E5H			0x0E5

#define AU8522_TVDEC_CHROMA_AGC_REG401H		0x401
#define AU8522_TVDEC_CHROMA_SFT_REG402H		0x402
#define AU8522_FILTER_COEF_R410     		0x410
#define AU8522_FILTER_COEF_R411     		0x411
#define AU8522_FILTER_COEF_R412     		0x412
#define AU8522_FILTER_COEF_R413     		0x413
#define AU8522_FILTER_COEF_R414     		0x414
#define AU8522_FILTER_COEF_R415     		0x415
#define AU8522_FILTER_COEF_R416     		0x416
#define AU8522_FILTER_COEF_R417     		0x417
#define AU8522_FILTER_COEF_R418     		0x418
#define AU8522_FILTER_COEF_R419     		0x419
#define AU8522_FILTER_COEF_R41A     		0x41A
#define AU8522_FILTER_COEF_R41B     		0x41B
#define AU8522_FILTER_COEF_R41C     		0x41C
#define AU8522_FILTER_COEF_R41D     		0x41D
#define AU8522_FILTER_COEF_R41E     		0x41E
#define AU8522_FILTER_COEF_R41F     		0x41F
#define AU8522_FILTER_COEF_R420     		0x420
#define AU8522_FILTER_COEF_R421     		0x421
#define AU8522_FILTER_COEF_R422     		0x422
#define AU8522_FILTER_COEF_R423     		0x423
#define AU8522_FILTER_COEF_R424     		0x424
#define AU8522_FILTER_COEF_R425     		0x425
#define AU8522_FILTER_COEF_R426     		0x426
#define AU8522_FILTER_COEF_R427     		0x427
#define AU8522_FILTER_COEF_R428     		0x428
#define AU8522_FILTER_COEF_R429     		0x429
#define AU8522_FILTER_COEF_R42A     		0x42A
#define AU8522_FILTER_COEF_R42B     		0x42B
#define AU8522_FILTER_COEF_R42C     		0x42C
#define AU8522_FILTER_COEF_R42D     		0x42D

/* VBI Control Registers */
#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H  	0x004
#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H  	0x005
#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H      	0x006
#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H       	0x007
#define AU8522_TVDEC_VBI_CTRL_H_REG017H			0x017
#define AU8522_TVDEC_VBI_CTRL_L_REG018H			0x018
#define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H	0x019
#define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH		0x01A
#define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH		0x01B
#define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH		0x01C
#define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH	0x01E
#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH   	0x01F
#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H   	0x020
#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 	0x021
#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H  	0x022
#define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H	0x023

#define AU8522_REG071H					0x071
#define AU8522_REG072H					0x072
#define AU8522_REG074H					0x074
#define AU8522_REG075H					0x075

/* Digital Demodulator Registers */
#define AU8522_FRAME_COUNT0_REG084H			0x084
#define AU8522_RS_STATUS_G0_REG085H			0x085
#define AU8522_RS_STATUS_B0_REG086H			0x086
#define AU8522_RS_STATUS_E_REG087H			0x087
#define AU8522_DEMODULATION_STATUS_REG088H		0x088
#define AU8522_TOREGTRESTATUS_REG0E6H			0x0E6
#define AU8522_TSPORT_CONTROL_REG10BH			0x10B
#define AU8522_TSTHES_REG10CH				0x10C
#define AU8522_FRMREGDFEKEEP_REG301H			0x301
#define AU8522_DFE_AVERAGE_REG302H			0x302
#define AU8522_FRMREGEQLERRWIN_REG303H			0x303
#define AU8522_FRMREGFFEKEEP_REG304H			0x304
#define AU8522_FRMREGDFECONTROL1_REG305H		0x305
#define AU8522_FRMREGEQLERRLOW_REG306H			0x306

#define AU8522_REG42EH				0x42E
#define AU8522_REG42FH				0x42F
#define AU8522_REG430H				0x430
#define AU8522_REG431H				0x431
#define AU8522_REG432H				0x432
#define AU8522_REG433H				0x433
#define AU8522_REG434H				0x434
#define AU8522_REG435H				0x435
#define AU8522_REG436H				0x436

/* GPIO Registers */
#define AU8522_GPIO_CONTROL_REG0E0H			0x0E0
#define AU8522_GPIO_STATUS_REG0E1H			0x0E1
#define AU8522_GPIO_DATA_REG0E2H			0x0E2

/* Audio Control Registers */
#define AU8522_AUDIOAGC_REG0EEH 			0x0EE
#define AU8522_AUDIO_STATUS_REG0F0H 			0x0F0
#define AU8522_AUDIO_MODE_REG0F1H 			0x0F1
#define AU8522_AUDIO_VOLUME_L_REG0F2H 			0x0F2
#define AU8522_AUDIO_VOLUME_R_REG0F3H 			0x0F3
#define AU8522_AUDIO_VOLUME_REG0F4H 			0x0F4
#define AU8522_FRMREGAUPHASE_REG0F7H 			0x0F7
#define AU8522_REG0F9H					0x0F9

#define AU8522_AUDIOAGC2_REG605H 			0x605
#define AU8522_AUDIOFREQ_REG606H 			0x606


/**************************************************************/

/* Format control 1 */

/* VCR Mode 7-6 */
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES		0x80
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO		0x40
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO		0x00
/* Field len 5-4 */
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625		0x20
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525		0x10
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO	0x00
/* Line len (us) 3-2 */
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000	0x0b
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492	0x08
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556	0x04
/* Subcarrier freq 1-0 */
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO	0x03
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443	0x02
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN	0x01
#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50	0x00

/* Format control 2 */
#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT	0x00
#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC		0x01
#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M		0x02


#define AU8522_INPUT_CONTROL_REG081H_ATSC               	0xC4
#define AU8522_INPUT_CONTROL_REG081H_ATVRF			0xC4
#define AU8522_INPUT_CONTROL_REG081H_ATVRF13			0xC4
#define AU8522_INPUT_CONTROL_REG081H_J83B64             	0xC4
#define AU8522_INPUT_CONTROL_REG081H_J83B256            	0xC4
#define AU8522_INPUT_CONTROL_REG081H_CVBS               	0x20
#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1			0xA2
#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2			0xA0
#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3			0x69
#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4			0x68
#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF        	0x28
/* CH1 AS Y,CH3 AS C */
#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13        	0x23
/* CH2 AS Y,CH4 AS C */
#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24        	0x20
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC        	0x0C
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64      	0x09
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256    		0x09
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS        	0x12
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF       	0x1A
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13		0x1A
#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO		0x02

#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR		0x00
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO		0x9C
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS     	0x9D
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC		0xE8
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 		0xCA
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64  		0xCA
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF   		0xDD
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13		0xDD
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL		0xDD
#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM		0xDD

#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC		0x80
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 		0x80
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64  		0x80
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC	0x40
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256	0x40
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64	0x40
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR	0x00
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF		0x01
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13		0x01
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO  		0x04
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS		0x01
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM     		0x03
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS      	0x09
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL		0x01
#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM		0x01

/* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */
#define AU8522_TVDEC_CONTRAST_REG00BH_CVBS			0x79
#define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS			0x80
#define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS			0x80
#define AU8522_TVDEC_HUE_H_REG00EH_CVBS				0x00
#define AU8522_TVDEC_HUE_L_REG00FH_CVBS				0x00
#define AU8522_TVDEC_PGA_REG012H_CVBS				0x0F
#define AU8522_TVDEC_COMB_MODE_REG015H_CVBS			0x00
#define AU8522_REG016H_CVBS					0x00
#define AU8522_TVDED_DBG_MODE_REG060H_CVBS			0x00
#define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS			0x19
#define AU8522_REG0F9H_AUDIO					0x20
#define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS			0xA7
#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS		0x0A
#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS		0x32
#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS		0x19
#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS		0x23
#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS		0x41
#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS		0x0A
#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS		0x32
#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS		0x34
#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO		0x2a
#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS		0x05
#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO		0x15
#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS		0x6E
#define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS			0x0F
#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS		0x80
#define AU8522_REG071H_CVBS					0x18
#define AU8522_REG072H_CVBS					0x30
#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS		0xF0
#define AU8522_REG074H_CVBS					0x80
#define AU8522_REG075H_CVBS					0xF0
#define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS			0xFB
#define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS			0x04
#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS		0x00
#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS		0x00
#define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS			0xEE
#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS			0xFE
#define AU8522_TOREGAAGC_REG0E5H_CVBS				0x00
#define AU8522_TVDEC_VBI6A_REG035H_CVBS				0x40

/* Enables Closed captioning */
#define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON			0x21
Commit	Line	Data
0c44bf36 DH	1	/*
	2	Auvitek AU8522 QAM/8VSB demodulator driver
	3
	4	Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
	5	Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>
	6	Copyright (C) 2005-2008 Auvitek International, Ltd.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/string.h>
	28	#include <linux/slab.h>
	29	#include <linux/delay.h>
	30	#include <linux/videodev2.h>
	31	#include <media/v4l2-device.h>
5a4bdb4b	32	#include <media/v4l2-ctrls.h>
0c44bf36 DH	33	#include <linux/i2c.h>
	34	#include "dvb_frontend.h"
	35	#include "au8522.h"
	36	#include "tuner-i2c.h"
	37
7f2c983c DH	38	#define AU8522_ANALOG_MODE 0
7f2c983c DH	39	#define AU8522_DIGITAL_MODE 1
38fe3510	40	#define AU8522_SUSPEND_MODE 2
7f2c983c	41
bed69196 RLLC	42	enum au8522_media_pads {
	43	AU8522_PAD_INPUT,
	44	AU8522_PAD_VID_OUT,
	45	AU8522_PAD_VBI_OUT,
	46
	47	AU8522_NUM_PADS
	48	};
	49
0c44bf36	50	struct au8522_state {
968cf782	51	struct i2c_client *c;
0c44bf36 DH	52	struct i2c_adapter *i2c;
0c44bf36 DH	53
7f2c983c DH	54	u8 operational_mode;
7f2c983c DH	55
209fdf66 DH	56	/* Used for sharing of the state between analog and digital mode */
	57	struct tuner_i2c_props i2c_props;
	58	struct list_head hybrid_tuner_instance_list;
	59
0c44bf36	60	/* configuration settings */
aa37763f	61	struct au8522_config config;
0c44bf36 DH	62
	63	struct dvb_frontend frontend;
	64
	65	u32 current_frequency;
0df289a2	66	enum fe_modulation current_modulation;
0c44bf36 DH	67
	68	u32 fe_status;
	69	unsigned int led_state;
968cf782 DH	70
	71	/* Analog settings */
	72	struct v4l2_subdev sd;
	73	v4l2_std_id std;
	74	int vid_input;
	75	int aud_input;
	76	u32 id;
	77	u32 rev;
5a4bdb4b	78	struct v4l2_ctrl_handler hdl;
bed69196 RLLC	79
	80	#ifdef CONFIG_MEDIA_CONTROLLER
	81	struct media_pad pads[AU8522_NUM_PADS];
	82	#endif
0c44bf36 DH	83	};
	84
	85	/* These are routines shared by both the VSB/QAM demodulator and the analog
	86	decoder */
	87	int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);
	88	u8 au8522_readreg(struct au8522_state *state, u16 reg);
	89	int au8522_init(struct dvb_frontend *fe);
	90	int au8522_sleep(struct dvb_frontend *fe);
209fdf66 DH	91
	92	int au8522_get_state(struct au8522_state *state, struct i2c_adapter i2c,
	93	u8 client_address);
	94	void au8522_release_state(struct au8522_state *state);
b31506c4	95	int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
4a03dafc	96	int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
b31506c4	97	int au8522_led_ctrl(struct au8522_state *state, int led);
968cf782 DH	98
	99	/* REGISTERS */
	100	#define AU8522_INPUT_CONTROL_REG081H 0x081
	101	#define AU8522_PGA_CONTROL_REG082H 0x082
	102	#define AU8522_CLAMPING_CONTROL_REG083H 0x083
	103
	104	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
	105	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
	106	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
	107	#define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
	108	#define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
	109	#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
	110	#define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A9
	111	#define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA
	112	#define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB
	113	#define AU8522_TUNER_AGC_IF_START_REG0ACH 0x0AC
	114	#define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH 0x0AD
	115	#define AU8522_TUNER_AGC_STEP_REG0AEH 0x0AE
	116	#define AU8522_TUNER_GAIN_STEP_REG0AFH 0x0AF
	117
	118	/* Receiver registers */
	119	#define AU8522_FRMREGTHRD1_REG0B0H 0x0B0
	120	#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1
	121	#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2
	122	#define AU8522_TOREGAGC1_REG0B3H 0x0B3
	123	#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4
	124	#define AU8522_FRMREGBBH_REG0B5H 0x0B5
	125	#define AU8522_FRMREGBBM_REG0B6H 0x0B6
	126	#define AU8522_FRMREGBBL_REG0B7H 0x0B7
	127	/* 0xB8 TO 0xD7 are the filter coefficients */
	128	#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8
	129	#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9
	130	#define AU8522_TOREGAGC2_REG0DAH 0x0DA
	131	#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB
	132	#define AU8522_FRMREGPILOTH_REG0DCH 0x0DC
	133	#define AU8522_FRMREGPILOTM_REG0DDH 0x0DD
	134	#define AU8522_FRMREGPILOTL_REG0DEH 0x0DE
	135	#define AU8522_TOREGFREQ_REG0DFH 0x0DF
	136
	137	#define AU8522_RX_PGA_RFOUT_REG0EBH 0x0EB
	138	#define AU8522_RX_PGA_IFOUT_REG0ECH 0x0EC
	139	#define AU8522_RX_PGA_PGAOUT_REG0EDH 0x0ED
	140
	141	#define AU8522_CHIP_MODE_REG0FEH 0x0FE
	142
	143	/* I2C bus control registers */
	144	#define AU8522_I2C_CONTROL_REG0_REG090H 0x090
	145	#define AU8522_I2C_CONTROL_REG1_REG091H 0x091
	146	#define AU8522_I2C_STATUS_REG092H 0x092
	147	#define AU8522_I2C_WR_DATA0_REG093H 0x093
	148	#define AU8522_I2C_WR_DATA1_REG094H 0x094
	149	#define AU8522_I2C_WR_DATA2_REG095H 0x095
	150	#define AU8522_I2C_WR_DATA3_REG096H 0x096
	151	#define AU8522_I2C_WR_DATA4_REG097H 0x097
	152	#define AU8522_I2C_WR_DATA5_REG098H 0x098
	153	#define AU8522_I2C_WR_DATA6_REG099H 0x099
	154	#define AU8522_I2C_WR_DATA7_REG09AH 0x09A
	155	#define AU8522_I2C_RD_DATA0_REG09BH 0x09B
	156	#define AU8522_I2C_RD_DATA1_REG09CH 0x09C
	157	#define AU8522_I2C_RD_DATA2_REG09DH 0x09D
	158	#define AU8522_I2C_RD_DATA3_REG09EH 0x09E
	159	#define AU8522_I2C_RD_DATA4_REG09FH 0x09F
	160	#define AU8522_I2C_RD_DATA5_REG0A0H 0x0A0
	161	#define AU8522_I2C_RD_DATA6_REG0A1H 0x0A1
162	#define AU8522_I2C_RD_DATA7_REG0A2H 0x0A2
163
164	#define AU8522_ENA_USB_REG101H 0x101
165
166	#define AU8522_I2S_CTRL_0_REG110H 0x110
167	#define AU8522_I2S_CTRL_1_REG111H 0x111
168	#define AU8522_I2S_CTRL_2_REG112H 0x112
169
170	#define AU8522_FRMREGFFECONTROL_REG121H 0x121
171	#define AU8522_FRMREGDFECONTROL_REG122H 0x122
172
173	#define AU8522_CARRFREQOFFSET0_REG201H 0x201
174	#define AU8522_CARRFREQOFFSET1_REG202H 0x202
175
176	#define AU8522_DECIMATION_GAIN_REG21AH 0x21A
177	#define AU8522_FRMREGIFSLP_REG21BH 0x21B
178	#define AU8522_FRMREGTHRDL2_REG21CH 0x21C
179	#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D
180	#define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E
181	#define AU8522_FRMREGPLLMODE_REG21FH 0x21F
182	#define AU8522_FRMREGCSTHRD_REG220H 0x220
183	#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221
184	#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222
185	#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223
186	#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224
187	#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225
188	#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226
189	#define AU_FRMREGPLLACQPHASESCL_REG227H 0x227
190	#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228
191
192	/* Analog TV Decoder */
193	#define AU8522_TVDEC_STATUS_REG000H 0x000
194	#define AU8522_TVDEC_INT_STATUS_REG001H 0x001
195	#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002
196	#define AU8522_TVDEC_SHARPNESSREG009H 0x009
197	#define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A
198	#define AU8522_TVDEC_CONTRAST_REG00BH 0x00B
199	#define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C
200	#define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D
201	#define AU8522_TVDEC_HUE_H_REG00EH 0x00E
202	#define AU8522_TVDEC_HUE_L_REG00FH 0x00F
203	#define AU8522_TVDEC_INT_MASK_REG010H 0x010
204	#define AU8522_VIDEO_MODE_REG011H 0x011
205	#define AU8522_TVDEC_PGA_REG012H 0x012
206	#define AU8522_TVDEC_COMB_MODE_REG015H 0x015
207	#define AU8522_REG016H 0x016
208	#define AU8522_TVDED_DBG_MODE_REG060H 0x060
209	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061
210	#define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062
211	#define AU8522_TVDEC_VCR_DET_LLIM_REG063H 0x063
212	#define AU8522_TVDEC_VCR_DET_HLIM_REG064H 0x064
213	#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H 0x065
214	#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066
215	#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067
216	#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068
217	#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069
218	#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A
219	#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B
220	#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C
221	#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D
222	#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E
223	#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F
224	#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070
225	#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073
226	#define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077
227	#define AU8522_TVDEC_PIC_START_ADJ_REG078H 0x078
228	#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H 0x079
229	#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH 0x07A
230	#define AU8522_TVDEC_INTRP_CTRL_REG07BH 0x07B
231	#define AU8522_TVDEC_PLL_STATUS_REG07EH 0x07E
232	#define AU8522_TVDEC_FSC_FREQ_REG07FH 0x07F
233
234	#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H 0x0E4
235	#define AU8522_TOREGAAGC_REG0E5H 0x0E5
236
237	#define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401
238	#define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402
239	#define AU8522_FILTER_COEF_R410 0x410
240	#define AU8522_FILTER_COEF_R411 0x411
241	#define AU8522_FILTER_COEF_R412 0x412
242	#define AU8522_FILTER_COEF_R413 0x413
243	#define AU8522_FILTER_COEF_R414 0x414
244	#define AU8522_FILTER_COEF_R415 0x415
245	#define AU8522_FILTER_COEF_R416 0x416
246	#define AU8522_FILTER_COEF_R417 0x417
247	#define AU8522_FILTER_COEF_R418 0x418
248	#define AU8522_FILTER_COEF_R419 0x419
249	#define AU8522_FILTER_COEF_R41A 0x41A
250	#define AU8522_FILTER_COEF_R41B 0x41B
251	#define AU8522_FILTER_COEF_R41C 0x41C
252	#define AU8522_FILTER_COEF_R41D 0x41D
253	#define AU8522_FILTER_COEF_R41E 0x41E
254	#define AU8522_FILTER_COEF_R41F 0x41F
255	#define AU8522_FILTER_COEF_R420 0x420
256	#define AU8522_FILTER_COEF_R421 0x421
257	#define AU8522_FILTER_COEF_R422 0x422
258	#define AU8522_FILTER_COEF_R423 0x423
259	#define AU8522_FILTER_COEF_R424 0x424
260	#define AU8522_FILTER_COEF_R425 0x425
261	#define AU8522_FILTER_COEF_R426 0x426
262	#define AU8522_FILTER_COEF_R427 0x427
263	#define AU8522_FILTER_COEF_R428 0x428
264	#define AU8522_FILTER_COEF_R429 0x429
265	#define AU8522_FILTER_COEF_R42A 0x42A
266	#define AU8522_FILTER_COEF_R42B 0x42B
267	#define AU8522_FILTER_COEF_R42C 0x42C
268	#define AU8522_FILTER_COEF_R42D 0x42D
269
270	/* VBI Control Registers */
271	#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004
272	#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005
273	#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006
274	#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007
275	#define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017
276	#define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018
277	#define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019
278	#define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH 0x01A
279	#define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B
280	#define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C
281	#define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E
282	#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F
283	#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020
284	#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021
285	#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022
286	#define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023
287
288	#define AU8522_REG071H 0x071
289	#define AU8522_REG072H 0x072
290	#define AU8522_REG074H 0x074
291	#define AU8522_REG075H 0x075
292
293	/* Digital Demodulator Registers */
294	#define AU8522_FRAME_COUNT0_REG084H 0x084
295	#define AU8522_RS_STATUS_G0_REG085H 0x085
296	#define AU8522_RS_STATUS_B0_REG086H 0x086
297	#define AU8522_RS_STATUS_E_REG087H 0x087
298	#define AU8522_DEMODULATION_STATUS_REG088H 0x088
299	#define AU8522_TOREGTRESTATUS_REG0E6H 0x0E6
300	#define AU8522_TSPORT_CONTROL_REG10BH 0x10B
301	#define AU8522_TSTHES_REG10CH 0x10C
302	#define AU8522_FRMREGDFEKEEP_REG301H 0x301
303	#define AU8522_DFE_AVERAGE_REG302H 0x302
304	#define AU8522_FRMREGEQLERRWIN_REG303H 0x303
305	#define AU8522_FRMREGFFEKEEP_REG304H 0x304
306	#define AU8522_FRMREGDFECONTROL1_REG305H 0x305
307	#define AU8522_FRMREGEQLERRLOW_REG306H 0x306
308
309	#define AU8522_REG42EH 0x42E
310	#define AU8522_REG42FH 0x42F
311	#define AU8522_REG430H 0x430
312	#define AU8522_REG431H 0x431
313	#define AU8522_REG432H 0x432
314	#define AU8522_REG433H 0x433
315	#define AU8522_REG434H 0x434
316	#define AU8522_REG435H 0x435
317	#define AU8522_REG436H 0x436
318
319	/* GPIO Registers */
320	#define AU8522_GPIO_CONTROL_REG0E0H 0x0E0
321	#define AU8522_GPIO_STATUS_REG0E1H 0x0E1
322	#define AU8522_GPIO_DATA_REG0E2H 0x0E2
323
324	/* Audio Control Registers */
325	#define AU8522_AUDIOAGC_REG0EEH 0x0EE
326	#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0
327	#define AU8522_AUDIO_MODE_REG0F1H 0x0F1
328	#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2
329	#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3
330	#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4
331	#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7
332	#define AU8522_REG0F9H 0x0F9
333
334	#define AU8522_AUDIOAGC2_REG605H 0x605
335	#define AU8522_AUDIOFREQ_REG606H 0x606
336
337
338	/**************************************************************/
339
a307cfa5 DH	340	/* Format control 1 */
	341
	342	/* VCR Mode 7-6 */
	343	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES 0x80
	344	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO 0x40
	345	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO 0x00
	346	/* Field len 5-4 */
	347	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625 0x20
	348	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 0x10
	349	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO 0x00
	350	/* Line len (us) 3-2 */
	351	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000 0x0b
	352	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 0x08
	353	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556 0x04
	354	/* Subcarrier freq 1-0 */
	355	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO 0x03
	356	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443 0x02
	357	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN 0x01
	358	#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50 0x00
	359
	360	/* Format control 2 */
	361	#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT 0x00
	362	#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC 0x01
f2fd7ce6	363	#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M 0x02
a307cfa5 DH	364
a307cfa5 DH	365
968cf782 DH	366	#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4
	367	#define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4
	368	#define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4
	369	#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4
	370	#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4
	371	#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20
	372	#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2
	373	#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0
	374	#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69
	375	#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68
	376	#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28
	377	/* CH1 AS Y,CH3 AS C */
	378	#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23
	379	/* CH2 AS Y,CH4 AS C */
	380	#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20
	381	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C
	382	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09
	383	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09
	384	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12
	385	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A
	386	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A
	387	#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02
	388
	389	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00
	390	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C
	391	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D
	392	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8
	393	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA
	394	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA
	395	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD
	396	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD
	397	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD
	398	#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD
	399
	400	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80
	401	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80
	402	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80
	403	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40
	404	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40
	405	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40
	406	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00
	407	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01
	408	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01
	409	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04
	410	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01
	411	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03
	412	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09
	413	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01
	414	#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01
	415
	416	/* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */
	417	#define AU8522_TVDEC_CONTRAST_REG00BH_CVBS 0x79
	418	#define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS 0x80
	419	#define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS 0x80
	420	#define AU8522_TVDEC_HUE_H_REG00EH_CVBS 0x00
	421	#define AU8522_TVDEC_HUE_L_REG00FH_CVBS 0x00
	422	#define AU8522_TVDEC_PGA_REG012H_CVBS 0x0F
	423	#define AU8522_TVDEC_COMB_MODE_REG015H_CVBS 0x00
	424	#define AU8522_REG016H_CVBS 0x00
	425	#define AU8522_TVDED_DBG_MODE_REG060H_CVBS 0x00
968cf782 DH	426	#define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS 0x19
	427	#define AU8522_REG0F9H_AUDIO 0x20
	428	#define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS 0xA7
	429	#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS 0x0A
	430	#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS 0x32
	431	#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS 0x19
	432	#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS 0x23
	433	#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS 0x41
	434	#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A
	435	#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32
	436	#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34
301c9f26	437	#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO 0x2a
968cf782	438	#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05
301c9f26	439	#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO 0x15
968cf782 DH	440	#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E
	441	#define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F
	442	#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80
	443	#define AU8522_REG071H_CVBS 0x18
	444	#define AU8522_REG072H_CVBS 0x30
	445	#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS 0xF0
	446	#define AU8522_REG074H_CVBS 0x80
	447	#define AU8522_REG075H_CVBS 0xF0
	448	#define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS 0xFB
	449	#define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS 0x04
	450	#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS 0x00
	451	#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS 0x00
	452	#define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS 0xEE
	453	#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS 0xFE
	454	#define AU8522_TOREGAAGC_REG0E5H_CVBS 0x00
	455	#define AU8522_TVDEC_VBI6A_REG035H_CVBS 0x40
	456
	457	/* Enables Closed captioning */
	458	#define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON 0x21