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Commit | Line | Data |
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27cfc85e AP |
1 | /* |
2 | * Sony CXD2820R demodulator driver | |
3 | * | |
4 | * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | ||
22 | #include "cxd2820r_priv.h" | |
23 | ||
27cfc85e AP |
24 | /* write multiple registers */ |
25 | static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, | |
26 | u8 *val, int len) | |
27 | { | |
28 | int ret; | |
29 | u8 buf[len+1]; | |
30 | struct i2c_msg msg[1] = { | |
31 | { | |
32 | .addr = i2c, | |
33 | .flags = 0, | |
34 | .len = sizeof(buf), | |
35 | .buf = buf, | |
36 | } | |
37 | }; | |
38 | ||
39 | buf[0] = reg; | |
40 | memcpy(&buf[1], val, len); | |
41 | ||
42 | ret = i2c_transfer(priv->i2c, msg, 1); | |
43 | if (ret == 1) { | |
44 | ret = 0; | |
45 | } else { | |
75aeafc9 AP |
46 | dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \ |
47 | "len=%d\n", KBUILD_MODNAME, ret, reg, len); | |
27cfc85e AP |
48 | ret = -EREMOTEIO; |
49 | } | |
50 | return ret; | |
51 | } | |
52 | ||
53 | /* read multiple registers */ | |
54 | static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, | |
55 | u8 *val, int len) | |
56 | { | |
57 | int ret; | |
58 | u8 buf[len]; | |
59 | struct i2c_msg msg[2] = { | |
60 | { | |
61 | .addr = i2c, | |
62 | .flags = 0, | |
63 | .len = 1, | |
64 | .buf = ®, | |
65 | }, { | |
66 | .addr = i2c, | |
67 | .flags = I2C_M_RD, | |
68 | .len = sizeof(buf), | |
69 | .buf = buf, | |
70 | } | |
71 | }; | |
72 | ||
73 | ret = i2c_transfer(priv->i2c, msg, 2); | |
74 | if (ret == 2) { | |
75 | memcpy(val, buf, len); | |
76 | ret = 0; | |
77 | } else { | |
75aeafc9 AP |
78 | dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \ |
79 | "len=%d\n", KBUILD_MODNAME, ret, reg, len); | |
27cfc85e AP |
80 | ret = -EREMOTEIO; |
81 | } | |
82 | ||
83 | return ret; | |
84 | } | |
85 | ||
86 | /* write multiple registers */ | |
9ac51c5e | 87 | int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, |
27cfc85e AP |
88 | int len) |
89 | { | |
90 | int ret; | |
91 | u8 i2c_addr; | |
92 | u8 reg = (reginfo >> 0) & 0xff; | |
93 | u8 bank = (reginfo >> 8) & 0xff; | |
94 | u8 i2c = (reginfo >> 16) & 0x01; | |
95 | ||
96 | /* select I2C */ | |
97 | if (i2c) | |
98 | i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ | |
99 | else | |
100 | i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ | |
101 | ||
102 | /* switch bank if needed */ | |
103 | if (bank != priv->bank[i2c]) { | |
104 | ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); | |
105 | if (ret) | |
106 | return ret; | |
107 | priv->bank[i2c] = bank; | |
108 | } | |
109 | return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len); | |
110 | } | |
111 | ||
112 | /* read multiple registers */ | |
9ac51c5e | 113 | int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, |
27cfc85e AP |
114 | int len) |
115 | { | |
116 | int ret; | |
117 | u8 i2c_addr; | |
118 | u8 reg = (reginfo >> 0) & 0xff; | |
119 | u8 bank = (reginfo >> 8) & 0xff; | |
120 | u8 i2c = (reginfo >> 16) & 0x01; | |
121 | ||
122 | /* select I2C */ | |
123 | if (i2c) | |
124 | i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ | |
125 | else | |
126 | i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ | |
127 | ||
128 | /* switch bank if needed */ | |
129 | if (bank != priv->bank[i2c]) { | |
130 | ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); | |
131 | if (ret) | |
132 | return ret; | |
133 | priv->bank[i2c] = bank; | |
134 | } | |
135 | return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len); | |
136 | } | |
137 | ||
138 | /* write single register */ | |
9ac51c5e | 139 | int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val) |
27cfc85e AP |
140 | { |
141 | return cxd2820r_wr_regs(priv, reg, &val, 1); | |
142 | } | |
143 | ||
144 | /* read single register */ | |
9ac51c5e | 145 | int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val) |
27cfc85e AP |
146 | { |
147 | return cxd2820r_rd_regs(priv, reg, val, 1); | |
148 | } | |
149 | ||
150 | /* write single register with mask */ | |
9ac51c5e | 151 | int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, |
27cfc85e AP |
152 | u8 mask) |
153 | { | |
154 | int ret; | |
155 | u8 tmp; | |
156 | ||
157 | /* no need for read if whole reg is written */ | |
158 | if (mask != 0xff) { | |
159 | ret = cxd2820r_rd_reg(priv, reg, &tmp); | |
160 | if (ret) | |
161 | return ret; | |
162 | ||
163 | val &= mask; | |
164 | tmp &= ~mask; | |
165 | val |= tmp; | |
166 | } | |
167 | ||
168 | return cxd2820r_wr_reg(priv, reg, val); | |
169 | } | |
170 | ||
1e8f31f3 | 171 | int cxd2820r_gpio(struct dvb_frontend *fe, u8 *gpio) |
27cfc85e AP |
172 | { |
173 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
174 | int ret, i; | |
1e8f31f3 | 175 | u8 tmp0, tmp1; |
75aeafc9 AP |
176 | |
177 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, | |
178 | fe->dtv_property_cache.delivery_system); | |
27cfc85e | 179 | |
27cfc85e AP |
180 | /* update GPIOs only when needed */ |
181 | if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio))) | |
182 | return 0; | |
183 | ||
184 | tmp0 = 0x00; | |
185 | tmp1 = 0x00; | |
186 | for (i = 0; i < sizeof(priv->gpio); i++) { | |
187 | /* enable / disable */ | |
188 | if (gpio[i] & CXD2820R_GPIO_E) | |
189 | tmp0 |= (2 << 6) >> (2 * i); | |
190 | else | |
191 | tmp0 |= (1 << 6) >> (2 * i); | |
192 | ||
193 | /* input / output */ | |
194 | if (gpio[i] & CXD2820R_GPIO_I) | |
195 | tmp1 |= (1 << (3 + i)); | |
196 | else | |
197 | tmp1 |= (0 << (3 + i)); | |
198 | ||
199 | /* high / low */ | |
200 | if (gpio[i] & CXD2820R_GPIO_H) | |
201 | tmp1 |= (1 << (0 + i)); | |
202 | else | |
203 | tmp1 |= (0 << (0 + i)); | |
204 | ||
75aeafc9 AP |
205 | dev_dbg(&priv->i2c->dev, "%s: gpio i=%d %02x %02x\n", __func__, |
206 | i, tmp0, tmp1); | |
27cfc85e AP |
207 | } |
208 | ||
75aeafc9 AP |
209 | dev_dbg(&priv->i2c->dev, "%s: wr gpio=%02x %02x\n", __func__, tmp0, |
210 | tmp1); | |
27cfc85e AP |
211 | |
212 | /* write bits [7:2] */ | |
213 | ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc); | |
214 | if (ret) | |
215 | goto error; | |
216 | ||
217 | /* write bits [5:0] */ | |
218 | ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f); | |
219 | if (ret) | |
220 | goto error; | |
221 | ||
222 | memcpy(priv->gpio, gpio, sizeof(priv->gpio)); | |
223 | ||
224 | return ret; | |
225 | error: | |
75aeafc9 | 226 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
227 | return ret; |
228 | } | |
229 | ||
27cfc85e | 230 | /* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */ |
9ac51c5e | 231 | u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor) |
27cfc85e AP |
232 | { |
233 | return div_u64(dividend + (divisor / 2), divisor); | |
234 | } | |
235 | ||
f311f68a | 236 | static int cxd2820r_set_frontend(struct dvb_frontend *fe) |
27cfc85e | 237 | { |
75aeafc9 | 238 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e AP |
239 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
240 | int ret; | |
27cfc85e | 241 | |
75aeafc9 AP |
242 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
243 | fe->dtv_property_cache.delivery_system); | |
244 | ||
14c03862 MA |
245 | switch (c->delivery_system) { |
246 | case SYS_DVBT: | |
247 | ret = cxd2820r_init_t(fe); | |
248 | if (ret < 0) | |
249 | goto err; | |
f311f68a | 250 | ret = cxd2820r_set_frontend_t(fe); |
14c03862 MA |
251 | if (ret < 0) |
252 | goto err; | |
253 | break; | |
254 | case SYS_DVBT2: | |
255 | ret = cxd2820r_init_t(fe); | |
256 | if (ret < 0) | |
257 | goto err; | |
f311f68a | 258 | ret = cxd2820r_set_frontend_t2(fe); |
14c03862 MA |
259 | if (ret < 0) |
260 | goto err; | |
261 | break; | |
f311f68a | 262 | case SYS_DVBC_ANNEX_A: |
14c03862 MA |
263 | ret = cxd2820r_init_c(fe); |
264 | if (ret < 0) | |
265 | goto err; | |
f311f68a | 266 | ret = cxd2820r_set_frontend_c(fe); |
14c03862 MA |
267 | if (ret < 0) |
268 | goto err; | |
269 | break; | |
270 | default: | |
75aeafc9 AP |
271 | dev_dbg(&priv->i2c->dev, "%s: error state=%d\n", __func__, |
272 | fe->dtv_property_cache.delivery_system); | |
14c03862 MA |
273 | ret = -EINVAL; |
274 | break; | |
27cfc85e | 275 | } |
14c03862 | 276 | err: |
27cfc85e AP |
277 | return ret; |
278 | } | |
27cfc85e AP |
279 | static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status) |
280 | { | |
75aeafc9 | 281 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 282 | int ret; |
27cfc85e | 283 | |
75aeafc9 AP |
284 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
285 | fe->dtv_property_cache.delivery_system); | |
286 | ||
14c03862 MA |
287 | switch (fe->dtv_property_cache.delivery_system) { |
288 | case SYS_DVBT: | |
289 | ret = cxd2820r_read_status_t(fe, status); | |
290 | break; | |
291 | case SYS_DVBT2: | |
292 | ret = cxd2820r_read_status_t2(fe, status); | |
293 | break; | |
f311f68a | 294 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 295 | ret = cxd2820r_read_status_c(fe, status); |
14c03862 MA |
296 | break; |
297 | default: | |
298 | ret = -EINVAL; | |
299 | break; | |
27cfc85e | 300 | } |
27cfc85e AP |
301 | return ret; |
302 | } | |
303 | ||
7c61d80a | 304 | static int cxd2820r_get_frontend(struct dvb_frontend *fe) |
27cfc85e | 305 | { |
3b6a567a | 306 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 307 | int ret; |
27cfc85e | 308 | |
75aeafc9 AP |
309 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
310 | fe->dtv_property_cache.delivery_system); | |
3b6a567a AP |
311 | |
312 | if (priv->delivery_system == SYS_UNDEFINED) | |
313 | return 0; | |
314 | ||
14c03862 MA |
315 | switch (fe->dtv_property_cache.delivery_system) { |
316 | case SYS_DVBT: | |
f311f68a | 317 | ret = cxd2820r_get_frontend_t(fe); |
14c03862 MA |
318 | break; |
319 | case SYS_DVBT2: | |
f311f68a | 320 | ret = cxd2820r_get_frontend_t2(fe); |
14c03862 | 321 | break; |
f311f68a MCC |
322 | case SYS_DVBC_ANNEX_A: |
323 | ret = cxd2820r_get_frontend_c(fe); | |
14c03862 MA |
324 | break; |
325 | default: | |
326 | ret = -EINVAL; | |
327 | break; | |
27cfc85e | 328 | } |
27cfc85e AP |
329 | return ret; |
330 | } | |
331 | ||
332 | static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber) | |
333 | { | |
75aeafc9 | 334 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 335 | int ret; |
27cfc85e | 336 | |
75aeafc9 AP |
337 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
338 | fe->dtv_property_cache.delivery_system); | |
339 | ||
14c03862 MA |
340 | switch (fe->dtv_property_cache.delivery_system) { |
341 | case SYS_DVBT: | |
342 | ret = cxd2820r_read_ber_t(fe, ber); | |
343 | break; | |
344 | case SYS_DVBT2: | |
345 | ret = cxd2820r_read_ber_t2(fe, ber); | |
346 | break; | |
f311f68a | 347 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 348 | ret = cxd2820r_read_ber_c(fe, ber); |
14c03862 MA |
349 | break; |
350 | default: | |
351 | ret = -EINVAL; | |
352 | break; | |
27cfc85e | 353 | } |
27cfc85e AP |
354 | return ret; |
355 | } | |
356 | ||
357 | static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
358 | { | |
75aeafc9 | 359 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 360 | int ret; |
27cfc85e | 361 | |
75aeafc9 AP |
362 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
363 | fe->dtv_property_cache.delivery_system); | |
364 | ||
14c03862 MA |
365 | switch (fe->dtv_property_cache.delivery_system) { |
366 | case SYS_DVBT: | |
367 | ret = cxd2820r_read_signal_strength_t(fe, strength); | |
368 | break; | |
369 | case SYS_DVBT2: | |
370 | ret = cxd2820r_read_signal_strength_t2(fe, strength); | |
371 | break; | |
f311f68a | 372 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 373 | ret = cxd2820r_read_signal_strength_c(fe, strength); |
14c03862 MA |
374 | break; |
375 | default: | |
376 | ret = -EINVAL; | |
377 | break; | |
27cfc85e | 378 | } |
27cfc85e AP |
379 | return ret; |
380 | } | |
381 | ||
382 | static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr) | |
383 | { | |
75aeafc9 | 384 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 385 | int ret; |
27cfc85e | 386 | |
75aeafc9 AP |
387 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
388 | fe->dtv_property_cache.delivery_system); | |
389 | ||
14c03862 MA |
390 | switch (fe->dtv_property_cache.delivery_system) { |
391 | case SYS_DVBT: | |
392 | ret = cxd2820r_read_snr_t(fe, snr); | |
393 | break; | |
394 | case SYS_DVBT2: | |
395 | ret = cxd2820r_read_snr_t2(fe, snr); | |
396 | break; | |
f311f68a | 397 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 398 | ret = cxd2820r_read_snr_c(fe, snr); |
14c03862 MA |
399 | break; |
400 | default: | |
401 | ret = -EINVAL; | |
402 | break; | |
27cfc85e | 403 | } |
27cfc85e AP |
404 | return ret; |
405 | } | |
406 | ||
407 | static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
408 | { | |
75aeafc9 | 409 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 410 | int ret; |
27cfc85e | 411 | |
75aeafc9 AP |
412 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
413 | fe->dtv_property_cache.delivery_system); | |
414 | ||
14c03862 MA |
415 | switch (fe->dtv_property_cache.delivery_system) { |
416 | case SYS_DVBT: | |
417 | ret = cxd2820r_read_ucblocks_t(fe, ucblocks); | |
418 | break; | |
419 | case SYS_DVBT2: | |
420 | ret = cxd2820r_read_ucblocks_t2(fe, ucblocks); | |
421 | break; | |
f311f68a | 422 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 423 | ret = cxd2820r_read_ucblocks_c(fe, ucblocks); |
14c03862 MA |
424 | break; |
425 | default: | |
426 | ret = -EINVAL; | |
427 | break; | |
27cfc85e | 428 | } |
27cfc85e AP |
429 | return ret; |
430 | } | |
431 | ||
432 | static int cxd2820r_init(struct dvb_frontend *fe) | |
433 | { | |
14c03862 | 434 | return 0; |
27cfc85e AP |
435 | } |
436 | ||
437 | static int cxd2820r_sleep(struct dvb_frontend *fe) | |
438 | { | |
75aeafc9 | 439 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 440 | int ret; |
27cfc85e | 441 | |
75aeafc9 AP |
442 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
443 | fe->dtv_property_cache.delivery_system); | |
444 | ||
14c03862 MA |
445 | switch (fe->dtv_property_cache.delivery_system) { |
446 | case SYS_DVBT: | |
447 | ret = cxd2820r_sleep_t(fe); | |
448 | break; | |
449 | case SYS_DVBT2: | |
450 | ret = cxd2820r_sleep_t2(fe); | |
451 | break; | |
f311f68a | 452 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 453 | ret = cxd2820r_sleep_c(fe); |
14c03862 MA |
454 | break; |
455 | default: | |
456 | ret = -EINVAL; | |
457 | break; | |
27cfc85e | 458 | } |
27cfc85e AP |
459 | return ret; |
460 | } | |
461 | ||
462 | static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, | |
14c03862 | 463 | struct dvb_frontend_tune_settings *s) |
27cfc85e | 464 | { |
75aeafc9 | 465 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
e47b78f0 | 466 | int ret; |
27cfc85e | 467 | |
75aeafc9 AP |
468 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
469 | fe->dtv_property_cache.delivery_system); | |
470 | ||
14c03862 MA |
471 | switch (fe->dtv_property_cache.delivery_system) { |
472 | case SYS_DVBT: | |
473 | ret = cxd2820r_get_tune_settings_t(fe, s); | |
474 | break; | |
475 | case SYS_DVBT2: | |
476 | ret = cxd2820r_get_tune_settings_t2(fe, s); | |
477 | break; | |
f311f68a | 478 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 479 | ret = cxd2820r_get_tune_settings_c(fe, s); |
14c03862 MA |
480 | break; |
481 | default: | |
482 | ret = -EINVAL; | |
483 | break; | |
27cfc85e | 484 | } |
27cfc85e AP |
485 | return ret; |
486 | } | |
487 | ||
41da5320 | 488 | static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe) |
e47b78f0 AP |
489 | { |
490 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
491 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
492 | int ret, i; | |
493 | fe_status_t status = 0; | |
75aeafc9 AP |
494 | |
495 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, | |
496 | fe->dtv_property_cache.delivery_system); | |
e47b78f0 AP |
497 | |
498 | /* switch between DVB-T and DVB-T2 when tune fails */ | |
d04ca8df | 499 | if (priv->last_tune_failed) { |
72565224 AP |
500 | if (priv->delivery_system == SYS_DVBT) { |
501 | ret = cxd2820r_sleep_t(fe); | |
502 | if (ret) | |
503 | goto error; | |
504 | ||
e47b78f0 | 505 | c->delivery_system = SYS_DVBT2; |
72565224 AP |
506 | } else if (priv->delivery_system == SYS_DVBT2) { |
507 | ret = cxd2820r_sleep_t2(fe); | |
508 | if (ret) | |
509 | goto error; | |
510 | ||
e47b78f0 | 511 | c->delivery_system = SYS_DVBT; |
72565224 | 512 | } |
e47b78f0 AP |
513 | } |
514 | ||
515 | /* set frontend */ | |
f311f68a | 516 | ret = cxd2820r_set_frontend(fe); |
e47b78f0 AP |
517 | if (ret) |
518 | goto error; | |
519 | ||
520 | ||
521 | /* frontend lock wait loop count */ | |
522 | switch (priv->delivery_system) { | |
523 | case SYS_DVBT: | |
1f649729 | 524 | case SYS_DVBC_ANNEX_A: |
e47b78f0 AP |
525 | i = 20; |
526 | break; | |
527 | case SYS_DVBT2: | |
528 | i = 40; | |
529 | break; | |
530 | case SYS_UNDEFINED: | |
531 | default: | |
532 | i = 0; | |
533 | break; | |
534 | } | |
535 | ||
536 | /* wait frontend lock */ | |
537 | for (; i > 0; i--) { | |
75aeafc9 | 538 | dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); |
e47b78f0 AP |
539 | msleep(50); |
540 | ret = cxd2820r_read_status(fe, &status); | |
541 | if (ret) | |
542 | goto error; | |
543 | ||
b115f400 | 544 | if (status & FE_HAS_LOCK) |
e47b78f0 AP |
545 | break; |
546 | } | |
547 | ||
548 | /* check if we have a valid signal */ | |
b115f400 | 549 | if (status & FE_HAS_LOCK) { |
e47b78f0 AP |
550 | priv->last_tune_failed = 0; |
551 | return DVBFE_ALGO_SEARCH_SUCCESS; | |
552 | } else { | |
553 | priv->last_tune_failed = 1; | |
554 | return DVBFE_ALGO_SEARCH_AGAIN; | |
555 | } | |
556 | ||
557 | error: | |
75aeafc9 | 558 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
e47b78f0 AP |
559 | return DVBFE_ALGO_SEARCH_ERROR; |
560 | } | |
561 | ||
562 | static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe) | |
563 | { | |
564 | return DVBFE_ALGO_CUSTOM; | |
565 | } | |
566 | ||
27cfc85e AP |
567 | static void cxd2820r_release(struct dvb_frontend *fe) |
568 | { | |
569 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
a36a66d7 | 570 | int uninitialized_var(ret); /* silence compiler warning */ |
75aeafc9 AP |
571 | |
572 | dev_dbg(&priv->i2c->dev, "%s\n", __func__); | |
27cfc85e | 573 | |
1e8f31f3 AP |
574 | #ifdef CONFIG_GPIOLIB |
575 | /* remove GPIOs */ | |
576 | if (priv->gpio_chip.label) { | |
577 | ret = gpiochip_remove(&priv->gpio_chip); | |
578 | if (ret) | |
579 | dev_err(&priv->i2c->dev, "%s: gpiochip_remove() " \ | |
580 | "failed=%d\n", KBUILD_MODNAME, ret); | |
581 | } | |
582 | #endif | |
14c03862 | 583 | kfree(priv); |
27cfc85e AP |
584 | return; |
585 | } | |
586 | ||
0db4bf42 | 587 | static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) |
27cfc85e AP |
588 | { |
589 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
75aeafc9 AP |
590 | |
591 | dev_dbg(&priv->i2c->dev, "%s: %d\n", __func__, enable); | |
0db4bf42 SK |
592 | |
593 | /* Bit 0 of reg 0xdb in bank 0x00 controls I2C repeater */ | |
594 | return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1); | |
27cfc85e | 595 | } |
27cfc85e | 596 | |
1e8f31f3 AP |
597 | #ifdef CONFIG_GPIOLIB |
598 | static int cxd2820r_gpio_direction_output(struct gpio_chip *chip, unsigned nr, | |
599 | int val) | |
600 | { | |
601 | struct cxd2820r_priv *priv = | |
602 | container_of(chip, struct cxd2820r_priv, gpio_chip); | |
603 | u8 gpio[GPIO_COUNT]; | |
604 | ||
605 | dev_dbg(&priv->i2c->dev, "%s: nr=%d val=%d\n", __func__, nr, val); | |
606 | ||
607 | memcpy(gpio, priv->gpio, sizeof(gpio)); | |
608 | gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2); | |
609 | ||
610 | return cxd2820r_gpio(&priv->fe, gpio); | |
611 | } | |
612 | ||
613 | static void cxd2820r_gpio_set(struct gpio_chip *chip, unsigned nr, int val) | |
614 | { | |
615 | struct cxd2820r_priv *priv = | |
616 | container_of(chip, struct cxd2820r_priv, gpio_chip); | |
617 | u8 gpio[GPIO_COUNT]; | |
618 | ||
619 | dev_dbg(&priv->i2c->dev, "%s: nr=%d val=%d\n", __func__, nr, val); | |
620 | ||
621 | memcpy(gpio, priv->gpio, sizeof(gpio)); | |
622 | gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2); | |
623 | ||
624 | (void) cxd2820r_gpio(&priv->fe, gpio); | |
625 | ||
626 | return; | |
627 | } | |
628 | ||
629 | static int cxd2820r_gpio_get(struct gpio_chip *chip, unsigned nr) | |
630 | { | |
631 | struct cxd2820r_priv *priv = | |
632 | container_of(chip, struct cxd2820r_priv, gpio_chip); | |
633 | ||
634 | dev_dbg(&priv->i2c->dev, "%s: nr=%d\n", __func__, nr); | |
635 | ||
636 | return (priv->gpio[nr] >> 2) & 0x01; | |
637 | } | |
638 | #endif | |
639 | ||
14c03862 | 640 | static const struct dvb_frontend_ops cxd2820r_ops = { |
f311f68a | 641 | .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A }, |
14c03862 MA |
642 | /* default: DVB-T/T2 */ |
643 | .info = { | |
9bf31efa | 644 | .name = "Sony CXD2820R", |
14c03862 MA |
645 | |
646 | .caps = FE_CAN_FEC_1_2 | | |
647 | FE_CAN_FEC_2_3 | | |
648 | FE_CAN_FEC_3_4 | | |
649 | FE_CAN_FEC_5_6 | | |
650 | FE_CAN_FEC_7_8 | | |
651 | FE_CAN_FEC_AUTO | | |
652 | FE_CAN_QPSK | | |
653 | FE_CAN_QAM_16 | | |
9bf31efa | 654 | FE_CAN_QAM_32 | |
14c03862 | 655 | FE_CAN_QAM_64 | |
9bf31efa | 656 | FE_CAN_QAM_128 | |
14c03862 MA |
657 | FE_CAN_QAM_256 | |
658 | FE_CAN_QAM_AUTO | | |
659 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
660 | FE_CAN_GUARD_INTERVAL_AUTO | | |
661 | FE_CAN_HIERARCHY_AUTO | | |
662 | FE_CAN_MUTE_TS | | |
4a74772e EP |
663 | FE_CAN_2G_MODULATION | |
664 | FE_CAN_MULTISTREAM | |
14c03862 | 665 | }, |
27cfc85e | 666 | |
14c03862 MA |
667 | .release = cxd2820r_release, |
668 | .init = cxd2820r_init, | |
669 | .sleep = cxd2820r_sleep, | |
27cfc85e | 670 | |
14c03862 MA |
671 | .get_tune_settings = cxd2820r_get_tune_settings, |
672 | .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl, | |
27cfc85e | 673 | |
f311f68a | 674 | .get_frontend = cxd2820r_get_frontend, |
27cfc85e | 675 | |
14c03862 MA |
676 | .get_frontend_algo = cxd2820r_get_frontend_algo, |
677 | .search = cxd2820r_search, | |
27cfc85e | 678 | |
14c03862 MA |
679 | .read_status = cxd2820r_read_status, |
680 | .read_snr = cxd2820r_read_snr, | |
681 | .read_ber = cxd2820r_read_ber, | |
682 | .read_ucblocks = cxd2820r_read_ucblocks, | |
683 | .read_signal_strength = cxd2820r_read_signal_strength, | |
14c03862 | 684 | }; |
27cfc85e | 685 | |
14c03862 | 686 | struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg, |
1e8f31f3 AP |
687 | struct i2c_adapter *i2c, int *gpio_chip_base |
688 | ) | |
14c03862 | 689 | { |
1e8f31f3 | 690 | struct cxd2820r_priv *priv; |
14c03862 | 691 | int ret; |
44e0d7de | 692 | u8 tmp; |
14c03862 | 693 | |
a36a66d7 | 694 | priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL); |
1e8f31f3 AP |
695 | if (!priv) { |
696 | ret = -ENOMEM; | |
697 | dev_err(&i2c->dev, "%s: kzalloc() failed\n", | |
698 | KBUILD_MODNAME); | |
14c03862 | 699 | goto error; |
1e8f31f3 | 700 | } |
27cfc85e | 701 | |
14c03862 | 702 | priv->i2c = i2c; |
a36a66d7 AP |
703 | memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config)); |
704 | memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof(struct dvb_frontend_ops)); | |
705 | priv->fe.demodulator_priv = priv; | |
14c03862 MA |
706 | |
707 | priv->bank[0] = priv->bank[1] = 0xff; | |
708 | ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp); | |
75aeafc9 | 709 | dev_dbg(&priv->i2c->dev, "%s: chip id=%02x\n", __func__, tmp); |
14c03862 MA |
710 | if (ret || tmp != 0xe1) |
711 | goto error; | |
712 | ||
1e8f31f3 | 713 | if (gpio_chip_base) { |
a36a66d7 AP |
714 | #ifdef CONFIG_GPIOLIB |
715 | /* add GPIOs */ | |
1e8f31f3 AP |
716 | priv->gpio_chip.label = KBUILD_MODNAME; |
717 | priv->gpio_chip.dev = &priv->i2c->dev; | |
718 | priv->gpio_chip.owner = THIS_MODULE; | |
719 | priv->gpio_chip.direction_output = | |
720 | cxd2820r_gpio_direction_output; | |
721 | priv->gpio_chip.set = cxd2820r_gpio_set; | |
722 | priv->gpio_chip.get = cxd2820r_gpio_get; | |
723 | priv->gpio_chip.base = -1; /* dynamic allocation */ | |
724 | priv->gpio_chip.ngpio = GPIO_COUNT; | |
725 | priv->gpio_chip.can_sleep = 1; | |
726 | ret = gpiochip_add(&priv->gpio_chip); | |
727 | if (ret) | |
728 | goto error; | |
729 | ||
730 | dev_dbg(&priv->i2c->dev, "%s: gpio_chip.base=%d\n", __func__, | |
731 | priv->gpio_chip.base); | |
732 | ||
733 | *gpio_chip_base = priv->gpio_chip.base; | |
a36a66d7 AP |
734 | #else |
735 | /* | |
736 | * Use static GPIO configuration if GPIOLIB is undefined. | |
737 | * This is fallback condition. | |
738 | */ | |
44e0d7de | 739 | u8 gpio[GPIO_COUNT]; |
a36a66d7 AP |
740 | gpio[0] = (*gpio_chip_base >> 0) & 0x07; |
741 | gpio[1] = (*gpio_chip_base >> 3) & 0x07; | |
742 | gpio[2] = 0; | |
743 | ret = cxd2820r_gpio(&priv->fe, gpio); | |
744 | if (ret) | |
745 | goto error; | |
1e8f31f3 | 746 | #endif |
a36a66d7 | 747 | } |
1e8f31f3 | 748 | |
14c03862 | 749 | return &priv->fe; |
27cfc85e | 750 | error: |
1e8f31f3 | 751 | dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
752 | kfree(priv); |
753 | return NULL; | |
754 | } | |
755 | EXPORT_SYMBOL(cxd2820r_attach); | |
756 | ||
27cfc85e AP |
757 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); |
758 | MODULE_DESCRIPTION("Sony CXD2820R demodulator driver"); | |
759 | MODULE_LICENSE("GPL"); |