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[media] MAINTAINERS: Add a maintainer for netup_unidvb, cxd2841er, horus3a, ascot2e
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb-frontends / cxd2841er.c
CommitLineData
a6dc60ff
KS		 1/*
2 * cxd2841er.c
3 *
83808c23
AO		 4 * Sony digital demodulator driver for
5 * CXD2441ER - DVB-S/S2/T/T2/C/C2
6 * CXD2454ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
a6dc60ff
KS		 7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
d13a7b67
MCC		 38#define MAX_WRITE_REGSIZE 16
39
a6dc60ff
KS		 40enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46};
47
48struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
83808c23 56 enum cxd2841er_xtal xtal;
a6dc60ff
KS		 57};
58
59static const struct cxd2841er_cnr_data s_cn_data[] = {
60 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
61 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
62 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
63 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
64 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
65 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
66 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
67 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
68 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
69 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
70 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
71 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
72 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
73 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
74 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
75 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
76 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
77 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
78 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
79 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
80 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
81 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
82 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
83 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
84 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
85 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
86 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
87 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
88 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
89 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
90 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
91 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
92 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
93 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
94 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
95 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
96 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
97 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
98 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
99 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
100 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
101 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
102 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
103 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
104 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
105 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
106 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
107 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
108 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
109 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
110 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
111 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
112 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
113 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
114 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
115 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
116 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
117 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
118 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
119 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
120 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
121 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
122 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
123 { 0x0015, 19900 }, { 0x0014, 20000 },
124};
125
126static const struct cxd2841er_cnr_data s2_cn_data[] = {
127 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
128 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
129 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
130 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
131 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
132 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
133 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
134 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
135 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
136 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
137 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
138 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
139 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
140 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
141 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
142 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
143 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
144 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
145 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
146 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
147 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
148 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
149 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
150 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
151 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
152 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
153 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
154 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
155 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
156 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
157 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
158 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
159 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
160 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
161 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
162 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
163 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
164 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
165 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
166 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
167 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
168 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
169 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
170 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
171 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
172 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
173 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
174 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
175 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
176 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
177 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
178 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
179 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
180 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
181 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
182 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
183 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
184 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
185 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
186 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
187 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
188 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
189 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
190 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
191};
192
193#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
83808c23
AO		 194#define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
195 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
196 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
a6dc60ff
KS		 197
198static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
199 u8 addr, u8 reg, u8 write,
200 const u8 *data, u32 len)
201{
202 dev_dbg(&priv->i2c->dev,
203 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
204 (write == 0 ? "read" : "write"), addr, reg, len);
205 print_hex_dump_bytes("cxd2841er: I2C data: ",
206 DUMP_PREFIX_OFFSET, data, len);
207}
208
209static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
210 u8 addr, u8 reg, const u8 *data, u32 len)
211{
212 int ret;
d13a7b67 213 u8 buf[MAX_WRITE_REGSIZE + 1];
a6dc60ff
KS		 214 u8 i2c_addr = (addr == I2C_SLVX ?
215 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
216 struct i2c_msg msg[1] = {
217 {
218 .addr = i2c_addr,
219 .flags = 0,
d13a7b67 220 .len = len + 1,
a6dc60ff
KS		 221 .buf = buf,
222 }
223 };
224
d13a7b67 225 if (len + 1 >= sizeof(buf)) {
83808c23 226 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
d13a7b67
MCC		 227 reg, len + 1);
228 return -E2BIG;
229 }
230
a6dc60ff
KS		 231 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
232 buf[0] = reg;
233 memcpy(&buf[1], data, len);
234
235 ret = i2c_transfer(priv->i2c, msg, 1);
236 if (ret >= 0 && ret != 1)
237 ret = -EIO;
238 if (ret < 0) {
239 dev_warn(&priv->i2c->dev,
240 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
241 KBUILD_MODNAME, ret, i2c_addr, reg, len);
242 return ret;
243 }
244 return 0;
245}
246
247static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
248 u8 addr, u8 reg, u8 val)
249{
250 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
251}
252
253static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
254 u8 addr, u8 reg, u8 *val, u32 len)
255{
256 int ret;
257 u8 i2c_addr = (addr == I2C_SLVX ?
258 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
259 struct i2c_msg msg[2] = {
260 {
261 .addr = i2c_addr,
262 .flags = 0,
263 .len = 1,
264 .buf = &reg,
265 }, {
266 .addr = i2c_addr,
267 .flags = I2C_M_RD,
268 .len = len,
269 .buf = val,
270 }
271 };
272
273 ret = i2c_transfer(priv->i2c, &msg[0], 1);
274 if (ret >= 0 && ret != 1)
275 ret = -EIO;
276 if (ret < 0) {
277 dev_warn(&priv->i2c->dev,
278 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
279 KBUILD_MODNAME, ret, i2c_addr, reg);
280 return ret;
281 }
282 ret = i2c_transfer(priv->i2c, &msg[1], 1);
283 if (ret >= 0 && ret != 1)
284 ret = -EIO;
285 if (ret < 0) {
286 dev_warn(&priv->i2c->dev,
287 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
288 KBUILD_MODNAME, ret, i2c_addr, reg);
289 return ret;
290 }
291 return 0;
292}
293
294static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
295 u8 addr, u8 reg, u8 *val)
296{
297 return cxd2841er_read_regs(priv, addr, reg, val, 1);
298}
299
300static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
301 u8 addr, u8 reg, u8 data, u8 mask)
302{
303 int res;
304 u8 rdata;
305
306 if (mask != 0xff) {
307 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
308 if (res)
309 return res;
310 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
311 }
312 return cxd2841er_write_reg(priv, addr, reg, data);
313}
314
315static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
316 u32 symbol_rate)
317{
318 u32 reg_value = 0;
319 u8 data[3] = {0, 0, 0};
320
321 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
322 /*
323 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
324 * = ((symbolRateKSps * 2^14) + 500) / 1000
325 * = ((symbolRateKSps * 16384) + 500) / 1000
326 */
327 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
328 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
329 dev_err(&priv->i2c->dev,
330 "%s(): reg_value is out of range\n", __func__);
331 return -EINVAL;
332 }
333 data[0] = (u8)((reg_value >> 16) & 0x0F);
334 data[1] = (u8)((reg_value >> 8) & 0xFF);
335 data[2] = (u8)(reg_value & 0xFF);
336 /* Set SLV-T Bank : 0xAE */
337 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
338 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
339 return 0;
340}
341
342static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
343 u8 system);
344
345static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
346 u8 system, u32 symbol_rate)
347{
348 int ret;
349 u8 data[4] = { 0, 0, 0, 0 };
350
351 if (priv->state != STATE_SLEEP_S) {
352 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
353 __func__, (int)priv->state);
354 return -EINVAL;
355 }
356 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
357 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
358 /* Set demod mode */
359 if (system == SYS_DVBS) {
360 data[0] = 0x0A;
361 } else if (system == SYS_DVBS2) {
362 data[0] = 0x0B;
363 } else {
364 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
365 __func__, system);
366 return -EINVAL;
367 }
368 /* Set SLV-X Bank : 0x00 */
369 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
370 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
371 /* DVB-S/S2 */
372 data[0] = 0x00;
373 /* Set SLV-T Bank : 0x00 */
374 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
375 /* Enable S/S2 auto detection 1 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
377 /* Set SLV-T Bank : 0xAE */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
379 /* Enable S/S2 auto detection 2 */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
381 /* Set SLV-T Bank : 0x00 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
383 /* Enable demod clock */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
385 /* Enable ADC clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
387 /* Enable ADC 1 */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
389 /* Enable ADC 2 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
391 /* Set SLV-X Bank : 0x00 */
392 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
393 /* Enable ADC 3 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
395 /* Set SLV-T Bank : 0xA3 */
396 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
397 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
398 data[0] = 0x07;
399 data[1] = 0x3B;
400 data[2] = 0x08;
401 data[3] = 0xC5;
402 /* Set SLV-T Bank : 0xAB */
403 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
404 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
405 data[0] = 0x05;
406 data[1] = 0x80;
407 data[2] = 0x0A;
408 data[3] = 0x80;
409 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
410 data[0] = 0x0C;
411 data[1] = 0xCC;
412 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
413 /* Set demod parameter */
414 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
415 if (ret != 0)
416 return ret;
417 /* Set SLV-T Bank : 0x00 */
418 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
419 /* disable Hi-Z setting 1 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
421 /* disable Hi-Z setting 2 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
423 priv->state = STATE_ACTIVE_S;
424 return 0;
425}
426
427static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
428 u32 bandwidth);
429
430static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
431 u32 bandwidth);
432
433static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
434 u32 bandwidth);
435
436static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
437 struct dtv_frontend_properties *p)
438{
439 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
440 if (priv->state != STATE_ACTIVE_S &&
441 priv->state != STATE_ACTIVE_TC) {
442 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
443 __func__, priv->state);
444 return -EINVAL;
445 }
446 /* Set SLV-T Bank : 0x00 */
447 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
448 /* disable TS output */
449 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
450 if (priv->state == STATE_ACTIVE_S)
451 return cxd2841er_dvbs2_set_symbol_rate(
452 priv, p->symbol_rate / 1000);
453 else if (priv->state == STATE_ACTIVE_TC) {
454 switch (priv->system) {
455 case SYS_DVBT:
456 return cxd2841er_sleep_tc_to_active_t_band(
457 priv, p->bandwidth_hz);
458 case SYS_DVBT2:
459 return cxd2841er_sleep_tc_to_active_t2_band(
460 priv, p->bandwidth_hz);
461 case SYS_DVBC_ANNEX_A:
462 return cxd2841er_sleep_tc_to_active_c_band(
463 priv, 8000000);
464 }
465 }
466 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
467 __func__, priv->system);
468 return -EINVAL;
469}
470
471static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
472{
473 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
474 if (priv->state != STATE_ACTIVE_S) {
475 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
476 __func__, priv->state);
477 return -EINVAL;
478 }
479 /* Set SLV-T Bank : 0x00 */
480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
481 /* disable TS output */
482 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
483 /* enable Hi-Z setting 1 */
484 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
485 /* enable Hi-Z setting 2 */
486 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
487 /* Set SLV-X Bank : 0x00 */
488 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
489 /* disable ADC 1 */
490 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
491 /* Set SLV-T Bank : 0x00 */
492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
493 /* disable ADC clock */
494 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
495 /* disable ADC 2 */
496 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
497 /* disable ADC 3 */
498 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
499 /* SADC Bias ON */
500 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
501 /* disable demod clock */
502 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
503 /* Set SLV-T Bank : 0xAE */
504 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
505 /* disable S/S2 auto detection1 */
506 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
507 /* Set SLV-T Bank : 0x00 */
508 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
509 /* disable S/S2 auto detection2 */
510 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
511 priv->state = STATE_SLEEP_S;
512 return 0;
513}
514
515static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
516{
517 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
518 if (priv->state != STATE_SLEEP_S) {
519 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
520 __func__, priv->state);
521 return -EINVAL;
522 }
523 /* Set SLV-T Bank : 0x00 */
524 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
525 /* Disable DSQOUT */
526 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
527 /* Disable DSQIN */
528 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
529 /* Set SLV-X Bank : 0x00 */
530 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
531 /* Disable oscillator */
532 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
533 /* Set demod mode */
534 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
535 priv->state = STATE_SHUTDOWN;
536 return 0;
537}
538
539static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
540{
541 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
542 if (priv->state != STATE_SLEEP_TC) {
543 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
544 __func__, priv->state);
545 return -EINVAL;
546 }
547 /* Set SLV-X Bank : 0x00 */
548 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
549 /* Disable oscillator */
550 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
551 /* Set demod mode */
552 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
553 priv->state = STATE_SHUTDOWN;
554 return 0;
555}
556
557static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
558{
559 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
560 if (priv->state != STATE_ACTIVE_TC) {
561 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
562 __func__, priv->state);
563 return -EINVAL;
564 }
565 /* Set SLV-T Bank : 0x00 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
567 /* disable TS output */
568 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
569 /* enable Hi-Z setting 1 */
570 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
571 /* enable Hi-Z setting 2 */
572 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
573 /* Set SLV-X Bank : 0x00 */
574 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
575 /* disable ADC 1 */
576 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
577 /* Set SLV-T Bank : 0x00 */
578 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
579 /* Disable ADC 2 */
580 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
581 /* Disable ADC 3 */
582 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
583 /* Disable ADC clock */
584 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
585 /* Disable RF level monitor */
586 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
587 /* Disable demod clock */
588 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
589 priv->state = STATE_SLEEP_TC;
590 return 0;
591}
592
593static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
594{
595 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
596 if (priv->state != STATE_ACTIVE_TC) {
597 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
598 __func__, priv->state);
599 return -EINVAL;
600 }
601 /* Set SLV-T Bank : 0x00 */
602 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
603 /* disable TS output */
604 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
605 /* enable Hi-Z setting 1 */
606 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
607 /* enable Hi-Z setting 2 */
608 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
609 /* Cancel DVB-T2 setting */
610 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
611 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
612 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
613 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
614 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
615 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
616 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
617 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
618 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
619 /* Set SLV-X Bank : 0x00 */
620 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
621 /* disable ADC 1 */
622 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
623 /* Set SLV-T Bank : 0x00 */
624 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
625 /* Disable ADC 2 */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
627 /* Disable ADC 3 */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
629 /* Disable ADC clock */
630 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
631 /* Disable RF level monitor */
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
633 /* Disable demod clock */
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
635 priv->state = STATE_SLEEP_TC;
636 return 0;
637}
638
639static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
640{
641 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
642 if (priv->state != STATE_ACTIVE_TC) {
643 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
644 __func__, priv->state);
645 return -EINVAL;
646 }
647 /* Set SLV-T Bank : 0x00 */
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
649 /* disable TS output */
650 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
651 /* enable Hi-Z setting 1 */
652 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
653 /* enable Hi-Z setting 2 */
654 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
655 /* Cancel DVB-C setting */
656 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
657 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
658 /* Set SLV-X Bank : 0x00 */
659 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
660 /* disable ADC 1 */
661 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
662 /* Set SLV-T Bank : 0x00 */
663 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
664 /* Disable ADC 2 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
666 /* Disable ADC 3 */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
668 /* Disable ADC clock */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
670 /* Disable RF level monitor */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
672 /* Disable demod clock */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
674 priv->state = STATE_SLEEP_TC;
675 return 0;
676}
677
83808c23
AO		 678static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
679{
680 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
681 if (priv->state != STATE_ACTIVE_TC) {
682 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
683 __func__, priv->state);
684 return -EINVAL;
685 }
686 /* Set SLV-T Bank : 0x00 */
687 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
688 /* disable TS output */
689 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
690 /* enable Hi-Z setting 1 */
691 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
692 /* enable Hi-Z setting 2 */
693 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
694
695 /* TODO: Cancel demod parameter */
696
697 /* Set SLV-X Bank : 0x00 */
698 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
699 /* disable ADC 1 */
700 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
701 /* Set SLV-T Bank : 0x00 */
702 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
703 /* Disable ADC 2 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
705 /* Disable ADC 3 */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
707 /* Disable ADC clock */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
709 /* Disable RF level monitor */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
711 /* Disable demod clock */
712 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
713 priv->state = STATE_SLEEP_TC;
714 return 0;
715}
716
a6dc60ff
KS		 717static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
718{
719 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
720 if (priv->state != STATE_SHUTDOWN) {
721 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
722 __func__, priv->state);
723 return -EINVAL;
724 }
725 /* Set SLV-X Bank : 0x00 */
726 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
727 /* Clear all demodulator registers */
728 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
729 usleep_range(3000, 5000);
730 /* Set SLV-X Bank : 0x00 */
731 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
732 /* Set demod SW reset */
733 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
83808c23
AO		 734
735 switch (priv->xtal) {
736 case SONY_XTAL_20500:
737 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
738 break;
739 case SONY_XTAL_24000:
740 /* Select demod frequency */
741 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
742 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
743 break;
744 case SONY_XTAL_41000:
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
746 break;
747 default:
748 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
749 __func__, priv->xtal);
750 return -EINVAL;
751 }
752
a6dc60ff
KS		 753 /* Set demod mode */
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
755 /* Clear demod SW reset */
756 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
757 usleep_range(1000, 2000);
758 /* Set SLV-T Bank : 0x00 */
759 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
760 /* enable DSQOUT */
761 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
762 /* enable DSQIN */
763 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
764 /* TADC Bias On */
765 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
766 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
767 /* SADC Bias On */
768 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
769 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
770 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
771 priv->state = STATE_SLEEP_S;
772 return 0;
773}
774
775static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
776{
777 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
778 if (priv->state != STATE_SHUTDOWN) {
779 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
780 __func__, priv->state);
781 return -EINVAL;
782 }
783 /* Set SLV-X Bank : 0x00 */
784 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
785 /* Clear all demodulator registers */
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
787 usleep_range(3000, 5000);
788 /* Set SLV-X Bank : 0x00 */
789 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
790 /* Set demod SW reset */
791 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
792 /* Set X'tal clock to 20.5Mhz */
793 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
794 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
795 /* Clear demod SW reset */
796 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
797 usleep_range(1000, 2000);
798 /* Set SLV-T Bank : 0x00 */
799 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
800 /* TADC Bias On */
801 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
802 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
803 /* SADC Bias On */
804 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
805 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
806 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
807 priv->state = STATE_SLEEP_TC;
808 return 0;
809}
810
811static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
812{
813 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
814 /* Set SLV-T Bank : 0x00 */
815 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
816 /* SW Reset */
817 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
818 /* Enable TS output */
819 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
820 return 0;
821}
822
823/* Set TS parallel mode */
824static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
825 u8 system)
826{
827 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
828
829 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
830 /* Set SLV-T Bank : 0x00 */
831 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
832 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
833 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
834 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
835 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
836 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
837
838 /*
839 * slave Bank Addr Bit default Name
840 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
841 */
842 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
843 /*
844 * Disable TS IF Clock
845 * slave Bank Addr Bit default Name
846 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
847 */
848 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
849 /*
850 * slave Bank Addr Bit default Name
851 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
852 */
853 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
854 /*
855 * Enable TS IF Clock
856 * slave Bank Addr Bit default Name
857 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
858 */
859 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
860
861 if (system == SYS_DVBT) {
862 /* Enable parity period for DVB-T */
863 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
864 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
865 } else if (system == SYS_DVBC_ANNEX_A) {
866 /* Enable parity period for DVB-C */
867 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
868 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
869 }
870}
871
872static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
873{
83808c23 874 u8 chip_id = 0;
a6dc60ff
KS		 875
876 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
83808c23
AO		 877 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
878 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
879 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
880 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
881
a6dc60ff
KS		 882 return chip_id;
883}
884
885static int cxd2841er_read_status_s(struct dvb_frontend *fe,
886 enum fe_status *status)
887{
888 u8 reg = 0;
889 struct cxd2841er_priv *priv = fe->demodulator_priv;
890
891 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
892 *status = 0;
893 if (priv->state != STATE_ACTIVE_S) {
894 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
895 __func__, priv->state);
896 return -EINVAL;
897 }
898 /* Set SLV-T Bank : 0xA0 */
899 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
900 /*
901 * slave Bank Addr Bit Signal name
902 * <SLV-T> A0h 11h [2] ITSLOCK
903 */
904 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
905 if (reg & 0x04) {
906 *status = FE_HAS_SIGNAL
907 | FE_HAS_CARRIER
908 | FE_HAS_VITERBI
909 | FE_HAS_SYNC
910 | FE_HAS_LOCK;
911 }
912 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
913 return 0;
914}
915
916static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
917 u8 *sync, u8 *tslock, u8 *unlock)
918{
919 u8 data = 0;
920
921 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
922 if (priv->state != STATE_ACTIVE_TC)
923 return -EINVAL;
924 if (priv->system == SYS_DVBT) {
925 /* Set SLV-T Bank : 0x10 */
926 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
927 } else {
928 /* Set SLV-T Bank : 0x20 */
929 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
930 }
931 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
932 if ((data & 0x07) == 0x07) {
933 dev_dbg(&priv->i2c->dev,
934 "%s(): invalid hardware state detected\n", __func__);
935 *sync = 0;
936 *tslock = 0;
937 *unlock = 0;
938 } else {
939 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
940 *tslock = ((data & 0x20) ? 1 : 0);
941 *unlock = ((data & 0x10) ? 1 : 0);
942 }
943 return 0;
944}
945
946static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
947{
948 u8 data;
949
950 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
951 if (priv->state != STATE_ACTIVE_TC)
952 return -EINVAL;
953 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
954 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
955 if ((data & 0x01) == 0) {
956 *tslock = 0;
957 } else {
958 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
959 *tslock = ((data & 0x20) ? 1 : 0);
960 }
961 return 0;
962}
963
83808c23
AO		 964static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
965 u8 *sync, u8 *tslock, u8 *unlock)
966{
967 u8 data = 0;
968
969 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
970 if (priv->state != STATE_ACTIVE_TC)
971 return -EINVAL;
972 /* Set SLV-T Bank : 0x60 */
973 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
974 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
975 dev_dbg(&priv->i2c->dev,
976 "%s(): lock=0x%x\n", __func__, data);
977 *sync = ((data & 0x02) ? 1 : 0);
978 *tslock = ((data & 0x01) ? 1 : 0);
979 *unlock = ((data & 0x10) ? 1 : 0);
980 return 0;
981}
982
a6dc60ff
KS		 983static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
984 enum fe_status *status)
985{
986 int ret = 0;
987 u8 sync = 0;
988 u8 tslock = 0;
989 u8 unlock = 0;
990 struct cxd2841er_priv *priv = fe->demodulator_priv;
991
992 *status = 0;
993 if (priv->state == STATE_ACTIVE_TC) {
994 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
995 ret = cxd2841er_read_status_t_t2(
996 priv, &sync, &tslock, &unlock);
997 if (ret)
998 goto done;
999 if (unlock)
1000 goto done;
1001 if (sync)
1002 *status = FE_HAS_SIGNAL |
1003 FE_HAS_CARRIER |
1004 FE_HAS_VITERBI |
1005 FE_HAS_SYNC;
1006 if (tslock)
1007 *status |= FE_HAS_LOCK;
83808c23
AO		 1008 } else if (priv->system == SYS_ISDBT) {
1009 ret = cxd2841er_read_status_i(
1010 priv, &sync, &tslock, &unlock);
1011 if (ret)
1012 goto done;
1013 if (unlock)
1014 goto done;
1015 if (sync)
1016 *status = FE_HAS_SIGNAL |
1017 FE_HAS_CARRIER |
1018 FE_HAS_VITERBI |
1019 FE_HAS_SYNC;
1020 if (tslock)
1021 *status |= FE_HAS_LOCK;
a6dc60ff
KS		 1022 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1023 ret = cxd2841er_read_status_c(priv, &tslock);
1024 if (ret)
1025 goto done;
1026 if (tslock)
1027 *status = FE_HAS_SIGNAL |
1028 FE_HAS_CARRIER |
1029 FE_HAS_VITERBI |
1030 FE_HAS_SYNC |
1031 FE_HAS_LOCK;
1032 }
1033 }
1034done:
1035 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1036 return ret;
1037}
1038
1039static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1040 int *offset)
1041{
1042 u8 data[3];
1043 u8 is_hs_mode;
1044 s32 cfrl_ctrlval;
1045 s32 temp_div, temp_q, temp_r;
1046
1047 if (priv->state != STATE_ACTIVE_S) {
1048 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1049 __func__, priv->state);
1050 return -EINVAL;
1051 }
1052 /*
1053 * Get High Sampling Rate mode
1054 * slave Bank Addr Bit Signal name
1055 * <SLV-T> A0h 10h [0] ITRL_LOCK
1056 */
1057 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1058 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1059 if (data[0] & 0x01) {
1060 /*
1061 * slave Bank Addr Bit Signal name
1062 * <SLV-T> A0h 50h [4] IHSMODE
1063 */
1064 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1065 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1066 } else {
1067 dev_dbg(&priv->i2c->dev,
1068 "%s(): unable to detect sampling rate mode\n",
1069 __func__);
1070 return -EINVAL;
1071 }
1072 /*
1073 * slave Bank Addr Bit Signal name
1074 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1075 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1076 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1077 */
1078 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1079 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1080 (((u32)data[1] & 0xFF) << 8) |
1081 ((u32)data[2] & 0xFF), 20);
1082 temp_div = (is_hs_mode ? 1048576 : 1572864);
1083 if (cfrl_ctrlval > 0) {
1084 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1085 temp_div, &temp_r);
1086 } else {
1087 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1088 temp_div, &temp_r);
1089 }
1090 if (temp_r >= temp_div / 2)
1091 temp_q++;
1092 if (cfrl_ctrlval > 0)
1093 temp_q *= -1;
1094 *offset = temp_q;
1095 return 0;
1096}
1097
c8946c8d
MCC		 1098static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1099 u32 bandwidth, int *offset)
a6dc60ff
KS		 1100{
1101 u8 data[4];
1102
1103 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1104 if (priv->state != STATE_ACTIVE_TC) {
1105 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1106 __func__, priv->state);
1107 return -EINVAL;
1108 }
1109 if (priv->system != SYS_DVBT2) {
1110 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1111 __func__, priv->system);
1112 return -EINVAL;
1113 }
1114 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1115 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1116 *offset = -1 * sign_extend32(
1117 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1118 ((u32)data[2] << 8) | (u32)data[3], 27);
1119 switch (bandwidth) {
1120 case 1712000:
1121 *offset /= 582;
1122 break;
1123 case 5000000:
1124 case 6000000:
1125 case 7000000:
1126 case 8000000:
1127 *offset *= (bandwidth / 1000000);
1128 *offset /= 940;
1129 break;
1130 default:
1131 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1132 __func__, bandwidth);
1133 return -EINVAL;
1134 }
1135 return 0;
1136}
1137
c8946c8d
MCC		 1138static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1139 int *offset)
a6dc60ff
KS		 1140{
1141 u8 data[2];
1142
1143 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1144 if (priv->state != STATE_ACTIVE_TC) {
1145 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1146 __func__, priv->state);
1147 return -EINVAL;
1148 }
1149 if (priv->system != SYS_DVBC_ANNEX_A) {
1150 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1151 __func__, priv->system);
1152 return -EINVAL;
1153 }
1154 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1155 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1156 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1157 | (u32)data[1], 13), 16384);
1158 return 0;
1159}
1160
1161static int cxd2841er_read_packet_errors_t(
1162 struct cxd2841er_priv *priv, u32 *penum)
1163{
1164 u8 data[3];
1165
1166 *penum = 0;
1167 if (priv->state != STATE_ACTIVE_TC) {
1168 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1169 __func__, priv->state);
1170 return -EINVAL;
1171 }
1172 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1173 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1174 if (data[2] & 0x01)
1175 *penum = ((u32)data[0] << 8) | (u32)data[1];
1176 return 0;
1177}
1178
1179static int cxd2841er_read_packet_errors_t2(
1180 struct cxd2841er_priv *priv, u32 *penum)
1181{
1182 u8 data[3];
1183
1184 *penum = 0;
1185 if (priv->state != STATE_ACTIVE_TC) {
1186 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1187 __func__, priv->state);
1188 return -EINVAL;
1189 }
1190 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1191 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1192 if (data[0] & 0x01)
1193 *penum = ((u32)data[1] << 8) | (u32)data[2];
1194 return 0;
1195}
1196
83808c23
AO		 1197static int cxd2841er_read_packet_errors_i(
1198 struct cxd2841er_priv *priv, u32 *penum)
1199{
1200 u8 data[2];
1201
1202 *penum = 0;
1203 if (priv->state != STATE_ACTIVE_TC) {
1204 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1205 __func__, priv->state);
1206 return -EINVAL;
1207 }
1208 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1209 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1210
1211 if (!(data[0] & 0x01))
1212 return 0;
1213
1214 /* Layer A */
1215 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1216 *penum = ((u32)data[0] << 8) | (u32)data[1];
1217
1218 /* Layer B */
1219 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1220 *penum += ((u32)data[0] << 8) | (u32)data[1];
1221
1222 /* Layer C */
1223 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1224 *penum += ((u32)data[0] << 8) | (u32)data[1];
1225
1226 return 0;
1227}
1228
a6dc60ff
KS		 1229static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1230{
1231 u8 data[11];
1232 u32 bit_error, bit_count;
1233 u32 temp_q, temp_r;
1234
1235 /* Set SLV-T Bank : 0xA0 */
1236 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1237 /*
1238 * slave Bank Addr Bit Signal name
1239 * <SLV-T> A0h 35h [0] IFVBER_VALID
1240 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1241 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1242 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1243 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1244 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1245 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1246 */
1247 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1248 if (data[0] & 0x01) {
1249 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1250 ((u32)(data[2] & 0xFF) << 8) |
1251 (u32)(data[3] & 0xFF);
1252 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1253 ((u32)(data[9] & 0xFF) << 8) |
1254 (u32)(data[10] & 0xFF);
1255 /*
1256 * BER = bitError / bitCount
1257 * = (bitError * 10^7) / bitCount
1258 * = ((bitError * 625 * 125 * 128) / bitCount
1259 */
1260 if ((bit_count == 0) || (bit_error > bit_count)) {
1261 dev_dbg(&priv->i2c->dev,
1262 "%s(): invalid bit_error %d, bit_count %d\n",
1263 __func__, bit_error, bit_count);
1264 return 0;
1265 }
1266 temp_q = div_u64_rem(10000000ULL * bit_error,
1267 bit_count, &temp_r);
1268 if (bit_count != 1 && temp_r >= bit_count / 2)
1269 temp_q++;
1270 return temp_q;
1271 }
1272 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1273 return 0;
1274}
1275
1276
1277static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1278{
1279 u8 data[5];
1280 u32 bit_error, period;
1281 u32 temp_q, temp_r;
1282 u32 result = 0;
1283
1284 /* Set SLV-T Bank : 0xB2 */
1285 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1286 /*
1287 * slave Bank Addr Bit Signal name
1288 * <SLV-T> B2h 30h [0] IFLBER_VALID
1289 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1290 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1291 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1292 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1293 */
1294 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1295 if (data[0] & 0x01) {
1296 /* Bit error count */
1297 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1298 ((u32)(data[2] & 0xFF) << 16) |
1299 ((u32)(data[3] & 0xFF) << 8) |
1300 (u32)(data[4] & 0xFF);
1301
1302 /* Set SLV-T Bank : 0xA0 */
1303 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1304 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1305 /* Measurement period */
1306 period = (u32)(1 << (data[0] & 0x0F));
1307 if (period == 0) {
1308 dev_dbg(&priv->i2c->dev,
1309 "%s(): period is 0\n", __func__);
1310 return 0;
1311 }
1312 if (bit_error > (period * 64800)) {
1313 dev_dbg(&priv->i2c->dev,
1314 "%s(): invalid bit_err 0x%x period 0x%x\n",
1315 __func__, bit_error, period);
1316 return 0;
1317 }
1318 /*
1319 * BER = bitError / (period * 64800)
1320 * = (bitError * 10^7) / (period * 64800)
1321 * = (bitError * 10^5) / (period * 648)
1322 * = (bitError * 12500) / (period * 81)
1323 * = (bitError * 10) * 1250 / (period * 81)
1324 */
1325 temp_q = div_u64_rem(12500ULL * bit_error,
1326 period * 81, &temp_r);
1327 if (temp_r >= period * 40)
1328 temp_q++;
1329 result = temp_q;
1330 } else {
1331 dev_dbg(&priv->i2c->dev,
1332 "%s(): no data available\n", __func__);
1333 }
1334 return result;
1335}
1336
1337static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1338{
1339 u8 data[4];
1340 u32 div, q, r;
1341 u32 bit_err, period_exp, n_ldpc;
1342
1343 *ber = 0;
1344 if (priv->state != STATE_ACTIVE_TC) {
1345 dev_dbg(&priv->i2c->dev,
1346 "%s(): invalid state %d\n", __func__, priv->state);
1347 return -EINVAL;
1348 }
1349 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1350 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1351 if (!(data[0] & 0x10)) {
1352 dev_dbg(&priv->i2c->dev,
1353 "%s(): no valid BER data\n", __func__);
1354 return 0;
1355 }
1356 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1357 ((u32)data[1] << 16) |
1358 ((u32)data[2] << 8) |
1359 (u32)data[3];
1360 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1361 period_exp = data[0] & 0x0f;
1362 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1363 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1364 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1365 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1366 dev_dbg(&priv->i2c->dev,
1367 "%s(): invalid BER value\n", __func__);
1368 return -EINVAL;
1369 }
1370 if (period_exp >= 4) {
1371 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1372 q = div_u64_rem(3125ULL * bit_err, div, &r);
1373 } else {
1374 div = (1U << period_exp) * (n_ldpc / 200);
1375 q = div_u64_rem(50000ULL * bit_err, div, &r);
1376 }
1377 *ber = (r >= div / 2) ? q + 1 : q;
1378 return 0;
1379}
1380
1381static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1382{
1383 u8 data[2];
1384 u32 div, q, r;
1385 u32 bit_err, period;
1386
1387 *ber = 0;
1388 if (priv->state != STATE_ACTIVE_TC) {
1389 dev_dbg(&priv->i2c->dev,
1390 "%s(): invalid state %d\n", __func__, priv->state);
1391 return -EINVAL;
1392 }
1393 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1394 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1395 if (!(data[0] & 0x01)) {
1396 dev_dbg(&priv->i2c->dev,
1397 "%s(): no valid BER data\n", __func__);
1398 return 0;
1399 }
1400 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1401 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1402 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1403 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1404 div = period / 128;
1405 q = div_u64_rem(78125ULL * bit_err, div, &r);
1406 *ber = (r >= div / 2) ? q + 1 : q;
1407 return 0;
1408}
1409
1410static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1411{
1412 u8 data[3];
1413 u32 res = 0, value;
1414 int min_index, max_index, index;
1415 static const struct cxd2841er_cnr_data *cn_data;
1416
1417 /* Set SLV-T Bank : 0xA1 */
1418 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1419 /*
1420 * slave Bank Addr Bit Signal name
1421 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1422 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1423 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1424 */
1425 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1426 if (data[0] & 0x01) {
1427 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1428 min_index = 0;
1429 if (delsys == SYS_DVBS) {
1430 cn_data = s_cn_data;
1431 max_index = sizeof(s_cn_data) /
1432 sizeof(s_cn_data[0]) - 1;
1433 } else {
1434 cn_data = s2_cn_data;
1435 max_index = sizeof(s2_cn_data) /
1436 sizeof(s2_cn_data[0]) - 1;
1437 }
1438 if (value >= cn_data[min_index].value) {
1439 res = cn_data[min_index].cnr_x1000;
1440 goto done;
1441 }
1442 if (value <= cn_data[max_index].value) {
1443 res = cn_data[max_index].cnr_x1000;
1444 goto done;
1445 }
1446 while ((max_index - min_index) > 1) {
1447 index = (max_index + min_index) / 2;
1448 if (value == cn_data[index].value) {
1449 res = cn_data[index].cnr_x1000;
1450 goto done;
1451 } else if (value > cn_data[index].value)
1452 max_index = index;
1453 else
1454 min_index = index;
1455 if ((max_index - min_index) <= 1) {
1456 if (value == cn_data[max_index].value) {
1457 res = cn_data[max_index].cnr_x1000;
1458 goto done;
1459 } else {
1460 res = cn_data[min_index].cnr_x1000;
1461 goto done;
1462 }
1463 }
1464 }
1465 } else {
1466 dev_dbg(&priv->i2c->dev,
1467 "%s(): no data available\n", __func__);
1468 }
1469done:
1470 return res;
1471}
1472
1473static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1474{
1475 u32 reg;
1476 u8 data[2];
1477
1478 *snr = 0;
1479 if (priv->state != STATE_ACTIVE_TC) {
1480 dev_dbg(&priv->i2c->dev,
1481 "%s(): invalid state %d\n", __func__, priv->state);
1482 return -EINVAL;
1483 }
1484 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1485 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1486 reg = ((u32)data[0] << 8) | (u32)data[1];
1487 if (reg == 0) {
1488 dev_dbg(&priv->i2c->dev,
1489 "%s(): reg value out of range\n", __func__);
1490 return 0;
1491 }
1492 if (reg > 4996)
1493 reg = 4996;
1494 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1495 return 0;
1496}
1497
c8946c8d 1498static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
a6dc60ff
KS		 1499{
1500 u32 reg;
1501 u8 data[2];
1502
1503 *snr = 0;
1504 if (priv->state != STATE_ACTIVE_TC) {
1505 dev_dbg(&priv->i2c->dev,
1506 "%s(): invalid state %d\n", __func__, priv->state);
1507 return -EINVAL;
1508 }
1509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1510 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1511 reg = ((u32)data[0] << 8) | (u32)data[1];
1512 if (reg == 0) {
1513 dev_dbg(&priv->i2c->dev,
1514 "%s(): reg value out of range\n", __func__);
1515 return 0;
1516 }
1517 if (reg > 10876)
1518 reg = 10876;
1519 *snr = 10000 * ((intlog10(reg) -
1520 intlog10(12600 - reg)) >> 24) + 32000;
1521 return 0;
1522}
1523
83808c23
AO		 1524static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1525{
1526 u32 reg;
1527 u8 data[2];
1528
1529 *snr = 0;
1530 if (priv->state != STATE_ACTIVE_TC) {
1531 dev_dbg(&priv->i2c->dev,
1532 "%s(): invalid state %d\n", __func__,
1533 priv->state);
1534 return -EINVAL;
1535 }
1536
1537 /* Freeze all registers */
1538 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1539
1540
1541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1542 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1543 reg = ((u32)data[0] << 8) | (u32)data[1];
1544 if (reg == 0) {
1545 dev_dbg(&priv->i2c->dev,
1546 "%s(): reg value out of range\n", __func__);
1547 return 0;
1548 }
1549 if (reg > 4996)
1550 reg = 4996;
1551 *snr = 100 * intlog10(reg) - 9031;
1552 return 0;
1553}
1554
a6dc60ff
KS		 1555static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1556 u8 delsys)
1557{
1558 u8 data[2];
1559
1560 cxd2841er_write_reg(
1561 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1562 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1563 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1564}
1565
83808c23
AO		 1566static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1567 u8 delsys)
1568{
1569 u8 data[2];
1570
1571 cxd2841er_write_reg(
1572 priv, I2C_SLVT, 0x00, 0x60);
1573 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1574
1575 dev_dbg(&priv->i2c->dev,
1576 "%s(): AGC value=%u\n",
1577 __func__, (((u16)data[0] & 0x0F) << 8) |
1578 (u16)(data[1] & 0xFF));
1579 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1580}
1581
a6dc60ff
KS		 1582static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1583{
1584 u8 data[2];
1585
1586 /* Set SLV-T Bank : 0xA0 */
1587 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1588 /*
1589 * slave Bank Addr Bit Signal name
1590 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1591 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1592 */
1593 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1594 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1595}
1596
1597static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1598{
1599 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1600 struct cxd2841er_priv *priv = fe->demodulator_priv;
1601
1602 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1603 *ber = 0;
1604 switch (p->delivery_system) {
1605 case SYS_DVBS:
1606 *ber = cxd2841er_mon_read_ber_s(priv);
1607 break;
1608 case SYS_DVBS2:
1609 *ber = cxd2841er_mon_read_ber_s2(priv);
1610 break;
1611 case SYS_DVBT:
1612 return cxd2841er_read_ber_t(priv, ber);
1613 case SYS_DVBT2:
1614 return cxd2841er_read_ber_t2(priv, ber);
1615 default:
1616 *ber = 0;
1617 break;
1618 }
1619 return 0;
1620}
1621
1622static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1623 u16 *strength)
1624{
1625 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1626 struct cxd2841er_priv *priv = fe->demodulator_priv;
1627
1628 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1629 switch (p->delivery_system) {
1630 case SYS_DVBT:
1631 case SYS_DVBT2:
1632 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1633 priv, p->delivery_system);
1634 break;
83808c23
AO		 1635 case SYS_ISDBT:
1636 *strength = 65535 - cxd2841er_read_agc_gain_i(
1637 priv, p->delivery_system);
1638 break;
a6dc60ff
KS		 1639 case SYS_DVBS:
1640 case SYS_DVBS2:
1641 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1642 break;
1643 default:
1644 *strength = 0;
1645 break;
1646 }
1647 return 0;
1648}
1649
1650static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1651{
1652 u32 tmp = 0;
1653 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1654 struct cxd2841er_priv *priv = fe->demodulator_priv;
1655
1656 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1657 switch (p->delivery_system) {
1658 case SYS_DVBT:
1659 cxd2841er_read_snr_t(priv, &tmp);
1660 break;
1661 case SYS_DVBT2:
1662 cxd2841er_read_snr_t2(priv, &tmp);
1663 break;
83808c23
AO		 1664 case SYS_ISDBT:
1665 cxd2841er_read_snr_i(priv, &tmp);
1666 break;
a6dc60ff
KS		 1667 case SYS_DVBS:
1668 case SYS_DVBS2:
1669 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1670 break;
1671 default:
1672 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1673 __func__, p->delivery_system);
1674 break;
1675 }
1676 *snr = tmp & 0xffff;
1677 return 0;
1678}
1679
1680static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1681{
1682 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1683 struct cxd2841er_priv *priv = fe->demodulator_priv;
1684
1685 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1686 switch (p->delivery_system) {
1687 case SYS_DVBT:
1688 cxd2841er_read_packet_errors_t(priv, ucblocks);
1689 break;
1690 case SYS_DVBT2:
1691 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1692 break;
83808c23
AO		 1693 case SYS_ISDBT:
1694 cxd2841er_read_packet_errors_i(priv, ucblocks);
1695 break;
a6dc60ff
KS		 1696 default:
1697 *ucblocks = 0;
1698 break;
1699 }
1700 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1701 return 0;
1702}
1703
1704static int cxd2841er_dvbt2_set_profile(
1705 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1706{
1707 u8 tune_mode;
1708 u8 seq_not2d_time;
1709
1710 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1711 switch (profile) {
1712 case DVBT2_PROFILE_BASE:
1713 tune_mode = 0x01;
1714 seq_not2d_time = 12;
1715 break;
1716 case DVBT2_PROFILE_LITE:
1717 tune_mode = 0x05;
1718 seq_not2d_time = 40;
1719 break;
1720 case DVBT2_PROFILE_ANY:
1721 tune_mode = 0x00;
1722 seq_not2d_time = 40;
1723 break;
1724 default:
1725 return -EINVAL;
1726 }
1727 /* Set SLV-T Bank : 0x2E */
1728 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1729 /* Set profile and tune mode */
1730 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1731 /* Set SLV-T Bank : 0x2B */
1732 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1733 /* Set early unlock detection time */
1734 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1735 return 0;
1736}
1737
1738static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1739 u8 is_auto, u8 plp_id)
1740{
1741 if (is_auto) {
1742 dev_dbg(&priv->i2c->dev,
1743 "%s() using auto PLP selection\n", __func__);
1744 } else {
1745 dev_dbg(&priv->i2c->dev,
1746 "%s() using manual PLP selection, ID %d\n",
1747 __func__, plp_id);
1748 }
1749 /* Set SLV-T Bank : 0x23 */
1750 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1751 if (!is_auto) {
1752 /* Manual PLP selection mode. Set the data PLP Id. */
1753 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1754 }
1755 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1756 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1757 return 0;
1758}
1759
1760static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1761 u32 bandwidth)
1762{
1763 u32 iffreq;
1764 u8 b20_9f[5];
1765 u8 b10_a6[14];
1766 u8 b10_b6[3];
1767 u8 b10_d7;
1768
1769 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1770 switch (bandwidth) {
1771 case 8000000:
1772 /* bank 0x20, reg 0x9f */
1773 b20_9f[0] = 0x11;
1774 b20_9f[1] = 0xf0;
1775 b20_9f[2] = 0x00;
1776 b20_9f[3] = 0x00;
1777 b20_9f[4] = 0x00;
1778 /* bank 0x10, reg 0xa6 */
1779 b10_a6[0] = 0x26;
1780 b10_a6[1] = 0xaf;
1781 b10_a6[2] = 0x06;
1782 b10_a6[3] = 0xcd;
1783 b10_a6[4] = 0x13;
1784 b10_a6[5] = 0xbb;
1785 b10_a6[6] = 0x28;
1786 b10_a6[7] = 0xba;
1787 b10_a6[8] = 0x23;
1788 b10_a6[9] = 0xa9;
1789 b10_a6[10] = 0x1f;
1790 b10_a6[11] = 0xa8;
1791 b10_a6[12] = 0x2c;
1792 b10_a6[13] = 0xc8;
1793 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1794 b10_d7 = 0x00;
1795 break;
1796 case 7000000:
1797 /* bank 0x20, reg 0x9f */
1798 b20_9f[0] = 0x14;
1799 b20_9f[1] = 0x80;
1800 b20_9f[2] = 0x00;
1801 b20_9f[3] = 0x00;
1802 b20_9f[4] = 0x00;
1803 /* bank 0x10, reg 0xa6 */
1804 b10_a6[0] = 0x2C;
1805 b10_a6[1] = 0xBD;
1806 b10_a6[2] = 0x02;
1807 b10_a6[3] = 0xCF;
1808 b10_a6[4] = 0x04;
1809 b10_a6[5] = 0xF8;
1810 b10_a6[6] = 0x23;
1811 b10_a6[7] = 0xA6;
1812 b10_a6[8] = 0x29;
1813 b10_a6[9] = 0xB0;
1814 b10_a6[10] = 0x26;
1815 b10_a6[11] = 0xA9;
1816 b10_a6[12] = 0x21;
1817 b10_a6[13] = 0xA5;
1818 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1819 b10_d7 = 0x02;
1820 break;
1821 case 6000000:
1822 /* bank 0x20, reg 0x9f */
1823 b20_9f[0] = 0x17;
1824 b20_9f[1] = 0xEA;
1825 b20_9f[2] = 0xAA;
1826 b20_9f[3] = 0xAA;
1827 b20_9f[4] = 0xAA;
1828 /* bank 0x10, reg 0xa6 */
1829 b10_a6[0] = 0x27;
1830 b10_a6[1] = 0xA7;
1831 b10_a6[2] = 0x28;
1832 b10_a6[3] = 0xB3;
1833 b10_a6[4] = 0x02;
1834 b10_a6[5] = 0xF0;
1835 b10_a6[6] = 0x01;
1836 b10_a6[7] = 0xE8;
1837 b10_a6[8] = 0x00;
1838 b10_a6[9] = 0xCF;
1839 b10_a6[10] = 0x00;
1840 b10_a6[11] = 0xE6;
1841 b10_a6[12] = 0x23;
1842 b10_a6[13] = 0xA4;
1843 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1844 b10_d7 = 0x04;
1845 break;
1846 case 5000000:
1847 /* bank 0x20, reg 0x9f */
1848 b20_9f[0] = 0x1C;
1849 b20_9f[1] = 0xB3;
1850 b20_9f[2] = 0x33;
1851 b20_9f[3] = 0x33;
1852 b20_9f[4] = 0x33;
1853 /* bank 0x10, reg 0xa6 */
1854 b10_a6[0] = 0x27;
1855 b10_a6[1] = 0xA7;
1856 b10_a6[2] = 0x28;
1857 b10_a6[3] = 0xB3;
1858 b10_a6[4] = 0x02;
1859 b10_a6[5] = 0xF0;
1860 b10_a6[6] = 0x01;
1861 b10_a6[7] = 0xE8;
1862 b10_a6[8] = 0x00;
1863 b10_a6[9] = 0xCF;
1864 b10_a6[10] = 0x00;
1865 b10_a6[11] = 0xE6;
1866 b10_a6[12] = 0x23;
1867 b10_a6[13] = 0xA4;
1868 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1869 b10_d7 = 0x06;
1870 break;
1871 case 1712000:
1872 /* bank 0x20, reg 0x9f */
1873 b20_9f[0] = 0x58;
1874 b20_9f[1] = 0xE2;
1875 b20_9f[2] = 0xAF;
1876 b20_9f[3] = 0xE0;
1877 b20_9f[4] = 0xBC;
1878 /* bank 0x10, reg 0xa6 */
1879 b10_a6[0] = 0x25;
1880 b10_a6[1] = 0xA0;
1881 b10_a6[2] = 0x36;
1882 b10_a6[3] = 0x8D;
1883 b10_a6[4] = 0x2E;
1884 b10_a6[5] = 0x94;
1885 b10_a6[6] = 0x28;
1886 b10_a6[7] = 0x9B;
1887 b10_a6[8] = 0x32;
1888 b10_a6[9] = 0x90;
1889 b10_a6[10] = 0x2C;
1890 b10_a6[11] = 0x9D;
1891 b10_a6[12] = 0x29;
1892 b10_a6[13] = 0x99;
1893 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1894 b10_d7 = 0x03;
1895 break;
1896 default:
1897 return -EINVAL;
1898 }
1899 /* Set SLV-T Bank : 0x20 */
1900 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1901 cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1902 /* Set SLV-T Bank : 0x27 */
1903 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1904 cxd2841er_set_reg_bits(
1905 priv, I2C_SLVT, 0x7a,
1906 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1907 /* Set SLV-T Bank : 0x10 */
1908 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1909 /* Group delay equaliser sett. for ASCOT2E */
1910 cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
1911 /* <IF freq setting> */
1912 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1913 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1914 b10_b6[2] = (u8)(iffreq & 0xff);
1915 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1916 /* System bandwidth setting */
1917 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
1918 return 0;
1919}
1920
1921static int cxd2841er_sleep_tc_to_active_t_band(
1922 struct cxd2841er_priv *priv, u32 bandwidth)
1923{
83808c23 1924 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff 1925 u32 iffreq;
83808c23
AO		 1926 u8 nominalRate8bw[3][5] = {
1927 /* TRCG Nominal Rate [37:0] */
1928 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1929 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1930 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1931 };
1932 u8 nominalRate7bw[3][5] = {
1933 /* TRCG Nominal Rate [37:0] */
1934 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1935 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1936 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1937 };
1938 u8 nominalRate6bw[3][5] = {
1939 /* TRCG Nominal Rate [37:0] */
1940 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1941 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1942 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1943 };
1944 u8 nominalRate5bw[3][5] = {
1945 /* TRCG Nominal Rate [37:0] */
1946 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1947 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1948 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1949 };
a6dc60ff 1950
83808c23
AO		 1951 u8 itbCoef8bw[3][14] = {
1952 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1953 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1954 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
1955 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1956 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1957 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1958 };
1959 u8 itbCoef7bw[3][14] = {
1960 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1961 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1962 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
1963 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1964 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1965 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1966 };
1967 u8 itbCoef6bw[3][14] = {
1968 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1969 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1970 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
1971 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1972 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1973 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1974 };
1975 u8 itbCoef5bw[3][14] = {
1976 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1977 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1978 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
1979 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1980 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1981 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1982 };
1983
1984 /* Set SLV-T Bank : 0x13 */
a6dc60ff
KS		 1985 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
1986 /* Echo performance optimization setting */
83808c23
AO		 1987 data[0] = 0x01;
1988 data[1] = 0x14;
1989 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
1990
1991 /* Set SLV-T Bank : 0x10 */
a6dc60ff
KS		 1992 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1993
1994 switch (bandwidth) {
1995 case 8000000:
83808c23
AO		 1996 /* <Timing Recovery setting> */
1997 cxd2841er_write_regs(priv, I2C_SLVT,
1998 0x9F, nominalRate8bw[priv->xtal], 5);
1999 /* Group delay equaliser settings for
2000 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2001 */
2002 cxd2841er_write_regs(priv, I2C_SLVT,
2003 0xA6, itbCoef8bw[priv->xtal], 14);
2004 /* <IF freq setting> */
2005 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2006 data[0] = (u8) ((iffreq >> 16) & 0xff);
2007 data[1] = (u8)((iffreq >> 8) & 0xff);
2008 data[2] = (u8)(iffreq & 0xff);
2009 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2010 /* System bandwidth setting */
2011 cxd2841er_set_reg_bits(
2012 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2013
2014 /* Demod core latency setting */
2015 if (priv->xtal == SONY_XTAL_24000) {
2016 data[0] = 0x15;
2017 data[1] = 0x28;
2018 } else {
2019 data[0] = 0x01;
2020 data[1] = 0xE0;
2021 }
2022 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2023
2024 /* Notch filter setting */
2025 data[0] = 0x01;
2026 data[1] = 0x02;
2027 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2028 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2029 break;
2030 case 7000000:
83808c23
AO		 2031 /* <Timing Recovery setting> */
2032 cxd2841er_write_regs(priv, I2C_SLVT,
2033 0x9F, nominalRate7bw[priv->xtal], 5);
2034 /* Group delay equaliser settings for
2035 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2036 */
2037 cxd2841er_write_regs(priv, I2C_SLVT,
2038 0xA6, itbCoef7bw[priv->xtal], 14);
2039 /* <IF freq setting> */
2040 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2041 data[0] = (u8) ((iffreq >> 16) & 0xff);
2042 data[1] = (u8)((iffreq >> 8) & 0xff);
2043 data[2] = (u8)(iffreq & 0xff);
2044 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2045 /* System bandwidth setting */
2046 cxd2841er_set_reg_bits(
2047 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2048
2049 /* Demod core latency setting */
2050 if (priv->xtal == SONY_XTAL_24000) {
2051 data[0] = 0x1F;
2052 data[1] = 0xF8;
2053 } else {
2054 data[0] = 0x12;
2055 data[1] = 0xF8;
2056 }
2057 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2058
2059 /* Notch filter setting */
2060 data[0] = 0x00;
2061 data[1] = 0x03;
2062 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2063 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2064 break;
2065 case 6000000:
83808c23
AO		 2066 /* <Timing Recovery setting> */
2067 cxd2841er_write_regs(priv, I2C_SLVT,
2068 0x9F, nominalRate6bw[priv->xtal], 5);
2069 /* Group delay equaliser settings for
2070 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2071 */
2072 cxd2841er_write_regs(priv, I2C_SLVT,
2073 0xA6, itbCoef6bw[priv->xtal], 14);
2074 /* <IF freq setting> */
2075 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2076 data[0] = (u8) ((iffreq >> 16) & 0xff);
2077 data[1] = (u8)((iffreq >> 8) & 0xff);
2078 data[2] = (u8)(iffreq & 0xff);
2079 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2080 /* System bandwidth setting */
2081 cxd2841er_set_reg_bits(
2082 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2083
2084 /* Demod core latency setting */
2085 if (priv->xtal == SONY_XTAL_24000) {
2086 data[0] = 0x25;
2087 data[1] = 0x4C;
2088 } else {
2089 data[0] = 0x1F;
2090 data[1] = 0xDC;
2091 }
2092 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2093
2094 /* Notch filter setting */
2095 data[0] = 0x00;
2096 data[1] = 0x03;
2097 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2098 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2099 break;
2100 case 5000000:
83808c23
AO		 2101 /* <Timing Recovery setting> */
2102 cxd2841er_write_regs(priv, I2C_SLVT,
2103 0x9F, nominalRate5bw[priv->xtal], 5);
2104 /* Group delay equaliser settings for
2105 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2106 */
2107 cxd2841er_write_regs(priv, I2C_SLVT,
2108 0xA6, itbCoef5bw[priv->xtal], 14);
2109 /* <IF freq setting> */
2110 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2111 data[0] = (u8) ((iffreq >> 16) & 0xff);
2112 data[1] = (u8)((iffreq >> 8) & 0xff);
2113 data[2] = (u8)(iffreq & 0xff);
2114 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2115 /* System bandwidth setting */
2116 cxd2841er_set_reg_bits(
2117 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2118
2119 /* Demod core latency setting */
2120 if (priv->xtal == SONY_XTAL_24000) {
2121 data[0] = 0x2C;
2122 data[1] = 0xC2;
2123 } else {
2124 data[0] = 0x26;
2125 data[1] = 0x3C;
2126 }
2127 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2128
2129 /* Notch filter setting */
2130 data[0] = 0x00;
2131 data[1] = 0x03;
2132 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2133 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2134 break;
2135 }
2136
2137 return 0;
2138}
2139
2140static int cxd2841er_sleep_tc_to_active_i_band(
2141 struct cxd2841er_priv *priv, u32 bandwidth)
2142{
2143 u32 iffreq;
2144 u8 data[3];
2145
2146 /* TRCG Nominal Rate */
2147 u8 nominalRate8bw[3][5] = {
2148 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2149 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2150 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2151 };
2152
2153 u8 nominalRate7bw[3][5] = {
2154 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2155 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2156 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2157 };
2158
2159 u8 nominalRate6bw[3][5] = {
2160 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2161 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2162 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2163 };
2164
2165 u8 itbCoef8bw[3][14] = {
2166 {0x00}, /* 20.5MHz XTal */
2167 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2168 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2169 {0x0}, /* 41MHz XTal */
2170 };
2171
2172 u8 itbCoef7bw[3][14] = {
2173 {0x00}, /* 20.5MHz XTal */
2174 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2175 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2176 {0x00}, /* 41MHz XTal */
2177 };
2178
2179 u8 itbCoef6bw[3][14] = {
2180 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2181 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2182 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2183 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2184 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2185 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2186 };
2187
2188 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2189 /* Set SLV-T Bank : 0x10 */
2190 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2191
2192 /* 20.5/41MHz Xtal support is not available
2193 * on ISDB-T 7MHzBW and 8MHzBW
2194 */
2195 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2196 dev_err(&priv->i2c->dev,
2197 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2198 __func__, bandwidth);
2199 return -EINVAL;
2200 }
2201
2202 switch (bandwidth) {
2203 case 8000000:
2204 /* TRCG Nominal Rate */
2205 cxd2841er_write_regs(priv, I2C_SLVT,
2206 0x9F, nominalRate8bw[priv->xtal], 5);
2207 /* Group delay equaliser settings for ASCOT tuners optimized */
2208 cxd2841er_write_regs(priv, I2C_SLVT,
2209 0xA6, itbCoef8bw[priv->xtal], 14);
2210
2211 /* IF freq setting */
2212 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2213 data[0] = (u8) ((iffreq >> 16) & 0xff);
2214 data[1] = (u8)((iffreq >> 8) & 0xff);
2215 data[2] = (u8)(iffreq & 0xff);
2216 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2217
2218 /* System bandwidth setting */
2219 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2220
2221 /* Demod core latency setting */
2222 data[0] = 0x13;
2223 data[1] = 0xFC;
2224 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2225
2226 /* Acquisition optimization setting */
2227 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2228 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2229 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2230 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2231 break;
2232 case 7000000:
2233 /* TRCG Nominal Rate */
2234 cxd2841er_write_regs(priv, I2C_SLVT,
2235 0x9F, nominalRate7bw[priv->xtal], 5);
2236 /* Group delay equaliser settings for ASCOT tuners optimized */
2237 cxd2841er_write_regs(priv, I2C_SLVT,
2238 0xA6, itbCoef7bw[priv->xtal], 14);
2239
2240 /* IF freq setting */
2241 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2242 data[0] = (u8) ((iffreq >> 16) & 0xff);
2243 data[1] = (u8)((iffreq >> 8) & 0xff);
2244 data[2] = (u8)(iffreq & 0xff);
2245 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2246
2247 /* System bandwidth setting */
2248 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2249
2250 /* Demod core latency setting */
2251 data[0] = 0x1A;
2252 data[1] = 0xFA;
2253 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2254
2255 /* Acquisition optimization setting */
2256 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2257 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2258 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2259 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2260 break;
2261 case 6000000:
2262 /* TRCG Nominal Rate */
2263 cxd2841er_write_regs(priv, I2C_SLVT,
2264 0x9F, nominalRate6bw[priv->xtal], 5);
2265 /* Group delay equaliser settings for ASCOT tuners optimized */
2266 cxd2841er_write_regs(priv, I2C_SLVT,
2267 0xA6, itbCoef6bw[priv->xtal], 14);
2268
2269 /* IF freq setting */
2270 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2271 data[0] = (u8) ((iffreq >> 16) & 0xff);
2272 data[1] = (u8)((iffreq >> 8) & 0xff);
2273 data[2] = (u8)(iffreq & 0xff);
2274 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2275
2276 /* System bandwidth setting */
2277 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2278
2279 /* Demod core latency setting */
2280 if (priv->xtal == SONY_XTAL_24000) {
2281 data[0] = 0x1F;
2282 data[1] = 0x79;
2283 } else {
2284 data[0] = 0x1A;
2285 data[1] = 0xE2;
2286 }
2287 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2288
2289 /* Acquisition optimization setting */
2290 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2291 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2292 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2293 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
a6dc60ff
KS		 2294 break;
2295 default:
2296 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
83808c23 2297 __func__, bandwidth);
a6dc60ff
KS		 2298 return -EINVAL;
2299 }
a6dc60ff
KS		 2300 return 0;
2301}
2302
2303static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2304 u32 bandwidth)
2305{
2306 u8 bw7_8mhz_b10_a6[] = {
2307 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2308 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2309 u8 bw6mhz_b10_a6[] = {
2310 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2311 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2312 u8 b10_b6[3];
2313 u32 iffreq;
2314
2315 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2316 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2317 switch (bandwidth) {
2318 case 8000000:
2319 case 7000000:
2320 cxd2841er_write_regs(
2321 priv, I2C_SLVT, 0xa6,
2322 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2323 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2324 break;
2325 case 6000000:
2326 cxd2841er_write_regs(
2327 priv, I2C_SLVT, 0xa6,
2328 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2329 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2330 break;
2331 default:
2332 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2333 __func__, bandwidth);
2334 return -EINVAL;
2335 }
2336 /* <IF freq setting> */
2337 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2338 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2339 b10_b6[2] = (u8)(iffreq & 0xff);
2340 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2341 /* Set SLV-T Bank : 0x11 */
2342 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2343 switch (bandwidth) {
2344 case 8000000:
2345 case 7000000:
2346 cxd2841er_set_reg_bits(
2347 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2348 break;
2349 case 6000000:
2350 cxd2841er_set_reg_bits(
2351 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2352 break;
2353 }
2354 /* Set SLV-T Bank : 0x40 */
2355 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2356 switch (bandwidth) {
2357 case 8000000:
2358 cxd2841er_set_reg_bits(
2359 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2360 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2361 break;
2362 case 7000000:
2363 cxd2841er_set_reg_bits(
2364 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2365 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2366 break;
2367 case 6000000:
2368 cxd2841er_set_reg_bits(
2369 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2370 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2371 break;
2372 }
2373 return 0;
2374}
2375
2376static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2377 u32 bandwidth)
2378{
2379 u8 data[2] = { 0x09, 0x54 };
83808c23 2380 u8 data24m[3] = {0xDC, 0x6C, 0x00};
a6dc60ff
KS		 2381
2382 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2383 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2384 /* Set SLV-X Bank : 0x00 */
2385 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2386 /* Set demod mode */
2387 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2388 /* Set SLV-T Bank : 0x00 */
2389 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2390 /* Enable demod clock */
2391 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2392 /* Disable RF level monitor */
2393 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2394 /* Enable ADC clock */
2395 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2396 /* Enable ADC 1 */
2397 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
83808c23
AO		 2398 /* Enable ADC 2 & 3 */
2399 if (priv->xtal == SONY_XTAL_41000) {
2400 data[0] = 0x0A;
2401 data[1] = 0xD4;
2402 }
a6dc60ff
KS		 2403 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2404 /* Enable ADC 4 */
2405 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2406 /* Set SLV-T Bank : 0x10 */
2407 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2408 /* IFAGC gain settings */
2409 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2410 /* Set SLV-T Bank : 0x11 */
2411 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2412 /* BBAGC TARGET level setting */
2413 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2414 /* Set SLV-T Bank : 0x10 */
2415 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2416 /* ASCOT setting ON */
2417 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2418 /* Set SLV-T Bank : 0x18 */
2419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2420 /* Pre-RS BER moniter setting */
2421 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2422 /* FEC Auto Recovery setting */
2423 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2424 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2425 /* Set SLV-T Bank : 0x00 */
2426 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2427 /* TSIF setting */
2428 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2429 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
83808c23
AO		 2430
2431 if (priv->xtal == SONY_XTAL_24000) {
2432 /* Set SLV-T Bank : 0x10 */
2433 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2434 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2435 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2436 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2437 }
2438
a6dc60ff
KS		 2439 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2440 /* Set SLV-T Bank : 0x00 */
2441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2442 /* Disable HiZ Setting 1 */
2443 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2444 /* Disable HiZ Setting 2 */
2445 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2446 priv->state = STATE_ACTIVE_TC;
2447 return 0;
2448}
2449
2450static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2451 u32 bandwidth)
2452{
2453 u8 data[2] = { 0x09, 0x54 };
2454
2455 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2456 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2457 /* Set SLV-X Bank : 0x00 */
2458 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2459 /* Set demod mode */
2460 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2461 /* Set SLV-T Bank : 0x00 */
2462 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2463 /* Enable demod clock */
2464 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2465 /* Disable RF level monitor */
2466 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2467 /* Enable ADC clock */
2468 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2469 /* Enable ADC 1 */
2470 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2471 /* xtal freq 20.5MHz */
2472 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2473 /* Enable ADC 4 */
2474 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2475 /* Set SLV-T Bank : 0x10 */
2476 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2477 /* IFAGC gain settings */
2478 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2479 /* Set SLV-T Bank : 0x11 */
2480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2481 /* BBAGC TARGET level setting */
2482 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2483 /* Set SLV-T Bank : 0x10 */
2484 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2485 /* ASCOT setting ON */
2486 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2487 /* Set SLV-T Bank : 0x20 */
2488 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2489 /* Acquisition optimization setting */
2490 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2491 /* Set SLV-T Bank : 0x2b */
2492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2493 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2494 /* Set SLV-T Bank : 0x00 */
2495 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2496 /* TSIF setting */
2497 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2498 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2499 /* DVB-T2 initial setting */
2500 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2501 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2502 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2503 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2504 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2505 /* Set SLV-T Bank : 0x2a */
2506 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2507 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2508 /* Set SLV-T Bank : 0x2b */
2509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2510 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2511
2512 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2513
2514 /* Set SLV-T Bank : 0x00 */
2515 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2516 /* Disable HiZ Setting 1 */
2517 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2518 /* Disable HiZ Setting 2 */
2519 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2520 priv->state = STATE_ACTIVE_TC;
2521 return 0;
2522}
2523
83808c23
AO		 2524/* ISDB-Tb part */
2525static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2526 u32 bandwidth)
2527{
2528 u8 data[2] = { 0x09, 0x54 };
2529 u8 data24m[2] = {0x60, 0x00};
2530 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2531
2532 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2533 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2534 /* Set SLV-X Bank : 0x00 */
2535 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2536 /* Set demod mode */
2537 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2538 /* Set SLV-T Bank : 0x00 */
2539 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2540 /* Enable demod clock */
2541 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2542 /* Enable RF level monitor */
2543 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2544 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2545 /* Enable ADC clock */
2546 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2547 /* Enable ADC 1 */
2548 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2549 /* xtal freq 20.5MHz or 24M */
2550 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2551 /* Enable ADC 4 */
2552 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2553 /* ASCOT setting ON */
2554 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2555 /* FEC Auto Recovery setting */
2556 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2557 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2558 /* ISDB-T initial setting */
2559 /* Set SLV-T Bank : 0x00 */
2560 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2561 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2562 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2563 /* Set SLV-T Bank : 0x10 */
2564 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2565 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2566 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2567 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2568 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2569 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2570 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2571 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2572 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2573 /* Set SLV-T Bank : 0x15 */
2574 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2575 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2576 /* Set SLV-T Bank : 0x1E */
2577 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2578 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2579 /* Set SLV-T Bank : 0x63 */
2580 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2581 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2582
2583 /* for xtal 24MHz */
2584 /* Set SLV-T Bank : 0x10 */
2585 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2586 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2587 /* Set SLV-T Bank : 0x60 */
2588 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2589 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2590
2591 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2592 /* Set SLV-T Bank : 0x00 */
2593 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2594 /* Disable HiZ Setting 1 */
2595 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2596 /* Disable HiZ Setting 2 */
2597 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2598 priv->state = STATE_ACTIVE_TC;
2599 return 0;
2600}
2601
a6dc60ff
KS		 2602static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2603 u32 bandwidth)
2604{
2605 u8 data[2] = { 0x09, 0x54 };
2606
2607 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2608 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2609 /* Set SLV-X Bank : 0x00 */
2610 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2611 /* Set demod mode */
2612 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2613 /* Set SLV-T Bank : 0x00 */
2614 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2615 /* Enable demod clock */
2616 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2617 /* Disable RF level monitor */
2618 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2619 /* Enable ADC clock */
2620 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2621 /* Enable ADC 1 */
2622 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2623 /* xtal freq 20.5MHz */
2624 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2625 /* Enable ADC 4 */
2626 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2627 /* Set SLV-T Bank : 0x10 */
2628 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2629 /* IFAGC gain settings */
2630 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2631 /* Set SLV-T Bank : 0x11 */
2632 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2633 /* BBAGC TARGET level setting */
2634 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2635 /* Set SLV-T Bank : 0x10 */
2636 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2637 /* ASCOT setting ON */
2638 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2639 /* Set SLV-T Bank : 0x40 */
2640 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2641 /* Demod setting */
2642 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2643 /* Set SLV-T Bank : 0x00 */
2644 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2645 /* TSIF setting */
2646 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2647 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2648
2649 cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2650 /* Set SLV-T Bank : 0x00 */
2651 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2652 /* Disable HiZ Setting 1 */
2653 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2654 /* Disable HiZ Setting 2 */
2655 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2656 priv->state = STATE_ACTIVE_TC;
2657 return 0;
2658}
2659
7e3e68bc
MCC		 2660static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2661 struct dtv_frontend_properties *p)
a6dc60ff
KS		 2662{
2663 enum fe_status status = 0;
2664 u16 strength = 0, snr = 0;
2665 u32 errors = 0, ber = 0;
2666 struct cxd2841er_priv *priv = fe->demodulator_priv;
a6dc60ff
KS		 2667
2668 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2669 if (priv->state == STATE_ACTIVE_S)
2670 cxd2841er_read_status_s(fe, &status);
2671 else if (priv->state == STATE_ACTIVE_TC)
2672 cxd2841er_read_status_tc(fe, &status);
2673
2674 if (status & FE_HAS_LOCK) {
2675 cxd2841er_read_signal_strength(fe, &strength);
2676 p->strength.len = 1;
2677 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2678 p->strength.stat[0].uvalue = strength;
2679 cxd2841er_read_snr(fe, &snr);
2680 p->cnr.len = 1;
2681 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2682 p->cnr.stat[0].svalue = snr;
2683 cxd2841er_read_ucblocks(fe, &errors);
2684 p->block_error.len = 1;
2685 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2686 p->block_error.stat[0].uvalue = errors;
2687 cxd2841er_read_ber(fe, &ber);
2688 p->post_bit_error.len = 1;
2689 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2690 p->post_bit_error.stat[0].uvalue = ber;
2691 } else {
2692 p->strength.len = 1;
2693 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2694 p->cnr.len = 1;
2695 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2696 p->block_error.len = 1;
2697 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2698 p->post_bit_error.len = 1;
2699 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2700 }
2701 return 0;
2702}
2703
2704static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2705{
2706 int ret = 0, i, timeout, carr_offset;
2707 enum fe_status status;
2708 struct cxd2841er_priv *priv = fe->demodulator_priv;
2709 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2710 u32 symbol_rate = p->symbol_rate/1000;
2711
83808c23 2712 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
a6dc60ff
KS		 2713 __func__,
2714 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
83808c23 2715 p->frequency, symbol_rate, priv->xtal);
a6dc60ff
KS		 2716 switch (priv->state) {
2717 case STATE_SLEEP_S:
2718 ret = cxd2841er_sleep_s_to_active_s(
2719 priv, p->delivery_system, symbol_rate);
2720 break;
2721 case STATE_ACTIVE_S:
2722 ret = cxd2841er_retune_active(priv, p);
2723 break;
2724 default:
2725 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2726 __func__, priv->state);
2727 ret = -EINVAL;
2728 goto done;
2729 }
2730 if (ret) {
2731 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2732 goto done;
2733 }
2734 if (fe->ops.i2c_gate_ctrl)
2735 fe->ops.i2c_gate_ctrl(fe, 1);
2736 if (fe->ops.tuner_ops.set_params)
2737 fe->ops.tuner_ops.set_params(fe);
2738 if (fe->ops.i2c_gate_ctrl)
2739 fe->ops.i2c_gate_ctrl(fe, 0);
2740 cxd2841er_tune_done(priv);
2741 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2742 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2743 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2744 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2745 cxd2841er_read_status_s(fe, &status);
2746 if (status & FE_HAS_LOCK)
2747 break;
2748 }
2749 if (status & FE_HAS_LOCK) {
2750 if (cxd2841er_get_carrier_offset_s_s2(
2751 priv, &carr_offset)) {
2752 ret = -EINVAL;
2753 goto done;
2754 }
2755 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2756 __func__, carr_offset);
2757 }
2758done:
2759 return ret;
2760}
2761
2762static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2763{
2764 int ret = 0, timeout;
2765 enum fe_status status;
2766 struct cxd2841er_priv *priv = fe->demodulator_priv;
2767 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2768
2769 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2770 if (p->delivery_system == SYS_DVBT) {
2771 priv->system = SYS_DVBT;
2772 switch (priv->state) {
2773 case STATE_SLEEP_TC:
2774 ret = cxd2841er_sleep_tc_to_active_t(
2775 priv, p->bandwidth_hz);
2776 break;
2777 case STATE_ACTIVE_TC:
2778 ret = cxd2841er_retune_active(priv, p);
2779 break;
2780 default:
2781 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2782 __func__, priv->state);
2783 ret = -EINVAL;
2784 }
2785 } else if (p->delivery_system == SYS_DVBT2) {
2786 priv->system = SYS_DVBT2;
2787 cxd2841er_dvbt2_set_plp_config(priv,
2788 (int)(p->stream_id > 255), p->stream_id);
2789 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2790 switch (priv->state) {
2791 case STATE_SLEEP_TC:
2792 ret = cxd2841er_sleep_tc_to_active_t2(priv,
2793 p->bandwidth_hz);
2794 break;
2795 case STATE_ACTIVE_TC:
2796 ret = cxd2841er_retune_active(priv, p);
2797 break;
2798 default:
2799 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2800 __func__, priv->state);
2801 ret = -EINVAL;
2802 }
83808c23
AO		 2803 } else if (p->delivery_system == SYS_ISDBT) {
2804 priv->system = SYS_ISDBT;
2805 switch (priv->state) {
2806 case STATE_SLEEP_TC:
2807 ret = cxd2841er_sleep_tc_to_active_i(
2808 priv, p->bandwidth_hz);
2809 break;
2810 case STATE_ACTIVE_TC:
2811 ret = cxd2841er_retune_active(priv, p);
2812 break;
2813 default:
2814 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2815 __func__, priv->state);
2816 ret = -EINVAL;
2817 }
a6dc60ff
KS		 2818 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2819 p->delivery_system == SYS_DVBC_ANNEX_C) {
2820 priv->system = SYS_DVBC_ANNEX_A;
2821 switch (priv->state) {
2822 case STATE_SLEEP_TC:
2823 ret = cxd2841er_sleep_tc_to_active_c(
2824 priv, p->bandwidth_hz);
2825 break;
2826 case STATE_ACTIVE_TC:
2827 ret = cxd2841er_retune_active(priv, p);
2828 break;
2829 default:
2830 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2831 __func__, priv->state);
2832 ret = -EINVAL;
2833 }
2834 } else {
2835 dev_dbg(&priv->i2c->dev,
2836 "%s(): invalid delivery system %d\n",
2837 __func__, p->delivery_system);
2838 ret = -EINVAL;
2839 }
2840 if (ret)
2841 goto done;
2842 if (fe->ops.i2c_gate_ctrl)
2843 fe->ops.i2c_gate_ctrl(fe, 1);
2844 if (fe->ops.tuner_ops.set_params)
2845 fe->ops.tuner_ops.set_params(fe);
2846 if (fe->ops.i2c_gate_ctrl)
2847 fe->ops.i2c_gate_ctrl(fe, 0);
2848 cxd2841er_tune_done(priv);
2849 timeout = 2500;
2850 while (timeout > 0) {
2851 ret = cxd2841er_read_status_tc(fe, &status);
2852 if (ret)
2853 goto done;
2854 if (status & FE_HAS_LOCK)
2855 break;
2856 msleep(20);
2857 timeout -= 20;
2858 }
2859 if (timeout < 0)
2860 dev_dbg(&priv->i2c->dev,
2861 "%s(): LOCK wait timeout\n", __func__);
2862done:
2863 return ret;
2864}
2865
2866static int cxd2841er_tune_s(struct dvb_frontend *fe,
2867 bool re_tune,
2868 unsigned int mode_flags,
2869 unsigned int *delay,
2870 enum fe_status *status)
2871{
2872 int ret, carrier_offset;
2873 struct cxd2841er_priv *priv = fe->demodulator_priv;
2874 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2875
2876 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2877 if (re_tune) {
2878 ret = cxd2841er_set_frontend_s(fe);
2879 if (ret)
2880 return ret;
2881 cxd2841er_read_status_s(fe, status);
2882 if (*status & FE_HAS_LOCK) {
2883 if (cxd2841er_get_carrier_offset_s_s2(
2884 priv, &carrier_offset))
2885 return -EINVAL;
2886 p->frequency += carrier_offset;
2887 ret = cxd2841er_set_frontend_s(fe);
2888 if (ret)
2889 return ret;
2890 }
2891 }
2892 *delay = HZ / 5;
2893 return cxd2841er_read_status_s(fe, status);
2894}
2895
2896static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2897 bool re_tune,
2898 unsigned int mode_flags,
2899 unsigned int *delay,
2900 enum fe_status *status)
2901{
2902 int ret, carrier_offset;
2903 struct cxd2841er_priv *priv = fe->demodulator_priv;
2904 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2905
2906 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2907 if (re_tune) {
2908 ret = cxd2841er_set_frontend_tc(fe);
2909 if (ret)
2910 return ret;
2911 cxd2841er_read_status_tc(fe, status);
2912 if (*status & FE_HAS_LOCK) {
2913 switch (priv->system) {
2914 case SYS_DVBT:
2915 case SYS_DVBT2:
2916 ret = cxd2841er_get_carrier_offset_t2(
2917 priv, p->bandwidth_hz,
2918 &carrier_offset);
2919 break;
2920 case SYS_DVBC_ANNEX_A:
2921 ret = cxd2841er_get_carrier_offset_c(
2922 priv, &carrier_offset);
2923 break;
2924 default:
2925 dev_dbg(&priv->i2c->dev,
2926 "%s(): invalid delivery system %d\n",
2927 __func__, priv->system);
2928 return -EINVAL;
2929 }
2930 if (ret)
2931 return ret;
2932 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
2933 __func__, carrier_offset);
2934 p->frequency += carrier_offset;
2935 ret = cxd2841er_set_frontend_tc(fe);
2936 if (ret)
2937 return ret;
2938 }
2939 }
2940 *delay = HZ / 5;
2941 return cxd2841er_read_status_tc(fe, status);
2942}
2943
2944static int cxd2841er_sleep_s(struct dvb_frontend *fe)
2945{
2946 struct cxd2841er_priv *priv = fe->demodulator_priv;
2947
2948 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2949 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
2950 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
2951 return 0;
2952}
2953
2954static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
2955{
2956 struct cxd2841er_priv *priv = fe->demodulator_priv;
2957
2958 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2959 if (priv->state == STATE_ACTIVE_TC) {
2960 switch (priv->system) {
2961 case SYS_DVBT:
2962 cxd2841er_active_t_to_sleep_tc(priv);
2963 break;
2964 case SYS_DVBT2:
2965 cxd2841er_active_t2_to_sleep_tc(priv);
2966 break;
83808c23
AO		 2967 case SYS_ISDBT:
2968 cxd2841er_active_i_to_sleep_tc(priv);
2969 break;
a6dc60ff
KS		 2970 case SYS_DVBC_ANNEX_A:
2971 cxd2841er_active_c_to_sleep_tc(priv);
2972 break;
2973 default:
2974 dev_warn(&priv->i2c->dev,
2975 "%s(): unknown delivery system %d\n",
2976 __func__, priv->system);
2977 }
2978 }
2979 if (priv->state != STATE_SLEEP_TC) {
2980 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
2981 __func__, priv->state);
2982 return -EINVAL;
2983 }
2984 cxd2841er_sleep_tc_to_shutdown(priv);
2985 return 0;
2986}
2987
2988static int cxd2841er_send_burst(struct dvb_frontend *fe,
2989 enum fe_sec_mini_cmd burst)
2990{
2991 u8 data;
2992 struct cxd2841er_priv *priv = fe->demodulator_priv;
2993
2994 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
2995 (burst == SEC_MINI_A ? "A" : "B"));
2996 if (priv->state != STATE_SLEEP_S &&
2997 priv->state != STATE_ACTIVE_S) {
2998 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2999 __func__, priv->state);
3000 return -EINVAL;
3001 }
3002 data = (burst == SEC_MINI_A ? 0 : 1);
3003 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3004 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3005 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3006 return 0;
3007}
3008
3009static int cxd2841er_set_tone(struct dvb_frontend *fe,
3010 enum fe_sec_tone_mode tone)
3011{
3012 u8 data;
3013 struct cxd2841er_priv *priv = fe->demodulator_priv;
3014
3015 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3016 (tone == SEC_TONE_ON ? "On" : "Off"));
3017 if (priv->state != STATE_SLEEP_S &&
3018 priv->state != STATE_ACTIVE_S) {
3019 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3020 __func__, priv->state);
3021 return -EINVAL;
3022 }
3023 data = (tone == SEC_TONE_ON ? 1 : 0);
3024 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3025 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3026 return 0;
3027}
3028
3029static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3030 struct dvb_diseqc_master_cmd *cmd)
3031{
3032 int i;
3033 u8 data[12];
3034 struct cxd2841er_priv *priv = fe->demodulator_priv;
3035
3036 if (priv->state != STATE_SLEEP_S &&
3037 priv->state != STATE_ACTIVE_S) {
3038 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3039 __func__, priv->state);
3040 return -EINVAL;
3041 }
3042 dev_dbg(&priv->i2c->dev,
3043 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3044 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3045 /* DiDEqC enable */
3046 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3047 /* cmd1 length & data */
3048 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3049 memset(data, 0, sizeof(data));
3050 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3051 data[i] = cmd->msg[i];
3052 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3053 /* repeat count for cmd1 */
3054 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3055 /* repeat count for cmd2: always 0 */
3056 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3057 /* start transmit */
3058 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3059 /* wait for 1 sec timeout */
3060 for (i = 0; i < 50; i++) {
3061 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3062 if (!data[0]) {
3063 dev_dbg(&priv->i2c->dev,
3064 "%s(): DiSEqC cmd has been sent\n", __func__);
3065 return 0;
3066 }
3067 msleep(20);
3068 }
3069 dev_dbg(&priv->i2c->dev,
3070 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3071 return -ETIMEDOUT;
3072}
3073
3074static void cxd2841er_release(struct dvb_frontend *fe)
3075{
3076 struct cxd2841er_priv *priv = fe->demodulator_priv;
3077
3078 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3079 kfree(priv);
3080}
3081
3082static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3083{
3084 struct cxd2841er_priv *priv = fe->demodulator_priv;
3085
3086 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3087 cxd2841er_set_reg_bits(
3088 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3089 return 0;
3090}
3091
3092static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3093{
3094 struct cxd2841er_priv *priv = fe->demodulator_priv;
3095
3096 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3097 return DVBFE_ALGO_HW;
3098}
3099
3100static int cxd2841er_init_s(struct dvb_frontend *fe)
3101{
3102 struct cxd2841er_priv *priv = fe->demodulator_priv;
3103
3104 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3105 cxd2841er_shutdown_to_sleep_s(priv);
3106 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3107 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3108 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3109 return 0;
3110}
3111
3112static int cxd2841er_init_tc(struct dvb_frontend *fe)
3113{
3114 struct cxd2841er_priv *priv = fe->demodulator_priv;
3115
3116 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3117 cxd2841er_shutdown_to_sleep_tc(priv);
3118 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3119 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3120 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3121 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3122 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3123 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3124 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3125 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3126 return 0;
3127}
3128
3129static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3130static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
3131static struct dvb_frontend_ops cxd2841er_dvbc_ops;
83808c23 3132static struct dvb_frontend_ops cxd2841er_isdbt_ops;
a6dc60ff
KS		 3133
3134static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3135 struct i2c_adapter *i2c,
3136 u8 system)
3137{
3138 u8 chip_id = 0;
3139 const char *type;
3140 struct cxd2841er_priv *priv = NULL;
3141
3142 /* allocate memory for the internal state */
3143 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3144 if (!priv)
3145 return NULL;
3146 priv->i2c = i2c;
3147 priv->config = cfg;
3148 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3149 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
83808c23 3150 priv->xtal = cfg->xtal;
a6dc60ff
KS		 3151 /* create dvb_frontend */
3152 switch (system) {
3153 case SYS_DVBS:
3154 memcpy(&priv->frontend.ops,
3155 &cxd2841er_dvbs_s2_ops,
3156 sizeof(struct dvb_frontend_ops));
3157 type = "S/S2";
3158 break;
3159 case SYS_DVBT:
3160 memcpy(&priv->frontend.ops,
3161 &cxd2841er_dvbt_t2_ops,
3162 sizeof(struct dvb_frontend_ops));
3163 type = "T/T2";
3164 break;
83808c23
AO		 3165 case SYS_ISDBT:
3166 memcpy(&priv->frontend.ops,
3167 &cxd2841er_isdbt_ops,
3168 sizeof(struct dvb_frontend_ops));
3169 type = "ISDBT";
3170 break;
a6dc60ff
KS		 3171 case SYS_DVBC_ANNEX_A:
3172 memcpy(&priv->frontend.ops,
3173 &cxd2841er_dvbc_ops,
3174 sizeof(struct dvb_frontend_ops));
3175 type = "C/C2";
3176 break;
3177 default:
3178 kfree(priv);
3179 return NULL;
3180 }
3181 priv->frontend.demodulator_priv = priv;
3182 dev_info(&priv->i2c->dev,
3183 "%s(): attaching CXD2841ER DVB-%s frontend\n",
3184 __func__, type);
3185 dev_info(&priv->i2c->dev,
3186 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3187 __func__, priv->i2c,
3188 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3189 chip_id = cxd2841er_chip_id(priv);
83808c23 3190 if (chip_id != CXD2841ER_CHIP_ID && chip_id != CXD2854ER_CHIP_ID) {
a6dc60ff
KS		 3191 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3192 __func__, chip_id);
3193 priv->frontend.demodulator_priv = NULL;
3194 kfree(priv);
3195 return NULL;
3196 }
3197 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3198 __func__, chip_id);
3199 return &priv->frontend;
3200}
3201
3202struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3203 struct i2c_adapter *i2c)
3204{
3205 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3206}
3207EXPORT_SYMBOL(cxd2841er_attach_s);
3208
3209struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
3210 struct i2c_adapter *i2c)
3211{
3212 return cxd2841er_attach(cfg, i2c, SYS_DVBT);
3213}
3214EXPORT_SYMBOL(cxd2841er_attach_t);
3215
83808c23
AO		 3216struct dvb_frontend *cxd2841er_attach_i(struct cxd2841er_config *cfg,
3217 struct i2c_adapter *i2c)
3218{
3219 return cxd2841er_attach(cfg, i2c, SYS_ISDBT);
3220}
3221EXPORT_SYMBOL(cxd2841er_attach_i);
3222
a6dc60ff
KS		 3223struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
3224 struct i2c_adapter *i2c)
3225{
3226 return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
3227}
3228EXPORT_SYMBOL(cxd2841er_attach_c);
3229
3230static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3231 .delsys = { SYS_DVBS, SYS_DVBS2 },
3232 .info = {
3233 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3234 .frequency_min = 500000,
3235 .frequency_max = 2500000,
3236 .frequency_stepsize = 0,
3237 .symbol_rate_min = 1000000,
3238 .symbol_rate_max = 45000000,
3239 .symbol_rate_tolerance = 500,
3240 .caps = FE_CAN_INVERSION_AUTO |
3241 FE_CAN_FEC_AUTO |
3242 FE_CAN_QPSK,
3243 },
3244 .init = cxd2841er_init_s,
3245 .sleep = cxd2841er_sleep_s,
3246 .release = cxd2841er_release,
3247 .set_frontend = cxd2841er_set_frontend_s,
3248 .get_frontend = cxd2841er_get_frontend,
3249 .read_status = cxd2841er_read_status_s,
3250 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3251 .get_frontend_algo = cxd2841er_get_algo,
3252 .set_tone = cxd2841er_set_tone,
3253 .diseqc_send_burst = cxd2841er_send_burst,
3254 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3255 .tune = cxd2841er_tune_s
3256};
3257
3258static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
3259 .delsys = { SYS_DVBT, SYS_DVBT2 },
3260 .info = {
3261 .name = "Sony CXD2841ER DVB-T/T2 demodulator",
3262 .caps = FE_CAN_FEC_1_2 |
3263 FE_CAN_FEC_2_3 |
3264 FE_CAN_FEC_3_4 |
3265 FE_CAN_FEC_5_6 |
3266 FE_CAN_FEC_7_8 |
3267 FE_CAN_FEC_AUTO |
3268 FE_CAN_QPSK |
3269 FE_CAN_QAM_16 |
3270 FE_CAN_QAM_32 |
3271 FE_CAN_QAM_64 |
3272 FE_CAN_QAM_128 |
3273 FE_CAN_QAM_256 |
3274 FE_CAN_QAM_AUTO |
3275 FE_CAN_TRANSMISSION_MODE_AUTO |
3276 FE_CAN_GUARD_INTERVAL_AUTO |
3277 FE_CAN_HIERARCHY_AUTO |
3278 FE_CAN_MUTE_TS |
3279 FE_CAN_2G_MODULATION,
3280 .frequency_min = 42000000,
3281 .frequency_max = 1002000000
3282 },
3283 .init = cxd2841er_init_tc,
3284 .sleep = cxd2841er_sleep_tc,
3285 .release = cxd2841er_release,
3286 .set_frontend = cxd2841er_set_frontend_tc,
3287 .get_frontend = cxd2841er_get_frontend,
3288 .read_status = cxd2841er_read_status_tc,
3289 .tune = cxd2841er_tune_tc,
3290 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3291 .get_frontend_algo = cxd2841er_get_algo
3292};
3293
83808c23
AO		 3294static struct dvb_frontend_ops cxd2841er_isdbt_ops = {
3295 .delsys = { SYS_ISDBT },
3296 .info = {
3297 .name = "Sony CXD2854ER ISDBT demodulator",
3298 .caps = FE_CAN_FEC_1_2 |
3299 FE_CAN_FEC_2_3 |
3300 FE_CAN_FEC_3_4 |
3301 FE_CAN_FEC_5_6 |
3302 FE_CAN_FEC_7_8 |
3303 FE_CAN_FEC_AUTO |
3304 FE_CAN_QPSK |
3305 FE_CAN_QAM_16 |
3306 FE_CAN_QAM_32 |
3307 FE_CAN_QAM_64 |
3308 FE_CAN_QAM_128 |
3309 FE_CAN_QAM_256 |
3310 FE_CAN_QAM_AUTO |
3311 FE_CAN_TRANSMISSION_MODE_AUTO |
3312 FE_CAN_GUARD_INTERVAL_AUTO |
3313 FE_CAN_HIERARCHY_AUTO |
3314 FE_CAN_MUTE_TS |
3315 FE_CAN_2G_MODULATION,
3316 .frequency_min = 42000000,
3317 .frequency_max = 1002000000
3318 },
3319 .init = cxd2841er_init_tc,
3320 .sleep = cxd2841er_sleep_tc,
3321 .release = cxd2841er_release,
3322 .set_frontend = cxd2841er_set_frontend_tc,
3323 .get_frontend = cxd2841er_get_frontend,
3324 .read_status = cxd2841er_read_status_tc,
3325 .tune = cxd2841er_tune_tc,
3326 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3327 .get_frontend_algo = cxd2841er_get_algo
3328};
3329
a6dc60ff
KS		 3330static struct dvb_frontend_ops cxd2841er_dvbc_ops = {
3331 .delsys = { SYS_DVBC_ANNEX_A },
3332 .info = {
3333 .name = "Sony CXD2841ER DVB-C demodulator",
3334 .caps = FE_CAN_FEC_1_2 |
3335 FE_CAN_FEC_2_3 |
3336 FE_CAN_FEC_3_4 |
3337 FE_CAN_FEC_5_6 |
3338 FE_CAN_FEC_7_8 |
3339 FE_CAN_FEC_AUTO |
3340 FE_CAN_QAM_16 |
3341 FE_CAN_QAM_32 |
3342 FE_CAN_QAM_64 |
3343 FE_CAN_QAM_128 |
3344 FE_CAN_QAM_256 |
3345 FE_CAN_QAM_AUTO |
3346 FE_CAN_INVERSION_AUTO,
3347 .frequency_min = 42000000,
3348 .frequency_max = 1002000000
3349 },
3350 .init = cxd2841er_init_tc,
3351 .sleep = cxd2841er_sleep_tc,
3352 .release = cxd2841er_release,
3353 .set_frontend = cxd2841er_set_frontend_tc,
3354 .get_frontend = cxd2841er_get_frontend,
3355 .read_status = cxd2841er_read_status_tc,
3356 .tune = cxd2841er_tune_tc,
3357 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3358 .get_frontend_algo = cxd2841er_get_algo,
3359};
3360
83808c23
AO		 3361MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3362MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
a6dc60ff 3363MODULE_LICENSE("GPL");
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