]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/media/dvb-frontends/cxd2841er.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] Fix DVB-T frequency offset calculation
[mirror_ubuntu-zesty-kernel.git] / drivers / media / dvb-frontends / cxd2841er.c
CommitLineData
a6dc60ff
KS		 1/*
2 * cxd2841er.c
3 *
83808c23
AO		 4 * Sony digital demodulator driver for
5 * CXD2441ER - DVB-S/S2/T/T2/C/C2
6 * CXD2454ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
a6dc60ff
KS		 7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
d13a7b67
MCC		 38#define MAX_WRITE_REGSIZE 16
39
a6dc60ff
KS		 40enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46};
47
48struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
83808c23 56 enum cxd2841er_xtal xtal;
a6dc60ff
KS		 57};
58
59static const struct cxd2841er_cnr_data s_cn_data[] = {
60 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
61 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
62 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
63 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
64 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
65 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
66 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
67 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
68 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
69 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
70 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
71 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
72 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
73 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
74 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
75 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
76 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
77 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
78 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
79 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
80 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
81 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
82 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
83 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
84 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
85 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
86 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
87 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
88 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
89 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
90 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
91 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
92 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
93 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
94 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
95 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
96 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
97 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
98 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
99 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
100 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
101 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
102 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
103 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
104 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
105 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
106 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
107 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
108 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
109 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
110 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
111 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
112 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
113 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
114 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
115 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
116 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
117 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
118 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
119 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
120 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
121 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
122 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
123 { 0x0015, 19900 }, { 0x0014, 20000 },
124};
125
126static const struct cxd2841er_cnr_data s2_cn_data[] = {
127 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
128 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
129 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
130 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
131 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
132 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
133 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
134 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
135 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
136 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
137 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
138 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
139 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
140 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
141 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
142 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
143 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
144 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
145 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
146 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
147 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
148 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
149 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
150 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
151 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
152 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
153 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
154 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
155 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
156 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
157 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
158 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
159 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
160 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
161 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
162 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
163 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
164 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
165 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
166 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
167 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
168 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
169 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
170 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
171 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
172 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
173 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
174 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
175 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
176 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
177 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
178 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
179 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
180 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
181 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
182 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
183 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
184 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
185 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
186 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
187 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
188 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
189 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
190 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
191};
192
193#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
83808c23
AO		 194#define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
195 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
196 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
a6dc60ff
KS		 197
198static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
199 u8 addr, u8 reg, u8 write,
200 const u8 *data, u32 len)
201{
202 dev_dbg(&priv->i2c->dev,
203 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
204 (write == 0 ? "read" : "write"), addr, reg, len);
205 print_hex_dump_bytes("cxd2841er: I2C data: ",
206 DUMP_PREFIX_OFFSET, data, len);
207}
208
209static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
210 u8 addr, u8 reg, const u8 *data, u32 len)
211{
212 int ret;
d13a7b67 213 u8 buf[MAX_WRITE_REGSIZE + 1];
a6dc60ff
KS		 214 u8 i2c_addr = (addr == I2C_SLVX ?
215 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
216 struct i2c_msg msg[1] = {
217 {
218 .addr = i2c_addr,
219 .flags = 0,
d13a7b67 220 .len = len + 1,
a6dc60ff
KS		 221 .buf = buf,
222 }
223 };
224
d13a7b67 225 if (len + 1 >= sizeof(buf)) {
83808c23 226 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
d13a7b67
MCC		 227 reg, len + 1);
228 return -E2BIG;
229 }
230
a6dc60ff
KS		 231 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
232 buf[0] = reg;
233 memcpy(&buf[1], data, len);
234
235 ret = i2c_transfer(priv->i2c, msg, 1);
236 if (ret >= 0 && ret != 1)
237 ret = -EIO;
238 if (ret < 0) {
239 dev_warn(&priv->i2c->dev,
240 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
241 KBUILD_MODNAME, ret, i2c_addr, reg, len);
242 return ret;
243 }
244 return 0;
245}
246
247static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
248 u8 addr, u8 reg, u8 val)
249{
250 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
251}
252
253static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
254 u8 addr, u8 reg, u8 *val, u32 len)
255{
256 int ret;
257 u8 i2c_addr = (addr == I2C_SLVX ?
258 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
259 struct i2c_msg msg[2] = {
260 {
261 .addr = i2c_addr,
262 .flags = 0,
263 .len = 1,
264 .buf = &reg,
265 }, {
266 .addr = i2c_addr,
267 .flags = I2C_M_RD,
268 .len = len,
269 .buf = val,
270 }
271 };
272
273 ret = i2c_transfer(priv->i2c, &msg[0], 1);
274 if (ret >= 0 && ret != 1)
275 ret = -EIO;
276 if (ret < 0) {
277 dev_warn(&priv->i2c->dev,
278 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
279 KBUILD_MODNAME, ret, i2c_addr, reg);
280 return ret;
281 }
282 ret = i2c_transfer(priv->i2c, &msg[1], 1);
283 if (ret >= 0 && ret != 1)
284 ret = -EIO;
285 if (ret < 0) {
286 dev_warn(&priv->i2c->dev,
287 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
288 KBUILD_MODNAME, ret, i2c_addr, reg);
289 return ret;
290 }
291 return 0;
292}
293
294static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
295 u8 addr, u8 reg, u8 *val)
296{
297 return cxd2841er_read_regs(priv, addr, reg, val, 1);
298}
299
300static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
301 u8 addr, u8 reg, u8 data, u8 mask)
302{
303 int res;
304 u8 rdata;
305
306 if (mask != 0xff) {
307 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
308 if (res)
309 return res;
310 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
311 }
312 return cxd2841er_write_reg(priv, addr, reg, data);
313}
314
315static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
316 u32 symbol_rate)
317{
318 u32 reg_value = 0;
319 u8 data[3] = {0, 0, 0};
320
321 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
322 /*
323 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
324 * = ((symbolRateKSps * 2^14) + 500) / 1000
325 * = ((symbolRateKSps * 16384) + 500) / 1000
326 */
327 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
328 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
329 dev_err(&priv->i2c->dev,
330 "%s(): reg_value is out of range\n", __func__);
331 return -EINVAL;
332 }
333 data[0] = (u8)((reg_value >> 16) & 0x0F);
334 data[1] = (u8)((reg_value >> 8) & 0xFF);
335 data[2] = (u8)(reg_value & 0xFF);
336 /* Set SLV-T Bank : 0xAE */
337 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
338 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
339 return 0;
340}
341
342static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
343 u8 system);
344
345static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
346 u8 system, u32 symbol_rate)
347{
348 int ret;
349 u8 data[4] = { 0, 0, 0, 0 };
350
351 if (priv->state != STATE_SLEEP_S) {
352 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
353 __func__, (int)priv->state);
354 return -EINVAL;
355 }
356 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
357 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
358 /* Set demod mode */
359 if (system == SYS_DVBS) {
360 data[0] = 0x0A;
361 } else if (system == SYS_DVBS2) {
362 data[0] = 0x0B;
363 } else {
364 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
365 __func__, system);
366 return -EINVAL;
367 }
368 /* Set SLV-X Bank : 0x00 */
369 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
370 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
371 /* DVB-S/S2 */
372 data[0] = 0x00;
373 /* Set SLV-T Bank : 0x00 */
374 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
375 /* Enable S/S2 auto detection 1 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
377 /* Set SLV-T Bank : 0xAE */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
379 /* Enable S/S2 auto detection 2 */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
381 /* Set SLV-T Bank : 0x00 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
383 /* Enable demod clock */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
385 /* Enable ADC clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
387 /* Enable ADC 1 */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
389 /* Enable ADC 2 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
391 /* Set SLV-X Bank : 0x00 */
392 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
393 /* Enable ADC 3 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
395 /* Set SLV-T Bank : 0xA3 */
396 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
397 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
398 data[0] = 0x07;
399 data[1] = 0x3B;
400 data[2] = 0x08;
401 data[3] = 0xC5;
402 /* Set SLV-T Bank : 0xAB */
403 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
404 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
405 data[0] = 0x05;
406 data[1] = 0x80;
407 data[2] = 0x0A;
408 data[3] = 0x80;
409 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
410 data[0] = 0x0C;
411 data[1] = 0xCC;
412 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
413 /* Set demod parameter */
414 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
415 if (ret != 0)
416 return ret;
417 /* Set SLV-T Bank : 0x00 */
418 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
419 /* disable Hi-Z setting 1 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
421 /* disable Hi-Z setting 2 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
423 priv->state = STATE_ACTIVE_S;
424 return 0;
425}
426
427static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
428 u32 bandwidth);
429
430static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
431 u32 bandwidth);
432
433static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
434 u32 bandwidth);
435
436static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
437 struct dtv_frontend_properties *p)
438{
439 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
440 if (priv->state != STATE_ACTIVE_S &&
441 priv->state != STATE_ACTIVE_TC) {
442 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
443 __func__, priv->state);
444 return -EINVAL;
445 }
446 /* Set SLV-T Bank : 0x00 */
447 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
448 /* disable TS output */
449 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
450 if (priv->state == STATE_ACTIVE_S)
451 return cxd2841er_dvbs2_set_symbol_rate(
452 priv, p->symbol_rate / 1000);
453 else if (priv->state == STATE_ACTIVE_TC) {
454 switch (priv->system) {
455 case SYS_DVBT:
456 return cxd2841er_sleep_tc_to_active_t_band(
457 priv, p->bandwidth_hz);
458 case SYS_DVBT2:
459 return cxd2841er_sleep_tc_to_active_t2_band(
460 priv, p->bandwidth_hz);
461 case SYS_DVBC_ANNEX_A:
462 return cxd2841er_sleep_tc_to_active_c_band(
463 priv, 8000000);
464 }
465 }
466 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
467 __func__, priv->system);
468 return -EINVAL;
469}
470
471static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
472{
473 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
474 if (priv->state != STATE_ACTIVE_S) {
475 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
476 __func__, priv->state);
477 return -EINVAL;
478 }
479 /* Set SLV-T Bank : 0x00 */
480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
481 /* disable TS output */
482 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
483 /* enable Hi-Z setting 1 */
484 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
485 /* enable Hi-Z setting 2 */
486 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
487 /* Set SLV-X Bank : 0x00 */
488 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
489 /* disable ADC 1 */
490 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
491 /* Set SLV-T Bank : 0x00 */
492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
493 /* disable ADC clock */
494 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
495 /* disable ADC 2 */
496 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
497 /* disable ADC 3 */
498 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
499 /* SADC Bias ON */
500 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
501 /* disable demod clock */
502 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
503 /* Set SLV-T Bank : 0xAE */
504 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
505 /* disable S/S2 auto detection1 */
506 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
507 /* Set SLV-T Bank : 0x00 */
508 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
509 /* disable S/S2 auto detection2 */
510 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
511 priv->state = STATE_SLEEP_S;
512 return 0;
513}
514
515static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
516{
517 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
518 if (priv->state != STATE_SLEEP_S) {
519 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
520 __func__, priv->state);
521 return -EINVAL;
522 }
523 /* Set SLV-T Bank : 0x00 */
524 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
525 /* Disable DSQOUT */
526 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
527 /* Disable DSQIN */
528 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
529 /* Set SLV-X Bank : 0x00 */
530 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
531 /* Disable oscillator */
532 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
533 /* Set demod mode */
534 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
535 priv->state = STATE_SHUTDOWN;
536 return 0;
537}
538
539static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
540{
541 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
542 if (priv->state != STATE_SLEEP_TC) {
543 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
544 __func__, priv->state);
545 return -EINVAL;
546 }
547 /* Set SLV-X Bank : 0x00 */
548 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
549 /* Disable oscillator */
550 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
551 /* Set demod mode */
552 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
553 priv->state = STATE_SHUTDOWN;
554 return 0;
555}
556
557static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
558{
559 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
560 if (priv->state != STATE_ACTIVE_TC) {
561 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
562 __func__, priv->state);
563 return -EINVAL;
564 }
565 /* Set SLV-T Bank : 0x00 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
567 /* disable TS output */
568 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
569 /* enable Hi-Z setting 1 */
570 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
571 /* enable Hi-Z setting 2 */
572 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
573 /* Set SLV-X Bank : 0x00 */
574 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
575 /* disable ADC 1 */
576 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
577 /* Set SLV-T Bank : 0x00 */
578 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
579 /* Disable ADC 2 */
580 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
581 /* Disable ADC 3 */
582 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
583 /* Disable ADC clock */
584 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
585 /* Disable RF level monitor */
586 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
587 /* Disable demod clock */
588 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
589 priv->state = STATE_SLEEP_TC;
590 return 0;
591}
592
593static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
594{
595 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
596 if (priv->state != STATE_ACTIVE_TC) {
597 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
598 __func__, priv->state);
599 return -EINVAL;
600 }
601 /* Set SLV-T Bank : 0x00 */
602 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
603 /* disable TS output */
604 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
605 /* enable Hi-Z setting 1 */
606 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
607 /* enable Hi-Z setting 2 */
608 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
609 /* Cancel DVB-T2 setting */
610 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
611 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
612 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
613 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
614 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
615 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
616 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
617 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
618 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
619 /* Set SLV-X Bank : 0x00 */
620 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
621 /* disable ADC 1 */
622 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
623 /* Set SLV-T Bank : 0x00 */
624 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
625 /* Disable ADC 2 */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
627 /* Disable ADC 3 */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
629 /* Disable ADC clock */
630 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
631 /* Disable RF level monitor */
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
633 /* Disable demod clock */
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
635 priv->state = STATE_SLEEP_TC;
636 return 0;
637}
638
639static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
640{
641 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
642 if (priv->state != STATE_ACTIVE_TC) {
643 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
644 __func__, priv->state);
645 return -EINVAL;
646 }
647 /* Set SLV-T Bank : 0x00 */
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
649 /* disable TS output */
650 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
651 /* enable Hi-Z setting 1 */
652 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
653 /* enable Hi-Z setting 2 */
654 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
655 /* Cancel DVB-C setting */
656 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
657 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
658 /* Set SLV-X Bank : 0x00 */
659 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
660 /* disable ADC 1 */
661 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
662 /* Set SLV-T Bank : 0x00 */
663 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
664 /* Disable ADC 2 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
666 /* Disable ADC 3 */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
668 /* Disable ADC clock */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
670 /* Disable RF level monitor */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
672 /* Disable demod clock */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
674 priv->state = STATE_SLEEP_TC;
675 return 0;
676}
677
83808c23
AO		 678static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
679{
680 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
681 if (priv->state != STATE_ACTIVE_TC) {
682 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
683 __func__, priv->state);
684 return -EINVAL;
685 }
686 /* Set SLV-T Bank : 0x00 */
687 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
688 /* disable TS output */
689 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
690 /* enable Hi-Z setting 1 */
691 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
692 /* enable Hi-Z setting 2 */
693 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
694
695 /* TODO: Cancel demod parameter */
696
697 /* Set SLV-X Bank : 0x00 */
698 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
699 /* disable ADC 1 */
700 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
701 /* Set SLV-T Bank : 0x00 */
702 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
703 /* Disable ADC 2 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
705 /* Disable ADC 3 */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
707 /* Disable ADC clock */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
709 /* Disable RF level monitor */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
711 /* Disable demod clock */
712 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
713 priv->state = STATE_SLEEP_TC;
714 return 0;
715}
716
a6dc60ff
KS		 717static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
718{
719 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
720 if (priv->state != STATE_SHUTDOWN) {
721 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
722 __func__, priv->state);
723 return -EINVAL;
724 }
725 /* Set SLV-X Bank : 0x00 */
726 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
727 /* Clear all demodulator registers */
728 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
729 usleep_range(3000, 5000);
730 /* Set SLV-X Bank : 0x00 */
731 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
732 /* Set demod SW reset */
733 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
83808c23
AO		 734
735 switch (priv->xtal) {
736 case SONY_XTAL_20500:
737 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
738 break;
739 case SONY_XTAL_24000:
740 /* Select demod frequency */
741 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
742 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
743 break;
744 case SONY_XTAL_41000:
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
746 break;
747 default:
748 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
749 __func__, priv->xtal);
750 return -EINVAL;
751 }
752
a6dc60ff
KS		 753 /* Set demod mode */
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
755 /* Clear demod SW reset */
756 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
757 usleep_range(1000, 2000);
758 /* Set SLV-T Bank : 0x00 */
759 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
760 /* enable DSQOUT */
761 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
762 /* enable DSQIN */
763 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
764 /* TADC Bias On */
765 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
766 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
767 /* SADC Bias On */
768 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
769 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
770 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
771 priv->state = STATE_SLEEP_S;
772 return 0;
773}
774
775static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
776{
777 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
778 if (priv->state != STATE_SHUTDOWN) {
779 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
780 __func__, priv->state);
781 return -EINVAL;
782 }
783 /* Set SLV-X Bank : 0x00 */
784 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
785 /* Clear all demodulator registers */
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
787 usleep_range(3000, 5000);
788 /* Set SLV-X Bank : 0x00 */
789 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
790 /* Set demod SW reset */
791 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
792 /* Set X'tal clock to 20.5Mhz */
793 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
794 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
795 /* Clear demod SW reset */
796 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
797 usleep_range(1000, 2000);
798 /* Set SLV-T Bank : 0x00 */
799 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
800 /* TADC Bias On */
801 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
802 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
803 /* SADC Bias On */
804 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
805 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
806 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
807 priv->state = STATE_SLEEP_TC;
808 return 0;
809}
810
811static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
812{
813 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
814 /* Set SLV-T Bank : 0x00 */
815 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
816 /* SW Reset */
817 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
818 /* Enable TS output */
819 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
820 return 0;
821}
822
823/* Set TS parallel mode */
824static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
825 u8 system)
826{
827 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
828
829 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
830 /* Set SLV-T Bank : 0x00 */
831 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
832 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
833 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
834 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
835 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
836 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
837
838 /*
839 * slave Bank Addr Bit default Name
840 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
841 */
842 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
843 /*
844 * Disable TS IF Clock
845 * slave Bank Addr Bit default Name
846 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
847 */
848 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
849 /*
850 * slave Bank Addr Bit default Name
851 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
852 */
853 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
854 /*
855 * Enable TS IF Clock
856 * slave Bank Addr Bit default Name
857 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
858 */
859 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
860
861 if (system == SYS_DVBT) {
862 /* Enable parity period for DVB-T */
863 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
864 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
865 } else if (system == SYS_DVBC_ANNEX_A) {
866 /* Enable parity period for DVB-C */
867 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
868 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
869 }
870}
871
872static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
873{
83808c23 874 u8 chip_id = 0;
a6dc60ff
KS		 875
876 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
83808c23
AO		 877 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
878 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
879 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
880 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
881
a6dc60ff
KS		 882 return chip_id;
883}
884
885static int cxd2841er_read_status_s(struct dvb_frontend *fe,
886 enum fe_status *status)
887{
888 u8 reg = 0;
889 struct cxd2841er_priv *priv = fe->demodulator_priv;
890
891 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
892 *status = 0;
893 if (priv->state != STATE_ACTIVE_S) {
894 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
895 __func__, priv->state);
896 return -EINVAL;
897 }
898 /* Set SLV-T Bank : 0xA0 */
899 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
900 /*
901 * slave Bank Addr Bit Signal name
902 * <SLV-T> A0h 11h [2] ITSLOCK
903 */
904 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
905 if (reg & 0x04) {
906 *status = FE_HAS_SIGNAL
907 | FE_HAS_CARRIER
908 | FE_HAS_VITERBI
909 | FE_HAS_SYNC
910 | FE_HAS_LOCK;
911 }
912 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
913 return 0;
914}
915
916static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
917 u8 *sync, u8 *tslock, u8 *unlock)
918{
919 u8 data = 0;
920
921 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
922 if (priv->state != STATE_ACTIVE_TC)
923 return -EINVAL;
924 if (priv->system == SYS_DVBT) {
925 /* Set SLV-T Bank : 0x10 */
926 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
927 } else {
928 /* Set SLV-T Bank : 0x20 */
929 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
930 }
931 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
932 if ((data & 0x07) == 0x07) {
933 dev_dbg(&priv->i2c->dev,
934 "%s(): invalid hardware state detected\n", __func__);
935 *sync = 0;
936 *tslock = 0;
937 *unlock = 0;
938 } else {
939 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
940 *tslock = ((data & 0x20) ? 1 : 0);
941 *unlock = ((data & 0x10) ? 1 : 0);
942 }
943 return 0;
944}
945
946static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
947{
948 u8 data;
949
950 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
951 if (priv->state != STATE_ACTIVE_TC)
952 return -EINVAL;
953 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
954 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
955 if ((data & 0x01) == 0) {
956 *tslock = 0;
957 } else {
958 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
959 *tslock = ((data & 0x20) ? 1 : 0);
960 }
961 return 0;
962}
963
83808c23
AO		 964static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
965 u8 *sync, u8 *tslock, u8 *unlock)
966{
967 u8 data = 0;
968
969 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
970 if (priv->state != STATE_ACTIVE_TC)
971 return -EINVAL;
972 /* Set SLV-T Bank : 0x60 */
973 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
974 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
975 dev_dbg(&priv->i2c->dev,
976 "%s(): lock=0x%x\n", __func__, data);
977 *sync = ((data & 0x02) ? 1 : 0);
978 *tslock = ((data & 0x01) ? 1 : 0);
979 *unlock = ((data & 0x10) ? 1 : 0);
980 return 0;
981}
982
a6dc60ff
KS		 983static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
984 enum fe_status *status)
985{
986 int ret = 0;
987 u8 sync = 0;
988 u8 tslock = 0;
989 u8 unlock = 0;
990 struct cxd2841er_priv *priv = fe->demodulator_priv;
991
992 *status = 0;
993 if (priv->state == STATE_ACTIVE_TC) {
994 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
995 ret = cxd2841er_read_status_t_t2(
996 priv, &sync, &tslock, &unlock);
997 if (ret)
998 goto done;
999 if (unlock)
1000 goto done;
1001 if (sync)
1002 *status = FE_HAS_SIGNAL |
1003 FE_HAS_CARRIER |
1004 FE_HAS_VITERBI |
1005 FE_HAS_SYNC;
1006 if (tslock)
1007 *status |= FE_HAS_LOCK;
83808c23
AO		 1008 } else if (priv->system == SYS_ISDBT) {
1009 ret = cxd2841er_read_status_i(
1010 priv, &sync, &tslock, &unlock);
1011 if (ret)
1012 goto done;
1013 if (unlock)
1014 goto done;
1015 if (sync)
1016 *status = FE_HAS_SIGNAL |
1017 FE_HAS_CARRIER |
1018 FE_HAS_VITERBI |
1019 FE_HAS_SYNC;
1020 if (tslock)
1021 *status |= FE_HAS_LOCK;
a6dc60ff
KS		 1022 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1023 ret = cxd2841er_read_status_c(priv, &tslock);
1024 if (ret)
1025 goto done;
1026 if (tslock)
1027 *status = FE_HAS_SIGNAL |
1028 FE_HAS_CARRIER |
1029 FE_HAS_VITERBI |
1030 FE_HAS_SYNC |
1031 FE_HAS_LOCK;
1032 }
1033 }
1034done:
1035 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1036 return ret;
1037}
1038
1039static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1040 int *offset)
1041{
1042 u8 data[3];
1043 u8 is_hs_mode;
1044 s32 cfrl_ctrlval;
1045 s32 temp_div, temp_q, temp_r;
1046
1047 if (priv->state != STATE_ACTIVE_S) {
1048 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1049 __func__, priv->state);
1050 return -EINVAL;
1051 }
1052 /*
1053 * Get High Sampling Rate mode
1054 * slave Bank Addr Bit Signal name
1055 * <SLV-T> A0h 10h [0] ITRL_LOCK
1056 */
1057 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1058 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1059 if (data[0] & 0x01) {
1060 /*
1061 * slave Bank Addr Bit Signal name
1062 * <SLV-T> A0h 50h [4] IHSMODE
1063 */
1064 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1065 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1066 } else {
1067 dev_dbg(&priv->i2c->dev,
1068 "%s(): unable to detect sampling rate mode\n",
1069 __func__);
1070 return -EINVAL;
1071 }
1072 /*
1073 * slave Bank Addr Bit Signal name
1074 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1075 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1076 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1077 */
1078 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1079 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1080 (((u32)data[1] & 0xFF) << 8) |
1081 ((u32)data[2] & 0xFF), 20);
1082 temp_div = (is_hs_mode ? 1048576 : 1572864);
1083 if (cfrl_ctrlval > 0) {
1084 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1085 temp_div, &temp_r);
1086 } else {
1087 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1088 temp_div, &temp_r);
1089 }
1090 if (temp_r >= temp_div / 2)
1091 temp_q++;
1092 if (cfrl_ctrlval > 0)
1093 temp_q *= -1;
1094 *offset = temp_q;
1095 return 0;
1096}
1097
c5ea46da
AO		 1098static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1099 u32 bandwidth, int *offset)
1100{
1101 u8 data[4];
1102
1103 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1104 if (priv->state != STATE_ACTIVE_TC) {
1105 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1106 __func__, priv->state);
1107 return -EINVAL;
1108 }
1109 if (priv->system != SYS_DVBT) {
1110 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1111 __func__, priv->system);
1112 return -EINVAL;
1113 }
1114 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1115 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1116 *offset = -1 * sign_extend32(
1117 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1118 ((u32)data[2] << 8) | (u32)data[3], 29);
4da093ce
AO		 1119 *offset *= (bandwidth / 1000000);
1120 *offset /= 235;
c5ea46da
AO		 1121 return 0;
1122}
1123
c8946c8d
MCC		 1124static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1125 u32 bandwidth, int *offset)
a6dc60ff
KS		 1126{
1127 u8 data[4];
1128
1129 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1130 if (priv->state != STATE_ACTIVE_TC) {
1131 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1132 __func__, priv->state);
1133 return -EINVAL;
1134 }
1135 if (priv->system != SYS_DVBT2) {
1136 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1137 __func__, priv->system);
1138 return -EINVAL;
1139 }
1140 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1141 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1142 *offset = -1 * sign_extend32(
1143 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1144 ((u32)data[2] << 8) | (u32)data[3], 27);
1145 switch (bandwidth) {
1146 case 1712000:
1147 *offset /= 582;
1148 break;
1149 case 5000000:
1150 case 6000000:
1151 case 7000000:
1152 case 8000000:
1153 *offset *= (bandwidth / 1000000);
1154 *offset /= 940;
1155 break;
1156 default:
1157 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1158 __func__, bandwidth);
1159 return -EINVAL;
1160 }
1161 return 0;
1162}
1163
c8946c8d
MCC		 1164static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1165 int *offset)
a6dc60ff
KS		 1166{
1167 u8 data[2];
1168
1169 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1170 if (priv->state != STATE_ACTIVE_TC) {
1171 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1172 __func__, priv->state);
1173 return -EINVAL;
1174 }
1175 if (priv->system != SYS_DVBC_ANNEX_A) {
1176 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1177 __func__, priv->system);
1178 return -EINVAL;
1179 }
1180 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1181 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1182 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1183 | (u32)data[1], 13), 16384);
1184 return 0;
1185}
1186
1187static int cxd2841er_read_packet_errors_t(
1188 struct cxd2841er_priv *priv, u32 *penum)
1189{
1190 u8 data[3];
1191
1192 *penum = 0;
1193 if (priv->state != STATE_ACTIVE_TC) {
1194 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1195 __func__, priv->state);
1196 return -EINVAL;
1197 }
1198 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1199 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1200 if (data[2] & 0x01)
1201 *penum = ((u32)data[0] << 8) | (u32)data[1];
1202 return 0;
1203}
1204
1205static int cxd2841er_read_packet_errors_t2(
1206 struct cxd2841er_priv *priv, u32 *penum)
1207{
1208 u8 data[3];
1209
1210 *penum = 0;
1211 if (priv->state != STATE_ACTIVE_TC) {
1212 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1213 __func__, priv->state);
1214 return -EINVAL;
1215 }
1216 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1217 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1218 if (data[0] & 0x01)
1219 *penum = ((u32)data[1] << 8) | (u32)data[2];
1220 return 0;
1221}
1222
83808c23
AO		 1223static int cxd2841er_read_packet_errors_i(
1224 struct cxd2841er_priv *priv, u32 *penum)
1225{
1226 u8 data[2];
1227
1228 *penum = 0;
1229 if (priv->state != STATE_ACTIVE_TC) {
1230 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1231 __func__, priv->state);
1232 return -EINVAL;
1233 }
1234 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1235 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1236
1237 if (!(data[0] & 0x01))
1238 return 0;
1239
1240 /* Layer A */
1241 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1242 *penum = ((u32)data[0] << 8) | (u32)data[1];
1243
1244 /* Layer B */
1245 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1246 *penum += ((u32)data[0] << 8) | (u32)data[1];
1247
1248 /* Layer C */
1249 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1250 *penum += ((u32)data[0] << 8) | (u32)data[1];
1251
1252 return 0;
1253}
1254
a6dc60ff
KS		 1255static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1256{
1257 u8 data[11];
1258 u32 bit_error, bit_count;
1259 u32 temp_q, temp_r;
1260
1261 /* Set SLV-T Bank : 0xA0 */
1262 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1263 /*
1264 * slave Bank Addr Bit Signal name
1265 * <SLV-T> A0h 35h [0] IFVBER_VALID
1266 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1267 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1268 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1269 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1270 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1271 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1272 */
1273 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1274 if (data[0] & 0x01) {
1275 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1276 ((u32)(data[2] & 0xFF) << 8) |
1277 (u32)(data[3] & 0xFF);
1278 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1279 ((u32)(data[9] & 0xFF) << 8) |
1280 (u32)(data[10] & 0xFF);
1281 /*
1282 * BER = bitError / bitCount
1283 * = (bitError * 10^7) / bitCount
1284 * = ((bitError * 625 * 125 * 128) / bitCount
1285 */
1286 if ((bit_count == 0) || (bit_error > bit_count)) {
1287 dev_dbg(&priv->i2c->dev,
1288 "%s(): invalid bit_error %d, bit_count %d\n",
1289 __func__, bit_error, bit_count);
1290 return 0;
1291 }
1292 temp_q = div_u64_rem(10000000ULL * bit_error,
1293 bit_count, &temp_r);
1294 if (bit_count != 1 && temp_r >= bit_count / 2)
1295 temp_q++;
1296 return temp_q;
1297 }
1298 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1299 return 0;
1300}
1301
1302
1303static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1304{
1305 u8 data[5];
1306 u32 bit_error, period;
1307 u32 temp_q, temp_r;
1308 u32 result = 0;
1309
1310 /* Set SLV-T Bank : 0xB2 */
1311 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1312 /*
1313 * slave Bank Addr Bit Signal name
1314 * <SLV-T> B2h 30h [0] IFLBER_VALID
1315 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1316 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1317 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1318 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1319 */
1320 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1321 if (data[0] & 0x01) {
1322 /* Bit error count */
1323 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1324 ((u32)(data[2] & 0xFF) << 16) |
1325 ((u32)(data[3] & 0xFF) << 8) |
1326 (u32)(data[4] & 0xFF);
1327
1328 /* Set SLV-T Bank : 0xA0 */
1329 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1330 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1331 /* Measurement period */
1332 period = (u32)(1 << (data[0] & 0x0F));
1333 if (period == 0) {
1334 dev_dbg(&priv->i2c->dev,
1335 "%s(): period is 0\n", __func__);
1336 return 0;
1337 }
1338 if (bit_error > (period * 64800)) {
1339 dev_dbg(&priv->i2c->dev,
1340 "%s(): invalid bit_err 0x%x period 0x%x\n",
1341 __func__, bit_error, period);
1342 return 0;
1343 }
1344 /*
1345 * BER = bitError / (period * 64800)
1346 * = (bitError * 10^7) / (period * 64800)
1347 * = (bitError * 10^5) / (period * 648)
1348 * = (bitError * 12500) / (period * 81)
1349 * = (bitError * 10) * 1250 / (period * 81)
1350 */
1351 temp_q = div_u64_rem(12500ULL * bit_error,
1352 period * 81, &temp_r);
1353 if (temp_r >= period * 40)
1354 temp_q++;
1355 result = temp_q;
1356 } else {
1357 dev_dbg(&priv->i2c->dev,
1358 "%s(): no data available\n", __func__);
1359 }
1360 return result;
1361}
1362
1363static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1364{
1365 u8 data[4];
1366 u32 div, q, r;
1367 u32 bit_err, period_exp, n_ldpc;
1368
1369 *ber = 0;
1370 if (priv->state != STATE_ACTIVE_TC) {
1371 dev_dbg(&priv->i2c->dev,
1372 "%s(): invalid state %d\n", __func__, priv->state);
1373 return -EINVAL;
1374 }
1375 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1376 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1377 if (!(data[0] & 0x10)) {
1378 dev_dbg(&priv->i2c->dev,
1379 "%s(): no valid BER data\n", __func__);
1380 return 0;
1381 }
1382 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1383 ((u32)data[1] << 16) |
1384 ((u32)data[2] << 8) |
1385 (u32)data[3];
1386 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1387 period_exp = data[0] & 0x0f;
1388 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1389 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1390 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1391 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1392 dev_dbg(&priv->i2c->dev,
1393 "%s(): invalid BER value\n", __func__);
1394 return -EINVAL;
1395 }
1396 if (period_exp >= 4) {
1397 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1398 q = div_u64_rem(3125ULL * bit_err, div, &r);
1399 } else {
1400 div = (1U << period_exp) * (n_ldpc / 200);
1401 q = div_u64_rem(50000ULL * bit_err, div, &r);
1402 }
1403 *ber = (r >= div / 2) ? q + 1 : q;
1404 return 0;
1405}
1406
1407static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1408{
1409 u8 data[2];
1410 u32 div, q, r;
1411 u32 bit_err, period;
1412
1413 *ber = 0;
1414 if (priv->state != STATE_ACTIVE_TC) {
1415 dev_dbg(&priv->i2c->dev,
1416 "%s(): invalid state %d\n", __func__, priv->state);
1417 return -EINVAL;
1418 }
1419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1420 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1421 if (!(data[0] & 0x01)) {
1422 dev_dbg(&priv->i2c->dev,
1423 "%s(): no valid BER data\n", __func__);
1424 return 0;
1425 }
1426 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1427 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1428 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1429 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1430 div = period / 128;
1431 q = div_u64_rem(78125ULL * bit_err, div, &r);
1432 *ber = (r >= div / 2) ? q + 1 : q;
1433 return 0;
1434}
1435
1436static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1437{
1438 u8 data[3];
1439 u32 res = 0, value;
1440 int min_index, max_index, index;
1441 static const struct cxd2841er_cnr_data *cn_data;
1442
1443 /* Set SLV-T Bank : 0xA1 */
1444 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1445 /*
1446 * slave Bank Addr Bit Signal name
1447 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1448 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1449 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1450 */
1451 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1452 if (data[0] & 0x01) {
1453 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1454 min_index = 0;
1455 if (delsys == SYS_DVBS) {
1456 cn_data = s_cn_data;
1457 max_index = sizeof(s_cn_data) /
1458 sizeof(s_cn_data[0]) - 1;
1459 } else {
1460 cn_data = s2_cn_data;
1461 max_index = sizeof(s2_cn_data) /
1462 sizeof(s2_cn_data[0]) - 1;
1463 }
1464 if (value >= cn_data[min_index].value) {
1465 res = cn_data[min_index].cnr_x1000;
1466 goto done;
1467 }
1468 if (value <= cn_data[max_index].value) {
1469 res = cn_data[max_index].cnr_x1000;
1470 goto done;
1471 }
1472 while ((max_index - min_index) > 1) {
1473 index = (max_index + min_index) / 2;
1474 if (value == cn_data[index].value) {
1475 res = cn_data[index].cnr_x1000;
1476 goto done;
1477 } else if (value > cn_data[index].value)
1478 max_index = index;
1479 else
1480 min_index = index;
1481 if ((max_index - min_index) <= 1) {
1482 if (value == cn_data[max_index].value) {
1483 res = cn_data[max_index].cnr_x1000;
1484 goto done;
1485 } else {
1486 res = cn_data[min_index].cnr_x1000;
1487 goto done;
1488 }
1489 }
1490 }
1491 } else {
1492 dev_dbg(&priv->i2c->dev,
1493 "%s(): no data available\n", __func__);
1494 }
1495done:
1496 return res;
1497}
1498
1499static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1500{
1501 u32 reg;
1502 u8 data[2];
1503
1504 *snr = 0;
1505 if (priv->state != STATE_ACTIVE_TC) {
1506 dev_dbg(&priv->i2c->dev,
1507 "%s(): invalid state %d\n", __func__, priv->state);
1508 return -EINVAL;
1509 }
1510 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1511 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1512 reg = ((u32)data[0] << 8) | (u32)data[1];
1513 if (reg == 0) {
1514 dev_dbg(&priv->i2c->dev,
1515 "%s(): reg value out of range\n", __func__);
1516 return 0;
1517 }
1518 if (reg > 4996)
1519 reg = 4996;
1520 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1521 return 0;
1522}
1523
c8946c8d 1524static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
a6dc60ff
KS		 1525{
1526 u32 reg;
1527 u8 data[2];
1528
1529 *snr = 0;
1530 if (priv->state != STATE_ACTIVE_TC) {
1531 dev_dbg(&priv->i2c->dev,
1532 "%s(): invalid state %d\n", __func__, priv->state);
1533 return -EINVAL;
1534 }
1535 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1536 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1537 reg = ((u32)data[0] << 8) | (u32)data[1];
1538 if (reg == 0) {
1539 dev_dbg(&priv->i2c->dev,
1540 "%s(): reg value out of range\n", __func__);
1541 return 0;
1542 }
1543 if (reg > 10876)
1544 reg = 10876;
1545 *snr = 10000 * ((intlog10(reg) -
1546 intlog10(12600 - reg)) >> 24) + 32000;
1547 return 0;
1548}
1549
83808c23
AO		 1550static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1551{
1552 u32 reg;
1553 u8 data[2];
1554
1555 *snr = 0;
1556 if (priv->state != STATE_ACTIVE_TC) {
1557 dev_dbg(&priv->i2c->dev,
1558 "%s(): invalid state %d\n", __func__,
1559 priv->state);
1560 return -EINVAL;
1561 }
1562
1563 /* Freeze all registers */
1564 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1565
1566
1567 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1568 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1569 reg = ((u32)data[0] << 8) | (u32)data[1];
1570 if (reg == 0) {
1571 dev_dbg(&priv->i2c->dev,
1572 "%s(): reg value out of range\n", __func__);
1573 return 0;
1574 }
1575 if (reg > 4996)
1576 reg = 4996;
1577 *snr = 100 * intlog10(reg) - 9031;
1578 return 0;
1579}
1580
a6dc60ff
KS		 1581static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1582 u8 delsys)
1583{
1584 u8 data[2];
1585
1586 cxd2841er_write_reg(
1587 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1588 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
c5ea46da
AO		 1589 dev_dbg(&priv->i2c->dev,
1590 "%s(): AGC value=%u\n",
1591 __func__, (((u16)data[0] & 0x0F) << 8) |
1592 (u16)(data[1] & 0xFF));
a6dc60ff
KS		 1593 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1594}
1595
83808c23
AO		 1596static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1597 u8 delsys)
1598{
1599 u8 data[2];
1600
1601 cxd2841er_write_reg(
1602 priv, I2C_SLVT, 0x00, 0x60);
1603 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1604
1605 dev_dbg(&priv->i2c->dev,
1606 "%s(): AGC value=%u\n",
1607 __func__, (((u16)data[0] & 0x0F) << 8) |
1608 (u16)(data[1] & 0xFF));
1609 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1610}
1611
a6dc60ff
KS		 1612static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1613{
1614 u8 data[2];
1615
1616 /* Set SLV-T Bank : 0xA0 */
1617 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1618 /*
1619 * slave Bank Addr Bit Signal name
1620 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1621 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1622 */
1623 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1624 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1625}
1626
1627static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1628{
1629 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1630 struct cxd2841er_priv *priv = fe->demodulator_priv;
1631
1632 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1633 *ber = 0;
1634 switch (p->delivery_system) {
1635 case SYS_DVBS:
1636 *ber = cxd2841er_mon_read_ber_s(priv);
1637 break;
1638 case SYS_DVBS2:
1639 *ber = cxd2841er_mon_read_ber_s2(priv);
1640 break;
1641 case SYS_DVBT:
1642 return cxd2841er_read_ber_t(priv, ber);
1643 case SYS_DVBT2:
1644 return cxd2841er_read_ber_t2(priv, ber);
1645 default:
1646 *ber = 0;
1647 break;
1648 }
1649 return 0;
1650}
1651
1652static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1653 u16 *strength)
1654{
1655 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1656 struct cxd2841er_priv *priv = fe->demodulator_priv;
1657
1658 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1659 switch (p->delivery_system) {
1660 case SYS_DVBT:
1661 case SYS_DVBT2:
1662 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1663 priv, p->delivery_system);
1664 break;
83808c23
AO		 1665 case SYS_ISDBT:
1666 *strength = 65535 - cxd2841er_read_agc_gain_i(
1667 priv, p->delivery_system);
1668 break;
a6dc60ff
KS		 1669 case SYS_DVBS:
1670 case SYS_DVBS2:
1671 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1672 break;
1673 default:
1674 *strength = 0;
1675 break;
1676 }
1677 return 0;
1678}
1679
1680static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1681{
1682 u32 tmp = 0;
1683 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1684 struct cxd2841er_priv *priv = fe->demodulator_priv;
1685
1686 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1687 switch (p->delivery_system) {
1688 case SYS_DVBT:
1689 cxd2841er_read_snr_t(priv, &tmp);
1690 break;
1691 case SYS_DVBT2:
1692 cxd2841er_read_snr_t2(priv, &tmp);
1693 break;
83808c23
AO		 1694 case SYS_ISDBT:
1695 cxd2841er_read_snr_i(priv, &tmp);
1696 break;
a6dc60ff
KS		 1697 case SYS_DVBS:
1698 case SYS_DVBS2:
1699 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1700 break;
1701 default:
1702 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1703 __func__, p->delivery_system);
1704 break;
1705 }
1706 *snr = tmp & 0xffff;
1707 return 0;
1708}
1709
1710static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1711{
1712 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1713 struct cxd2841er_priv *priv = fe->demodulator_priv;
1714
1715 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1716 switch (p->delivery_system) {
1717 case SYS_DVBT:
1718 cxd2841er_read_packet_errors_t(priv, ucblocks);
1719 break;
1720 case SYS_DVBT2:
1721 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1722 break;
83808c23
AO		 1723 case SYS_ISDBT:
1724 cxd2841er_read_packet_errors_i(priv, ucblocks);
1725 break;
a6dc60ff
KS		 1726 default:
1727 *ucblocks = 0;
1728 break;
1729 }
1730 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1731 return 0;
1732}
1733
1734static int cxd2841er_dvbt2_set_profile(
1735 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1736{
1737 u8 tune_mode;
1738 u8 seq_not2d_time;
1739
1740 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1741 switch (profile) {
1742 case DVBT2_PROFILE_BASE:
1743 tune_mode = 0x01;
1744 seq_not2d_time = 12;
1745 break;
1746 case DVBT2_PROFILE_LITE:
1747 tune_mode = 0x05;
1748 seq_not2d_time = 40;
1749 break;
1750 case DVBT2_PROFILE_ANY:
1751 tune_mode = 0x00;
1752 seq_not2d_time = 40;
1753 break;
1754 default:
1755 return -EINVAL;
1756 }
1757 /* Set SLV-T Bank : 0x2E */
1758 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1759 /* Set profile and tune mode */
1760 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1761 /* Set SLV-T Bank : 0x2B */
1762 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1763 /* Set early unlock detection time */
1764 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1765 return 0;
1766}
1767
1768static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1769 u8 is_auto, u8 plp_id)
1770{
1771 if (is_auto) {
1772 dev_dbg(&priv->i2c->dev,
1773 "%s() using auto PLP selection\n", __func__);
1774 } else {
1775 dev_dbg(&priv->i2c->dev,
1776 "%s() using manual PLP selection, ID %d\n",
1777 __func__, plp_id);
1778 }
1779 /* Set SLV-T Bank : 0x23 */
1780 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1781 if (!is_auto) {
1782 /* Manual PLP selection mode. Set the data PLP Id. */
1783 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1784 }
1785 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1786 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1787 return 0;
1788}
1789
1790static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1791 u32 bandwidth)
1792{
1793 u32 iffreq;
1794 u8 b20_9f[5];
1795 u8 b10_a6[14];
1796 u8 b10_b6[3];
1797 u8 b10_d7;
1798
1799 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1800 switch (bandwidth) {
1801 case 8000000:
1802 /* bank 0x20, reg 0x9f */
1803 b20_9f[0] = 0x11;
1804 b20_9f[1] = 0xf0;
1805 b20_9f[2] = 0x00;
1806 b20_9f[3] = 0x00;
1807 b20_9f[4] = 0x00;
1808 /* bank 0x10, reg 0xa6 */
1809 b10_a6[0] = 0x26;
1810 b10_a6[1] = 0xaf;
1811 b10_a6[2] = 0x06;
1812 b10_a6[3] = 0xcd;
1813 b10_a6[4] = 0x13;
1814 b10_a6[5] = 0xbb;
1815 b10_a6[6] = 0x28;
1816 b10_a6[7] = 0xba;
1817 b10_a6[8] = 0x23;
1818 b10_a6[9] = 0xa9;
1819 b10_a6[10] = 0x1f;
1820 b10_a6[11] = 0xa8;
1821 b10_a6[12] = 0x2c;
1822 b10_a6[13] = 0xc8;
1823 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1824 b10_d7 = 0x00;
1825 break;
1826 case 7000000:
1827 /* bank 0x20, reg 0x9f */
1828 b20_9f[0] = 0x14;
1829 b20_9f[1] = 0x80;
1830 b20_9f[2] = 0x00;
1831 b20_9f[3] = 0x00;
1832 b20_9f[4] = 0x00;
1833 /* bank 0x10, reg 0xa6 */
1834 b10_a6[0] = 0x2C;
1835 b10_a6[1] = 0xBD;
1836 b10_a6[2] = 0x02;
1837 b10_a6[3] = 0xCF;
1838 b10_a6[4] = 0x04;
1839 b10_a6[5] = 0xF8;
1840 b10_a6[6] = 0x23;
1841 b10_a6[7] = 0xA6;
1842 b10_a6[8] = 0x29;
1843 b10_a6[9] = 0xB0;
1844 b10_a6[10] = 0x26;
1845 b10_a6[11] = 0xA9;
1846 b10_a6[12] = 0x21;
1847 b10_a6[13] = 0xA5;
1848 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1849 b10_d7 = 0x02;
1850 break;
1851 case 6000000:
1852 /* bank 0x20, reg 0x9f */
1853 b20_9f[0] = 0x17;
1854 b20_9f[1] = 0xEA;
1855 b20_9f[2] = 0xAA;
1856 b20_9f[3] = 0xAA;
1857 b20_9f[4] = 0xAA;
1858 /* bank 0x10, reg 0xa6 */
1859 b10_a6[0] = 0x27;
1860 b10_a6[1] = 0xA7;
1861 b10_a6[2] = 0x28;
1862 b10_a6[3] = 0xB3;
1863 b10_a6[4] = 0x02;
1864 b10_a6[5] = 0xF0;
1865 b10_a6[6] = 0x01;
1866 b10_a6[7] = 0xE8;
1867 b10_a6[8] = 0x00;
1868 b10_a6[9] = 0xCF;
1869 b10_a6[10] = 0x00;
1870 b10_a6[11] = 0xE6;
1871 b10_a6[12] = 0x23;
1872 b10_a6[13] = 0xA4;
1873 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1874 b10_d7 = 0x04;
1875 break;
1876 case 5000000:
1877 /* bank 0x20, reg 0x9f */
1878 b20_9f[0] = 0x1C;
1879 b20_9f[1] = 0xB3;
1880 b20_9f[2] = 0x33;
1881 b20_9f[3] = 0x33;
1882 b20_9f[4] = 0x33;
1883 /* bank 0x10, reg 0xa6 */
1884 b10_a6[0] = 0x27;
1885 b10_a6[1] = 0xA7;
1886 b10_a6[2] = 0x28;
1887 b10_a6[3] = 0xB3;
1888 b10_a6[4] = 0x02;
1889 b10_a6[5] = 0xF0;
1890 b10_a6[6] = 0x01;
1891 b10_a6[7] = 0xE8;
1892 b10_a6[8] = 0x00;
1893 b10_a6[9] = 0xCF;
1894 b10_a6[10] = 0x00;
1895 b10_a6[11] = 0xE6;
1896 b10_a6[12] = 0x23;
1897 b10_a6[13] = 0xA4;
1898 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1899 b10_d7 = 0x06;
1900 break;
1901 case 1712000:
1902 /* bank 0x20, reg 0x9f */
1903 b20_9f[0] = 0x58;
1904 b20_9f[1] = 0xE2;
1905 b20_9f[2] = 0xAF;
1906 b20_9f[3] = 0xE0;
1907 b20_9f[4] = 0xBC;
1908 /* bank 0x10, reg 0xa6 */
1909 b10_a6[0] = 0x25;
1910 b10_a6[1] = 0xA0;
1911 b10_a6[2] = 0x36;
1912 b10_a6[3] = 0x8D;
1913 b10_a6[4] = 0x2E;
1914 b10_a6[5] = 0x94;
1915 b10_a6[6] = 0x28;
1916 b10_a6[7] = 0x9B;
1917 b10_a6[8] = 0x32;
1918 b10_a6[9] = 0x90;
1919 b10_a6[10] = 0x2C;
1920 b10_a6[11] = 0x9D;
1921 b10_a6[12] = 0x29;
1922 b10_a6[13] = 0x99;
1923 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1924 b10_d7 = 0x03;
1925 break;
1926 default:
1927 return -EINVAL;
1928 }
1929 /* Set SLV-T Bank : 0x20 */
1930 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1931 cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1932 /* Set SLV-T Bank : 0x27 */
1933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1934 cxd2841er_set_reg_bits(
1935 priv, I2C_SLVT, 0x7a,
1936 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1937 /* Set SLV-T Bank : 0x10 */
1938 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1939 /* Group delay equaliser sett. for ASCOT2E */
1940 cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
1941 /* <IF freq setting> */
1942 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1943 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1944 b10_b6[2] = (u8)(iffreq & 0xff);
1945 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1946 /* System bandwidth setting */
1947 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
1948 return 0;
1949}
1950
1951static int cxd2841er_sleep_tc_to_active_t_band(
1952 struct cxd2841er_priv *priv, u32 bandwidth)
1953{
83808c23 1954 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff 1955 u32 iffreq;
83808c23
AO		 1956 u8 nominalRate8bw[3][5] = {
1957 /* TRCG Nominal Rate [37:0] */
1958 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1959 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1960 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1961 };
1962 u8 nominalRate7bw[3][5] = {
1963 /* TRCG Nominal Rate [37:0] */
1964 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1965 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1966 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1967 };
1968 u8 nominalRate6bw[3][5] = {
1969 /* TRCG Nominal Rate [37:0] */
1970 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1971 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1972 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1973 };
1974 u8 nominalRate5bw[3][5] = {
1975 /* TRCG Nominal Rate [37:0] */
1976 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1977 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1978 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1979 };
a6dc60ff 1980
83808c23
AO		 1981 u8 itbCoef8bw[3][14] = {
1982 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1983 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1984 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
1985 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1986 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1987 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1988 };
1989 u8 itbCoef7bw[3][14] = {
1990 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1991 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1992 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
1993 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1994 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1995 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1996 };
1997 u8 itbCoef6bw[3][14] = {
1998 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1999 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2000 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2001 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2002 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2003 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2004 };
2005 u8 itbCoef5bw[3][14] = {
2006 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2007 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2008 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2009 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2010 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2011 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2012 };
2013
2014 /* Set SLV-T Bank : 0x13 */
a6dc60ff
KS		 2015 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2016 /* Echo performance optimization setting */
83808c23
AO		 2017 data[0] = 0x01;
2018 data[1] = 0x14;
2019 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2020
2021 /* Set SLV-T Bank : 0x10 */
a6dc60ff
KS		 2022 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2023
2024 switch (bandwidth) {
2025 case 8000000:
83808c23
AO		 2026 /* <Timing Recovery setting> */
2027 cxd2841er_write_regs(priv, I2C_SLVT,
2028 0x9F, nominalRate8bw[priv->xtal], 5);
2029 /* Group delay equaliser settings for
2030 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2031 */
2032 cxd2841er_write_regs(priv, I2C_SLVT,
2033 0xA6, itbCoef8bw[priv->xtal], 14);
2034 /* <IF freq setting> */
2035 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2036 data[0] = (u8) ((iffreq >> 16) & 0xff);
2037 data[1] = (u8)((iffreq >> 8) & 0xff);
2038 data[2] = (u8)(iffreq & 0xff);
2039 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2040 /* System bandwidth setting */
2041 cxd2841er_set_reg_bits(
2042 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2043
2044 /* Demod core latency setting */
2045 if (priv->xtal == SONY_XTAL_24000) {
2046 data[0] = 0x15;
2047 data[1] = 0x28;
2048 } else {
2049 data[0] = 0x01;
2050 data[1] = 0xE0;
2051 }
2052 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2053
2054 /* Notch filter setting */
2055 data[0] = 0x01;
2056 data[1] = 0x02;
2057 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2058 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2059 break;
2060 case 7000000:
83808c23
AO		 2061 /* <Timing Recovery setting> */
2062 cxd2841er_write_regs(priv, I2C_SLVT,
2063 0x9F, nominalRate7bw[priv->xtal], 5);
2064 /* Group delay equaliser settings for
2065 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2066 */
2067 cxd2841er_write_regs(priv, I2C_SLVT,
2068 0xA6, itbCoef7bw[priv->xtal], 14);
2069 /* <IF freq setting> */
2070 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2071 data[0] = (u8) ((iffreq >> 16) & 0xff);
2072 data[1] = (u8)((iffreq >> 8) & 0xff);
2073 data[2] = (u8)(iffreq & 0xff);
2074 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2075 /* System bandwidth setting */
2076 cxd2841er_set_reg_bits(
2077 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2078
2079 /* Demod core latency setting */
2080 if (priv->xtal == SONY_XTAL_24000) {
2081 data[0] = 0x1F;
2082 data[1] = 0xF8;
2083 } else {
2084 data[0] = 0x12;
2085 data[1] = 0xF8;
2086 }
2087 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2088
2089 /* Notch filter setting */
2090 data[0] = 0x00;
2091 data[1] = 0x03;
2092 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2093 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2094 break;
2095 case 6000000:
83808c23
AO		 2096 /* <Timing Recovery setting> */
2097 cxd2841er_write_regs(priv, I2C_SLVT,
2098 0x9F, nominalRate6bw[priv->xtal], 5);
2099 /* Group delay equaliser settings for
2100 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2101 */
2102 cxd2841er_write_regs(priv, I2C_SLVT,
2103 0xA6, itbCoef6bw[priv->xtal], 14);
2104 /* <IF freq setting> */
2105 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2106 data[0] = (u8) ((iffreq >> 16) & 0xff);
2107 data[1] = (u8)((iffreq >> 8) & 0xff);
2108 data[2] = (u8)(iffreq & 0xff);
2109 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2110 /* System bandwidth setting */
2111 cxd2841er_set_reg_bits(
2112 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2113
2114 /* Demod core latency setting */
2115 if (priv->xtal == SONY_XTAL_24000) {
2116 data[0] = 0x25;
2117 data[1] = 0x4C;
2118 } else {
2119 data[0] = 0x1F;
2120 data[1] = 0xDC;
2121 }
2122 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2123
2124 /* Notch filter setting */
2125 data[0] = 0x00;
2126 data[1] = 0x03;
2127 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2128 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2129 break;
2130 case 5000000:
83808c23
AO		 2131 /* <Timing Recovery setting> */
2132 cxd2841er_write_regs(priv, I2C_SLVT,
2133 0x9F, nominalRate5bw[priv->xtal], 5);
2134 /* Group delay equaliser settings for
2135 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2136 */
2137 cxd2841er_write_regs(priv, I2C_SLVT,
2138 0xA6, itbCoef5bw[priv->xtal], 14);
2139 /* <IF freq setting> */
2140 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2141 data[0] = (u8) ((iffreq >> 16) & 0xff);
2142 data[1] = (u8)((iffreq >> 8) & 0xff);
2143 data[2] = (u8)(iffreq & 0xff);
2144 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2145 /* System bandwidth setting */
2146 cxd2841er_set_reg_bits(
2147 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2148
2149 /* Demod core latency setting */
2150 if (priv->xtal == SONY_XTAL_24000) {
2151 data[0] = 0x2C;
2152 data[1] = 0xC2;
2153 } else {
2154 data[0] = 0x26;
2155 data[1] = 0x3C;
2156 }
2157 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2158
2159 /* Notch filter setting */
2160 data[0] = 0x00;
2161 data[1] = 0x03;
2162 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2163 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2164 break;
2165 }
2166
2167 return 0;
2168}
2169
2170static int cxd2841er_sleep_tc_to_active_i_band(
2171 struct cxd2841er_priv *priv, u32 bandwidth)
2172{
2173 u32 iffreq;
2174 u8 data[3];
2175
2176 /* TRCG Nominal Rate */
2177 u8 nominalRate8bw[3][5] = {
2178 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2179 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2180 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2181 };
2182
2183 u8 nominalRate7bw[3][5] = {
2184 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2185 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2186 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2187 };
2188
2189 u8 nominalRate6bw[3][5] = {
2190 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2191 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2192 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2193 };
2194
2195 u8 itbCoef8bw[3][14] = {
2196 {0x00}, /* 20.5MHz XTal */
2197 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2198 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2199 {0x0}, /* 41MHz XTal */
2200 };
2201
2202 u8 itbCoef7bw[3][14] = {
2203 {0x00}, /* 20.5MHz XTal */
2204 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2205 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2206 {0x00}, /* 41MHz XTal */
2207 };
2208
2209 u8 itbCoef6bw[3][14] = {
2210 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2211 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2212 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2213 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2214 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2215 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2216 };
2217
2218 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2219 /* Set SLV-T Bank : 0x10 */
2220 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2221
2222 /* 20.5/41MHz Xtal support is not available
2223 * on ISDB-T 7MHzBW and 8MHzBW
2224 */
2225 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2226 dev_err(&priv->i2c->dev,
2227 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2228 __func__, bandwidth);
2229 return -EINVAL;
2230 }
2231
2232 switch (bandwidth) {
2233 case 8000000:
2234 /* TRCG Nominal Rate */
2235 cxd2841er_write_regs(priv, I2C_SLVT,
2236 0x9F, nominalRate8bw[priv->xtal], 5);
2237 /* Group delay equaliser settings for ASCOT tuners optimized */
2238 cxd2841er_write_regs(priv, I2C_SLVT,
2239 0xA6, itbCoef8bw[priv->xtal], 14);
2240
2241 /* IF freq setting */
2242 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2243 data[0] = (u8) ((iffreq >> 16) & 0xff);
2244 data[1] = (u8)((iffreq >> 8) & 0xff);
2245 data[2] = (u8)(iffreq & 0xff);
2246 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2247
2248 /* System bandwidth setting */
2249 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2250
2251 /* Demod core latency setting */
2252 data[0] = 0x13;
2253 data[1] = 0xFC;
2254 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2255
2256 /* Acquisition optimization setting */
2257 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2258 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2259 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2260 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2261 break;
2262 case 7000000:
2263 /* TRCG Nominal Rate */
2264 cxd2841er_write_regs(priv, I2C_SLVT,
2265 0x9F, nominalRate7bw[priv->xtal], 5);
2266 /* Group delay equaliser settings for ASCOT tuners optimized */
2267 cxd2841er_write_regs(priv, I2C_SLVT,
2268 0xA6, itbCoef7bw[priv->xtal], 14);
2269
2270 /* IF freq setting */
2271 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2272 data[0] = (u8) ((iffreq >> 16) & 0xff);
2273 data[1] = (u8)((iffreq >> 8) & 0xff);
2274 data[2] = (u8)(iffreq & 0xff);
2275 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2276
2277 /* System bandwidth setting */
2278 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2279
2280 /* Demod core latency setting */
2281 data[0] = 0x1A;
2282 data[1] = 0xFA;
2283 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2284
2285 /* Acquisition optimization setting */
2286 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2287 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2288 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2289 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2290 break;
2291 case 6000000:
2292 /* TRCG Nominal Rate */
2293 cxd2841er_write_regs(priv, I2C_SLVT,
2294 0x9F, nominalRate6bw[priv->xtal], 5);
2295 /* Group delay equaliser settings for ASCOT tuners optimized */
2296 cxd2841er_write_regs(priv, I2C_SLVT,
2297 0xA6, itbCoef6bw[priv->xtal], 14);
2298
2299 /* IF freq setting */
2300 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2301 data[0] = (u8) ((iffreq >> 16) & 0xff);
2302 data[1] = (u8)((iffreq >> 8) & 0xff);
2303 data[2] = (u8)(iffreq & 0xff);
2304 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2305
2306 /* System bandwidth setting */
2307 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2308
2309 /* Demod core latency setting */
2310 if (priv->xtal == SONY_XTAL_24000) {
2311 data[0] = 0x1F;
2312 data[1] = 0x79;
2313 } else {
2314 data[0] = 0x1A;
2315 data[1] = 0xE2;
2316 }
2317 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2318
2319 /* Acquisition optimization setting */
2320 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2321 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2322 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2323 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
a6dc60ff
KS		 2324 break;
2325 default:
2326 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
83808c23 2327 __func__, bandwidth);
a6dc60ff
KS		 2328 return -EINVAL;
2329 }
a6dc60ff
KS		 2330 return 0;
2331}
2332
2333static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2334 u32 bandwidth)
2335{
2336 u8 bw7_8mhz_b10_a6[] = {
2337 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2338 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2339 u8 bw6mhz_b10_a6[] = {
2340 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2341 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2342 u8 b10_b6[3];
2343 u32 iffreq;
2344
2345 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2346 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2347 switch (bandwidth) {
2348 case 8000000:
2349 case 7000000:
2350 cxd2841er_write_regs(
2351 priv, I2C_SLVT, 0xa6,
2352 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2353 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2354 break;
2355 case 6000000:
2356 cxd2841er_write_regs(
2357 priv, I2C_SLVT, 0xa6,
2358 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2359 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2360 break;
2361 default:
2362 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2363 __func__, bandwidth);
2364 return -EINVAL;
2365 }
2366 /* <IF freq setting> */
2367 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2368 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2369 b10_b6[2] = (u8)(iffreq & 0xff);
2370 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2371 /* Set SLV-T Bank : 0x11 */
2372 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2373 switch (bandwidth) {
2374 case 8000000:
2375 case 7000000:
2376 cxd2841er_set_reg_bits(
2377 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2378 break;
2379 case 6000000:
2380 cxd2841er_set_reg_bits(
2381 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2382 break;
2383 }
2384 /* Set SLV-T Bank : 0x40 */
2385 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2386 switch (bandwidth) {
2387 case 8000000:
2388 cxd2841er_set_reg_bits(
2389 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2390 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2391 break;
2392 case 7000000:
2393 cxd2841er_set_reg_bits(
2394 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2395 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2396 break;
2397 case 6000000:
2398 cxd2841er_set_reg_bits(
2399 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2400 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2401 break;
2402 }
2403 return 0;
2404}
2405
2406static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2407 u32 bandwidth)
2408{
2409 u8 data[2] = { 0x09, 0x54 };
83808c23 2410 u8 data24m[3] = {0xDC, 0x6C, 0x00};
a6dc60ff
KS		 2411
2412 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2413 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2414 /* Set SLV-X Bank : 0x00 */
2415 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2416 /* Set demod mode */
2417 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2418 /* Set SLV-T Bank : 0x00 */
2419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2420 /* Enable demod clock */
2421 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2422 /* Disable RF level monitor */
2423 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2424 /* Enable ADC clock */
2425 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2426 /* Enable ADC 1 */
2427 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
83808c23
AO		 2428 /* Enable ADC 2 & 3 */
2429 if (priv->xtal == SONY_XTAL_41000) {
2430 data[0] = 0x0A;
2431 data[1] = 0xD4;
2432 }
a6dc60ff
KS		 2433 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2434 /* Enable ADC 4 */
2435 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2436 /* Set SLV-T Bank : 0x10 */
2437 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2438 /* IFAGC gain settings */
2439 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2440 /* Set SLV-T Bank : 0x11 */
2441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2442 /* BBAGC TARGET level setting */
2443 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2444 /* Set SLV-T Bank : 0x10 */
2445 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2446 /* ASCOT setting ON */
2447 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2448 /* Set SLV-T Bank : 0x18 */
2449 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2450 /* Pre-RS BER moniter setting */
2451 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2452 /* FEC Auto Recovery setting */
2453 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2454 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2455 /* Set SLV-T Bank : 0x00 */
2456 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2457 /* TSIF setting */
2458 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2459 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
83808c23
AO		 2460
2461 if (priv->xtal == SONY_XTAL_24000) {
2462 /* Set SLV-T Bank : 0x10 */
2463 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2464 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2465 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2466 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2467 }
2468
a6dc60ff
KS		 2469 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2470 /* Set SLV-T Bank : 0x00 */
2471 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2472 /* Disable HiZ Setting 1 */
2473 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2474 /* Disable HiZ Setting 2 */
2475 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2476 priv->state = STATE_ACTIVE_TC;
2477 return 0;
2478}
2479
2480static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2481 u32 bandwidth)
2482{
2483 u8 data[2] = { 0x09, 0x54 };
2484
2485 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2486 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2487 /* Set SLV-X Bank : 0x00 */
2488 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2489 /* Set demod mode */
2490 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2491 /* Set SLV-T Bank : 0x00 */
2492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2493 /* Enable demod clock */
2494 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2495 /* Disable RF level monitor */
2496 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2497 /* Enable ADC clock */
2498 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2499 /* Enable ADC 1 */
2500 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2501 /* xtal freq 20.5MHz */
2502 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2503 /* Enable ADC 4 */
2504 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2505 /* Set SLV-T Bank : 0x10 */
2506 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2507 /* IFAGC gain settings */
2508 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2509 /* Set SLV-T Bank : 0x11 */
2510 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2511 /* BBAGC TARGET level setting */
2512 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2513 /* Set SLV-T Bank : 0x10 */
2514 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2515 /* ASCOT setting ON */
2516 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2517 /* Set SLV-T Bank : 0x20 */
2518 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2519 /* Acquisition optimization setting */
2520 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2521 /* Set SLV-T Bank : 0x2b */
2522 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2523 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2524 /* Set SLV-T Bank : 0x00 */
2525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2526 /* TSIF setting */
2527 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2528 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2529 /* DVB-T2 initial setting */
2530 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2531 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2532 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2533 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2534 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2535 /* Set SLV-T Bank : 0x2a */
2536 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2537 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2538 /* Set SLV-T Bank : 0x2b */
2539 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2540 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2541
2542 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2543
2544 /* Set SLV-T Bank : 0x00 */
2545 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2546 /* Disable HiZ Setting 1 */
2547 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2548 /* Disable HiZ Setting 2 */
2549 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2550 priv->state = STATE_ACTIVE_TC;
2551 return 0;
2552}
2553
83808c23
AO		 2554/* ISDB-Tb part */
2555static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2556 u32 bandwidth)
2557{
2558 u8 data[2] = { 0x09, 0x54 };
2559 u8 data24m[2] = {0x60, 0x00};
2560 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2561
2562 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2563 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2564 /* Set SLV-X Bank : 0x00 */
2565 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2566 /* Set demod mode */
2567 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2568 /* Set SLV-T Bank : 0x00 */
2569 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2570 /* Enable demod clock */
2571 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2572 /* Enable RF level monitor */
2573 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2574 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2575 /* Enable ADC clock */
2576 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2577 /* Enable ADC 1 */
2578 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2579 /* xtal freq 20.5MHz or 24M */
2580 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2581 /* Enable ADC 4 */
2582 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2583 /* ASCOT setting ON */
2584 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2585 /* FEC Auto Recovery setting */
2586 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2587 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2588 /* ISDB-T initial setting */
2589 /* Set SLV-T Bank : 0x00 */
2590 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2591 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2592 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2593 /* Set SLV-T Bank : 0x10 */
2594 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2595 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2596 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2597 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2598 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2599 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2600 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2601 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2602 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2603 /* Set SLV-T Bank : 0x15 */
2604 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2605 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2606 /* Set SLV-T Bank : 0x1E */
2607 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2608 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2609 /* Set SLV-T Bank : 0x63 */
2610 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2611 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2612
2613 /* for xtal 24MHz */
2614 /* Set SLV-T Bank : 0x10 */
2615 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2616 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2617 /* Set SLV-T Bank : 0x60 */
2618 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2619 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2620
2621 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2622 /* Set SLV-T Bank : 0x00 */
2623 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2624 /* Disable HiZ Setting 1 */
2625 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2626 /* Disable HiZ Setting 2 */
2627 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2628 priv->state = STATE_ACTIVE_TC;
2629 return 0;
2630}
2631
a6dc60ff
KS		 2632static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2633 u32 bandwidth)
2634{
2635 u8 data[2] = { 0x09, 0x54 };
2636
2637 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2638 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2639 /* Set SLV-X Bank : 0x00 */
2640 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2641 /* Set demod mode */
2642 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2643 /* Set SLV-T Bank : 0x00 */
2644 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2645 /* Enable demod clock */
2646 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2647 /* Disable RF level monitor */
2648 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2649 /* Enable ADC clock */
2650 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2651 /* Enable ADC 1 */
2652 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2653 /* xtal freq 20.5MHz */
2654 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2655 /* Enable ADC 4 */
2656 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2657 /* Set SLV-T Bank : 0x10 */
2658 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2659 /* IFAGC gain settings */
2660 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2661 /* Set SLV-T Bank : 0x11 */
2662 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2663 /* BBAGC TARGET level setting */
2664 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2665 /* Set SLV-T Bank : 0x10 */
2666 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2667 /* ASCOT setting ON */
2668 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2669 /* Set SLV-T Bank : 0x40 */
2670 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2671 /* Demod setting */
2672 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2673 /* Set SLV-T Bank : 0x00 */
2674 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2675 /* TSIF setting */
2676 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2677 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2678
2679 cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2680 /* Set SLV-T Bank : 0x00 */
2681 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2682 /* Disable HiZ Setting 1 */
2683 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2684 /* Disable HiZ Setting 2 */
2685 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2686 priv->state = STATE_ACTIVE_TC;
2687 return 0;
2688}
2689
7e3e68bc
MCC		 2690static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2691 struct dtv_frontend_properties *p)
a6dc60ff
KS		 2692{
2693 enum fe_status status = 0;
2694 u16 strength = 0, snr = 0;
2695 u32 errors = 0, ber = 0;
2696 struct cxd2841er_priv *priv = fe->demodulator_priv;
a6dc60ff
KS		 2697
2698 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2699 if (priv->state == STATE_ACTIVE_S)
2700 cxd2841er_read_status_s(fe, &status);
2701 else if (priv->state == STATE_ACTIVE_TC)
2702 cxd2841er_read_status_tc(fe, &status);
2703
2704 if (status & FE_HAS_LOCK) {
2705 cxd2841er_read_signal_strength(fe, &strength);
2706 p->strength.len = 1;
2707 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2708 p->strength.stat[0].uvalue = strength;
2709 cxd2841er_read_snr(fe, &snr);
2710 p->cnr.len = 1;
2711 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2712 p->cnr.stat[0].svalue = snr;
2713 cxd2841er_read_ucblocks(fe, &errors);
2714 p->block_error.len = 1;
2715 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2716 p->block_error.stat[0].uvalue = errors;
2717 cxd2841er_read_ber(fe, &ber);
2718 p->post_bit_error.len = 1;
2719 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2720 p->post_bit_error.stat[0].uvalue = ber;
2721 } else {
2722 p->strength.len = 1;
2723 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2724 p->cnr.len = 1;
2725 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2726 p->block_error.len = 1;
2727 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2728 p->post_bit_error.len = 1;
2729 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2730 }
2731 return 0;
2732}
2733
2734static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2735{
2736 int ret = 0, i, timeout, carr_offset;
2737 enum fe_status status;
2738 struct cxd2841er_priv *priv = fe->demodulator_priv;
2739 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2740 u32 symbol_rate = p->symbol_rate/1000;
2741
83808c23 2742 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
a6dc60ff
KS		 2743 __func__,
2744 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
83808c23 2745 p->frequency, symbol_rate, priv->xtal);
a6dc60ff
KS		 2746 switch (priv->state) {
2747 case STATE_SLEEP_S:
2748 ret = cxd2841er_sleep_s_to_active_s(
2749 priv, p->delivery_system, symbol_rate);
2750 break;
2751 case STATE_ACTIVE_S:
2752 ret = cxd2841er_retune_active(priv, p);
2753 break;
2754 default:
2755 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2756 __func__, priv->state);
2757 ret = -EINVAL;
2758 goto done;
2759 }
2760 if (ret) {
2761 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2762 goto done;
2763 }
2764 if (fe->ops.i2c_gate_ctrl)
2765 fe->ops.i2c_gate_ctrl(fe, 1);
2766 if (fe->ops.tuner_ops.set_params)
2767 fe->ops.tuner_ops.set_params(fe);
2768 if (fe->ops.i2c_gate_ctrl)
2769 fe->ops.i2c_gate_ctrl(fe, 0);
2770 cxd2841er_tune_done(priv);
2771 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2772 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2773 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2774 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2775 cxd2841er_read_status_s(fe, &status);
2776 if (status & FE_HAS_LOCK)
2777 break;
2778 }
2779 if (status & FE_HAS_LOCK) {
2780 if (cxd2841er_get_carrier_offset_s_s2(
2781 priv, &carr_offset)) {
2782 ret = -EINVAL;
2783 goto done;
2784 }
2785 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2786 __func__, carr_offset);
2787 }
2788done:
2789 return ret;
2790}
2791
2792static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2793{
2794 int ret = 0, timeout;
2795 enum fe_status status;
2796 struct cxd2841er_priv *priv = fe->demodulator_priv;
2797 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2798
2799 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2800 if (p->delivery_system == SYS_DVBT) {
2801 priv->system = SYS_DVBT;
2802 switch (priv->state) {
2803 case STATE_SLEEP_TC:
2804 ret = cxd2841er_sleep_tc_to_active_t(
2805 priv, p->bandwidth_hz);
2806 break;
2807 case STATE_ACTIVE_TC:
2808 ret = cxd2841er_retune_active(priv, p);
2809 break;
2810 default:
2811 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2812 __func__, priv->state);
2813 ret = -EINVAL;
2814 }
2815 } else if (p->delivery_system == SYS_DVBT2) {
2816 priv->system = SYS_DVBT2;
2817 cxd2841er_dvbt2_set_plp_config(priv,
2818 (int)(p->stream_id > 255), p->stream_id);
2819 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2820 switch (priv->state) {
2821 case STATE_SLEEP_TC:
2822 ret = cxd2841er_sleep_tc_to_active_t2(priv,
2823 p->bandwidth_hz);
2824 break;
2825 case STATE_ACTIVE_TC:
2826 ret = cxd2841er_retune_active(priv, p);
2827 break;
2828 default:
2829 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2830 __func__, priv->state);
2831 ret = -EINVAL;
2832 }
83808c23
AO		 2833 } else if (p->delivery_system == SYS_ISDBT) {
2834 priv->system = SYS_ISDBT;
2835 switch (priv->state) {
2836 case STATE_SLEEP_TC:
2837 ret = cxd2841er_sleep_tc_to_active_i(
2838 priv, p->bandwidth_hz);
2839 break;
2840 case STATE_ACTIVE_TC:
2841 ret = cxd2841er_retune_active(priv, p);
2842 break;
2843 default:
2844 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2845 __func__, priv->state);
2846 ret = -EINVAL;
2847 }
a6dc60ff
KS		 2848 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2849 p->delivery_system == SYS_DVBC_ANNEX_C) {
2850 priv->system = SYS_DVBC_ANNEX_A;
2851 switch (priv->state) {
2852 case STATE_SLEEP_TC:
2853 ret = cxd2841er_sleep_tc_to_active_c(
2854 priv, p->bandwidth_hz);
2855 break;
2856 case STATE_ACTIVE_TC:
2857 ret = cxd2841er_retune_active(priv, p);
2858 break;
2859 default:
2860 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2861 __func__, priv->state);
2862 ret = -EINVAL;
2863 }
2864 } else {
2865 dev_dbg(&priv->i2c->dev,
2866 "%s(): invalid delivery system %d\n",
2867 __func__, p->delivery_system);
2868 ret = -EINVAL;
2869 }
2870 if (ret)
2871 goto done;
2872 if (fe->ops.i2c_gate_ctrl)
2873 fe->ops.i2c_gate_ctrl(fe, 1);
2874 if (fe->ops.tuner_ops.set_params)
2875 fe->ops.tuner_ops.set_params(fe);
2876 if (fe->ops.i2c_gate_ctrl)
2877 fe->ops.i2c_gate_ctrl(fe, 0);
2878 cxd2841er_tune_done(priv);
2879 timeout = 2500;
2880 while (timeout > 0) {
2881 ret = cxd2841er_read_status_tc(fe, &status);
2882 if (ret)
2883 goto done;
2884 if (status & FE_HAS_LOCK)
2885 break;
2886 msleep(20);
2887 timeout -= 20;
2888 }
2889 if (timeout < 0)
2890 dev_dbg(&priv->i2c->dev,
2891 "%s(): LOCK wait timeout\n", __func__);
2892done:
2893 return ret;
2894}
2895
2896static int cxd2841er_tune_s(struct dvb_frontend *fe,
2897 bool re_tune,
2898 unsigned int mode_flags,
2899 unsigned int *delay,
2900 enum fe_status *status)
2901{
2902 int ret, carrier_offset;
2903 struct cxd2841er_priv *priv = fe->demodulator_priv;
2904 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2905
2906 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2907 if (re_tune) {
2908 ret = cxd2841er_set_frontend_s(fe);
2909 if (ret)
2910 return ret;
2911 cxd2841er_read_status_s(fe, status);
2912 if (*status & FE_HAS_LOCK) {
2913 if (cxd2841er_get_carrier_offset_s_s2(
2914 priv, &carrier_offset))
2915 return -EINVAL;
2916 p->frequency += carrier_offset;
2917 ret = cxd2841er_set_frontend_s(fe);
2918 if (ret)
2919 return ret;
2920 }
2921 }
2922 *delay = HZ / 5;
2923 return cxd2841er_read_status_s(fe, status);
2924}
2925
2926static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2927 bool re_tune,
2928 unsigned int mode_flags,
2929 unsigned int *delay,
2930 enum fe_status *status)
2931{
2932 int ret, carrier_offset;
2933 struct cxd2841er_priv *priv = fe->demodulator_priv;
2934 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2935
2936 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2937 if (re_tune) {
2938 ret = cxd2841er_set_frontend_tc(fe);
2939 if (ret)
2940 return ret;
2941 cxd2841er_read_status_tc(fe, status);
2942 if (*status & FE_HAS_LOCK) {
2943 switch (priv->system) {
2944 case SYS_DVBT:
c5ea46da
AO		 2945 ret = cxd2841er_get_carrier_offset_t(
2946 priv, p->bandwidth_hz,
2947 &carrier_offset);
2948 break;
a6dc60ff
KS		 2949 case SYS_DVBT2:
2950 ret = cxd2841er_get_carrier_offset_t2(
2951 priv, p->bandwidth_hz,
2952 &carrier_offset);
2953 break;
2954 case SYS_DVBC_ANNEX_A:
2955 ret = cxd2841er_get_carrier_offset_c(
2956 priv, &carrier_offset);
2957 break;
2958 default:
2959 dev_dbg(&priv->i2c->dev,
2960 "%s(): invalid delivery system %d\n",
2961 __func__, priv->system);
2962 return -EINVAL;
2963 }
2964 if (ret)
2965 return ret;
2966 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
2967 __func__, carrier_offset);
2968 p->frequency += carrier_offset;
2969 ret = cxd2841er_set_frontend_tc(fe);
2970 if (ret)
2971 return ret;
2972 }
2973 }
2974 *delay = HZ / 5;
2975 return cxd2841er_read_status_tc(fe, status);
2976}
2977
2978static int cxd2841er_sleep_s(struct dvb_frontend *fe)
2979{
2980 struct cxd2841er_priv *priv = fe->demodulator_priv;
2981
2982 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2983 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
2984 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
2985 return 0;
2986}
2987
2988static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
2989{
2990 struct cxd2841er_priv *priv = fe->demodulator_priv;
2991
2992 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2993 if (priv->state == STATE_ACTIVE_TC) {
2994 switch (priv->system) {
2995 case SYS_DVBT:
2996 cxd2841er_active_t_to_sleep_tc(priv);
2997 break;
2998 case SYS_DVBT2:
2999 cxd2841er_active_t2_to_sleep_tc(priv);
3000 break;
83808c23
AO		 3001 case SYS_ISDBT:
3002 cxd2841er_active_i_to_sleep_tc(priv);
3003 break;
a6dc60ff
KS		 3004 case SYS_DVBC_ANNEX_A:
3005 cxd2841er_active_c_to_sleep_tc(priv);
3006 break;
3007 default:
3008 dev_warn(&priv->i2c->dev,
3009 "%s(): unknown delivery system %d\n",
3010 __func__, priv->system);
3011 }
3012 }
3013 if (priv->state != STATE_SLEEP_TC) {
3014 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3015 __func__, priv->state);
3016 return -EINVAL;
3017 }
3018 cxd2841er_sleep_tc_to_shutdown(priv);
3019 return 0;
3020}
3021
3022static int cxd2841er_send_burst(struct dvb_frontend *fe,
3023 enum fe_sec_mini_cmd burst)
3024{
3025 u8 data;
3026 struct cxd2841er_priv *priv = fe->demodulator_priv;
3027
3028 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3029 (burst == SEC_MINI_A ? "A" : "B"));
3030 if (priv->state != STATE_SLEEP_S &&
3031 priv->state != STATE_ACTIVE_S) {
3032 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3033 __func__, priv->state);
3034 return -EINVAL;
3035 }
3036 data = (burst == SEC_MINI_A ? 0 : 1);
3037 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3038 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3039 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3040 return 0;
3041}
3042
3043static int cxd2841er_set_tone(struct dvb_frontend *fe,
3044 enum fe_sec_tone_mode tone)
3045{
3046 u8 data;
3047 struct cxd2841er_priv *priv = fe->demodulator_priv;
3048
3049 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3050 (tone == SEC_TONE_ON ? "On" : "Off"));
3051 if (priv->state != STATE_SLEEP_S &&
3052 priv->state != STATE_ACTIVE_S) {
3053 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3054 __func__, priv->state);
3055 return -EINVAL;
3056 }
3057 data = (tone == SEC_TONE_ON ? 1 : 0);
3058 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3059 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3060 return 0;
3061}
3062
3063static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3064 struct dvb_diseqc_master_cmd *cmd)
3065{
3066 int i;
3067 u8 data[12];
3068 struct cxd2841er_priv *priv = fe->demodulator_priv;
3069
3070 if (priv->state != STATE_SLEEP_S &&
3071 priv->state != STATE_ACTIVE_S) {
3072 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3073 __func__, priv->state);
3074 return -EINVAL;
3075 }
3076 dev_dbg(&priv->i2c->dev,
3077 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3078 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3079 /* DiDEqC enable */
3080 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3081 /* cmd1 length & data */
3082 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3083 memset(data, 0, sizeof(data));
3084 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3085 data[i] = cmd->msg[i];
3086 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3087 /* repeat count for cmd1 */
3088 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3089 /* repeat count for cmd2: always 0 */
3090 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3091 /* start transmit */
3092 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3093 /* wait for 1 sec timeout */
3094 for (i = 0; i < 50; i++) {
3095 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3096 if (!data[0]) {
3097 dev_dbg(&priv->i2c->dev,
3098 "%s(): DiSEqC cmd has been sent\n", __func__);
3099 return 0;
3100 }
3101 msleep(20);
3102 }
3103 dev_dbg(&priv->i2c->dev,
3104 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3105 return -ETIMEDOUT;
3106}
3107
3108static void cxd2841er_release(struct dvb_frontend *fe)
3109{
3110 struct cxd2841er_priv *priv = fe->demodulator_priv;
3111
3112 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3113 kfree(priv);
3114}
3115
3116static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3117{
3118 struct cxd2841er_priv *priv = fe->demodulator_priv;
3119
3120 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3121 cxd2841er_set_reg_bits(
3122 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3123 return 0;
3124}
3125
3126static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3127{
3128 struct cxd2841er_priv *priv = fe->demodulator_priv;
3129
3130 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3131 return DVBFE_ALGO_HW;
3132}
3133
3134static int cxd2841er_init_s(struct dvb_frontend *fe)
3135{
3136 struct cxd2841er_priv *priv = fe->demodulator_priv;
3137
30ae3307
AO		 3138 /* sanity. force demod to SHUTDOWN state */
3139 if (priv->state == STATE_SLEEP_S) {
3140 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3141 __func__);
3142 cxd2841er_sleep_s_to_shutdown(priv);
3143 } else if (priv->state == STATE_ACTIVE_S) {
3144 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3145 __func__);
3146 cxd2841er_active_s_to_sleep_s(priv);
3147 cxd2841er_sleep_s_to_shutdown(priv);
3148 }
3149
a6dc60ff
KS		 3150 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3151 cxd2841er_shutdown_to_sleep_s(priv);
3152 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3153 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3154 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3155 return 0;
3156}
3157
3158static int cxd2841er_init_tc(struct dvb_frontend *fe)
3159{
3160 struct cxd2841er_priv *priv = fe->demodulator_priv;
3161
3162 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3163 cxd2841er_shutdown_to_sleep_tc(priv);
3164 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3165 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3166 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3167 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3168 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3169 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3170 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3171 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3172 return 0;
3173}
3174
3175static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3176static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
3177static struct dvb_frontend_ops cxd2841er_dvbc_ops;
83808c23 3178static struct dvb_frontend_ops cxd2841er_isdbt_ops;
a6dc60ff
KS		 3179
3180static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3181 struct i2c_adapter *i2c,
3182 u8 system)
3183{
3184 u8 chip_id = 0;
3185 const char *type;
3186 struct cxd2841er_priv *priv = NULL;
3187
3188 /* allocate memory for the internal state */
3189 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3190 if (!priv)
3191 return NULL;
3192 priv->i2c = i2c;
3193 priv->config = cfg;
3194 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3195 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
83808c23 3196 priv->xtal = cfg->xtal;
a6dc60ff
KS		 3197 /* create dvb_frontend */
3198 switch (system) {
3199 case SYS_DVBS:
3200 memcpy(&priv->frontend.ops,
3201 &cxd2841er_dvbs_s2_ops,
3202 sizeof(struct dvb_frontend_ops));
3203 type = "S/S2";
3204 break;
3205 case SYS_DVBT:
3206 memcpy(&priv->frontend.ops,
3207 &cxd2841er_dvbt_t2_ops,
3208 sizeof(struct dvb_frontend_ops));
3209 type = "T/T2";
3210 break;
83808c23
AO		 3211 case SYS_ISDBT:
3212 memcpy(&priv->frontend.ops,
3213 &cxd2841er_isdbt_ops,
3214 sizeof(struct dvb_frontend_ops));
3215 type = "ISDBT";
3216 break;
a6dc60ff
KS		 3217 case SYS_DVBC_ANNEX_A:
3218 memcpy(&priv->frontend.ops,
3219 &cxd2841er_dvbc_ops,
3220 sizeof(struct dvb_frontend_ops));
3221 type = "C/C2";
3222 break;
3223 default:
3224 kfree(priv);
3225 return NULL;
3226 }
3227 priv->frontend.demodulator_priv = priv;
3228 dev_info(&priv->i2c->dev,
3229 "%s(): attaching CXD2841ER DVB-%s frontend\n",
3230 __func__, type);
3231 dev_info(&priv->i2c->dev,
3232 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3233 __func__, priv->i2c,
3234 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3235 chip_id = cxd2841er_chip_id(priv);
83808c23 3236 if (chip_id != CXD2841ER_CHIP_ID && chip_id != CXD2854ER_CHIP_ID) {
a6dc60ff
KS		 3237 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3238 __func__, chip_id);
3239 priv->frontend.demodulator_priv = NULL;
3240 kfree(priv);
3241 return NULL;
3242 }
3243 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3244 __func__, chip_id);
3245 return &priv->frontend;
3246}
3247
3248struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3249 struct i2c_adapter *i2c)
3250{
3251 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3252}
3253EXPORT_SYMBOL(cxd2841er_attach_s);
3254
3255struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
3256 struct i2c_adapter *i2c)
3257{
3258 return cxd2841er_attach(cfg, i2c, SYS_DVBT);
3259}
3260EXPORT_SYMBOL(cxd2841er_attach_t);
3261
83808c23
AO		 3262struct dvb_frontend *cxd2841er_attach_i(struct cxd2841er_config *cfg,
3263 struct i2c_adapter *i2c)
3264{
3265 return cxd2841er_attach(cfg, i2c, SYS_ISDBT);
3266}
3267EXPORT_SYMBOL(cxd2841er_attach_i);
3268
a6dc60ff
KS		 3269struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
3270 struct i2c_adapter *i2c)
3271{
3272 return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
3273}
3274EXPORT_SYMBOL(cxd2841er_attach_c);
3275
3276static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3277 .delsys = { SYS_DVBS, SYS_DVBS2 },
3278 .info = {
3279 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3280 .frequency_min = 500000,
3281 .frequency_max = 2500000,
3282 .frequency_stepsize = 0,
3283 .symbol_rate_min = 1000000,
3284 .symbol_rate_max = 45000000,
3285 .symbol_rate_tolerance = 500,
3286 .caps = FE_CAN_INVERSION_AUTO |
3287 FE_CAN_FEC_AUTO |
3288 FE_CAN_QPSK,
3289 },
3290 .init = cxd2841er_init_s,
3291 .sleep = cxd2841er_sleep_s,
3292 .release = cxd2841er_release,
3293 .set_frontend = cxd2841er_set_frontend_s,
3294 .get_frontend = cxd2841er_get_frontend,
3295 .read_status = cxd2841er_read_status_s,
3296 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3297 .get_frontend_algo = cxd2841er_get_algo,
3298 .set_tone = cxd2841er_set_tone,
3299 .diseqc_send_burst = cxd2841er_send_burst,
3300 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3301 .tune = cxd2841er_tune_s
3302};
3303
3304static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
3305 .delsys = { SYS_DVBT, SYS_DVBT2 },
3306 .info = {
3307 .name = "Sony CXD2841ER DVB-T/T2 demodulator",
3308 .caps = FE_CAN_FEC_1_2 |
3309 FE_CAN_FEC_2_3 |
3310 FE_CAN_FEC_3_4 |
3311 FE_CAN_FEC_5_6 |
3312 FE_CAN_FEC_7_8 |
3313 FE_CAN_FEC_AUTO |
3314 FE_CAN_QPSK |
3315 FE_CAN_QAM_16 |
3316 FE_CAN_QAM_32 |
3317 FE_CAN_QAM_64 |
3318 FE_CAN_QAM_128 |
3319 FE_CAN_QAM_256 |
3320 FE_CAN_QAM_AUTO |
3321 FE_CAN_TRANSMISSION_MODE_AUTO |
3322 FE_CAN_GUARD_INTERVAL_AUTO |
3323 FE_CAN_HIERARCHY_AUTO |
3324 FE_CAN_MUTE_TS |
3325 FE_CAN_2G_MODULATION,
3326 .frequency_min = 42000000,
3327 .frequency_max = 1002000000
3328 },
3329 .init = cxd2841er_init_tc,
3330 .sleep = cxd2841er_sleep_tc,
3331 .release = cxd2841er_release,
3332 .set_frontend = cxd2841er_set_frontend_tc,
3333 .get_frontend = cxd2841er_get_frontend,
3334 .read_status = cxd2841er_read_status_tc,
3335 .tune = cxd2841er_tune_tc,
3336 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3337 .get_frontend_algo = cxd2841er_get_algo
3338};
3339
83808c23
AO		 3340static struct dvb_frontend_ops cxd2841er_isdbt_ops = {
3341 .delsys = { SYS_ISDBT },
3342 .info = {
3343 .name = "Sony CXD2854ER ISDBT demodulator",
3344 .caps = FE_CAN_FEC_1_2 |
3345 FE_CAN_FEC_2_3 |
3346 FE_CAN_FEC_3_4 |
3347 FE_CAN_FEC_5_6 |
3348 FE_CAN_FEC_7_8 |
3349 FE_CAN_FEC_AUTO |
3350 FE_CAN_QPSK |
3351 FE_CAN_QAM_16 |
3352 FE_CAN_QAM_32 |
3353 FE_CAN_QAM_64 |
3354 FE_CAN_QAM_128 |
3355 FE_CAN_QAM_256 |
3356 FE_CAN_QAM_AUTO |
3357 FE_CAN_TRANSMISSION_MODE_AUTO |
3358 FE_CAN_GUARD_INTERVAL_AUTO |
3359 FE_CAN_HIERARCHY_AUTO |
3360 FE_CAN_MUTE_TS |
3361 FE_CAN_2G_MODULATION,
3362 .frequency_min = 42000000,
3363 .frequency_max = 1002000000
3364 },
3365 .init = cxd2841er_init_tc,
3366 .sleep = cxd2841er_sleep_tc,
3367 .release = cxd2841er_release,
3368 .set_frontend = cxd2841er_set_frontend_tc,
3369 .get_frontend = cxd2841er_get_frontend,
3370 .read_status = cxd2841er_read_status_tc,
3371 .tune = cxd2841er_tune_tc,
3372 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3373 .get_frontend_algo = cxd2841er_get_algo
3374};
3375
a6dc60ff
KS		 3376static struct dvb_frontend_ops cxd2841er_dvbc_ops = {
3377 .delsys = { SYS_DVBC_ANNEX_A },
3378 .info = {
3379 .name = "Sony CXD2841ER DVB-C demodulator",
3380 .caps = FE_CAN_FEC_1_2 |
3381 FE_CAN_FEC_2_3 |
3382 FE_CAN_FEC_3_4 |
3383 FE_CAN_FEC_5_6 |
3384 FE_CAN_FEC_7_8 |
3385 FE_CAN_FEC_AUTO |
3386 FE_CAN_QAM_16 |
3387 FE_CAN_QAM_32 |
3388 FE_CAN_QAM_64 |
3389 FE_CAN_QAM_128 |
3390 FE_CAN_QAM_256 |
3391 FE_CAN_QAM_AUTO |
3392 FE_CAN_INVERSION_AUTO,
3393 .frequency_min = 42000000,
3394 .frequency_max = 1002000000
3395 },
3396 .init = cxd2841er_init_tc,
3397 .sleep = cxd2841er_sleep_tc,
3398 .release = cxd2841er_release,
3399 .set_frontend = cxd2841er_set_frontend_tc,
3400 .get_frontend = cxd2841er_get_frontend,
3401 .read_status = cxd2841er_read_status_tc,
3402 .tune = cxd2841er_tune_tc,
3403 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3404 .get_frontend_algo = cxd2841er_get_algo,
3405};
3406
83808c23
AO		 3407MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3408MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
a6dc60ff 3409MODULE_LICENSE("GPL");
ubuntu-zesty-kernel mirror