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[media] dvb-frontends/cxd2841er: optionally tune earlier in set_frontend()
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / cxd2841er.c
CommitLineData
a6dc60ff
KS		 1/*
2 * cxd2841er.c
3 *
83808c23 4 * Sony digital demodulator driver for
9ca1736f
AO		 5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
a6dc60ff
KS		 7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
d13a7b67 38#define MAX_WRITE_REGSIZE 16
a6f330cb
AO		 39#define LOG2_E_100X 144
40
41/* DVB-C constellation */
42enum sony_dvbc_constellation_t {
43 SONY_DVBC_CONSTELLATION_16QAM,
44 SONY_DVBC_CONSTELLATION_32QAM,
45 SONY_DVBC_CONSTELLATION_64QAM,
46 SONY_DVBC_CONSTELLATION_128QAM,
47 SONY_DVBC_CONSTELLATION_256QAM
48};
d13a7b67 49
a6dc60ff
KS		 50enum cxd2841er_state {
51 STATE_SHUTDOWN = 0,
52 STATE_SLEEP_S,
53 STATE_ACTIVE_S,
54 STATE_SLEEP_TC,
55 STATE_ACTIVE_TC
56};
57
58struct cxd2841er_priv {
59 struct dvb_frontend frontend;
60 struct i2c_adapter *i2c;
61 u8 i2c_addr_slvx;
62 u8 i2c_addr_slvt;
63 const struct cxd2841er_config *config;
64 enum cxd2841er_state state;
65 u8 system;
83808c23 66 enum cxd2841er_xtal xtal;
3f3b48a0 67 enum fe_caps caps;
050863aa 68 u32 flags;
a6dc60ff
KS		 69};
70
71static const struct cxd2841er_cnr_data s_cn_data[] = {
72 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
73 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
74 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
75 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
76 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
77 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
78 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
79 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
80 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
81 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
82 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
83 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
84 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
85 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
86 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
87 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
88 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
89 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
90 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
91 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
92 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
93 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
94 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
95 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
96 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
97 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
98 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
99 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
100 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
101 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
102 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
103 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
104 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
105 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
106 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
107 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
108 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
109 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
110 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
111 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
112 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
113 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
114 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
115 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
116 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
117 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
118 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
119 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
120 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
121 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
122 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
123 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
124 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
125 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
126 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
127 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
128 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
129 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
130 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
131 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
132 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
133 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
134 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
135 { 0x0015, 19900 }, { 0x0014, 20000 },
136};
137
138static const struct cxd2841er_cnr_data s2_cn_data[] = {
139 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
140 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
141 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
142 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
143 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
144 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
145 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
146 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
147 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
148 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
149 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
150 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
151 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
152 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
153 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
154 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
155 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
156 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
157 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
158 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
159 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
160 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
161 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
162 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
163 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
164 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
165 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
166 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
167 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
168 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
169 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
170 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
171 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
172 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
173 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
174 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
175 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
176 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
177 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
178 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
179 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
180 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
181 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
182 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
183 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
184 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
185 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
186 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
187 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
188 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
189 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
190 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
191 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
192 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
193 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
194 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
195 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
196 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
197 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
198 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
199 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
200 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
201 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
202 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
203};
204
0854df79
AO		 205static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
206static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
207
a6dc60ff
KS		 208static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
209 u8 addr, u8 reg, u8 write,
210 const u8 *data, u32 len)
211{
212 dev_dbg(&priv->i2c->dev,
5d6d93a1
DS		 213 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
214 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
a6dc60ff
KS		 215}
216
217static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
218 u8 addr, u8 reg, const u8 *data, u32 len)
219{
220 int ret;
d13a7b67 221 u8 buf[MAX_WRITE_REGSIZE + 1];
a6dc60ff
KS		 222 u8 i2c_addr = (addr == I2C_SLVX ?
223 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
224 struct i2c_msg msg[1] = {
225 {
226 .addr = i2c_addr,
227 .flags = 0,
d13a7b67 228 .len = len + 1,
a6dc60ff
KS		 229 .buf = buf,
230 }
231 };
232
d13a7b67 233 if (len + 1 >= sizeof(buf)) {
83808c23 234 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
d13a7b67
MCC		 235 reg, len + 1);
236 return -E2BIG;
237 }
238
a6dc60ff
KS		 239 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
240 buf[0] = reg;
241 memcpy(&buf[1], data, len);
242
243 ret = i2c_transfer(priv->i2c, msg, 1);
244 if (ret >= 0 && ret != 1)
245 ret = -EIO;
246 if (ret < 0) {
247 dev_warn(&priv->i2c->dev,
248 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
249 KBUILD_MODNAME, ret, i2c_addr, reg, len);
250 return ret;
251 }
252 return 0;
253}
254
255static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
256 u8 addr, u8 reg, u8 val)
257{
258 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
259}
260
261static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
262 u8 addr, u8 reg, u8 *val, u32 len)
263{
264 int ret;
265 u8 i2c_addr = (addr == I2C_SLVX ?
266 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
267 struct i2c_msg msg[2] = {
268 {
269 .addr = i2c_addr,
270 .flags = 0,
271 .len = 1,
272 .buf = &reg,
273 }, {
274 .addr = i2c_addr,
275 .flags = I2C_M_RD,
276 .len = len,
277 .buf = val,
278 }
279 };
280
725e93eb
DS		 281 ret = i2c_transfer(priv->i2c, msg, 2);
282 if (ret >= 0 && ret != 2)
a6dc60ff
KS		 283 ret = -EIO;
284 if (ret < 0) {
285 dev_warn(&priv->i2c->dev,
286 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
287 KBUILD_MODNAME, ret, i2c_addr, reg);
288 return ret;
289 }
6c77161a 290 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
a6dc60ff
KS		 291 return 0;
292}
293
294static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
295 u8 addr, u8 reg, u8 *val)
296{
297 return cxd2841er_read_regs(priv, addr, reg, val, 1);
298}
299
300static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
301 u8 addr, u8 reg, u8 data, u8 mask)
302{
303 int res;
304 u8 rdata;
305
306 if (mask != 0xff) {
307 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
308 if (res)
309 return res;
310 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
311 }
312 return cxd2841er_write_reg(priv, addr, reg, data);
313}
314
cbc85a47
DS		 315static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
316{
317 u64 tmp;
318
319 tmp = (u64) ifhz * 16777216;
320 do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
321
322 return (u32) tmp;
323}
324
325static u32 cxd2841er_calc_iffreq(u32 ifhz)
326{
327 return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
328}
329
4b866c4e
DS		 330static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
331{
332 u32 hz;
333
334 if (priv->frontend.ops.tuner_ops.get_if_frequency
335 && (priv->flags & CXD2841ER_AUTO_IFHZ))
336 priv->frontend.ops.tuner_ops.get_if_frequency(
337 &priv->frontend, &hz);
338 else
339 hz = def_hz;
340
341 return hz;
342}
343
c7518d13
DS		 344static int cxd2841er_tuner_set(struct dvb_frontend *fe)
345{
346 struct cxd2841er_priv *priv = fe->demodulator_priv;
347
348 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
349 fe->ops.i2c_gate_ctrl(fe, 1);
350 if (fe->ops.tuner_ops.set_params)
351 fe->ops.tuner_ops.set_params(fe);
352 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
353 fe->ops.i2c_gate_ctrl(fe, 0);
354
355 return 0;
356}
357
a6dc60ff
KS		 358static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
359 u32 symbol_rate)
360{
361 u32 reg_value = 0;
362 u8 data[3] = {0, 0, 0};
363
364 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
365 /*
366 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
367 * = ((symbolRateKSps * 2^14) + 500) / 1000
368 * = ((symbolRateKSps * 16384) + 500) / 1000
369 */
370 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
371 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
372 dev_err(&priv->i2c->dev,
373 "%s(): reg_value is out of range\n", __func__);
374 return -EINVAL;
375 }
376 data[0] = (u8)((reg_value >> 16) & 0x0F);
377 data[1] = (u8)((reg_value >> 8) & 0xFF);
378 data[2] = (u8)(reg_value & 0xFF);
379 /* Set SLV-T Bank : 0xAE */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
381 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
382 return 0;
383}
384
385static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
386 u8 system);
387
388static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
389 u8 system, u32 symbol_rate)
390{
391 int ret;
392 u8 data[4] = { 0, 0, 0, 0 };
393
394 if (priv->state != STATE_SLEEP_S) {
395 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
396 __func__, (int)priv->state);
397 return -EINVAL;
398 }
399 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
400 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
401 /* Set demod mode */
402 if (system == SYS_DVBS) {
403 data[0] = 0x0A;
404 } else if (system == SYS_DVBS2) {
405 data[0] = 0x0B;
406 } else {
407 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
408 __func__, system);
409 return -EINVAL;
410 }
411 /* Set SLV-X Bank : 0x00 */
412 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
413 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
414 /* DVB-S/S2 */
415 data[0] = 0x00;
416 /* Set SLV-T Bank : 0x00 */
417 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
418 /* Enable S/S2 auto detection 1 */
419 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
420 /* Set SLV-T Bank : 0xAE */
421 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
422 /* Enable S/S2 auto detection 2 */
423 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
424 /* Set SLV-T Bank : 0x00 */
425 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
426 /* Enable demod clock */
427 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
428 /* Enable ADC clock */
429 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
430 /* Enable ADC 1 */
431 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
432 /* Enable ADC 2 */
433 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
434 /* Set SLV-X Bank : 0x00 */
435 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
436 /* Enable ADC 3 */
437 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
438 /* Set SLV-T Bank : 0xA3 */
439 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
440 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
441 data[0] = 0x07;
442 data[1] = 0x3B;
443 data[2] = 0x08;
444 data[3] = 0xC5;
445 /* Set SLV-T Bank : 0xAB */
446 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
447 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
448 data[0] = 0x05;
449 data[1] = 0x80;
450 data[2] = 0x0A;
451 data[3] = 0x80;
452 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
453 data[0] = 0x0C;
454 data[1] = 0xCC;
455 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
456 /* Set demod parameter */
457 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
458 if (ret != 0)
459 return ret;
460 /* Set SLV-T Bank : 0x00 */
461 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
462 /* disable Hi-Z setting 1 */
463 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
464 /* disable Hi-Z setting 2 */
465 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
466 priv->state = STATE_ACTIVE_S;
467 return 0;
468}
469
470static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
471 u32 bandwidth);
472
473static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
474 u32 bandwidth);
475
476static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
477 u32 bandwidth);
478
76344a3f
MCC		 479static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
480 u32 bandwidth);
481
482static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
483
484static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
485
486static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
487
a6dc60ff
KS		 488static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
489 struct dtv_frontend_properties *p)
490{
491 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
492 if (priv->state != STATE_ACTIVE_S &&
493 priv->state != STATE_ACTIVE_TC) {
494 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
495 __func__, priv->state);
496 return -EINVAL;
497 }
498 /* Set SLV-T Bank : 0x00 */
499 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
500 /* disable TS output */
501 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
502 if (priv->state == STATE_ACTIVE_S)
503 return cxd2841er_dvbs2_set_symbol_rate(
504 priv, p->symbol_rate / 1000);
505 else if (priv->state == STATE_ACTIVE_TC) {
506 switch (priv->system) {
507 case SYS_DVBT:
508 return cxd2841er_sleep_tc_to_active_t_band(
509 priv, p->bandwidth_hz);
510 case SYS_DVBT2:
511 return cxd2841er_sleep_tc_to_active_t2_band(
512 priv, p->bandwidth_hz);
513 case SYS_DVBC_ANNEX_A:
514 return cxd2841er_sleep_tc_to_active_c_band(
76344a3f
MCC		 515 priv, p->bandwidth_hz);
516 case SYS_ISDBT:
517 cxd2841er_active_i_to_sleep_tc(priv);
518 cxd2841er_sleep_tc_to_shutdown(priv);
519 cxd2841er_shutdown_to_sleep_tc(priv);
520 return cxd2841er_sleep_tc_to_active_i(
521 priv, p->bandwidth_hz);
a6dc60ff
KS		 522 }
523 }
524 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
525 __func__, priv->system);
526 return -EINVAL;
527}
528
529static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
530{
531 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
532 if (priv->state != STATE_ACTIVE_S) {
533 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
534 __func__, priv->state);
535 return -EINVAL;
536 }
537 /* Set SLV-T Bank : 0x00 */
538 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
539 /* disable TS output */
540 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
541 /* enable Hi-Z setting 1 */
542 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
543 /* enable Hi-Z setting 2 */
544 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
545 /* Set SLV-X Bank : 0x00 */
546 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
547 /* disable ADC 1 */
548 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
549 /* Set SLV-T Bank : 0x00 */
550 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
551 /* disable ADC clock */
552 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
553 /* disable ADC 2 */
554 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
555 /* disable ADC 3 */
556 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
557 /* SADC Bias ON */
558 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
559 /* disable demod clock */
560 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
561 /* Set SLV-T Bank : 0xAE */
562 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
563 /* disable S/S2 auto detection1 */
564 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
565 /* Set SLV-T Bank : 0x00 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
567 /* disable S/S2 auto detection2 */
568 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
569 priv->state = STATE_SLEEP_S;
570 return 0;
571}
572
573static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
574{
575 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
576 if (priv->state != STATE_SLEEP_S) {
577 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
578 __func__, priv->state);
579 return -EINVAL;
580 }
581 /* Set SLV-T Bank : 0x00 */
582 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
583 /* Disable DSQOUT */
584 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
585 /* Disable DSQIN */
586 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
587 /* Set SLV-X Bank : 0x00 */
588 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
589 /* Disable oscillator */
590 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
591 /* Set demod mode */
592 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
593 priv->state = STATE_SHUTDOWN;
594 return 0;
595}
596
597static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
598{
599 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
600 if (priv->state != STATE_SLEEP_TC) {
601 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
602 __func__, priv->state);
603 return -EINVAL;
604 }
605 /* Set SLV-X Bank : 0x00 */
606 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
607 /* Disable oscillator */
608 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
609 /* Set demod mode */
610 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
611 priv->state = STATE_SHUTDOWN;
612 return 0;
613}
614
615static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
616{
617 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
618 if (priv->state != STATE_ACTIVE_TC) {
619 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
620 __func__, priv->state);
621 return -EINVAL;
622 }
623 /* Set SLV-T Bank : 0x00 */
624 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
625 /* disable TS output */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
627 /* enable Hi-Z setting 1 */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
629 /* enable Hi-Z setting 2 */
630 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
631 /* Set SLV-X Bank : 0x00 */
632 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
633 /* disable ADC 1 */
634 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
635 /* Set SLV-T Bank : 0x00 */
636 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
637 /* Disable ADC 2 */
638 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
639 /* Disable ADC 3 */
640 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
641 /* Disable ADC clock */
642 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
643 /* Disable RF level monitor */
644 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
645 /* Disable demod clock */
646 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
647 priv->state = STATE_SLEEP_TC;
648 return 0;
649}
650
651static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
652{
653 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
654 if (priv->state != STATE_ACTIVE_TC) {
655 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
656 __func__, priv->state);
657 return -EINVAL;
658 }
659 /* Set SLV-T Bank : 0x00 */
660 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
661 /* disable TS output */
662 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
663 /* enable Hi-Z setting 1 */
664 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
665 /* enable Hi-Z setting 2 */
666 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
667 /* Cancel DVB-T2 setting */
668 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
670 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
671 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
672 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
675 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
676 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
677 /* Set SLV-X Bank : 0x00 */
678 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
679 /* disable ADC 1 */
680 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
681 /* Set SLV-T Bank : 0x00 */
682 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
683 /* Disable ADC 2 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
685 /* Disable ADC 3 */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
687 /* Disable ADC clock */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
689 /* Disable RF level monitor */
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
691 /* Disable demod clock */
692 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
693 priv->state = STATE_SLEEP_TC;
694 return 0;
695}
696
697static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
698{
699 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
700 if (priv->state != STATE_ACTIVE_TC) {
701 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
702 __func__, priv->state);
703 return -EINVAL;
704 }
705 /* Set SLV-T Bank : 0x00 */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
707 /* disable TS output */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
709 /* enable Hi-Z setting 1 */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
711 /* enable Hi-Z setting 2 */
712 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
713 /* Cancel DVB-C setting */
714 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
715 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
716 /* Set SLV-X Bank : 0x00 */
717 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
718 /* disable ADC 1 */
719 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
720 /* Set SLV-T Bank : 0x00 */
721 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
722 /* Disable ADC 2 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
724 /* Disable ADC 3 */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
726 /* Disable ADC clock */
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
728 /* Disable RF level monitor */
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
730 /* Disable demod clock */
731 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
732 priv->state = STATE_SLEEP_TC;
733 return 0;
734}
735
83808c23
AO		 736static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
737{
738 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
739 if (priv->state != STATE_ACTIVE_TC) {
740 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
741 __func__, priv->state);
742 return -EINVAL;
743 }
744 /* Set SLV-T Bank : 0x00 */
745 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
746 /* disable TS output */
747 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
748 /* enable Hi-Z setting 1 */
749 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
750 /* enable Hi-Z setting 2 */
751 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
752
753 /* TODO: Cancel demod parameter */
754
755 /* Set SLV-X Bank : 0x00 */
756 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
757 /* disable ADC 1 */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
759 /* Set SLV-T Bank : 0x00 */
760 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
761 /* Disable ADC 2 */
762 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
763 /* Disable ADC 3 */
764 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
765 /* Disable ADC clock */
766 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
767 /* Disable RF level monitor */
768 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
769 /* Disable demod clock */
770 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
771 priv->state = STATE_SLEEP_TC;
772 return 0;
773}
774
a6dc60ff
KS		 775static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
776{
777 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
778 if (priv->state != STATE_SHUTDOWN) {
779 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
780 __func__, priv->state);
781 return -EINVAL;
782 }
783 /* Set SLV-X Bank : 0x00 */
784 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
785 /* Clear all demodulator registers */
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
787 usleep_range(3000, 5000);
788 /* Set SLV-X Bank : 0x00 */
789 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
790 /* Set demod SW reset */
791 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
83808c23
AO		 792
793 switch (priv->xtal) {
794 case SONY_XTAL_20500:
795 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
796 break;
797 case SONY_XTAL_24000:
798 /* Select demod frequency */
799 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
800 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
801 break;
802 case SONY_XTAL_41000:
803 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
804 break;
805 default:
806 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
807 __func__, priv->xtal);
808 return -EINVAL;
809 }
810
a6dc60ff
KS		 811 /* Set demod mode */
812 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
813 /* Clear demod SW reset */
814 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
815 usleep_range(1000, 2000);
816 /* Set SLV-T Bank : 0x00 */
817 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
818 /* enable DSQOUT */
819 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
820 /* enable DSQIN */
821 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
822 /* TADC Bias On */
823 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
824 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
825 /* SADC Bias On */
826 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
827 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
828 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
829 priv->state = STATE_SLEEP_S;
830 return 0;
831}
832
833static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
834{
6c77161a 835 u8 data = 0;
3f3b48a0 836
a6dc60ff
KS		 837 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
838 if (priv->state != STATE_SHUTDOWN) {
839 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
840 __func__, priv->state);
841 return -EINVAL;
842 }
843 /* Set SLV-X Bank : 0x00 */
844 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
845 /* Clear all demodulator registers */
846 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
847 usleep_range(3000, 5000);
848 /* Set SLV-X Bank : 0x00 */
849 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
850 /* Set demod SW reset */
851 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
6c77161a 852 /* Select ADC clock mode */
a6dc60ff 853 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
6c77161a
AO		 854
855 switch (priv->xtal) {
856 case SONY_XTAL_20500:
857 data = 0x0;
858 break;
859 case SONY_XTAL_24000:
860 /* Select demod frequency */
861 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
862 data = 0x3;
863 break;
864 case SONY_XTAL_41000:
865 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
866 data = 0x1;
867 break;
868 }
869 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
a6dc60ff
KS		 870 /* Clear demod SW reset */
871 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
872 usleep_range(1000, 2000);
873 /* Set SLV-T Bank : 0x00 */
874 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
875 /* TADC Bias On */
876 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
877 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
878 /* SADC Bias On */
879 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
880 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
881 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
882 priv->state = STATE_SLEEP_TC;
883 return 0;
884}
885
886static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
887{
888 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
889 /* Set SLV-T Bank : 0x00 */
890 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
891 /* SW Reset */
892 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
893 /* Enable TS output */
894 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
895 return 0;
896}
897
898/* Set TS parallel mode */
899static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
900 u8 system)
901{
902 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
903
904 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
905 /* Set SLV-T Bank : 0x00 */
906 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
907 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
908 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
909 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
910 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
911 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
912
03ab1bd5
DS		 913 /*
914 * slave Bank Addr Bit default Name
915 * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE
916 */
917 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
918 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
919 /*
920 * slave Bank Addr Bit default Name
921 * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE
922 */
923 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
924 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
a6dc60ff
KS		 925 /*
926 * slave Bank Addr Bit default Name
927 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
928 */
929 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
930 /*
931 * Disable TS IF Clock
932 * slave Bank Addr Bit default Name
933 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
934 */
935 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
936 /*
937 * slave Bank Addr Bit default Name
938 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
939 */
03ab1bd5
DS		 940 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
941 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
a6dc60ff
KS		 942 /*
943 * Enable TS IF Clock
944 * slave Bank Addr Bit default Name
945 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
946 */
947 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
948
949 if (system == SYS_DVBT) {
950 /* Enable parity period for DVB-T */
951 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
952 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
953 } else if (system == SYS_DVBC_ANNEX_A) {
954 /* Enable parity period for DVB-C */
955 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
956 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
957 }
958}
959
960static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
961{
83808c23 962 u8 chip_id = 0;
a6dc60ff
KS		 963
964 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
83808c23
AO		 965 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
966 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
967 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
968 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
969
a6dc60ff
KS		 970 return chip_id;
971}
972
973static int cxd2841er_read_status_s(struct dvb_frontend *fe,
974 enum fe_status *status)
975{
976 u8 reg = 0;
977 struct cxd2841er_priv *priv = fe->demodulator_priv;
978
979 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
980 *status = 0;
981 if (priv->state != STATE_ACTIVE_S) {
982 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
983 __func__, priv->state);
984 return -EINVAL;
985 }
986 /* Set SLV-T Bank : 0xA0 */
987 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
988 /*
989 * slave Bank Addr Bit Signal name
990 * <SLV-T> A0h 11h [2] ITSLOCK
991 */
992 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
993 if (reg & 0x04) {
994 *status = FE_HAS_SIGNAL
995 | FE_HAS_CARRIER
996 | FE_HAS_VITERBI
997 | FE_HAS_SYNC
998 | FE_HAS_LOCK;
999 }
1000 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1001 return 0;
1002}
1003
1004static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1005 u8 *sync, u8 *tslock, u8 *unlock)
1006{
1007 u8 data = 0;
1008
1009 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1010 if (priv->state != STATE_ACTIVE_TC)
1011 return -EINVAL;
1012 if (priv->system == SYS_DVBT) {
1013 /* Set SLV-T Bank : 0x10 */
1014 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1015 } else {
1016 /* Set SLV-T Bank : 0x20 */
1017 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1018 }
1019 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1020 if ((data & 0x07) == 0x07) {
1021 dev_dbg(&priv->i2c->dev,
1022 "%s(): invalid hardware state detected\n", __func__);
1023 *sync = 0;
1024 *tslock = 0;
1025 *unlock = 0;
1026 } else {
1027 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1028 *tslock = ((data & 0x20) ? 1 : 0);
1029 *unlock = ((data & 0x10) ? 1 : 0);
1030 }
1031 return 0;
1032}
1033
1034static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1035{
1036 u8 data;
1037
1038 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1039 if (priv->state != STATE_ACTIVE_TC)
1040 return -EINVAL;
1041 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1042 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1043 if ((data & 0x01) == 0) {
1044 *tslock = 0;
1045 } else {
1046 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1047 *tslock = ((data & 0x20) ? 1 : 0);
1048 }
1049 return 0;
1050}
1051
83808c23
AO		 1052static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1053 u8 *sync, u8 *tslock, u8 *unlock)
1054{
1055 u8 data = 0;
1056
1057 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1058 if (priv->state != STATE_ACTIVE_TC)
1059 return -EINVAL;
1060 /* Set SLV-T Bank : 0x60 */
1061 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1062 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1063 dev_dbg(&priv->i2c->dev,
1064 "%s(): lock=0x%x\n", __func__, data);
1065 *sync = ((data & 0x02) ? 1 : 0);
1066 *tslock = ((data & 0x01) ? 1 : 0);
1067 *unlock = ((data & 0x10) ? 1 : 0);
1068 return 0;
1069}
1070
a6dc60ff
KS		 1071static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1072 enum fe_status *status)
1073{
1074 int ret = 0;
1075 u8 sync = 0;
1076 u8 tslock = 0;
1077 u8 unlock = 0;
1078 struct cxd2841er_priv *priv = fe->demodulator_priv;
1079
1080 *status = 0;
1081 if (priv->state == STATE_ACTIVE_TC) {
1082 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1083 ret = cxd2841er_read_status_t_t2(
1084 priv, &sync, &tslock, &unlock);
1085 if (ret)
1086 goto done;
1087 if (unlock)
1088 goto done;
1089 if (sync)
1090 *status = FE_HAS_SIGNAL |
1091 FE_HAS_CARRIER |
1092 FE_HAS_VITERBI |
1093 FE_HAS_SYNC;
1094 if (tslock)
1095 *status |= FE_HAS_LOCK;
83808c23
AO		 1096 } else if (priv->system == SYS_ISDBT) {
1097 ret = cxd2841er_read_status_i(
1098 priv, &sync, &tslock, &unlock);
1099 if (ret)
1100 goto done;
1101 if (unlock)
1102 goto done;
1103 if (sync)
1104 *status = FE_HAS_SIGNAL |
1105 FE_HAS_CARRIER |
1106 FE_HAS_VITERBI |
1107 FE_HAS_SYNC;
1108 if (tslock)
1109 *status |= FE_HAS_LOCK;
a6dc60ff
KS		 1110 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1111 ret = cxd2841er_read_status_c(priv, &tslock);
1112 if (ret)
1113 goto done;
1114 if (tslock)
1115 *status = FE_HAS_SIGNAL |
1116 FE_HAS_CARRIER |
1117 FE_HAS_VITERBI |
1118 FE_HAS_SYNC |
1119 FE_HAS_LOCK;
1120 }
1121 }
1122done:
1123 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1124 return ret;
1125}
1126
1127static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1128 int *offset)
1129{
1130 u8 data[3];
1131 u8 is_hs_mode;
1132 s32 cfrl_ctrlval;
1133 s32 temp_div, temp_q, temp_r;
1134
1135 if (priv->state != STATE_ACTIVE_S) {
1136 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1137 __func__, priv->state);
1138 return -EINVAL;
1139 }
1140 /*
1141 * Get High Sampling Rate mode
1142 * slave Bank Addr Bit Signal name
1143 * <SLV-T> A0h 10h [0] ITRL_LOCK
1144 */
1145 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1146 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1147 if (data[0] & 0x01) {
1148 /*
1149 * slave Bank Addr Bit Signal name
1150 * <SLV-T> A0h 50h [4] IHSMODE
1151 */
1152 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1153 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1154 } else {
1155 dev_dbg(&priv->i2c->dev,
1156 "%s(): unable to detect sampling rate mode\n",
1157 __func__);
1158 return -EINVAL;
1159 }
1160 /*
1161 * slave Bank Addr Bit Signal name
1162 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1163 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1164 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1165 */
1166 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1167 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1168 (((u32)data[1] & 0xFF) << 8) |
1169 ((u32)data[2] & 0xFF), 20);
1170 temp_div = (is_hs_mode ? 1048576 : 1572864);
1171 if (cfrl_ctrlval > 0) {
1172 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1173 temp_div, &temp_r);
1174 } else {
1175 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1176 temp_div, &temp_r);
1177 }
1178 if (temp_r >= temp_div / 2)
1179 temp_q++;
1180 if (cfrl_ctrlval > 0)
1181 temp_q *= -1;
1182 *offset = temp_q;
1183 return 0;
1184}
1185
76344a3f
MCC		 1186static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1187 u32 bandwidth, int *offset)
1188{
1189 u8 data[4];
1190
1191 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1192 if (priv->state != STATE_ACTIVE_TC) {
1193 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1194 __func__, priv->state);
1195 return -EINVAL;
1196 }
1197 if (priv->system != SYS_ISDBT) {
1198 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1199 __func__, priv->system);
1200 return -EINVAL;
1201 }
1202 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1203 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1204 *offset = -1 * sign_extend32(
1205 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1206 ((u32)data[2] << 8) | (u32)data[3], 29);
1207
1208 switch (bandwidth) {
1209 case 6000000:
1210 *offset = -1 * ((*offset) * 8/264);
1211 break;
1212 case 7000000:
1213 *offset = -1 * ((*offset) * 8/231);
1214 break;
1215 case 8000000:
1216 *offset = -1 * ((*offset) * 8/198);
1217 break;
1218 default:
1219 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1220 __func__, bandwidth);
1221 return -EINVAL;
1222 }
1223
1224 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1225 __func__, bandwidth, *offset);
1226
1227 return 0;
1228}
1229
c5ea46da
AO		 1230static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1231 u32 bandwidth, int *offset)
1232{
1233 u8 data[4];
1234
1235 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1236 if (priv->state != STATE_ACTIVE_TC) {
1237 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1238 __func__, priv->state);
1239 return -EINVAL;
1240 }
1241 if (priv->system != SYS_DVBT) {
1242 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1243 __func__, priv->system);
1244 return -EINVAL;
1245 }
1246 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1247 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1248 *offset = -1 * sign_extend32(
1249 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1250 ((u32)data[2] << 8) | (u32)data[3], 29);
6c77161a
AO		 1251 *offset *= (bandwidth / 1000000);
1252 *offset /= 235;
c5ea46da
AO		 1253 return 0;
1254}
1255
c8946c8d
MCC		 1256static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1257 u32 bandwidth, int *offset)
a6dc60ff
KS		 1258{
1259 u8 data[4];
1260
1261 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1262 if (priv->state != STATE_ACTIVE_TC) {
1263 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1264 __func__, priv->state);
1265 return -EINVAL;
1266 }
1267 if (priv->system != SYS_DVBT2) {
1268 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1269 __func__, priv->system);
1270 return -EINVAL;
1271 }
1272 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1273 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1274 *offset = -1 * sign_extend32(
1275 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1276 ((u32)data[2] << 8) | (u32)data[3], 27);
1277 switch (bandwidth) {
1278 case 1712000:
1279 *offset /= 582;
1280 break;
1281 case 5000000:
1282 case 6000000:
1283 case 7000000:
1284 case 8000000:
1285 *offset *= (bandwidth / 1000000);
1286 *offset /= 940;
1287 break;
1288 default:
1289 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1290 __func__, bandwidth);
1291 return -EINVAL;
1292 }
1293 return 0;
1294}
1295
c8946c8d
MCC		 1296static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1297 int *offset)
a6dc60ff
KS		 1298{
1299 u8 data[2];
1300
1301 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1302 if (priv->state != STATE_ACTIVE_TC) {
1303 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1304 __func__, priv->state);
1305 return -EINVAL;
1306 }
1307 if (priv->system != SYS_DVBC_ANNEX_A) {
1308 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1309 __func__, priv->system);
1310 return -EINVAL;
1311 }
1312 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1313 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1314 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1315 | (u32)data[1], 13), 16384);
1316 return 0;
1317}
1318
a6f330cb
AO		 1319static int cxd2841er_read_packet_errors_c(
1320 struct cxd2841er_priv *priv, u32 *penum)
1321{
1322 u8 data[3];
1323
1324 *penum = 0;
1325 if (priv->state != STATE_ACTIVE_TC) {
1326 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1327 __func__, priv->state);
1328 return -EINVAL;
1329 }
1330 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1331 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1332 if (data[2] & 0x01)
1333 *penum = ((u32)data[0] << 8) | (u32)data[1];
1334 return 0;
1335}
1336
a6dc60ff
KS		 1337static int cxd2841er_read_packet_errors_t(
1338 struct cxd2841er_priv *priv, u32 *penum)
1339{
1340 u8 data[3];
1341
1342 *penum = 0;
1343 if (priv->state != STATE_ACTIVE_TC) {
1344 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1345 __func__, priv->state);
1346 return -EINVAL;
1347 }
1348 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1349 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1350 if (data[2] & 0x01)
1351 *penum = ((u32)data[0] << 8) | (u32)data[1];
1352 return 0;
1353}
1354
1355static int cxd2841er_read_packet_errors_t2(
1356 struct cxd2841er_priv *priv, u32 *penum)
1357{
1358 u8 data[3];
1359
1360 *penum = 0;
1361 if (priv->state != STATE_ACTIVE_TC) {
1362 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1363 __func__, priv->state);
1364 return -EINVAL;
1365 }
1366 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1367 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1368 if (data[0] & 0x01)
1369 *penum = ((u32)data[1] << 8) | (u32)data[2];
1370 return 0;
1371}
1372
83808c23
AO		 1373static int cxd2841er_read_packet_errors_i(
1374 struct cxd2841er_priv *priv, u32 *penum)
1375{
1376 u8 data[2];
1377
1378 *penum = 0;
1379 if (priv->state != STATE_ACTIVE_TC) {
1380 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1381 __func__, priv->state);
1382 return -EINVAL;
1383 }
1384 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1385 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1386
1387 if (!(data[0] & 0x01))
1388 return 0;
1389
1390 /* Layer A */
1391 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1392 *penum = ((u32)data[0] << 8) | (u32)data[1];
1393
1394 /* Layer B */
1395 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1396 *penum += ((u32)data[0] << 8) | (u32)data[1];
1397
1398 /* Layer C */
1399 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1400 *penum += ((u32)data[0] << 8) | (u32)data[1];
1401
1402 return 0;
1403}
1404
a6f330cb
AO		 1405static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1406 u32 *bit_error, u32 *bit_count)
1407{
1408 u8 data[3];
1409 u32 bit_err, period_exp;
1410
1411 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1412 if (priv->state != STATE_ACTIVE_TC) {
1413 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1414 __func__, priv->state);
1415 return -EINVAL;
1416 }
1417 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1418 cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1419 if (!(data[0] & 0x80)) {
1420 dev_dbg(&priv->i2c->dev,
1421 "%s(): no valid BER data\n", __func__);
1422 return -EINVAL;
1423 }
1424 bit_err = ((u32)(data[0] & 0x3f) << 16) |
1425 ((u32)data[1] << 8) |
1426 (u32)data[2];
1427 cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1428 period_exp = data[0] & 0x1f;
1429
1430 if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1431 dev_dbg(&priv->i2c->dev,
1432 "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
1433 __func__, period_exp, bit_err);
1434 return -EINVAL;
1435 }
1436
1437 dev_dbg(&priv->i2c->dev,
1438 "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1439 __func__, period_exp, bit_err,
1440 ((1 << period_exp) * 204 * 8));
1441
1442 *bit_error = bit_err;
1443 *bit_count = ((1 << period_exp) * 204 * 8);
1444
1445 return 0;
1446}
1447
0854df79
AO		 1448static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1449 u32 *bit_error, u32 *bit_count)
1450{
1451 u8 data[3];
1452 u8 pktnum[2];
1453
1454 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1455 if (priv->state != STATE_ACTIVE_TC) {
1456 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1457 __func__, priv->state);
1458 return -EINVAL;
1459 }
1460
1461 cxd2841er_freeze_regs(priv);
1462 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1463 cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1464 cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
6ccf821c 1465 cxd2841er_unfreeze_regs(priv);
0854df79
AO		 1466
1467 if (!pktnum[0] && !pktnum[1]) {
1468 dev_dbg(&priv->i2c->dev,
1469 "%s(): no valid BER data\n", __func__);
0854df79
AO		 1470 return -EINVAL;
1471 }
1472
1473 *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1474 ((u32)data[1] << 8) | data[2];
1475 *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1476 dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1477 __func__, *bit_error, *bit_count);
1478
0854df79
AO		 1479 return 0;
1480}
1481
4216be14
MCC		 1482static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1483 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1484{
1485 u8 data[11];
a6dc60ff
KS		 1486
1487 /* Set SLV-T Bank : 0xA0 */
1488 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1489 /*
1490 * slave Bank Addr Bit Signal name
1491 * <SLV-T> A0h 35h [0] IFVBER_VALID
1492 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1493 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1494 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1495 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1496 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1497 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1498 */
1499 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1500 if (data[0] & 0x01) {
4216be14
MCC		 1501 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1502 ((u32)(data[2] & 0xFF) << 8) |
1503 (u32)(data[3] & 0xFF);
1504 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1505 ((u32)(data[9] & 0xFF) << 8) |
1506 (u32)(data[10] & 0xFF);
1507 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
a6dc60ff
KS		 1508 dev_dbg(&priv->i2c->dev,
1509 "%s(): invalid bit_error %d, bit_count %d\n",
4216be14 1510 __func__, *bit_error, *bit_count);
f1b26622 1511 return -EINVAL;
a6dc60ff 1512 }
f1b26622 1513 return 0;
a6dc60ff
KS		 1514 }
1515 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
f1b26622 1516 return -EINVAL;
a6dc60ff
KS		 1517}
1518
1519
4216be14
MCC		 1520static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1521 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1522{
1523 u8 data[5];
4216be14 1524 u32 period;
a6dc60ff
KS		 1525
1526 /* Set SLV-T Bank : 0xB2 */
1527 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1528 /*
1529 * slave Bank Addr Bit Signal name
1530 * <SLV-T> B2h 30h [0] IFLBER_VALID
1531 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1532 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1533 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1534 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1535 */
1536 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1537 if (data[0] & 0x01) {
1538 /* Bit error count */
4216be14
MCC		 1539 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1540 ((u32)(data[2] & 0xFF) << 16) |
1541 ((u32)(data[3] & 0xFF) << 8) |
1542 (u32)(data[4] & 0xFF);
a6dc60ff
KS		 1543
1544 /* Set SLV-T Bank : 0xA0 */
1545 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1546 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1547 /* Measurement period */
1548 period = (u32)(1 << (data[0] & 0x0F));
1549 if (period == 0) {
1550 dev_dbg(&priv->i2c->dev,
1551 "%s(): period is 0\n", __func__);
f1b26622 1552 return -EINVAL;
a6dc60ff 1553 }
4216be14 1554 if (*bit_error > (period * 64800)) {
a6dc60ff
KS		 1555 dev_dbg(&priv->i2c->dev,
1556 "%s(): invalid bit_err 0x%x period 0x%x\n",
4216be14 1557 __func__, *bit_error, period);
f1b26622 1558 return -EINVAL;
a6dc60ff 1559 }
4216be14
MCC		 1560 *bit_count = period * 64800;
1561
f1b26622 1562 return 0;
a6dc60ff
KS		 1563 } else {
1564 dev_dbg(&priv->i2c->dev,
1565 "%s(): no data available\n", __func__);
1566 }
f1b26622 1567 return -EINVAL;
a6dc60ff
KS		 1568}
1569
4216be14
MCC		 1570static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1571 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1572{
1573 u8 data[4];
4216be14 1574 u32 period_exp, n_ldpc;
a6dc60ff 1575
a6dc60ff
KS		 1576 if (priv->state != STATE_ACTIVE_TC) {
1577 dev_dbg(&priv->i2c->dev,
1578 "%s(): invalid state %d\n", __func__, priv->state);
1579 return -EINVAL;
1580 }
1581 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1582 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1583 if (!(data[0] & 0x10)) {
1584 dev_dbg(&priv->i2c->dev,
1585 "%s(): no valid BER data\n", __func__);
4216be14 1586 return -EINVAL;
a6dc60ff 1587 }
4216be14
MCC		 1588 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1589 ((u32)data[1] << 16) |
1590 ((u32)data[2] << 8) |
1591 (u32)data[3];
a6dc60ff
KS		 1592 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1593 period_exp = data[0] & 0x0f;
1594 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1595 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1596 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
4216be14 1597 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
a6dc60ff
KS		 1598 dev_dbg(&priv->i2c->dev,
1599 "%s(): invalid BER value\n", __func__);
1600 return -EINVAL;
1601 }
4216be14
MCC		 1602
1603 /*
1604 * FIXME: the right thing would be to return bit_error untouched,
1605 * but, as we don't know the scale returned by the counters, let's
1606 * at least preserver BER = bit_error/bit_count.
1607 */
a6dc60ff 1608 if (period_exp >= 4) {
4216be14
MCC		 1609 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1610 *bit_error *= 3125ULL;
a6dc60ff 1611 } else {
4216be14 1612 *bit_count = (1U << period_exp) * (n_ldpc / 200);
a6f330cb 1613 *bit_error *= 50000ULL;
a6dc60ff 1614 }
a6dc60ff
KS		 1615 return 0;
1616}
1617
4216be14
MCC		 1618static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1619 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1620{
1621 u8 data[2];
4216be14 1622 u32 period;
a6dc60ff 1623
a6dc60ff
KS		 1624 if (priv->state != STATE_ACTIVE_TC) {
1625 dev_dbg(&priv->i2c->dev,
1626 "%s(): invalid state %d\n", __func__, priv->state);
1627 return -EINVAL;
1628 }
1629 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1630 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1631 if (!(data[0] & 0x01)) {
1632 dev_dbg(&priv->i2c->dev,
1633 "%s(): no valid BER data\n", __func__);
1634 return 0;
1635 }
1636 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
4216be14 1637 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
a6dc60ff
KS		 1638 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1639 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
4216be14
MCC		 1640
1641 /*
1642 * FIXME: the right thing would be to return bit_error untouched,
1643 * but, as we don't know the scale returned by the counters, let's
1644 * at least preserver BER = bit_error/bit_count.
1645 */
1646 *bit_count = period / 128;
1647 *bit_error *= 78125ULL;
a6dc60ff
KS		 1648 return 0;
1649}
1650
4a86bc10
AO		 1651static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1652{
1653 /*
1654 * Freeze registers: ensure multiple separate register reads
1655 * are from the same snapshot
1656 */
1657 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1658 return 0;
1659}
1660
1661static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1662{
1663 /*
1664 * un-freeze registers
1665 */
1666 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1667 return 0;
1668}
1669
e05b1872
AO		 1670static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1671 u8 delsys, u32 *snr)
a6dc60ff
KS		 1672{
1673 u8 data[3];
1674 u32 res = 0, value;
1675 int min_index, max_index, index;
1676 static const struct cxd2841er_cnr_data *cn_data;
1677
4a86bc10 1678 cxd2841er_freeze_regs(priv);
a6dc60ff
KS		 1679 /* Set SLV-T Bank : 0xA1 */
1680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1681 /*
1682 * slave Bank Addr Bit Signal name
1683 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1684 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1685 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1686 */
1687 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
6ccf821c
DS		 1688 cxd2841er_unfreeze_regs(priv);
1689
a6dc60ff
KS		 1690 if (data[0] & 0x01) {
1691 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1692 min_index = 0;
1693 if (delsys == SYS_DVBS) {
1694 cn_data = s_cn_data;
1695 max_index = sizeof(s_cn_data) /
1696 sizeof(s_cn_data[0]) - 1;
1697 } else {
1698 cn_data = s2_cn_data;
1699 max_index = sizeof(s2_cn_data) /
1700 sizeof(s2_cn_data[0]) - 1;
1701 }
1702 if (value >= cn_data[min_index].value) {
1703 res = cn_data[min_index].cnr_x1000;
1704 goto done;
1705 }
1706 if (value <= cn_data[max_index].value) {
1707 res = cn_data[max_index].cnr_x1000;
1708 goto done;
1709 }
1710 while ((max_index - min_index) > 1) {
1711 index = (max_index + min_index) / 2;
1712 if (value == cn_data[index].value) {
1713 res = cn_data[index].cnr_x1000;
1714 goto done;
1715 } else if (value > cn_data[index].value)
1716 max_index = index;
1717 else
1718 min_index = index;
1719 if ((max_index - min_index) <= 1) {
1720 if (value == cn_data[max_index].value) {
1721 res = cn_data[max_index].cnr_x1000;
1722 goto done;
1723 } else {
1724 res = cn_data[min_index].cnr_x1000;
1725 goto done;
1726 }
1727 }
1728 }
1729 } else {
1730 dev_dbg(&priv->i2c->dev,
1731 "%s(): no data available\n", __func__);
e05b1872 1732 return -EINVAL;
a6dc60ff
KS		 1733 }
1734done:
e05b1872
AO		 1735 *snr = res;
1736 return 0;
1737}
1738
1739static uint32_t sony_log(uint32_t x)
1740{
1741 return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1742}
1743
1744static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1745{
1746 u32 reg;
1747 u8 data[2];
1748 enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1749
1750 *snr = 0;
1751 if (priv->state != STATE_ACTIVE_TC) {
1752 dev_dbg(&priv->i2c->dev,
1753 "%s(): invalid state %d\n",
1754 __func__, priv->state);
1755 return -EINVAL;
1756 }
1757
4a86bc10 1758 cxd2841er_freeze_regs(priv);
e05b1872
AO		 1759 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1760 cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1761 qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1762 cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
6ccf821c 1763 cxd2841er_unfreeze_regs(priv);
e05b1872
AO		 1764
1765 reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1766 if (reg == 0) {
1767 dev_dbg(&priv->i2c->dev,
1768 "%s(): reg value out of range\n", __func__);
1769 return 0;
1770 }
1771
1772 switch (qam) {
1773 case SONY_DVBC_CONSTELLATION_16QAM:
1774 case SONY_DVBC_CONSTELLATION_64QAM:
1775 case SONY_DVBC_CONSTELLATION_256QAM:
1776 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1777 if (reg < 126)
1778 reg = 126;
1779 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1780 break;
1781 case SONY_DVBC_CONSTELLATION_32QAM:
1782 case SONY_DVBC_CONSTELLATION_128QAM:
1783 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1784 if (reg < 69)
1785 reg = 69;
1786 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1787 break;
1788 default:
1789 return -EINVAL;
1790 }
1791
1792 return 0;
a6dc60ff
KS		 1793}
1794
1795static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1796{
1797 u32 reg;
1798 u8 data[2];
1799
1800 *snr = 0;
1801 if (priv->state != STATE_ACTIVE_TC) {
1802 dev_dbg(&priv->i2c->dev,
1803 "%s(): invalid state %d\n", __func__, priv->state);
1804 return -EINVAL;
1805 }
4a86bc10
AO		 1806
1807 cxd2841er_freeze_regs(priv);
a6dc60ff
KS		 1808 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1809 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
6ccf821c
DS		 1810 cxd2841er_unfreeze_regs(priv);
1811
a6dc60ff
KS		 1812 reg = ((u32)data[0] << 8) | (u32)data[1];
1813 if (reg == 0) {
1814 dev_dbg(&priv->i2c->dev,
1815 "%s(): reg value out of range\n", __func__);
1816 return 0;
1817 }
1818 if (reg > 4996)
1819 reg = 4996;
1820 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1821 return 0;
1822}
1823
c8946c8d 1824static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
a6dc60ff
KS		 1825{
1826 u32 reg;
1827 u8 data[2];
1828
1829 *snr = 0;
1830 if (priv->state != STATE_ACTIVE_TC) {
1831 dev_dbg(&priv->i2c->dev,
1832 "%s(): invalid state %d\n", __func__, priv->state);
1833 return -EINVAL;
1834 }
4a86bc10
AO		 1835
1836 cxd2841er_freeze_regs(priv);
a6dc60ff
KS		 1837 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1838 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
6ccf821c
DS		 1839 cxd2841er_unfreeze_regs(priv);
1840
a6dc60ff
KS		 1841 reg = ((u32)data[0] << 8) | (u32)data[1];
1842 if (reg == 0) {
1843 dev_dbg(&priv->i2c->dev,
1844 "%s(): reg value out of range\n", __func__);
1845 return 0;
1846 }
1847 if (reg > 10876)
1848 reg = 10876;
1849 *snr = 10000 * ((intlog10(reg) -
1850 intlog10(12600 - reg)) >> 24) + 32000;
1851 return 0;
1852}
1853
83808c23
AO		 1854static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1855{
1856 u32 reg;
1857 u8 data[2];
1858
1859 *snr = 0;
1860 if (priv->state != STATE_ACTIVE_TC) {
1861 dev_dbg(&priv->i2c->dev,
1862 "%s(): invalid state %d\n", __func__,
1863 priv->state);
1864 return -EINVAL;
1865 }
1866
4a86bc10 1867 cxd2841er_freeze_regs(priv);
83808c23
AO		 1868 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1869 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
6ccf821c
DS		 1870 cxd2841er_unfreeze_regs(priv);
1871
83808c23
AO		 1872 reg = ((u32)data[0] << 8) | (u32)data[1];
1873 if (reg == 0) {
1874 dev_dbg(&priv->i2c->dev,
1875 "%s(): reg value out of range\n", __func__);
1876 return 0;
1877 }
0854df79 1878 *snr = 10000 * (intlog10(reg) >> 24) - 9031;
83808c23
AO		 1879 return 0;
1880}
1881
d0998ce7
AO		 1882static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1883 u8 delsys)
1884{
1885 u8 data[2];
1886
1887 cxd2841er_write_reg(
1888 priv, I2C_SLVT, 0x00, 0x40);
1889 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1890 dev_dbg(&priv->i2c->dev,
1891 "%s(): AGC value=%u\n",
1892 __func__, (((u16)data[0] & 0x0F) << 8) |
1893 (u16)(data[1] & 0xFF));
1894 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1895}
1896
a6dc60ff
KS		 1897static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1898 u8 delsys)
1899{
1900 u8 data[2];
1901
1902 cxd2841er_write_reg(
1903 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1904 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
c5ea46da
AO		 1905 dev_dbg(&priv->i2c->dev,
1906 "%s(): AGC value=%u\n",
1907 __func__, (((u16)data[0] & 0x0F) << 8) |
1908 (u16)(data[1] & 0xFF));
a6dc60ff
KS		 1909 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1910}
1911
83808c23
AO		 1912static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1913 u8 delsys)
1914{
1915 u8 data[2];
1916
1917 cxd2841er_write_reg(
1918 priv, I2C_SLVT, 0x00, 0x60);
1919 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1920
1921 dev_dbg(&priv->i2c->dev,
1922 "%s(): AGC value=%u\n",
1923 __func__, (((u16)data[0] & 0x0F) << 8) |
1924 (u16)(data[1] & 0xFF));
1925 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1926}
1927
a6dc60ff
KS		 1928static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1929{
1930 u8 data[2];
1931
1932 /* Set SLV-T Bank : 0xA0 */
1933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1934 /*
1935 * slave Bank Addr Bit Signal name
1936 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1937 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1938 */
1939 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1940 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1941}
1942
f1b26622 1943static void cxd2841er_read_ber(struct dvb_frontend *fe)
a6dc60ff
KS		 1944{
1945 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1946 struct cxd2841er_priv *priv = fe->demodulator_priv;
4216be14 1947 u32 ret, bit_error = 0, bit_count = 0;
a6dc60ff
KS		 1948
1949 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
a6dc60ff 1950 switch (p->delivery_system) {
a6f330cb
AO		 1951 case SYS_DVBC_ANNEX_A:
1952 case SYS_DVBC_ANNEX_B:
1953 case SYS_DVBC_ANNEX_C:
1954 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1955 break;
0854df79
AO		 1956 case SYS_ISDBT:
1957 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1958 break;
a6dc60ff 1959 case SYS_DVBS:
4216be14 1960 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
a6dc60ff
KS		 1961 break;
1962 case SYS_DVBS2:
4216be14 1963 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
a6dc60ff
KS		 1964 break;
1965 case SYS_DVBT:
4216be14 1966 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
f1b26622 1967 break;
a6dc60ff 1968 case SYS_DVBT2:
4216be14 1969 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
a6dc60ff 1970 break;
f1b26622
MCC		 1971 default:
1972 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 1973 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
f1b26622
MCC		 1974 return;
1975 }
1976
1977 if (!ret) {
1978 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
a6f330cb 1979 p->post_bit_error.stat[0].uvalue += bit_error;
4216be14 1980 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
a6f330cb 1981 p->post_bit_count.stat[0].uvalue += bit_count;
f1b26622
MCC		 1982 } else {
1983 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 1984 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 1985 }
a6dc60ff
KS		 1986}
1987
5fda1b65 1988static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
a6dc60ff
KS		 1989{
1990 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1991 struct cxd2841er_priv *priv = fe->demodulator_priv;
313a7dfb 1992 s32 strength;
a6dc60ff
KS		 1993
1994 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1995 switch (p->delivery_system) {
1996 case SYS_DVBT:
1997 case SYS_DVBT2:
5fda1b65
MCC		 1998 strength = cxd2841er_read_agc_gain_t_t2(priv,
1999 p->delivery_system);
2000 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2001 /* Formula was empirically determinated @ 410 MHz */
313a7dfb 2002 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
5fda1b65 2003 break; /* Code moved out of the function */
988bd281 2004 case SYS_DVBC_ANNEX_A:
997bdc0c
AO		 2005 case SYS_DVBC_ANNEX_B:
2006 case SYS_DVBC_ANNEX_C:
2007 strength = cxd2841er_read_agc_gain_c(priv,
988bd281 2008 p->delivery_system);
d12b791e
MCC		 2009 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2010 /*
2011 * Formula was empirically determinated via linear regression,
2012 * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2013 * stream modulated with QAM64
2014 */
313a7dfb 2015 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
988bd281 2016 break;
83808c23 2017 case SYS_ISDBT:
313a7dfb
MCC		 2018 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2019 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2020 /*
2021 * Formula was empirically determinated via linear regression,
2022 * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2023 */
2024 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
83808c23 2025 break;
a6dc60ff
KS		 2026 case SYS_DVBS:
2027 case SYS_DVBS2:
5fda1b65
MCC		 2028 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2029 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2030 p->strength.stat[0].uvalue = strength;
a6dc60ff
KS		 2031 break;
2032 default:
f1b26622 2033 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff
KS		 2034 break;
2035 }
a6dc60ff
KS		 2036}
2037
f1b26622 2038static void cxd2841er_read_snr(struct dvb_frontend *fe)
a6dc60ff
KS		 2039{
2040 u32 tmp = 0;
e05b1872 2041 int ret = 0;
a6dc60ff
KS		 2042 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2043 struct cxd2841er_priv *priv = fe->demodulator_priv;
2044
2045 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2046 switch (p->delivery_system) {
e05b1872
AO		 2047 case SYS_DVBC_ANNEX_A:
2048 case SYS_DVBC_ANNEX_B:
2049 case SYS_DVBC_ANNEX_C:
2050 ret = cxd2841er_read_snr_c(priv, &tmp);
2051 break;
a6dc60ff 2052 case SYS_DVBT:
e05b1872 2053 ret = cxd2841er_read_snr_t(priv, &tmp);
a6dc60ff
KS		 2054 break;
2055 case SYS_DVBT2:
e05b1872 2056 ret = cxd2841er_read_snr_t2(priv, &tmp);
a6dc60ff 2057 break;
83808c23 2058 case SYS_ISDBT:
e05b1872 2059 ret = cxd2841er_read_snr_i(priv, &tmp);
83808c23 2060 break;
a6dc60ff
KS		 2061 case SYS_DVBS:
2062 case SYS_DVBS2:
e05b1872 2063 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
a6dc60ff
KS		 2064 break;
2065 default:
2066 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2067 __func__, p->delivery_system);
f1b26622
MCC		 2068 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2069 return;
a6dc60ff 2070 }
f1b26622 2071
0854df79
AO		 2072 dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2073 __func__, (int32_t)tmp);
2074
e05b1872
AO		 2075 if (!ret) {
2076 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2077 p->cnr.stat[0].svalue = tmp;
2078 } else {
2079 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2080 }
a6dc60ff
KS		 2081}
2082
f1b26622 2083static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
a6dc60ff
KS		 2084{
2085 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2086 struct cxd2841er_priv *priv = fe->demodulator_priv;
4a86bc10 2087 u32 ucblocks = 0;
a6dc60ff
KS		 2088
2089 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2090 switch (p->delivery_system) {
a6f330cb
AO		 2091 case SYS_DVBC_ANNEX_A:
2092 case SYS_DVBC_ANNEX_B:
2093 case SYS_DVBC_ANNEX_C:
2094 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2095 break;
a6dc60ff 2096 case SYS_DVBT:
f1b26622 2097 cxd2841er_read_packet_errors_t(priv, &ucblocks);
a6dc60ff
KS		 2098 break;
2099 case SYS_DVBT2:
f1b26622 2100 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
a6dc60ff 2101 break;
83808c23 2102 case SYS_ISDBT:
f1b26622 2103 cxd2841er_read_packet_errors_i(priv, &ucblocks);
83808c23 2104 break;
a6dc60ff 2105 default:
f1b26622
MCC		 2106 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2107 return;
a6dc60ff 2108 }
4a86bc10 2109 dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
f1b26622
MCC		 2110
2111 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2112 p->block_error.stat[0].uvalue = ucblocks;
a6dc60ff
KS		 2113}
2114
2115static int cxd2841er_dvbt2_set_profile(
2116 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2117{
2118 u8 tune_mode;
2119 u8 seq_not2d_time;
2120
2121 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2122 switch (profile) {
2123 case DVBT2_PROFILE_BASE:
2124 tune_mode = 0x01;
6c77161a
AO		 2125 /* Set early unlock time */
2126 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
a6dc60ff
KS		 2127 break;
2128 case DVBT2_PROFILE_LITE:
2129 tune_mode = 0x05;
6c77161a
AO		 2130 /* Set early unlock time */
2131 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
a6dc60ff
KS		 2132 break;
2133 case DVBT2_PROFILE_ANY:
2134 tune_mode = 0x00;
6c77161a
AO		 2135 /* Set early unlock time */
2136 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
a6dc60ff
KS		 2137 break;
2138 default:
2139 return -EINVAL;
2140 }
2141 /* Set SLV-T Bank : 0x2E */
2142 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2143 /* Set profile and tune mode */
2144 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2145 /* Set SLV-T Bank : 0x2B */
2146 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2147 /* Set early unlock detection time */
2148 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2149 return 0;
2150}
2151
2152static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2153 u8 is_auto, u8 plp_id)
2154{
2155 if (is_auto) {
2156 dev_dbg(&priv->i2c->dev,
2157 "%s() using auto PLP selection\n", __func__);
2158 } else {
2159 dev_dbg(&priv->i2c->dev,
2160 "%s() using manual PLP selection, ID %d\n",
2161 __func__, plp_id);
2162 }
2163 /* Set SLV-T Bank : 0x23 */
2164 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2165 if (!is_auto) {
2166 /* Manual PLP selection mode. Set the data PLP Id. */
2167 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2168 }
2169 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2170 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2171 return 0;
2172}
2173
2174static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2175 u32 bandwidth)
2176{
4b866c4e 2177 u32 iffreq, ifhz;
6c77161a
AO		 2178 u8 data[MAX_WRITE_REGSIZE];
2179
2180 const uint8_t nominalRate8bw[3][5] = {
2181 /* TRCG Nominal Rate [37:0] */
2182 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2183 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2184 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2185 };
2186
2187 const uint8_t nominalRate7bw[3][5] = {
2188 /* TRCG Nominal Rate [37:0] */
2189 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2190 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2191 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2192 };
2193
2194 const uint8_t nominalRate6bw[3][5] = {
2195 /* TRCG Nominal Rate [37:0] */
2196 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2197 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2198 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2199 };
2200
2201 const uint8_t nominalRate5bw[3][5] = {
2202 /* TRCG Nominal Rate [37:0] */
2203 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2204 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2205 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2206 };
2207
2208 const uint8_t nominalRate17bw[3][5] = {
2209 /* TRCG Nominal Rate [37:0] */
2210 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2211 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2212 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
2213 };
2214
2215 const uint8_t itbCoef8bw[3][14] = {
2216 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2217 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2218 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2219 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2220 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2221 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2222 };
2223
2224 const uint8_t itbCoef7bw[3][14] = {
2225 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2226 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2227 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2228 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2229 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2230 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2231 };
2232
2233 const uint8_t itbCoef6bw[3][14] = {
2234 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2235 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2236 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2237 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2238 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2239 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2240 };
2241
2242 const uint8_t itbCoef5bw[3][14] = {
2243 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2244 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2245 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2246 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2247 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2248 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2249 };
2250
2251 const uint8_t itbCoef17bw[3][14] = {
2252 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2253 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2254 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2255 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
2256 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2257 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
2258 };
2259
2260 /* Set SLV-T Bank : 0x20 */
2261 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
a6dc60ff 2262
a6dc60ff
KS		 2263 switch (bandwidth) {
2264 case 8000000:
6c77161a
AO		 2265 /* <Timing Recovery setting> */
2266 cxd2841er_write_regs(priv, I2C_SLVT,
2267 0x9F, nominalRate8bw[priv->xtal], 5);
2268
2269 /* Set SLV-T Bank : 0x27 */
2270 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2271 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2272 0x7a, 0x00, 0x0f);
2273
2274 /* Set SLV-T Bank : 0x10 */
2275 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2276
2277 /* Group delay equaliser settings for
2278 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2279 */
7afe510a
DS		 2280 if (priv->flags & CXD2841ER_ASCOT)
2281 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2282 0xA6, itbCoef8bw[priv->xtal], 14);
2283 /* <IF freq setting> */
4b866c4e
DS		 2284 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2285 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2286 data[0] = (u8) ((iffreq >> 16) & 0xff);
2287 data[1] = (u8)((iffreq >> 8) & 0xff);
2288 data[2] = (u8)(iffreq & 0xff);
2289 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2290 /* System bandwidth setting */
2291 cxd2841er_set_reg_bits(
2292 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
a6dc60ff
KS		 2293 break;
2294 case 7000000:
6c77161a
AO		 2295 /* <Timing Recovery setting> */
2296 cxd2841er_write_regs(priv, I2C_SLVT,
2297 0x9F, nominalRate7bw[priv->xtal], 5);
2298
2299 /* Set SLV-T Bank : 0x27 */
2300 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2301 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2302 0x7a, 0x00, 0x0f);
2303
2304 /* Set SLV-T Bank : 0x10 */
2305 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2306
2307 /* Group delay equaliser settings for
2308 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2309 */
7afe510a
DS		 2310 if (priv->flags & CXD2841ER_ASCOT)
2311 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2312 0xA6, itbCoef7bw[priv->xtal], 14);
2313 /* <IF freq setting> */
4b866c4e
DS		 2314 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2315 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2316 data[0] = (u8) ((iffreq >> 16) & 0xff);
2317 data[1] = (u8)((iffreq >> 8) & 0xff);
2318 data[2] = (u8)(iffreq & 0xff);
2319 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2320 /* System bandwidth setting */
2321 cxd2841er_set_reg_bits(
2322 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
a6dc60ff
KS		 2323 break;
2324 case 6000000:
6c77161a
AO		 2325 /* <Timing Recovery setting> */
2326 cxd2841er_write_regs(priv, I2C_SLVT,
2327 0x9F, nominalRate6bw[priv->xtal], 5);
2328
2329 /* Set SLV-T Bank : 0x27 */
2330 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2331 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2332 0x7a, 0x00, 0x0f);
2333
2334 /* Set SLV-T Bank : 0x10 */
2335 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2336
2337 /* Group delay equaliser settings for
2338 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2339 */
7afe510a
DS		 2340 if (priv->flags & CXD2841ER_ASCOT)
2341 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2342 0xA6, itbCoef6bw[priv->xtal], 14);
2343 /* <IF freq setting> */
4b866c4e
DS		 2344 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2345 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2346 data[0] = (u8) ((iffreq >> 16) & 0xff);
2347 data[1] = (u8)((iffreq >> 8) & 0xff);
2348 data[2] = (u8)(iffreq & 0xff);
2349 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2350 /* System bandwidth setting */
2351 cxd2841er_set_reg_bits(
2352 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
a6dc60ff
KS		 2353 break;
2354 case 5000000:
6c77161a
AO		 2355 /* <Timing Recovery setting> */
2356 cxd2841er_write_regs(priv, I2C_SLVT,
2357 0x9F, nominalRate5bw[priv->xtal], 5);
2358
2359 /* Set SLV-T Bank : 0x27 */
2360 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2361 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2362 0x7a, 0x00, 0x0f);
2363
2364 /* Set SLV-T Bank : 0x10 */
2365 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2366
2367 /* Group delay equaliser settings for
2368 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2369 */
7afe510a
DS		 2370 if (priv->flags & CXD2841ER_ASCOT)
2371 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2372 0xA6, itbCoef5bw[priv->xtal], 14);
2373 /* <IF freq setting> */
4b866c4e
DS		 2374 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2375 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2376 data[0] = (u8) ((iffreq >> 16) & 0xff);
2377 data[1] = (u8)((iffreq >> 8) & 0xff);
2378 data[2] = (u8)(iffreq & 0xff);
2379 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2380 /* System bandwidth setting */
2381 cxd2841er_set_reg_bits(
2382 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
a6dc60ff
KS		 2383 break;
2384 case 1712000:
6c77161a
AO		 2385 /* <Timing Recovery setting> */
2386 cxd2841er_write_regs(priv, I2C_SLVT,
2387 0x9F, nominalRate17bw[priv->xtal], 5);
2388
2389 /* Set SLV-T Bank : 0x27 */
2390 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2391 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2392 0x7a, 0x03, 0x0f);
2393
2394 /* Set SLV-T Bank : 0x10 */
2395 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2396
2397 /* Group delay equaliser settings for
2398 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2399 */
7afe510a
DS		 2400 if (priv->flags & CXD2841ER_ASCOT)
2401 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2402 0xA6, itbCoef17bw[priv->xtal], 14);
2403 /* <IF freq setting> */
4b866c4e
DS		 2404 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2405 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2406 data[0] = (u8) ((iffreq >> 16) & 0xff);
2407 data[1] = (u8)((iffreq >> 8) & 0xff);
2408 data[2] = (u8)(iffreq & 0xff);
2409 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2410 /* System bandwidth setting */
2411 cxd2841er_set_reg_bits(
2412 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
a6dc60ff
KS		 2413 break;
2414 default:
2415 return -EINVAL;
2416 }
a6dc60ff
KS		 2417 return 0;
2418}
2419
2420static int cxd2841er_sleep_tc_to_active_t_band(
2421 struct cxd2841er_priv *priv, u32 bandwidth)
2422{
83808c23 2423 u8 data[MAX_WRITE_REGSIZE];
4b866c4e 2424 u32 iffreq, ifhz;
83808c23
AO		 2425 u8 nominalRate8bw[3][5] = {
2426 /* TRCG Nominal Rate [37:0] */
2427 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2428 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2429 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2430 };
2431 u8 nominalRate7bw[3][5] = {
2432 /* TRCG Nominal Rate [37:0] */
2433 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2434 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2435 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2436 };
2437 u8 nominalRate6bw[3][5] = {
2438 /* TRCG Nominal Rate [37:0] */
2439 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2440 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2441 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2442 };
2443 u8 nominalRate5bw[3][5] = {
2444 /* TRCG Nominal Rate [37:0] */
2445 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2446 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2447 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2448 };
a6dc60ff 2449
83808c23
AO		 2450 u8 itbCoef8bw[3][14] = {
2451 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2452 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2453 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2454 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2455 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2456 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2457 };
2458 u8 itbCoef7bw[3][14] = {
2459 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2460 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2461 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2462 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2463 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2464 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2465 };
2466 u8 itbCoef6bw[3][14] = {
2467 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2468 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2469 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2470 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2471 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2472 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2473 };
2474 u8 itbCoef5bw[3][14] = {
2475 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2476 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2477 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2478 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2479 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2480 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2481 };
2482
2483 /* Set SLV-T Bank : 0x13 */
a6dc60ff
KS		 2484 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2485 /* Echo performance optimization setting */
83808c23
AO		 2486 data[0] = 0x01;
2487 data[1] = 0x14;
2488 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2489
2490 /* Set SLV-T Bank : 0x10 */
a6dc60ff
KS		 2491 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2492
2493 switch (bandwidth) {
2494 case 8000000:
83808c23
AO		 2495 /* <Timing Recovery setting> */
2496 cxd2841er_write_regs(priv, I2C_SLVT,
2497 0x9F, nominalRate8bw[priv->xtal], 5);
2498 /* Group delay equaliser settings for
2499 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2500 */
7afe510a
DS		 2501 if (priv->flags & CXD2841ER_ASCOT)
2502 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2503 0xA6, itbCoef8bw[priv->xtal], 14);
2504 /* <IF freq setting> */
4b866c4e
DS		 2505 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2506 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2507 data[0] = (u8) ((iffreq >> 16) & 0xff);
2508 data[1] = (u8)((iffreq >> 8) & 0xff);
2509 data[2] = (u8)(iffreq & 0xff);
2510 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2511 /* System bandwidth setting */
2512 cxd2841er_set_reg_bits(
2513 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2514
2515 /* Demod core latency setting */
2516 if (priv->xtal == SONY_XTAL_24000) {
2517 data[0] = 0x15;
2518 data[1] = 0x28;
2519 } else {
2520 data[0] = 0x01;
2521 data[1] = 0xE0;
2522 }
2523 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2524
2525 /* Notch filter setting */
2526 data[0] = 0x01;
2527 data[1] = 0x02;
2528 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2529 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2530 break;
2531 case 7000000:
83808c23
AO		 2532 /* <Timing Recovery setting> */
2533 cxd2841er_write_regs(priv, I2C_SLVT,
2534 0x9F, nominalRate7bw[priv->xtal], 5);
2535 /* Group delay equaliser settings for
2536 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2537 */
7afe510a
DS		 2538 if (priv->flags & CXD2841ER_ASCOT)
2539 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2540 0xA6, itbCoef7bw[priv->xtal], 14);
2541 /* <IF freq setting> */
4b866c4e
DS		 2542 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2543 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2544 data[0] = (u8) ((iffreq >> 16) & 0xff);
2545 data[1] = (u8)((iffreq >> 8) & 0xff);
2546 data[2] = (u8)(iffreq & 0xff);
2547 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2548 /* System bandwidth setting */
2549 cxd2841er_set_reg_bits(
2550 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2551
2552 /* Demod core latency setting */
2553 if (priv->xtal == SONY_XTAL_24000) {
2554 data[0] = 0x1F;
2555 data[1] = 0xF8;
2556 } else {
2557 data[0] = 0x12;
2558 data[1] = 0xF8;
2559 }
2560 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2561
2562 /* Notch filter setting */
2563 data[0] = 0x00;
2564 data[1] = 0x03;
2565 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2566 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2567 break;
2568 case 6000000:
83808c23
AO		 2569 /* <Timing Recovery setting> */
2570 cxd2841er_write_regs(priv, I2C_SLVT,
2571 0x9F, nominalRate6bw[priv->xtal], 5);
2572 /* Group delay equaliser settings for
2573 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2574 */
7afe510a
DS		 2575 if (priv->flags & CXD2841ER_ASCOT)
2576 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2577 0xA6, itbCoef6bw[priv->xtal], 14);
2578 /* <IF freq setting> */
4b866c4e
DS		 2579 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2580 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2581 data[0] = (u8) ((iffreq >> 16) & 0xff);
2582 data[1] = (u8)((iffreq >> 8) & 0xff);
2583 data[2] = (u8)(iffreq & 0xff);
2584 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2585 /* System bandwidth setting */
2586 cxd2841er_set_reg_bits(
2587 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2588
2589 /* Demod core latency setting */
2590 if (priv->xtal == SONY_XTAL_24000) {
2591 data[0] = 0x25;
2592 data[1] = 0x4C;
2593 } else {
2594 data[0] = 0x1F;
2595 data[1] = 0xDC;
2596 }
2597 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2598
2599 /* Notch filter setting */
2600 data[0] = 0x00;
2601 data[1] = 0x03;
2602 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2603 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2604 break;
2605 case 5000000:
83808c23
AO		 2606 /* <Timing Recovery setting> */
2607 cxd2841er_write_regs(priv, I2C_SLVT,
2608 0x9F, nominalRate5bw[priv->xtal], 5);
2609 /* Group delay equaliser settings for
2610 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2611 */
7afe510a
DS		 2612 if (priv->flags & CXD2841ER_ASCOT)
2613 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2614 0xA6, itbCoef5bw[priv->xtal], 14);
2615 /* <IF freq setting> */
4b866c4e
DS		 2616 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2617 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2618 data[0] = (u8) ((iffreq >> 16) & 0xff);
2619 data[1] = (u8)((iffreq >> 8) & 0xff);
2620 data[2] = (u8)(iffreq & 0xff);
2621 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2622 /* System bandwidth setting */
2623 cxd2841er_set_reg_bits(
2624 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2625
2626 /* Demod core latency setting */
2627 if (priv->xtal == SONY_XTAL_24000) {
2628 data[0] = 0x2C;
2629 data[1] = 0xC2;
2630 } else {
2631 data[0] = 0x26;
2632 data[1] = 0x3C;
2633 }
2634 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2635
2636 /* Notch filter setting */
2637 data[0] = 0x00;
2638 data[1] = 0x03;
2639 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2640 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2641 break;
2642 }
2643
2644 return 0;
2645}
2646
2647static int cxd2841er_sleep_tc_to_active_i_band(
2648 struct cxd2841er_priv *priv, u32 bandwidth)
2649{
4b866c4e 2650 u32 iffreq, ifhz;
83808c23
AO		 2651 u8 data[3];
2652
2653 /* TRCG Nominal Rate */
2654 u8 nominalRate8bw[3][5] = {
2655 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2656 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2657 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2658 };
2659
2660 u8 nominalRate7bw[3][5] = {
2661 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2662 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2663 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2664 };
2665
2666 u8 nominalRate6bw[3][5] = {
2667 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2668 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2669 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2670 };
2671
2672 u8 itbCoef8bw[3][14] = {
2673 {0x00}, /* 20.5MHz XTal */
2674 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2675 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2676 {0x0}, /* 41MHz XTal */
2677 };
2678
2679 u8 itbCoef7bw[3][14] = {
2680 {0x00}, /* 20.5MHz XTal */
2681 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2682 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2683 {0x00}, /* 41MHz XTal */
2684 };
2685
2686 u8 itbCoef6bw[3][14] = {
2687 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2688 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2689 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2690 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2691 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2692 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2693 };
2694
2695 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2696 /* Set SLV-T Bank : 0x10 */
2697 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2698
2699 /* 20.5/41MHz Xtal support is not available
2700 * on ISDB-T 7MHzBW and 8MHzBW
2701 */
2702 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2703 dev_err(&priv->i2c->dev,
2704 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2705 __func__, bandwidth);
2706 return -EINVAL;
2707 }
2708
2709 switch (bandwidth) {
2710 case 8000000:
2711 /* TRCG Nominal Rate */
2712 cxd2841er_write_regs(priv, I2C_SLVT,
2713 0x9F, nominalRate8bw[priv->xtal], 5);
2714 /* Group delay equaliser settings for ASCOT tuners optimized */
7afe510a
DS		 2715 if (priv->flags & CXD2841ER_ASCOT)
2716 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2717 0xA6, itbCoef8bw[priv->xtal], 14);
2718
2719 /* IF freq setting */
4b866c4e
DS		 2720 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2721 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2722 data[0] = (u8) ((iffreq >> 16) & 0xff);
2723 data[1] = (u8)((iffreq >> 8) & 0xff);
2724 data[2] = (u8)(iffreq & 0xff);
2725 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2726
2727 /* System bandwidth setting */
2728 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2729
2730 /* Demod core latency setting */
2731 data[0] = 0x13;
2732 data[1] = 0xFC;
2733 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2734
2735 /* Acquisition optimization setting */
2736 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2737 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2738 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2739 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2740 break;
2741 case 7000000:
2742 /* TRCG Nominal Rate */
2743 cxd2841er_write_regs(priv, I2C_SLVT,
2744 0x9F, nominalRate7bw[priv->xtal], 5);
2745 /* Group delay equaliser settings for ASCOT tuners optimized */
7afe510a
DS		 2746 if (priv->flags & CXD2841ER_ASCOT)
2747 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2748 0xA6, itbCoef7bw[priv->xtal], 14);
2749
2750 /* IF freq setting */
4b866c4e
DS		 2751 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2752 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2753 data[0] = (u8) ((iffreq >> 16) & 0xff);
2754 data[1] = (u8)((iffreq >> 8) & 0xff);
2755 data[2] = (u8)(iffreq & 0xff);
2756 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2757
2758 /* System bandwidth setting */
2759 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2760
2761 /* Demod core latency setting */
2762 data[0] = 0x1A;
2763 data[1] = 0xFA;
2764 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2765
2766 /* Acquisition optimization setting */
2767 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2768 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2769 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2770 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2771 break;
2772 case 6000000:
2773 /* TRCG Nominal Rate */
2774 cxd2841er_write_regs(priv, I2C_SLVT,
2775 0x9F, nominalRate6bw[priv->xtal], 5);
2776 /* Group delay equaliser settings for ASCOT tuners optimized */
7afe510a
DS		 2777 if (priv->flags & CXD2841ER_ASCOT)
2778 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2779 0xA6, itbCoef6bw[priv->xtal], 14);
2780
2781 /* IF freq setting */
4b866c4e
DS		 2782 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2783 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2784 data[0] = (u8) ((iffreq >> 16) & 0xff);
2785 data[1] = (u8)((iffreq >> 8) & 0xff);
2786 data[2] = (u8)(iffreq & 0xff);
2787 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2788
2789 /* System bandwidth setting */
2790 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2791
2792 /* Demod core latency setting */
2793 if (priv->xtal == SONY_XTAL_24000) {
2794 data[0] = 0x1F;
2795 data[1] = 0x79;
2796 } else {
2797 data[0] = 0x1A;
2798 data[1] = 0xE2;
2799 }
2800 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2801
2802 /* Acquisition optimization setting */
2803 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2804 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2805 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2806 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
a6dc60ff
KS		 2807 break;
2808 default:
2809 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
83808c23 2810 __func__, bandwidth);
a6dc60ff
KS		 2811 return -EINVAL;
2812 }
a6dc60ff
KS		 2813 return 0;
2814}
2815
2816static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2817 u32 bandwidth)
2818{
2819 u8 bw7_8mhz_b10_a6[] = {
2820 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2821 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2822 u8 bw6mhz_b10_a6[] = {
2823 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2824 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2825 u8 b10_b6[3];
4b866c4e 2826 u32 iffreq, ifhz;
a6dc60ff 2827
af4cc462
AO		 2828 if (bandwidth != 6000000 &&
2829 bandwidth != 7000000 &&
2830 bandwidth != 8000000) {
2831 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2832 __func__, bandwidth);
2833 bandwidth = 8000000;
2834 }
2835
3f3b48a0 2836 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
a6dc60ff
KS		 2837 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2838 switch (bandwidth) {
2839 case 8000000:
2840 case 7000000:
7afe510a
DS		 2841 if (priv->flags & CXD2841ER_ASCOT)
2842 cxd2841er_write_regs(
2843 priv, I2C_SLVT, 0xa6,
2844 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
4b866c4e
DS		 2845 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2846 iffreq = cxd2841er_calc_iffreq(ifhz);
a6dc60ff
KS		 2847 break;
2848 case 6000000:
7afe510a
DS		 2849 if (priv->flags & CXD2841ER_ASCOT)
2850 cxd2841er_write_regs(
2851 priv, I2C_SLVT, 0xa6,
2852 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
4b866c4e
DS		 2853 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2854 iffreq = cxd2841er_calc_iffreq(ifhz);
a6dc60ff
KS		 2855 break;
2856 default:
3f3b48a0 2857 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
a6dc60ff
KS		 2858 __func__, bandwidth);
2859 return -EINVAL;
2860 }
2861 /* <IF freq setting> */
2862 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2863 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2864 b10_b6[2] = (u8)(iffreq & 0xff);
2865 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2866 /* Set SLV-T Bank : 0x11 */
2867 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2868 switch (bandwidth) {
2869 case 8000000:
2870 case 7000000:
2871 cxd2841er_set_reg_bits(
2872 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2873 break;
2874 case 6000000:
2875 cxd2841er_set_reg_bits(
2876 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2877 break;
2878 }
2879 /* Set SLV-T Bank : 0x40 */
2880 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2881 switch (bandwidth) {
2882 case 8000000:
2883 cxd2841er_set_reg_bits(
2884 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2885 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2886 break;
2887 case 7000000:
2888 cxd2841er_set_reg_bits(
2889 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2890 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2891 break;
2892 case 6000000:
2893 cxd2841er_set_reg_bits(
2894 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2895 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2896 break;
2897 }
2898 return 0;
2899}
2900
2901static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2902 u32 bandwidth)
2903{
2904 u8 data[2] = { 0x09, 0x54 };
83808c23 2905 u8 data24m[3] = {0xDC, 0x6C, 0x00};
a6dc60ff
KS		 2906
2907 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2908 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2909 /* Set SLV-X Bank : 0x00 */
2910 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2911 /* Set demod mode */
2912 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2913 /* Set SLV-T Bank : 0x00 */
2914 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2915 /* Enable demod clock */
2916 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2917 /* Disable RF level monitor */
2918 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2919 /* Enable ADC clock */
2920 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2921 /* Enable ADC 1 */
2922 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
83808c23
AO		 2923 /* Enable ADC 2 & 3 */
2924 if (priv->xtal == SONY_XTAL_41000) {
2925 data[0] = 0x0A;
2926 data[1] = 0xD4;
2927 }
a6dc60ff
KS		 2928 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2929 /* Enable ADC 4 */
2930 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2931 /* Set SLV-T Bank : 0x10 */
2932 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2933 /* IFAGC gain settings */
2934 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2935 /* Set SLV-T Bank : 0x11 */
2936 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2937 /* BBAGC TARGET level setting */
2938 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2939 /* Set SLV-T Bank : 0x10 */
2940 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
7afe510a
DS		 2941 /* ASCOT setting */
2942 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2943 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
a6dc60ff
KS		 2944 /* Set SLV-T Bank : 0x18 */
2945 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2946 /* Pre-RS BER moniter setting */
2947 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2948 /* FEC Auto Recovery setting */
2949 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2951 /* Set SLV-T Bank : 0x00 */
2952 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2953 /* TSIF setting */
2954 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2955 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
83808c23
AO		 2956
2957 if (priv->xtal == SONY_XTAL_24000) {
2958 /* Set SLV-T Bank : 0x10 */
2959 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2960 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2961 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2962 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2963 }
2964
a6dc60ff
KS		 2965 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2966 /* Set SLV-T Bank : 0x00 */
2967 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2968 /* Disable HiZ Setting 1 */
2969 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2970 /* Disable HiZ Setting 2 */
2971 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2972 priv->state = STATE_ACTIVE_TC;
2973 return 0;
2974}
2975
2976static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2977 u32 bandwidth)
2978{
6c77161a 2979 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff
KS		 2980
2981 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2982 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2983 /* Set SLV-X Bank : 0x00 */
2984 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2985 /* Set demod mode */
2986 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2987 /* Set SLV-T Bank : 0x00 */
2988 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2989 /* Enable demod clock */
2990 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2991 /* Disable RF level monitor */
6c77161a 2992 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
a6dc60ff
KS		 2993 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2994 /* Enable ADC clock */
2995 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2996 /* Enable ADC 1 */
2997 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
6c77161a
AO		 2998
2999 if (priv->xtal == SONY_XTAL_41000) {
3000 data[0] = 0x0A;
3001 data[1] = 0xD4;
3002 } else {
3003 data[0] = 0x09;
3004 data[1] = 0x54;
3005 }
3006
a6dc60ff
KS		 3007 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3008 /* Enable ADC 4 */
3009 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3010 /* Set SLV-T Bank : 0x10 */
3011 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3012 /* IFAGC gain settings */
3013 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3014 /* Set SLV-T Bank : 0x11 */
3015 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3016 /* BBAGC TARGET level setting */
3017 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3018 /* Set SLV-T Bank : 0x10 */
3019 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
7afe510a
DS		 3020 /* ASCOT setting */
3021 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3022 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
a6dc60ff
KS		 3023 /* Set SLV-T Bank : 0x20 */
3024 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3025 /* Acquisition optimization setting */
3026 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3027 /* Set SLV-T Bank : 0x2b */
3028 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3029 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
6c77161a
AO		 3030 /* Set SLV-T Bank : 0x23 */
3031 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3032 /* L1 Control setting */
3033 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
a6dc60ff
KS		 3034 /* Set SLV-T Bank : 0x00 */
3035 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3036 /* TSIF setting */
3037 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3038 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3039 /* DVB-T2 initial setting */
3040 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3041 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3042 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3043 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3044 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3045 /* Set SLV-T Bank : 0x2a */
3046 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3047 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3048 /* Set SLV-T Bank : 0x2b */
3049 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3050 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3051
6c77161a
AO		 3052 /* 24MHz Xtal setting */
3053 if (priv->xtal == SONY_XTAL_24000) {
3054 /* Set SLV-T Bank : 0x11 */
3055 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3056 data[0] = 0xEB;
3057 data[1] = 0x03;
3058 data[2] = 0x3B;
3059 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3060
3061 /* Set SLV-T Bank : 0x20 */
3062 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3063 data[0] = 0x5E;
3064 data[1] = 0x5E;
3065 data[2] = 0x47;
3066 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3067
3068 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3069
3070 data[0] = 0x3F;
3071 data[1] = 0xFF;
3072 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3073
3074 /* Set SLV-T Bank : 0x24 */
3075 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3076 data[0] = 0x0B;
3077 data[1] = 0x72;
3078 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3079
3080 data[0] = 0x93;
3081 data[1] = 0xF3;
3082 data[2] = 0x00;
3083 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3084
3085 data[0] = 0x05;
3086 data[1] = 0xB8;
3087 data[2] = 0xD8;
3088 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3089
3090 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3091
3092 /* Set SLV-T Bank : 0x25 */
3093 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3094 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3095
3096 /* Set SLV-T Bank : 0x27 */
3097 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3098 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3099
3100 /* Set SLV-T Bank : 0x2B */
3101 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3102 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3103 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3104
3105 /* Set SLV-T Bank : 0x2D */
3106 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3107 data[0] = 0x89;
3108 data[1] = 0x89;
3109 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3110
3111 /* Set SLV-T Bank : 0x5E */
3112 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3113 data[0] = 0x24;
3114 data[1] = 0x95;
3115 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3116 }
3117
a6dc60ff
KS		 3118 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3119
3120 /* Set SLV-T Bank : 0x00 */
3121 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3122 /* Disable HiZ Setting 1 */
3123 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3124 /* Disable HiZ Setting 2 */
3125 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3126 priv->state = STATE_ACTIVE_TC;
3127 return 0;
3128}
3129
83808c23
AO		 3130/* ISDB-Tb part */
3131static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3132 u32 bandwidth)
3133{
3134 u8 data[2] = { 0x09, 0x54 };
3135 u8 data24m[2] = {0x60, 0x00};
3136 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3137
3138 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3139 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3140 /* Set SLV-X Bank : 0x00 */
3141 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3142 /* Set demod mode */
3143 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3144 /* Set SLV-T Bank : 0x00 */
3145 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3146 /* Enable demod clock */
3147 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3148 /* Enable RF level monitor */
3149 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3150 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3151 /* Enable ADC clock */
3152 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3153 /* Enable ADC 1 */
3154 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3155 /* xtal freq 20.5MHz or 24M */
3156 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3157 /* Enable ADC 4 */
3158 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
7afe510a
DS		 3159 /* ASCOT setting */
3160 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3161 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
83808c23
AO		 3162 /* FEC Auto Recovery setting */
3163 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3164 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3165 /* ISDB-T initial setting */
3166 /* Set SLV-T Bank : 0x00 */
3167 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3168 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3169 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3170 /* Set SLV-T Bank : 0x10 */
3171 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3172 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3173 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3174 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3175 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3176 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3177 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3178 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3179 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3180 /* Set SLV-T Bank : 0x15 */
3181 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3182 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3183 /* Set SLV-T Bank : 0x1E */
3184 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3185 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3186 /* Set SLV-T Bank : 0x63 */
3187 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3188 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3189
3190 /* for xtal 24MHz */
3191 /* Set SLV-T Bank : 0x10 */
3192 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3193 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3194 /* Set SLV-T Bank : 0x60 */
3195 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3196 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3197
3198 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3199 /* Set SLV-T Bank : 0x00 */
3200 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3201 /* Disable HiZ Setting 1 */
3202 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3203 /* Disable HiZ Setting 2 */
3204 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3205 priv->state = STATE_ACTIVE_TC;
3206 return 0;
3207}
3208
a6dc60ff
KS		 3209static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3210 u32 bandwidth)
3211{
3212 u8 data[2] = { 0x09, 0x54 };
3213
3214 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3215 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3216 /* Set SLV-X Bank : 0x00 */
3217 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3218 /* Set demod mode */
3219 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3220 /* Set SLV-T Bank : 0x00 */
3221 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3222 /* Enable demod clock */
3223 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3224 /* Disable RF level monitor */
4a86bc10 3225 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
a6dc60ff
KS		 3226 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3227 /* Enable ADC clock */
3228 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3229 /* Enable ADC 1 */
3230 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3231 /* xtal freq 20.5MHz */
3232 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3233 /* Enable ADC 4 */
3234 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3235 /* Set SLV-T Bank : 0x10 */
3236 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3237 /* IFAGC gain settings */
3238 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3239 /* Set SLV-T Bank : 0x11 */
3240 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3241 /* BBAGC TARGET level setting */
3242 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3243 /* Set SLV-T Bank : 0x10 */
3244 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
7afe510a
DS		 3245 /* ASCOT setting */
3246 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3247 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
a6dc60ff
KS		 3248 /* Set SLV-T Bank : 0x40 */
3249 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3250 /* Demod setting */
3251 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3252 /* Set SLV-T Bank : 0x00 */
3253 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3254 /* TSIF setting */
3255 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3256 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3257
3f3b48a0 3258 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
a6dc60ff
KS		 3259 /* Set SLV-T Bank : 0x00 */
3260 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3261 /* Disable HiZ Setting 1 */
3262 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3263 /* Disable HiZ Setting 2 */
3264 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3265 priv->state = STATE_ACTIVE_TC;
3266 return 0;
3267}
3268
7e3e68bc
MCC		 3269static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3270 struct dtv_frontend_properties *p)
a6dc60ff
KS		 3271{
3272 enum fe_status status = 0;
a6dc60ff 3273 struct cxd2841er_priv *priv = fe->demodulator_priv;
a6dc60ff
KS		 3274
3275 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3276 if (priv->state == STATE_ACTIVE_S)
3277 cxd2841er_read_status_s(fe, &status);
3278 else if (priv->state == STATE_ACTIVE_TC)
3279 cxd2841er_read_status_tc(fe, &status);
3280
5fda1b65 3281 cxd2841er_read_signal_strength(fe);
d0e20e13 3282
a6dc60ff 3283 if (status & FE_HAS_LOCK) {
f1b26622
MCC		 3284 cxd2841er_read_snr(fe);
3285 cxd2841er_read_ucblocks(fe);
d0e20e13 3286
f1b26622 3287 cxd2841er_read_ber(fe);
a6dc60ff 3288 } else {
a6dc60ff 3289 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 3290 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 3291 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 3292 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff
KS		 3293 }
3294 return 0;
3295}
3296
3297static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3298{
3299 int ret = 0, i, timeout, carr_offset;
3300 enum fe_status status;
3301 struct cxd2841er_priv *priv = fe->demodulator_priv;
3302 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3303 u32 symbol_rate = p->symbol_rate/1000;
3304
83808c23 3305 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
a6dc60ff
KS		 3306 __func__,
3307 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
83808c23 3308 p->frequency, symbol_rate, priv->xtal);
763f857e
DS		 3309
3310 if (priv->flags & CXD2841ER_EARLY_TUNE)
3311 cxd2841er_tuner_set(fe);
3312
a6dc60ff
KS		 3313 switch (priv->state) {
3314 case STATE_SLEEP_S:
3315 ret = cxd2841er_sleep_s_to_active_s(
3316 priv, p->delivery_system, symbol_rate);
3317 break;
3318 case STATE_ACTIVE_S:
3319 ret = cxd2841er_retune_active(priv, p);
3320 break;
3321 default:
3322 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3323 __func__, priv->state);
3324 ret = -EINVAL;
3325 goto done;
3326 }
3327 if (ret) {
3328 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3329 goto done;
3330 }
c7518d13 3331
763f857e
DS		 3332 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3333 cxd2841er_tuner_set(fe);
c7518d13 3334
a6dc60ff
KS		 3335 cxd2841er_tune_done(priv);
3336 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3337 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3338 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3339 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3340 cxd2841er_read_status_s(fe, &status);
3341 if (status & FE_HAS_LOCK)
3342 break;
3343 }
3344 if (status & FE_HAS_LOCK) {
3345 if (cxd2841er_get_carrier_offset_s_s2(
3346 priv, &carr_offset)) {
3347 ret = -EINVAL;
3348 goto done;
3349 }
3350 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3351 __func__, carr_offset);
3352 }
3353done:
d0e20e13
MCC		 3354 /* Reset stats */
3355 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3356 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3357 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3358 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 3359 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
d0e20e13 3360
a6dc60ff
KS		 3361 return ret;
3362}
3363
3364static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3365{
3366 int ret = 0, timeout;
3367 enum fe_status status;
3368 struct cxd2841er_priv *priv = fe->demodulator_priv;
3369 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3370
3f3b48a0
AO		 3371 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3372 __func__, p->delivery_system, p->bandwidth_hz);
763f857e
DS		 3373
3374 if (priv->flags & CXD2841ER_EARLY_TUNE)
3375 cxd2841er_tuner_set(fe);
3376
a6dc60ff
KS		 3377 if (p->delivery_system == SYS_DVBT) {
3378 priv->system = SYS_DVBT;
3379 switch (priv->state) {
3380 case STATE_SLEEP_TC:
3381 ret = cxd2841er_sleep_tc_to_active_t(
3382 priv, p->bandwidth_hz);
3383 break;
3384 case STATE_ACTIVE_TC:
3385 ret = cxd2841er_retune_active(priv, p);
3386 break;
3387 default:
3388 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3389 __func__, priv->state);
3390 ret = -EINVAL;
3391 }
3392 } else if (p->delivery_system == SYS_DVBT2) {
3393 priv->system = SYS_DVBT2;
3394 cxd2841er_dvbt2_set_plp_config(priv,
3395 (int)(p->stream_id > 255), p->stream_id);
3396 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3397 switch (priv->state) {
3398 case STATE_SLEEP_TC:
3399 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3400 p->bandwidth_hz);
3401 break;
3402 case STATE_ACTIVE_TC:
3403 ret = cxd2841er_retune_active(priv, p);
3404 break;
3405 default:
3406 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3407 __func__, priv->state);
3408 ret = -EINVAL;
3409 }
83808c23
AO		 3410 } else if (p->delivery_system == SYS_ISDBT) {
3411 priv->system = SYS_ISDBT;
3412 switch (priv->state) {
3413 case STATE_SLEEP_TC:
3414 ret = cxd2841er_sleep_tc_to_active_i(
3415 priv, p->bandwidth_hz);
3416 break;
3417 case STATE_ACTIVE_TC:
3418 ret = cxd2841er_retune_active(priv, p);
3419 break;
3420 default:
3421 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3422 __func__, priv->state);
3423 ret = -EINVAL;
3424 }
a6dc60ff
KS		 3425 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3426 p->delivery_system == SYS_DVBC_ANNEX_C) {
3427 priv->system = SYS_DVBC_ANNEX_A;
3f3b48a0
AO		 3428 /* correct bandwidth */
3429 if (p->bandwidth_hz != 6000000 &&
3430 p->bandwidth_hz != 7000000 &&
3431 p->bandwidth_hz != 8000000) {
3432 p->bandwidth_hz = 8000000;
3433 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3434 __func__, p->bandwidth_hz);
3435 }
3436
a6dc60ff
KS		 3437 switch (priv->state) {
3438 case STATE_SLEEP_TC:
3439 ret = cxd2841er_sleep_tc_to_active_c(
3440 priv, p->bandwidth_hz);
3441 break;
3442 case STATE_ACTIVE_TC:
3443 ret = cxd2841er_retune_active(priv, p);
3444 break;
3445 default:
3446 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3447 __func__, priv->state);
3448 ret = -EINVAL;
3449 }
3450 } else {
3451 dev_dbg(&priv->i2c->dev,
3452 "%s(): invalid delivery system %d\n",
3453 __func__, p->delivery_system);
3454 ret = -EINVAL;
3455 }
3456 if (ret)
3457 goto done;
c7518d13 3458
763f857e
DS		 3459 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3460 cxd2841er_tuner_set(fe);
c7518d13 3461
a6dc60ff
KS		 3462 cxd2841er_tune_done(priv);
3463 timeout = 2500;
3464 while (timeout > 0) {
3465 ret = cxd2841er_read_status_tc(fe, &status);
3466 if (ret)
3467 goto done;
3468 if (status & FE_HAS_LOCK)
3469 break;
3470 msleep(20);
3471 timeout -= 20;
3472 }
3473 if (timeout < 0)
3474 dev_dbg(&priv->i2c->dev,
3475 "%s(): LOCK wait timeout\n", __func__);
3476done:
3477 return ret;
3478}
3479
3480static int cxd2841er_tune_s(struct dvb_frontend *fe,
3481 bool re_tune,
3482 unsigned int mode_flags,
3483 unsigned int *delay,
3484 enum fe_status *status)
3485{
3486 int ret, carrier_offset;
3487 struct cxd2841er_priv *priv = fe->demodulator_priv;
3488 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3489
3490 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3491 if (re_tune) {
3492 ret = cxd2841er_set_frontend_s(fe);
3493 if (ret)
3494 return ret;
3495 cxd2841er_read_status_s(fe, status);
3496 if (*status & FE_HAS_LOCK) {
3497 if (cxd2841er_get_carrier_offset_s_s2(
3498 priv, &carrier_offset))
3499 return -EINVAL;
3500 p->frequency += carrier_offset;
3501 ret = cxd2841er_set_frontend_s(fe);
3502 if (ret)
3503 return ret;
3504 }
3505 }
3506 *delay = HZ / 5;
3507 return cxd2841er_read_status_s(fe, status);
3508}
3509
3510static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3511 bool re_tune,
3512 unsigned int mode_flags,
3513 unsigned int *delay,
3514 enum fe_status *status)
3515{
3516 int ret, carrier_offset;
3517 struct cxd2841er_priv *priv = fe->demodulator_priv;
3518 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3519
3f3b48a0
AO		 3520 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3521 re_tune, p->bandwidth_hz);
a6dc60ff
KS		 3522 if (re_tune) {
3523 ret = cxd2841er_set_frontend_tc(fe);
3524 if (ret)
3525 return ret;
3526 cxd2841er_read_status_tc(fe, status);
3527 if (*status & FE_HAS_LOCK) {
3528 switch (priv->system) {
76344a3f
MCC		 3529 case SYS_ISDBT:
3530 ret = cxd2841er_get_carrier_offset_i(
3531 priv, p->bandwidth_hz,
3532 &carrier_offset);
bb9bd878
AB		 3533 if (ret)
3534 return ret;
76344a3f 3535 break;
a6dc60ff 3536 case SYS_DVBT:
c5ea46da
AO		 3537 ret = cxd2841er_get_carrier_offset_t(
3538 priv, p->bandwidth_hz,
3539 &carrier_offset);
bb9bd878
AB		 3540 if (ret)
3541 return ret;
c5ea46da 3542 break;
a6dc60ff
KS		 3543 case SYS_DVBT2:
3544 ret = cxd2841er_get_carrier_offset_t2(
3545 priv, p->bandwidth_hz,
3546 &carrier_offset);
bb9bd878
AB		 3547 if (ret)
3548 return ret;
a6dc60ff
KS		 3549 break;
3550 case SYS_DVBC_ANNEX_A:
3551 ret = cxd2841er_get_carrier_offset_c(
3552 priv, &carrier_offset);
bb9bd878
AB		 3553 if (ret)
3554 return ret;
a6dc60ff
KS		 3555 break;
3556 default:
3557 dev_dbg(&priv->i2c->dev,
3558 "%s(): invalid delivery system %d\n",
3559 __func__, priv->system);
3560 return -EINVAL;
3561 }
a6dc60ff
KS		 3562 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3563 __func__, carrier_offset);
3564 p->frequency += carrier_offset;
3565 ret = cxd2841er_set_frontend_tc(fe);
3566 if (ret)
3567 return ret;
3568 }
3569 }
3570 *delay = HZ / 5;
3571 return cxd2841er_read_status_tc(fe, status);
3572}
3573
3574static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3575{
3576 struct cxd2841er_priv *priv = fe->demodulator_priv;
3577
3578 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3579 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3580 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3581 return 0;
3582}
3583
3584static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3585{
3586 struct cxd2841er_priv *priv = fe->demodulator_priv;
3587
3588 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3589 if (priv->state == STATE_ACTIVE_TC) {
3590 switch (priv->system) {
3591 case SYS_DVBT:
3592 cxd2841er_active_t_to_sleep_tc(priv);
3593 break;
3594 case SYS_DVBT2:
3595 cxd2841er_active_t2_to_sleep_tc(priv);
3596 break;
83808c23
AO		 3597 case SYS_ISDBT:
3598 cxd2841er_active_i_to_sleep_tc(priv);
3599 break;
a6dc60ff
KS		 3600 case SYS_DVBC_ANNEX_A:
3601 cxd2841er_active_c_to_sleep_tc(priv);
3602 break;
3603 default:
3604 dev_warn(&priv->i2c->dev,
3605 "%s(): unknown delivery system %d\n",
3606 __func__, priv->system);
3607 }
3608 }
3609 if (priv->state != STATE_SLEEP_TC) {
3610 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3611 __func__, priv->state);
3612 return -EINVAL;
3613 }
3614 cxd2841er_sleep_tc_to_shutdown(priv);
3615 return 0;
3616}
3617
3618static int cxd2841er_send_burst(struct dvb_frontend *fe,
3619 enum fe_sec_mini_cmd burst)
3620{
3621 u8 data;
3622 struct cxd2841er_priv *priv = fe->demodulator_priv;
3623
3624 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3625 (burst == SEC_MINI_A ? "A" : "B"));
3626 if (priv->state != STATE_SLEEP_S &&
3627 priv->state != STATE_ACTIVE_S) {
3628 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3629 __func__, priv->state);
3630 return -EINVAL;
3631 }
3632 data = (burst == SEC_MINI_A ? 0 : 1);
3633 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3634 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3635 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3636 return 0;
3637}
3638
3639static int cxd2841er_set_tone(struct dvb_frontend *fe,
3640 enum fe_sec_tone_mode tone)
3641{
3642 u8 data;
3643 struct cxd2841er_priv *priv = fe->demodulator_priv;
3644
3645 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3646 (tone == SEC_TONE_ON ? "On" : "Off"));
3647 if (priv->state != STATE_SLEEP_S &&
3648 priv->state != STATE_ACTIVE_S) {
3649 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3650 __func__, priv->state);
3651 return -EINVAL;
3652 }
3653 data = (tone == SEC_TONE_ON ? 1 : 0);
3654 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3655 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3656 return 0;
3657}
3658
3659static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3660 struct dvb_diseqc_master_cmd *cmd)
3661{
3662 int i;
3663 u8 data[12];
3664 struct cxd2841er_priv *priv = fe->demodulator_priv;
3665
3666 if (priv->state != STATE_SLEEP_S &&
3667 priv->state != STATE_ACTIVE_S) {
3668 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3669 __func__, priv->state);
3670 return -EINVAL;
3671 }
3672 dev_dbg(&priv->i2c->dev,
3673 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3674 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3675 /* DiDEqC enable */
3676 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3677 /* cmd1 length & data */
3678 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3679 memset(data, 0, sizeof(data));
3680 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3681 data[i] = cmd->msg[i];
3682 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3683 /* repeat count for cmd1 */
3684 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3685 /* repeat count for cmd2: always 0 */
3686 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3687 /* start transmit */
3688 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3689 /* wait for 1 sec timeout */
3690 for (i = 0; i < 50; i++) {
3691 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3692 if (!data[0]) {
3693 dev_dbg(&priv->i2c->dev,
3694 "%s(): DiSEqC cmd has been sent\n", __func__);
3695 return 0;
3696 }
3697 msleep(20);
3698 }
3699 dev_dbg(&priv->i2c->dev,
3700 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3701 return -ETIMEDOUT;
3702}
3703
3704static void cxd2841er_release(struct dvb_frontend *fe)
3705{
3706 struct cxd2841er_priv *priv = fe->demodulator_priv;
3707
3708 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3709 kfree(priv);
3710}
3711
3712static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3713{
3714 struct cxd2841er_priv *priv = fe->demodulator_priv;
3715
3716 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3717 cxd2841er_set_reg_bits(
3718 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3719 return 0;
3720}
3721
3722static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3723{
3724 struct cxd2841er_priv *priv = fe->demodulator_priv;
3725
3726 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3727 return DVBFE_ALGO_HW;
3728}
3729
d0e20e13
MCC		 3730static void cxd2841er_init_stats(struct dvb_frontend *fe)
3731{
3732 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3733
3734 p->strength.len = 1;
3735 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3736 p->cnr.len = 1;
3737 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3738 p->block_error.len = 1;
3739 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3740 p->post_bit_error.len = 1;
3741 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14
MCC		 3742 p->post_bit_count.len = 1;
3743 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
d0e20e13
MCC		 3744}
3745
3746
a6dc60ff
KS		 3747static int cxd2841er_init_s(struct dvb_frontend *fe)
3748{
3749 struct cxd2841er_priv *priv = fe->demodulator_priv;
3750
30ae3307
AO		 3751 /* sanity. force demod to SHUTDOWN state */
3752 if (priv->state == STATE_SLEEP_S) {
3753 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3754 __func__);
3755 cxd2841er_sleep_s_to_shutdown(priv);
3756 } else if (priv->state == STATE_ACTIVE_S) {
3757 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3758 __func__);
3759 cxd2841er_active_s_to_sleep_s(priv);
3760 cxd2841er_sleep_s_to_shutdown(priv);
3761 }
3762
a6dc60ff
KS		 3763 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3764 cxd2841er_shutdown_to_sleep_s(priv);
3765 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3766 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3767 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
d0e20e13
MCC		 3768
3769 cxd2841er_init_stats(fe);
3770
a6dc60ff
KS		 3771 return 0;
3772}
3773
3774static int cxd2841er_init_tc(struct dvb_frontend *fe)
3775{
3776 struct cxd2841er_priv *priv = fe->demodulator_priv;
3f3b48a0 3777 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
a6dc60ff 3778
3f3b48a0
AO		 3779 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3780 __func__, p->bandwidth_hz);
a6dc60ff
KS		 3781 cxd2841er_shutdown_to_sleep_tc(priv);
3782 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3783 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3784 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3785 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3786 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3787 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3788 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
03ab1bd5
DS		 3789 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3790 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
d0e20e13
MCC		 3791
3792 cxd2841er_init_stats(fe);
3793
a6dc60ff
KS		 3794 return 0;
3795}
3796
bd336e63 3797static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3f3b48a0 3798static struct dvb_frontend_ops cxd2841er_t_c_ops;
a6dc60ff
KS		 3799
3800static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3801 struct i2c_adapter *i2c,
3802 u8 system)
3803{
3804 u8 chip_id = 0;
3805 const char *type;
3f3b48a0 3806 const char *name;
a6dc60ff
KS		 3807 struct cxd2841er_priv *priv = NULL;
3808
3809 /* allocate memory for the internal state */
3810 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3811 if (!priv)
3812 return NULL;
3813 priv->i2c = i2c;
3814 priv->config = cfg;
3815 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3816 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
83808c23 3817 priv->xtal = cfg->xtal;
050863aa 3818 priv->flags = cfg->flags;
a6dc60ff 3819 priv->frontend.demodulator_priv = priv;
a6dc60ff
KS		 3820 dev_info(&priv->i2c->dev,
3821 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3822 __func__, priv->i2c,
3823 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3824 chip_id = cxd2841er_chip_id(priv);
3f3b48a0 3825 switch (chip_id) {
1ecda28c
DS		 3826 case CXD2837ER_CHIP_ID:
3827 snprintf(cxd2841er_t_c_ops.info.name, 128,
3828 "Sony CXD2837ER DVB-T/T2/C demodulator");
3829 name = "CXD2837ER";
3830 type = "C/T/T2";
3831 break;
3832 case CXD2838ER_CHIP_ID:
3833 snprintf(cxd2841er_t_c_ops.info.name, 128,
3834 "Sony CXD2838ER ISDB-T demodulator");
3835 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3836 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3837 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3838 name = "CXD2838ER";
3839 type = "ISDB-T";
3840 break;
3f3b48a0
AO		 3841 case CXD2841ER_CHIP_ID:
3842 snprintf(cxd2841er_t_c_ops.info.name, 128,
3843 "Sony CXD2841ER DVB-T/T2/C demodulator");
3844 name = "CXD2841ER";
1ecda28c
DS		 3845 type = "T/T2/C/ISDB-T";
3846 break;
3847 case CXD2843ER_CHIP_ID:
3848 snprintf(cxd2841er_t_c_ops.info.name, 128,
3849 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3850 name = "CXD2843ER";
3851 type = "C/C2/T/T2";
3f3b48a0
AO		 3852 break;
3853 case CXD2854ER_CHIP_ID:
3854 snprintf(cxd2841er_t_c_ops.info.name, 128,
3855 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3856 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3857 name = "CXD2854ER";
1ecda28c 3858 type = "C/C2/T/T2/ISDB-T";
3f3b48a0
AO		 3859 break;
3860 default:
a6dc60ff 3861 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3f3b48a0 3862 __func__, chip_id);
a6dc60ff
KS		 3863 priv->frontend.demodulator_priv = NULL;
3864 kfree(priv);
3865 return NULL;
3866 }
3f3b48a0
AO		 3867
3868 /* create dvb_frontend */
3869 if (system == SYS_DVBS) {
3870 memcpy(&priv->frontend.ops,
3871 &cxd2841er_dvbs_s2_ops,
3872 sizeof(struct dvb_frontend_ops));
3873 type = "S/S2";
3874 } else {
3875 memcpy(&priv->frontend.ops,
3876 &cxd2841er_t_c_ops,
3877 sizeof(struct dvb_frontend_ops));
3f3b48a0
AO		 3878 }
3879
3880 dev_info(&priv->i2c->dev,
3881 "%s(): attaching %s DVB-%s frontend\n",
3882 __func__, name, type);
a6dc60ff
KS		 3883 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3884 __func__, chip_id);
3885 return &priv->frontend;
3886}
3887
3888struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3889 struct i2c_adapter *i2c)
3890{
3891 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3892}
3893EXPORT_SYMBOL(cxd2841er_attach_s);
3894
3f3b48a0 3895struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
a6dc60ff
KS		 3896 struct i2c_adapter *i2c)
3897{
3f3b48a0 3898 return cxd2841er_attach(cfg, i2c, 0);
a6dc60ff 3899}
3f3b48a0 3900EXPORT_SYMBOL(cxd2841er_attach_t_c);
a6dc60ff 3901
bd336e63 3902static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
a6dc60ff
KS		 3903 .delsys = { SYS_DVBS, SYS_DVBS2 },
3904 .info = {
3905 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3906 .frequency_min = 500000,
3907 .frequency_max = 2500000,
3908 .frequency_stepsize = 0,
3909 .symbol_rate_min = 1000000,
3910 .symbol_rate_max = 45000000,
3911 .symbol_rate_tolerance = 500,
3912 .caps = FE_CAN_INVERSION_AUTO |
3913 FE_CAN_FEC_AUTO |
3914 FE_CAN_QPSK,
3915 },
3916 .init = cxd2841er_init_s,
3917 .sleep = cxd2841er_sleep_s,
3918 .release = cxd2841er_release,
3919 .set_frontend = cxd2841er_set_frontend_s,
3920 .get_frontend = cxd2841er_get_frontend,
3921 .read_status = cxd2841er_read_status_s,
3922 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3923 .get_frontend_algo = cxd2841er_get_algo,
3924 .set_tone = cxd2841er_set_tone,
3925 .diseqc_send_burst = cxd2841er_send_burst,
3926 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3927 .tune = cxd2841er_tune_s
3928};
3929
bd336e63 3930static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3f3b48a0 3931 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
83808c23 3932 .info = {
3f3b48a0 3933 .name = "", /* will set in attach function */
83808c23
AO		 3934 .caps = FE_CAN_FEC_1_2 |
3935 FE_CAN_FEC_2_3 |
3936 FE_CAN_FEC_3_4 |
3937 FE_CAN_FEC_5_6 |
3938 FE_CAN_FEC_7_8 |
3939 FE_CAN_FEC_AUTO |
3940 FE_CAN_QPSK |
3941 FE_CAN_QAM_16 |
3942 FE_CAN_QAM_32 |
3943 FE_CAN_QAM_64 |
3944 FE_CAN_QAM_128 |
3945 FE_CAN_QAM_256 |
3946 FE_CAN_QAM_AUTO |
3947 FE_CAN_TRANSMISSION_MODE_AUTO |
3948 FE_CAN_GUARD_INTERVAL_AUTO |
3949 FE_CAN_HIERARCHY_AUTO |
3950 FE_CAN_MUTE_TS |
3951 FE_CAN_2G_MODULATION,
3952 .frequency_min = 42000000,
158f0328
DS		 3953 .frequency_max = 1002000000,
3954 .symbol_rate_min = 870000,
3955 .symbol_rate_max = 11700000
83808c23
AO		 3956 },
3957 .init = cxd2841er_init_tc,
3958 .sleep = cxd2841er_sleep_tc,
3959 .release = cxd2841er_release,
3960 .set_frontend = cxd2841er_set_frontend_tc,
3961 .get_frontend = cxd2841er_get_frontend,
3962 .read_status = cxd2841er_read_status_tc,
3963 .tune = cxd2841er_tune_tc,
3964 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3965 .get_frontend_algo = cxd2841er_get_algo
3966};
3967
83808c23
AO		 3968MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3969MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
a6dc60ff 3970MODULE_LICENSE("GPL");
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