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[media] Add carrier offset calculation for DVB-T
[mirror_ubuntu-zesty-kernel.git] / drivers / media / dvb-frontends / cxd2841er.c
CommitLineData
a6dc60ff
KS		 1/*
2 * cxd2841er.c
3 *
83808c23
AO		 4 * Sony digital demodulator driver for
5 * CXD2441ER - DVB-S/S2/T/T2/C/C2
6 * CXD2454ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
a6dc60ff
KS		 7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
d13a7b67
MCC		 38#define MAX_WRITE_REGSIZE 16
39
a6dc60ff
KS		 40enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46};
47
48struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
83808c23 56 enum cxd2841er_xtal xtal;
a6dc60ff
KS		 57};
58
59static const struct cxd2841er_cnr_data s_cn_data[] = {
60 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
61 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
62 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
63 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
64 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
65 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
66 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
67 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
68 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
69 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
70 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
71 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
72 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
73 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
74 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
75 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
76 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
77 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
78 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
79 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
80 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
81 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
82 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
83 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
84 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
85 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
86 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
87 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
88 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
89 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
90 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
91 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
92 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
93 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
94 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
95 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
96 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
97 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
98 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
99 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
100 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
101 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
102 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
103 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
104 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
105 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
106 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
107 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
108 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
109 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
110 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
111 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
112 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
113 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
114 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
115 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
116 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
117 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
118 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
119 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
120 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
121 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
122 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
123 { 0x0015, 19900 }, { 0x0014, 20000 },
124};
125
126static const struct cxd2841er_cnr_data s2_cn_data[] = {
127 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
128 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
129 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
130 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
131 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
132 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
133 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
134 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
135 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
136 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
137 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
138 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
139 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
140 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
141 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
142 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
143 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
144 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
145 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
146 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
147 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
148 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
149 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
150 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
151 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
152 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
153 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
154 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
155 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
156 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
157 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
158 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
159 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
160 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
161 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
162 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
163 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
164 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
165 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
166 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
167 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
168 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
169 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
170 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
171 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
172 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
173 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
174 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
175 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
176 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
177 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
178 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
179 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
180 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
181 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
182 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
183 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
184 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
185 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
186 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
187 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
188 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
189 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
190 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
191};
192
193#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
83808c23
AO		 194#define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
195 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
196 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
a6dc60ff
KS		 197
198static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
199 u8 addr, u8 reg, u8 write,
200 const u8 *data, u32 len)
201{
202 dev_dbg(&priv->i2c->dev,
203 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
204 (write == 0 ? "read" : "write"), addr, reg, len);
205 print_hex_dump_bytes("cxd2841er: I2C data: ",
206 DUMP_PREFIX_OFFSET, data, len);
207}
208
209static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
210 u8 addr, u8 reg, const u8 *data, u32 len)
211{
212 int ret;
d13a7b67 213 u8 buf[MAX_WRITE_REGSIZE + 1];
a6dc60ff
KS		 214 u8 i2c_addr = (addr == I2C_SLVX ?
215 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
216 struct i2c_msg msg[1] = {
217 {
218 .addr = i2c_addr,
219 .flags = 0,
d13a7b67 220 .len = len + 1,
a6dc60ff
KS		 221 .buf = buf,
222 }
223 };
224
d13a7b67 225 if (len + 1 >= sizeof(buf)) {
83808c23 226 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
d13a7b67
MCC		 227 reg, len + 1);
228 return -E2BIG;
229 }
230
a6dc60ff
KS		 231 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
232 buf[0] = reg;
233 memcpy(&buf[1], data, len);
234
235 ret = i2c_transfer(priv->i2c, msg, 1);
236 if (ret >= 0 && ret != 1)
237 ret = -EIO;
238 if (ret < 0) {
239 dev_warn(&priv->i2c->dev,
240 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
241 KBUILD_MODNAME, ret, i2c_addr, reg, len);
242 return ret;
243 }
244 return 0;
245}
246
247static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
248 u8 addr, u8 reg, u8 val)
249{
250 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
251}
252
253static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
254 u8 addr, u8 reg, u8 *val, u32 len)
255{
256 int ret;
257 u8 i2c_addr = (addr == I2C_SLVX ?
258 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
259 struct i2c_msg msg[2] = {
260 {
261 .addr = i2c_addr,
262 .flags = 0,
263 .len = 1,
264 .buf = &reg,
265 }, {
266 .addr = i2c_addr,
267 .flags = I2C_M_RD,
268 .len = len,
269 .buf = val,
270 }
271 };
272
273 ret = i2c_transfer(priv->i2c, &msg[0], 1);
274 if (ret >= 0 && ret != 1)
275 ret = -EIO;
276 if (ret < 0) {
277 dev_warn(&priv->i2c->dev,
278 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
279 KBUILD_MODNAME, ret, i2c_addr, reg);
280 return ret;
281 }
282 ret = i2c_transfer(priv->i2c, &msg[1], 1);
283 if (ret >= 0 && ret != 1)
284 ret = -EIO;
285 if (ret < 0) {
286 dev_warn(&priv->i2c->dev,
287 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
288 KBUILD_MODNAME, ret, i2c_addr, reg);
289 return ret;
290 }
291 return 0;
292}
293
294static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
295 u8 addr, u8 reg, u8 *val)
296{
297 return cxd2841er_read_regs(priv, addr, reg, val, 1);
298}
299
300static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
301 u8 addr, u8 reg, u8 data, u8 mask)
302{
303 int res;
304 u8 rdata;
305
306 if (mask != 0xff) {
307 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
308 if (res)
309 return res;
310 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
311 }
312 return cxd2841er_write_reg(priv, addr, reg, data);
313}
314
315static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
316 u32 symbol_rate)
317{
318 u32 reg_value = 0;
319 u8 data[3] = {0, 0, 0};
320
321 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
322 /*
323 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
324 * = ((symbolRateKSps * 2^14) + 500) / 1000
325 * = ((symbolRateKSps * 16384) + 500) / 1000
326 */
327 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
328 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
329 dev_err(&priv->i2c->dev,
330 "%s(): reg_value is out of range\n", __func__);
331 return -EINVAL;
332 }
333 data[0] = (u8)((reg_value >> 16) & 0x0F);
334 data[1] = (u8)((reg_value >> 8) & 0xFF);
335 data[2] = (u8)(reg_value & 0xFF);
336 /* Set SLV-T Bank : 0xAE */
337 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
338 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
339 return 0;
340}
341
342static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
343 u8 system);
344
345static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
346 u8 system, u32 symbol_rate)
347{
348 int ret;
349 u8 data[4] = { 0, 0, 0, 0 };
350
351 if (priv->state != STATE_SLEEP_S) {
352 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
353 __func__, (int)priv->state);
354 return -EINVAL;
355 }
356 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
357 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
358 /* Set demod mode */
359 if (system == SYS_DVBS) {
360 data[0] = 0x0A;
361 } else if (system == SYS_DVBS2) {
362 data[0] = 0x0B;
363 } else {
364 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
365 __func__, system);
366 return -EINVAL;
367 }
368 /* Set SLV-X Bank : 0x00 */
369 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
370 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
371 /* DVB-S/S2 */
372 data[0] = 0x00;
373 /* Set SLV-T Bank : 0x00 */
374 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
375 /* Enable S/S2 auto detection 1 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
377 /* Set SLV-T Bank : 0xAE */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
379 /* Enable S/S2 auto detection 2 */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
381 /* Set SLV-T Bank : 0x00 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
383 /* Enable demod clock */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
385 /* Enable ADC clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
387 /* Enable ADC 1 */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
389 /* Enable ADC 2 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
391 /* Set SLV-X Bank : 0x00 */
392 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
393 /* Enable ADC 3 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
395 /* Set SLV-T Bank : 0xA3 */
396 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
397 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
398 data[0] = 0x07;
399 data[1] = 0x3B;
400 data[2] = 0x08;
401 data[3] = 0xC5;
402 /* Set SLV-T Bank : 0xAB */
403 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
404 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
405 data[0] = 0x05;
406 data[1] = 0x80;
407 data[2] = 0x0A;
408 data[3] = 0x80;
409 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
410 data[0] = 0x0C;
411 data[1] = 0xCC;
412 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
413 /* Set demod parameter */
414 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
415 if (ret != 0)
416 return ret;
417 /* Set SLV-T Bank : 0x00 */
418 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
419 /* disable Hi-Z setting 1 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
421 /* disable Hi-Z setting 2 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
423 priv->state = STATE_ACTIVE_S;
424 return 0;
425}
426
427static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
428 u32 bandwidth);
429
430static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
431 u32 bandwidth);
432
433static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
434 u32 bandwidth);
435
436static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
437 struct dtv_frontend_properties *p)
438{
439 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
440 if (priv->state != STATE_ACTIVE_S &&
441 priv->state != STATE_ACTIVE_TC) {
442 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
443 __func__, priv->state);
444 return -EINVAL;
445 }
446 /* Set SLV-T Bank : 0x00 */
447 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
448 /* disable TS output */
449 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
450 if (priv->state == STATE_ACTIVE_S)
451 return cxd2841er_dvbs2_set_symbol_rate(
452 priv, p->symbol_rate / 1000);
453 else if (priv->state == STATE_ACTIVE_TC) {
454 switch (priv->system) {
455 case SYS_DVBT:
456 return cxd2841er_sleep_tc_to_active_t_band(
457 priv, p->bandwidth_hz);
458 case SYS_DVBT2:
459 return cxd2841er_sleep_tc_to_active_t2_band(
460 priv, p->bandwidth_hz);
461 case SYS_DVBC_ANNEX_A:
462 return cxd2841er_sleep_tc_to_active_c_band(
463 priv, 8000000);
464 }
465 }
466 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
467 __func__, priv->system);
468 return -EINVAL;
469}
470
471static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
472{
473 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
474 if (priv->state != STATE_ACTIVE_S) {
475 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
476 __func__, priv->state);
477 return -EINVAL;
478 }
479 /* Set SLV-T Bank : 0x00 */
480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
481 /* disable TS output */
482 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
483 /* enable Hi-Z setting 1 */
484 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
485 /* enable Hi-Z setting 2 */
486 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
487 /* Set SLV-X Bank : 0x00 */
488 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
489 /* disable ADC 1 */
490 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
491 /* Set SLV-T Bank : 0x00 */
492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
493 /* disable ADC clock */
494 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
495 /* disable ADC 2 */
496 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
497 /* disable ADC 3 */
498 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
499 /* SADC Bias ON */
500 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
501 /* disable demod clock */
502 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
503 /* Set SLV-T Bank : 0xAE */
504 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
505 /* disable S/S2 auto detection1 */
506 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
507 /* Set SLV-T Bank : 0x00 */
508 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
509 /* disable S/S2 auto detection2 */
510 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
511 priv->state = STATE_SLEEP_S;
512 return 0;
513}
514
515static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
516{
517 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
518 if (priv->state != STATE_SLEEP_S) {
519 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
520 __func__, priv->state);
521 return -EINVAL;
522 }
523 /* Set SLV-T Bank : 0x00 */
524 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
525 /* Disable DSQOUT */
526 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
527 /* Disable DSQIN */
528 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
529 /* Set SLV-X Bank : 0x00 */
530 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
531 /* Disable oscillator */
532 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
533 /* Set demod mode */
534 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
535 priv->state = STATE_SHUTDOWN;
536 return 0;
537}
538
539static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
540{
541 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
542 if (priv->state != STATE_SLEEP_TC) {
543 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
544 __func__, priv->state);
545 return -EINVAL;
546 }
547 /* Set SLV-X Bank : 0x00 */
548 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
549 /* Disable oscillator */
550 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
551 /* Set demod mode */
552 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
553 priv->state = STATE_SHUTDOWN;
554 return 0;
555}
556
557static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
558{
559 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
560 if (priv->state != STATE_ACTIVE_TC) {
561 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
562 __func__, priv->state);
563 return -EINVAL;
564 }
565 /* Set SLV-T Bank : 0x00 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
567 /* disable TS output */
568 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
569 /* enable Hi-Z setting 1 */
570 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
571 /* enable Hi-Z setting 2 */
572 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
573 /* Set SLV-X Bank : 0x00 */
574 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
575 /* disable ADC 1 */
576 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
577 /* Set SLV-T Bank : 0x00 */
578 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
579 /* Disable ADC 2 */
580 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
581 /* Disable ADC 3 */
582 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
583 /* Disable ADC clock */
584 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
585 /* Disable RF level monitor */
586 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
587 /* Disable demod clock */
588 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
589 priv->state = STATE_SLEEP_TC;
590 return 0;
591}
592
593static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
594{
595 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
596 if (priv->state != STATE_ACTIVE_TC) {
597 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
598 __func__, priv->state);
599 return -EINVAL;
600 }
601 /* Set SLV-T Bank : 0x00 */
602 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
603 /* disable TS output */
604 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
605 /* enable Hi-Z setting 1 */
606 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
607 /* enable Hi-Z setting 2 */
608 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
609 /* Cancel DVB-T2 setting */
610 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
611 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
612 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
613 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
614 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
615 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
616 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
617 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
618 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
619 /* Set SLV-X Bank : 0x00 */
620 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
621 /* disable ADC 1 */
622 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
623 /* Set SLV-T Bank : 0x00 */
624 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
625 /* Disable ADC 2 */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
627 /* Disable ADC 3 */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
629 /* Disable ADC clock */
630 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
631 /* Disable RF level monitor */
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
633 /* Disable demod clock */
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
635 priv->state = STATE_SLEEP_TC;
636 return 0;
637}
638
639static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
640{
641 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
642 if (priv->state != STATE_ACTIVE_TC) {
643 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
644 __func__, priv->state);
645 return -EINVAL;
646 }
647 /* Set SLV-T Bank : 0x00 */
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
649 /* disable TS output */
650 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
651 /* enable Hi-Z setting 1 */
652 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
653 /* enable Hi-Z setting 2 */
654 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
655 /* Cancel DVB-C setting */
656 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
657 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
658 /* Set SLV-X Bank : 0x00 */
659 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
660 /* disable ADC 1 */
661 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
662 /* Set SLV-T Bank : 0x00 */
663 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
664 /* Disable ADC 2 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
666 /* Disable ADC 3 */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
668 /* Disable ADC clock */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
670 /* Disable RF level monitor */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
672 /* Disable demod clock */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
674 priv->state = STATE_SLEEP_TC;
675 return 0;
676}
677
83808c23
AO		 678static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
679{
680 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
681 if (priv->state != STATE_ACTIVE_TC) {
682 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
683 __func__, priv->state);
684 return -EINVAL;
685 }
686 /* Set SLV-T Bank : 0x00 */
687 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
688 /* disable TS output */
689 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
690 /* enable Hi-Z setting 1 */
691 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
692 /* enable Hi-Z setting 2 */
693 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
694
695 /* TODO: Cancel demod parameter */
696
697 /* Set SLV-X Bank : 0x00 */
698 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
699 /* disable ADC 1 */
700 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
701 /* Set SLV-T Bank : 0x00 */
702 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
703 /* Disable ADC 2 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
705 /* Disable ADC 3 */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
707 /* Disable ADC clock */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
709 /* Disable RF level monitor */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
711 /* Disable demod clock */
712 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
713 priv->state = STATE_SLEEP_TC;
714 return 0;
715}
716
a6dc60ff
KS		 717static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
718{
719 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
720 if (priv->state != STATE_SHUTDOWN) {
721 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
722 __func__, priv->state);
723 return -EINVAL;
724 }
725 /* Set SLV-X Bank : 0x00 */
726 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
727 /* Clear all demodulator registers */
728 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
729 usleep_range(3000, 5000);
730 /* Set SLV-X Bank : 0x00 */
731 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
732 /* Set demod SW reset */
733 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
83808c23
AO		 734
735 switch (priv->xtal) {
736 case SONY_XTAL_20500:
737 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
738 break;
739 case SONY_XTAL_24000:
740 /* Select demod frequency */
741 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
742 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
743 break;
744 case SONY_XTAL_41000:
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
746 break;
747 default:
748 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
749 __func__, priv->xtal);
750 return -EINVAL;
751 }
752
a6dc60ff
KS		 753 /* Set demod mode */
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
755 /* Clear demod SW reset */
756 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
757 usleep_range(1000, 2000);
758 /* Set SLV-T Bank : 0x00 */
759 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
760 /* enable DSQOUT */
761 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
762 /* enable DSQIN */
763 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
764 /* TADC Bias On */
765 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
766 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
767 /* SADC Bias On */
768 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
769 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
770 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
771 priv->state = STATE_SLEEP_S;
772 return 0;
773}
774
775static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
776{
777 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
778 if (priv->state != STATE_SHUTDOWN) {
779 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
780 __func__, priv->state);
781 return -EINVAL;
782 }
783 /* Set SLV-X Bank : 0x00 */
784 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
785 /* Clear all demodulator registers */
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
787 usleep_range(3000, 5000);
788 /* Set SLV-X Bank : 0x00 */
789 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
790 /* Set demod SW reset */
791 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
792 /* Set X'tal clock to 20.5Mhz */
793 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
794 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
795 /* Clear demod SW reset */
796 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
797 usleep_range(1000, 2000);
798 /* Set SLV-T Bank : 0x00 */
799 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
800 /* TADC Bias On */
801 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
802 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
803 /* SADC Bias On */
804 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
805 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
806 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
807 priv->state = STATE_SLEEP_TC;
808 return 0;
809}
810
811static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
812{
813 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
814 /* Set SLV-T Bank : 0x00 */
815 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
816 /* SW Reset */
817 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
818 /* Enable TS output */
819 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
820 return 0;
821}
822
823/* Set TS parallel mode */
824static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
825 u8 system)
826{
827 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
828
829 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
830 /* Set SLV-T Bank : 0x00 */
831 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
832 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
833 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
834 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
835 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
836 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
837
838 /*
839 * slave Bank Addr Bit default Name
840 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
841 */
842 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
843 /*
844 * Disable TS IF Clock
845 * slave Bank Addr Bit default Name
846 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
847 */
848 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
849 /*
850 * slave Bank Addr Bit default Name
851 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
852 */
853 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
854 /*
855 * Enable TS IF Clock
856 * slave Bank Addr Bit default Name
857 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
858 */
859 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
860
861 if (system == SYS_DVBT) {
862 /* Enable parity period for DVB-T */
863 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
864 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
865 } else if (system == SYS_DVBC_ANNEX_A) {
866 /* Enable parity period for DVB-C */
867 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
868 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
869 }
870}
871
872static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
873{
83808c23 874 u8 chip_id = 0;
a6dc60ff
KS		 875
876 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
83808c23
AO		 877 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
878 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
879 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
880 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
881
a6dc60ff
KS		 882 return chip_id;
883}
884
885static int cxd2841er_read_status_s(struct dvb_frontend *fe,
886 enum fe_status *status)
887{
888 u8 reg = 0;
889 struct cxd2841er_priv *priv = fe->demodulator_priv;
890
891 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
892 *status = 0;
893 if (priv->state != STATE_ACTIVE_S) {
894 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
895 __func__, priv->state);
896 return -EINVAL;
897 }
898 /* Set SLV-T Bank : 0xA0 */
899 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
900 /*
901 * slave Bank Addr Bit Signal name
902 * <SLV-T> A0h 11h [2] ITSLOCK
903 */
904 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
905 if (reg & 0x04) {
906 *status = FE_HAS_SIGNAL
907 | FE_HAS_CARRIER
908 | FE_HAS_VITERBI
909 | FE_HAS_SYNC
910 | FE_HAS_LOCK;
911 }
912 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
913 return 0;
914}
915
916static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
917 u8 *sync, u8 *tslock, u8 *unlock)
918{
919 u8 data = 0;
920
921 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
922 if (priv->state != STATE_ACTIVE_TC)
923 return -EINVAL;
924 if (priv->system == SYS_DVBT) {
925 /* Set SLV-T Bank : 0x10 */
926 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
927 } else {
928 /* Set SLV-T Bank : 0x20 */
929 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
930 }
931 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
932 if ((data & 0x07) == 0x07) {
933 dev_dbg(&priv->i2c->dev,
934 "%s(): invalid hardware state detected\n", __func__);
935 *sync = 0;
936 *tslock = 0;
937 *unlock = 0;
938 } else {
939 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
940 *tslock = ((data & 0x20) ? 1 : 0);
941 *unlock = ((data & 0x10) ? 1 : 0);
942 }
943 return 0;
944}
945
946static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
947{
948 u8 data;
949
950 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
951 if (priv->state != STATE_ACTIVE_TC)
952 return -EINVAL;
953 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
954 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
955 if ((data & 0x01) == 0) {
956 *tslock = 0;
957 } else {
958 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
959 *tslock = ((data & 0x20) ? 1 : 0);
960 }
961 return 0;
962}
963
83808c23
AO		 964static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
965 u8 *sync, u8 *tslock, u8 *unlock)
966{
967 u8 data = 0;
968
969 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
970 if (priv->state != STATE_ACTIVE_TC)
971 return -EINVAL;
972 /* Set SLV-T Bank : 0x60 */
973 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
974 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
975 dev_dbg(&priv->i2c->dev,
976 "%s(): lock=0x%x\n", __func__, data);
977 *sync = ((data & 0x02) ? 1 : 0);
978 *tslock = ((data & 0x01) ? 1 : 0);
979 *unlock = ((data & 0x10) ? 1 : 0);
980 return 0;
981}
982
a6dc60ff
KS		 983static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
984 enum fe_status *status)
985{
986 int ret = 0;
987 u8 sync = 0;
988 u8 tslock = 0;
989 u8 unlock = 0;
990 struct cxd2841er_priv *priv = fe->demodulator_priv;
991
992 *status = 0;
993 if (priv->state == STATE_ACTIVE_TC) {
994 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
995 ret = cxd2841er_read_status_t_t2(
996 priv, &sync, &tslock, &unlock);
997 if (ret)
998 goto done;
999 if (unlock)
1000 goto done;
1001 if (sync)
1002 *status = FE_HAS_SIGNAL |
1003 FE_HAS_CARRIER |
1004 FE_HAS_VITERBI |
1005 FE_HAS_SYNC;
1006 if (tslock)
1007 *status |= FE_HAS_LOCK;
83808c23
AO		 1008 } else if (priv->system == SYS_ISDBT) {
1009 ret = cxd2841er_read_status_i(
1010 priv, &sync, &tslock, &unlock);
1011 if (ret)
1012 goto done;
1013 if (unlock)
1014 goto done;
1015 if (sync)
1016 *status = FE_HAS_SIGNAL |
1017 FE_HAS_CARRIER |
1018 FE_HAS_VITERBI |
1019 FE_HAS_SYNC;
1020 if (tslock)
1021 *status |= FE_HAS_LOCK;
a6dc60ff
KS		 1022 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1023 ret = cxd2841er_read_status_c(priv, &tslock);
1024 if (ret)
1025 goto done;
1026 if (tslock)
1027 *status = FE_HAS_SIGNAL |
1028 FE_HAS_CARRIER |
1029 FE_HAS_VITERBI |
1030 FE_HAS_SYNC |
1031 FE_HAS_LOCK;
1032 }
1033 }
1034done:
1035 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1036 return ret;
1037}
1038
1039static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1040 int *offset)
1041{
1042 u8 data[3];
1043 u8 is_hs_mode;
1044 s32 cfrl_ctrlval;
1045 s32 temp_div, temp_q, temp_r;
1046
1047 if (priv->state != STATE_ACTIVE_S) {
1048 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1049 __func__, priv->state);
1050 return -EINVAL;
1051 }
1052 /*
1053 * Get High Sampling Rate mode
1054 * slave Bank Addr Bit Signal name
1055 * <SLV-T> A0h 10h [0] ITRL_LOCK
1056 */
1057 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1058 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1059 if (data[0] & 0x01) {
1060 /*
1061 * slave Bank Addr Bit Signal name
1062 * <SLV-T> A0h 50h [4] IHSMODE
1063 */
1064 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1065 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1066 } else {
1067 dev_dbg(&priv->i2c->dev,
1068 "%s(): unable to detect sampling rate mode\n",
1069 __func__);
1070 return -EINVAL;
1071 }
1072 /*
1073 * slave Bank Addr Bit Signal name
1074 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1075 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1076 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1077 */
1078 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1079 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1080 (((u32)data[1] & 0xFF) << 8) |
1081 ((u32)data[2] & 0xFF), 20);
1082 temp_div = (is_hs_mode ? 1048576 : 1572864);
1083 if (cfrl_ctrlval > 0) {
1084 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1085 temp_div, &temp_r);
1086 } else {
1087 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1088 temp_div, &temp_r);
1089 }
1090 if (temp_r >= temp_div / 2)
1091 temp_q++;
1092 if (cfrl_ctrlval > 0)
1093 temp_q *= -1;
1094 *offset = temp_q;
1095 return 0;
1096}
1097
c5ea46da
AO		 1098static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1099 u32 bandwidth, int *offset)
1100{
1101 u8 data[4];
1102
1103 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1104 if (priv->state != STATE_ACTIVE_TC) {
1105 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1106 __func__, priv->state);
1107 return -EINVAL;
1108 }
1109 if (priv->system != SYS_DVBT) {
1110 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1111 __func__, priv->system);
1112 return -EINVAL;
1113 }
1114 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1115 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1116 *offset = -1 * sign_extend32(
1117 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1118 ((u32)data[2] << 8) | (u32)data[3], 29);
1119 return 0;
1120}
1121
c8946c8d
MCC		 1122static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1123 u32 bandwidth, int *offset)
a6dc60ff
KS		 1124{
1125 u8 data[4];
1126
1127 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1128 if (priv->state != STATE_ACTIVE_TC) {
1129 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1130 __func__, priv->state);
1131 return -EINVAL;
1132 }
1133 if (priv->system != SYS_DVBT2) {
1134 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1135 __func__, priv->system);
1136 return -EINVAL;
1137 }
1138 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1139 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1140 *offset = -1 * sign_extend32(
1141 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1142 ((u32)data[2] << 8) | (u32)data[3], 27);
1143 switch (bandwidth) {
1144 case 1712000:
1145 *offset /= 582;
1146 break;
1147 case 5000000:
1148 case 6000000:
1149 case 7000000:
1150 case 8000000:
1151 *offset *= (bandwidth / 1000000);
1152 *offset /= 940;
1153 break;
1154 default:
1155 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1156 __func__, bandwidth);
1157 return -EINVAL;
1158 }
1159 return 0;
1160}
1161
c8946c8d
MCC		 1162static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1163 int *offset)
a6dc60ff
KS		 1164{
1165 u8 data[2];
1166
1167 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1168 if (priv->state != STATE_ACTIVE_TC) {
1169 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1170 __func__, priv->state);
1171 return -EINVAL;
1172 }
1173 if (priv->system != SYS_DVBC_ANNEX_A) {
1174 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1175 __func__, priv->system);
1176 return -EINVAL;
1177 }
1178 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1179 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1180 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1181 | (u32)data[1], 13), 16384);
1182 return 0;
1183}
1184
1185static int cxd2841er_read_packet_errors_t(
1186 struct cxd2841er_priv *priv, u32 *penum)
1187{
1188 u8 data[3];
1189
1190 *penum = 0;
1191 if (priv->state != STATE_ACTIVE_TC) {
1192 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1193 __func__, priv->state);
1194 return -EINVAL;
1195 }
1196 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1197 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1198 if (data[2] & 0x01)
1199 *penum = ((u32)data[0] << 8) | (u32)data[1];
1200 return 0;
1201}
1202
1203static int cxd2841er_read_packet_errors_t2(
1204 struct cxd2841er_priv *priv, u32 *penum)
1205{
1206 u8 data[3];
1207
1208 *penum = 0;
1209 if (priv->state != STATE_ACTIVE_TC) {
1210 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1211 __func__, priv->state);
1212 return -EINVAL;
1213 }
1214 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1215 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1216 if (data[0] & 0x01)
1217 *penum = ((u32)data[1] << 8) | (u32)data[2];
1218 return 0;
1219}
1220
83808c23
AO		 1221static int cxd2841er_read_packet_errors_i(
1222 struct cxd2841er_priv *priv, u32 *penum)
1223{
1224 u8 data[2];
1225
1226 *penum = 0;
1227 if (priv->state != STATE_ACTIVE_TC) {
1228 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1229 __func__, priv->state);
1230 return -EINVAL;
1231 }
1232 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1233 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1234
1235 if (!(data[0] & 0x01))
1236 return 0;
1237
1238 /* Layer A */
1239 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1240 *penum = ((u32)data[0] << 8) | (u32)data[1];
1241
1242 /* Layer B */
1243 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1244 *penum += ((u32)data[0] << 8) | (u32)data[1];
1245
1246 /* Layer C */
1247 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1248 *penum += ((u32)data[0] << 8) | (u32)data[1];
1249
1250 return 0;
1251}
1252
a6dc60ff
KS		 1253static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1254{
1255 u8 data[11];
1256 u32 bit_error, bit_count;
1257 u32 temp_q, temp_r;
1258
1259 /* Set SLV-T Bank : 0xA0 */
1260 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1261 /*
1262 * slave Bank Addr Bit Signal name
1263 * <SLV-T> A0h 35h [0] IFVBER_VALID
1264 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1265 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1266 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1267 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1268 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1269 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1270 */
1271 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1272 if (data[0] & 0x01) {
1273 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1274 ((u32)(data[2] & 0xFF) << 8) |
1275 (u32)(data[3] & 0xFF);
1276 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1277 ((u32)(data[9] & 0xFF) << 8) |
1278 (u32)(data[10] & 0xFF);
1279 /*
1280 * BER = bitError / bitCount
1281 * = (bitError * 10^7) / bitCount
1282 * = ((bitError * 625 * 125 * 128) / bitCount
1283 */
1284 if ((bit_count == 0) || (bit_error > bit_count)) {
1285 dev_dbg(&priv->i2c->dev,
1286 "%s(): invalid bit_error %d, bit_count %d\n",
1287 __func__, bit_error, bit_count);
1288 return 0;
1289 }
1290 temp_q = div_u64_rem(10000000ULL * bit_error,
1291 bit_count, &temp_r);
1292 if (bit_count != 1 && temp_r >= bit_count / 2)
1293 temp_q++;
1294 return temp_q;
1295 }
1296 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1297 return 0;
1298}
1299
1300
1301static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1302{
1303 u8 data[5];
1304 u32 bit_error, period;
1305 u32 temp_q, temp_r;
1306 u32 result = 0;
1307
1308 /* Set SLV-T Bank : 0xB2 */
1309 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1310 /*
1311 * slave Bank Addr Bit Signal name
1312 * <SLV-T> B2h 30h [0] IFLBER_VALID
1313 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1314 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1315 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1316 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1317 */
1318 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1319 if (data[0] & 0x01) {
1320 /* Bit error count */
1321 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1322 ((u32)(data[2] & 0xFF) << 16) |
1323 ((u32)(data[3] & 0xFF) << 8) |
1324 (u32)(data[4] & 0xFF);
1325
1326 /* Set SLV-T Bank : 0xA0 */
1327 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1328 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1329 /* Measurement period */
1330 period = (u32)(1 << (data[0] & 0x0F));
1331 if (period == 0) {
1332 dev_dbg(&priv->i2c->dev,
1333 "%s(): period is 0\n", __func__);
1334 return 0;
1335 }
1336 if (bit_error > (period * 64800)) {
1337 dev_dbg(&priv->i2c->dev,
1338 "%s(): invalid bit_err 0x%x period 0x%x\n",
1339 __func__, bit_error, period);
1340 return 0;
1341 }
1342 /*
1343 * BER = bitError / (period * 64800)
1344 * = (bitError * 10^7) / (period * 64800)
1345 * = (bitError * 10^5) / (period * 648)
1346 * = (bitError * 12500) / (period * 81)
1347 * = (bitError * 10) * 1250 / (period * 81)
1348 */
1349 temp_q = div_u64_rem(12500ULL * bit_error,
1350 period * 81, &temp_r);
1351 if (temp_r >= period * 40)
1352 temp_q++;
1353 result = temp_q;
1354 } else {
1355 dev_dbg(&priv->i2c->dev,
1356 "%s(): no data available\n", __func__);
1357 }
1358 return result;
1359}
1360
1361static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1362{
1363 u8 data[4];
1364 u32 div, q, r;
1365 u32 bit_err, period_exp, n_ldpc;
1366
1367 *ber = 0;
1368 if (priv->state != STATE_ACTIVE_TC) {
1369 dev_dbg(&priv->i2c->dev,
1370 "%s(): invalid state %d\n", __func__, priv->state);
1371 return -EINVAL;
1372 }
1373 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1374 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1375 if (!(data[0] & 0x10)) {
1376 dev_dbg(&priv->i2c->dev,
1377 "%s(): no valid BER data\n", __func__);
1378 return 0;
1379 }
1380 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1381 ((u32)data[1] << 16) |
1382 ((u32)data[2] << 8) |
1383 (u32)data[3];
1384 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1385 period_exp = data[0] & 0x0f;
1386 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1387 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1388 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1389 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1390 dev_dbg(&priv->i2c->dev,
1391 "%s(): invalid BER value\n", __func__);
1392 return -EINVAL;
1393 }
1394 if (period_exp >= 4) {
1395 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1396 q = div_u64_rem(3125ULL * bit_err, div, &r);
1397 } else {
1398 div = (1U << period_exp) * (n_ldpc / 200);
1399 q = div_u64_rem(50000ULL * bit_err, div, &r);
1400 }
1401 *ber = (r >= div / 2) ? q + 1 : q;
1402 return 0;
1403}
1404
1405static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1406{
1407 u8 data[2];
1408 u32 div, q, r;
1409 u32 bit_err, period;
1410
1411 *ber = 0;
1412 if (priv->state != STATE_ACTIVE_TC) {
1413 dev_dbg(&priv->i2c->dev,
1414 "%s(): invalid state %d\n", __func__, priv->state);
1415 return -EINVAL;
1416 }
1417 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1418 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1419 if (!(data[0] & 0x01)) {
1420 dev_dbg(&priv->i2c->dev,
1421 "%s(): no valid BER data\n", __func__);
1422 return 0;
1423 }
1424 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1425 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1426 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1427 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1428 div = period / 128;
1429 q = div_u64_rem(78125ULL * bit_err, div, &r);
1430 *ber = (r >= div / 2) ? q + 1 : q;
1431 return 0;
1432}
1433
1434static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1435{
1436 u8 data[3];
1437 u32 res = 0, value;
1438 int min_index, max_index, index;
1439 static const struct cxd2841er_cnr_data *cn_data;
1440
1441 /* Set SLV-T Bank : 0xA1 */
1442 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1443 /*
1444 * slave Bank Addr Bit Signal name
1445 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1446 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1447 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1448 */
1449 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1450 if (data[0] & 0x01) {
1451 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1452 min_index = 0;
1453 if (delsys == SYS_DVBS) {
1454 cn_data = s_cn_data;
1455 max_index = sizeof(s_cn_data) /
1456 sizeof(s_cn_data[0]) - 1;
1457 } else {
1458 cn_data = s2_cn_data;
1459 max_index = sizeof(s2_cn_data) /
1460 sizeof(s2_cn_data[0]) - 1;
1461 }
1462 if (value >= cn_data[min_index].value) {
1463 res = cn_data[min_index].cnr_x1000;
1464 goto done;
1465 }
1466 if (value <= cn_data[max_index].value) {
1467 res = cn_data[max_index].cnr_x1000;
1468 goto done;
1469 }
1470 while ((max_index - min_index) > 1) {
1471 index = (max_index + min_index) / 2;
1472 if (value == cn_data[index].value) {
1473 res = cn_data[index].cnr_x1000;
1474 goto done;
1475 } else if (value > cn_data[index].value)
1476 max_index = index;
1477 else
1478 min_index = index;
1479 if ((max_index - min_index) <= 1) {
1480 if (value == cn_data[max_index].value) {
1481 res = cn_data[max_index].cnr_x1000;
1482 goto done;
1483 } else {
1484 res = cn_data[min_index].cnr_x1000;
1485 goto done;
1486 }
1487 }
1488 }
1489 } else {
1490 dev_dbg(&priv->i2c->dev,
1491 "%s(): no data available\n", __func__);
1492 }
1493done:
1494 return res;
1495}
1496
1497static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1498{
1499 u32 reg;
1500 u8 data[2];
1501
1502 *snr = 0;
1503 if (priv->state != STATE_ACTIVE_TC) {
1504 dev_dbg(&priv->i2c->dev,
1505 "%s(): invalid state %d\n", __func__, priv->state);
1506 return -EINVAL;
1507 }
1508 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1509 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1510 reg = ((u32)data[0] << 8) | (u32)data[1];
1511 if (reg == 0) {
1512 dev_dbg(&priv->i2c->dev,
1513 "%s(): reg value out of range\n", __func__);
1514 return 0;
1515 }
1516 if (reg > 4996)
1517 reg = 4996;
1518 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1519 return 0;
1520}
1521
c8946c8d 1522static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
a6dc60ff
KS		 1523{
1524 u32 reg;
1525 u8 data[2];
1526
1527 *snr = 0;
1528 if (priv->state != STATE_ACTIVE_TC) {
1529 dev_dbg(&priv->i2c->dev,
1530 "%s(): invalid state %d\n", __func__, priv->state);
1531 return -EINVAL;
1532 }
1533 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1534 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1535 reg = ((u32)data[0] << 8) | (u32)data[1];
1536 if (reg == 0) {
1537 dev_dbg(&priv->i2c->dev,
1538 "%s(): reg value out of range\n", __func__);
1539 return 0;
1540 }
1541 if (reg > 10876)
1542 reg = 10876;
1543 *snr = 10000 * ((intlog10(reg) -
1544 intlog10(12600 - reg)) >> 24) + 32000;
1545 return 0;
1546}
1547
83808c23
AO		 1548static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1549{
1550 u32 reg;
1551 u8 data[2];
1552
1553 *snr = 0;
1554 if (priv->state != STATE_ACTIVE_TC) {
1555 dev_dbg(&priv->i2c->dev,
1556 "%s(): invalid state %d\n", __func__,
1557 priv->state);
1558 return -EINVAL;
1559 }
1560
1561 /* Freeze all registers */
1562 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1563
1564
1565 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1566 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1567 reg = ((u32)data[0] << 8) | (u32)data[1];
1568 if (reg == 0) {
1569 dev_dbg(&priv->i2c->dev,
1570 "%s(): reg value out of range\n", __func__);
1571 return 0;
1572 }
1573 if (reg > 4996)
1574 reg = 4996;
1575 *snr = 100 * intlog10(reg) - 9031;
1576 return 0;
1577}
1578
a6dc60ff
KS		 1579static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1580 u8 delsys)
1581{
1582 u8 data[2];
1583
1584 cxd2841er_write_reg(
1585 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1586 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
c5ea46da
AO		 1587 dev_dbg(&priv->i2c->dev,
1588 "%s(): AGC value=%u\n",
1589 __func__, (((u16)data[0] & 0x0F) << 8) |
1590 (u16)(data[1] & 0xFF));
a6dc60ff
KS		 1591 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1592}
1593
83808c23
AO		 1594static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1595 u8 delsys)
1596{
1597 u8 data[2];
1598
1599 cxd2841er_write_reg(
1600 priv, I2C_SLVT, 0x00, 0x60);
1601 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1602
1603 dev_dbg(&priv->i2c->dev,
1604 "%s(): AGC value=%u\n",
1605 __func__, (((u16)data[0] & 0x0F) << 8) |
1606 (u16)(data[1] & 0xFF));
1607 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1608}
1609
a6dc60ff
KS		 1610static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1611{
1612 u8 data[2];
1613
1614 /* Set SLV-T Bank : 0xA0 */
1615 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1616 /*
1617 * slave Bank Addr Bit Signal name
1618 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1619 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1620 */
1621 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1622 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1623}
1624
1625static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1626{
1627 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1628 struct cxd2841er_priv *priv = fe->demodulator_priv;
1629
1630 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1631 *ber = 0;
1632 switch (p->delivery_system) {
1633 case SYS_DVBS:
1634 *ber = cxd2841er_mon_read_ber_s(priv);
1635 break;
1636 case SYS_DVBS2:
1637 *ber = cxd2841er_mon_read_ber_s2(priv);
1638 break;
1639 case SYS_DVBT:
1640 return cxd2841er_read_ber_t(priv, ber);
1641 case SYS_DVBT2:
1642 return cxd2841er_read_ber_t2(priv, ber);
1643 default:
1644 *ber = 0;
1645 break;
1646 }
1647 return 0;
1648}
1649
1650static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1651 u16 *strength)
1652{
1653 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1654 struct cxd2841er_priv *priv = fe->demodulator_priv;
1655
1656 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1657 switch (p->delivery_system) {
1658 case SYS_DVBT:
1659 case SYS_DVBT2:
1660 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1661 priv, p->delivery_system);
1662 break;
83808c23
AO		 1663 case SYS_ISDBT:
1664 *strength = 65535 - cxd2841er_read_agc_gain_i(
1665 priv, p->delivery_system);
1666 break;
a6dc60ff
KS		 1667 case SYS_DVBS:
1668 case SYS_DVBS2:
1669 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1670 break;
1671 default:
1672 *strength = 0;
1673 break;
1674 }
1675 return 0;
1676}
1677
1678static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1679{
1680 u32 tmp = 0;
1681 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1682 struct cxd2841er_priv *priv = fe->demodulator_priv;
1683
1684 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1685 switch (p->delivery_system) {
1686 case SYS_DVBT:
1687 cxd2841er_read_snr_t(priv, &tmp);
1688 break;
1689 case SYS_DVBT2:
1690 cxd2841er_read_snr_t2(priv, &tmp);
1691 break;
83808c23
AO		 1692 case SYS_ISDBT:
1693 cxd2841er_read_snr_i(priv, &tmp);
1694 break;
a6dc60ff
KS		 1695 case SYS_DVBS:
1696 case SYS_DVBS2:
1697 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1698 break;
1699 default:
1700 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1701 __func__, p->delivery_system);
1702 break;
1703 }
1704 *snr = tmp & 0xffff;
1705 return 0;
1706}
1707
1708static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1709{
1710 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1711 struct cxd2841er_priv *priv = fe->demodulator_priv;
1712
1713 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1714 switch (p->delivery_system) {
1715 case SYS_DVBT:
1716 cxd2841er_read_packet_errors_t(priv, ucblocks);
1717 break;
1718 case SYS_DVBT2:
1719 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1720 break;
83808c23
AO		 1721 case SYS_ISDBT:
1722 cxd2841er_read_packet_errors_i(priv, ucblocks);
1723 break;
a6dc60ff
KS		 1724 default:
1725 *ucblocks = 0;
1726 break;
1727 }
1728 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1729 return 0;
1730}
1731
1732static int cxd2841er_dvbt2_set_profile(
1733 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1734{
1735 u8 tune_mode;
1736 u8 seq_not2d_time;
1737
1738 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1739 switch (profile) {
1740 case DVBT2_PROFILE_BASE:
1741 tune_mode = 0x01;
1742 seq_not2d_time = 12;
1743 break;
1744 case DVBT2_PROFILE_LITE:
1745 tune_mode = 0x05;
1746 seq_not2d_time = 40;
1747 break;
1748 case DVBT2_PROFILE_ANY:
1749 tune_mode = 0x00;
1750 seq_not2d_time = 40;
1751 break;
1752 default:
1753 return -EINVAL;
1754 }
1755 /* Set SLV-T Bank : 0x2E */
1756 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1757 /* Set profile and tune mode */
1758 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1759 /* Set SLV-T Bank : 0x2B */
1760 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1761 /* Set early unlock detection time */
1762 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1763 return 0;
1764}
1765
1766static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1767 u8 is_auto, u8 plp_id)
1768{
1769 if (is_auto) {
1770 dev_dbg(&priv->i2c->dev,
1771 "%s() using auto PLP selection\n", __func__);
1772 } else {
1773 dev_dbg(&priv->i2c->dev,
1774 "%s() using manual PLP selection, ID %d\n",
1775 __func__, plp_id);
1776 }
1777 /* Set SLV-T Bank : 0x23 */
1778 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1779 if (!is_auto) {
1780 /* Manual PLP selection mode. Set the data PLP Id. */
1781 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1782 }
1783 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1784 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1785 return 0;
1786}
1787
1788static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1789 u32 bandwidth)
1790{
1791 u32 iffreq;
1792 u8 b20_9f[5];
1793 u8 b10_a6[14];
1794 u8 b10_b6[3];
1795 u8 b10_d7;
1796
1797 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1798 switch (bandwidth) {
1799 case 8000000:
1800 /* bank 0x20, reg 0x9f */
1801 b20_9f[0] = 0x11;
1802 b20_9f[1] = 0xf0;
1803 b20_9f[2] = 0x00;
1804 b20_9f[3] = 0x00;
1805 b20_9f[4] = 0x00;
1806 /* bank 0x10, reg 0xa6 */
1807 b10_a6[0] = 0x26;
1808 b10_a6[1] = 0xaf;
1809 b10_a6[2] = 0x06;
1810 b10_a6[3] = 0xcd;
1811 b10_a6[4] = 0x13;
1812 b10_a6[5] = 0xbb;
1813 b10_a6[6] = 0x28;
1814 b10_a6[7] = 0xba;
1815 b10_a6[8] = 0x23;
1816 b10_a6[9] = 0xa9;
1817 b10_a6[10] = 0x1f;
1818 b10_a6[11] = 0xa8;
1819 b10_a6[12] = 0x2c;
1820 b10_a6[13] = 0xc8;
1821 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1822 b10_d7 = 0x00;
1823 break;
1824 case 7000000:
1825 /* bank 0x20, reg 0x9f */
1826 b20_9f[0] = 0x14;
1827 b20_9f[1] = 0x80;
1828 b20_9f[2] = 0x00;
1829 b20_9f[3] = 0x00;
1830 b20_9f[4] = 0x00;
1831 /* bank 0x10, reg 0xa6 */
1832 b10_a6[0] = 0x2C;
1833 b10_a6[1] = 0xBD;
1834 b10_a6[2] = 0x02;
1835 b10_a6[3] = 0xCF;
1836 b10_a6[4] = 0x04;
1837 b10_a6[5] = 0xF8;
1838 b10_a6[6] = 0x23;
1839 b10_a6[7] = 0xA6;
1840 b10_a6[8] = 0x29;
1841 b10_a6[9] = 0xB0;
1842 b10_a6[10] = 0x26;
1843 b10_a6[11] = 0xA9;
1844 b10_a6[12] = 0x21;
1845 b10_a6[13] = 0xA5;
1846 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1847 b10_d7 = 0x02;
1848 break;
1849 case 6000000:
1850 /* bank 0x20, reg 0x9f */
1851 b20_9f[0] = 0x17;
1852 b20_9f[1] = 0xEA;
1853 b20_9f[2] = 0xAA;
1854 b20_9f[3] = 0xAA;
1855 b20_9f[4] = 0xAA;
1856 /* bank 0x10, reg 0xa6 */
1857 b10_a6[0] = 0x27;
1858 b10_a6[1] = 0xA7;
1859 b10_a6[2] = 0x28;
1860 b10_a6[3] = 0xB3;
1861 b10_a6[4] = 0x02;
1862 b10_a6[5] = 0xF0;
1863 b10_a6[6] = 0x01;
1864 b10_a6[7] = 0xE8;
1865 b10_a6[8] = 0x00;
1866 b10_a6[9] = 0xCF;
1867 b10_a6[10] = 0x00;
1868 b10_a6[11] = 0xE6;
1869 b10_a6[12] = 0x23;
1870 b10_a6[13] = 0xA4;
1871 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1872 b10_d7 = 0x04;
1873 break;
1874 case 5000000:
1875 /* bank 0x20, reg 0x9f */
1876 b20_9f[0] = 0x1C;
1877 b20_9f[1] = 0xB3;
1878 b20_9f[2] = 0x33;
1879 b20_9f[3] = 0x33;
1880 b20_9f[4] = 0x33;
1881 /* bank 0x10, reg 0xa6 */
1882 b10_a6[0] = 0x27;
1883 b10_a6[1] = 0xA7;
1884 b10_a6[2] = 0x28;
1885 b10_a6[3] = 0xB3;
1886 b10_a6[4] = 0x02;
1887 b10_a6[5] = 0xF0;
1888 b10_a6[6] = 0x01;
1889 b10_a6[7] = 0xE8;
1890 b10_a6[8] = 0x00;
1891 b10_a6[9] = 0xCF;
1892 b10_a6[10] = 0x00;
1893 b10_a6[11] = 0xE6;
1894 b10_a6[12] = 0x23;
1895 b10_a6[13] = 0xA4;
1896 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1897 b10_d7 = 0x06;
1898 break;
1899 case 1712000:
1900 /* bank 0x20, reg 0x9f */
1901 b20_9f[0] = 0x58;
1902 b20_9f[1] = 0xE2;
1903 b20_9f[2] = 0xAF;
1904 b20_9f[3] = 0xE0;
1905 b20_9f[4] = 0xBC;
1906 /* bank 0x10, reg 0xa6 */
1907 b10_a6[0] = 0x25;
1908 b10_a6[1] = 0xA0;
1909 b10_a6[2] = 0x36;
1910 b10_a6[3] = 0x8D;
1911 b10_a6[4] = 0x2E;
1912 b10_a6[5] = 0x94;
1913 b10_a6[6] = 0x28;
1914 b10_a6[7] = 0x9B;
1915 b10_a6[8] = 0x32;
1916 b10_a6[9] = 0x90;
1917 b10_a6[10] = 0x2C;
1918 b10_a6[11] = 0x9D;
1919 b10_a6[12] = 0x29;
1920 b10_a6[13] = 0x99;
1921 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1922 b10_d7 = 0x03;
1923 break;
1924 default:
1925 return -EINVAL;
1926 }
1927 /* Set SLV-T Bank : 0x20 */
1928 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1929 cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1930 /* Set SLV-T Bank : 0x27 */
1931 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1932 cxd2841er_set_reg_bits(
1933 priv, I2C_SLVT, 0x7a,
1934 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1935 /* Set SLV-T Bank : 0x10 */
1936 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1937 /* Group delay equaliser sett. for ASCOT2E */
1938 cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
1939 /* <IF freq setting> */
1940 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1941 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1942 b10_b6[2] = (u8)(iffreq & 0xff);
1943 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1944 /* System bandwidth setting */
1945 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
1946 return 0;
1947}
1948
1949static int cxd2841er_sleep_tc_to_active_t_band(
1950 struct cxd2841er_priv *priv, u32 bandwidth)
1951{
83808c23 1952 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff 1953 u32 iffreq;
83808c23
AO		 1954 u8 nominalRate8bw[3][5] = {
1955 /* TRCG Nominal Rate [37:0] */
1956 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1957 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1958 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1959 };
1960 u8 nominalRate7bw[3][5] = {
1961 /* TRCG Nominal Rate [37:0] */
1962 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1963 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1964 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1965 };
1966 u8 nominalRate6bw[3][5] = {
1967 /* TRCG Nominal Rate [37:0] */
1968 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1969 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1970 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1971 };
1972 u8 nominalRate5bw[3][5] = {
1973 /* TRCG Nominal Rate [37:0] */
1974 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1975 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1976 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1977 };
a6dc60ff 1978
83808c23
AO		 1979 u8 itbCoef8bw[3][14] = {
1980 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1981 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1982 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
1983 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1984 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
1985 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1986 };
1987 u8 itbCoef7bw[3][14] = {
1988 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1989 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1990 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
1991 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1992 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
1993 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1994 };
1995 u8 itbCoef6bw[3][14] = {
1996 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
1997 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1998 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
1999 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2000 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2001 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2002 };
2003 u8 itbCoef5bw[3][14] = {
2004 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2005 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2006 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2007 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2008 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2009 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2010 };
2011
2012 /* Set SLV-T Bank : 0x13 */
a6dc60ff
KS		 2013 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2014 /* Echo performance optimization setting */
83808c23
AO		 2015 data[0] = 0x01;
2016 data[1] = 0x14;
2017 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2018
2019 /* Set SLV-T Bank : 0x10 */
a6dc60ff
KS		 2020 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2021
2022 switch (bandwidth) {
2023 case 8000000:
83808c23
AO		 2024 /* <Timing Recovery setting> */
2025 cxd2841er_write_regs(priv, I2C_SLVT,
2026 0x9F, nominalRate8bw[priv->xtal], 5);
2027 /* Group delay equaliser settings for
2028 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2029 */
2030 cxd2841er_write_regs(priv, I2C_SLVT,
2031 0xA6, itbCoef8bw[priv->xtal], 14);
2032 /* <IF freq setting> */
2033 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2034 data[0] = (u8) ((iffreq >> 16) & 0xff);
2035 data[1] = (u8)((iffreq >> 8) & 0xff);
2036 data[2] = (u8)(iffreq & 0xff);
2037 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2038 /* System bandwidth setting */
2039 cxd2841er_set_reg_bits(
2040 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2041
2042 /* Demod core latency setting */
2043 if (priv->xtal == SONY_XTAL_24000) {
2044 data[0] = 0x15;
2045 data[1] = 0x28;
2046 } else {
2047 data[0] = 0x01;
2048 data[1] = 0xE0;
2049 }
2050 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2051
2052 /* Notch filter setting */
2053 data[0] = 0x01;
2054 data[1] = 0x02;
2055 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2056 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2057 break;
2058 case 7000000:
83808c23
AO		 2059 /* <Timing Recovery setting> */
2060 cxd2841er_write_regs(priv, I2C_SLVT,
2061 0x9F, nominalRate7bw[priv->xtal], 5);
2062 /* Group delay equaliser settings for
2063 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2064 */
2065 cxd2841er_write_regs(priv, I2C_SLVT,
2066 0xA6, itbCoef7bw[priv->xtal], 14);
2067 /* <IF freq setting> */
2068 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2069 data[0] = (u8) ((iffreq >> 16) & 0xff);
2070 data[1] = (u8)((iffreq >> 8) & 0xff);
2071 data[2] = (u8)(iffreq & 0xff);
2072 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2073 /* System bandwidth setting */
2074 cxd2841er_set_reg_bits(
2075 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2076
2077 /* Demod core latency setting */
2078 if (priv->xtal == SONY_XTAL_24000) {
2079 data[0] = 0x1F;
2080 data[1] = 0xF8;
2081 } else {
2082 data[0] = 0x12;
2083 data[1] = 0xF8;
2084 }
2085 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2086
2087 /* Notch filter setting */
2088 data[0] = 0x00;
2089 data[1] = 0x03;
2090 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2091 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2092 break;
2093 case 6000000:
83808c23
AO		 2094 /* <Timing Recovery setting> */
2095 cxd2841er_write_regs(priv, I2C_SLVT,
2096 0x9F, nominalRate6bw[priv->xtal], 5);
2097 /* Group delay equaliser settings for
2098 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2099 */
2100 cxd2841er_write_regs(priv, I2C_SLVT,
2101 0xA6, itbCoef6bw[priv->xtal], 14);
2102 /* <IF freq setting> */
2103 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2104 data[0] = (u8) ((iffreq >> 16) & 0xff);
2105 data[1] = (u8)((iffreq >> 8) & 0xff);
2106 data[2] = (u8)(iffreq & 0xff);
2107 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2108 /* System bandwidth setting */
2109 cxd2841er_set_reg_bits(
2110 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2111
2112 /* Demod core latency setting */
2113 if (priv->xtal == SONY_XTAL_24000) {
2114 data[0] = 0x25;
2115 data[1] = 0x4C;
2116 } else {
2117 data[0] = 0x1F;
2118 data[1] = 0xDC;
2119 }
2120 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2121
2122 /* Notch filter setting */
2123 data[0] = 0x00;
2124 data[1] = 0x03;
2125 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2126 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2127 break;
2128 case 5000000:
83808c23
AO		 2129 /* <Timing Recovery setting> */
2130 cxd2841er_write_regs(priv, I2C_SLVT,
2131 0x9F, nominalRate5bw[priv->xtal], 5);
2132 /* Group delay equaliser settings for
2133 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2134 */
2135 cxd2841er_write_regs(priv, I2C_SLVT,
2136 0xA6, itbCoef5bw[priv->xtal], 14);
2137 /* <IF freq setting> */
2138 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2139 data[0] = (u8) ((iffreq >> 16) & 0xff);
2140 data[1] = (u8)((iffreq >> 8) & 0xff);
2141 data[2] = (u8)(iffreq & 0xff);
2142 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2143 /* System bandwidth setting */
2144 cxd2841er_set_reg_bits(
2145 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2146
2147 /* Demod core latency setting */
2148 if (priv->xtal == SONY_XTAL_24000) {
2149 data[0] = 0x2C;
2150 data[1] = 0xC2;
2151 } else {
2152 data[0] = 0x26;
2153 data[1] = 0x3C;
2154 }
2155 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2156
2157 /* Notch filter setting */
2158 data[0] = 0x00;
2159 data[1] = 0x03;
2160 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2161 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2162 break;
2163 }
2164
2165 return 0;
2166}
2167
2168static int cxd2841er_sleep_tc_to_active_i_band(
2169 struct cxd2841er_priv *priv, u32 bandwidth)
2170{
2171 u32 iffreq;
2172 u8 data[3];
2173
2174 /* TRCG Nominal Rate */
2175 u8 nominalRate8bw[3][5] = {
2176 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2177 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2178 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2179 };
2180
2181 u8 nominalRate7bw[3][5] = {
2182 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2183 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2184 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2185 };
2186
2187 u8 nominalRate6bw[3][5] = {
2188 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2189 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2190 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2191 };
2192
2193 u8 itbCoef8bw[3][14] = {
2194 {0x00}, /* 20.5MHz XTal */
2195 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2196 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2197 {0x0}, /* 41MHz XTal */
2198 };
2199
2200 u8 itbCoef7bw[3][14] = {
2201 {0x00}, /* 20.5MHz XTal */
2202 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2203 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2204 {0x00}, /* 41MHz XTal */
2205 };
2206
2207 u8 itbCoef6bw[3][14] = {
2208 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2209 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2210 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2211 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2212 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2213 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2214 };
2215
2216 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2217 /* Set SLV-T Bank : 0x10 */
2218 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2219
2220 /* 20.5/41MHz Xtal support is not available
2221 * on ISDB-T 7MHzBW and 8MHzBW
2222 */
2223 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2224 dev_err(&priv->i2c->dev,
2225 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2226 __func__, bandwidth);
2227 return -EINVAL;
2228 }
2229
2230 switch (bandwidth) {
2231 case 8000000:
2232 /* TRCG Nominal Rate */
2233 cxd2841er_write_regs(priv, I2C_SLVT,
2234 0x9F, nominalRate8bw[priv->xtal], 5);
2235 /* Group delay equaliser settings for ASCOT tuners optimized */
2236 cxd2841er_write_regs(priv, I2C_SLVT,
2237 0xA6, itbCoef8bw[priv->xtal], 14);
2238
2239 /* IF freq setting */
2240 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2241 data[0] = (u8) ((iffreq >> 16) & 0xff);
2242 data[1] = (u8)((iffreq >> 8) & 0xff);
2243 data[2] = (u8)(iffreq & 0xff);
2244 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2245
2246 /* System bandwidth setting */
2247 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2248
2249 /* Demod core latency setting */
2250 data[0] = 0x13;
2251 data[1] = 0xFC;
2252 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2253
2254 /* Acquisition optimization setting */
2255 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2256 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2257 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2258 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2259 break;
2260 case 7000000:
2261 /* TRCG Nominal Rate */
2262 cxd2841er_write_regs(priv, I2C_SLVT,
2263 0x9F, nominalRate7bw[priv->xtal], 5);
2264 /* Group delay equaliser settings for ASCOT tuners optimized */
2265 cxd2841er_write_regs(priv, I2C_SLVT,
2266 0xA6, itbCoef7bw[priv->xtal], 14);
2267
2268 /* IF freq setting */
2269 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2270 data[0] = (u8) ((iffreq >> 16) & 0xff);
2271 data[1] = (u8)((iffreq >> 8) & 0xff);
2272 data[2] = (u8)(iffreq & 0xff);
2273 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2274
2275 /* System bandwidth setting */
2276 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2277
2278 /* Demod core latency setting */
2279 data[0] = 0x1A;
2280 data[1] = 0xFA;
2281 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2282
2283 /* Acquisition optimization setting */
2284 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2285 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2286 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2287 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2288 break;
2289 case 6000000:
2290 /* TRCG Nominal Rate */
2291 cxd2841er_write_regs(priv, I2C_SLVT,
2292 0x9F, nominalRate6bw[priv->xtal], 5);
2293 /* Group delay equaliser settings for ASCOT tuners optimized */
2294 cxd2841er_write_regs(priv, I2C_SLVT,
2295 0xA6, itbCoef6bw[priv->xtal], 14);
2296
2297 /* IF freq setting */
2298 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2299 data[0] = (u8) ((iffreq >> 16) & 0xff);
2300 data[1] = (u8)((iffreq >> 8) & 0xff);
2301 data[2] = (u8)(iffreq & 0xff);
2302 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2303
2304 /* System bandwidth setting */
2305 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2306
2307 /* Demod core latency setting */
2308 if (priv->xtal == SONY_XTAL_24000) {
2309 data[0] = 0x1F;
2310 data[1] = 0x79;
2311 } else {
2312 data[0] = 0x1A;
2313 data[1] = 0xE2;
2314 }
2315 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2316
2317 /* Acquisition optimization setting */
2318 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2319 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2320 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2321 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
a6dc60ff
KS		 2322 break;
2323 default:
2324 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
83808c23 2325 __func__, bandwidth);
a6dc60ff
KS		 2326 return -EINVAL;
2327 }
a6dc60ff
KS		 2328 return 0;
2329}
2330
2331static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2332 u32 bandwidth)
2333{
2334 u8 bw7_8mhz_b10_a6[] = {
2335 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2336 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2337 u8 bw6mhz_b10_a6[] = {
2338 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2339 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2340 u8 b10_b6[3];
2341 u32 iffreq;
2342
2343 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2344 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2345 switch (bandwidth) {
2346 case 8000000:
2347 case 7000000:
2348 cxd2841er_write_regs(
2349 priv, I2C_SLVT, 0xa6,
2350 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2351 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2352 break;
2353 case 6000000:
2354 cxd2841er_write_regs(
2355 priv, I2C_SLVT, 0xa6,
2356 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2357 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2358 break;
2359 default:
2360 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2361 __func__, bandwidth);
2362 return -EINVAL;
2363 }
2364 /* <IF freq setting> */
2365 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2366 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2367 b10_b6[2] = (u8)(iffreq & 0xff);
2368 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2369 /* Set SLV-T Bank : 0x11 */
2370 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2371 switch (bandwidth) {
2372 case 8000000:
2373 case 7000000:
2374 cxd2841er_set_reg_bits(
2375 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2376 break;
2377 case 6000000:
2378 cxd2841er_set_reg_bits(
2379 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2380 break;
2381 }
2382 /* Set SLV-T Bank : 0x40 */
2383 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2384 switch (bandwidth) {
2385 case 8000000:
2386 cxd2841er_set_reg_bits(
2387 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2388 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2389 break;
2390 case 7000000:
2391 cxd2841er_set_reg_bits(
2392 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2393 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2394 break;
2395 case 6000000:
2396 cxd2841er_set_reg_bits(
2397 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2398 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2399 break;
2400 }
2401 return 0;
2402}
2403
2404static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2405 u32 bandwidth)
2406{
2407 u8 data[2] = { 0x09, 0x54 };
83808c23 2408 u8 data24m[3] = {0xDC, 0x6C, 0x00};
a6dc60ff
KS		 2409
2410 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2411 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2412 /* Set SLV-X Bank : 0x00 */
2413 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2414 /* Set demod mode */
2415 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2416 /* Set SLV-T Bank : 0x00 */
2417 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2418 /* Enable demod clock */
2419 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2420 /* Disable RF level monitor */
2421 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2422 /* Enable ADC clock */
2423 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2424 /* Enable ADC 1 */
2425 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
83808c23
AO		 2426 /* Enable ADC 2 & 3 */
2427 if (priv->xtal == SONY_XTAL_41000) {
2428 data[0] = 0x0A;
2429 data[1] = 0xD4;
2430 }
a6dc60ff
KS		 2431 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2432 /* Enable ADC 4 */
2433 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2434 /* Set SLV-T Bank : 0x10 */
2435 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2436 /* IFAGC gain settings */
2437 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2438 /* Set SLV-T Bank : 0x11 */
2439 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2440 /* BBAGC TARGET level setting */
2441 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2442 /* Set SLV-T Bank : 0x10 */
2443 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2444 /* ASCOT setting ON */
2445 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2446 /* Set SLV-T Bank : 0x18 */
2447 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2448 /* Pre-RS BER moniter setting */
2449 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2450 /* FEC Auto Recovery setting */
2451 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2452 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2453 /* Set SLV-T Bank : 0x00 */
2454 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2455 /* TSIF setting */
2456 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2457 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
83808c23
AO		 2458
2459 if (priv->xtal == SONY_XTAL_24000) {
2460 /* Set SLV-T Bank : 0x10 */
2461 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2462 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2463 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2464 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2465 }
2466
a6dc60ff
KS		 2467 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2468 /* Set SLV-T Bank : 0x00 */
2469 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2470 /* Disable HiZ Setting 1 */
2471 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2472 /* Disable HiZ Setting 2 */
2473 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2474 priv->state = STATE_ACTIVE_TC;
2475 return 0;
2476}
2477
2478static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2479 u32 bandwidth)
2480{
2481 u8 data[2] = { 0x09, 0x54 };
2482
2483 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2484 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2485 /* Set SLV-X Bank : 0x00 */
2486 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2487 /* Set demod mode */
2488 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2489 /* Set SLV-T Bank : 0x00 */
2490 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2491 /* Enable demod clock */
2492 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2493 /* Disable RF level monitor */
2494 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2495 /* Enable ADC clock */
2496 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2497 /* Enable ADC 1 */
2498 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2499 /* xtal freq 20.5MHz */
2500 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2501 /* Enable ADC 4 */
2502 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2503 /* Set SLV-T Bank : 0x10 */
2504 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2505 /* IFAGC gain settings */
2506 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2507 /* Set SLV-T Bank : 0x11 */
2508 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2509 /* BBAGC TARGET level setting */
2510 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2511 /* Set SLV-T Bank : 0x10 */
2512 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2513 /* ASCOT setting ON */
2514 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2515 /* Set SLV-T Bank : 0x20 */
2516 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2517 /* Acquisition optimization setting */
2518 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2519 /* Set SLV-T Bank : 0x2b */
2520 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2521 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2522 /* Set SLV-T Bank : 0x00 */
2523 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2524 /* TSIF setting */
2525 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2526 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2527 /* DVB-T2 initial setting */
2528 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2529 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2530 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2531 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2532 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2533 /* Set SLV-T Bank : 0x2a */
2534 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2535 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2536 /* Set SLV-T Bank : 0x2b */
2537 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2538 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2539
2540 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2541
2542 /* Set SLV-T Bank : 0x00 */
2543 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2544 /* Disable HiZ Setting 1 */
2545 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2546 /* Disable HiZ Setting 2 */
2547 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2548 priv->state = STATE_ACTIVE_TC;
2549 return 0;
2550}
2551
83808c23
AO		 2552/* ISDB-Tb part */
2553static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2554 u32 bandwidth)
2555{
2556 u8 data[2] = { 0x09, 0x54 };
2557 u8 data24m[2] = {0x60, 0x00};
2558 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2559
2560 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2561 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2562 /* Set SLV-X Bank : 0x00 */
2563 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2564 /* Set demod mode */
2565 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2566 /* Set SLV-T Bank : 0x00 */
2567 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2568 /* Enable demod clock */
2569 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2570 /* Enable RF level monitor */
2571 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2572 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2573 /* Enable ADC clock */
2574 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2575 /* Enable ADC 1 */
2576 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2577 /* xtal freq 20.5MHz or 24M */
2578 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2579 /* Enable ADC 4 */
2580 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2581 /* ASCOT setting ON */
2582 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2583 /* FEC Auto Recovery setting */
2584 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2585 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2586 /* ISDB-T initial setting */
2587 /* Set SLV-T Bank : 0x00 */
2588 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2589 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2590 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2591 /* Set SLV-T Bank : 0x10 */
2592 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2593 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2594 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2595 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2596 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2597 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2598 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2599 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2600 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2601 /* Set SLV-T Bank : 0x15 */
2602 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2603 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2604 /* Set SLV-T Bank : 0x1E */
2605 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2606 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2607 /* Set SLV-T Bank : 0x63 */
2608 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2609 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2610
2611 /* for xtal 24MHz */
2612 /* Set SLV-T Bank : 0x10 */
2613 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2614 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2615 /* Set SLV-T Bank : 0x60 */
2616 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2617 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2618
2619 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2620 /* Set SLV-T Bank : 0x00 */
2621 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2622 /* Disable HiZ Setting 1 */
2623 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2624 /* Disable HiZ Setting 2 */
2625 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2626 priv->state = STATE_ACTIVE_TC;
2627 return 0;
2628}
2629
a6dc60ff
KS		 2630static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2631 u32 bandwidth)
2632{
2633 u8 data[2] = { 0x09, 0x54 };
2634
2635 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2636 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2637 /* Set SLV-X Bank : 0x00 */
2638 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2639 /* Set demod mode */
2640 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2641 /* Set SLV-T Bank : 0x00 */
2642 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2643 /* Enable demod clock */
2644 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2645 /* Disable RF level monitor */
2646 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2647 /* Enable ADC clock */
2648 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2649 /* Enable ADC 1 */
2650 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2651 /* xtal freq 20.5MHz */
2652 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2653 /* Enable ADC 4 */
2654 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2655 /* Set SLV-T Bank : 0x10 */
2656 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2657 /* IFAGC gain settings */
2658 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2659 /* Set SLV-T Bank : 0x11 */
2660 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2661 /* BBAGC TARGET level setting */
2662 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2663 /* Set SLV-T Bank : 0x10 */
2664 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2665 /* ASCOT setting ON */
2666 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2667 /* Set SLV-T Bank : 0x40 */
2668 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2669 /* Demod setting */
2670 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2671 /* Set SLV-T Bank : 0x00 */
2672 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2673 /* TSIF setting */
2674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2675 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2676
2677 cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2678 /* Set SLV-T Bank : 0x00 */
2679 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2680 /* Disable HiZ Setting 1 */
2681 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2682 /* Disable HiZ Setting 2 */
2683 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2684 priv->state = STATE_ACTIVE_TC;
2685 return 0;
2686}
2687
7e3e68bc
MCC		 2688static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2689 struct dtv_frontend_properties *p)
a6dc60ff
KS		 2690{
2691 enum fe_status status = 0;
2692 u16 strength = 0, snr = 0;
2693 u32 errors = 0, ber = 0;
2694 struct cxd2841er_priv *priv = fe->demodulator_priv;
a6dc60ff
KS		 2695
2696 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2697 if (priv->state == STATE_ACTIVE_S)
2698 cxd2841er_read_status_s(fe, &status);
2699 else if (priv->state == STATE_ACTIVE_TC)
2700 cxd2841er_read_status_tc(fe, &status);
2701
2702 if (status & FE_HAS_LOCK) {
2703 cxd2841er_read_signal_strength(fe, &strength);
2704 p->strength.len = 1;
2705 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2706 p->strength.stat[0].uvalue = strength;
2707 cxd2841er_read_snr(fe, &snr);
2708 p->cnr.len = 1;
2709 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2710 p->cnr.stat[0].svalue = snr;
2711 cxd2841er_read_ucblocks(fe, &errors);
2712 p->block_error.len = 1;
2713 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2714 p->block_error.stat[0].uvalue = errors;
2715 cxd2841er_read_ber(fe, &ber);
2716 p->post_bit_error.len = 1;
2717 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2718 p->post_bit_error.stat[0].uvalue = ber;
2719 } else {
2720 p->strength.len = 1;
2721 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2722 p->cnr.len = 1;
2723 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2724 p->block_error.len = 1;
2725 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2726 p->post_bit_error.len = 1;
2727 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2728 }
2729 return 0;
2730}
2731
2732static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2733{
2734 int ret = 0, i, timeout, carr_offset;
2735 enum fe_status status;
2736 struct cxd2841er_priv *priv = fe->demodulator_priv;
2737 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2738 u32 symbol_rate = p->symbol_rate/1000;
2739
83808c23 2740 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
a6dc60ff
KS		 2741 __func__,
2742 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
83808c23 2743 p->frequency, symbol_rate, priv->xtal);
a6dc60ff
KS		 2744 switch (priv->state) {
2745 case STATE_SLEEP_S:
2746 ret = cxd2841er_sleep_s_to_active_s(
2747 priv, p->delivery_system, symbol_rate);
2748 break;
2749 case STATE_ACTIVE_S:
2750 ret = cxd2841er_retune_active(priv, p);
2751 break;
2752 default:
2753 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2754 __func__, priv->state);
2755 ret = -EINVAL;
2756 goto done;
2757 }
2758 if (ret) {
2759 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2760 goto done;
2761 }
2762 if (fe->ops.i2c_gate_ctrl)
2763 fe->ops.i2c_gate_ctrl(fe, 1);
2764 if (fe->ops.tuner_ops.set_params)
2765 fe->ops.tuner_ops.set_params(fe);
2766 if (fe->ops.i2c_gate_ctrl)
2767 fe->ops.i2c_gate_ctrl(fe, 0);
2768 cxd2841er_tune_done(priv);
2769 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2770 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2771 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2772 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2773 cxd2841er_read_status_s(fe, &status);
2774 if (status & FE_HAS_LOCK)
2775 break;
2776 }
2777 if (status & FE_HAS_LOCK) {
2778 if (cxd2841er_get_carrier_offset_s_s2(
2779 priv, &carr_offset)) {
2780 ret = -EINVAL;
2781 goto done;
2782 }
2783 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2784 __func__, carr_offset);
2785 }
2786done:
2787 return ret;
2788}
2789
2790static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2791{
2792 int ret = 0, timeout;
2793 enum fe_status status;
2794 struct cxd2841er_priv *priv = fe->demodulator_priv;
2795 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2796
2797 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2798 if (p->delivery_system == SYS_DVBT) {
2799 priv->system = SYS_DVBT;
2800 switch (priv->state) {
2801 case STATE_SLEEP_TC:
2802 ret = cxd2841er_sleep_tc_to_active_t(
2803 priv, p->bandwidth_hz);
2804 break;
2805 case STATE_ACTIVE_TC:
2806 ret = cxd2841er_retune_active(priv, p);
2807 break;
2808 default:
2809 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2810 __func__, priv->state);
2811 ret = -EINVAL;
2812 }
2813 } else if (p->delivery_system == SYS_DVBT2) {
2814 priv->system = SYS_DVBT2;
2815 cxd2841er_dvbt2_set_plp_config(priv,
2816 (int)(p->stream_id > 255), p->stream_id);
2817 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2818 switch (priv->state) {
2819 case STATE_SLEEP_TC:
2820 ret = cxd2841er_sleep_tc_to_active_t2(priv,
2821 p->bandwidth_hz);
2822 break;
2823 case STATE_ACTIVE_TC:
2824 ret = cxd2841er_retune_active(priv, p);
2825 break;
2826 default:
2827 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2828 __func__, priv->state);
2829 ret = -EINVAL;
2830 }
83808c23
AO		 2831 } else if (p->delivery_system == SYS_ISDBT) {
2832 priv->system = SYS_ISDBT;
2833 switch (priv->state) {
2834 case STATE_SLEEP_TC:
2835 ret = cxd2841er_sleep_tc_to_active_i(
2836 priv, p->bandwidth_hz);
2837 break;
2838 case STATE_ACTIVE_TC:
2839 ret = cxd2841er_retune_active(priv, p);
2840 break;
2841 default:
2842 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2843 __func__, priv->state);
2844 ret = -EINVAL;
2845 }
a6dc60ff
KS		 2846 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2847 p->delivery_system == SYS_DVBC_ANNEX_C) {
2848 priv->system = SYS_DVBC_ANNEX_A;
2849 switch (priv->state) {
2850 case STATE_SLEEP_TC:
2851 ret = cxd2841er_sleep_tc_to_active_c(
2852 priv, p->bandwidth_hz);
2853 break;
2854 case STATE_ACTIVE_TC:
2855 ret = cxd2841er_retune_active(priv, p);
2856 break;
2857 default:
2858 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2859 __func__, priv->state);
2860 ret = -EINVAL;
2861 }
2862 } else {
2863 dev_dbg(&priv->i2c->dev,
2864 "%s(): invalid delivery system %d\n",
2865 __func__, p->delivery_system);
2866 ret = -EINVAL;
2867 }
2868 if (ret)
2869 goto done;
2870 if (fe->ops.i2c_gate_ctrl)
2871 fe->ops.i2c_gate_ctrl(fe, 1);
2872 if (fe->ops.tuner_ops.set_params)
2873 fe->ops.tuner_ops.set_params(fe);
2874 if (fe->ops.i2c_gate_ctrl)
2875 fe->ops.i2c_gate_ctrl(fe, 0);
2876 cxd2841er_tune_done(priv);
2877 timeout = 2500;
2878 while (timeout > 0) {
2879 ret = cxd2841er_read_status_tc(fe, &status);
2880 if (ret)
2881 goto done;
2882 if (status & FE_HAS_LOCK)
2883 break;
2884 msleep(20);
2885 timeout -= 20;
2886 }
2887 if (timeout < 0)
2888 dev_dbg(&priv->i2c->dev,
2889 "%s(): LOCK wait timeout\n", __func__);
2890done:
2891 return ret;
2892}
2893
2894static int cxd2841er_tune_s(struct dvb_frontend *fe,
2895 bool re_tune,
2896 unsigned int mode_flags,
2897 unsigned int *delay,
2898 enum fe_status *status)
2899{
2900 int ret, carrier_offset;
2901 struct cxd2841er_priv *priv = fe->demodulator_priv;
2902 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2903
2904 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2905 if (re_tune) {
2906 ret = cxd2841er_set_frontend_s(fe);
2907 if (ret)
2908 return ret;
2909 cxd2841er_read_status_s(fe, status);
2910 if (*status & FE_HAS_LOCK) {
2911 if (cxd2841er_get_carrier_offset_s_s2(
2912 priv, &carrier_offset))
2913 return -EINVAL;
2914 p->frequency += carrier_offset;
2915 ret = cxd2841er_set_frontend_s(fe);
2916 if (ret)
2917 return ret;
2918 }
2919 }
2920 *delay = HZ / 5;
2921 return cxd2841er_read_status_s(fe, status);
2922}
2923
2924static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2925 bool re_tune,
2926 unsigned int mode_flags,
2927 unsigned int *delay,
2928 enum fe_status *status)
2929{
2930 int ret, carrier_offset;
2931 struct cxd2841er_priv *priv = fe->demodulator_priv;
2932 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2933
2934 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2935 if (re_tune) {
2936 ret = cxd2841er_set_frontend_tc(fe);
2937 if (ret)
2938 return ret;
2939 cxd2841er_read_status_tc(fe, status);
2940 if (*status & FE_HAS_LOCK) {
2941 switch (priv->system) {
2942 case SYS_DVBT:
c5ea46da
AO		 2943 ret = cxd2841er_get_carrier_offset_t(
2944 priv, p->bandwidth_hz,
2945 &carrier_offset);
2946 break;
a6dc60ff
KS		 2947 case SYS_DVBT2:
2948 ret = cxd2841er_get_carrier_offset_t2(
2949 priv, p->bandwidth_hz,
2950 &carrier_offset);
2951 break;
2952 case SYS_DVBC_ANNEX_A:
2953 ret = cxd2841er_get_carrier_offset_c(
2954 priv, &carrier_offset);
2955 break;
2956 default:
2957 dev_dbg(&priv->i2c->dev,
2958 "%s(): invalid delivery system %d\n",
2959 __func__, priv->system);
2960 return -EINVAL;
2961 }
2962 if (ret)
2963 return ret;
2964 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
2965 __func__, carrier_offset);
2966 p->frequency += carrier_offset;
2967 ret = cxd2841er_set_frontend_tc(fe);
2968 if (ret)
2969 return ret;
2970 }
2971 }
2972 *delay = HZ / 5;
2973 return cxd2841er_read_status_tc(fe, status);
2974}
2975
2976static int cxd2841er_sleep_s(struct dvb_frontend *fe)
2977{
2978 struct cxd2841er_priv *priv = fe->demodulator_priv;
2979
2980 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2981 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
2982 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
2983 return 0;
2984}
2985
2986static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
2987{
2988 struct cxd2841er_priv *priv = fe->demodulator_priv;
2989
2990 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2991 if (priv->state == STATE_ACTIVE_TC) {
2992 switch (priv->system) {
2993 case SYS_DVBT:
2994 cxd2841er_active_t_to_sleep_tc(priv);
2995 break;
2996 case SYS_DVBT2:
2997 cxd2841er_active_t2_to_sleep_tc(priv);
2998 break;
83808c23
AO		 2999 case SYS_ISDBT:
3000 cxd2841er_active_i_to_sleep_tc(priv);
3001 break;
a6dc60ff
KS		 3002 case SYS_DVBC_ANNEX_A:
3003 cxd2841er_active_c_to_sleep_tc(priv);
3004 break;
3005 default:
3006 dev_warn(&priv->i2c->dev,
3007 "%s(): unknown delivery system %d\n",
3008 __func__, priv->system);
3009 }
3010 }
3011 if (priv->state != STATE_SLEEP_TC) {
3012 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3013 __func__, priv->state);
3014 return -EINVAL;
3015 }
3016 cxd2841er_sleep_tc_to_shutdown(priv);
3017 return 0;
3018}
3019
3020static int cxd2841er_send_burst(struct dvb_frontend *fe,
3021 enum fe_sec_mini_cmd burst)
3022{
3023 u8 data;
3024 struct cxd2841er_priv *priv = fe->demodulator_priv;
3025
3026 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3027 (burst == SEC_MINI_A ? "A" : "B"));
3028 if (priv->state != STATE_SLEEP_S &&
3029 priv->state != STATE_ACTIVE_S) {
3030 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3031 __func__, priv->state);
3032 return -EINVAL;
3033 }
3034 data = (burst == SEC_MINI_A ? 0 : 1);
3035 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3036 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3037 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3038 return 0;
3039}
3040
3041static int cxd2841er_set_tone(struct dvb_frontend *fe,
3042 enum fe_sec_tone_mode tone)
3043{
3044 u8 data;
3045 struct cxd2841er_priv *priv = fe->demodulator_priv;
3046
3047 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3048 (tone == SEC_TONE_ON ? "On" : "Off"));
3049 if (priv->state != STATE_SLEEP_S &&
3050 priv->state != STATE_ACTIVE_S) {
3051 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3052 __func__, priv->state);
3053 return -EINVAL;
3054 }
3055 data = (tone == SEC_TONE_ON ? 1 : 0);
3056 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3057 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3058 return 0;
3059}
3060
3061static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3062 struct dvb_diseqc_master_cmd *cmd)
3063{
3064 int i;
3065 u8 data[12];
3066 struct cxd2841er_priv *priv = fe->demodulator_priv;
3067
3068 if (priv->state != STATE_SLEEP_S &&
3069 priv->state != STATE_ACTIVE_S) {
3070 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3071 __func__, priv->state);
3072 return -EINVAL;
3073 }
3074 dev_dbg(&priv->i2c->dev,
3075 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3076 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3077 /* DiDEqC enable */
3078 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3079 /* cmd1 length & data */
3080 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3081 memset(data, 0, sizeof(data));
3082 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3083 data[i] = cmd->msg[i];
3084 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3085 /* repeat count for cmd1 */
3086 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3087 /* repeat count for cmd2: always 0 */
3088 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3089 /* start transmit */
3090 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3091 /* wait for 1 sec timeout */
3092 for (i = 0; i < 50; i++) {
3093 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3094 if (!data[0]) {
3095 dev_dbg(&priv->i2c->dev,
3096 "%s(): DiSEqC cmd has been sent\n", __func__);
3097 return 0;
3098 }
3099 msleep(20);
3100 }
3101 dev_dbg(&priv->i2c->dev,
3102 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3103 return -ETIMEDOUT;
3104}
3105
3106static void cxd2841er_release(struct dvb_frontend *fe)
3107{
3108 struct cxd2841er_priv *priv = fe->demodulator_priv;
3109
3110 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3111 kfree(priv);
3112}
3113
3114static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3115{
3116 struct cxd2841er_priv *priv = fe->demodulator_priv;
3117
3118 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3119 cxd2841er_set_reg_bits(
3120 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3121 return 0;
3122}
3123
3124static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3125{
3126 struct cxd2841er_priv *priv = fe->demodulator_priv;
3127
3128 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3129 return DVBFE_ALGO_HW;
3130}
3131
3132static int cxd2841er_init_s(struct dvb_frontend *fe)
3133{
3134 struct cxd2841er_priv *priv = fe->demodulator_priv;
3135
3136 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3137 cxd2841er_shutdown_to_sleep_s(priv);
3138 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3139 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3140 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3141 return 0;
3142}
3143
3144static int cxd2841er_init_tc(struct dvb_frontend *fe)
3145{
3146 struct cxd2841er_priv *priv = fe->demodulator_priv;
3147
3148 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3149 cxd2841er_shutdown_to_sleep_tc(priv);
3150 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3151 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3152 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3153 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3154 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3155 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3156 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3157 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3158 return 0;
3159}
3160
3161static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3162static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
3163static struct dvb_frontend_ops cxd2841er_dvbc_ops;
83808c23 3164static struct dvb_frontend_ops cxd2841er_isdbt_ops;
a6dc60ff
KS		 3165
3166static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3167 struct i2c_adapter *i2c,
3168 u8 system)
3169{
3170 u8 chip_id = 0;
3171 const char *type;
3172 struct cxd2841er_priv *priv = NULL;
3173
3174 /* allocate memory for the internal state */
3175 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3176 if (!priv)
3177 return NULL;
3178 priv->i2c = i2c;
3179 priv->config = cfg;
3180 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3181 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
83808c23 3182 priv->xtal = cfg->xtal;
a6dc60ff
KS		 3183 /* create dvb_frontend */
3184 switch (system) {
3185 case SYS_DVBS:
3186 memcpy(&priv->frontend.ops,
3187 &cxd2841er_dvbs_s2_ops,
3188 sizeof(struct dvb_frontend_ops));
3189 type = "S/S2";
3190 break;
3191 case SYS_DVBT:
3192 memcpy(&priv->frontend.ops,
3193 &cxd2841er_dvbt_t2_ops,
3194 sizeof(struct dvb_frontend_ops));
3195 type = "T/T2";
3196 break;
83808c23
AO		 3197 case SYS_ISDBT:
3198 memcpy(&priv->frontend.ops,
3199 &cxd2841er_isdbt_ops,
3200 sizeof(struct dvb_frontend_ops));
3201 type = "ISDBT";
3202 break;
a6dc60ff
KS		 3203 case SYS_DVBC_ANNEX_A:
3204 memcpy(&priv->frontend.ops,
3205 &cxd2841er_dvbc_ops,
3206 sizeof(struct dvb_frontend_ops));
3207 type = "C/C2";
3208 break;
3209 default:
3210 kfree(priv);
3211 return NULL;
3212 }
3213 priv->frontend.demodulator_priv = priv;
3214 dev_info(&priv->i2c->dev,
3215 "%s(): attaching CXD2841ER DVB-%s frontend\n",
3216 __func__, type);
3217 dev_info(&priv->i2c->dev,
3218 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3219 __func__, priv->i2c,
3220 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3221 chip_id = cxd2841er_chip_id(priv);
83808c23 3222 if (chip_id != CXD2841ER_CHIP_ID && chip_id != CXD2854ER_CHIP_ID) {
a6dc60ff
KS		 3223 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3224 __func__, chip_id);
3225 priv->frontend.demodulator_priv = NULL;
3226 kfree(priv);
3227 return NULL;
3228 }
3229 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3230 __func__, chip_id);
3231 return &priv->frontend;
3232}
3233
3234struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3235 struct i2c_adapter *i2c)
3236{
3237 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3238}
3239EXPORT_SYMBOL(cxd2841er_attach_s);
3240
3241struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
3242 struct i2c_adapter *i2c)
3243{
3244 return cxd2841er_attach(cfg, i2c, SYS_DVBT);
3245}
3246EXPORT_SYMBOL(cxd2841er_attach_t);
3247
83808c23
AO		 3248struct dvb_frontend *cxd2841er_attach_i(struct cxd2841er_config *cfg,
3249 struct i2c_adapter *i2c)
3250{
3251 return cxd2841er_attach(cfg, i2c, SYS_ISDBT);
3252}
3253EXPORT_SYMBOL(cxd2841er_attach_i);
3254
a6dc60ff
KS		 3255struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
3256 struct i2c_adapter *i2c)
3257{
3258 return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
3259}
3260EXPORT_SYMBOL(cxd2841er_attach_c);
3261
3262static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3263 .delsys = { SYS_DVBS, SYS_DVBS2 },
3264 .info = {
3265 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3266 .frequency_min = 500000,
3267 .frequency_max = 2500000,
3268 .frequency_stepsize = 0,
3269 .symbol_rate_min = 1000000,
3270 .symbol_rate_max = 45000000,
3271 .symbol_rate_tolerance = 500,
3272 .caps = FE_CAN_INVERSION_AUTO |
3273 FE_CAN_FEC_AUTO |
3274 FE_CAN_QPSK,
3275 },
3276 .init = cxd2841er_init_s,
3277 .sleep = cxd2841er_sleep_s,
3278 .release = cxd2841er_release,
3279 .set_frontend = cxd2841er_set_frontend_s,
3280 .get_frontend = cxd2841er_get_frontend,
3281 .read_status = cxd2841er_read_status_s,
3282 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3283 .get_frontend_algo = cxd2841er_get_algo,
3284 .set_tone = cxd2841er_set_tone,
3285 .diseqc_send_burst = cxd2841er_send_burst,
3286 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3287 .tune = cxd2841er_tune_s
3288};
3289
3290static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
3291 .delsys = { SYS_DVBT, SYS_DVBT2 },
3292 .info = {
3293 .name = "Sony CXD2841ER DVB-T/T2 demodulator",
3294 .caps = FE_CAN_FEC_1_2 |
3295 FE_CAN_FEC_2_3 |
3296 FE_CAN_FEC_3_4 |
3297 FE_CAN_FEC_5_6 |
3298 FE_CAN_FEC_7_8 |
3299 FE_CAN_FEC_AUTO |
3300 FE_CAN_QPSK |
3301 FE_CAN_QAM_16 |
3302 FE_CAN_QAM_32 |
3303 FE_CAN_QAM_64 |
3304 FE_CAN_QAM_128 |
3305 FE_CAN_QAM_256 |
3306 FE_CAN_QAM_AUTO |
3307 FE_CAN_TRANSMISSION_MODE_AUTO |
3308 FE_CAN_GUARD_INTERVAL_AUTO |
3309 FE_CAN_HIERARCHY_AUTO |
3310 FE_CAN_MUTE_TS |
3311 FE_CAN_2G_MODULATION,
3312 .frequency_min = 42000000,
3313 .frequency_max = 1002000000
3314 },
3315 .init = cxd2841er_init_tc,
3316 .sleep = cxd2841er_sleep_tc,
3317 .release = cxd2841er_release,
3318 .set_frontend = cxd2841er_set_frontend_tc,
3319 .get_frontend = cxd2841er_get_frontend,
3320 .read_status = cxd2841er_read_status_tc,
3321 .tune = cxd2841er_tune_tc,
3322 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3323 .get_frontend_algo = cxd2841er_get_algo
3324};
3325
83808c23
AO		 3326static struct dvb_frontend_ops cxd2841er_isdbt_ops = {
3327 .delsys = { SYS_ISDBT },
3328 .info = {
3329 .name = "Sony CXD2854ER ISDBT demodulator",
3330 .caps = FE_CAN_FEC_1_2 |
3331 FE_CAN_FEC_2_3 |
3332 FE_CAN_FEC_3_4 |
3333 FE_CAN_FEC_5_6 |
3334 FE_CAN_FEC_7_8 |
3335 FE_CAN_FEC_AUTO |
3336 FE_CAN_QPSK |
3337 FE_CAN_QAM_16 |
3338 FE_CAN_QAM_32 |
3339 FE_CAN_QAM_64 |
3340 FE_CAN_QAM_128 |
3341 FE_CAN_QAM_256 |
3342 FE_CAN_QAM_AUTO |
3343 FE_CAN_TRANSMISSION_MODE_AUTO |
3344 FE_CAN_GUARD_INTERVAL_AUTO |
3345 FE_CAN_HIERARCHY_AUTO |
3346 FE_CAN_MUTE_TS |
3347 FE_CAN_2G_MODULATION,
3348 .frequency_min = 42000000,
3349 .frequency_max = 1002000000
3350 },
3351 .init = cxd2841er_init_tc,
3352 .sleep = cxd2841er_sleep_tc,
3353 .release = cxd2841er_release,
3354 .set_frontend = cxd2841er_set_frontend_tc,
3355 .get_frontend = cxd2841er_get_frontend,
3356 .read_status = cxd2841er_read_status_tc,
3357 .tune = cxd2841er_tune_tc,
3358 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3359 .get_frontend_algo = cxd2841er_get_algo
3360};
3361
a6dc60ff
KS		 3362static struct dvb_frontend_ops cxd2841er_dvbc_ops = {
3363 .delsys = { SYS_DVBC_ANNEX_A },
3364 .info = {
3365 .name = "Sony CXD2841ER DVB-C demodulator",
3366 .caps = FE_CAN_FEC_1_2 |
3367 FE_CAN_FEC_2_3 |
3368 FE_CAN_FEC_3_4 |
3369 FE_CAN_FEC_5_6 |
3370 FE_CAN_FEC_7_8 |
3371 FE_CAN_FEC_AUTO |
3372 FE_CAN_QAM_16 |
3373 FE_CAN_QAM_32 |
3374 FE_CAN_QAM_64 |
3375 FE_CAN_QAM_128 |
3376 FE_CAN_QAM_256 |
3377 FE_CAN_QAM_AUTO |
3378 FE_CAN_INVERSION_AUTO,
3379 .frequency_min = 42000000,
3380 .frequency_max = 1002000000
3381 },
3382 .init = cxd2841er_init_tc,
3383 .sleep = cxd2841er_sleep_tc,
3384 .release = cxd2841er_release,
3385 .set_frontend = cxd2841er_set_frontend_tc,
3386 .get_frontend = cxd2841er_get_frontend,
3387 .read_status = cxd2841er_read_status_tc,
3388 .tune = cxd2841er_tune_tc,
3389 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3390 .get_frontend_algo = cxd2841er_get_algo,
3391};
3392
83808c23
AO		 3393MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3394MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
a6dc60ff 3395MODULE_LICENSE("GPL");
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