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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / cxd2841er.c
CommitLineData
a6dc60ff
KS		 1/*
2 * cxd2841er.c
3 *
83808c23 4 * Sony digital demodulator driver for
9ca1736f
AO		 5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
a6dc60ff
KS		 7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
d13a7b67 38#define MAX_WRITE_REGSIZE 16
a6f330cb
AO		 39#define LOG2_E_100X 144
40
df61f828
DS		 41#define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
42
a6f330cb
AO		 43/* DVB-C constellation */
44enum sony_dvbc_constellation_t {
45 SONY_DVBC_CONSTELLATION_16QAM,
46 SONY_DVBC_CONSTELLATION_32QAM,
47 SONY_DVBC_CONSTELLATION_64QAM,
48 SONY_DVBC_CONSTELLATION_128QAM,
49 SONY_DVBC_CONSTELLATION_256QAM
50};
d13a7b67 51
a6dc60ff
KS		 52enum cxd2841er_state {
53 STATE_SHUTDOWN = 0,
54 STATE_SLEEP_S,
55 STATE_ACTIVE_S,
56 STATE_SLEEP_TC,
57 STATE_ACTIVE_TC
58};
59
60struct cxd2841er_priv {
61 struct dvb_frontend frontend;
62 struct i2c_adapter *i2c;
63 u8 i2c_addr_slvx;
64 u8 i2c_addr_slvt;
65 const struct cxd2841er_config *config;
66 enum cxd2841er_state state;
67 u8 system;
83808c23 68 enum cxd2841er_xtal xtal;
3f3b48a0 69 enum fe_caps caps;
050863aa 70 u32 flags;
a6dc60ff
KS		 71};
72
73static const struct cxd2841er_cnr_data s_cn_data[] = {
74 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
75 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
76 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
77 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
78 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
79 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
80 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
81 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
82 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
83 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
84 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
85 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
86 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
87 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
88 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
89 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
90 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
91 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
92 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
93 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
94 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
95 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
96 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
97 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
98 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
99 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
100 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
101 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
102 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
103 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
104 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
105 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
106 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
107 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
108 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
109 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
110 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
111 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
112 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
113 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
114 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
115 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
116 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
117 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
118 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
119 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
120 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
121 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
122 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
123 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
124 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
125 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
126 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
127 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
128 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
129 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
130 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
131 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
132 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
133 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
134 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
135 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
136 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
137 { 0x0015, 19900 }, { 0x0014, 20000 },
138};
139
140static const struct cxd2841er_cnr_data s2_cn_data[] = {
141 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
142 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
143 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
144 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
145 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
146 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
147 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
148 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
149 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
150 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
151 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
152 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
153 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
154 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
155 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
156 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
157 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
158 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
159 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
160 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
161 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
162 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
163 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
164 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
165 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
166 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
167 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
168 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
169 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
170 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
171 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
172 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
173 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
174 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
175 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
176 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
177 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
178 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
179 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
180 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
181 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
182 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
183 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
184 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
185 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
186 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
187 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
188 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
189 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
190 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
191 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
192 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
193 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
194 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
195 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
196 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
197 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
198 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
199 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
200 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
201 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
202 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
203 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
204 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
205};
206
0854df79
AO		 207static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
208static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
209
a6dc60ff
KS		 210static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
211 u8 addr, u8 reg, u8 write,
212 const u8 *data, u32 len)
213{
214 dev_dbg(&priv->i2c->dev,
5d6d93a1
DS		 215 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
216 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
a6dc60ff
KS		 217}
218
219static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
220 u8 addr, u8 reg, const u8 *data, u32 len)
221{
222 int ret;
d13a7b67 223 u8 buf[MAX_WRITE_REGSIZE + 1];
a6dc60ff
KS		 224 u8 i2c_addr = (addr == I2C_SLVX ?
225 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
226 struct i2c_msg msg[1] = {
227 {
228 .addr = i2c_addr,
229 .flags = 0,
d13a7b67 230 .len = len + 1,
a6dc60ff
KS		 231 .buf = buf,
232 }
233 };
234
d13a7b67 235 if (len + 1 >= sizeof(buf)) {
83808c23 236 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
d13a7b67
MCC		 237 reg, len + 1);
238 return -E2BIG;
239 }
240
a6dc60ff
KS		 241 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
242 buf[0] = reg;
243 memcpy(&buf[1], data, len);
244
245 ret = i2c_transfer(priv->i2c, msg, 1);
246 if (ret >= 0 && ret != 1)
247 ret = -EIO;
248 if (ret < 0) {
249 dev_warn(&priv->i2c->dev,
250 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
251 KBUILD_MODNAME, ret, i2c_addr, reg, len);
252 return ret;
253 }
254 return 0;
255}
256
257static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
258 u8 addr, u8 reg, u8 val)
259{
260 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
261}
262
263static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
264 u8 addr, u8 reg, u8 *val, u32 len)
265{
266 int ret;
267 u8 i2c_addr = (addr == I2C_SLVX ?
268 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
269 struct i2c_msg msg[2] = {
270 {
271 .addr = i2c_addr,
272 .flags = 0,
273 .len = 1,
274 .buf = &reg,
275 }, {
276 .addr = i2c_addr,
277 .flags = I2C_M_RD,
278 .len = len,
279 .buf = val,
280 }
281 };
282
725e93eb
DS		 283 ret = i2c_transfer(priv->i2c, msg, 2);
284 if (ret >= 0 && ret != 2)
a6dc60ff
KS		 285 ret = -EIO;
286 if (ret < 0) {
287 dev_warn(&priv->i2c->dev,
288 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
289 KBUILD_MODNAME, ret, i2c_addr, reg);
290 return ret;
291 }
6c77161a 292 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
a6dc60ff
KS		 293 return 0;
294}
295
296static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 *val)
298{
299 return cxd2841er_read_regs(priv, addr, reg, val, 1);
300}
301
302static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
303 u8 addr, u8 reg, u8 data, u8 mask)
304{
305 int res;
306 u8 rdata;
307
308 if (mask != 0xff) {
309 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
310 if (res)
311 return res;
312 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
313 }
314 return cxd2841er_write_reg(priv, addr, reg, data);
315}
316
cbc85a47
DS		 317static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
318{
319 u64 tmp;
320
321 tmp = (u64) ifhz * 16777216;
322 do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
323
324 return (u32) tmp;
325}
326
327static u32 cxd2841er_calc_iffreq(u32 ifhz)
328{
329 return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
330}
331
4b866c4e
DS		 332static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
333{
334 u32 hz;
335
336 if (priv->frontend.ops.tuner_ops.get_if_frequency
337 && (priv->flags & CXD2841ER_AUTO_IFHZ))
338 priv->frontend.ops.tuner_ops.get_if_frequency(
339 &priv->frontend, &hz);
340 else
341 hz = def_hz;
342
343 return hz;
344}
345
c7518d13
DS		 346static int cxd2841er_tuner_set(struct dvb_frontend *fe)
347{
348 struct cxd2841er_priv *priv = fe->demodulator_priv;
349
350 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
351 fe->ops.i2c_gate_ctrl(fe, 1);
352 if (fe->ops.tuner_ops.set_params)
353 fe->ops.tuner_ops.set_params(fe);
354 if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
355 fe->ops.i2c_gate_ctrl(fe, 0);
356
357 return 0;
358}
359
a6dc60ff
KS		 360static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
361 u32 symbol_rate)
362{
363 u32 reg_value = 0;
364 u8 data[3] = {0, 0, 0};
365
366 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
367 /*
368 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
369 * = ((symbolRateKSps * 2^14) + 500) / 1000
370 * = ((symbolRateKSps * 16384) + 500) / 1000
371 */
372 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
373 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
374 dev_err(&priv->i2c->dev,
375 "%s(): reg_value is out of range\n", __func__);
376 return -EINVAL;
377 }
378 data[0] = (u8)((reg_value >> 16) & 0x0F);
379 data[1] = (u8)((reg_value >> 8) & 0xFF);
380 data[2] = (u8)(reg_value & 0xFF);
381 /* Set SLV-T Bank : 0xAE */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
383 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
384 return 0;
385}
386
387static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
388 u8 system);
389
390static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
391 u8 system, u32 symbol_rate)
392{
393 int ret;
394 u8 data[4] = { 0, 0, 0, 0 };
395
396 if (priv->state != STATE_SLEEP_S) {
397 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
398 __func__, (int)priv->state);
399 return -EINVAL;
400 }
401 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
402 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
403 /* Set demod mode */
404 if (system == SYS_DVBS) {
405 data[0] = 0x0A;
406 } else if (system == SYS_DVBS2) {
407 data[0] = 0x0B;
408 } else {
409 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
410 __func__, system);
411 return -EINVAL;
412 }
413 /* Set SLV-X Bank : 0x00 */
414 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
415 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
416 /* DVB-S/S2 */
417 data[0] = 0x00;
418 /* Set SLV-T Bank : 0x00 */
419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
420 /* Enable S/S2 auto detection 1 */
421 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
422 /* Set SLV-T Bank : 0xAE */
423 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
424 /* Enable S/S2 auto detection 2 */
425 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
426 /* Set SLV-T Bank : 0x00 */
427 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
428 /* Enable demod clock */
429 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
430 /* Enable ADC clock */
431 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
432 /* Enable ADC 1 */
433 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
434 /* Enable ADC 2 */
435 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
436 /* Set SLV-X Bank : 0x00 */
437 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
438 /* Enable ADC 3 */
439 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
440 /* Set SLV-T Bank : 0xA3 */
441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
442 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
443 data[0] = 0x07;
444 data[1] = 0x3B;
445 data[2] = 0x08;
446 data[3] = 0xC5;
447 /* Set SLV-T Bank : 0xAB */
448 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
449 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
450 data[0] = 0x05;
451 data[1] = 0x80;
452 data[2] = 0x0A;
453 data[3] = 0x80;
454 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
455 data[0] = 0x0C;
456 data[1] = 0xCC;
457 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
458 /* Set demod parameter */
459 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
460 if (ret != 0)
461 return ret;
462 /* Set SLV-T Bank : 0x00 */
463 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
464 /* disable Hi-Z setting 1 */
465 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
466 /* disable Hi-Z setting 2 */
467 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
468 priv->state = STATE_ACTIVE_S;
469 return 0;
470}
471
472static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
473 u32 bandwidth);
474
475static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
476 u32 bandwidth);
477
478static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
479 u32 bandwidth);
480
76344a3f
MCC		 481static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
482 u32 bandwidth);
483
484static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
485
486static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
487
488static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
489
a6dc60ff
KS		 490static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
491 struct dtv_frontend_properties *p)
492{
493 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
494 if (priv->state != STATE_ACTIVE_S &&
495 priv->state != STATE_ACTIVE_TC) {
496 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
497 __func__, priv->state);
498 return -EINVAL;
499 }
500 /* Set SLV-T Bank : 0x00 */
501 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
502 /* disable TS output */
503 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
504 if (priv->state == STATE_ACTIVE_S)
505 return cxd2841er_dvbs2_set_symbol_rate(
506 priv, p->symbol_rate / 1000);
507 else if (priv->state == STATE_ACTIVE_TC) {
508 switch (priv->system) {
509 case SYS_DVBT:
510 return cxd2841er_sleep_tc_to_active_t_band(
511 priv, p->bandwidth_hz);
512 case SYS_DVBT2:
513 return cxd2841er_sleep_tc_to_active_t2_band(
514 priv, p->bandwidth_hz);
515 case SYS_DVBC_ANNEX_A:
516 return cxd2841er_sleep_tc_to_active_c_band(
76344a3f
MCC		 517 priv, p->bandwidth_hz);
518 case SYS_ISDBT:
519 cxd2841er_active_i_to_sleep_tc(priv);
520 cxd2841er_sleep_tc_to_shutdown(priv);
521 cxd2841er_shutdown_to_sleep_tc(priv);
522 return cxd2841er_sleep_tc_to_active_i(
523 priv, p->bandwidth_hz);
a6dc60ff
KS		 524 }
525 }
526 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
527 __func__, priv->system);
528 return -EINVAL;
529}
530
531static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
532{
533 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
534 if (priv->state != STATE_ACTIVE_S) {
535 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
536 __func__, priv->state);
537 return -EINVAL;
538 }
539 /* Set SLV-T Bank : 0x00 */
540 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
541 /* disable TS output */
542 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
543 /* enable Hi-Z setting 1 */
544 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
545 /* enable Hi-Z setting 2 */
546 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
547 /* Set SLV-X Bank : 0x00 */
548 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
549 /* disable ADC 1 */
550 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
551 /* Set SLV-T Bank : 0x00 */
552 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
553 /* disable ADC clock */
554 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
555 /* disable ADC 2 */
556 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
557 /* disable ADC 3 */
558 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
559 /* SADC Bias ON */
560 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
561 /* disable demod clock */
562 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
563 /* Set SLV-T Bank : 0xAE */
564 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
565 /* disable S/S2 auto detection1 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
567 /* Set SLV-T Bank : 0x00 */
568 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
569 /* disable S/S2 auto detection2 */
570 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
571 priv->state = STATE_SLEEP_S;
572 return 0;
573}
574
575static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
576{
577 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
578 if (priv->state != STATE_SLEEP_S) {
579 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
580 __func__, priv->state);
581 return -EINVAL;
582 }
583 /* Set SLV-T Bank : 0x00 */
584 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
585 /* Disable DSQOUT */
586 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
587 /* Disable DSQIN */
588 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
589 /* Set SLV-X Bank : 0x00 */
590 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
591 /* Disable oscillator */
592 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
593 /* Set demod mode */
594 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
595 priv->state = STATE_SHUTDOWN;
596 return 0;
597}
598
599static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
600{
601 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
602 if (priv->state != STATE_SLEEP_TC) {
603 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
604 __func__, priv->state);
605 return -EINVAL;
606 }
607 /* Set SLV-X Bank : 0x00 */
608 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
609 /* Disable oscillator */
610 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
611 /* Set demod mode */
612 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
613 priv->state = STATE_SHUTDOWN;
614 return 0;
615}
616
617static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
618{
619 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
620 if (priv->state != STATE_ACTIVE_TC) {
621 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
622 __func__, priv->state);
623 return -EINVAL;
624 }
625 /* Set SLV-T Bank : 0x00 */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
627 /* disable TS output */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
629 /* enable Hi-Z setting 1 */
630 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
631 /* enable Hi-Z setting 2 */
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
633 /* Set SLV-X Bank : 0x00 */
634 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
635 /* disable ADC 1 */
636 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
637 /* Set SLV-T Bank : 0x00 */
638 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
639 /* Disable ADC 2 */
640 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
641 /* Disable ADC 3 */
642 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
643 /* Disable ADC clock */
644 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
645 /* Disable RF level monitor */
646 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
647 /* Disable demod clock */
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
649 priv->state = STATE_SLEEP_TC;
650 return 0;
651}
652
653static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
654{
655 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
656 if (priv->state != STATE_ACTIVE_TC) {
657 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
658 __func__, priv->state);
659 return -EINVAL;
660 }
661 /* Set SLV-T Bank : 0x00 */
662 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
663 /* disable TS output */
664 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
665 /* enable Hi-Z setting 1 */
666 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
667 /* enable Hi-Z setting 2 */
668 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
669 /* Cancel DVB-T2 setting */
670 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
672 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
673 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
674 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
675 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
676 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
677 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
678 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
679 /* Set SLV-X Bank : 0x00 */
680 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
681 /* disable ADC 1 */
682 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
683 /* Set SLV-T Bank : 0x00 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
685 /* Disable ADC 2 */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
687 /* Disable ADC 3 */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
689 /* Disable ADC clock */
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
691 /* Disable RF level monitor */
692 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
693 /* Disable demod clock */
694 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
695 priv->state = STATE_SLEEP_TC;
696 return 0;
697}
698
699static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
700{
701 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
702 if (priv->state != STATE_ACTIVE_TC) {
703 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
704 __func__, priv->state);
705 return -EINVAL;
706 }
707 /* Set SLV-T Bank : 0x00 */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
709 /* disable TS output */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
711 /* enable Hi-Z setting 1 */
712 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
713 /* enable Hi-Z setting 2 */
714 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
715 /* Cancel DVB-C setting */
716 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
717 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
718 /* Set SLV-X Bank : 0x00 */
719 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
720 /* disable ADC 1 */
721 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
722 /* Set SLV-T Bank : 0x00 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
724 /* Disable ADC 2 */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
726 /* Disable ADC 3 */
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
728 /* Disable ADC clock */
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
730 /* Disable RF level monitor */
731 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
732 /* Disable demod clock */
733 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
734 priv->state = STATE_SLEEP_TC;
735 return 0;
736}
737
83808c23
AO		 738static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
739{
740 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
741 if (priv->state != STATE_ACTIVE_TC) {
742 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
743 __func__, priv->state);
744 return -EINVAL;
745 }
746 /* Set SLV-T Bank : 0x00 */
747 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
748 /* disable TS output */
749 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
750 /* enable Hi-Z setting 1 */
751 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
752 /* enable Hi-Z setting 2 */
753 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
754
755 /* TODO: Cancel demod parameter */
756
757 /* Set SLV-X Bank : 0x00 */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
759 /* disable ADC 1 */
760 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
761 /* Set SLV-T Bank : 0x00 */
762 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
763 /* Disable ADC 2 */
764 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
765 /* Disable ADC 3 */
766 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
767 /* Disable ADC clock */
768 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
769 /* Disable RF level monitor */
770 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
771 /* Disable demod clock */
772 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
773 priv->state = STATE_SLEEP_TC;
774 return 0;
775}
776
a6dc60ff
KS		 777static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
778{
779 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
780 if (priv->state != STATE_SHUTDOWN) {
781 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
782 __func__, priv->state);
783 return -EINVAL;
784 }
785 /* Set SLV-X Bank : 0x00 */
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
787 /* Clear all demodulator registers */
788 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
789 usleep_range(3000, 5000);
790 /* Set SLV-X Bank : 0x00 */
791 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
792 /* Set demod SW reset */
793 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
83808c23
AO		 794
795 switch (priv->xtal) {
796 case SONY_XTAL_20500:
797 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
798 break;
799 case SONY_XTAL_24000:
800 /* Select demod frequency */
801 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
802 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
803 break;
804 case SONY_XTAL_41000:
805 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
806 break;
807 default:
808 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
809 __func__, priv->xtal);
810 return -EINVAL;
811 }
812
a6dc60ff
KS		 813 /* Set demod mode */
814 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
815 /* Clear demod SW reset */
816 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
817 usleep_range(1000, 2000);
818 /* Set SLV-T Bank : 0x00 */
819 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
820 /* enable DSQOUT */
821 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
822 /* enable DSQIN */
823 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
824 /* TADC Bias On */
825 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
826 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
827 /* SADC Bias On */
828 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
829 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
830 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
831 priv->state = STATE_SLEEP_S;
832 return 0;
833}
834
835static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
836{
6c77161a 837 u8 data = 0;
3f3b48a0 838
a6dc60ff
KS		 839 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
840 if (priv->state != STATE_SHUTDOWN) {
841 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
842 __func__, priv->state);
843 return -EINVAL;
844 }
845 /* Set SLV-X Bank : 0x00 */
846 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
847 /* Clear all demodulator registers */
848 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
849 usleep_range(3000, 5000);
850 /* Set SLV-X Bank : 0x00 */
851 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
852 /* Set demod SW reset */
853 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
6c77161a 854 /* Select ADC clock mode */
a6dc60ff 855 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
6c77161a
AO		 856
857 switch (priv->xtal) {
858 case SONY_XTAL_20500:
859 data = 0x0;
860 break;
861 case SONY_XTAL_24000:
862 /* Select demod frequency */
863 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
864 data = 0x3;
865 break;
866 case SONY_XTAL_41000:
867 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
868 data = 0x1;
869 break;
870 }
871 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
a6dc60ff
KS		 872 /* Clear demod SW reset */
873 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
874 usleep_range(1000, 2000);
875 /* Set SLV-T Bank : 0x00 */
876 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
877 /* TADC Bias On */
878 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
879 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
880 /* SADC Bias On */
881 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
882 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
883 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
884 priv->state = STATE_SLEEP_TC;
885 return 0;
886}
887
888static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
889{
890 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
891 /* Set SLV-T Bank : 0x00 */
892 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
893 /* SW Reset */
894 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
895 /* Enable TS output */
896 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
897 return 0;
898}
899
900/* Set TS parallel mode */
901static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
902 u8 system)
903{
904 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
905
906 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
907 /* Set SLV-T Bank : 0x00 */
908 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
909 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
910 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
911 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
912 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
913 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
914
03ab1bd5
DS		 915 /*
916 * slave Bank Addr Bit default Name
917 * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE
918 */
919 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
920 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
921 /*
922 * slave Bank Addr Bit default Name
923 * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE
924 */
925 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
926 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
a6dc60ff
KS		 927 /*
928 * slave Bank Addr Bit default Name
929 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
930 */
931 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
932 /*
933 * Disable TS IF Clock
934 * slave Bank Addr Bit default Name
935 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
936 */
937 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
938 /*
939 * slave Bank Addr Bit default Name
940 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
941 */
03ab1bd5
DS		 942 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
943 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
a6dc60ff
KS		 944 /*
945 * Enable TS IF Clock
946 * slave Bank Addr Bit default Name
947 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
948 */
949 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
950
951 if (system == SYS_DVBT) {
952 /* Enable parity period for DVB-T */
953 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
954 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
955 } else if (system == SYS_DVBC_ANNEX_A) {
956 /* Enable parity period for DVB-C */
957 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
958 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
959 }
960}
961
962static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
963{
83808c23 964 u8 chip_id = 0;
a6dc60ff
KS		 965
966 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
83808c23
AO		 967 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
968 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
969 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
970 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
971
a6dc60ff
KS		 972 return chip_id;
973}
974
975static int cxd2841er_read_status_s(struct dvb_frontend *fe,
976 enum fe_status *status)
977{
978 u8 reg = 0;
979 struct cxd2841er_priv *priv = fe->demodulator_priv;
980
981 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
982 *status = 0;
983 if (priv->state != STATE_ACTIVE_S) {
984 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
985 __func__, priv->state);
986 return -EINVAL;
987 }
988 /* Set SLV-T Bank : 0xA0 */
989 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
990 /*
991 * slave Bank Addr Bit Signal name
992 * <SLV-T> A0h 11h [2] ITSLOCK
993 */
994 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
995 if (reg & 0x04) {
996 *status = FE_HAS_SIGNAL
997 | FE_HAS_CARRIER
998 | FE_HAS_VITERBI
999 | FE_HAS_SYNC
1000 | FE_HAS_LOCK;
1001 }
1002 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1003 return 0;
1004}
1005
1006static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1007 u8 *sync, u8 *tslock, u8 *unlock)
1008{
1009 u8 data = 0;
1010
1011 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1012 if (priv->state != STATE_ACTIVE_TC)
1013 return -EINVAL;
1014 if (priv->system == SYS_DVBT) {
1015 /* Set SLV-T Bank : 0x10 */
1016 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1017 } else {
1018 /* Set SLV-T Bank : 0x20 */
1019 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1020 }
1021 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1022 if ((data & 0x07) == 0x07) {
1023 dev_dbg(&priv->i2c->dev,
1024 "%s(): invalid hardware state detected\n", __func__);
1025 *sync = 0;
1026 *tslock = 0;
1027 *unlock = 0;
1028 } else {
1029 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1030 *tslock = ((data & 0x20) ? 1 : 0);
1031 *unlock = ((data & 0x10) ? 1 : 0);
1032 }
1033 return 0;
1034}
1035
1036static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1037{
1038 u8 data;
1039
1040 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1041 if (priv->state != STATE_ACTIVE_TC)
1042 return -EINVAL;
1043 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1044 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1045 if ((data & 0x01) == 0) {
1046 *tslock = 0;
1047 } else {
1048 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1049 *tslock = ((data & 0x20) ? 1 : 0);
1050 }
1051 return 0;
1052}
1053
83808c23
AO		 1054static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1055 u8 *sync, u8 *tslock, u8 *unlock)
1056{
1057 u8 data = 0;
1058
1059 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1060 if (priv->state != STATE_ACTIVE_TC)
1061 return -EINVAL;
1062 /* Set SLV-T Bank : 0x60 */
1063 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1064 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1065 dev_dbg(&priv->i2c->dev,
1066 "%s(): lock=0x%x\n", __func__, data);
1067 *sync = ((data & 0x02) ? 1 : 0);
1068 *tslock = ((data & 0x01) ? 1 : 0);
1069 *unlock = ((data & 0x10) ? 1 : 0);
1070 return 0;
1071}
1072
a6dc60ff
KS		 1073static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1074 enum fe_status *status)
1075{
1076 int ret = 0;
1077 u8 sync = 0;
1078 u8 tslock = 0;
1079 u8 unlock = 0;
1080 struct cxd2841er_priv *priv = fe->demodulator_priv;
1081
1082 *status = 0;
1083 if (priv->state == STATE_ACTIVE_TC) {
1084 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1085 ret = cxd2841er_read_status_t_t2(
1086 priv, &sync, &tslock, &unlock);
1087 if (ret)
1088 goto done;
1089 if (unlock)
1090 goto done;
1091 if (sync)
1092 *status = FE_HAS_SIGNAL |
1093 FE_HAS_CARRIER |
1094 FE_HAS_VITERBI |
1095 FE_HAS_SYNC;
1096 if (tslock)
1097 *status |= FE_HAS_LOCK;
83808c23
AO		 1098 } else if (priv->system == SYS_ISDBT) {
1099 ret = cxd2841er_read_status_i(
1100 priv, &sync, &tslock, &unlock);
1101 if (ret)
1102 goto done;
1103 if (unlock)
1104 goto done;
1105 if (sync)
1106 *status = FE_HAS_SIGNAL |
1107 FE_HAS_CARRIER |
1108 FE_HAS_VITERBI |
1109 FE_HAS_SYNC;
1110 if (tslock)
1111 *status |= FE_HAS_LOCK;
a6dc60ff
KS		 1112 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1113 ret = cxd2841er_read_status_c(priv, &tslock);
1114 if (ret)
1115 goto done;
1116 if (tslock)
1117 *status = FE_HAS_SIGNAL |
1118 FE_HAS_CARRIER |
1119 FE_HAS_VITERBI |
1120 FE_HAS_SYNC |
1121 FE_HAS_LOCK;
1122 }
1123 }
1124done:
1125 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1126 return ret;
1127}
1128
1129static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1130 int *offset)
1131{
1132 u8 data[3];
1133 u8 is_hs_mode;
1134 s32 cfrl_ctrlval;
1135 s32 temp_div, temp_q, temp_r;
1136
1137 if (priv->state != STATE_ACTIVE_S) {
1138 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1139 __func__, priv->state);
1140 return -EINVAL;
1141 }
1142 /*
1143 * Get High Sampling Rate mode
1144 * slave Bank Addr Bit Signal name
1145 * <SLV-T> A0h 10h [0] ITRL_LOCK
1146 */
1147 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1148 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1149 if (data[0] & 0x01) {
1150 /*
1151 * slave Bank Addr Bit Signal name
1152 * <SLV-T> A0h 50h [4] IHSMODE
1153 */
1154 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1155 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1156 } else {
1157 dev_dbg(&priv->i2c->dev,
1158 "%s(): unable to detect sampling rate mode\n",
1159 __func__);
1160 return -EINVAL;
1161 }
1162 /*
1163 * slave Bank Addr Bit Signal name
1164 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1165 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1166 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1167 */
1168 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1169 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1170 (((u32)data[1] & 0xFF) << 8) |
1171 ((u32)data[2] & 0xFF), 20);
1172 temp_div = (is_hs_mode ? 1048576 : 1572864);
1173 if (cfrl_ctrlval > 0) {
1174 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1175 temp_div, &temp_r);
1176 } else {
1177 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1178 temp_div, &temp_r);
1179 }
1180 if (temp_r >= temp_div / 2)
1181 temp_q++;
1182 if (cfrl_ctrlval > 0)
1183 temp_q *= -1;
1184 *offset = temp_q;
1185 return 0;
1186}
1187
76344a3f
MCC		 1188static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1189 u32 bandwidth, int *offset)
1190{
1191 u8 data[4];
1192
1193 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1194 if (priv->state != STATE_ACTIVE_TC) {
1195 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1196 __func__, priv->state);
1197 return -EINVAL;
1198 }
1199 if (priv->system != SYS_ISDBT) {
1200 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1201 __func__, priv->system);
1202 return -EINVAL;
1203 }
1204 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1205 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1206 *offset = -1 * sign_extend32(
1207 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1208 ((u32)data[2] << 8) | (u32)data[3], 29);
1209
1210 switch (bandwidth) {
1211 case 6000000:
1212 *offset = -1 * ((*offset) * 8/264);
1213 break;
1214 case 7000000:
1215 *offset = -1 * ((*offset) * 8/231);
1216 break;
1217 case 8000000:
1218 *offset = -1 * ((*offset) * 8/198);
1219 break;
1220 default:
1221 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1222 __func__, bandwidth);
1223 return -EINVAL;
1224 }
1225
1226 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1227 __func__, bandwidth, *offset);
1228
1229 return 0;
1230}
1231
c5ea46da
AO		 1232static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1233 u32 bandwidth, int *offset)
1234{
1235 u8 data[4];
1236
1237 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1238 if (priv->state != STATE_ACTIVE_TC) {
1239 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1240 __func__, priv->state);
1241 return -EINVAL;
1242 }
1243 if (priv->system != SYS_DVBT) {
1244 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1245 __func__, priv->system);
1246 return -EINVAL;
1247 }
1248 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1249 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1250 *offset = -1 * sign_extend32(
1251 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1252 ((u32)data[2] << 8) | (u32)data[3], 29);
6c77161a
AO		 1253 *offset *= (bandwidth / 1000000);
1254 *offset /= 235;
c5ea46da
AO		 1255 return 0;
1256}
1257
c8946c8d
MCC		 1258static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1259 u32 bandwidth, int *offset)
a6dc60ff
KS		 1260{
1261 u8 data[4];
1262
1263 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1264 if (priv->state != STATE_ACTIVE_TC) {
1265 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1266 __func__, priv->state);
1267 return -EINVAL;
1268 }
1269 if (priv->system != SYS_DVBT2) {
1270 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1271 __func__, priv->system);
1272 return -EINVAL;
1273 }
1274 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1275 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1276 *offset = -1 * sign_extend32(
1277 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1278 ((u32)data[2] << 8) | (u32)data[3], 27);
1279 switch (bandwidth) {
1280 case 1712000:
1281 *offset /= 582;
1282 break;
1283 case 5000000:
1284 case 6000000:
1285 case 7000000:
1286 case 8000000:
1287 *offset *= (bandwidth / 1000000);
1288 *offset /= 940;
1289 break;
1290 default:
1291 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1292 __func__, bandwidth);
1293 return -EINVAL;
1294 }
1295 return 0;
1296}
1297
c8946c8d
MCC		 1298static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1299 int *offset)
a6dc60ff
KS		 1300{
1301 u8 data[2];
1302
1303 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1304 if (priv->state != STATE_ACTIVE_TC) {
1305 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1306 __func__, priv->state);
1307 return -EINVAL;
1308 }
1309 if (priv->system != SYS_DVBC_ANNEX_A) {
1310 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1311 __func__, priv->system);
1312 return -EINVAL;
1313 }
1314 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1315 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1316 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1317 | (u32)data[1], 13), 16384);
1318 return 0;
1319}
1320
a6f330cb
AO		 1321static int cxd2841er_read_packet_errors_c(
1322 struct cxd2841er_priv *priv, u32 *penum)
1323{
1324 u8 data[3];
1325
1326 *penum = 0;
1327 if (priv->state != STATE_ACTIVE_TC) {
1328 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1329 __func__, priv->state);
1330 return -EINVAL;
1331 }
1332 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1333 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1334 if (data[2] & 0x01)
1335 *penum = ((u32)data[0] << 8) | (u32)data[1];
1336 return 0;
1337}
1338
a6dc60ff
KS		 1339static int cxd2841er_read_packet_errors_t(
1340 struct cxd2841er_priv *priv, u32 *penum)
1341{
1342 u8 data[3];
1343
1344 *penum = 0;
1345 if (priv->state != STATE_ACTIVE_TC) {
1346 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1347 __func__, priv->state);
1348 return -EINVAL;
1349 }
1350 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1351 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1352 if (data[2] & 0x01)
1353 *penum = ((u32)data[0] << 8) | (u32)data[1];
1354 return 0;
1355}
1356
1357static int cxd2841er_read_packet_errors_t2(
1358 struct cxd2841er_priv *priv, u32 *penum)
1359{
1360 u8 data[3];
1361
1362 *penum = 0;
1363 if (priv->state != STATE_ACTIVE_TC) {
1364 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1365 __func__, priv->state);
1366 return -EINVAL;
1367 }
1368 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1369 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1370 if (data[0] & 0x01)
1371 *penum = ((u32)data[1] << 8) | (u32)data[2];
1372 return 0;
1373}
1374
83808c23
AO		 1375static int cxd2841er_read_packet_errors_i(
1376 struct cxd2841er_priv *priv, u32 *penum)
1377{
1378 u8 data[2];
1379
1380 *penum = 0;
1381 if (priv->state != STATE_ACTIVE_TC) {
1382 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1383 __func__, priv->state);
1384 return -EINVAL;
1385 }
1386 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1387 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1388
1389 if (!(data[0] & 0x01))
1390 return 0;
1391
1392 /* Layer A */
1393 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1394 *penum = ((u32)data[0] << 8) | (u32)data[1];
1395
1396 /* Layer B */
1397 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1398 *penum += ((u32)data[0] << 8) | (u32)data[1];
1399
1400 /* Layer C */
1401 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1402 *penum += ((u32)data[0] << 8) | (u32)data[1];
1403
1404 return 0;
1405}
1406
a6f330cb
AO		 1407static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1408 u32 *bit_error, u32 *bit_count)
1409{
1410 u8 data[3];
1411 u32 bit_err, period_exp;
1412
1413 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1414 if (priv->state != STATE_ACTIVE_TC) {
1415 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1416 __func__, priv->state);
1417 return -EINVAL;
1418 }
1419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1420 cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1421 if (!(data[0] & 0x80)) {
1422 dev_dbg(&priv->i2c->dev,
1423 "%s(): no valid BER data\n", __func__);
1424 return -EINVAL;
1425 }
1426 bit_err = ((u32)(data[0] & 0x3f) << 16) |
1427 ((u32)data[1] << 8) |
1428 (u32)data[2];
1429 cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1430 period_exp = data[0] & 0x1f;
1431
1432 if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1433 dev_dbg(&priv->i2c->dev,
1434 "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
1435 __func__, period_exp, bit_err);
1436 return -EINVAL;
1437 }
1438
1439 dev_dbg(&priv->i2c->dev,
1440 "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1441 __func__, period_exp, bit_err,
1442 ((1 << period_exp) * 204 * 8));
1443
1444 *bit_error = bit_err;
1445 *bit_count = ((1 << period_exp) * 204 * 8);
1446
1447 return 0;
1448}
1449
0854df79
AO		 1450static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1451 u32 *bit_error, u32 *bit_count)
1452{
1453 u8 data[3];
1454 u8 pktnum[2];
1455
1456 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1457 if (priv->state != STATE_ACTIVE_TC) {
1458 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1459 __func__, priv->state);
1460 return -EINVAL;
1461 }
1462
1463 cxd2841er_freeze_regs(priv);
1464 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1465 cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1466 cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
6ccf821c 1467 cxd2841er_unfreeze_regs(priv);
0854df79
AO		 1468
1469 if (!pktnum[0] && !pktnum[1]) {
1470 dev_dbg(&priv->i2c->dev,
1471 "%s(): no valid BER data\n", __func__);
0854df79
AO		 1472 return -EINVAL;
1473 }
1474
1475 *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1476 ((u32)data[1] << 8) | data[2];
1477 *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1478 dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1479 __func__, *bit_error, *bit_count);
1480
0854df79
AO		 1481 return 0;
1482}
1483
4216be14
MCC		 1484static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1485 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1486{
1487 u8 data[11];
a6dc60ff
KS		 1488
1489 /* Set SLV-T Bank : 0xA0 */
1490 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1491 /*
1492 * slave Bank Addr Bit Signal name
1493 * <SLV-T> A0h 35h [0] IFVBER_VALID
1494 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1495 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1496 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1497 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1498 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1499 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1500 */
1501 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1502 if (data[0] & 0x01) {
4216be14
MCC		 1503 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1504 ((u32)(data[2] & 0xFF) << 8) |
1505 (u32)(data[3] & 0xFF);
1506 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1507 ((u32)(data[9] & 0xFF) << 8) |
1508 (u32)(data[10] & 0xFF);
1509 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
a6dc60ff
KS		 1510 dev_dbg(&priv->i2c->dev,
1511 "%s(): invalid bit_error %d, bit_count %d\n",
4216be14 1512 __func__, *bit_error, *bit_count);
f1b26622 1513 return -EINVAL;
a6dc60ff 1514 }
f1b26622 1515 return 0;
a6dc60ff
KS		 1516 }
1517 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
f1b26622 1518 return -EINVAL;
a6dc60ff
KS		 1519}
1520
1521
4216be14
MCC		 1522static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1523 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1524{
1525 u8 data[5];
4216be14 1526 u32 period;
a6dc60ff
KS		 1527
1528 /* Set SLV-T Bank : 0xB2 */
1529 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1530 /*
1531 * slave Bank Addr Bit Signal name
1532 * <SLV-T> B2h 30h [0] IFLBER_VALID
1533 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1534 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1535 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1536 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1537 */
1538 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1539 if (data[0] & 0x01) {
1540 /* Bit error count */
4216be14
MCC		 1541 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1542 ((u32)(data[2] & 0xFF) << 16) |
1543 ((u32)(data[3] & 0xFF) << 8) |
1544 (u32)(data[4] & 0xFF);
a6dc60ff
KS		 1545
1546 /* Set SLV-T Bank : 0xA0 */
1547 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1548 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1549 /* Measurement period */
1550 period = (u32)(1 << (data[0] & 0x0F));
1551 if (period == 0) {
1552 dev_dbg(&priv->i2c->dev,
1553 "%s(): period is 0\n", __func__);
f1b26622 1554 return -EINVAL;
a6dc60ff 1555 }
4216be14 1556 if (*bit_error > (period * 64800)) {
a6dc60ff
KS		 1557 dev_dbg(&priv->i2c->dev,
1558 "%s(): invalid bit_err 0x%x period 0x%x\n",
4216be14 1559 __func__, *bit_error, period);
f1b26622 1560 return -EINVAL;
a6dc60ff 1561 }
4216be14
MCC		 1562 *bit_count = period * 64800;
1563
f1b26622 1564 return 0;
a6dc60ff
KS		 1565 } else {
1566 dev_dbg(&priv->i2c->dev,
1567 "%s(): no data available\n", __func__);
1568 }
f1b26622 1569 return -EINVAL;
a6dc60ff
KS		 1570}
1571
4216be14
MCC		 1572static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1573 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1574{
1575 u8 data[4];
4216be14 1576 u32 period_exp, n_ldpc;
a6dc60ff 1577
a6dc60ff
KS		 1578 if (priv->state != STATE_ACTIVE_TC) {
1579 dev_dbg(&priv->i2c->dev,
1580 "%s(): invalid state %d\n", __func__, priv->state);
1581 return -EINVAL;
1582 }
1583 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1584 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1585 if (!(data[0] & 0x10)) {
1586 dev_dbg(&priv->i2c->dev,
1587 "%s(): no valid BER data\n", __func__);
4216be14 1588 return -EINVAL;
a6dc60ff 1589 }
4216be14
MCC		 1590 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1591 ((u32)data[1] << 16) |
1592 ((u32)data[2] << 8) |
1593 (u32)data[3];
a6dc60ff
KS		 1594 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1595 period_exp = data[0] & 0x0f;
1596 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1597 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1598 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
4216be14 1599 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
a6dc60ff
KS		 1600 dev_dbg(&priv->i2c->dev,
1601 "%s(): invalid BER value\n", __func__);
1602 return -EINVAL;
1603 }
4216be14
MCC		 1604
1605 /*
1606 * FIXME: the right thing would be to return bit_error untouched,
1607 * but, as we don't know the scale returned by the counters, let's
1608 * at least preserver BER = bit_error/bit_count.
1609 */
a6dc60ff 1610 if (period_exp >= 4) {
4216be14
MCC		 1611 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1612 *bit_error *= 3125ULL;
a6dc60ff 1613 } else {
4216be14 1614 *bit_count = (1U << period_exp) * (n_ldpc / 200);
a6f330cb 1615 *bit_error *= 50000ULL;
a6dc60ff 1616 }
a6dc60ff
KS		 1617 return 0;
1618}
1619
4216be14
MCC		 1620static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1621 u32 *bit_error, u32 *bit_count)
a6dc60ff
KS		 1622{
1623 u8 data[2];
4216be14 1624 u32 period;
a6dc60ff 1625
a6dc60ff
KS		 1626 if (priv->state != STATE_ACTIVE_TC) {
1627 dev_dbg(&priv->i2c->dev,
1628 "%s(): invalid state %d\n", __func__, priv->state);
1629 return -EINVAL;
1630 }
1631 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1632 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1633 if (!(data[0] & 0x01)) {
1634 dev_dbg(&priv->i2c->dev,
1635 "%s(): no valid BER data\n", __func__);
1636 return 0;
1637 }
1638 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
4216be14 1639 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
a6dc60ff
KS		 1640 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1641 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
4216be14
MCC		 1642
1643 /*
1644 * FIXME: the right thing would be to return bit_error untouched,
1645 * but, as we don't know the scale returned by the counters, let's
1646 * at least preserver BER = bit_error/bit_count.
1647 */
1648 *bit_count = period / 128;
1649 *bit_error *= 78125ULL;
a6dc60ff
KS		 1650 return 0;
1651}
1652
4a86bc10
AO		 1653static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1654{
1655 /*
1656 * Freeze registers: ensure multiple separate register reads
1657 * are from the same snapshot
1658 */
1659 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1660 return 0;
1661}
1662
1663static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1664{
1665 /*
1666 * un-freeze registers
1667 */
1668 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1669 return 0;
1670}
1671
e05b1872
AO		 1672static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1673 u8 delsys, u32 *snr)
a6dc60ff
KS		 1674{
1675 u8 data[3];
1676 u32 res = 0, value;
1677 int min_index, max_index, index;
1678 static const struct cxd2841er_cnr_data *cn_data;
1679
4a86bc10 1680 cxd2841er_freeze_regs(priv);
a6dc60ff
KS		 1681 /* Set SLV-T Bank : 0xA1 */
1682 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1683 /*
1684 * slave Bank Addr Bit Signal name
1685 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1686 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1687 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1688 */
1689 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
6ccf821c
DS		 1690 cxd2841er_unfreeze_regs(priv);
1691
a6dc60ff
KS		 1692 if (data[0] & 0x01) {
1693 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1694 min_index = 0;
1695 if (delsys == SYS_DVBS) {
1696 cn_data = s_cn_data;
1697 max_index = sizeof(s_cn_data) /
1698 sizeof(s_cn_data[0]) - 1;
1699 } else {
1700 cn_data = s2_cn_data;
1701 max_index = sizeof(s2_cn_data) /
1702 sizeof(s2_cn_data[0]) - 1;
1703 }
1704 if (value >= cn_data[min_index].value) {
1705 res = cn_data[min_index].cnr_x1000;
1706 goto done;
1707 }
1708 if (value <= cn_data[max_index].value) {
1709 res = cn_data[max_index].cnr_x1000;
1710 goto done;
1711 }
1712 while ((max_index - min_index) > 1) {
1713 index = (max_index + min_index) / 2;
1714 if (value == cn_data[index].value) {
1715 res = cn_data[index].cnr_x1000;
1716 goto done;
1717 } else if (value > cn_data[index].value)
1718 max_index = index;
1719 else
1720 min_index = index;
1721 if ((max_index - min_index) <= 1) {
1722 if (value == cn_data[max_index].value) {
1723 res = cn_data[max_index].cnr_x1000;
1724 goto done;
1725 } else {
1726 res = cn_data[min_index].cnr_x1000;
1727 goto done;
1728 }
1729 }
1730 }
1731 } else {
1732 dev_dbg(&priv->i2c->dev,
1733 "%s(): no data available\n", __func__);
e05b1872 1734 return -EINVAL;
a6dc60ff
KS		 1735 }
1736done:
e05b1872
AO		 1737 *snr = res;
1738 return 0;
1739}
1740
1741static uint32_t sony_log(uint32_t x)
1742{
1743 return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1744}
1745
1746static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1747{
1748 u32 reg;
1749 u8 data[2];
1750 enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1751
1752 *snr = 0;
1753 if (priv->state != STATE_ACTIVE_TC) {
1754 dev_dbg(&priv->i2c->dev,
1755 "%s(): invalid state %d\n",
1756 __func__, priv->state);
1757 return -EINVAL;
1758 }
1759
4a86bc10 1760 cxd2841er_freeze_regs(priv);
e05b1872
AO		 1761 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1762 cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1763 qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1764 cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
6ccf821c 1765 cxd2841er_unfreeze_regs(priv);
e05b1872
AO		 1766
1767 reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1768 if (reg == 0) {
1769 dev_dbg(&priv->i2c->dev,
1770 "%s(): reg value out of range\n", __func__);
1771 return 0;
1772 }
1773
1774 switch (qam) {
1775 case SONY_DVBC_CONSTELLATION_16QAM:
1776 case SONY_DVBC_CONSTELLATION_64QAM:
1777 case SONY_DVBC_CONSTELLATION_256QAM:
1778 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1779 if (reg < 126)
1780 reg = 126;
1781 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1782 break;
1783 case SONY_DVBC_CONSTELLATION_32QAM:
1784 case SONY_DVBC_CONSTELLATION_128QAM:
1785 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1786 if (reg < 69)
1787 reg = 69;
1788 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1789 break;
1790 default:
1791 return -EINVAL;
1792 }
1793
1794 return 0;
a6dc60ff
KS		 1795}
1796
1797static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1798{
1799 u32 reg;
1800 u8 data[2];
1801
1802 *snr = 0;
1803 if (priv->state != STATE_ACTIVE_TC) {
1804 dev_dbg(&priv->i2c->dev,
1805 "%s(): invalid state %d\n", __func__, priv->state);
1806 return -EINVAL;
1807 }
4a86bc10
AO		 1808
1809 cxd2841er_freeze_regs(priv);
a6dc60ff
KS		 1810 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1811 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
6ccf821c
DS		 1812 cxd2841er_unfreeze_regs(priv);
1813
a6dc60ff
KS		 1814 reg = ((u32)data[0] << 8) | (u32)data[1];
1815 if (reg == 0) {
1816 dev_dbg(&priv->i2c->dev,
1817 "%s(): reg value out of range\n", __func__);
1818 return 0;
1819 }
1820 if (reg > 4996)
1821 reg = 4996;
df61f828 1822 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
a6dc60ff
KS		 1823 return 0;
1824}
1825
c8946c8d 1826static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
a6dc60ff
KS		 1827{
1828 u32 reg;
1829 u8 data[2];
1830
1831 *snr = 0;
1832 if (priv->state != STATE_ACTIVE_TC) {
1833 dev_dbg(&priv->i2c->dev,
1834 "%s(): invalid state %d\n", __func__, priv->state);
1835 return -EINVAL;
1836 }
4a86bc10
AO		 1837
1838 cxd2841er_freeze_regs(priv);
a6dc60ff
KS		 1839 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1840 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
6ccf821c
DS		 1841 cxd2841er_unfreeze_regs(priv);
1842
a6dc60ff
KS		 1843 reg = ((u32)data[0] << 8) | (u32)data[1];
1844 if (reg == 0) {
1845 dev_dbg(&priv->i2c->dev,
1846 "%s(): reg value out of range\n", __func__);
1847 return 0;
1848 }
1849 if (reg > 10876)
1850 reg = 10876;
df61f828 1851 *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
a6dc60ff
KS		 1852 return 0;
1853}
1854
83808c23
AO		 1855static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1856{
1857 u32 reg;
1858 u8 data[2];
1859
1860 *snr = 0;
1861 if (priv->state != STATE_ACTIVE_TC) {
1862 dev_dbg(&priv->i2c->dev,
1863 "%s(): invalid state %d\n", __func__,
1864 priv->state);
1865 return -EINVAL;
1866 }
1867
4a86bc10 1868 cxd2841er_freeze_regs(priv);
83808c23
AO		 1869 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1870 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
6ccf821c
DS		 1871 cxd2841er_unfreeze_regs(priv);
1872
83808c23
AO		 1873 reg = ((u32)data[0] << 8) | (u32)data[1];
1874 if (reg == 0) {
1875 dev_dbg(&priv->i2c->dev,
1876 "%s(): reg value out of range\n", __func__);
1877 return 0;
1878 }
0854df79 1879 *snr = 10000 * (intlog10(reg) >> 24) - 9031;
83808c23
AO		 1880 return 0;
1881}
1882
d0998ce7
AO		 1883static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1884 u8 delsys)
1885{
1886 u8 data[2];
1887
1888 cxd2841er_write_reg(
1889 priv, I2C_SLVT, 0x00, 0x40);
1890 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1891 dev_dbg(&priv->i2c->dev,
1892 "%s(): AGC value=%u\n",
1893 __func__, (((u16)data[0] & 0x0F) << 8) |
1894 (u16)(data[1] & 0xFF));
1895 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1896}
1897
a6dc60ff
KS		 1898static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1899 u8 delsys)
1900{
1901 u8 data[2];
1902
1903 cxd2841er_write_reg(
1904 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1905 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
c5ea46da
AO		 1906 dev_dbg(&priv->i2c->dev,
1907 "%s(): AGC value=%u\n",
1908 __func__, (((u16)data[0] & 0x0F) << 8) |
1909 (u16)(data[1] & 0xFF));
a6dc60ff
KS		 1910 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1911}
1912
83808c23
AO		 1913static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1914 u8 delsys)
1915{
1916 u8 data[2];
1917
1918 cxd2841er_write_reg(
1919 priv, I2C_SLVT, 0x00, 0x60);
1920 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1921
1922 dev_dbg(&priv->i2c->dev,
1923 "%s(): AGC value=%u\n",
1924 __func__, (((u16)data[0] & 0x0F) << 8) |
1925 (u16)(data[1] & 0xFF));
1926 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1927}
1928
a6dc60ff
KS		 1929static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1930{
1931 u8 data[2];
1932
1933 /* Set SLV-T Bank : 0xA0 */
1934 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1935 /*
1936 * slave Bank Addr Bit Signal name
1937 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1938 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1939 */
1940 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1941 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1942}
1943
f1b26622 1944static void cxd2841er_read_ber(struct dvb_frontend *fe)
a6dc60ff
KS		 1945{
1946 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1947 struct cxd2841er_priv *priv = fe->demodulator_priv;
4216be14 1948 u32 ret, bit_error = 0, bit_count = 0;
a6dc60ff
KS		 1949
1950 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
a6dc60ff 1951 switch (p->delivery_system) {
a6f330cb
AO		 1952 case SYS_DVBC_ANNEX_A:
1953 case SYS_DVBC_ANNEX_B:
1954 case SYS_DVBC_ANNEX_C:
1955 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1956 break;
0854df79
AO		 1957 case SYS_ISDBT:
1958 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1959 break;
a6dc60ff 1960 case SYS_DVBS:
4216be14 1961 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
a6dc60ff
KS		 1962 break;
1963 case SYS_DVBS2:
4216be14 1964 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
a6dc60ff
KS		 1965 break;
1966 case SYS_DVBT:
4216be14 1967 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
f1b26622 1968 break;
a6dc60ff 1969 case SYS_DVBT2:
4216be14 1970 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
a6dc60ff 1971 break;
f1b26622
MCC		 1972 default:
1973 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 1974 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
f1b26622
MCC		 1975 return;
1976 }
1977
1978 if (!ret) {
1979 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
a6f330cb 1980 p->post_bit_error.stat[0].uvalue += bit_error;
4216be14 1981 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
a6f330cb 1982 p->post_bit_count.stat[0].uvalue += bit_count;
f1b26622
MCC		 1983 } else {
1984 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 1985 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 1986 }
a6dc60ff
KS		 1987}
1988
5fda1b65 1989static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
a6dc60ff
KS		 1990{
1991 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1992 struct cxd2841er_priv *priv = fe->demodulator_priv;
313a7dfb 1993 s32 strength;
a6dc60ff
KS		 1994
1995 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1996 switch (p->delivery_system) {
1997 case SYS_DVBT:
1998 case SYS_DVBT2:
5fda1b65
MCC		 1999 strength = cxd2841er_read_agc_gain_t_t2(priv,
2000 p->delivery_system);
2001 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2002 /* Formula was empirically determinated @ 410 MHz */
313a7dfb 2003 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
5fda1b65 2004 break; /* Code moved out of the function */
988bd281 2005 case SYS_DVBC_ANNEX_A:
997bdc0c
AO		 2006 case SYS_DVBC_ANNEX_B:
2007 case SYS_DVBC_ANNEX_C:
2008 strength = cxd2841er_read_agc_gain_c(priv,
988bd281 2009 p->delivery_system);
d12b791e
MCC		 2010 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2011 /*
2012 * Formula was empirically determinated via linear regression,
2013 * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2014 * stream modulated with QAM64
2015 */
313a7dfb 2016 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
988bd281 2017 break;
83808c23 2018 case SYS_ISDBT:
313a7dfb
MCC		 2019 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2020 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2021 /*
2022 * Formula was empirically determinated via linear regression,
2023 * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2024 */
2025 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
83808c23 2026 break;
a6dc60ff
KS		 2027 case SYS_DVBS:
2028 case SYS_DVBS2:
5fda1b65
MCC		 2029 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2030 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2031 p->strength.stat[0].uvalue = strength;
a6dc60ff
KS		 2032 break;
2033 default:
f1b26622 2034 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff
KS		 2035 break;
2036 }
a6dc60ff
KS		 2037}
2038
f1b26622 2039static void cxd2841er_read_snr(struct dvb_frontend *fe)
a6dc60ff
KS		 2040{
2041 u32 tmp = 0;
e05b1872 2042 int ret = 0;
a6dc60ff
KS		 2043 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2044 struct cxd2841er_priv *priv = fe->demodulator_priv;
2045
2046 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2047 switch (p->delivery_system) {
e05b1872
AO		 2048 case SYS_DVBC_ANNEX_A:
2049 case SYS_DVBC_ANNEX_B:
2050 case SYS_DVBC_ANNEX_C:
2051 ret = cxd2841er_read_snr_c(priv, &tmp);
2052 break;
a6dc60ff 2053 case SYS_DVBT:
e05b1872 2054 ret = cxd2841er_read_snr_t(priv, &tmp);
a6dc60ff
KS		 2055 break;
2056 case SYS_DVBT2:
e05b1872 2057 ret = cxd2841er_read_snr_t2(priv, &tmp);
a6dc60ff 2058 break;
83808c23 2059 case SYS_ISDBT:
e05b1872 2060 ret = cxd2841er_read_snr_i(priv, &tmp);
83808c23 2061 break;
a6dc60ff
KS		 2062 case SYS_DVBS:
2063 case SYS_DVBS2:
e05b1872 2064 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
a6dc60ff
KS		 2065 break;
2066 default:
2067 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2068 __func__, p->delivery_system);
f1b26622
MCC		 2069 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2070 return;
a6dc60ff 2071 }
f1b26622 2072
0854df79
AO		 2073 dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2074 __func__, (int32_t)tmp);
2075
e05b1872
AO		 2076 if (!ret) {
2077 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2078 p->cnr.stat[0].svalue = tmp;
2079 } else {
2080 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2081 }
a6dc60ff
KS		 2082}
2083
f1b26622 2084static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
a6dc60ff
KS		 2085{
2086 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2087 struct cxd2841er_priv *priv = fe->demodulator_priv;
4a86bc10 2088 u32 ucblocks = 0;
a6dc60ff
KS		 2089
2090 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2091 switch (p->delivery_system) {
a6f330cb
AO		 2092 case SYS_DVBC_ANNEX_A:
2093 case SYS_DVBC_ANNEX_B:
2094 case SYS_DVBC_ANNEX_C:
2095 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2096 break;
a6dc60ff 2097 case SYS_DVBT:
f1b26622 2098 cxd2841er_read_packet_errors_t(priv, &ucblocks);
a6dc60ff
KS		 2099 break;
2100 case SYS_DVBT2:
f1b26622 2101 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
a6dc60ff 2102 break;
83808c23 2103 case SYS_ISDBT:
f1b26622 2104 cxd2841er_read_packet_errors_i(priv, &ucblocks);
83808c23 2105 break;
a6dc60ff 2106 default:
f1b26622
MCC		 2107 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2108 return;
a6dc60ff 2109 }
4a86bc10 2110 dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
f1b26622
MCC		 2111
2112 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2113 p->block_error.stat[0].uvalue = ucblocks;
a6dc60ff
KS		 2114}
2115
2116static int cxd2841er_dvbt2_set_profile(
2117 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2118{
2119 u8 tune_mode;
2120 u8 seq_not2d_time;
2121
2122 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2123 switch (profile) {
2124 case DVBT2_PROFILE_BASE:
2125 tune_mode = 0x01;
6c77161a
AO		 2126 /* Set early unlock time */
2127 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
a6dc60ff
KS		 2128 break;
2129 case DVBT2_PROFILE_LITE:
2130 tune_mode = 0x05;
6c77161a
AO		 2131 /* Set early unlock time */
2132 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
a6dc60ff
KS		 2133 break;
2134 case DVBT2_PROFILE_ANY:
2135 tune_mode = 0x00;
6c77161a
AO		 2136 /* Set early unlock time */
2137 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
a6dc60ff
KS		 2138 break;
2139 default:
2140 return -EINVAL;
2141 }
2142 /* Set SLV-T Bank : 0x2E */
2143 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2144 /* Set profile and tune mode */
2145 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2146 /* Set SLV-T Bank : 0x2B */
2147 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2148 /* Set early unlock detection time */
2149 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2150 return 0;
2151}
2152
2153static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2154 u8 is_auto, u8 plp_id)
2155{
2156 if (is_auto) {
2157 dev_dbg(&priv->i2c->dev,
2158 "%s() using auto PLP selection\n", __func__);
2159 } else {
2160 dev_dbg(&priv->i2c->dev,
2161 "%s() using manual PLP selection, ID %d\n",
2162 __func__, plp_id);
2163 }
2164 /* Set SLV-T Bank : 0x23 */
2165 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2166 if (!is_auto) {
2167 /* Manual PLP selection mode. Set the data PLP Id. */
2168 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2169 }
2170 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2171 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2172 return 0;
2173}
2174
2175static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2176 u32 bandwidth)
2177{
4b866c4e 2178 u32 iffreq, ifhz;
6c77161a
AO		 2179 u8 data[MAX_WRITE_REGSIZE];
2180
2181 const uint8_t nominalRate8bw[3][5] = {
2182 /* TRCG Nominal Rate [37:0] */
2183 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2184 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2185 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2186 };
2187
2188 const uint8_t nominalRate7bw[3][5] = {
2189 /* TRCG Nominal Rate [37:0] */
2190 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2191 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2192 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2193 };
2194
2195 const uint8_t nominalRate6bw[3][5] = {
2196 /* TRCG Nominal Rate [37:0] */
2197 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2198 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2199 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2200 };
2201
2202 const uint8_t nominalRate5bw[3][5] = {
2203 /* TRCG Nominal Rate [37:0] */
2204 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2205 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2206 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2207 };
2208
2209 const uint8_t nominalRate17bw[3][5] = {
2210 /* TRCG Nominal Rate [37:0] */
2211 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2212 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2213 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
2214 };
2215
2216 const uint8_t itbCoef8bw[3][14] = {
2217 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2218 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2219 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2220 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2221 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2222 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2223 };
2224
2225 const uint8_t itbCoef7bw[3][14] = {
2226 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2227 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2228 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2229 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2230 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2231 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2232 };
2233
2234 const uint8_t itbCoef6bw[3][14] = {
2235 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2236 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2237 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2238 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2239 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2240 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2241 };
2242
2243 const uint8_t itbCoef5bw[3][14] = {
2244 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2245 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2246 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2247 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2248 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2249 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2250 };
2251
2252 const uint8_t itbCoef17bw[3][14] = {
2253 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2254 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2255 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2256 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
2257 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2258 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
2259 };
2260
2261 /* Set SLV-T Bank : 0x20 */
2262 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
a6dc60ff 2263
a6dc60ff
KS		 2264 switch (bandwidth) {
2265 case 8000000:
6c77161a
AO		 2266 /* <Timing Recovery setting> */
2267 cxd2841er_write_regs(priv, I2C_SLVT,
2268 0x9F, nominalRate8bw[priv->xtal], 5);
2269
2270 /* Set SLV-T Bank : 0x27 */
2271 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2272 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2273 0x7a, 0x00, 0x0f);
2274
2275 /* Set SLV-T Bank : 0x10 */
2276 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2277
2278 /* Group delay equaliser settings for
2279 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2280 */
7afe510a
DS		 2281 if (priv->flags & CXD2841ER_ASCOT)
2282 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2283 0xA6, itbCoef8bw[priv->xtal], 14);
2284 /* <IF freq setting> */
4b866c4e
DS		 2285 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2286 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2287 data[0] = (u8) ((iffreq >> 16) & 0xff);
2288 data[1] = (u8)((iffreq >> 8) & 0xff);
2289 data[2] = (u8)(iffreq & 0xff);
2290 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2291 /* System bandwidth setting */
2292 cxd2841er_set_reg_bits(
2293 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
a6dc60ff
KS		 2294 break;
2295 case 7000000:
6c77161a
AO		 2296 /* <Timing Recovery setting> */
2297 cxd2841er_write_regs(priv, I2C_SLVT,
2298 0x9F, nominalRate7bw[priv->xtal], 5);
2299
2300 /* Set SLV-T Bank : 0x27 */
2301 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2302 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2303 0x7a, 0x00, 0x0f);
2304
2305 /* Set SLV-T Bank : 0x10 */
2306 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2307
2308 /* Group delay equaliser settings for
2309 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2310 */
7afe510a
DS		 2311 if (priv->flags & CXD2841ER_ASCOT)
2312 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2313 0xA6, itbCoef7bw[priv->xtal], 14);
2314 /* <IF freq setting> */
4b866c4e
DS		 2315 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2316 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2317 data[0] = (u8) ((iffreq >> 16) & 0xff);
2318 data[1] = (u8)((iffreq >> 8) & 0xff);
2319 data[2] = (u8)(iffreq & 0xff);
2320 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2321 /* System bandwidth setting */
2322 cxd2841er_set_reg_bits(
2323 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
a6dc60ff
KS		 2324 break;
2325 case 6000000:
6c77161a
AO		 2326 /* <Timing Recovery setting> */
2327 cxd2841er_write_regs(priv, I2C_SLVT,
2328 0x9F, nominalRate6bw[priv->xtal], 5);
2329
2330 /* Set SLV-T Bank : 0x27 */
2331 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2332 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2333 0x7a, 0x00, 0x0f);
2334
2335 /* Set SLV-T Bank : 0x10 */
2336 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2337
2338 /* Group delay equaliser settings for
2339 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2340 */
7afe510a
DS		 2341 if (priv->flags & CXD2841ER_ASCOT)
2342 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2343 0xA6, itbCoef6bw[priv->xtal], 14);
2344 /* <IF freq setting> */
4b866c4e
DS		 2345 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2346 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2347 data[0] = (u8) ((iffreq >> 16) & 0xff);
2348 data[1] = (u8)((iffreq >> 8) & 0xff);
2349 data[2] = (u8)(iffreq & 0xff);
2350 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2351 /* System bandwidth setting */
2352 cxd2841er_set_reg_bits(
2353 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
a6dc60ff
KS		 2354 break;
2355 case 5000000:
6c77161a
AO		 2356 /* <Timing Recovery setting> */
2357 cxd2841er_write_regs(priv, I2C_SLVT,
2358 0x9F, nominalRate5bw[priv->xtal], 5);
2359
2360 /* Set SLV-T Bank : 0x27 */
2361 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2362 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2363 0x7a, 0x00, 0x0f);
2364
2365 /* Set SLV-T Bank : 0x10 */
2366 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2367
2368 /* Group delay equaliser settings for
2369 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2370 */
7afe510a
DS		 2371 if (priv->flags & CXD2841ER_ASCOT)
2372 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2373 0xA6, itbCoef5bw[priv->xtal], 14);
2374 /* <IF freq setting> */
4b866c4e
DS		 2375 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2376 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2377 data[0] = (u8) ((iffreq >> 16) & 0xff);
2378 data[1] = (u8)((iffreq >> 8) & 0xff);
2379 data[2] = (u8)(iffreq & 0xff);
2380 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2381 /* System bandwidth setting */
2382 cxd2841er_set_reg_bits(
2383 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
a6dc60ff
KS		 2384 break;
2385 case 1712000:
6c77161a
AO		 2386 /* <Timing Recovery setting> */
2387 cxd2841er_write_regs(priv, I2C_SLVT,
2388 0x9F, nominalRate17bw[priv->xtal], 5);
2389
2390 /* Set SLV-T Bank : 0x27 */
2391 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2392 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2393 0x7a, 0x03, 0x0f);
2394
2395 /* Set SLV-T Bank : 0x10 */
2396 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2397
2398 /* Group delay equaliser settings for
2399 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2400 */
7afe510a
DS		 2401 if (priv->flags & CXD2841ER_ASCOT)
2402 cxd2841er_write_regs(priv, I2C_SLVT,
6c77161a
AO		 2403 0xA6, itbCoef17bw[priv->xtal], 14);
2404 /* <IF freq setting> */
4b866c4e
DS		 2405 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2406 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
6c77161a
AO		 2407 data[0] = (u8) ((iffreq >> 16) & 0xff);
2408 data[1] = (u8)((iffreq >> 8) & 0xff);
2409 data[2] = (u8)(iffreq & 0xff);
2410 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2411 /* System bandwidth setting */
2412 cxd2841er_set_reg_bits(
2413 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
a6dc60ff
KS		 2414 break;
2415 default:
2416 return -EINVAL;
2417 }
a6dc60ff
KS		 2418 return 0;
2419}
2420
2421static int cxd2841er_sleep_tc_to_active_t_band(
2422 struct cxd2841er_priv *priv, u32 bandwidth)
2423{
83808c23 2424 u8 data[MAX_WRITE_REGSIZE];
4b866c4e 2425 u32 iffreq, ifhz;
83808c23
AO		 2426 u8 nominalRate8bw[3][5] = {
2427 /* TRCG Nominal Rate [37:0] */
2428 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2429 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2430 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2431 };
2432 u8 nominalRate7bw[3][5] = {
2433 /* TRCG Nominal Rate [37:0] */
2434 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2435 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2436 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2437 };
2438 u8 nominalRate6bw[3][5] = {
2439 /* TRCG Nominal Rate [37:0] */
2440 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2441 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2442 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2443 };
2444 u8 nominalRate5bw[3][5] = {
2445 /* TRCG Nominal Rate [37:0] */
2446 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2447 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2448 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2449 };
a6dc60ff 2450
83808c23
AO		 2451 u8 itbCoef8bw[3][14] = {
2452 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2453 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2454 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2455 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2456 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2457 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2458 };
2459 u8 itbCoef7bw[3][14] = {
2460 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2461 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2462 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2463 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2464 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2465 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2466 };
2467 u8 itbCoef6bw[3][14] = {
2468 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2469 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2470 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2471 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2472 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2473 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2474 };
2475 u8 itbCoef5bw[3][14] = {
2476 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2477 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2478 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2479 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2480 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2481 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2482 };
2483
2484 /* Set SLV-T Bank : 0x13 */
a6dc60ff
KS		 2485 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2486 /* Echo performance optimization setting */
83808c23
AO		 2487 data[0] = 0x01;
2488 data[1] = 0x14;
2489 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2490
2491 /* Set SLV-T Bank : 0x10 */
a6dc60ff
KS		 2492 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2493
2494 switch (bandwidth) {
2495 case 8000000:
83808c23
AO		 2496 /* <Timing Recovery setting> */
2497 cxd2841er_write_regs(priv, I2C_SLVT,
2498 0x9F, nominalRate8bw[priv->xtal], 5);
2499 /* Group delay equaliser settings for
2500 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2501 */
7afe510a
DS		 2502 if (priv->flags & CXD2841ER_ASCOT)
2503 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2504 0xA6, itbCoef8bw[priv->xtal], 14);
2505 /* <IF freq setting> */
4b866c4e
DS		 2506 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2507 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2508 data[0] = (u8) ((iffreq >> 16) & 0xff);
2509 data[1] = (u8)((iffreq >> 8) & 0xff);
2510 data[2] = (u8)(iffreq & 0xff);
2511 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2512 /* System bandwidth setting */
2513 cxd2841er_set_reg_bits(
2514 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2515
2516 /* Demod core latency setting */
2517 if (priv->xtal == SONY_XTAL_24000) {
2518 data[0] = 0x15;
2519 data[1] = 0x28;
2520 } else {
2521 data[0] = 0x01;
2522 data[1] = 0xE0;
2523 }
2524 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2525
2526 /* Notch filter setting */
2527 data[0] = 0x01;
2528 data[1] = 0x02;
2529 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2530 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2531 break;
2532 case 7000000:
83808c23
AO		 2533 /* <Timing Recovery setting> */
2534 cxd2841er_write_regs(priv, I2C_SLVT,
2535 0x9F, nominalRate7bw[priv->xtal], 5);
2536 /* Group delay equaliser settings for
2537 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2538 */
7afe510a
DS		 2539 if (priv->flags & CXD2841ER_ASCOT)
2540 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2541 0xA6, itbCoef7bw[priv->xtal], 14);
2542 /* <IF freq setting> */
4b866c4e
DS		 2543 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2544 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2545 data[0] = (u8) ((iffreq >> 16) & 0xff);
2546 data[1] = (u8)((iffreq >> 8) & 0xff);
2547 data[2] = (u8)(iffreq & 0xff);
2548 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2549 /* System bandwidth setting */
2550 cxd2841er_set_reg_bits(
2551 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2552
2553 /* Demod core latency setting */
2554 if (priv->xtal == SONY_XTAL_24000) {
2555 data[0] = 0x1F;
2556 data[1] = 0xF8;
2557 } else {
2558 data[0] = 0x12;
2559 data[1] = 0xF8;
2560 }
2561 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2562
2563 /* Notch filter setting */
2564 data[0] = 0x00;
2565 data[1] = 0x03;
2566 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2567 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2568 break;
2569 case 6000000:
83808c23
AO		 2570 /* <Timing Recovery setting> */
2571 cxd2841er_write_regs(priv, I2C_SLVT,
2572 0x9F, nominalRate6bw[priv->xtal], 5);
2573 /* Group delay equaliser settings for
2574 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2575 */
7afe510a
DS		 2576 if (priv->flags & CXD2841ER_ASCOT)
2577 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2578 0xA6, itbCoef6bw[priv->xtal], 14);
2579 /* <IF freq setting> */
4b866c4e
DS		 2580 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2581 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2582 data[0] = (u8) ((iffreq >> 16) & 0xff);
2583 data[1] = (u8)((iffreq >> 8) & 0xff);
2584 data[2] = (u8)(iffreq & 0xff);
2585 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2586 /* System bandwidth setting */
2587 cxd2841er_set_reg_bits(
2588 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2589
2590 /* Demod core latency setting */
2591 if (priv->xtal == SONY_XTAL_24000) {
2592 data[0] = 0x25;
2593 data[1] = 0x4C;
2594 } else {
2595 data[0] = 0x1F;
2596 data[1] = 0xDC;
2597 }
2598 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2599
2600 /* Notch filter setting */
2601 data[0] = 0x00;
2602 data[1] = 0x03;
2603 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2604 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2605 break;
2606 case 5000000:
83808c23
AO		 2607 /* <Timing Recovery setting> */
2608 cxd2841er_write_regs(priv, I2C_SLVT,
2609 0x9F, nominalRate5bw[priv->xtal], 5);
2610 /* Group delay equaliser settings for
2611 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2612 */
7afe510a
DS		 2613 if (priv->flags & CXD2841ER_ASCOT)
2614 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2615 0xA6, itbCoef5bw[priv->xtal], 14);
2616 /* <IF freq setting> */
4b866c4e
DS		 2617 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2618 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2619 data[0] = (u8) ((iffreq >> 16) & 0xff);
2620 data[1] = (u8)((iffreq >> 8) & 0xff);
2621 data[2] = (u8)(iffreq & 0xff);
2622 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2623 /* System bandwidth setting */
2624 cxd2841er_set_reg_bits(
2625 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2626
2627 /* Demod core latency setting */
2628 if (priv->xtal == SONY_XTAL_24000) {
2629 data[0] = 0x2C;
2630 data[1] = 0xC2;
2631 } else {
2632 data[0] = 0x26;
2633 data[1] = 0x3C;
2634 }
2635 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2636
2637 /* Notch filter setting */
2638 data[0] = 0x00;
2639 data[1] = 0x03;
2640 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2641 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2642 break;
2643 }
2644
2645 return 0;
2646}
2647
2648static int cxd2841er_sleep_tc_to_active_i_band(
2649 struct cxd2841er_priv *priv, u32 bandwidth)
2650{
4b866c4e 2651 u32 iffreq, ifhz;
83808c23
AO		 2652 u8 data[3];
2653
2654 /* TRCG Nominal Rate */
2655 u8 nominalRate8bw[3][5] = {
2656 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2657 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2658 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2659 };
2660
2661 u8 nominalRate7bw[3][5] = {
2662 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2663 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2664 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2665 };
2666
2667 u8 nominalRate6bw[3][5] = {
2668 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2669 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2670 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2671 };
2672
2673 u8 itbCoef8bw[3][14] = {
2674 {0x00}, /* 20.5MHz XTal */
2675 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2676 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2677 {0x0}, /* 41MHz XTal */
2678 };
2679
2680 u8 itbCoef7bw[3][14] = {
2681 {0x00}, /* 20.5MHz XTal */
2682 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2683 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2684 {0x00}, /* 41MHz XTal */
2685 };
2686
2687 u8 itbCoef6bw[3][14] = {
2688 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2689 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2690 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2691 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2692 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2693 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2694 };
2695
2696 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2697 /* Set SLV-T Bank : 0x10 */
2698 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2699
2700 /* 20.5/41MHz Xtal support is not available
2701 * on ISDB-T 7MHzBW and 8MHzBW
2702 */
2703 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2704 dev_err(&priv->i2c->dev,
2705 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2706 __func__, bandwidth);
2707 return -EINVAL;
2708 }
2709
2710 switch (bandwidth) {
2711 case 8000000:
2712 /* TRCG Nominal Rate */
2713 cxd2841er_write_regs(priv, I2C_SLVT,
2714 0x9F, nominalRate8bw[priv->xtal], 5);
2715 /* Group delay equaliser settings for ASCOT tuners optimized */
7afe510a
DS		 2716 if (priv->flags & CXD2841ER_ASCOT)
2717 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2718 0xA6, itbCoef8bw[priv->xtal], 14);
2719
2720 /* IF freq setting */
4b866c4e
DS		 2721 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2722 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2723 data[0] = (u8) ((iffreq >> 16) & 0xff);
2724 data[1] = (u8)((iffreq >> 8) & 0xff);
2725 data[2] = (u8)(iffreq & 0xff);
2726 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2727
2728 /* System bandwidth setting */
2729 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2730
2731 /* Demod core latency setting */
2732 data[0] = 0x13;
2733 data[1] = 0xFC;
2734 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2735
2736 /* Acquisition optimization setting */
2737 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2738 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2739 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2740 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2741 break;
2742 case 7000000:
2743 /* TRCG Nominal Rate */
2744 cxd2841er_write_regs(priv, I2C_SLVT,
2745 0x9F, nominalRate7bw[priv->xtal], 5);
2746 /* Group delay equaliser settings for ASCOT tuners optimized */
7afe510a
DS		 2747 if (priv->flags & CXD2841ER_ASCOT)
2748 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2749 0xA6, itbCoef7bw[priv->xtal], 14);
2750
2751 /* IF freq setting */
4b866c4e
DS		 2752 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2753 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2754 data[0] = (u8) ((iffreq >> 16) & 0xff);
2755 data[1] = (u8)((iffreq >> 8) & 0xff);
2756 data[2] = (u8)(iffreq & 0xff);
2757 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2758
2759 /* System bandwidth setting */
2760 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2761
2762 /* Demod core latency setting */
2763 data[0] = 0x1A;
2764 data[1] = 0xFA;
2765 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2766
2767 /* Acquisition optimization setting */
2768 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2769 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2770 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2771 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2772 break;
2773 case 6000000:
2774 /* TRCG Nominal Rate */
2775 cxd2841er_write_regs(priv, I2C_SLVT,
2776 0x9F, nominalRate6bw[priv->xtal], 5);
2777 /* Group delay equaliser settings for ASCOT tuners optimized */
7afe510a
DS		 2778 if (priv->flags & CXD2841ER_ASCOT)
2779 cxd2841er_write_regs(priv, I2C_SLVT,
83808c23
AO		 2780 0xA6, itbCoef6bw[priv->xtal], 14);
2781
2782 /* IF freq setting */
4b866c4e
DS		 2783 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2784 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
83808c23
AO		 2785 data[0] = (u8) ((iffreq >> 16) & 0xff);
2786 data[1] = (u8)((iffreq >> 8) & 0xff);
2787 data[2] = (u8)(iffreq & 0xff);
2788 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2789
2790 /* System bandwidth setting */
2791 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2792
2793 /* Demod core latency setting */
2794 if (priv->xtal == SONY_XTAL_24000) {
2795 data[0] = 0x1F;
2796 data[1] = 0x79;
2797 } else {
2798 data[0] = 0x1A;
2799 data[1] = 0xE2;
2800 }
2801 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2802
2803 /* Acquisition optimization setting */
2804 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2805 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2806 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2807 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
a6dc60ff
KS		 2808 break;
2809 default:
2810 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
83808c23 2811 __func__, bandwidth);
a6dc60ff
KS		 2812 return -EINVAL;
2813 }
a6dc60ff
KS		 2814 return 0;
2815}
2816
2817static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2818 u32 bandwidth)
2819{
2820 u8 bw7_8mhz_b10_a6[] = {
2821 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2822 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2823 u8 bw6mhz_b10_a6[] = {
2824 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2825 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2826 u8 b10_b6[3];
4b866c4e 2827 u32 iffreq, ifhz;
a6dc60ff 2828
af4cc462
AO		 2829 if (bandwidth != 6000000 &&
2830 bandwidth != 7000000 &&
2831 bandwidth != 8000000) {
2832 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2833 __func__, bandwidth);
2834 bandwidth = 8000000;
2835 }
2836
3f3b48a0 2837 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
a6dc60ff
KS		 2838 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2839 switch (bandwidth) {
2840 case 8000000:
2841 case 7000000:
7afe510a
DS		 2842 if (priv->flags & CXD2841ER_ASCOT)
2843 cxd2841er_write_regs(
2844 priv, I2C_SLVT, 0xa6,
2845 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
4b866c4e
DS		 2846 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2847 iffreq = cxd2841er_calc_iffreq(ifhz);
a6dc60ff
KS		 2848 break;
2849 case 6000000:
7afe510a
DS		 2850 if (priv->flags & CXD2841ER_ASCOT)
2851 cxd2841er_write_regs(
2852 priv, I2C_SLVT, 0xa6,
2853 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
4b866c4e
DS		 2854 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2855 iffreq = cxd2841er_calc_iffreq(ifhz);
a6dc60ff
KS		 2856 break;
2857 default:
3f3b48a0 2858 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
a6dc60ff
KS		 2859 __func__, bandwidth);
2860 return -EINVAL;
2861 }
2862 /* <IF freq setting> */
2863 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2864 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2865 b10_b6[2] = (u8)(iffreq & 0xff);
2866 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2867 /* Set SLV-T Bank : 0x11 */
2868 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2869 switch (bandwidth) {
2870 case 8000000:
2871 case 7000000:
2872 cxd2841er_set_reg_bits(
2873 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2874 break;
2875 case 6000000:
2876 cxd2841er_set_reg_bits(
2877 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2878 break;
2879 }
2880 /* Set SLV-T Bank : 0x40 */
2881 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2882 switch (bandwidth) {
2883 case 8000000:
2884 cxd2841er_set_reg_bits(
2885 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2886 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2887 break;
2888 case 7000000:
2889 cxd2841er_set_reg_bits(
2890 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2891 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2892 break;
2893 case 6000000:
2894 cxd2841er_set_reg_bits(
2895 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2896 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2897 break;
2898 }
2899 return 0;
2900}
2901
2902static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2903 u32 bandwidth)
2904{
2905 u8 data[2] = { 0x09, 0x54 };
83808c23 2906 u8 data24m[3] = {0xDC, 0x6C, 0x00};
a6dc60ff
KS		 2907
2908 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2909 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2910 /* Set SLV-X Bank : 0x00 */
2911 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2912 /* Set demod mode */
2913 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2914 /* Set SLV-T Bank : 0x00 */
2915 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2916 /* Enable demod clock */
2917 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2918 /* Disable RF level monitor */
2919 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2920 /* Enable ADC clock */
2921 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2922 /* Enable ADC 1 */
2923 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
83808c23
AO		 2924 /* Enable ADC 2 & 3 */
2925 if (priv->xtal == SONY_XTAL_41000) {
2926 data[0] = 0x0A;
2927 data[1] = 0xD4;
2928 }
a6dc60ff
KS		 2929 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2930 /* Enable ADC 4 */
2931 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2932 /* Set SLV-T Bank : 0x10 */
2933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2934 /* IFAGC gain settings */
2935 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2936 /* Set SLV-T Bank : 0x11 */
2937 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2938 /* BBAGC TARGET level setting */
2939 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2940 /* Set SLV-T Bank : 0x10 */
2941 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
7afe510a
DS		 2942 /* ASCOT setting */
2943 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2944 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
a6dc60ff
KS		 2945 /* Set SLV-T Bank : 0x18 */
2946 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2947 /* Pre-RS BER moniter setting */
2948 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2949 /* FEC Auto Recovery setting */
2950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2951 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2952 /* Set SLV-T Bank : 0x00 */
2953 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2954 /* TSIF setting */
2955 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2956 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
83808c23
AO		 2957
2958 if (priv->xtal == SONY_XTAL_24000) {
2959 /* Set SLV-T Bank : 0x10 */
2960 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2961 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2962 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2963 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2964 }
2965
a6dc60ff
KS		 2966 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2967 /* Set SLV-T Bank : 0x00 */
2968 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2969 /* Disable HiZ Setting 1 */
2970 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2971 /* Disable HiZ Setting 2 */
2972 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2973 priv->state = STATE_ACTIVE_TC;
2974 return 0;
2975}
2976
2977static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2978 u32 bandwidth)
2979{
6c77161a 2980 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff
KS		 2981
2982 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2983 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2984 /* Set SLV-X Bank : 0x00 */
2985 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2986 /* Set demod mode */
2987 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2988 /* Set SLV-T Bank : 0x00 */
2989 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2990 /* Enable demod clock */
2991 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2992 /* Disable RF level monitor */
6c77161a 2993 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
a6dc60ff
KS		 2994 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2995 /* Enable ADC clock */
2996 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2997 /* Enable ADC 1 */
2998 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
6c77161a
AO		 2999
3000 if (priv->xtal == SONY_XTAL_41000) {
3001 data[0] = 0x0A;
3002 data[1] = 0xD4;
3003 } else {
3004 data[0] = 0x09;
3005 data[1] = 0x54;
3006 }
3007
a6dc60ff
KS		 3008 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3009 /* Enable ADC 4 */
3010 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3011 /* Set SLV-T Bank : 0x10 */
3012 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3013 /* IFAGC gain settings */
3014 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3015 /* Set SLV-T Bank : 0x11 */
3016 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3017 /* BBAGC TARGET level setting */
3018 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3019 /* Set SLV-T Bank : 0x10 */
3020 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
7afe510a
DS		 3021 /* ASCOT setting */
3022 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3023 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
a6dc60ff
KS		 3024 /* Set SLV-T Bank : 0x20 */
3025 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3026 /* Acquisition optimization setting */
3027 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3028 /* Set SLV-T Bank : 0x2b */
3029 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3030 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
6c77161a
AO		 3031 /* Set SLV-T Bank : 0x23 */
3032 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3033 /* L1 Control setting */
3034 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
a6dc60ff
KS		 3035 /* Set SLV-T Bank : 0x00 */
3036 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3037 /* TSIF setting */
3038 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3039 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3040 /* DVB-T2 initial setting */
3041 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3042 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3043 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3044 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3045 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3046 /* Set SLV-T Bank : 0x2a */
3047 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3048 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3049 /* Set SLV-T Bank : 0x2b */
3050 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3051 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3052
6c77161a
AO		 3053 /* 24MHz Xtal setting */
3054 if (priv->xtal == SONY_XTAL_24000) {
3055 /* Set SLV-T Bank : 0x11 */
3056 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3057 data[0] = 0xEB;
3058 data[1] = 0x03;
3059 data[2] = 0x3B;
3060 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3061
3062 /* Set SLV-T Bank : 0x20 */
3063 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3064 data[0] = 0x5E;
3065 data[1] = 0x5E;
3066 data[2] = 0x47;
3067 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3068
3069 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3070
3071 data[0] = 0x3F;
3072 data[1] = 0xFF;
3073 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3074
3075 /* Set SLV-T Bank : 0x24 */
3076 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3077 data[0] = 0x0B;
3078 data[1] = 0x72;
3079 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3080
3081 data[0] = 0x93;
3082 data[1] = 0xF3;
3083 data[2] = 0x00;
3084 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3085
3086 data[0] = 0x05;
3087 data[1] = 0xB8;
3088 data[2] = 0xD8;
3089 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3090
3091 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3092
3093 /* Set SLV-T Bank : 0x25 */
3094 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3095 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3096
3097 /* Set SLV-T Bank : 0x27 */
3098 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3099 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3100
3101 /* Set SLV-T Bank : 0x2B */
3102 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3103 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3104 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3105
3106 /* Set SLV-T Bank : 0x2D */
3107 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3108 data[0] = 0x89;
3109 data[1] = 0x89;
3110 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3111
3112 /* Set SLV-T Bank : 0x5E */
3113 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3114 data[0] = 0x24;
3115 data[1] = 0x95;
3116 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3117 }
3118
a6dc60ff
KS		 3119 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3120
3121 /* Set SLV-T Bank : 0x00 */
3122 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3123 /* Disable HiZ Setting 1 */
3124 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3125 /* Disable HiZ Setting 2 */
3126 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3127 priv->state = STATE_ACTIVE_TC;
3128 return 0;
3129}
3130
83808c23
AO		 3131/* ISDB-Tb part */
3132static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3133 u32 bandwidth)
3134{
3135 u8 data[2] = { 0x09, 0x54 };
3136 u8 data24m[2] = {0x60, 0x00};
3137 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3138
3139 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3140 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3141 /* Set SLV-X Bank : 0x00 */
3142 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3143 /* Set demod mode */
3144 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3145 /* Set SLV-T Bank : 0x00 */
3146 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3147 /* Enable demod clock */
3148 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3149 /* Enable RF level monitor */
3150 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3151 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3152 /* Enable ADC clock */
3153 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3154 /* Enable ADC 1 */
3155 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3156 /* xtal freq 20.5MHz or 24M */
3157 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3158 /* Enable ADC 4 */
3159 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
7afe510a
DS		 3160 /* ASCOT setting */
3161 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3162 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
83808c23
AO		 3163 /* FEC Auto Recovery setting */
3164 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3165 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3166 /* ISDB-T initial setting */
3167 /* Set SLV-T Bank : 0x00 */
3168 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3169 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3170 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3171 /* Set SLV-T Bank : 0x10 */
3172 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3173 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3174 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3175 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3176 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3177 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3178 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3179 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3180 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3181 /* Set SLV-T Bank : 0x15 */
3182 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3183 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3184 /* Set SLV-T Bank : 0x1E */
3185 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3186 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3187 /* Set SLV-T Bank : 0x63 */
3188 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3189 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3190
3191 /* for xtal 24MHz */
3192 /* Set SLV-T Bank : 0x10 */
3193 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3194 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3195 /* Set SLV-T Bank : 0x60 */
3196 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3197 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3198
3199 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3200 /* Set SLV-T Bank : 0x00 */
3201 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3202 /* Disable HiZ Setting 1 */
3203 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3204 /* Disable HiZ Setting 2 */
3205 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3206 priv->state = STATE_ACTIVE_TC;
3207 return 0;
3208}
3209
a6dc60ff
KS		 3210static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3211 u32 bandwidth)
3212{
3213 u8 data[2] = { 0x09, 0x54 };
3214
3215 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3216 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3217 /* Set SLV-X Bank : 0x00 */
3218 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3219 /* Set demod mode */
3220 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3221 /* Set SLV-T Bank : 0x00 */
3222 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3223 /* Enable demod clock */
3224 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3225 /* Disable RF level monitor */
4a86bc10 3226 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
a6dc60ff
KS		 3227 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3228 /* Enable ADC clock */
3229 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3230 /* Enable ADC 1 */
3231 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3232 /* xtal freq 20.5MHz */
3233 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3234 /* Enable ADC 4 */
3235 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3236 /* Set SLV-T Bank : 0x10 */
3237 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3238 /* IFAGC gain settings */
3239 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3240 /* Set SLV-T Bank : 0x11 */
3241 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3242 /* BBAGC TARGET level setting */
3243 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3244 /* Set SLV-T Bank : 0x10 */
3245 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
7afe510a
DS		 3246 /* ASCOT setting */
3247 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3248 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
a6dc60ff
KS		 3249 /* Set SLV-T Bank : 0x40 */
3250 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3251 /* Demod setting */
3252 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3253 /* Set SLV-T Bank : 0x00 */
3254 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3255 /* TSIF setting */
3256 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3257 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3258
3f3b48a0 3259 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
a6dc60ff
KS		 3260 /* Set SLV-T Bank : 0x00 */
3261 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3262 /* Disable HiZ Setting 1 */
3263 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3264 /* Disable HiZ Setting 2 */
3265 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3266 priv->state = STATE_ACTIVE_TC;
3267 return 0;
3268}
3269
7e3e68bc
MCC		 3270static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3271 struct dtv_frontend_properties *p)
a6dc60ff
KS		 3272{
3273 enum fe_status status = 0;
a6dc60ff 3274 struct cxd2841er_priv *priv = fe->demodulator_priv;
a6dc60ff
KS		 3275
3276 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3277 if (priv->state == STATE_ACTIVE_S)
3278 cxd2841er_read_status_s(fe, &status);
3279 else if (priv->state == STATE_ACTIVE_TC)
3280 cxd2841er_read_status_tc(fe, &status);
3281
8982735f
DS		 3282 if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3283 cxd2841er_read_signal_strength(fe);
3284 else
3285 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
d0e20e13 3286
a6dc60ff 3287 if (status & FE_HAS_LOCK) {
f1b26622
MCC		 3288 cxd2841er_read_snr(fe);
3289 cxd2841er_read_ucblocks(fe);
d0e20e13 3290
f1b26622 3291 cxd2841er_read_ber(fe);
a6dc60ff 3292 } else {
a6dc60ff 3293 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 3294 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 3295 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 3296 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff
KS		 3297 }
3298 return 0;
3299}
3300
3301static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3302{
3303 int ret = 0, i, timeout, carr_offset;
3304 enum fe_status status;
3305 struct cxd2841er_priv *priv = fe->demodulator_priv;
3306 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3307 u32 symbol_rate = p->symbol_rate/1000;
3308
83808c23 3309 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
a6dc60ff
KS		 3310 __func__,
3311 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
83808c23 3312 p->frequency, symbol_rate, priv->xtal);
763f857e
DS		 3313
3314 if (priv->flags & CXD2841ER_EARLY_TUNE)
3315 cxd2841er_tuner_set(fe);
3316
a6dc60ff
KS		 3317 switch (priv->state) {
3318 case STATE_SLEEP_S:
3319 ret = cxd2841er_sleep_s_to_active_s(
3320 priv, p->delivery_system, symbol_rate);
3321 break;
3322 case STATE_ACTIVE_S:
3323 ret = cxd2841er_retune_active(priv, p);
3324 break;
3325 default:
3326 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3327 __func__, priv->state);
3328 ret = -EINVAL;
3329 goto done;
3330 }
3331 if (ret) {
3332 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3333 goto done;
3334 }
c7518d13 3335
763f857e
DS		 3336 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3337 cxd2841er_tuner_set(fe);
c7518d13 3338
a6dc60ff
KS		 3339 cxd2841er_tune_done(priv);
3340 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3341 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3342 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3343 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3344 cxd2841er_read_status_s(fe, &status);
3345 if (status & FE_HAS_LOCK)
3346 break;
3347 }
3348 if (status & FE_HAS_LOCK) {
3349 if (cxd2841er_get_carrier_offset_s_s2(
3350 priv, &carr_offset)) {
3351 ret = -EINVAL;
3352 goto done;
3353 }
3354 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3355 __func__, carr_offset);
3356 }
3357done:
d0e20e13
MCC		 3358 /* Reset stats */
3359 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3360 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3361 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3362 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14 3363 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
d0e20e13 3364
a6dc60ff
KS		 3365 return ret;
3366}
3367
3368static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3369{
3370 int ret = 0, timeout;
3371 enum fe_status status;
3372 struct cxd2841er_priv *priv = fe->demodulator_priv;
3373 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3374
3f3b48a0
AO		 3375 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3376 __func__, p->delivery_system, p->bandwidth_hz);
763f857e
DS		 3377
3378 if (priv->flags & CXD2841ER_EARLY_TUNE)
3379 cxd2841er_tuner_set(fe);
3380
a6dc60ff
KS		 3381 if (p->delivery_system == SYS_DVBT) {
3382 priv->system = SYS_DVBT;
3383 switch (priv->state) {
3384 case STATE_SLEEP_TC:
3385 ret = cxd2841er_sleep_tc_to_active_t(
3386 priv, p->bandwidth_hz);
3387 break;
3388 case STATE_ACTIVE_TC:
3389 ret = cxd2841er_retune_active(priv, p);
3390 break;
3391 default:
3392 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3393 __func__, priv->state);
3394 ret = -EINVAL;
3395 }
3396 } else if (p->delivery_system == SYS_DVBT2) {
3397 priv->system = SYS_DVBT2;
3398 cxd2841er_dvbt2_set_plp_config(priv,
3399 (int)(p->stream_id > 255), p->stream_id);
3400 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3401 switch (priv->state) {
3402 case STATE_SLEEP_TC:
3403 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3404 p->bandwidth_hz);
3405 break;
3406 case STATE_ACTIVE_TC:
3407 ret = cxd2841er_retune_active(priv, p);
3408 break;
3409 default:
3410 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3411 __func__, priv->state);
3412 ret = -EINVAL;
3413 }
83808c23
AO		 3414 } else if (p->delivery_system == SYS_ISDBT) {
3415 priv->system = SYS_ISDBT;
3416 switch (priv->state) {
3417 case STATE_SLEEP_TC:
3418 ret = cxd2841er_sleep_tc_to_active_i(
3419 priv, p->bandwidth_hz);
3420 break;
3421 case STATE_ACTIVE_TC:
3422 ret = cxd2841er_retune_active(priv, p);
3423 break;
3424 default:
3425 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3426 __func__, priv->state);
3427 ret = -EINVAL;
3428 }
a6dc60ff
KS		 3429 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3430 p->delivery_system == SYS_DVBC_ANNEX_C) {
3431 priv->system = SYS_DVBC_ANNEX_A;
3f3b48a0
AO		 3432 /* correct bandwidth */
3433 if (p->bandwidth_hz != 6000000 &&
3434 p->bandwidth_hz != 7000000 &&
3435 p->bandwidth_hz != 8000000) {
3436 p->bandwidth_hz = 8000000;
3437 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3438 __func__, p->bandwidth_hz);
3439 }
3440
a6dc60ff
KS		 3441 switch (priv->state) {
3442 case STATE_SLEEP_TC:
3443 ret = cxd2841er_sleep_tc_to_active_c(
3444 priv, p->bandwidth_hz);
3445 break;
3446 case STATE_ACTIVE_TC:
3447 ret = cxd2841er_retune_active(priv, p);
3448 break;
3449 default:
3450 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3451 __func__, priv->state);
3452 ret = -EINVAL;
3453 }
3454 } else {
3455 dev_dbg(&priv->i2c->dev,
3456 "%s(): invalid delivery system %d\n",
3457 __func__, p->delivery_system);
3458 ret = -EINVAL;
3459 }
3460 if (ret)
3461 goto done;
c7518d13 3462
763f857e
DS		 3463 if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3464 cxd2841er_tuner_set(fe);
c7518d13 3465
a6dc60ff 3466 cxd2841er_tune_done(priv);
e3943aa6
DS		 3467
3468 if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3469 goto done;
3470
a6dc60ff
KS		 3471 timeout = 2500;
3472 while (timeout > 0) {
3473 ret = cxd2841er_read_status_tc(fe, &status);
3474 if (ret)
3475 goto done;
3476 if (status & FE_HAS_LOCK)
3477 break;
3478 msleep(20);
3479 timeout -= 20;
3480 }
3481 if (timeout < 0)
3482 dev_dbg(&priv->i2c->dev,
3483 "%s(): LOCK wait timeout\n", __func__);
3484done:
3485 return ret;
3486}
3487
3488static int cxd2841er_tune_s(struct dvb_frontend *fe,
3489 bool re_tune,
3490 unsigned int mode_flags,
3491 unsigned int *delay,
3492 enum fe_status *status)
3493{
3494 int ret, carrier_offset;
3495 struct cxd2841er_priv *priv = fe->demodulator_priv;
3496 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3497
3498 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3499 if (re_tune) {
3500 ret = cxd2841er_set_frontend_s(fe);
3501 if (ret)
3502 return ret;
3503 cxd2841er_read_status_s(fe, status);
3504 if (*status & FE_HAS_LOCK) {
3505 if (cxd2841er_get_carrier_offset_s_s2(
3506 priv, &carrier_offset))
3507 return -EINVAL;
3508 p->frequency += carrier_offset;
3509 ret = cxd2841er_set_frontend_s(fe);
3510 if (ret)
3511 return ret;
3512 }
3513 }
3514 *delay = HZ / 5;
3515 return cxd2841er_read_status_s(fe, status);
3516}
3517
3518static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3519 bool re_tune,
3520 unsigned int mode_flags,
3521 unsigned int *delay,
3522 enum fe_status *status)
3523{
3524 int ret, carrier_offset;
3525 struct cxd2841er_priv *priv = fe->demodulator_priv;
3526 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3527
3f3b48a0
AO		 3528 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3529 re_tune, p->bandwidth_hz);
a6dc60ff
KS		 3530 if (re_tune) {
3531 ret = cxd2841er_set_frontend_tc(fe);
3532 if (ret)
3533 return ret;
3534 cxd2841er_read_status_tc(fe, status);
3535 if (*status & FE_HAS_LOCK) {
3536 switch (priv->system) {
76344a3f
MCC		 3537 case SYS_ISDBT:
3538 ret = cxd2841er_get_carrier_offset_i(
3539 priv, p->bandwidth_hz,
3540 &carrier_offset);
bb9bd878
AB		 3541 if (ret)
3542 return ret;
76344a3f 3543 break;
a6dc60ff 3544 case SYS_DVBT:
c5ea46da
AO		 3545 ret = cxd2841er_get_carrier_offset_t(
3546 priv, p->bandwidth_hz,
3547 &carrier_offset);
bb9bd878
AB		 3548 if (ret)
3549 return ret;
c5ea46da 3550 break;
a6dc60ff
KS		 3551 case SYS_DVBT2:
3552 ret = cxd2841er_get_carrier_offset_t2(
3553 priv, p->bandwidth_hz,
3554 &carrier_offset);
bb9bd878
AB		 3555 if (ret)
3556 return ret;
a6dc60ff
KS		 3557 break;
3558 case SYS_DVBC_ANNEX_A:
3559 ret = cxd2841er_get_carrier_offset_c(
3560 priv, &carrier_offset);
bb9bd878
AB		 3561 if (ret)
3562 return ret;
a6dc60ff
KS		 3563 break;
3564 default:
3565 dev_dbg(&priv->i2c->dev,
3566 "%s(): invalid delivery system %d\n",
3567 __func__, priv->system);
3568 return -EINVAL;
3569 }
a6dc60ff
KS		 3570 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3571 __func__, carrier_offset);
3572 p->frequency += carrier_offset;
3573 ret = cxd2841er_set_frontend_tc(fe);
3574 if (ret)
3575 return ret;
3576 }
3577 }
3578 *delay = HZ / 5;
3579 return cxd2841er_read_status_tc(fe, status);
3580}
3581
3582static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3583{
3584 struct cxd2841er_priv *priv = fe->demodulator_priv;
3585
3586 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3587 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3588 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3589 return 0;
3590}
3591
3592static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3593{
3594 struct cxd2841er_priv *priv = fe->demodulator_priv;
3595
3596 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3597 if (priv->state == STATE_ACTIVE_TC) {
3598 switch (priv->system) {
3599 case SYS_DVBT:
3600 cxd2841er_active_t_to_sleep_tc(priv);
3601 break;
3602 case SYS_DVBT2:
3603 cxd2841er_active_t2_to_sleep_tc(priv);
3604 break;
83808c23
AO		 3605 case SYS_ISDBT:
3606 cxd2841er_active_i_to_sleep_tc(priv);
3607 break;
a6dc60ff
KS		 3608 case SYS_DVBC_ANNEX_A:
3609 cxd2841er_active_c_to_sleep_tc(priv);
3610 break;
3611 default:
3612 dev_warn(&priv->i2c->dev,
3613 "%s(): unknown delivery system %d\n",
3614 __func__, priv->system);
3615 }
3616 }
3617 if (priv->state != STATE_SLEEP_TC) {
3618 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3619 __func__, priv->state);
3620 return -EINVAL;
3621 }
3622 cxd2841er_sleep_tc_to_shutdown(priv);
3623 return 0;
3624}
3625
3626static int cxd2841er_send_burst(struct dvb_frontend *fe,
3627 enum fe_sec_mini_cmd burst)
3628{
3629 u8 data;
3630 struct cxd2841er_priv *priv = fe->demodulator_priv;
3631
3632 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3633 (burst == SEC_MINI_A ? "A" : "B"));
3634 if (priv->state != STATE_SLEEP_S &&
3635 priv->state != STATE_ACTIVE_S) {
3636 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3637 __func__, priv->state);
3638 return -EINVAL;
3639 }
3640 data = (burst == SEC_MINI_A ? 0 : 1);
3641 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3642 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3643 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3644 return 0;
3645}
3646
3647static int cxd2841er_set_tone(struct dvb_frontend *fe,
3648 enum fe_sec_tone_mode tone)
3649{
3650 u8 data;
3651 struct cxd2841er_priv *priv = fe->demodulator_priv;
3652
3653 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3654 (tone == SEC_TONE_ON ? "On" : "Off"));
3655 if (priv->state != STATE_SLEEP_S &&
3656 priv->state != STATE_ACTIVE_S) {
3657 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3658 __func__, priv->state);
3659 return -EINVAL;
3660 }
3661 data = (tone == SEC_TONE_ON ? 1 : 0);
3662 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3663 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3664 return 0;
3665}
3666
3667static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3668 struct dvb_diseqc_master_cmd *cmd)
3669{
3670 int i;
3671 u8 data[12];
3672 struct cxd2841er_priv *priv = fe->demodulator_priv;
3673
3674 if (priv->state != STATE_SLEEP_S &&
3675 priv->state != STATE_ACTIVE_S) {
3676 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3677 __func__, priv->state);
3678 return -EINVAL;
3679 }
3680 dev_dbg(&priv->i2c->dev,
3681 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3682 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3683 /* DiDEqC enable */
3684 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3685 /* cmd1 length & data */
3686 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3687 memset(data, 0, sizeof(data));
3688 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3689 data[i] = cmd->msg[i];
3690 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3691 /* repeat count for cmd1 */
3692 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3693 /* repeat count for cmd2: always 0 */
3694 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3695 /* start transmit */
3696 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3697 /* wait for 1 sec timeout */
3698 for (i = 0; i < 50; i++) {
3699 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3700 if (!data[0]) {
3701 dev_dbg(&priv->i2c->dev,
3702 "%s(): DiSEqC cmd has been sent\n", __func__);
3703 return 0;
3704 }
3705 msleep(20);
3706 }
3707 dev_dbg(&priv->i2c->dev,
3708 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3709 return -ETIMEDOUT;
3710}
3711
3712static void cxd2841er_release(struct dvb_frontend *fe)
3713{
3714 struct cxd2841er_priv *priv = fe->demodulator_priv;
3715
3716 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3717 kfree(priv);
3718}
3719
3720static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3721{
3722 struct cxd2841er_priv *priv = fe->demodulator_priv;
3723
3724 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3725 cxd2841er_set_reg_bits(
3726 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3727 return 0;
3728}
3729
3730static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3731{
3732 struct cxd2841er_priv *priv = fe->demodulator_priv;
3733
3734 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3735 return DVBFE_ALGO_HW;
3736}
3737
d0e20e13
MCC		 3738static void cxd2841er_init_stats(struct dvb_frontend *fe)
3739{
3740 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3741
3742 p->strength.len = 1;
3743 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3744 p->cnr.len = 1;
3745 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3746 p->block_error.len = 1;
3747 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3748 p->post_bit_error.len = 1;
3749 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4216be14
MCC		 3750 p->post_bit_count.len = 1;
3751 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
d0e20e13
MCC		 3752}
3753
3754
a6dc60ff
KS		 3755static int cxd2841er_init_s(struct dvb_frontend *fe)
3756{
3757 struct cxd2841er_priv *priv = fe->demodulator_priv;
3758
30ae3307
AO		 3759 /* sanity. force demod to SHUTDOWN state */
3760 if (priv->state == STATE_SLEEP_S) {
3761 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3762 __func__);
3763 cxd2841er_sleep_s_to_shutdown(priv);
3764 } else if (priv->state == STATE_ACTIVE_S) {
3765 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3766 __func__);
3767 cxd2841er_active_s_to_sleep_s(priv);
3768 cxd2841er_sleep_s_to_shutdown(priv);
3769 }
3770
a6dc60ff
KS		 3771 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3772 cxd2841er_shutdown_to_sleep_s(priv);
3773 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3774 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3775 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
d0e20e13
MCC		 3776
3777 cxd2841er_init_stats(fe);
3778
a6dc60ff
KS		 3779 return 0;
3780}
3781
3782static int cxd2841er_init_tc(struct dvb_frontend *fe)
3783{
3784 struct cxd2841er_priv *priv = fe->demodulator_priv;
3f3b48a0 3785 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
a6dc60ff 3786
3f3b48a0
AO		 3787 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3788 __func__, p->bandwidth_hz);
a6dc60ff 3789 cxd2841er_shutdown_to_sleep_tc(priv);
14fd8629 3790 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
a6dc60ff 3791 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
14fd8629
DS		 3792 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3793 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
a6dc60ff
KS		 3794 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3795 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3796 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3797 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
03ab1bd5
DS		 3798 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3799 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
d0e20e13 3800
bf51bbb0
DS		 3801 /* clear TSCFG bits 3+4 */
3802 if (priv->flags & CXD2841ER_TSBITS)
3803 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3804
d0e20e13
MCC		 3805 cxd2841er_init_stats(fe);
3806
a6dc60ff
KS		 3807 return 0;
3808}
3809
bd336e63 3810static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3f3b48a0 3811static struct dvb_frontend_ops cxd2841er_t_c_ops;
a6dc60ff
KS		 3812
3813static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3814 struct i2c_adapter *i2c,
3815 u8 system)
3816{
3817 u8 chip_id = 0;
3818 const char *type;
3f3b48a0 3819 const char *name;
a6dc60ff
KS		 3820 struct cxd2841er_priv *priv = NULL;
3821
3822 /* allocate memory for the internal state */
3823 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3824 if (!priv)
3825 return NULL;
3826 priv->i2c = i2c;
3827 priv->config = cfg;
3828 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3829 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
83808c23 3830 priv->xtal = cfg->xtal;
050863aa 3831 priv->flags = cfg->flags;
a6dc60ff 3832 priv->frontend.demodulator_priv = priv;
a6dc60ff
KS		 3833 dev_info(&priv->i2c->dev,
3834 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3835 __func__, priv->i2c,
3836 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3837 chip_id = cxd2841er_chip_id(priv);
3f3b48a0 3838 switch (chip_id) {
1ecda28c
DS		 3839 case CXD2837ER_CHIP_ID:
3840 snprintf(cxd2841er_t_c_ops.info.name, 128,
3841 "Sony CXD2837ER DVB-T/T2/C demodulator");
3842 name = "CXD2837ER";
3843 type = "C/T/T2";
3844 break;
3845 case CXD2838ER_CHIP_ID:
3846 snprintf(cxd2841er_t_c_ops.info.name, 128,
3847 "Sony CXD2838ER ISDB-T demodulator");
3848 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3849 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3850 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3851 name = "CXD2838ER";
3852 type = "ISDB-T";
3853 break;
3f3b48a0
AO		 3854 case CXD2841ER_CHIP_ID:
3855 snprintf(cxd2841er_t_c_ops.info.name, 128,
3856 "Sony CXD2841ER DVB-T/T2/C demodulator");
3857 name = "CXD2841ER";
1ecda28c
DS		 3858 type = "T/T2/C/ISDB-T";
3859 break;
3860 case CXD2843ER_CHIP_ID:
3861 snprintf(cxd2841er_t_c_ops.info.name, 128,
3862 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3863 name = "CXD2843ER";
3864 type = "C/C2/T/T2";
3f3b48a0
AO		 3865 break;
3866 case CXD2854ER_CHIP_ID:
3867 snprintf(cxd2841er_t_c_ops.info.name, 128,
3868 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3869 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3870 name = "CXD2854ER";
1ecda28c 3871 type = "C/C2/T/T2/ISDB-T";
3f3b48a0
AO		 3872 break;
3873 default:
a6dc60ff 3874 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3f3b48a0 3875 __func__, chip_id);
a6dc60ff
KS		 3876 priv->frontend.demodulator_priv = NULL;
3877 kfree(priv);
3878 return NULL;
3879 }
3f3b48a0
AO		 3880
3881 /* create dvb_frontend */
3882 if (system == SYS_DVBS) {
3883 memcpy(&priv->frontend.ops,
3884 &cxd2841er_dvbs_s2_ops,
3885 sizeof(struct dvb_frontend_ops));
3886 type = "S/S2";
3887 } else {
3888 memcpy(&priv->frontend.ops,
3889 &cxd2841er_t_c_ops,
3890 sizeof(struct dvb_frontend_ops));
3f3b48a0
AO		 3891 }
3892
3893 dev_info(&priv->i2c->dev,
3894 "%s(): attaching %s DVB-%s frontend\n",
3895 __func__, name, type);
a6dc60ff
KS		 3896 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3897 __func__, chip_id);
3898 return &priv->frontend;
3899}
3900
3901struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3902 struct i2c_adapter *i2c)
3903{
3904 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3905}
3906EXPORT_SYMBOL(cxd2841er_attach_s);
3907
3f3b48a0 3908struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
a6dc60ff
KS		 3909 struct i2c_adapter *i2c)
3910{
3f3b48a0 3911 return cxd2841er_attach(cfg, i2c, 0);
a6dc60ff 3912}
3f3b48a0 3913EXPORT_SYMBOL(cxd2841er_attach_t_c);
a6dc60ff 3914
bd336e63 3915static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
a6dc60ff
KS		 3916 .delsys = { SYS_DVBS, SYS_DVBS2 },
3917 .info = {
3918 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3919 .frequency_min = 500000,
3920 .frequency_max = 2500000,
3921 .frequency_stepsize = 0,
3922 .symbol_rate_min = 1000000,
3923 .symbol_rate_max = 45000000,
3924 .symbol_rate_tolerance = 500,
3925 .caps = FE_CAN_INVERSION_AUTO |
3926 FE_CAN_FEC_AUTO |
3927 FE_CAN_QPSK,
3928 },
3929 .init = cxd2841er_init_s,
3930 .sleep = cxd2841er_sleep_s,
3931 .release = cxd2841er_release,
3932 .set_frontend = cxd2841er_set_frontend_s,
3933 .get_frontend = cxd2841er_get_frontend,
3934 .read_status = cxd2841er_read_status_s,
3935 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3936 .get_frontend_algo = cxd2841er_get_algo,
3937 .set_tone = cxd2841er_set_tone,
3938 .diseqc_send_burst = cxd2841er_send_burst,
3939 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3940 .tune = cxd2841er_tune_s
3941};
3942
bd336e63 3943static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3f3b48a0 3944 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
83808c23 3945 .info = {
3f3b48a0 3946 .name = "", /* will set in attach function */
83808c23
AO		 3947 .caps = FE_CAN_FEC_1_2 |
3948 FE_CAN_FEC_2_3 |
3949 FE_CAN_FEC_3_4 |
3950 FE_CAN_FEC_5_6 |
3951 FE_CAN_FEC_7_8 |
3952 FE_CAN_FEC_AUTO |
3953 FE_CAN_QPSK |
3954 FE_CAN_QAM_16 |
3955 FE_CAN_QAM_32 |
3956 FE_CAN_QAM_64 |
3957 FE_CAN_QAM_128 |
3958 FE_CAN_QAM_256 |
3959 FE_CAN_QAM_AUTO |
3960 FE_CAN_TRANSMISSION_MODE_AUTO |
3961 FE_CAN_GUARD_INTERVAL_AUTO |
3962 FE_CAN_HIERARCHY_AUTO |
3963 FE_CAN_MUTE_TS |
3964 FE_CAN_2G_MODULATION,
3965 .frequency_min = 42000000,
158f0328
DS		 3966 .frequency_max = 1002000000,
3967 .symbol_rate_min = 870000,
3968 .symbol_rate_max = 11700000
83808c23
AO		 3969 },
3970 .init = cxd2841er_init_tc,
3971 .sleep = cxd2841er_sleep_tc,
3972 .release = cxd2841er_release,
3973 .set_frontend = cxd2841er_set_frontend_tc,
3974 .get_frontend = cxd2841er_get_frontend,
3975 .read_status = cxd2841er_read_status_tc,
3976 .tune = cxd2841er_tune_tc,
3977 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3978 .get_frontend_algo = cxd2841er_get_algo
3979};
3980
83808c23
AO		 3981MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3982MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
a6dc60ff 3983MODULE_LICENSE("GPL");
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