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[media] mb86a20s: apply mask to val after checking for read failure
[mirror_ubuntu-zesty-kernel.git] / drivers / media / dvb-frontends / cxd2841er.c
CommitLineData
a6dc60ff
KS		 1/*
2 * cxd2841er.c
3 *
83808c23 4 * Sony digital demodulator driver for
9ca1736f
AO		 5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
a6dc60ff
KS		 7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/bitops.h>
29#include <linux/math64.h>
30#include <linux/log2.h>
31#include <linux/dynamic_debug.h>
32
33#include "dvb_math.h"
34#include "dvb_frontend.h"
35#include "cxd2841er.h"
36#include "cxd2841er_priv.h"
37
d13a7b67
MCC		 38#define MAX_WRITE_REGSIZE 16
39
a6dc60ff
KS		 40enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46};
47
48struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
83808c23 56 enum cxd2841er_xtal xtal;
3f3b48a0 57 enum fe_caps caps;
a6dc60ff
KS		 58};
59
60static const struct cxd2841er_cnr_data s_cn_data[] = {
61 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
62 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
63 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
64 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
65 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
66 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
67 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
68 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
69 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
70 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
71 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
72 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
73 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
74 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
75 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
76 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
77 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
78 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
79 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
80 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
81 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
82 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
83 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
84 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
85 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
86 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
87 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
88 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
89 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
90 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
91 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
92 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
93 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
94 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
95 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
96 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
97 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
98 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
99 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
100 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
101 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
102 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
103 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
104 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
105 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
106 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
107 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
108 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
109 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
110 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
111 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
112 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
113 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
114 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
115 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
116 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
117 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
118 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
119 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
120 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
121 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
122 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
123 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
124 { 0x0015, 19900 }, { 0x0014, 20000 },
125};
126
127static const struct cxd2841er_cnr_data s2_cn_data[] = {
128 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
129 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
130 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
131 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
132 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
133 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
134 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
135 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
136 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
137 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
138 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
139 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
140 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
141 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
142 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
143 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
144 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
145 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
146 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
147 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
148 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
149 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
150 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
151 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
152 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
153 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
154 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
155 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
156 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
157 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
158 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
159 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
160 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
161 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
162 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
163 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
164 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
165 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
166 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
167 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
168 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
169 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
170 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
171 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
172 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
173 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
174 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
175 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
176 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
177 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
178 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
179 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
180 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
181 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
182 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
183 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
184 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
185 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
186 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
187 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
188 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
189 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
190 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
191 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
192};
193
194#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
83808c23
AO		 195#define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
196 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
197 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
a6dc60ff
KS		 198
199static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
200 u8 addr, u8 reg, u8 write,
201 const u8 *data, u32 len)
202{
203 dev_dbg(&priv->i2c->dev,
204 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
205 (write == 0 ? "read" : "write"), addr, reg, len);
206 print_hex_dump_bytes("cxd2841er: I2C data: ",
207 DUMP_PREFIX_OFFSET, data, len);
208}
209
210static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
211 u8 addr, u8 reg, const u8 *data, u32 len)
212{
213 int ret;
d13a7b67 214 u8 buf[MAX_WRITE_REGSIZE + 1];
a6dc60ff
KS		 215 u8 i2c_addr = (addr == I2C_SLVX ?
216 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
217 struct i2c_msg msg[1] = {
218 {
219 .addr = i2c_addr,
220 .flags = 0,
d13a7b67 221 .len = len + 1,
a6dc60ff
KS		 222 .buf = buf,
223 }
224 };
225
d13a7b67 226 if (len + 1 >= sizeof(buf)) {
83808c23 227 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
d13a7b67
MCC		 228 reg, len + 1);
229 return -E2BIG;
230 }
231
a6dc60ff
KS		 232 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
233 buf[0] = reg;
234 memcpy(&buf[1], data, len);
235
236 ret = i2c_transfer(priv->i2c, msg, 1);
237 if (ret >= 0 && ret != 1)
238 ret = -EIO;
239 if (ret < 0) {
240 dev_warn(&priv->i2c->dev,
241 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
242 KBUILD_MODNAME, ret, i2c_addr, reg, len);
243 return ret;
244 }
245 return 0;
246}
247
248static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
249 u8 addr, u8 reg, u8 val)
250{
251 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
252}
253
254static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
255 u8 addr, u8 reg, u8 *val, u32 len)
256{
257 int ret;
258 u8 i2c_addr = (addr == I2C_SLVX ?
259 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
260 struct i2c_msg msg[2] = {
261 {
262 .addr = i2c_addr,
263 .flags = 0,
264 .len = 1,
265 .buf = &reg,
266 }, {
267 .addr = i2c_addr,
268 .flags = I2C_M_RD,
269 .len = len,
270 .buf = val,
271 }
272 };
273
274 ret = i2c_transfer(priv->i2c, &msg[0], 1);
275 if (ret >= 0 && ret != 1)
276 ret = -EIO;
277 if (ret < 0) {
278 dev_warn(&priv->i2c->dev,
279 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
280 KBUILD_MODNAME, ret, i2c_addr, reg);
281 return ret;
282 }
283 ret = i2c_transfer(priv->i2c, &msg[1], 1);
284 if (ret >= 0 && ret != 1)
285 ret = -EIO;
286 if (ret < 0) {
287 dev_warn(&priv->i2c->dev,
288 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
289 KBUILD_MODNAME, ret, i2c_addr, reg);
290 return ret;
291 }
6c77161a 292 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
a6dc60ff
KS		 293 return 0;
294}
295
296static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 *val)
298{
299 return cxd2841er_read_regs(priv, addr, reg, val, 1);
300}
301
302static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
303 u8 addr, u8 reg, u8 data, u8 mask)
304{
305 int res;
306 u8 rdata;
307
308 if (mask != 0xff) {
309 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
310 if (res)
311 return res;
312 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
313 }
314 return cxd2841er_write_reg(priv, addr, reg, data);
315}
316
317static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
318 u32 symbol_rate)
319{
320 u32 reg_value = 0;
321 u8 data[3] = {0, 0, 0};
322
323 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
324 /*
325 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
326 * = ((symbolRateKSps * 2^14) + 500) / 1000
327 * = ((symbolRateKSps * 16384) + 500) / 1000
328 */
329 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
330 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
331 dev_err(&priv->i2c->dev,
332 "%s(): reg_value is out of range\n", __func__);
333 return -EINVAL;
334 }
335 data[0] = (u8)((reg_value >> 16) & 0x0F);
336 data[1] = (u8)((reg_value >> 8) & 0xFF);
337 data[2] = (u8)(reg_value & 0xFF);
338 /* Set SLV-T Bank : 0xAE */
339 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
340 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
341 return 0;
342}
343
344static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
345 u8 system);
346
347static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
348 u8 system, u32 symbol_rate)
349{
350 int ret;
351 u8 data[4] = { 0, 0, 0, 0 };
352
353 if (priv->state != STATE_SLEEP_S) {
354 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
355 __func__, (int)priv->state);
356 return -EINVAL;
357 }
358 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
359 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
360 /* Set demod mode */
361 if (system == SYS_DVBS) {
362 data[0] = 0x0A;
363 } else if (system == SYS_DVBS2) {
364 data[0] = 0x0B;
365 } else {
366 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
367 __func__, system);
368 return -EINVAL;
369 }
370 /* Set SLV-X Bank : 0x00 */
371 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
372 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
373 /* DVB-S/S2 */
374 data[0] = 0x00;
375 /* Set SLV-T Bank : 0x00 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
377 /* Enable S/S2 auto detection 1 */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
379 /* Set SLV-T Bank : 0xAE */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
381 /* Enable S/S2 auto detection 2 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
383 /* Set SLV-T Bank : 0x00 */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
385 /* Enable demod clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
387 /* Enable ADC clock */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
389 /* Enable ADC 1 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
391 /* Enable ADC 2 */
392 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
393 /* Set SLV-X Bank : 0x00 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
395 /* Enable ADC 3 */
396 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
397 /* Set SLV-T Bank : 0xA3 */
398 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
399 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
400 data[0] = 0x07;
401 data[1] = 0x3B;
402 data[2] = 0x08;
403 data[3] = 0xC5;
404 /* Set SLV-T Bank : 0xAB */
405 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
406 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
407 data[0] = 0x05;
408 data[1] = 0x80;
409 data[2] = 0x0A;
410 data[3] = 0x80;
411 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
412 data[0] = 0x0C;
413 data[1] = 0xCC;
414 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
415 /* Set demod parameter */
416 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
417 if (ret != 0)
418 return ret;
419 /* Set SLV-T Bank : 0x00 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
421 /* disable Hi-Z setting 1 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
423 /* disable Hi-Z setting 2 */
424 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
425 priv->state = STATE_ACTIVE_S;
426 return 0;
427}
428
429static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
430 u32 bandwidth);
431
432static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
433 u32 bandwidth);
434
435static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
436 u32 bandwidth);
437
76344a3f
MCC		 438static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
439 u32 bandwidth);
440
441static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
442
443static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
444
445static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
446
a6dc60ff
KS		 447static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
448 struct dtv_frontend_properties *p)
449{
450 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
451 if (priv->state != STATE_ACTIVE_S &&
452 priv->state != STATE_ACTIVE_TC) {
453 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
454 __func__, priv->state);
455 return -EINVAL;
456 }
457 /* Set SLV-T Bank : 0x00 */
458 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
459 /* disable TS output */
460 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
461 if (priv->state == STATE_ACTIVE_S)
462 return cxd2841er_dvbs2_set_symbol_rate(
463 priv, p->symbol_rate / 1000);
464 else if (priv->state == STATE_ACTIVE_TC) {
465 switch (priv->system) {
466 case SYS_DVBT:
467 return cxd2841er_sleep_tc_to_active_t_band(
468 priv, p->bandwidth_hz);
469 case SYS_DVBT2:
470 return cxd2841er_sleep_tc_to_active_t2_band(
471 priv, p->bandwidth_hz);
472 case SYS_DVBC_ANNEX_A:
473 return cxd2841er_sleep_tc_to_active_c_band(
76344a3f
MCC		 474 priv, p->bandwidth_hz);
475 case SYS_ISDBT:
476 cxd2841er_active_i_to_sleep_tc(priv);
477 cxd2841er_sleep_tc_to_shutdown(priv);
478 cxd2841er_shutdown_to_sleep_tc(priv);
479 return cxd2841er_sleep_tc_to_active_i(
480 priv, p->bandwidth_hz);
a6dc60ff
KS		 481 }
482 }
483 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
484 __func__, priv->system);
485 return -EINVAL;
486}
487
488static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
489{
490 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
491 if (priv->state != STATE_ACTIVE_S) {
492 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
493 __func__, priv->state);
494 return -EINVAL;
495 }
496 /* Set SLV-T Bank : 0x00 */
497 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
498 /* disable TS output */
499 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
500 /* enable Hi-Z setting 1 */
501 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
502 /* enable Hi-Z setting 2 */
503 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
504 /* Set SLV-X Bank : 0x00 */
505 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
506 /* disable ADC 1 */
507 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
508 /* Set SLV-T Bank : 0x00 */
509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
510 /* disable ADC clock */
511 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
512 /* disable ADC 2 */
513 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
514 /* disable ADC 3 */
515 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
516 /* SADC Bias ON */
517 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
518 /* disable demod clock */
519 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
520 /* Set SLV-T Bank : 0xAE */
521 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
522 /* disable S/S2 auto detection1 */
523 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
524 /* Set SLV-T Bank : 0x00 */
525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
526 /* disable S/S2 auto detection2 */
527 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
528 priv->state = STATE_SLEEP_S;
529 return 0;
530}
531
532static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
533{
534 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
535 if (priv->state != STATE_SLEEP_S) {
536 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
537 __func__, priv->state);
538 return -EINVAL;
539 }
540 /* Set SLV-T Bank : 0x00 */
541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
542 /* Disable DSQOUT */
543 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
544 /* Disable DSQIN */
545 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
546 /* Set SLV-X Bank : 0x00 */
547 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
548 /* Disable oscillator */
549 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
550 /* Set demod mode */
551 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
552 priv->state = STATE_SHUTDOWN;
553 return 0;
554}
555
556static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
557{
558 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
559 if (priv->state != STATE_SLEEP_TC) {
560 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
561 __func__, priv->state);
562 return -EINVAL;
563 }
564 /* Set SLV-X Bank : 0x00 */
565 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
566 /* Disable oscillator */
567 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
568 /* Set demod mode */
569 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
570 priv->state = STATE_SHUTDOWN;
571 return 0;
572}
573
574static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
575{
576 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
577 if (priv->state != STATE_ACTIVE_TC) {
578 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
579 __func__, priv->state);
580 return -EINVAL;
581 }
582 /* Set SLV-T Bank : 0x00 */
583 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
584 /* disable TS output */
585 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
586 /* enable Hi-Z setting 1 */
587 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
588 /* enable Hi-Z setting 2 */
589 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
590 /* Set SLV-X Bank : 0x00 */
591 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
592 /* disable ADC 1 */
593 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
594 /* Set SLV-T Bank : 0x00 */
595 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
596 /* Disable ADC 2 */
597 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
598 /* Disable ADC 3 */
599 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
600 /* Disable ADC clock */
601 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
602 /* Disable RF level monitor */
603 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
604 /* Disable demod clock */
605 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
606 priv->state = STATE_SLEEP_TC;
607 return 0;
608}
609
610static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
611{
612 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
613 if (priv->state != STATE_ACTIVE_TC) {
614 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
615 __func__, priv->state);
616 return -EINVAL;
617 }
618 /* Set SLV-T Bank : 0x00 */
619 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
620 /* disable TS output */
621 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
622 /* enable Hi-Z setting 1 */
623 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
624 /* enable Hi-Z setting 2 */
625 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
626 /* Cancel DVB-T2 setting */
627 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
629 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
630 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
631 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
633 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
635 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
636 /* Set SLV-X Bank : 0x00 */
637 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
638 /* disable ADC 1 */
639 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
640 /* Set SLV-T Bank : 0x00 */
641 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
642 /* Disable ADC 2 */
643 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
644 /* Disable ADC 3 */
645 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
646 /* Disable ADC clock */
647 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
648 /* Disable RF level monitor */
649 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
650 /* Disable demod clock */
651 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
652 priv->state = STATE_SLEEP_TC;
653 return 0;
654}
655
656static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
657{
658 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
659 if (priv->state != STATE_ACTIVE_TC) {
660 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
661 __func__, priv->state);
662 return -EINVAL;
663 }
664 /* Set SLV-T Bank : 0x00 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
666 /* disable TS output */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
668 /* enable Hi-Z setting 1 */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
670 /* enable Hi-Z setting 2 */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
672 /* Cancel DVB-C setting */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
675 /* Set SLV-X Bank : 0x00 */
676 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
677 /* disable ADC 1 */
678 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
679 /* Set SLV-T Bank : 0x00 */
680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
681 /* Disable ADC 2 */
682 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
683 /* Disable ADC 3 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
685 /* Disable ADC clock */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
687 /* Disable RF level monitor */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
689 /* Disable demod clock */
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
691 priv->state = STATE_SLEEP_TC;
692 return 0;
693}
694
83808c23
AO		 695static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
696{
697 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
698 if (priv->state != STATE_ACTIVE_TC) {
699 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
700 __func__, priv->state);
701 return -EINVAL;
702 }
703 /* Set SLV-T Bank : 0x00 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
705 /* disable TS output */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
707 /* enable Hi-Z setting 1 */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
709 /* enable Hi-Z setting 2 */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
711
712 /* TODO: Cancel demod parameter */
713
714 /* Set SLV-X Bank : 0x00 */
715 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
716 /* disable ADC 1 */
717 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
718 /* Set SLV-T Bank : 0x00 */
719 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
720 /* Disable ADC 2 */
721 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
722 /* Disable ADC 3 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
724 /* Disable ADC clock */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
726 /* Disable RF level monitor */
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
728 /* Disable demod clock */
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
730 priv->state = STATE_SLEEP_TC;
731 return 0;
732}
733
a6dc60ff
KS		 734static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
735{
736 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
737 if (priv->state != STATE_SHUTDOWN) {
738 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
739 __func__, priv->state);
740 return -EINVAL;
741 }
742 /* Set SLV-X Bank : 0x00 */
743 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
744 /* Clear all demodulator registers */
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
746 usleep_range(3000, 5000);
747 /* Set SLV-X Bank : 0x00 */
748 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
749 /* Set demod SW reset */
750 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
83808c23
AO		 751
752 switch (priv->xtal) {
753 case SONY_XTAL_20500:
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
755 break;
756 case SONY_XTAL_24000:
757 /* Select demod frequency */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
759 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
760 break;
761 case SONY_XTAL_41000:
762 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
763 break;
764 default:
765 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
766 __func__, priv->xtal);
767 return -EINVAL;
768 }
769
a6dc60ff
KS		 770 /* Set demod mode */
771 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
772 /* Clear demod SW reset */
773 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
774 usleep_range(1000, 2000);
775 /* Set SLV-T Bank : 0x00 */
776 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
777 /* enable DSQOUT */
778 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
779 /* enable DSQIN */
780 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
781 /* TADC Bias On */
782 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
783 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
784 /* SADC Bias On */
785 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
786 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
787 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
788 priv->state = STATE_SLEEP_S;
789 return 0;
790}
791
792static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
793{
6c77161a 794 u8 data = 0;
3f3b48a0 795
a6dc60ff
KS		 796 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
797 if (priv->state != STATE_SHUTDOWN) {
798 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
799 __func__, priv->state);
800 return -EINVAL;
801 }
802 /* Set SLV-X Bank : 0x00 */
803 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
804 /* Clear all demodulator registers */
805 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
806 usleep_range(3000, 5000);
807 /* Set SLV-X Bank : 0x00 */
808 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
809 /* Set demod SW reset */
810 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
6c77161a 811 /* Select ADC clock mode */
a6dc60ff 812 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
6c77161a
AO		 813
814 switch (priv->xtal) {
815 case SONY_XTAL_20500:
816 data = 0x0;
817 break;
818 case SONY_XTAL_24000:
819 /* Select demod frequency */
820 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
821 data = 0x3;
822 break;
823 case SONY_XTAL_41000:
824 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
825 data = 0x1;
826 break;
827 }
828 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
a6dc60ff
KS		 829 /* Clear demod SW reset */
830 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
831 usleep_range(1000, 2000);
832 /* Set SLV-T Bank : 0x00 */
833 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
834 /* TADC Bias On */
835 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
836 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
837 /* SADC Bias On */
838 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
839 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
840 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
841 priv->state = STATE_SLEEP_TC;
842 return 0;
843}
844
845static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
846{
847 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
848 /* Set SLV-T Bank : 0x00 */
849 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
850 /* SW Reset */
851 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
852 /* Enable TS output */
853 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
854 return 0;
855}
856
857/* Set TS parallel mode */
858static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
859 u8 system)
860{
861 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
862
863 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
864 /* Set SLV-T Bank : 0x00 */
865 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
866 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
867 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
868 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
869 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
870 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
871
872 /*
873 * slave Bank Addr Bit default Name
874 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
875 */
876 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
877 /*
878 * Disable TS IF Clock
879 * slave Bank Addr Bit default Name
880 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
881 */
882 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
883 /*
884 * slave Bank Addr Bit default Name
885 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
886 */
887 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
888 /*
889 * Enable TS IF Clock
890 * slave Bank Addr Bit default Name
891 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
892 */
893 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
894
895 if (system == SYS_DVBT) {
896 /* Enable parity period for DVB-T */
897 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
898 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
899 } else if (system == SYS_DVBC_ANNEX_A) {
900 /* Enable parity period for DVB-C */
901 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
902 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
903 }
904}
905
906static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
907{
83808c23 908 u8 chip_id = 0;
a6dc60ff
KS		 909
910 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
83808c23
AO		 911 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
912 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
913 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
914 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
915
a6dc60ff
KS		 916 return chip_id;
917}
918
919static int cxd2841er_read_status_s(struct dvb_frontend *fe,
920 enum fe_status *status)
921{
922 u8 reg = 0;
923 struct cxd2841er_priv *priv = fe->demodulator_priv;
924
925 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
926 *status = 0;
927 if (priv->state != STATE_ACTIVE_S) {
928 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
929 __func__, priv->state);
930 return -EINVAL;
931 }
932 /* Set SLV-T Bank : 0xA0 */
933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
934 /*
935 * slave Bank Addr Bit Signal name
936 * <SLV-T> A0h 11h [2] ITSLOCK
937 */
938 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
939 if (reg & 0x04) {
940 *status = FE_HAS_SIGNAL
941 | FE_HAS_CARRIER
942 | FE_HAS_VITERBI
943 | FE_HAS_SYNC
944 | FE_HAS_LOCK;
945 }
946 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
947 return 0;
948}
949
950static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
951 u8 *sync, u8 *tslock, u8 *unlock)
952{
953 u8 data = 0;
954
955 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
956 if (priv->state != STATE_ACTIVE_TC)
957 return -EINVAL;
958 if (priv->system == SYS_DVBT) {
959 /* Set SLV-T Bank : 0x10 */
960 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
961 } else {
962 /* Set SLV-T Bank : 0x20 */
963 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
964 }
965 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
966 if ((data & 0x07) == 0x07) {
967 dev_dbg(&priv->i2c->dev,
968 "%s(): invalid hardware state detected\n", __func__);
969 *sync = 0;
970 *tslock = 0;
971 *unlock = 0;
972 } else {
973 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
974 *tslock = ((data & 0x20) ? 1 : 0);
975 *unlock = ((data & 0x10) ? 1 : 0);
976 }
977 return 0;
978}
979
980static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
981{
982 u8 data;
983
984 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
985 if (priv->state != STATE_ACTIVE_TC)
986 return -EINVAL;
987 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
988 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
989 if ((data & 0x01) == 0) {
990 *tslock = 0;
991 } else {
992 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
993 *tslock = ((data & 0x20) ? 1 : 0);
994 }
995 return 0;
996}
997
83808c23
AO		 998static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
999 u8 *sync, u8 *tslock, u8 *unlock)
1000{
1001 u8 data = 0;
1002
1003 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1004 if (priv->state != STATE_ACTIVE_TC)
1005 return -EINVAL;
1006 /* Set SLV-T Bank : 0x60 */
1007 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1008 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1009 dev_dbg(&priv->i2c->dev,
1010 "%s(): lock=0x%x\n", __func__, data);
1011 *sync = ((data & 0x02) ? 1 : 0);
1012 *tslock = ((data & 0x01) ? 1 : 0);
1013 *unlock = ((data & 0x10) ? 1 : 0);
1014 return 0;
1015}
1016
a6dc60ff
KS		 1017static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1018 enum fe_status *status)
1019{
1020 int ret = 0;
1021 u8 sync = 0;
1022 u8 tslock = 0;
1023 u8 unlock = 0;
1024 struct cxd2841er_priv *priv = fe->demodulator_priv;
1025
1026 *status = 0;
1027 if (priv->state == STATE_ACTIVE_TC) {
1028 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1029 ret = cxd2841er_read_status_t_t2(
1030 priv, &sync, &tslock, &unlock);
1031 if (ret)
1032 goto done;
1033 if (unlock)
1034 goto done;
1035 if (sync)
1036 *status = FE_HAS_SIGNAL |
1037 FE_HAS_CARRIER |
1038 FE_HAS_VITERBI |
1039 FE_HAS_SYNC;
1040 if (tslock)
1041 *status |= FE_HAS_LOCK;
83808c23
AO		 1042 } else if (priv->system == SYS_ISDBT) {
1043 ret = cxd2841er_read_status_i(
1044 priv, &sync, &tslock, &unlock);
1045 if (ret)
1046 goto done;
1047 if (unlock)
1048 goto done;
1049 if (sync)
1050 *status = FE_HAS_SIGNAL |
1051 FE_HAS_CARRIER |
1052 FE_HAS_VITERBI |
1053 FE_HAS_SYNC;
1054 if (tslock)
1055 *status |= FE_HAS_LOCK;
a6dc60ff
KS		 1056 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1057 ret = cxd2841er_read_status_c(priv, &tslock);
1058 if (ret)
1059 goto done;
1060 if (tslock)
1061 *status = FE_HAS_SIGNAL |
1062 FE_HAS_CARRIER |
1063 FE_HAS_VITERBI |
1064 FE_HAS_SYNC |
1065 FE_HAS_LOCK;
1066 }
1067 }
1068done:
1069 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1070 return ret;
1071}
1072
1073static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1074 int *offset)
1075{
1076 u8 data[3];
1077 u8 is_hs_mode;
1078 s32 cfrl_ctrlval;
1079 s32 temp_div, temp_q, temp_r;
1080
1081 if (priv->state != STATE_ACTIVE_S) {
1082 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1083 __func__, priv->state);
1084 return -EINVAL;
1085 }
1086 /*
1087 * Get High Sampling Rate mode
1088 * slave Bank Addr Bit Signal name
1089 * <SLV-T> A0h 10h [0] ITRL_LOCK
1090 */
1091 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1092 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1093 if (data[0] & 0x01) {
1094 /*
1095 * slave Bank Addr Bit Signal name
1096 * <SLV-T> A0h 50h [4] IHSMODE
1097 */
1098 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1099 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1100 } else {
1101 dev_dbg(&priv->i2c->dev,
1102 "%s(): unable to detect sampling rate mode\n",
1103 __func__);
1104 return -EINVAL;
1105 }
1106 /*
1107 * slave Bank Addr Bit Signal name
1108 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1109 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1110 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1111 */
1112 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1113 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1114 (((u32)data[1] & 0xFF) << 8) |
1115 ((u32)data[2] & 0xFF), 20);
1116 temp_div = (is_hs_mode ? 1048576 : 1572864);
1117 if (cfrl_ctrlval > 0) {
1118 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1119 temp_div, &temp_r);
1120 } else {
1121 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1122 temp_div, &temp_r);
1123 }
1124 if (temp_r >= temp_div / 2)
1125 temp_q++;
1126 if (cfrl_ctrlval > 0)
1127 temp_q *= -1;
1128 *offset = temp_q;
1129 return 0;
1130}
1131
76344a3f
MCC		 1132static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1133 u32 bandwidth, int *offset)
1134{
1135 u8 data[4];
1136
1137 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1138 if (priv->state != STATE_ACTIVE_TC) {
1139 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1140 __func__, priv->state);
1141 return -EINVAL;
1142 }
1143 if (priv->system != SYS_ISDBT) {
1144 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1145 __func__, priv->system);
1146 return -EINVAL;
1147 }
1148 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1149 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1150 *offset = -1 * sign_extend32(
1151 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1152 ((u32)data[2] << 8) | (u32)data[3], 29);
1153
1154 switch (bandwidth) {
1155 case 6000000:
1156 *offset = -1 * ((*offset) * 8/264);
1157 break;
1158 case 7000000:
1159 *offset = -1 * ((*offset) * 8/231);
1160 break;
1161 case 8000000:
1162 *offset = -1 * ((*offset) * 8/198);
1163 break;
1164 default:
1165 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1166 __func__, bandwidth);
1167 return -EINVAL;
1168 }
1169
1170 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1171 __func__, bandwidth, *offset);
1172
1173 return 0;
1174}
1175
c5ea46da
AO		 1176static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1177 u32 bandwidth, int *offset)
1178{
1179 u8 data[4];
1180
1181 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1182 if (priv->state != STATE_ACTIVE_TC) {
1183 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1184 __func__, priv->state);
1185 return -EINVAL;
1186 }
1187 if (priv->system != SYS_DVBT) {
1188 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1189 __func__, priv->system);
1190 return -EINVAL;
1191 }
1192 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1193 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1194 *offset = -1 * sign_extend32(
1195 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1196 ((u32)data[2] << 8) | (u32)data[3], 29);
6c77161a
AO		 1197 *offset *= (bandwidth / 1000000);
1198 *offset /= 235;
c5ea46da
AO		 1199 return 0;
1200}
1201
c8946c8d
MCC		 1202static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1203 u32 bandwidth, int *offset)
a6dc60ff
KS		 1204{
1205 u8 data[4];
1206
1207 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1208 if (priv->state != STATE_ACTIVE_TC) {
1209 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1210 __func__, priv->state);
1211 return -EINVAL;
1212 }
1213 if (priv->system != SYS_DVBT2) {
1214 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1215 __func__, priv->system);
1216 return -EINVAL;
1217 }
1218 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1219 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1220 *offset = -1 * sign_extend32(
1221 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1222 ((u32)data[2] << 8) | (u32)data[3], 27);
1223 switch (bandwidth) {
1224 case 1712000:
1225 *offset /= 582;
1226 break;
1227 case 5000000:
1228 case 6000000:
1229 case 7000000:
1230 case 8000000:
1231 *offset *= (bandwidth / 1000000);
1232 *offset /= 940;
1233 break;
1234 default:
1235 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1236 __func__, bandwidth);
1237 return -EINVAL;
1238 }
1239 return 0;
1240}
1241
c8946c8d
MCC		 1242static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1243 int *offset)
a6dc60ff
KS		 1244{
1245 u8 data[2];
1246
1247 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1248 if (priv->state != STATE_ACTIVE_TC) {
1249 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1250 __func__, priv->state);
1251 return -EINVAL;
1252 }
1253 if (priv->system != SYS_DVBC_ANNEX_A) {
1254 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1255 __func__, priv->system);
1256 return -EINVAL;
1257 }
1258 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1259 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1260 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1261 | (u32)data[1], 13), 16384);
1262 return 0;
1263}
1264
1265static int cxd2841er_read_packet_errors_t(
1266 struct cxd2841er_priv *priv, u32 *penum)
1267{
1268 u8 data[3];
1269
1270 *penum = 0;
1271 if (priv->state != STATE_ACTIVE_TC) {
1272 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1273 __func__, priv->state);
1274 return -EINVAL;
1275 }
1276 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1277 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1278 if (data[2] & 0x01)
1279 *penum = ((u32)data[0] << 8) | (u32)data[1];
1280 return 0;
1281}
1282
1283static int cxd2841er_read_packet_errors_t2(
1284 struct cxd2841er_priv *priv, u32 *penum)
1285{
1286 u8 data[3];
1287
1288 *penum = 0;
1289 if (priv->state != STATE_ACTIVE_TC) {
1290 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1291 __func__, priv->state);
1292 return -EINVAL;
1293 }
1294 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1295 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1296 if (data[0] & 0x01)
1297 *penum = ((u32)data[1] << 8) | (u32)data[2];
1298 return 0;
1299}
1300
83808c23
AO		 1301static int cxd2841er_read_packet_errors_i(
1302 struct cxd2841er_priv *priv, u32 *penum)
1303{
1304 u8 data[2];
1305
1306 *penum = 0;
1307 if (priv->state != STATE_ACTIVE_TC) {
1308 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1309 __func__, priv->state);
1310 return -EINVAL;
1311 }
1312 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1313 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1314
1315 if (!(data[0] & 0x01))
1316 return 0;
1317
1318 /* Layer A */
1319 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1320 *penum = ((u32)data[0] << 8) | (u32)data[1];
1321
1322 /* Layer B */
1323 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1324 *penum += ((u32)data[0] << 8) | (u32)data[1];
1325
1326 /* Layer C */
1327 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1328 *penum += ((u32)data[0] << 8) | (u32)data[1];
1329
1330 return 0;
1331}
1332
f1b26622 1333static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv, u32 *ber)
a6dc60ff
KS		 1334{
1335 u8 data[11];
1336 u32 bit_error, bit_count;
1337 u32 temp_q, temp_r;
1338
1339 /* Set SLV-T Bank : 0xA0 */
1340 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1341 /*
1342 * slave Bank Addr Bit Signal name
1343 * <SLV-T> A0h 35h [0] IFVBER_VALID
1344 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1345 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1346 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1347 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1348 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1349 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1350 */
1351 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1352 if (data[0] & 0x01) {
1353 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1354 ((u32)(data[2] & 0xFF) << 8) |
1355 (u32)(data[3] & 0xFF);
1356 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1357 ((u32)(data[9] & 0xFF) << 8) |
1358 (u32)(data[10] & 0xFF);
1359 /*
1360 * BER = bitError / bitCount
1361 * = (bitError * 10^7) / bitCount
1362 * = ((bitError * 625 * 125 * 128) / bitCount
1363 */
1364 if ((bit_count == 0) || (bit_error > bit_count)) {
1365 dev_dbg(&priv->i2c->dev,
1366 "%s(): invalid bit_error %d, bit_count %d\n",
1367 __func__, bit_error, bit_count);
f1b26622 1368 return -EINVAL;
a6dc60ff
KS		 1369 }
1370 temp_q = div_u64_rem(10000000ULL * bit_error,
1371 bit_count, &temp_r);
1372 if (bit_count != 1 && temp_r >= bit_count / 2)
1373 temp_q++;
f1b26622
MCC		 1374 *ber = temp_q;
1375 return 0;
a6dc60ff
KS		 1376 }
1377 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
f1b26622 1378 return -EINVAL;
a6dc60ff
KS		 1379}
1380
1381
f1b26622 1382static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv, u32 *ber)
a6dc60ff
KS		 1383{
1384 u8 data[5];
1385 u32 bit_error, period;
1386 u32 temp_q, temp_r;
a6dc60ff
KS		 1387
1388 /* Set SLV-T Bank : 0xB2 */
1389 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1390 /*
1391 * slave Bank Addr Bit Signal name
1392 * <SLV-T> B2h 30h [0] IFLBER_VALID
1393 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1394 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1395 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1396 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1397 */
1398 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1399 if (data[0] & 0x01) {
1400 /* Bit error count */
1401 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1402 ((u32)(data[2] & 0xFF) << 16) |
1403 ((u32)(data[3] & 0xFF) << 8) |
1404 (u32)(data[4] & 0xFF);
1405
1406 /* Set SLV-T Bank : 0xA0 */
1407 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1408 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1409 /* Measurement period */
1410 period = (u32)(1 << (data[0] & 0x0F));
1411 if (period == 0) {
1412 dev_dbg(&priv->i2c->dev,
1413 "%s(): period is 0\n", __func__);
f1b26622 1414 return -EINVAL;
a6dc60ff
KS		 1415 }
1416 if (bit_error > (period * 64800)) {
1417 dev_dbg(&priv->i2c->dev,
1418 "%s(): invalid bit_err 0x%x period 0x%x\n",
1419 __func__, bit_error, period);
f1b26622 1420 return -EINVAL;
a6dc60ff
KS		 1421 }
1422 /*
1423 * BER = bitError / (period * 64800)
1424 * = (bitError * 10^7) / (period * 64800)
1425 * = (bitError * 10^5) / (period * 648)
1426 * = (bitError * 12500) / (period * 81)
1427 * = (bitError * 10) * 1250 / (period * 81)
1428 */
1429 temp_q = div_u64_rem(12500ULL * bit_error,
1430 period * 81, &temp_r);
1431 if (temp_r >= period * 40)
1432 temp_q++;
f1b26622
MCC		 1433 *ber = temp_q;
1434 return 0;
a6dc60ff
KS		 1435 } else {
1436 dev_dbg(&priv->i2c->dev,
1437 "%s(): no data available\n", __func__);
1438 }
f1b26622 1439 return -EINVAL;
a6dc60ff
KS		 1440}
1441
1442static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1443{
1444 u8 data[4];
1445 u32 div, q, r;
1446 u32 bit_err, period_exp, n_ldpc;
1447
1448 *ber = 0;
1449 if (priv->state != STATE_ACTIVE_TC) {
1450 dev_dbg(&priv->i2c->dev,
1451 "%s(): invalid state %d\n", __func__, priv->state);
1452 return -EINVAL;
1453 }
1454 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1455 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1456 if (!(data[0] & 0x10)) {
1457 dev_dbg(&priv->i2c->dev,
1458 "%s(): no valid BER data\n", __func__);
1459 return 0;
1460 }
1461 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1462 ((u32)data[1] << 16) |
1463 ((u32)data[2] << 8) |
1464 (u32)data[3];
1465 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1466 period_exp = data[0] & 0x0f;
1467 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1468 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1469 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1470 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1471 dev_dbg(&priv->i2c->dev,
1472 "%s(): invalid BER value\n", __func__);
1473 return -EINVAL;
1474 }
1475 if (period_exp >= 4) {
1476 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1477 q = div_u64_rem(3125ULL * bit_err, div, &r);
1478 } else {
1479 div = (1U << period_exp) * (n_ldpc / 200);
1480 q = div_u64_rem(50000ULL * bit_err, div, &r);
1481 }
1482 *ber = (r >= div / 2) ? q + 1 : q;
1483 return 0;
1484}
1485
1486static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1487{
1488 u8 data[2];
1489 u32 div, q, r;
1490 u32 bit_err, period;
1491
1492 *ber = 0;
1493 if (priv->state != STATE_ACTIVE_TC) {
1494 dev_dbg(&priv->i2c->dev,
1495 "%s(): invalid state %d\n", __func__, priv->state);
1496 return -EINVAL;
1497 }
1498 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1499 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1500 if (!(data[0] & 0x01)) {
1501 dev_dbg(&priv->i2c->dev,
1502 "%s(): no valid BER data\n", __func__);
1503 return 0;
1504 }
1505 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1506 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1507 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1508 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1509 div = period / 128;
1510 q = div_u64_rem(78125ULL * bit_err, div, &r);
1511 *ber = (r >= div / 2) ? q + 1 : q;
1512 return 0;
1513}
1514
1515static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1516{
1517 u8 data[3];
1518 u32 res = 0, value;
1519 int min_index, max_index, index;
1520 static const struct cxd2841er_cnr_data *cn_data;
1521
1522 /* Set SLV-T Bank : 0xA1 */
1523 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1524 /*
1525 * slave Bank Addr Bit Signal name
1526 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1527 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1528 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1529 */
1530 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1531 if (data[0] & 0x01) {
1532 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1533 min_index = 0;
1534 if (delsys == SYS_DVBS) {
1535 cn_data = s_cn_data;
1536 max_index = sizeof(s_cn_data) /
1537 sizeof(s_cn_data[0]) - 1;
1538 } else {
1539 cn_data = s2_cn_data;
1540 max_index = sizeof(s2_cn_data) /
1541 sizeof(s2_cn_data[0]) - 1;
1542 }
1543 if (value >= cn_data[min_index].value) {
1544 res = cn_data[min_index].cnr_x1000;
1545 goto done;
1546 }
1547 if (value <= cn_data[max_index].value) {
1548 res = cn_data[max_index].cnr_x1000;
1549 goto done;
1550 }
1551 while ((max_index - min_index) > 1) {
1552 index = (max_index + min_index) / 2;
1553 if (value == cn_data[index].value) {
1554 res = cn_data[index].cnr_x1000;
1555 goto done;
1556 } else if (value > cn_data[index].value)
1557 max_index = index;
1558 else
1559 min_index = index;
1560 if ((max_index - min_index) <= 1) {
1561 if (value == cn_data[max_index].value) {
1562 res = cn_data[max_index].cnr_x1000;
1563 goto done;
1564 } else {
1565 res = cn_data[min_index].cnr_x1000;
1566 goto done;
1567 }
1568 }
1569 }
1570 } else {
1571 dev_dbg(&priv->i2c->dev,
1572 "%s(): no data available\n", __func__);
1573 }
1574done:
1575 return res;
1576}
1577
1578static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1579{
1580 u32 reg;
1581 u8 data[2];
1582
1583 *snr = 0;
1584 if (priv->state != STATE_ACTIVE_TC) {
1585 dev_dbg(&priv->i2c->dev,
1586 "%s(): invalid state %d\n", __func__, priv->state);
1587 return -EINVAL;
1588 }
1589 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1590 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1591 reg = ((u32)data[0] << 8) | (u32)data[1];
1592 if (reg == 0) {
1593 dev_dbg(&priv->i2c->dev,
1594 "%s(): reg value out of range\n", __func__);
1595 return 0;
1596 }
1597 if (reg > 4996)
1598 reg = 4996;
1599 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1600 return 0;
1601}
1602
c8946c8d 1603static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
a6dc60ff
KS		 1604{
1605 u32 reg;
1606 u8 data[2];
1607
1608 *snr = 0;
1609 if (priv->state != STATE_ACTIVE_TC) {
1610 dev_dbg(&priv->i2c->dev,
1611 "%s(): invalid state %d\n", __func__, priv->state);
1612 return -EINVAL;
1613 }
1614 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1615 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1616 reg = ((u32)data[0] << 8) | (u32)data[1];
1617 if (reg == 0) {
1618 dev_dbg(&priv->i2c->dev,
1619 "%s(): reg value out of range\n", __func__);
1620 return 0;
1621 }
1622 if (reg > 10876)
1623 reg = 10876;
1624 *snr = 10000 * ((intlog10(reg) -
1625 intlog10(12600 - reg)) >> 24) + 32000;
1626 return 0;
1627}
1628
83808c23
AO		 1629static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1630{
1631 u32 reg;
1632 u8 data[2];
1633
1634 *snr = 0;
1635 if (priv->state != STATE_ACTIVE_TC) {
1636 dev_dbg(&priv->i2c->dev,
1637 "%s(): invalid state %d\n", __func__,
1638 priv->state);
1639 return -EINVAL;
1640 }
1641
1642 /* Freeze all registers */
1643 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1644
1645
1646 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1647 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1648 reg = ((u32)data[0] << 8) | (u32)data[1];
1649 if (reg == 0) {
1650 dev_dbg(&priv->i2c->dev,
1651 "%s(): reg value out of range\n", __func__);
1652 return 0;
1653 }
1654 if (reg > 4996)
1655 reg = 4996;
1656 *snr = 100 * intlog10(reg) - 9031;
1657 return 0;
1658}
1659
d0998ce7
AO		 1660static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1661 u8 delsys)
1662{
1663 u8 data[2];
1664
1665 cxd2841er_write_reg(
1666 priv, I2C_SLVT, 0x00, 0x40);
1667 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1668 dev_dbg(&priv->i2c->dev,
1669 "%s(): AGC value=%u\n",
1670 __func__, (((u16)data[0] & 0x0F) << 8) |
1671 (u16)(data[1] & 0xFF));
1672 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1673}
1674
a6dc60ff
KS		 1675static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1676 u8 delsys)
1677{
1678 u8 data[2];
1679
1680 cxd2841er_write_reg(
1681 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1682 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
c5ea46da
AO		 1683 dev_dbg(&priv->i2c->dev,
1684 "%s(): AGC value=%u\n",
1685 __func__, (((u16)data[0] & 0x0F) << 8) |
1686 (u16)(data[1] & 0xFF));
a6dc60ff
KS		 1687 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1688}
1689
83808c23
AO		 1690static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1691 u8 delsys)
1692{
1693 u8 data[2];
1694
1695 cxd2841er_write_reg(
1696 priv, I2C_SLVT, 0x00, 0x60);
1697 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1698
1699 dev_dbg(&priv->i2c->dev,
1700 "%s(): AGC value=%u\n",
1701 __func__, (((u16)data[0] & 0x0F) << 8) |
1702 (u16)(data[1] & 0xFF));
1703 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1704}
1705
a6dc60ff
KS		 1706static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1707{
1708 u8 data[2];
1709
1710 /* Set SLV-T Bank : 0xA0 */
1711 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1712 /*
1713 * slave Bank Addr Bit Signal name
1714 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1715 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1716 */
1717 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1718 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1719}
1720
f1b26622 1721static void cxd2841er_read_ber(struct dvb_frontend *fe)
a6dc60ff
KS		 1722{
1723 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1724 struct cxd2841er_priv *priv = fe->demodulator_priv;
f1b26622 1725 u32 ber = 0, ret;
a6dc60ff
KS		 1726
1727 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
a6dc60ff
KS		 1728 switch (p->delivery_system) {
1729 case SYS_DVBS:
f1b26622 1730 ret = cxd2841er_mon_read_ber_s(priv, &ber);
a6dc60ff
KS		 1731 break;
1732 case SYS_DVBS2:
f1b26622 1733 ret = cxd2841er_mon_read_ber_s2(priv, &ber);
a6dc60ff
KS		 1734 break;
1735 case SYS_DVBT:
f1b26622
MCC		 1736 ret = cxd2841er_read_ber_t(priv, &ber);
1737 break;
a6dc60ff 1738 case SYS_DVBT2:
f1b26622 1739 ret = cxd2841er_read_ber_t2(priv, &ber);
a6dc60ff 1740 break;
f1b26622
MCC		 1741 default:
1742 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1743 return;
1744 }
1745
1746 if (!ret) {
1747 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1748 p->post_bit_error.stat[0].uvalue = ber;
1749 } else {
1750 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 1751 }
a6dc60ff
KS		 1752}
1753
5fda1b65 1754static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
a6dc60ff
KS		 1755{
1756 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1757 struct cxd2841er_priv *priv = fe->demodulator_priv;
5fda1b65 1758 u32 strength;
a6dc60ff
KS		 1759
1760 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1761 switch (p->delivery_system) {
d0998ce7
AO		 1762 case SYS_DVBC_ANNEX_A:
1763 case SYS_DVBC_ANNEX_B:
1764 case SYS_DVBC_ANNEX_C:
1765 strength = 65535 - cxd2841er_read_agc_gain_c(
1766 priv, p->delivery_system);
1767 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1768 p->strength.stat[0].uvalue = strength;
1769 break;
a6dc60ff
KS		 1770 case SYS_DVBT:
1771 case SYS_DVBT2:
5fda1b65
MCC		 1772 strength = cxd2841er_read_agc_gain_t_t2(priv,
1773 p->delivery_system);
1774 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1775 /* Formula was empirically determinated @ 410 MHz */
1776 p->strength.stat[0].uvalue = ((s32)strength) * 366 / 100 - 89520;
1777 break; /* Code moved out of the function */
83808c23 1778 case SYS_ISDBT:
5fda1b65 1779 strength = 65535 - cxd2841er_read_agc_gain_i(
83808c23 1780 priv, p->delivery_system);
5fda1b65
MCC		 1781 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1782 p->strength.stat[0].uvalue = strength;
83808c23 1783 break;
a6dc60ff
KS		 1784 case SYS_DVBS:
1785 case SYS_DVBS2:
5fda1b65
MCC		 1786 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1787 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1788 p->strength.stat[0].uvalue = strength;
a6dc60ff
KS		 1789 break;
1790 default:
f1b26622 1791 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff
KS		 1792 break;
1793 }
a6dc60ff
KS		 1794}
1795
f1b26622 1796static void cxd2841er_read_snr(struct dvb_frontend *fe)
a6dc60ff
KS		 1797{
1798 u32 tmp = 0;
1799 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1800 struct cxd2841er_priv *priv = fe->demodulator_priv;
1801
1802 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1803 switch (p->delivery_system) {
1804 case SYS_DVBT:
1805 cxd2841er_read_snr_t(priv, &tmp);
1806 break;
1807 case SYS_DVBT2:
1808 cxd2841er_read_snr_t2(priv, &tmp);
1809 break;
83808c23
AO		 1810 case SYS_ISDBT:
1811 cxd2841er_read_snr_i(priv, &tmp);
1812 break;
a6dc60ff
KS		 1813 case SYS_DVBS:
1814 case SYS_DVBS2:
1815 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1816 break;
1817 default:
1818 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1819 __func__, p->delivery_system);
f1b26622
MCC		 1820 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1821 return;
a6dc60ff 1822 }
f1b26622
MCC		 1823
1824 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1825 p->cnr.stat[0].svalue = tmp;
a6dc60ff
KS		 1826}
1827
f1b26622 1828static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
a6dc60ff
KS		 1829{
1830 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1831 struct cxd2841er_priv *priv = fe->demodulator_priv;
f1b26622 1832 u32 ucblocks;
a6dc60ff
KS		 1833
1834 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1835 switch (p->delivery_system) {
1836 case SYS_DVBT:
f1b26622 1837 cxd2841er_read_packet_errors_t(priv, &ucblocks);
a6dc60ff
KS		 1838 break;
1839 case SYS_DVBT2:
f1b26622 1840 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
a6dc60ff 1841 break;
83808c23 1842 case SYS_ISDBT:
f1b26622 1843 cxd2841er_read_packet_errors_i(priv, &ucblocks);
83808c23 1844 break;
a6dc60ff 1845 default:
f1b26622
MCC		 1846 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1847 return;
a6dc60ff
KS		 1848 }
1849 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
f1b26622
MCC		 1850
1851 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
1852 p->block_error.stat[0].uvalue = ucblocks;
a6dc60ff
KS		 1853}
1854
1855static int cxd2841er_dvbt2_set_profile(
1856 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1857{
1858 u8 tune_mode;
1859 u8 seq_not2d_time;
1860
1861 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1862 switch (profile) {
1863 case DVBT2_PROFILE_BASE:
1864 tune_mode = 0x01;
6c77161a
AO		 1865 /* Set early unlock time */
1866 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
a6dc60ff
KS		 1867 break;
1868 case DVBT2_PROFILE_LITE:
1869 tune_mode = 0x05;
6c77161a
AO		 1870 /* Set early unlock time */
1871 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
a6dc60ff
KS		 1872 break;
1873 case DVBT2_PROFILE_ANY:
1874 tune_mode = 0x00;
6c77161a
AO		 1875 /* Set early unlock time */
1876 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
a6dc60ff
KS		 1877 break;
1878 default:
1879 return -EINVAL;
1880 }
1881 /* Set SLV-T Bank : 0x2E */
1882 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1883 /* Set profile and tune mode */
1884 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1885 /* Set SLV-T Bank : 0x2B */
1886 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1887 /* Set early unlock detection time */
1888 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1889 return 0;
1890}
1891
1892static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1893 u8 is_auto, u8 plp_id)
1894{
1895 if (is_auto) {
1896 dev_dbg(&priv->i2c->dev,
1897 "%s() using auto PLP selection\n", __func__);
1898 } else {
1899 dev_dbg(&priv->i2c->dev,
1900 "%s() using manual PLP selection, ID %d\n",
1901 __func__, plp_id);
1902 }
1903 /* Set SLV-T Bank : 0x23 */
1904 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1905 if (!is_auto) {
1906 /* Manual PLP selection mode. Set the data PLP Id. */
1907 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1908 }
1909 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1910 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1911 return 0;
1912}
1913
1914static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1915 u32 bandwidth)
1916{
1917 u32 iffreq;
6c77161a
AO		 1918 u8 data[MAX_WRITE_REGSIZE];
1919
1920 const uint8_t nominalRate8bw[3][5] = {
1921 /* TRCG Nominal Rate [37:0] */
1922 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1923 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1924 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1925 };
1926
1927 const uint8_t nominalRate7bw[3][5] = {
1928 /* TRCG Nominal Rate [37:0] */
1929 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1930 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1931 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1932 };
1933
1934 const uint8_t nominalRate6bw[3][5] = {
1935 /* TRCG Nominal Rate [37:0] */
1936 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1937 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1938 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1939 };
1940
1941 const uint8_t nominalRate5bw[3][5] = {
1942 /* TRCG Nominal Rate [37:0] */
1943 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1944 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1945 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1946 };
1947
1948 const uint8_t nominalRate17bw[3][5] = {
1949 /* TRCG Nominal Rate [37:0] */
1950 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
1951 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
1952 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
1953 };
1954
1955 const uint8_t itbCoef8bw[3][14] = {
1956 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1957 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1958 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
1959 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1960 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1961 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1962 };
1963
1964 const uint8_t itbCoef7bw[3][14] = {
1965 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1966 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1967 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
1968 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1969 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1970 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1971 };
1972
1973 const uint8_t itbCoef6bw[3][14] = {
1974 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1975 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1976 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1977 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1978 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1979 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1980 };
1981
1982 const uint8_t itbCoef5bw[3][14] = {
1983 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1984 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1985 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1986 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1987 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1988 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1989 };
1990
1991 const uint8_t itbCoef17bw[3][14] = {
1992 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1993 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
1994 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
1995 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
1996 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1997 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
1998 };
1999
2000 /* Set SLV-T Bank : 0x20 */
2001 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
a6dc60ff 2002
a6dc60ff
KS		 2003 switch (bandwidth) {
2004 case 8000000:
6c77161a
AO		 2005 /* <Timing Recovery setting> */
2006 cxd2841er_write_regs(priv, I2C_SLVT,
2007 0x9F, nominalRate8bw[priv->xtal], 5);
2008
2009 /* Set SLV-T Bank : 0x27 */
2010 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2011 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2012 0x7a, 0x00, 0x0f);
2013
2014 /* Set SLV-T Bank : 0x10 */
2015 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2016
2017 /* Group delay equaliser settings for
2018 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2019 */
2020 cxd2841er_write_regs(priv, I2C_SLVT,
2021 0xA6, itbCoef8bw[priv->xtal], 14);
2022 /* <IF freq setting> */
2023 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2024 data[0] = (u8) ((iffreq >> 16) & 0xff);
2025 data[1] = (u8)((iffreq >> 8) & 0xff);
2026 data[2] = (u8)(iffreq & 0xff);
2027 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2028 /* System bandwidth setting */
2029 cxd2841er_set_reg_bits(
2030 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
a6dc60ff
KS		 2031 break;
2032 case 7000000:
6c77161a
AO		 2033 /* <Timing Recovery setting> */
2034 cxd2841er_write_regs(priv, I2C_SLVT,
2035 0x9F, nominalRate7bw[priv->xtal], 5);
2036
2037 /* Set SLV-T Bank : 0x27 */
2038 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2039 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2040 0x7a, 0x00, 0x0f);
2041
2042 /* Set SLV-T Bank : 0x10 */
2043 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2044
2045 /* Group delay equaliser settings for
2046 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2047 */
2048 cxd2841er_write_regs(priv, I2C_SLVT,
2049 0xA6, itbCoef7bw[priv->xtal], 14);
2050 /* <IF freq setting> */
2051 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2052 data[0] = (u8) ((iffreq >> 16) & 0xff);
2053 data[1] = (u8)((iffreq >> 8) & 0xff);
2054 data[2] = (u8)(iffreq & 0xff);
2055 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2056 /* System bandwidth setting */
2057 cxd2841er_set_reg_bits(
2058 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
a6dc60ff
KS		 2059 break;
2060 case 6000000:
6c77161a
AO		 2061 /* <Timing Recovery setting> */
2062 cxd2841er_write_regs(priv, I2C_SLVT,
2063 0x9F, nominalRate6bw[priv->xtal], 5);
2064
2065 /* Set SLV-T Bank : 0x27 */
2066 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2067 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2068 0x7a, 0x00, 0x0f);
2069
2070 /* Set SLV-T Bank : 0x10 */
2071 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2072
2073 /* Group delay equaliser settings for
2074 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2075 */
2076 cxd2841er_write_regs(priv, I2C_SLVT,
2077 0xA6, itbCoef6bw[priv->xtal], 14);
2078 /* <IF freq setting> */
2079 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2080 data[0] = (u8) ((iffreq >> 16) & 0xff);
2081 data[1] = (u8)((iffreq >> 8) & 0xff);
2082 data[2] = (u8)(iffreq & 0xff);
2083 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2084 /* System bandwidth setting */
2085 cxd2841er_set_reg_bits(
2086 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
a6dc60ff
KS		 2087 break;
2088 case 5000000:
6c77161a
AO		 2089 /* <Timing Recovery setting> */
2090 cxd2841er_write_regs(priv, I2C_SLVT,
2091 0x9F, nominalRate5bw[priv->xtal], 5);
2092
2093 /* Set SLV-T Bank : 0x27 */
2094 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2095 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2096 0x7a, 0x00, 0x0f);
2097
2098 /* Set SLV-T Bank : 0x10 */
2099 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2100
2101 /* Group delay equaliser settings for
2102 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2103 */
2104 cxd2841er_write_regs(priv, I2C_SLVT,
2105 0xA6, itbCoef5bw[priv->xtal], 14);
2106 /* <IF freq setting> */
2107 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2108 data[0] = (u8) ((iffreq >> 16) & 0xff);
2109 data[1] = (u8)((iffreq >> 8) & 0xff);
2110 data[2] = (u8)(iffreq & 0xff);
2111 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2112 /* System bandwidth setting */
2113 cxd2841er_set_reg_bits(
2114 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
a6dc60ff
KS		 2115 break;
2116 case 1712000:
6c77161a
AO		 2117 /* <Timing Recovery setting> */
2118 cxd2841er_write_regs(priv, I2C_SLVT,
2119 0x9F, nominalRate17bw[priv->xtal], 5);
2120
2121 /* Set SLV-T Bank : 0x27 */
2122 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2123 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2124 0x7a, 0x03, 0x0f);
2125
2126 /* Set SLV-T Bank : 0x10 */
2127 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2128
2129 /* Group delay equaliser settings for
2130 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2131 */
2132 cxd2841er_write_regs(priv, I2C_SLVT,
2133 0xA6, itbCoef17bw[priv->xtal], 14);
2134 /* <IF freq setting> */
2135 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2136 data[0] = (u8) ((iffreq >> 16) & 0xff);
2137 data[1] = (u8)((iffreq >> 8) & 0xff);
2138 data[2] = (u8)(iffreq & 0xff);
2139 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2140 /* System bandwidth setting */
2141 cxd2841er_set_reg_bits(
2142 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
a6dc60ff
KS		 2143 break;
2144 default:
2145 return -EINVAL;
2146 }
a6dc60ff
KS		 2147 return 0;
2148}
2149
2150static int cxd2841er_sleep_tc_to_active_t_band(
2151 struct cxd2841er_priv *priv, u32 bandwidth)
2152{
83808c23 2153 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff 2154 u32 iffreq;
83808c23
AO		 2155 u8 nominalRate8bw[3][5] = {
2156 /* TRCG Nominal Rate [37:0] */
2157 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2158 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2159 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2160 };
2161 u8 nominalRate7bw[3][5] = {
2162 /* TRCG Nominal Rate [37:0] */
2163 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2164 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2165 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2166 };
2167 u8 nominalRate6bw[3][5] = {
2168 /* TRCG Nominal Rate [37:0] */
2169 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2170 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2171 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2172 };
2173 u8 nominalRate5bw[3][5] = {
2174 /* TRCG Nominal Rate [37:0] */
2175 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2176 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2177 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2178 };
a6dc60ff 2179
83808c23
AO		 2180 u8 itbCoef8bw[3][14] = {
2181 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2182 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2183 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2184 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2185 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2186 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2187 };
2188 u8 itbCoef7bw[3][14] = {
2189 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2190 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2191 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2192 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2193 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2194 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2195 };
2196 u8 itbCoef6bw[3][14] = {
2197 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2198 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2199 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2200 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2201 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2202 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2203 };
2204 u8 itbCoef5bw[3][14] = {
2205 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2206 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2207 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2208 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2209 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2210 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2211 };
2212
2213 /* Set SLV-T Bank : 0x13 */
a6dc60ff
KS		 2214 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2215 /* Echo performance optimization setting */
83808c23
AO		 2216 data[0] = 0x01;
2217 data[1] = 0x14;
2218 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2219
2220 /* Set SLV-T Bank : 0x10 */
a6dc60ff
KS		 2221 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2222
2223 switch (bandwidth) {
2224 case 8000000:
83808c23
AO		 2225 /* <Timing Recovery setting> */
2226 cxd2841er_write_regs(priv, I2C_SLVT,
2227 0x9F, nominalRate8bw[priv->xtal], 5);
2228 /* Group delay equaliser settings for
2229 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2230 */
2231 cxd2841er_write_regs(priv, I2C_SLVT,
2232 0xA6, itbCoef8bw[priv->xtal], 14);
2233 /* <IF freq setting> */
2234 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2235 data[0] = (u8) ((iffreq >> 16) & 0xff);
2236 data[1] = (u8)((iffreq >> 8) & 0xff);
2237 data[2] = (u8)(iffreq & 0xff);
2238 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2239 /* System bandwidth setting */
2240 cxd2841er_set_reg_bits(
2241 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2242
2243 /* Demod core latency setting */
2244 if (priv->xtal == SONY_XTAL_24000) {
2245 data[0] = 0x15;
2246 data[1] = 0x28;
2247 } else {
2248 data[0] = 0x01;
2249 data[1] = 0xE0;
2250 }
2251 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2252
2253 /* Notch filter setting */
2254 data[0] = 0x01;
2255 data[1] = 0x02;
2256 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2257 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2258 break;
2259 case 7000000:
83808c23
AO		 2260 /* <Timing Recovery setting> */
2261 cxd2841er_write_regs(priv, I2C_SLVT,
2262 0x9F, nominalRate7bw[priv->xtal], 5);
2263 /* Group delay equaliser settings for
2264 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2265 */
2266 cxd2841er_write_regs(priv, I2C_SLVT,
2267 0xA6, itbCoef7bw[priv->xtal], 14);
2268 /* <IF freq setting> */
2269 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2270 data[0] = (u8) ((iffreq >> 16) & 0xff);
2271 data[1] = (u8)((iffreq >> 8) & 0xff);
2272 data[2] = (u8)(iffreq & 0xff);
2273 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2274 /* System bandwidth setting */
2275 cxd2841er_set_reg_bits(
2276 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2277
2278 /* Demod core latency setting */
2279 if (priv->xtal == SONY_XTAL_24000) {
2280 data[0] = 0x1F;
2281 data[1] = 0xF8;
2282 } else {
2283 data[0] = 0x12;
2284 data[1] = 0xF8;
2285 }
2286 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2287
2288 /* Notch filter setting */
2289 data[0] = 0x00;
2290 data[1] = 0x03;
2291 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2292 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2293 break;
2294 case 6000000:
83808c23
AO		 2295 /* <Timing Recovery setting> */
2296 cxd2841er_write_regs(priv, I2C_SLVT,
2297 0x9F, nominalRate6bw[priv->xtal], 5);
2298 /* Group delay equaliser settings for
2299 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2300 */
2301 cxd2841er_write_regs(priv, I2C_SLVT,
2302 0xA6, itbCoef6bw[priv->xtal], 14);
2303 /* <IF freq setting> */
2304 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2305 data[0] = (u8) ((iffreq >> 16) & 0xff);
2306 data[1] = (u8)((iffreq >> 8) & 0xff);
2307 data[2] = (u8)(iffreq & 0xff);
2308 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2309 /* System bandwidth setting */
2310 cxd2841er_set_reg_bits(
2311 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2312
2313 /* Demod core latency setting */
2314 if (priv->xtal == SONY_XTAL_24000) {
2315 data[0] = 0x25;
2316 data[1] = 0x4C;
2317 } else {
2318 data[0] = 0x1F;
2319 data[1] = 0xDC;
2320 }
2321 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2322
2323 /* Notch filter setting */
2324 data[0] = 0x00;
2325 data[1] = 0x03;
2326 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2327 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
a6dc60ff
KS		 2328 break;
2329 case 5000000:
83808c23
AO		 2330 /* <Timing Recovery setting> */
2331 cxd2841er_write_regs(priv, I2C_SLVT,
2332 0x9F, nominalRate5bw[priv->xtal], 5);
2333 /* Group delay equaliser settings for
2334 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2335 */
2336 cxd2841er_write_regs(priv, I2C_SLVT,
2337 0xA6, itbCoef5bw[priv->xtal], 14);
2338 /* <IF freq setting> */
2339 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2340 data[0] = (u8) ((iffreq >> 16) & 0xff);
2341 data[1] = (u8)((iffreq >> 8) & 0xff);
2342 data[2] = (u8)(iffreq & 0xff);
2343 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2344 /* System bandwidth setting */
2345 cxd2841er_set_reg_bits(
2346 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2347
2348 /* Demod core latency setting */
2349 if (priv->xtal == SONY_XTAL_24000) {
2350 data[0] = 0x2C;
2351 data[1] = 0xC2;
2352 } else {
2353 data[0] = 0x26;
2354 data[1] = 0x3C;
2355 }
2356 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2357
2358 /* Notch filter setting */
2359 data[0] = 0x00;
2360 data[1] = 0x03;
2361 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2362 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2363 break;
2364 }
2365
2366 return 0;
2367}
2368
2369static int cxd2841er_sleep_tc_to_active_i_band(
2370 struct cxd2841er_priv *priv, u32 bandwidth)
2371{
2372 u32 iffreq;
2373 u8 data[3];
2374
2375 /* TRCG Nominal Rate */
2376 u8 nominalRate8bw[3][5] = {
2377 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2378 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2379 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2380 };
2381
2382 u8 nominalRate7bw[3][5] = {
2383 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2384 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2385 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2386 };
2387
2388 u8 nominalRate6bw[3][5] = {
2389 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2390 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2391 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2392 };
2393
2394 u8 itbCoef8bw[3][14] = {
2395 {0x00}, /* 20.5MHz XTal */
2396 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2397 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2398 {0x0}, /* 41MHz XTal */
2399 };
2400
2401 u8 itbCoef7bw[3][14] = {
2402 {0x00}, /* 20.5MHz XTal */
2403 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2404 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2405 {0x00}, /* 41MHz XTal */
2406 };
2407
2408 u8 itbCoef6bw[3][14] = {
2409 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2410 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2411 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2412 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2413 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2414 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2415 };
2416
2417 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2418 /* Set SLV-T Bank : 0x10 */
2419 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2420
2421 /* 20.5/41MHz Xtal support is not available
2422 * on ISDB-T 7MHzBW and 8MHzBW
2423 */
2424 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2425 dev_err(&priv->i2c->dev,
2426 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2427 __func__, bandwidth);
2428 return -EINVAL;
2429 }
2430
2431 switch (bandwidth) {
2432 case 8000000:
2433 /* TRCG Nominal Rate */
2434 cxd2841er_write_regs(priv, I2C_SLVT,
2435 0x9F, nominalRate8bw[priv->xtal], 5);
2436 /* Group delay equaliser settings for ASCOT tuners optimized */
2437 cxd2841er_write_regs(priv, I2C_SLVT,
2438 0xA6, itbCoef8bw[priv->xtal], 14);
2439
2440 /* IF freq setting */
2441 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2442 data[0] = (u8) ((iffreq >> 16) & 0xff);
2443 data[1] = (u8)((iffreq >> 8) & 0xff);
2444 data[2] = (u8)(iffreq & 0xff);
2445 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2446
2447 /* System bandwidth setting */
2448 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2449
2450 /* Demod core latency setting */
2451 data[0] = 0x13;
2452 data[1] = 0xFC;
2453 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2454
2455 /* Acquisition optimization setting */
2456 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2457 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2458 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2459 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2460 break;
2461 case 7000000:
2462 /* TRCG Nominal Rate */
2463 cxd2841er_write_regs(priv, I2C_SLVT,
2464 0x9F, nominalRate7bw[priv->xtal], 5);
2465 /* Group delay equaliser settings for ASCOT tuners optimized */
2466 cxd2841er_write_regs(priv, I2C_SLVT,
2467 0xA6, itbCoef7bw[priv->xtal], 14);
2468
2469 /* IF freq setting */
2470 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2471 data[0] = (u8) ((iffreq >> 16) & 0xff);
2472 data[1] = (u8)((iffreq >> 8) & 0xff);
2473 data[2] = (u8)(iffreq & 0xff);
2474 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2475
2476 /* System bandwidth setting */
2477 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2478
2479 /* Demod core latency setting */
2480 data[0] = 0x1A;
2481 data[1] = 0xFA;
2482 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2483
2484 /* Acquisition optimization setting */
2485 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2486 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2487 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2488 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2489 break;
2490 case 6000000:
2491 /* TRCG Nominal Rate */
2492 cxd2841er_write_regs(priv, I2C_SLVT,
2493 0x9F, nominalRate6bw[priv->xtal], 5);
2494 /* Group delay equaliser settings for ASCOT tuners optimized */
2495 cxd2841er_write_regs(priv, I2C_SLVT,
2496 0xA6, itbCoef6bw[priv->xtal], 14);
2497
2498 /* IF freq setting */
2499 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2500 data[0] = (u8) ((iffreq >> 16) & 0xff);
2501 data[1] = (u8)((iffreq >> 8) & 0xff);
2502 data[2] = (u8)(iffreq & 0xff);
2503 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2504
2505 /* System bandwidth setting */
2506 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2507
2508 /* Demod core latency setting */
2509 if (priv->xtal == SONY_XTAL_24000) {
2510 data[0] = 0x1F;
2511 data[1] = 0x79;
2512 } else {
2513 data[0] = 0x1A;
2514 data[1] = 0xE2;
2515 }
2516 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2517
2518 /* Acquisition optimization setting */
2519 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2520 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2521 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2522 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
a6dc60ff
KS		 2523 break;
2524 default:
2525 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
83808c23 2526 __func__, bandwidth);
a6dc60ff
KS		 2527 return -EINVAL;
2528 }
a6dc60ff
KS		 2529 return 0;
2530}
2531
2532static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2533 u32 bandwidth)
2534{
2535 u8 bw7_8mhz_b10_a6[] = {
2536 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2537 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2538 u8 bw6mhz_b10_a6[] = {
2539 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2540 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2541 u8 b10_b6[3];
2542 u32 iffreq;
2543
3f3b48a0 2544 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
a6dc60ff
KS		 2545 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2546 switch (bandwidth) {
2547 case 8000000:
2548 case 7000000:
2549 cxd2841er_write_regs(
2550 priv, I2C_SLVT, 0xa6,
2551 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2552 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2553 break;
2554 case 6000000:
2555 cxd2841er_write_regs(
2556 priv, I2C_SLVT, 0xa6,
2557 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2558 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2559 break;
2560 default:
3f3b48a0 2561 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
a6dc60ff
KS		 2562 __func__, bandwidth);
2563 return -EINVAL;
2564 }
2565 /* <IF freq setting> */
2566 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2567 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2568 b10_b6[2] = (u8)(iffreq & 0xff);
2569 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2570 /* Set SLV-T Bank : 0x11 */
2571 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2572 switch (bandwidth) {
2573 case 8000000:
2574 case 7000000:
2575 cxd2841er_set_reg_bits(
2576 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2577 break;
2578 case 6000000:
2579 cxd2841er_set_reg_bits(
2580 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2581 break;
2582 }
2583 /* Set SLV-T Bank : 0x40 */
2584 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2585 switch (bandwidth) {
2586 case 8000000:
2587 cxd2841er_set_reg_bits(
2588 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2589 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2590 break;
2591 case 7000000:
2592 cxd2841er_set_reg_bits(
2593 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2594 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2595 break;
2596 case 6000000:
2597 cxd2841er_set_reg_bits(
2598 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2599 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2600 break;
2601 }
2602 return 0;
2603}
2604
2605static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2606 u32 bandwidth)
2607{
2608 u8 data[2] = { 0x09, 0x54 };
83808c23 2609 u8 data24m[3] = {0xDC, 0x6C, 0x00};
a6dc60ff
KS		 2610
2611 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2612 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2613 /* Set SLV-X Bank : 0x00 */
2614 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2615 /* Set demod mode */
2616 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2617 /* Set SLV-T Bank : 0x00 */
2618 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2619 /* Enable demod clock */
2620 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2621 /* Disable RF level monitor */
2622 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2623 /* Enable ADC clock */
2624 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2625 /* Enable ADC 1 */
2626 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
83808c23
AO		 2627 /* Enable ADC 2 & 3 */
2628 if (priv->xtal == SONY_XTAL_41000) {
2629 data[0] = 0x0A;
2630 data[1] = 0xD4;
2631 }
a6dc60ff
KS		 2632 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2633 /* Enable ADC 4 */
2634 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2635 /* Set SLV-T Bank : 0x10 */
2636 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2637 /* IFAGC gain settings */
2638 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2639 /* Set SLV-T Bank : 0x11 */
2640 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2641 /* BBAGC TARGET level setting */
2642 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2643 /* Set SLV-T Bank : 0x10 */
2644 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2645 /* ASCOT setting ON */
2646 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2647 /* Set SLV-T Bank : 0x18 */
2648 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2649 /* Pre-RS BER moniter setting */
2650 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2651 /* FEC Auto Recovery setting */
2652 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2653 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2654 /* Set SLV-T Bank : 0x00 */
2655 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2656 /* TSIF setting */
2657 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2658 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
83808c23
AO		 2659
2660 if (priv->xtal == SONY_XTAL_24000) {
2661 /* Set SLV-T Bank : 0x10 */
2662 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2663 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2664 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2665 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2666 }
2667
a6dc60ff
KS		 2668 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2669 /* Set SLV-T Bank : 0x00 */
2670 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2671 /* Disable HiZ Setting 1 */
2672 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2673 /* Disable HiZ Setting 2 */
2674 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2675 priv->state = STATE_ACTIVE_TC;
2676 return 0;
2677}
2678
2679static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2680 u32 bandwidth)
2681{
6c77161a 2682 u8 data[MAX_WRITE_REGSIZE];
a6dc60ff
KS		 2683
2684 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2685 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2686 /* Set SLV-X Bank : 0x00 */
2687 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2688 /* Set demod mode */
2689 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2690 /* Set SLV-T Bank : 0x00 */
2691 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2692 /* Enable demod clock */
2693 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2694 /* Disable RF level monitor */
6c77161a 2695 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
a6dc60ff
KS		 2696 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2697 /* Enable ADC clock */
2698 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2699 /* Enable ADC 1 */
2700 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
6c77161a
AO		 2701
2702 if (priv->xtal == SONY_XTAL_41000) {
2703 data[0] = 0x0A;
2704 data[1] = 0xD4;
2705 } else {
2706 data[0] = 0x09;
2707 data[1] = 0x54;
2708 }
2709
a6dc60ff
KS		 2710 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2711 /* Enable ADC 4 */
2712 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2713 /* Set SLV-T Bank : 0x10 */
2714 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2715 /* IFAGC gain settings */
2716 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2717 /* Set SLV-T Bank : 0x11 */
2718 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2719 /* BBAGC TARGET level setting */
2720 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2721 /* Set SLV-T Bank : 0x10 */
2722 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2723 /* ASCOT setting ON */
2724 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2725 /* Set SLV-T Bank : 0x20 */
2726 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2727 /* Acquisition optimization setting */
2728 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2729 /* Set SLV-T Bank : 0x2b */
2730 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2731 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
6c77161a
AO		 2732 /* Set SLV-T Bank : 0x23 */
2733 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2734 /* L1 Control setting */
2735 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
a6dc60ff
KS		 2736 /* Set SLV-T Bank : 0x00 */
2737 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2738 /* TSIF setting */
2739 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2740 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2741 /* DVB-T2 initial setting */
2742 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2743 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2744 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2745 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2746 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2747 /* Set SLV-T Bank : 0x2a */
2748 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2749 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2750 /* Set SLV-T Bank : 0x2b */
2751 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2752 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2753
6c77161a
AO		 2754 /* 24MHz Xtal setting */
2755 if (priv->xtal == SONY_XTAL_24000) {
2756 /* Set SLV-T Bank : 0x11 */
2757 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2758 data[0] = 0xEB;
2759 data[1] = 0x03;
2760 data[2] = 0x3B;
2761 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2762
2763 /* Set SLV-T Bank : 0x20 */
2764 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2765 data[0] = 0x5E;
2766 data[1] = 0x5E;
2767 data[2] = 0x47;
2768 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2769
2770 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2771
2772 data[0] = 0x3F;
2773 data[1] = 0xFF;
2774 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2775
2776 /* Set SLV-T Bank : 0x24 */
2777 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2778 data[0] = 0x0B;
2779 data[1] = 0x72;
2780 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2781
2782 data[0] = 0x93;
2783 data[1] = 0xF3;
2784 data[2] = 0x00;
2785 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2786
2787 data[0] = 0x05;
2788 data[1] = 0xB8;
2789 data[2] = 0xD8;
2790 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2791
2792 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2793
2794 /* Set SLV-T Bank : 0x25 */
2795 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2796 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2797
2798 /* Set SLV-T Bank : 0x27 */
2799 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2800 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2801
2802 /* Set SLV-T Bank : 0x2B */
2803 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2804 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2805 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2806
2807 /* Set SLV-T Bank : 0x2D */
2808 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2809 data[0] = 0x89;
2810 data[1] = 0x89;
2811 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2812
2813 /* Set SLV-T Bank : 0x5E */
2814 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2815 data[0] = 0x24;
2816 data[1] = 0x95;
2817 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2818 }
2819
a6dc60ff
KS		 2820 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2821
2822 /* Set SLV-T Bank : 0x00 */
2823 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2824 /* Disable HiZ Setting 1 */
2825 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2826 /* Disable HiZ Setting 2 */
2827 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2828 priv->state = STATE_ACTIVE_TC;
2829 return 0;
2830}
2831
83808c23
AO		 2832/* ISDB-Tb part */
2833static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2834 u32 bandwidth)
2835{
2836 u8 data[2] = { 0x09, 0x54 };
2837 u8 data24m[2] = {0x60, 0x00};
2838 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2839
2840 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2841 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2842 /* Set SLV-X Bank : 0x00 */
2843 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2844 /* Set demod mode */
2845 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2846 /* Set SLV-T Bank : 0x00 */
2847 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2848 /* Enable demod clock */
2849 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2850 /* Enable RF level monitor */
2851 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2852 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2853 /* Enable ADC clock */
2854 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2855 /* Enable ADC 1 */
2856 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2857 /* xtal freq 20.5MHz or 24M */
2858 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2859 /* Enable ADC 4 */
2860 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2861 /* ASCOT setting ON */
2862 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2863 /* FEC Auto Recovery setting */
2864 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2865 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2866 /* ISDB-T initial setting */
2867 /* Set SLV-T Bank : 0x00 */
2868 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2869 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2870 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2871 /* Set SLV-T Bank : 0x10 */
2872 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2873 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2874 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2875 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2876 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2877 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2878 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2879 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2880 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2881 /* Set SLV-T Bank : 0x15 */
2882 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2883 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2884 /* Set SLV-T Bank : 0x1E */
2885 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2886 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2887 /* Set SLV-T Bank : 0x63 */
2888 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2889 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2890
2891 /* for xtal 24MHz */
2892 /* Set SLV-T Bank : 0x10 */
2893 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2894 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2895 /* Set SLV-T Bank : 0x60 */
2896 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2897 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2898
2899 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2900 /* Set SLV-T Bank : 0x00 */
2901 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2902 /* Disable HiZ Setting 1 */
2903 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2904 /* Disable HiZ Setting 2 */
2905 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2906 priv->state = STATE_ACTIVE_TC;
2907 return 0;
2908}
2909
a6dc60ff
KS		 2910static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2911 u32 bandwidth)
2912{
2913 u8 data[2] = { 0x09, 0x54 };
2914
2915 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2916 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2917 /* Set SLV-X Bank : 0x00 */
2918 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2919 /* Set demod mode */
2920 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2921 /* Set SLV-T Bank : 0x00 */
2922 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2923 /* Enable demod clock */
2924 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2925 /* Disable RF level monitor */
2926 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2927 /* Enable ADC clock */
2928 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2929 /* Enable ADC 1 */
2930 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2931 /* xtal freq 20.5MHz */
2932 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2933 /* Enable ADC 4 */
2934 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2935 /* Set SLV-T Bank : 0x10 */
2936 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2937 /* IFAGC gain settings */
2938 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2939 /* Set SLV-T Bank : 0x11 */
2940 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2941 /* BBAGC TARGET level setting */
2942 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2943 /* Set SLV-T Bank : 0x10 */
2944 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2945 /* ASCOT setting ON */
2946 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2947 /* Set SLV-T Bank : 0x40 */
2948 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2949 /* Demod setting */
2950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2951 /* Set SLV-T Bank : 0x00 */
2952 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2953 /* TSIF setting */
2954 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2955 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2956
3f3b48a0 2957 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
a6dc60ff
KS		 2958 /* Set SLV-T Bank : 0x00 */
2959 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2960 /* Disable HiZ Setting 1 */
2961 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2962 /* Disable HiZ Setting 2 */
2963 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2964 priv->state = STATE_ACTIVE_TC;
2965 return 0;
2966}
2967
7e3e68bc
MCC		 2968static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2969 struct dtv_frontend_properties *p)
a6dc60ff
KS		 2970{
2971 enum fe_status status = 0;
a6dc60ff 2972 struct cxd2841er_priv *priv = fe->demodulator_priv;
a6dc60ff
KS		 2973
2974 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2975 if (priv->state == STATE_ACTIVE_S)
2976 cxd2841er_read_status_s(fe, &status);
2977 else if (priv->state == STATE_ACTIVE_TC)
2978 cxd2841er_read_status_tc(fe, &status);
2979
5fda1b65 2980 cxd2841er_read_signal_strength(fe);
d0e20e13 2981
a6dc60ff 2982 if (status & FE_HAS_LOCK) {
f1b26622
MCC		 2983 cxd2841er_read_snr(fe);
2984 cxd2841er_read_ucblocks(fe);
d0e20e13 2985
f1b26622 2986 cxd2841er_read_ber(fe);
a6dc60ff 2987 } else {
a6dc60ff 2988 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff 2989 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
a6dc60ff
KS		 2990 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2991 }
2992 return 0;
2993}
2994
2995static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2996{
2997 int ret = 0, i, timeout, carr_offset;
2998 enum fe_status status;
2999 struct cxd2841er_priv *priv = fe->demodulator_priv;
3000 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3001 u32 symbol_rate = p->symbol_rate/1000;
3002
83808c23 3003 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
a6dc60ff
KS		 3004 __func__,
3005 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
83808c23 3006 p->frequency, symbol_rate, priv->xtal);
a6dc60ff
KS		 3007 switch (priv->state) {
3008 case STATE_SLEEP_S:
3009 ret = cxd2841er_sleep_s_to_active_s(
3010 priv, p->delivery_system, symbol_rate);
3011 break;
3012 case STATE_ACTIVE_S:
3013 ret = cxd2841er_retune_active(priv, p);
3014 break;
3015 default:
3016 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3017 __func__, priv->state);
3018 ret = -EINVAL;
3019 goto done;
3020 }
3021 if (ret) {
3022 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3023 goto done;
3024 }
3025 if (fe->ops.i2c_gate_ctrl)
3026 fe->ops.i2c_gate_ctrl(fe, 1);
3027 if (fe->ops.tuner_ops.set_params)
3028 fe->ops.tuner_ops.set_params(fe);
3029 if (fe->ops.i2c_gate_ctrl)
3030 fe->ops.i2c_gate_ctrl(fe, 0);
3031 cxd2841er_tune_done(priv);
3032 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3033 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3034 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3035 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3036 cxd2841er_read_status_s(fe, &status);
3037 if (status & FE_HAS_LOCK)
3038 break;
3039 }
3040 if (status & FE_HAS_LOCK) {
3041 if (cxd2841er_get_carrier_offset_s_s2(
3042 priv, &carr_offset)) {
3043 ret = -EINVAL;
3044 goto done;
3045 }
3046 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3047 __func__, carr_offset);
3048 }
3049done:
d0e20e13
MCC		 3050 /* Reset stats */
3051 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3052 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3053 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3054 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3055
a6dc60ff
KS		 3056 return ret;
3057}
3058
3059static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3060{
3061 int ret = 0, timeout;
3062 enum fe_status status;
3063 struct cxd2841er_priv *priv = fe->demodulator_priv;
3064 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3065
3f3b48a0
AO		 3066 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3067 __func__, p->delivery_system, p->bandwidth_hz);
a6dc60ff
KS		 3068 if (p->delivery_system == SYS_DVBT) {
3069 priv->system = SYS_DVBT;
3070 switch (priv->state) {
3071 case STATE_SLEEP_TC:
3072 ret = cxd2841er_sleep_tc_to_active_t(
3073 priv, p->bandwidth_hz);
3074 break;
3075 case STATE_ACTIVE_TC:
3076 ret = cxd2841er_retune_active(priv, p);
3077 break;
3078 default:
3079 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3080 __func__, priv->state);
3081 ret = -EINVAL;
3082 }
3083 } else if (p->delivery_system == SYS_DVBT2) {
3084 priv->system = SYS_DVBT2;
3085 cxd2841er_dvbt2_set_plp_config(priv,
3086 (int)(p->stream_id > 255), p->stream_id);
3087 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3088 switch (priv->state) {
3089 case STATE_SLEEP_TC:
3090 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3091 p->bandwidth_hz);
3092 break;
3093 case STATE_ACTIVE_TC:
3094 ret = cxd2841er_retune_active(priv, p);
3095 break;
3096 default:
3097 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3098 __func__, priv->state);
3099 ret = -EINVAL;
3100 }
83808c23
AO		 3101 } else if (p->delivery_system == SYS_ISDBT) {
3102 priv->system = SYS_ISDBT;
3103 switch (priv->state) {
3104 case STATE_SLEEP_TC:
3105 ret = cxd2841er_sleep_tc_to_active_i(
3106 priv, p->bandwidth_hz);
3107 break;
3108 case STATE_ACTIVE_TC:
3109 ret = cxd2841er_retune_active(priv, p);
3110 break;
3111 default:
3112 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3113 __func__, priv->state);
3114 ret = -EINVAL;
3115 }
a6dc60ff
KS		 3116 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3117 p->delivery_system == SYS_DVBC_ANNEX_C) {
3118 priv->system = SYS_DVBC_ANNEX_A;
3f3b48a0
AO		 3119 /* correct bandwidth */
3120 if (p->bandwidth_hz != 6000000 &&
3121 p->bandwidth_hz != 7000000 &&
3122 p->bandwidth_hz != 8000000) {
3123 p->bandwidth_hz = 8000000;
3124 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3125 __func__, p->bandwidth_hz);
3126 }
3127
a6dc60ff
KS		 3128 switch (priv->state) {
3129 case STATE_SLEEP_TC:
3130 ret = cxd2841er_sleep_tc_to_active_c(
3131 priv, p->bandwidth_hz);
3132 break;
3133 case STATE_ACTIVE_TC:
3134 ret = cxd2841er_retune_active(priv, p);
3135 break;
3136 default:
3137 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3138 __func__, priv->state);
3139 ret = -EINVAL;
3140 }
3141 } else {
3142 dev_dbg(&priv->i2c->dev,
3143 "%s(): invalid delivery system %d\n",
3144 __func__, p->delivery_system);
3145 ret = -EINVAL;
3146 }
3147 if (ret)
3148 goto done;
3149 if (fe->ops.i2c_gate_ctrl)
3150 fe->ops.i2c_gate_ctrl(fe, 1);
3151 if (fe->ops.tuner_ops.set_params)
3152 fe->ops.tuner_ops.set_params(fe);
3153 if (fe->ops.i2c_gate_ctrl)
3154 fe->ops.i2c_gate_ctrl(fe, 0);
3155 cxd2841er_tune_done(priv);
3156 timeout = 2500;
3157 while (timeout > 0) {
3158 ret = cxd2841er_read_status_tc(fe, &status);
3159 if (ret)
3160 goto done;
3161 if (status & FE_HAS_LOCK)
3162 break;
3163 msleep(20);
3164 timeout -= 20;
3165 }
3166 if (timeout < 0)
3167 dev_dbg(&priv->i2c->dev,
3168 "%s(): LOCK wait timeout\n", __func__);
3169done:
3170 return ret;
3171}
3172
3173static int cxd2841er_tune_s(struct dvb_frontend *fe,
3174 bool re_tune,
3175 unsigned int mode_flags,
3176 unsigned int *delay,
3177 enum fe_status *status)
3178{
3179 int ret, carrier_offset;
3180 struct cxd2841er_priv *priv = fe->demodulator_priv;
3181 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3182
3183 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3184 if (re_tune) {
3185 ret = cxd2841er_set_frontend_s(fe);
3186 if (ret)
3187 return ret;
3188 cxd2841er_read_status_s(fe, status);
3189 if (*status & FE_HAS_LOCK) {
3190 if (cxd2841er_get_carrier_offset_s_s2(
3191 priv, &carrier_offset))
3192 return -EINVAL;
3193 p->frequency += carrier_offset;
3194 ret = cxd2841er_set_frontend_s(fe);
3195 if (ret)
3196 return ret;
3197 }
3198 }
3199 *delay = HZ / 5;
3200 return cxd2841er_read_status_s(fe, status);
3201}
3202
3203static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3204 bool re_tune,
3205 unsigned int mode_flags,
3206 unsigned int *delay,
3207 enum fe_status *status)
3208{
3209 int ret, carrier_offset;
3210 struct cxd2841er_priv *priv = fe->demodulator_priv;
3211 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3212
3f3b48a0
AO		 3213 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3214 re_tune, p->bandwidth_hz);
a6dc60ff
KS		 3215 if (re_tune) {
3216 ret = cxd2841er_set_frontend_tc(fe);
3217 if (ret)
3218 return ret;
3219 cxd2841er_read_status_tc(fe, status);
3220 if (*status & FE_HAS_LOCK) {
3221 switch (priv->system) {
76344a3f
MCC		 3222 case SYS_ISDBT:
3223 ret = cxd2841er_get_carrier_offset_i(
3224 priv, p->bandwidth_hz,
3225 &carrier_offset);
3226 break;
a6dc60ff 3227 case SYS_DVBT:
c5ea46da
AO		 3228 ret = cxd2841er_get_carrier_offset_t(
3229 priv, p->bandwidth_hz,
3230 &carrier_offset);
3231 break;
a6dc60ff
KS		 3232 case SYS_DVBT2:
3233 ret = cxd2841er_get_carrier_offset_t2(
3234 priv, p->bandwidth_hz,
3235 &carrier_offset);
3236 break;
3237 case SYS_DVBC_ANNEX_A:
3238 ret = cxd2841er_get_carrier_offset_c(
3239 priv, &carrier_offset);
3240 break;
3241 default:
3242 dev_dbg(&priv->i2c->dev,
3243 "%s(): invalid delivery system %d\n",
3244 __func__, priv->system);
3245 return -EINVAL;
3246 }
3247 if (ret)
3248 return ret;
3249 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3250 __func__, carrier_offset);
3251 p->frequency += carrier_offset;
3252 ret = cxd2841er_set_frontend_tc(fe);
3253 if (ret)
3254 return ret;
3255 }
3256 }
3257 *delay = HZ / 5;
3258 return cxd2841er_read_status_tc(fe, status);
3259}
3260
3261static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3262{
3263 struct cxd2841er_priv *priv = fe->demodulator_priv;
3264
3265 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3266 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3267 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3268 return 0;
3269}
3270
3271static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3272{
3273 struct cxd2841er_priv *priv = fe->demodulator_priv;
3274
3275 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3276 if (priv->state == STATE_ACTIVE_TC) {
3277 switch (priv->system) {
3278 case SYS_DVBT:
3279 cxd2841er_active_t_to_sleep_tc(priv);
3280 break;
3281 case SYS_DVBT2:
3282 cxd2841er_active_t2_to_sleep_tc(priv);
3283 break;
83808c23
AO		 3284 case SYS_ISDBT:
3285 cxd2841er_active_i_to_sleep_tc(priv);
3286 break;
a6dc60ff
KS		 3287 case SYS_DVBC_ANNEX_A:
3288 cxd2841er_active_c_to_sleep_tc(priv);
3289 break;
3290 default:
3291 dev_warn(&priv->i2c->dev,
3292 "%s(): unknown delivery system %d\n",
3293 __func__, priv->system);
3294 }
3295 }
3296 if (priv->state != STATE_SLEEP_TC) {
3297 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3298 __func__, priv->state);
3299 return -EINVAL;
3300 }
3301 cxd2841er_sleep_tc_to_shutdown(priv);
3302 return 0;
3303}
3304
3305static int cxd2841er_send_burst(struct dvb_frontend *fe,
3306 enum fe_sec_mini_cmd burst)
3307{
3308 u8 data;
3309 struct cxd2841er_priv *priv = fe->demodulator_priv;
3310
3311 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3312 (burst == SEC_MINI_A ? "A" : "B"));
3313 if (priv->state != STATE_SLEEP_S &&
3314 priv->state != STATE_ACTIVE_S) {
3315 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3316 __func__, priv->state);
3317 return -EINVAL;
3318 }
3319 data = (burst == SEC_MINI_A ? 0 : 1);
3320 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3321 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3322 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3323 return 0;
3324}
3325
3326static int cxd2841er_set_tone(struct dvb_frontend *fe,
3327 enum fe_sec_tone_mode tone)
3328{
3329 u8 data;
3330 struct cxd2841er_priv *priv = fe->demodulator_priv;
3331
3332 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3333 (tone == SEC_TONE_ON ? "On" : "Off"));
3334 if (priv->state != STATE_SLEEP_S &&
3335 priv->state != STATE_ACTIVE_S) {
3336 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3337 __func__, priv->state);
3338 return -EINVAL;
3339 }
3340 data = (tone == SEC_TONE_ON ? 1 : 0);
3341 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3342 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3343 return 0;
3344}
3345
3346static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3347 struct dvb_diseqc_master_cmd *cmd)
3348{
3349 int i;
3350 u8 data[12];
3351 struct cxd2841er_priv *priv = fe->demodulator_priv;
3352
3353 if (priv->state != STATE_SLEEP_S &&
3354 priv->state != STATE_ACTIVE_S) {
3355 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3356 __func__, priv->state);
3357 return -EINVAL;
3358 }
3359 dev_dbg(&priv->i2c->dev,
3360 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3361 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3362 /* DiDEqC enable */
3363 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3364 /* cmd1 length & data */
3365 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3366 memset(data, 0, sizeof(data));
3367 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3368 data[i] = cmd->msg[i];
3369 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3370 /* repeat count for cmd1 */
3371 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3372 /* repeat count for cmd2: always 0 */
3373 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3374 /* start transmit */
3375 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3376 /* wait for 1 sec timeout */
3377 for (i = 0; i < 50; i++) {
3378 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3379 if (!data[0]) {
3380 dev_dbg(&priv->i2c->dev,
3381 "%s(): DiSEqC cmd has been sent\n", __func__);
3382 return 0;
3383 }
3384 msleep(20);
3385 }
3386 dev_dbg(&priv->i2c->dev,
3387 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3388 return -ETIMEDOUT;
3389}
3390
3391static void cxd2841er_release(struct dvb_frontend *fe)
3392{
3393 struct cxd2841er_priv *priv = fe->demodulator_priv;
3394
3395 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3396 kfree(priv);
3397}
3398
3399static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3400{
3401 struct cxd2841er_priv *priv = fe->demodulator_priv;
3402
3403 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3404 cxd2841er_set_reg_bits(
3405 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3406 return 0;
3407}
3408
3409static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3410{
3411 struct cxd2841er_priv *priv = fe->demodulator_priv;
3412
3413 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3414 return DVBFE_ALGO_HW;
3415}
3416
d0e20e13
MCC		 3417static void cxd2841er_init_stats(struct dvb_frontend *fe)
3418{
3419 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3420
3421 p->strength.len = 1;
3422 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3423 p->cnr.len = 1;
3424 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3425 p->block_error.len = 1;
3426 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3427 p->post_bit_error.len = 1;
3428 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3429}
3430
3431
a6dc60ff
KS		 3432static int cxd2841er_init_s(struct dvb_frontend *fe)
3433{
3434 struct cxd2841er_priv *priv = fe->demodulator_priv;
3435
30ae3307
AO		 3436 /* sanity. force demod to SHUTDOWN state */
3437 if (priv->state == STATE_SLEEP_S) {
3438 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3439 __func__);
3440 cxd2841er_sleep_s_to_shutdown(priv);
3441 } else if (priv->state == STATE_ACTIVE_S) {
3442 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3443 __func__);
3444 cxd2841er_active_s_to_sleep_s(priv);
3445 cxd2841er_sleep_s_to_shutdown(priv);
3446 }
3447
a6dc60ff
KS		 3448 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3449 cxd2841er_shutdown_to_sleep_s(priv);
3450 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3451 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3452 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
d0e20e13
MCC		 3453
3454 cxd2841er_init_stats(fe);
3455
a6dc60ff
KS		 3456 return 0;
3457}
3458
3459static int cxd2841er_init_tc(struct dvb_frontend *fe)
3460{
3461 struct cxd2841er_priv *priv = fe->demodulator_priv;
3f3b48a0 3462 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
a6dc60ff 3463
3f3b48a0
AO		 3464 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3465 __func__, p->bandwidth_hz);
a6dc60ff
KS		 3466 cxd2841er_shutdown_to_sleep_tc(priv);
3467 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3468 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3469 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3470 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3471 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3472 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3473 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3474 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
d0e20e13
MCC		 3475
3476 cxd2841er_init_stats(fe);
3477
a6dc60ff
KS		 3478 return 0;
3479}
3480
3481static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3f3b48a0 3482static struct dvb_frontend_ops cxd2841er_t_c_ops;
a6dc60ff
KS		 3483
3484static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3485 struct i2c_adapter *i2c,
3486 u8 system)
3487{
3488 u8 chip_id = 0;
3489 const char *type;
3f3b48a0 3490 const char *name;
a6dc60ff
KS		 3491 struct cxd2841er_priv *priv = NULL;
3492
3493 /* allocate memory for the internal state */
3494 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3495 if (!priv)
3496 return NULL;
3497 priv->i2c = i2c;
3498 priv->config = cfg;
3499 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3500 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
83808c23 3501 priv->xtal = cfg->xtal;
a6dc60ff 3502 priv->frontend.demodulator_priv = priv;
a6dc60ff
KS		 3503 dev_info(&priv->i2c->dev,
3504 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3505 __func__, priv->i2c,
3506 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3507 chip_id = cxd2841er_chip_id(priv);
3f3b48a0
AO		 3508 switch (chip_id) {
3509 case CXD2841ER_CHIP_ID:
3510 snprintf(cxd2841er_t_c_ops.info.name, 128,
3511 "Sony CXD2841ER DVB-T/T2/C demodulator");
3512 name = "CXD2841ER";
3513 break;
3514 case CXD2854ER_CHIP_ID:
3515 snprintf(cxd2841er_t_c_ops.info.name, 128,
3516 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3517 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3518 name = "CXD2854ER";
3519 break;
3520 default:
a6dc60ff 3521 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3f3b48a0 3522 __func__, chip_id);
a6dc60ff
KS		 3523 priv->frontend.demodulator_priv = NULL;
3524 kfree(priv);
3525 return NULL;
3526 }
3f3b48a0
AO		 3527
3528 /* create dvb_frontend */
3529 if (system == SYS_DVBS) {
3530 memcpy(&priv->frontend.ops,
3531 &cxd2841er_dvbs_s2_ops,
3532 sizeof(struct dvb_frontend_ops));
3533 type = "S/S2";
3534 } else {
3535 memcpy(&priv->frontend.ops,
3536 &cxd2841er_t_c_ops,
3537 sizeof(struct dvb_frontend_ops));
3538 type = "T/T2/C/ISDB-T";
3539 }
3540
3541 dev_info(&priv->i2c->dev,
3542 "%s(): attaching %s DVB-%s frontend\n",
3543 __func__, name, type);
a6dc60ff
KS		 3544 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3545 __func__, chip_id);
3546 return &priv->frontend;
3547}
3548
3549struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3550 struct i2c_adapter *i2c)
3551{
3552 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3553}
3554EXPORT_SYMBOL(cxd2841er_attach_s);
3555
3f3b48a0 3556struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
a6dc60ff
KS		 3557 struct i2c_adapter *i2c)
3558{
3f3b48a0 3559 return cxd2841er_attach(cfg, i2c, 0);
a6dc60ff 3560}
3f3b48a0 3561EXPORT_SYMBOL(cxd2841er_attach_t_c);
a6dc60ff
KS		 3562
3563static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3564 .delsys = { SYS_DVBS, SYS_DVBS2 },
3565 .info = {
3566 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3567 .frequency_min = 500000,
3568 .frequency_max = 2500000,
3569 .frequency_stepsize = 0,
3570 .symbol_rate_min = 1000000,
3571 .symbol_rate_max = 45000000,
3572 .symbol_rate_tolerance = 500,
3573 .caps = FE_CAN_INVERSION_AUTO |
3574 FE_CAN_FEC_AUTO |
3575 FE_CAN_QPSK,
3576 },
3577 .init = cxd2841er_init_s,
3578 .sleep = cxd2841er_sleep_s,
3579 .release = cxd2841er_release,
3580 .set_frontend = cxd2841er_set_frontend_s,
3581 .get_frontend = cxd2841er_get_frontend,
3582 .read_status = cxd2841er_read_status_s,
3583 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3584 .get_frontend_algo = cxd2841er_get_algo,
3585 .set_tone = cxd2841er_set_tone,
3586 .diseqc_send_burst = cxd2841er_send_burst,
3587 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3588 .tune = cxd2841er_tune_s
3589};
3590
3f3b48a0
AO		 3591static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3592 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
83808c23 3593 .info = {
3f3b48a0 3594 .name = "", /* will set in attach function */
83808c23
AO		 3595 .caps = FE_CAN_FEC_1_2 |
3596 FE_CAN_FEC_2_3 |
3597 FE_CAN_FEC_3_4 |
3598 FE_CAN_FEC_5_6 |
3599 FE_CAN_FEC_7_8 |
3600 FE_CAN_FEC_AUTO |
3601 FE_CAN_QPSK |
3602 FE_CAN_QAM_16 |
3603 FE_CAN_QAM_32 |
3604 FE_CAN_QAM_64 |
3605 FE_CAN_QAM_128 |
3606 FE_CAN_QAM_256 |
3607 FE_CAN_QAM_AUTO |
3608 FE_CAN_TRANSMISSION_MODE_AUTO |
3609 FE_CAN_GUARD_INTERVAL_AUTO |
3610 FE_CAN_HIERARCHY_AUTO |
3611 FE_CAN_MUTE_TS |
3612 FE_CAN_2G_MODULATION,
3613 .frequency_min = 42000000,
3614 .frequency_max = 1002000000
3615 },
3616 .init = cxd2841er_init_tc,
3617 .sleep = cxd2841er_sleep_tc,
3618 .release = cxd2841er_release,
3619 .set_frontend = cxd2841er_set_frontend_tc,
3620 .get_frontend = cxd2841er_get_frontend,
3621 .read_status = cxd2841er_read_status_tc,
3622 .tune = cxd2841er_tune_tc,
3623 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3624 .get_frontend_algo = cxd2841er_get_algo
3625};
3626
83808c23
AO		 3627MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3628MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
a6dc60ff 3629MODULE_LICENSE("GPL");
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