]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B | |
3 | * DiBcom (http://www.dibcom.fr/) | |
4 | * | |
99e44da7 | 5 | * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de) |
1da177e4 LT |
6 | * |
7 | * based on GPL code from DibCom, which has | |
8 | * | |
99e44da7 | 9 | * Copyright (C) 2004 Amaury Demol for DiBcom |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation, version 2. | |
14 | * | |
15 | * Acknowledgements | |
16 | * | |
99e44da7 | 17 | * Amaury Demol from DiBcom for providing specs and driver |
1da177e4 LT |
18 | * sources, on which this driver (and the dvb-dibusb) are based. |
19 | * | |
395cf969 | 20 | * see Documentation/dvb/README.dvb-usb for more information |
1da177e4 LT |
21 | * |
22 | */ | |
23 | ||
1da177e4 | 24 | #include <linux/kernel.h> |
1da177e4 | 25 | #include <linux/module.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/delay.h> | |
4e57b681 TS |
28 | #include <linux/string.h> |
29 | #include <linux/slab.h> | |
1da177e4 | 30 | |
74340b0a PB |
31 | #include "dvb_frontend.h" |
32 | ||
1da177e4 | 33 | #include "dib3000.h" |
74340b0a | 34 | #include "dib3000mb_priv.h" |
1da177e4 LT |
35 | |
36 | /* Version information */ | |
37 | #define DRIVER_VERSION "0.1" | |
38 | #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator" | |
99e44da7 | 39 | #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@posteo.de" |
1da177e4 | 40 | |
1da177e4 LT |
41 | static int debug; |
42 | module_param(debug, int, 0644); | |
43 | MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able))."); | |
9059cd44 | 44 | |
1da177e4 | 45 | #define deb_info(args...) dprintk(0x01,args) |
74340b0a PB |
46 | #define deb_i2c(args...) dprintk(0x02,args) |
47 | #define deb_srch(args...) dprintk(0x04,args) | |
48 | #define deb_info(args...) dprintk(0x01,args) | |
1da177e4 LT |
49 | #define deb_xfer(args...) dprintk(0x02,args) |
50 | #define deb_setf(args...) dprintk(0x04,args) | |
51 | #define deb_getf(args...) dprintk(0x08,args) | |
52 | ||
74340b0a PB |
53 | static int dib3000_read_reg(struct dib3000_state *state, u16 reg) |
54 | { | |
55 | u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff }; | |
56 | u8 rb[2]; | |
57 | struct i2c_msg msg[] = { | |
58 | { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 }, | |
59 | { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 }, | |
60 | }; | |
61 | ||
62 | if (i2c_transfer(state->i2c, msg, 2) != 2) | |
63 | deb_i2c("i2c read error\n"); | |
64 | ||
65 | deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg, | |
66 | (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]); | |
67 | ||
68 | return (rb[0] << 8) | rb[1]; | |
69 | } | |
70 | ||
71 | static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val) | |
72 | { | |
73 | u8 b[] = { | |
74 | (reg >> 8) & 0xff, reg & 0xff, | |
75 | (val >> 8) & 0xff, val & 0xff, | |
76 | }; | |
77 | struct i2c_msg msg[] = { | |
78 | { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 } | |
79 | }; | |
80 | deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val); | |
81 | ||
82 | return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0; | |
83 | } | |
84 | ||
85 | static int dib3000_search_status(u16 irq,u16 lock) | |
86 | { | |
87 | if (irq & 0x02) { | |
88 | if (lock & 0x01) { | |
89 | deb_srch("auto search succeeded\n"); | |
90 | return 1; // auto search succeeded | |
91 | } else { | |
92 | deb_srch("auto search not successful\n"); | |
93 | return 0; // auto search failed | |
94 | } | |
95 | } else if (irq & 0x01) { | |
96 | deb_srch("auto search failed\n"); | |
97 | return 0; // auto search failed | |
98 | } | |
99 | return -1; // try again | |
100 | } | |
101 | ||
102 | /* for auto search */ | |
103 | static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */ | |
104 | { /* fft */ | |
105 | { /* gua */ | |
106 | { 0, 1 }, /* 0 0 { 0,1 } */ | |
107 | { 3, 9 }, /* 0 1 { 0,1 } */ | |
108 | }, | |
109 | { | |
110 | { 2, 5 }, /* 1 0 { 0,1 } */ | |
111 | { 6, 11 }, /* 1 1 { 0,1 } */ | |
112 | } | |
113 | }; | |
114 | ||
7e3e68bc MCC |
115 | static int dib3000mb_get_frontend(struct dvb_frontend* fe, |
116 | struct dtv_frontend_properties *c); | |
1da177e4 | 117 | |
fe084929 | 118 | static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner) |
1da177e4 | 119 | { |
b8742700 | 120 | struct dib3000_state* state = fe->demodulator_priv; |
fe084929 | 121 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
0df289a2 | 122 | enum fe_code_rate fe_cr = FEC_NONE; |
1da177e4 LT |
123 | int search_state, seq; |
124 | ||
dea74869 | 125 | if (tuner && fe->ops.tuner_ops.set_params) { |
14d24d14 | 126 | fe->ops.tuner_ops.set_params(fe); |
dea74869 | 127 | if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); |
1da177e4 LT |
128 | |
129 | deb_setf("bandwidth: "); | |
fe084929 MCC |
130 | switch (c->bandwidth_hz) { |
131 | case 8000000: | |
1da177e4 LT |
132 | deb_setf("8 MHz\n"); |
133 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); | |
134 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); | |
135 | break; | |
fe084929 | 136 | case 7000000: |
1da177e4 LT |
137 | deb_setf("7 MHz\n"); |
138 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]); | |
139 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz); | |
140 | break; | |
fe084929 | 141 | case 6000000: |
1da177e4 LT |
142 | deb_setf("6 MHz\n"); |
143 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]); | |
144 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz); | |
145 | break; | |
fe084929 | 146 | case 0: |
1da177e4 LT |
147 | return -EOPNOTSUPP; |
148 | default: | |
af901ca1 | 149 | err("unknown bandwidth value."); |
1da177e4 LT |
150 | return -EINVAL; |
151 | } | |
152 | } | |
153 | wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); | |
154 | ||
155 | deb_setf("transmission mode: "); | |
fe084929 | 156 | switch (c->transmission_mode) { |
1da177e4 LT |
157 | case TRANSMISSION_MODE_2K: |
158 | deb_setf("2k\n"); | |
159 | wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K); | |
160 | break; | |
161 | case TRANSMISSION_MODE_8K: | |
162 | deb_setf("8k\n"); | |
163 | wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K); | |
164 | break; | |
165 | case TRANSMISSION_MODE_AUTO: | |
166 | deb_setf("auto\n"); | |
167 | break; | |
168 | default: | |
169 | return -EINVAL; | |
170 | } | |
171 | ||
172 | deb_setf("guard: "); | |
fe084929 | 173 | switch (c->guard_interval) { |
1da177e4 LT |
174 | case GUARD_INTERVAL_1_32: |
175 | deb_setf("1_32\n"); | |
176 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32); | |
177 | break; | |
178 | case GUARD_INTERVAL_1_16: | |
179 | deb_setf("1_16\n"); | |
180 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16); | |
181 | break; | |
182 | case GUARD_INTERVAL_1_8: | |
183 | deb_setf("1_8\n"); | |
184 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8); | |
185 | break; | |
186 | case GUARD_INTERVAL_1_4: | |
187 | deb_setf("1_4\n"); | |
188 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4); | |
189 | break; | |
190 | case GUARD_INTERVAL_AUTO: | |
191 | deb_setf("auto\n"); | |
192 | break; | |
193 | default: | |
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | deb_setf("inversion: "); | |
fe084929 | 198 | switch (c->inversion) { |
1da177e4 LT |
199 | case INVERSION_OFF: |
200 | deb_setf("off\n"); | |
201 | wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF); | |
202 | break; | |
203 | case INVERSION_AUTO: | |
204 | deb_setf("auto "); | |
205 | break; | |
206 | case INVERSION_ON: | |
207 | deb_setf("on\n"); | |
208 | wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON); | |
209 | break; | |
210 | default: | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
fe084929 MCC |
214 | deb_setf("modulation: "); |
215 | switch (c->modulation) { | |
1da177e4 LT |
216 | case QPSK: |
217 | deb_setf("qpsk\n"); | |
218 | wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK); | |
219 | break; | |
220 | case QAM_16: | |
221 | deb_setf("qam16\n"); | |
222 | wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM); | |
223 | break; | |
224 | case QAM_64: | |
225 | deb_setf("qam64\n"); | |
226 | wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM); | |
227 | break; | |
228 | case QAM_AUTO: | |
229 | break; | |
230 | default: | |
231 | return -EINVAL; | |
232 | } | |
1b3c3714 | 233 | deb_setf("hierarchy: "); |
fe084929 | 234 | switch (c->hierarchy) { |
1da177e4 LT |
235 | case HIERARCHY_NONE: |
236 | deb_setf("none "); | |
237 | /* fall through */ | |
238 | case HIERARCHY_1: | |
239 | deb_setf("alpha=1\n"); | |
240 | wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1); | |
241 | break; | |
242 | case HIERARCHY_2: | |
243 | deb_setf("alpha=2\n"); | |
244 | wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2); | |
245 | break; | |
246 | case HIERARCHY_4: | |
247 | deb_setf("alpha=4\n"); | |
248 | wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4); | |
249 | break; | |
250 | case HIERARCHY_AUTO: | |
251 | deb_setf("alpha=auto\n"); | |
252 | break; | |
253 | default: | |
254 | return -EINVAL; | |
255 | } | |
256 | ||
257 | deb_setf("hierarchy: "); | |
fe084929 | 258 | if (c->hierarchy == HIERARCHY_NONE) { |
1da177e4 LT |
259 | deb_setf("none\n"); |
260 | wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF); | |
261 | wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP); | |
fe084929 MCC |
262 | fe_cr = c->code_rate_HP; |
263 | } else if (c->hierarchy != HIERARCHY_AUTO) { | |
1da177e4 LT |
264 | deb_setf("on\n"); |
265 | wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON); | |
266 | wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP); | |
fe084929 | 267 | fe_cr = c->code_rate_LP; |
1da177e4 LT |
268 | } |
269 | deb_setf("fec: "); | |
270 | switch (fe_cr) { | |
271 | case FEC_1_2: | |
272 | deb_setf("1_2\n"); | |
273 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2); | |
274 | break; | |
275 | case FEC_2_3: | |
276 | deb_setf("2_3\n"); | |
277 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3); | |
278 | break; | |
279 | case FEC_3_4: | |
280 | deb_setf("3_4\n"); | |
281 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4); | |
282 | break; | |
283 | case FEC_5_6: | |
284 | deb_setf("5_6\n"); | |
285 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6); | |
286 | break; | |
287 | case FEC_7_8: | |
288 | deb_setf("7_8\n"); | |
289 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8); | |
290 | break; | |
291 | case FEC_NONE: | |
292 | deb_setf("none "); | |
293 | break; | |
294 | case FEC_AUTO: | |
295 | deb_setf("auto\n"); | |
296 | break; | |
297 | default: | |
298 | return -EINVAL; | |
299 | } | |
300 | ||
301 | seq = dib3000_seq | |
fe084929 MCC |
302 | [c->transmission_mode == TRANSMISSION_MODE_AUTO] |
303 | [c->guard_interval == GUARD_INTERVAL_AUTO] | |
304 | [c->inversion == INVERSION_AUTO]; | |
1da177e4 LT |
305 | |
306 | deb_setf("seq? %d\n", seq); | |
307 | ||
308 | wr(DIB3000MB_REG_SEQ, seq); | |
309 | ||
310 | wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE); | |
311 | ||
fe084929 MCC |
312 | if (c->transmission_mode == TRANSMISSION_MODE_2K) { |
313 | if (c->guard_interval == GUARD_INTERVAL_1_8) { | |
1da177e4 LT |
314 | wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8); |
315 | } else { | |
316 | wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT); | |
317 | } | |
318 | ||
319 | wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K); | |
320 | } else { | |
321 | wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT); | |
322 | } | |
323 | ||
324 | wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF); | |
325 | wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); | |
326 | wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF); | |
327 | ||
328 | wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high); | |
329 | ||
330 | wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE); | |
331 | ||
332 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL); | |
333 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); | |
334 | ||
335 | /* wait for AGC lock */ | |
336 | msleep(70); | |
337 | ||
338 | wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); | |
339 | ||
340 | /* something has to be auto searched */ | |
fe084929 MCC |
341 | if (c->modulation == QAM_AUTO || |
342 | c->hierarchy == HIERARCHY_AUTO || | |
1da177e4 | 343 | fe_cr == FEC_AUTO || |
fe084929 | 344 | c->inversion == INVERSION_AUTO) { |
1da177e4 LT |
345 | int as_count=0; |
346 | ||
347 | deb_setf("autosearch enabled.\n"); | |
348 | ||
349 | wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); | |
350 | ||
351 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH); | |
352 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); | |
353 | ||
354 | while ((search_state = | |
355 | dib3000_search_status( | |
356 | rd(DIB3000MB_REG_AS_IRQ_PENDING), | |
357 | rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100) | |
358 | msleep(1); | |
359 | ||
360 | deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count); | |
361 | ||
362 | if (search_state == 1) { | |
7e3e68bc | 363 | if (dib3000mb_get_frontend(fe, c) == 0) { |
1da177e4 | 364 | deb_setf("reading tuning data from frontend succeeded.\n"); |
fe084929 | 365 | return dib3000mb_set_frontend(fe, 0); |
1da177e4 LT |
366 | } |
367 | } | |
368 | ||
369 | } else { | |
370 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL); | |
371 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode) | |
378 | { | |
b8742700 | 379 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
380 | |
381 | deb_info("dib3000mb is getting up.\n"); | |
382 | wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP); | |
383 | ||
384 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC); | |
385 | ||
386 | wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE); | |
387 | wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST); | |
388 | ||
389 | wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT); | |
390 | ||
391 | wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON); | |
392 | ||
393 | wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB); | |
394 | wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB); | |
395 | ||
396 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); | |
397 | ||
398 | wr_foreach(dib3000mb_reg_impulse_noise, | |
399 | dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]); | |
400 | ||
401 | wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain); | |
402 | ||
403 | wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT); | |
404 | ||
405 | wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase); | |
406 | ||
407 | wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration); | |
408 | ||
409 | wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); | |
410 | ||
411 | wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT); | |
412 | wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); | |
413 | wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT); | |
414 | wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]); | |
415 | ||
416 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); | |
417 | ||
418 | wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68); | |
419 | wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69); | |
420 | wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71); | |
421 | wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77); | |
422 | wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78); | |
423 | wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); | |
424 | wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92); | |
425 | wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96); | |
426 | wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97); | |
427 | wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106); | |
428 | wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107); | |
429 | wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108); | |
430 | wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122); | |
431 | wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); | |
432 | wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT); | |
433 | ||
434 | wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs); | |
435 | ||
436 | wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON); | |
437 | wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB); | |
438 | wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB); | |
439 | ||
440 | wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE); | |
441 | ||
442 | wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142); | |
443 | wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188); | |
444 | wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE); | |
445 | wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); | |
446 | wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146); | |
447 | wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147); | |
448 | ||
449 | wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF); | |
450 | ||
1da177e4 LT |
451 | return 0; |
452 | } | |
453 | ||
7e3e68bc MCC |
454 | static int dib3000mb_get_frontend(struct dvb_frontend* fe, |
455 | struct dtv_frontend_properties *c) | |
1da177e4 | 456 | { |
b8742700 | 457 | struct dib3000_state* state = fe->demodulator_priv; |
0df289a2 | 458 | enum fe_code_rate *cr; |
1da177e4 LT |
459 | u16 tps_val; |
460 | int inv_test1,inv_test2; | |
461 | u32 dds_val, threshold = 0x800000; | |
462 | ||
463 | if (!rd(DIB3000MB_REG_TPS_LOCK)) | |
464 | return 0; | |
465 | ||
466 | dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB); | |
467 | deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB)); | |
468 | if (dds_val < threshold) | |
469 | inv_test1 = 0; | |
470 | else if (dds_val == threshold) | |
471 | inv_test1 = 1; | |
472 | else | |
473 | inv_test1 = 2; | |
474 | ||
475 | dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB); | |
476 | deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB)); | |
477 | if (dds_val < threshold) | |
478 | inv_test2 = 0; | |
479 | else if (dds_val == threshold) | |
480 | inv_test2 = 1; | |
481 | else | |
482 | inv_test2 = 2; | |
483 | ||
fe084929 | 484 | c->inversion = |
1da177e4 LT |
485 | ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) || |
486 | ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ? | |
487 | INVERSION_ON : INVERSION_OFF; | |
488 | ||
fe084929 | 489 | deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion); |
1da177e4 LT |
490 | |
491 | switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) { | |
492 | case DIB3000_CONSTELLATION_QPSK: | |
493 | deb_getf("QPSK "); | |
fe084929 | 494 | c->modulation = QPSK; |
1da177e4 LT |
495 | break; |
496 | case DIB3000_CONSTELLATION_16QAM: | |
497 | deb_getf("QAM16 "); | |
fe084929 | 498 | c->modulation = QAM_16; |
1da177e4 LT |
499 | break; |
500 | case DIB3000_CONSTELLATION_64QAM: | |
501 | deb_getf("QAM64 "); | |
fe084929 | 502 | c->modulation = QAM_64; |
1da177e4 LT |
503 | break; |
504 | default: | |
505 | err("Unexpected constellation returned by TPS (%d)", tps_val); | |
506 | break; | |
507 | } | |
508 | deb_getf("TPS: %d\n", tps_val); | |
509 | ||
510 | if (rd(DIB3000MB_REG_TPS_HRCH)) { | |
511 | deb_getf("HRCH ON\n"); | |
fe084929 MCC |
512 | cr = &c->code_rate_LP; |
513 | c->code_rate_HP = FEC_NONE; | |
1da177e4 LT |
514 | switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) { |
515 | case DIB3000_ALPHA_0: | |
516 | deb_getf("HIERARCHY_NONE "); | |
fe084929 | 517 | c->hierarchy = HIERARCHY_NONE; |
1da177e4 LT |
518 | break; |
519 | case DIB3000_ALPHA_1: | |
520 | deb_getf("HIERARCHY_1 "); | |
fe084929 | 521 | c->hierarchy = HIERARCHY_1; |
1da177e4 LT |
522 | break; |
523 | case DIB3000_ALPHA_2: | |
524 | deb_getf("HIERARCHY_2 "); | |
fe084929 | 525 | c->hierarchy = HIERARCHY_2; |
1da177e4 LT |
526 | break; |
527 | case DIB3000_ALPHA_4: | |
528 | deb_getf("HIERARCHY_4 "); | |
fe084929 | 529 | c->hierarchy = HIERARCHY_4; |
1da177e4 LT |
530 | break; |
531 | default: | |
532 | err("Unexpected ALPHA value returned by TPS (%d)", tps_val); | |
533 | break; | |
534 | } | |
535 | deb_getf("TPS: %d\n", tps_val); | |
536 | ||
537 | tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP); | |
538 | } else { | |
539 | deb_getf("HRCH OFF\n"); | |
fe084929 MCC |
540 | cr = &c->code_rate_HP; |
541 | c->code_rate_LP = FEC_NONE; | |
542 | c->hierarchy = HIERARCHY_NONE; | |
1da177e4 LT |
543 | |
544 | tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP); | |
545 | } | |
546 | ||
547 | switch (tps_val) { | |
548 | case DIB3000_FEC_1_2: | |
549 | deb_getf("FEC_1_2 "); | |
550 | *cr = FEC_1_2; | |
551 | break; | |
552 | case DIB3000_FEC_2_3: | |
553 | deb_getf("FEC_2_3 "); | |
554 | *cr = FEC_2_3; | |
555 | break; | |
556 | case DIB3000_FEC_3_4: | |
557 | deb_getf("FEC_3_4 "); | |
558 | *cr = FEC_3_4; | |
559 | break; | |
560 | case DIB3000_FEC_5_6: | |
561 | deb_getf("FEC_5_6 "); | |
562 | *cr = FEC_4_5; | |
563 | break; | |
564 | case DIB3000_FEC_7_8: | |
565 | deb_getf("FEC_7_8 "); | |
566 | *cr = FEC_7_8; | |
567 | break; | |
568 | default: | |
569 | err("Unexpected FEC returned by TPS (%d)", tps_val); | |
570 | break; | |
571 | } | |
572 | deb_getf("TPS: %d\n",tps_val); | |
573 | ||
574 | switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) { | |
575 | case DIB3000_GUARD_TIME_1_32: | |
576 | deb_getf("GUARD_INTERVAL_1_32 "); | |
fe084929 | 577 | c->guard_interval = GUARD_INTERVAL_1_32; |
1da177e4 LT |
578 | break; |
579 | case DIB3000_GUARD_TIME_1_16: | |
580 | deb_getf("GUARD_INTERVAL_1_16 "); | |
fe084929 | 581 | c->guard_interval = GUARD_INTERVAL_1_16; |
1da177e4 LT |
582 | break; |
583 | case DIB3000_GUARD_TIME_1_8: | |
584 | deb_getf("GUARD_INTERVAL_1_8 "); | |
fe084929 | 585 | c->guard_interval = GUARD_INTERVAL_1_8; |
1da177e4 LT |
586 | break; |
587 | case DIB3000_GUARD_TIME_1_4: | |
588 | deb_getf("GUARD_INTERVAL_1_4 "); | |
fe084929 | 589 | c->guard_interval = GUARD_INTERVAL_1_4; |
1da177e4 LT |
590 | break; |
591 | default: | |
592 | err("Unexpected Guard Time returned by TPS (%d)", tps_val); | |
593 | break; | |
594 | } | |
595 | deb_getf("TPS: %d\n", tps_val); | |
596 | ||
597 | switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) { | |
598 | case DIB3000_TRANSMISSION_MODE_2K: | |
599 | deb_getf("TRANSMISSION_MODE_2K "); | |
fe084929 | 600 | c->transmission_mode = TRANSMISSION_MODE_2K; |
1da177e4 LT |
601 | break; |
602 | case DIB3000_TRANSMISSION_MODE_8K: | |
603 | deb_getf("TRANSMISSION_MODE_8K "); | |
fe084929 | 604 | c->transmission_mode = TRANSMISSION_MODE_8K; |
1da177e4 LT |
605 | break; |
606 | default: | |
607 | err("unexpected transmission mode return by TPS (%d)", tps_val); | |
608 | break; | |
609 | } | |
610 | deb_getf("TPS: %d\n", tps_val); | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
0df289a2 MCC |
615 | static int dib3000mb_read_status(struct dvb_frontend *fe, |
616 | enum fe_status *stat) | |
1da177e4 | 617 | { |
b8742700 | 618 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
619 | |
620 | *stat = 0; | |
621 | ||
622 | if (rd(DIB3000MB_REG_AGC_LOCK)) | |
623 | *stat |= FE_HAS_SIGNAL; | |
624 | if (rd(DIB3000MB_REG_CARRIER_LOCK)) | |
625 | *stat |= FE_HAS_CARRIER; | |
626 | if (rd(DIB3000MB_REG_VIT_LCK)) | |
627 | *stat |= FE_HAS_VITERBI; | |
628 | if (rd(DIB3000MB_REG_TS_SYNC_LOCK)) | |
629 | *stat |= (FE_HAS_SYNC | FE_HAS_LOCK); | |
630 | ||
631 | deb_getf("actual status is %2x\n",*stat); | |
632 | ||
633 | deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n", | |
634 | rd(DIB3000MB_REG_TPS_LOCK), | |
635 | rd(DIB3000MB_REG_TPS_QAM), | |
636 | rd(DIB3000MB_REG_TPS_HRCH), | |
637 | rd(DIB3000MB_REG_TPS_VIT_ALPHA), | |
638 | rd(DIB3000MB_REG_TPS_CODE_RATE_HP), | |
639 | rd(DIB3000MB_REG_TPS_CODE_RATE_LP), | |
640 | rd(DIB3000MB_REG_TPS_GUARD_TIME), | |
641 | rd(DIB3000MB_REG_TPS_FFT), | |
642 | rd(DIB3000MB_REG_TPS_CELL_ID)); | |
643 | ||
644 | //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; | |
645 | return 0; | |
646 | } | |
647 | ||
648 | static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber) | |
649 | { | |
b8742700 | 650 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
651 | |
652 | *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB)); | |
653 | return 0; | |
654 | } | |
655 | ||
656 | /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */ | |
657 | static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength) | |
658 | { | |
b8742700 | 659 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
660 | |
661 | *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170; | |
662 | return 0; | |
663 | } | |
664 | ||
665 | static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr) | |
666 | { | |
b8742700 | 667 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
668 | short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER); |
669 | int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) | | |
670 | rd(DIB3000MB_REG_NOISE_POWER_LSB); | |
671 | *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1); | |
672 | return 0; | |
673 | } | |
674 | ||
675 | static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc) | |
676 | { | |
b8742700 | 677 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 | 678 | |
776338e1 | 679 | *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE); |
1da177e4 LT |
680 | return 0; |
681 | } | |
682 | ||
683 | static int dib3000mb_sleep(struct dvb_frontend* fe) | |
684 | { | |
b8742700 | 685 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
686 | deb_info("dib3000mb is going to bed.\n"); |
687 | wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN); | |
688 | return 0; | |
689 | } | |
690 | ||
691 | static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune) | |
692 | { | |
693 | tune->min_delay_ms = 800; | |
1da177e4 LT |
694 | return 0; |
695 | } | |
696 | ||
697 | static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe) | |
698 | { | |
699 | return dib3000mb_fe_init(fe, 0); | |
700 | } | |
701 | ||
fe084929 | 702 | static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe) |
1da177e4 | 703 | { |
fe084929 | 704 | return dib3000mb_set_frontend(fe, 1); |
1da177e4 LT |
705 | } |
706 | ||
707 | static void dib3000mb_release(struct dvb_frontend* fe) | |
708 | { | |
b8742700 | 709 | struct dib3000_state *state = fe->demodulator_priv; |
1da177e4 LT |
710 | kfree(state); |
711 | } | |
712 | ||
713 | /* pid filter and transfer stuff */ | |
714 | static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff) | |
715 | { | |
716 | struct dib3000_state *state = fe->demodulator_priv; | |
717 | pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0); | |
718 | wr(index+DIB3000MB_REG_FIRST_PID,pid); | |
719 | return 0; | |
720 | } | |
721 | ||
722 | static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff) | |
723 | { | |
b8742700 | 724 | struct dib3000_state *state = fe->demodulator_priv; |
1da177e4 LT |
725 | |
726 | deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling"); | |
727 | if (onoff) { | |
728 | wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE); | |
729 | } else { | |
730 | wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); | |
731 | } | |
732 | return 0; | |
733 | } | |
734 | ||
735 | static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff) | |
736 | { | |
737 | struct dib3000_state *state = fe->demodulator_priv; | |
738 | deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling"); | |
739 | wr(DIB3000MB_REG_PID_PARSE,onoff); | |
740 | return 0; | |
741 | } | |
742 | ||
743 | static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr) | |
744 | { | |
b8742700 | 745 | struct dib3000_state *state = fe->demodulator_priv; |
1da177e4 LT |
746 | if (onoff) { |
747 | wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr)); | |
748 | } else { | |
749 | wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr)); | |
750 | } | |
751 | return 0; | |
752 | } | |
753 | ||
754 | static struct dvb_frontend_ops dib3000mb_ops; | |
755 | ||
756 | struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config, | |
757 | struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops) | |
758 | { | |
759 | struct dib3000_state* state = NULL; | |
760 | ||
761 | /* allocate memory for the internal state */ | |
7408187d | 762 | state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL); |
1da177e4 LT |
763 | if (state == NULL) |
764 | goto error; | |
1da177e4 LT |
765 | |
766 | /* setup the state */ | |
767 | state->i2c = i2c; | |
768 | memcpy(&state->config,config,sizeof(struct dib3000_config)); | |
1da177e4 LT |
769 | |
770 | /* check for the correct demod */ | |
771 | if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM) | |
772 | goto error; | |
773 | ||
774 | if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID) | |
775 | goto error; | |
776 | ||
777 | /* create dvb_frontend */ | |
dea74869 | 778 | memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops)); |
1da177e4 LT |
779 | state->frontend.demodulator_priv = state; |
780 | ||
781 | /* set the xfer operations */ | |
782 | xfer_ops->pid_parse = dib3000mb_pid_parse; | |
783 | xfer_ops->fifo_ctrl = dib3000mb_fifo_control; | |
784 | xfer_ops->pid_ctrl = dib3000mb_pid_control; | |
785 | xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl; | |
786 | ||
787 | return &state->frontend; | |
788 | ||
789 | error: | |
790 | kfree(state); | |
791 | return NULL; | |
792 | } | |
793 | ||
794 | static struct dvb_frontend_ops dib3000mb_ops = { | |
fe084929 | 795 | .delsys = { SYS_DVBT }, |
1da177e4 LT |
796 | .info = { |
797 | .name = "DiBcom 3000M-B DVB-T", | |
1da177e4 LT |
798 | .frequency_min = 44250000, |
799 | .frequency_max = 867250000, | |
800 | .frequency_stepsize = 62500, | |
801 | .caps = FE_CAN_INVERSION_AUTO | | |
802 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
803 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
804 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | | |
805 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
806 | FE_CAN_GUARD_INTERVAL_AUTO | | |
807 | FE_CAN_RECOVER | | |
808 | FE_CAN_HIERARCHY_AUTO, | |
809 | }, | |
810 | ||
811 | .release = dib3000mb_release, | |
812 | ||
813 | .init = dib3000mb_fe_init_nonmobile, | |
814 | .sleep = dib3000mb_sleep, | |
815 | ||
fe084929 MCC |
816 | .set_frontend = dib3000mb_set_frontend_and_tuner, |
817 | .get_frontend = dib3000mb_get_frontend, | |
1da177e4 LT |
818 | .get_tune_settings = dib3000mb_fe_get_tune_settings, |
819 | ||
820 | .read_status = dib3000mb_read_status, | |
821 | .read_ber = dib3000mb_read_ber, | |
822 | .read_signal_strength = dib3000mb_read_signal_strength, | |
823 | .read_snr = dib3000mb_read_snr, | |
824 | .read_ucblocks = dib3000mb_read_unc_blocks, | |
825 | }; | |
826 | ||
827 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
828 | MODULE_DESCRIPTION(DRIVER_DESC); | |
829 | MODULE_LICENSE("GPL"); | |
830 | ||
831 | EXPORT_SYMBOL(dib3000mb_attach); |