[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb-frontends / dibx000_common.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DIBX000_COMMON_H
#define DIBX000_COMMON_H

enum dibx000_i2c_interface {
	DIBX000_I2C_INTERFACE_TUNER = 0,
	DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
	DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
	DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
};

struct dibx000_i2c_master {
#define DIB3000MC 1
#define DIB7000   2
#define DIB7000P  11
#define DIB7000MC 12
#define DIB8000   13
	u16 device_rev;

	enum dibx000_i2c_interface selected_interface;

/*	struct i2c_adapter  tuner_i2c_adap; */
	struct i2c_adapter gated_tuner_i2c_adap;
	struct i2c_adapter master_i2c_adap_gpio12;
	struct i2c_adapter master_i2c_adap_gpio34;
	struct i2c_adapter master_i2c_adap_gpio67;

	struct i2c_adapter *i2c_adap;
	u8 i2c_addr;

	u16 base_reg;

	/* for the I2C transfer */
	struct i2c_msg msg[34];
	u8 i2c_write_buffer[8];
	u8 i2c_read_buffer[2];
	struct mutex i2c_buffer_lock;
};

extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
					u16 device_rev, struct i2c_adapter *i2c_adap,
					u8 i2c_addr);
extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
							*mst,
							enum dibx000_i2c_interface
							intf, int gating);
extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);

#define BAND_LBAND 0x01
#define BAND_UHF   0x02
#define BAND_VHF   0x04
#define BAND_SBAND 0x08
#define BAND_FM	   0x10
#define BAND_CBAND 0x20

#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
									(freq_kHz) <= 115000 ? BAND_FM : \
									(freq_kHz) <= 250000 ? BAND_VHF : \
									(freq_kHz) <= 863000 ? BAND_UHF : \
									(freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )

struct dibx000_agc_config {
	/* defines the capabilities of this AGC-setting - using the BAND_-defines */
	u8 band_caps;

	u16 setup;

	u16 inv_gain;
	u16 time_stabiliz;

	u8 alpha_level;
	u16 thlock;

	u8 wbd_inv;
	u16 wbd_ref;
	u8 wbd_sel;
	u8 wbd_alpha;

	u16 agc1_max;
	u16 agc1_min;
	u16 agc2_max;
	u16 agc2_min;

	u8 agc1_pt1;
	u8 agc1_pt2;
	u8 agc1_pt3;

	u8 agc1_slope1;
	u8 agc1_slope2;

	u8 agc2_pt1;
	u8 agc2_pt2;

	u8 agc2_slope1;
	u8 agc2_slope2;

	u8 alpha_mant;
	u8 alpha_exp;

	u8 beta_mant;
	u8 beta_exp;

	u8 perform_agc_softsplit;

	struct {
		u16 min;
		u16 max;
		u16 min_thres;
		u16 max_thres;
	} split;
};

struct dibx000_bandwidth_config {
	u32 internal;
	u32 sampling;

	u8 pll_prediv;
	u8 pll_ratio;
	u8 pll_range;
	u8 pll_reset;
	u8 pll_bypass;

	u8 enable_refdiv;
	u8 bypclk_div;
	u8 IO_CLK_en_core;
	u8 ADClkSrc;
	u8 modulo;

	u16 sad_cfg;

	u32 ifreq;
	u32 timf;

	u32 xtal_hz;
};

enum dibx000_adc_states {
	DIBX000_SLOW_ADC_ON = 0,
	DIBX000_SLOW_ADC_OFF,
	DIBX000_ADC_ON,
	DIBX000_ADC_OFF,
	DIBX000_VBG_ENABLE,
	DIBX000_VBG_DISABLE,
};

#define BANDWIDTH_TO_KHZ(v)	((v) / 1000)
#define BANDWIDTH_TO_HZ(v)	((v) * 1000)

/* Chip output mode. */
#define OUTMODE_HIGH_Z              0
#define OUTMODE_MPEG2_PAR_GATED_CLK 1
#define OUTMODE_MPEG2_PAR_CONT_CLK  2
#define OUTMODE_MPEG2_SERIAL        7
#define OUTMODE_DIVERSITY           4
#define OUTMODE_MPEG2_FIFO          5
#define OUTMODE_ANALOG_ADC          6

#define INPUT_MODE_OFF                0x11
#define INPUT_MODE_DIVERSITY          0x12
#define INPUT_MODE_MPEG               0x13

enum frontend_tune_state {
	CT_TUNER_START = 10,
	CT_TUNER_STEP_0,
	CT_TUNER_STEP_1,
	CT_TUNER_STEP_2,
	CT_TUNER_STEP_3,
	CT_TUNER_STEP_4,
	CT_TUNER_STEP_5,
	CT_TUNER_STEP_6,
	CT_TUNER_STEP_7,
	CT_TUNER_STOP,

	CT_AGC_START = 20,
	CT_AGC_STEP_0,
	CT_AGC_STEP_1,
	CT_AGC_STEP_2,
	CT_AGC_STEP_3,
	CT_AGC_STEP_4,
	CT_AGC_STOP,

	CT_DEMOD_START = 30,
	CT_DEMOD_STEP_1,
	CT_DEMOD_STEP_2,
	CT_DEMOD_STEP_3,
	CT_DEMOD_STEP_4,
	CT_DEMOD_STEP_5,
	CT_DEMOD_STEP_6,
	CT_DEMOD_STEP_7,
	CT_DEMOD_STEP_8,
	CT_DEMOD_STEP_9,
	CT_DEMOD_STEP_10,
	CT_DEMOD_STEP_11,
	CT_DEMOD_SEARCH_NEXT = 51,
	CT_DEMOD_STEP_LOCKED,
	CT_DEMOD_STOP,

	CT_DONE = 100,
	CT_SHUTDOWN,

};

struct dvb_frontend_parametersContext {
#define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
#define CHANNEL_STATUS_PARAMETERS_SET       0x02
	u8 status;
	u32 tune_time_estimation[2];
	s32 tps_available;
	u16 tps[9];
};

#define FE_STATUS_TUNE_FAILED          0
#define FE_STATUS_TUNE_TIMED_OUT      -1
#define FE_STATUS_TUNE_TIME_TOO_SHORT -2
#define FE_STATUS_TUNE_PENDING        -3
#define FE_STATUS_STD_SUCCESS         -4
#define FE_STATUS_FFT_SUCCESS         -5
#define FE_STATUS_DEMOD_SUCCESS       -6
#define FE_STATUS_LOCKED              -7
#define FE_STATUS_DATA_LOCKED         -8

#define FE_CALLBACK_TIME_NEVER 0xffffffff

#define ABS(x) ((x < 0) ? (-x) : (x))

#define DATA_BUS_ACCESS_MODE_8BIT                 0x01
#define DATA_BUS_ACCESS_MODE_16BIT                0x02
#define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10

struct dibGPIOFunction {
#define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
#define BOARD_GPIO_COMPONENT_DEMOD       2
	u8 component;

#define BOARD_GPIO_FUNCTION_BOARD_ON      1
#define BOARD_GPIO_FUNCTION_BOARD_OFF     2
#define BOARD_GPIO_FUNCTION_COMPONENT_ON  3
#define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
#define BOARD_GPIO_FUNCTION_SUBBAND_PWM   5
#define BOARD_GPIO_FUNCTION_SUBBAND_GPIO   6
	u8 function;

/* mask, direction and value are used specify which GPIO to change GPIO0
 * is LSB and possible GPIO31 is MSB.  The same bit-position as in the
 * mask is used for the direction and the value. Direction == 1 is OUT,
 * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
 * value has no meaning.
 *
 * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
 * used to do the PWM. Direction gives the PWModulator to be used.
 * Value gives the PWM value in device-dependent scale.
 */
	u32 mask;
	u32 direction;
	u32 value;
};

#define MAX_NB_SUBBANDS   8
struct dibSubbandSelection {
	u8  size; /* Actual number of subbands. */
	struct {
		u16 f_mhz;
		struct dibGPIOFunction gpio;
	} subband[MAX_NB_SUBBANDS];
};

#define DEMOD_TIMF_SET    0x00
#define DEMOD_TIMF_GET    0x01
#define DEMOD_TIMF_UPDATE 0x02

#define MPEG_ON_DIBTX		1
#define DIV_ON_DIBTX		2
#define ADC_ON_DIBTX		3
#define DEMOUT_ON_HOSTBUS	4
#define DIBTX_ON_HOSTBUS	5
#define MPEG_ON_HOSTBUS		6

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
42afd061 PB	2	#ifndef DIBX000_COMMON_H
	3	#define DIBX000_COMMON_H
	4
	5	enum dibx000_i2c_interface {
77e2c0f5	6	DIBX000_I2C_INTERFACE_TUNER = 0,
42afd061	7	DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
b994d192 OG	8	DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
b994d192 OG	9	DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
42afd061 PB	10	};
	11
	12	struct dibx000_i2c_master {
	13	#define DIB3000MC 1
	14	#define DIB7000 2
	15	#define DIB7000P 11
	16	#define DIB7000MC 12
77e2c0f5	17	#define DIB8000 13
42afd061 PB	18	u16 device_rev;
	19
	20	enum dibx000_i2c_interface selected_interface;
	21
b4d6046e	22	/* struct i2c_adapter tuner_i2c_adap; */
77e2c0f5	23	struct i2c_adapter gated_tuner_i2c_adap;
b994d192 OG	24	struct i2c_adapter master_i2c_adap_gpio12;
	25	struct i2c_adapter master_i2c_adap_gpio34;
	26	struct i2c_adapter master_i2c_adap_gpio67;
42afd061 PB	27
42afd061 PB	28	struct i2c_adapter *i2c_adap;
77e2c0f5	29	u8 i2c_addr;
42afd061 PB	30
42afd061 PB	31	u16 base_reg;
5a0deeed OG	32
	33	/* for the I2C transfer */
	34	struct i2c_msg msg[34];
	35	u8 i2c_write_buffer[8];
	36	u8 i2c_read_buffer[2];
79fcce32	37	struct mutex i2c_buffer_lock;
42afd061 PB	38	};
42afd061 PB	39
77e2c0f5	40	extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
b994d192 OG	41	u16 device_rev, struct i2c_adapter *i2c_adap,
b994d192 OG	42	u8 i2c_addr);
77e2c0f5	43	extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
b994d192 OG	44	*mst,
	45	enum dibx000_i2c_interface
	46	intf, int gating);
42afd061	47	extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
77e2c0f5	48	extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
b994d192	49	extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
42afd061 PB	50
	51	#define BAND_LBAND 0x01
	52	#define BAND_UHF 0x02
	53	#define BAND_VHF 0x04
69ea31e7	54	#define BAND_SBAND 0x08
b994d192	55	#define BAND_FM 0x10
03245a5e	56	#define BAND_CBAND 0x20
69ea31e7	57
b4d6046e	58	#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
03245a5e	59	(freq_kHz) <= 115000 ? BAND_FM : \
69ea31e7 PB	60	(freq_kHz) <= 250000 ? BAND_VHF : \
	61	(freq_kHz) <= 863000 ? BAND_UHF : \
	62	(freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
42afd061 PB	63
42afd061 PB	64	struct dibx000_agc_config {
77e2c0f5 PB	65	/* defines the capabilities of this AGC-setting - using the BAND_-defines */
77e2c0f5 PB	66	u8 band_caps;
42afd061 PB	67
	68	u16 setup;
	69
	70	u16 inv_gain;
	71	u16 time_stabiliz;
	72
77e2c0f5	73	u8 alpha_level;
42afd061 PB	74	u16 thlock;
42afd061 PB	75
77e2c0f5	76	u8 wbd_inv;
42afd061 PB	77	u16 wbd_ref;
	78	u8 wbd_sel;
	79	u8 wbd_alpha;
	80
	81	u16 agc1_max;
	82	u16 agc1_min;
	83	u16 agc2_max;
	84	u16 agc2_min;
	85
	86	u8 agc1_pt1;
	87	u8 agc1_pt2;
	88	u8 agc1_pt3;
	89
	90	u8 agc1_slope1;
	91	u8 agc1_slope2;
	92
	93	u8 agc2_pt1;
	94	u8 agc2_pt2;
	95
	96	u8 agc2_slope1;
	97	u8 agc2_slope2;
	98
	99	u8 alpha_mant;
	100	u8 alpha_exp;
	101
	102	u8 beta_mant;
	103	u8 beta_exp;
	104
	105	u8 perform_agc_softsplit;
	106
	107	struct {
	108	u16 min;
	109	u16 max;
	110	u16 min_thres;
	111	u16 max_thres;
	112	} split;
	113	};
	114
	115	struct dibx000_bandwidth_config {
77e2c0f5 PB	116	u32 internal;
77e2c0f5 PB	117	u32 sampling;
42afd061 PB	118
	119	u8 pll_prediv;
	120	u8 pll_ratio;
	121	u8 pll_range;
	122	u8 pll_reset;
	123	u8 pll_bypass;
	124
	125	u8 enable_refdiv;
	126	u8 bypclk_div;
	127	u8 IO_CLK_en_core;
	128	u8 ADClkSrc;
	129	u8 modulo;
	130
	131	u16 sad_cfg;
	132
	133	u32 ifreq;
	134	u32 timf;
b6884a17 PB	135
b6884a17 PB	136	u32 xtal_hz;
42afd061 PB	137	};
	138
	139	enum dibx000_adc_states {
	140	DIBX000_SLOW_ADC_ON = 0,
	141	DIBX000_SLOW_ADC_OFF,
	142	DIBX000_ADC_ON,
	143	DIBX000_ADC_OFF,
	144	DIBX000_VBG_ENABLE,
	145	DIBX000_VBG_DISABLE,
	146	};
	147
c1f814f4 MCC	148	#define BANDWIDTH_TO_KHZ(v) ((v) / 1000)
c1f814f4 MCC	149	#define BANDWIDTH_TO_HZ(v) ((v) * 1000)
904a82e3	150
42afd061	151	/* Chip output mode. */
b6884a17 PB	152	#define OUTMODE_HIGH_Z 0
	153	#define OUTMODE_MPEG2_PAR_GATED_CLK 1
	154	#define OUTMODE_MPEG2_PAR_CONT_CLK 2
	155	#define OUTMODE_MPEG2_SERIAL 7
	156	#define OUTMODE_DIVERSITY 4
	157	#define OUTMODE_MPEG2_FIFO 5
	158	#define OUTMODE_ANALOG_ADC 6
42afd061	159
713d54a8 OG	160	#define INPUT_MODE_OFF 0x11
	161	#define INPUT_MODE_DIVERSITY 0x12
	162	#define INPUT_MODE_MPEG 0x13
	163
03245a5e	164	enum frontend_tune_state {
713d54a8 OG	165	CT_TUNER_START = 10,
	166	CT_TUNER_STEP_0,
	167	CT_TUNER_STEP_1,
	168	CT_TUNER_STEP_2,
	169	CT_TUNER_STEP_3,
	170	CT_TUNER_STEP_4,
	171	CT_TUNER_STEP_5,
	172	CT_TUNER_STEP_6,
	173	CT_TUNER_STEP_7,
	174	CT_TUNER_STOP,
	175
	176	CT_AGC_START = 20,
	177	CT_AGC_STEP_0,
	178	CT_AGC_STEP_1,
	179	CT_AGC_STEP_2,
	180	CT_AGC_STEP_3,
	181	CT_AGC_STEP_4,
	182	CT_AGC_STOP,
03245a5e OG	183
03245a5e OG	184	CT_DEMOD_START = 30,
713d54a8 OG	185	CT_DEMOD_STEP_1,
	186	CT_DEMOD_STEP_2,
	187	CT_DEMOD_STEP_3,
	188	CT_DEMOD_STEP_4,
	189	CT_DEMOD_STEP_5,
	190	CT_DEMOD_STEP_6,
	191	CT_DEMOD_STEP_7,
	192	CT_DEMOD_STEP_8,
	193	CT_DEMOD_STEP_9,
	194	CT_DEMOD_STEP_10,
173a64cb PB	195	CT_DEMOD_STEP_11,
173a64cb PB	196	CT_DEMOD_SEARCH_NEXT = 51,
713d54a8 OG	197	CT_DEMOD_STEP_LOCKED,
	198	CT_DEMOD_STOP,
	199
	200	CT_DONE = 100,
	201	CT_SHUTDOWN,
03245a5e OG	202
	203	};
	204
	205	struct dvb_frontend_parametersContext {
	206	#define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01
	207	#define CHANNEL_STATUS_PARAMETERS_SET 0x02
713d54a8 OG	208	u8 status;
	209	u32 tune_time_estimation[2];
	210	s32 tps_available;
	211	u16 tps[9];
03245a5e OG	212	};
	213
	214	#define FE_STATUS_TUNE_FAILED 0
	215	#define FE_STATUS_TUNE_TIMED_OUT -1
	216	#define FE_STATUS_TUNE_TIME_TOO_SHORT -2
	217	#define FE_STATUS_TUNE_PENDING -3
	218	#define FE_STATUS_STD_SUCCESS -4
	219	#define FE_STATUS_FFT_SUCCESS -5
	220	#define FE_STATUS_DEMOD_SUCCESS -6
	221	#define FE_STATUS_LOCKED -7
	222	#define FE_STATUS_DATA_LOCKED -8
	223
	224	#define FE_CALLBACK_TIME_NEVER 0xffffffff
	225
b4d6046e	226	#define ABS(x) ((x < 0) ? (-x) : (x))
dd316c6b OG	227
	228	#define DATA_BUS_ACCESS_MODE_8BIT 0x01
	229	#define DATA_BUS_ACCESS_MODE_16BIT 0x02
	230	#define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
	231
	232	struct dibGPIOFunction {
	233	#define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
	234	#define BOARD_GPIO_COMPONENT_DEMOD 2
	235	u8 component;
	236
	237	#define BOARD_GPIO_FUNCTION_BOARD_ON 1
	238	#define BOARD_GPIO_FUNCTION_BOARD_OFF 2
	239	#define BOARD_GPIO_FUNCTION_COMPONENT_ON 3
	240	#define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
	241	#define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5
	242	#define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6
	243	u8 function;
	244
	245	/* mask, direction and value are used specify which GPIO to change GPIO0
	246	* is LSB and possible GPIO31 is MSB. The same bit-position as in the
	247	* mask is used for the direction and the value. Direction == 1 is OUT,
	248	* 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
	249	* value has no meaning.
	250	*
	251	* In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
	252	* used to do the PWM. Direction gives the PWModulator to be used.
	253	* Value gives the PWM value in device-dependent scale.
	254	*/
	255	u32 mask;
	256	u32 direction;
	257	u32 value;
	258	};
	259
	260	#define MAX_NB_SUBBANDS 8
	261	struct dibSubbandSelection {
	262	u8 size; /* Actual number of subbands. */
	263	struct {
	264	u16 f_mhz;
	265	struct dibGPIOFunction gpio;
	266	} subband[MAX_NB_SUBBANDS];
	267	};
	268
	269	#define DEMOD_TIMF_SET 0x00
	270	#define DEMOD_TIMF_GET 0x01
	271	#define DEMOD_TIMF_UPDATE 0x02
03245a5e	272
0c32dbd7 OG	273	#define MPEG_ON_DIBTX 1
	274	#define DIV_ON_DIBTX 2
	275	#define ADC_ON_DIBTX 3
	276	#define DEMOUT_ON_HOSTBUS 4
	277	#define DIBTX_ON_HOSTBUS 5
	278	#define MPEG_ON_HOSTBUS 6
	279
42afd061	280	#endif