projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 126f1e61 RM |
1 | /* |
| 2 | * drx3973d_map_firm.h | |
| 3 | * | |
| 4 | * Copyright (C) 2006-2007 Micronas | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * version 2 only, as published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
| 20 | * 02110-1301, USA | |
| 21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __DRX3973D_MAP__H__ | |
| 25 | #define __DRX3973D_MAP__H__ | |
| 26 | ||
| 935c630c MCC |
27 | /* |
| 28 | * Note: originally, this file contained 12000+ lines of data | |
| 29 | * Probably a few lines for every firwmare assembler instruction. However, | |
| 30 | * only a few defines were actually used. So, removed all uneeded lines. | |
| 31 | * If ever needed, the other lines can be easily obtained via git history. | |
| 32 | */ | |
| be9297d1 MCC |
33 | |
| 34 | #define HI_COMM_EXEC__A 0x400000 | |
| be9297d1 | 35 | #define HI_COMM_MB__A 0x400002 |
| be9297d1 | 36 | #define HI_CT_REG_COMM_STATE__A 0x410001 |
| be9297d1 | 37 | #define HI_RA_RAM_SRV_RES__A 0x420031 |
| be9297d1 | 38 | #define HI_RA_RAM_SRV_CMD__A 0x420032 |
| be9297d1 MCC |
39 | #define HI_RA_RAM_SRV_CMD_RESET 0x2 |
| 40 | #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 | |
| be9297d1 | 41 | #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 |
| be9297d1 | 42 | #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 |
| be9297d1 | 43 | #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 |
| be9297d1 | 44 | #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 |
| be9297d1 | 45 | #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 |
| be9297d1 | 46 | #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 |
| be9297d1 | 47 | #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 |
| be9297d1 | 48 | #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 |
| be9297d1 | 49 | #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 |
| be9297d1 MCC |
50 | #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 |
| 51 | #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 | |
| 52 | #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 | |
| be9297d1 | 53 | #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 |
| be9297d1 | 54 | #define HI_RA_RAM_USR_BEGIN__A 0x420040 |
| be9297d1 | 55 | #define HI_IF_RAM_TRP_BPT0__AX 0x430000 |
| be9297d1 | 56 | #define HI_IF_RAM_USR_BEGIN__A 0x430200 |
| be9297d1 | 57 | #define SC_COMM_EXEC__A 0x800000 |
| be9297d1 | 58 | #define SC_COMM_EXEC_CTL_STOP 0x0 |
| be9297d1 | 59 | #define SC_COMM_STATE__A 0x800001 |
| be9297d1 | 60 | #define SC_RA_RAM_PARAM0__A 0x820040 |
| be9297d1 | 61 | #define SC_RA_RAM_PARAM1__A 0x820041 |
| be9297d1 | 62 | #define SC_RA_RAM_CMD_ADDR__A 0x820042 |
| be9297d1 | 63 | #define SC_RA_RAM_CMD__A 0x820043 |
| be9297d1 | 64 | #define SC_RA_RAM_CMD_PROC_START 0x1 |
| be9297d1 | 65 | #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 |
| be9297d1 | 66 | #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 |
| be9297d1 | 67 | #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 |
| be9297d1 | 68 | #define SC_RA_RAM_LOCKTRACK_MIN 0x1 |
| be9297d1 MCC |
69 | #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 |
| 70 | #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 | |
| be9297d1 MCC |
71 | #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 |
| 72 | #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 | |
| 73 | #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 | |
| 74 | #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC | |
| be9297d1 MCC |
75 | #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 |
| 76 | #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 | |
| 77 | #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 | |
| be9297d1 MCC |
78 | #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 |
| 79 | #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 | |
| 80 | #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 | |
| 81 | #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 | |
| be9297d1 MCC |
82 | #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 |
| 83 | #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 | |
| 84 | #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 | |
| 85 | #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 | |
| 86 | #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 | |
| be9297d1 MCC |
87 | #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 |
| 88 | #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 | |
| be9297d1 | 89 | #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 |
| be9297d1 | 90 | #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 |
| be9297d1 | 91 | #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 |
| be9297d1 | 92 | #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 |
| be9297d1 | 93 | #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 |
| be9297d1 | 94 | #define SC_RA_RAM_LOCK__A 0x82004B |
| be9297d1 | 95 | #define SC_RA_RAM_LOCK_DEMOD__M 0x1 |
| be9297d1 | 96 | #define SC_RA_RAM_LOCK_FEC__M 0x2 |
| be9297d1 | 97 | #define SC_RA_RAM_LOCK_MPEG__M 0x4 |
| be9297d1 | 98 | #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C |
| be9297d1 | 99 | #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 |
| be9297d1 | 100 | #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D |
| be9297d1 | 101 | #define SC_RA_RAM_CONFIG__A 0x820050 |
| be9297d1 | 102 | #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 |
| be9297d1 | 103 | #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 |
| be9297d1 | 104 | #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 |
| be9297d1 | 105 | #define SC_RA_RAM_IF_SAVE__AX 0x82008E |
| be9297d1 | 106 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 |
| be9297d1 MCC |
107 | #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 |
| 108 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 | |
| be9297d1 MCC |
109 | #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 |
| 110 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 | |
| be9297d1 | 111 | #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 |
| be9297d1 | 112 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 |
| be9297d1 MCC |
113 | #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 |
| 114 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 | |
| be9297d1 MCC |
115 | #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 |
| 116 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 | |
| be9297d1 | 117 | #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 |
| be9297d1 | 118 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 |
| be9297d1 MCC |
119 | #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 |
| 120 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 | |
| be9297d1 MCC |
121 | #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 |
| 122 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 | |
| be9297d1 | 123 | #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 |
| be9297d1 | 124 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA |
| be9297d1 MCC |
125 | #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB |
| 126 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB | |
| be9297d1 MCC |
127 | #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 |
| 128 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC | |
| be9297d1 | 129 | #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 |
| be9297d1 | 130 | #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD |
| be9297d1 | 131 | #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 |
| be9297d1 | 132 | #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 |
| be9297d1 | 133 | #define SC_RA_RAM_BAND__A 0x8200EC |
| be9297d1 | 134 | #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 |
| be9297d1 MCC |
135 | #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F |
| 136 | #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 | |
| be9297d1 | 137 | #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F |
| be9297d1 | 138 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 |
| be9297d1 | 139 | #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 |
| be9297d1 | 140 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB |
| be9297d1 | 141 | #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 |
| be9297d1 | 142 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF |
| be9297d1 | 143 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 |
| be9297d1 | 144 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E |
| be9297d1 | 145 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 |
| be9297d1 | 146 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A |
| be9297d1 | 147 | #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 |
| be9297d1 | 148 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB |
| be9297d1 | 149 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 |
| be9297d1 | 150 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F |
| be9297d1 | 151 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 |
| be9297d1 | 152 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 |
| be9297d1 MCC |
153 | #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 |
| 154 | #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE | |
| be9297d1 | 155 | #define SC_RA_RAM_PROC_LOCKTRACK 0x0 |
| be9297d1 | 156 | #define FE_COMM_EXEC__A 0xC00000 |
| be9297d1 | 157 | #define FE_AD_REG_COMM_EXEC__A 0xC10000 |
| be9297d1 | 158 | #define FE_AD_REG_FDB_IN__A 0xC10012 |
| be9297d1 | 159 | #define FE_AD_REG_PD__A 0xC10013 |
| be9297d1 | 160 | #define FE_AD_REG_INVEXT__A 0xC10014 |
| be9297d1 | 161 | #define FE_AD_REG_CLKNEG__A 0xC10015 |
| be9297d1 | 162 | #define FE_AG_REG_COMM_EXEC__A 0xC20000 |
| be9297d1 | 163 | #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 |
| be9297d1 MCC |
164 | #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 |
| 165 | #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 | |
| 166 | #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 | |
| be9297d1 MCC |
167 | #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 |
| 168 | #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 | |
| be9297d1 MCC |
169 | #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 |
| 170 | #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 | |
| 171 | #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 | |
| be9297d1 MCC |
172 | #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 |
| 173 | #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 | |
| 174 | #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 | |
| be9297d1 | 175 | #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 |
| be9297d1 | 176 | #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 |
| be9297d1 MCC |
177 | #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 |
| 178 | #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 | |
| be9297d1 | 179 | #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 |
| be9297d1 MCC |
180 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 |
| 181 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 | |
| 182 | #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 | |
| be9297d1 | 183 | #define FE_AG_REG_AG_PWD__A 0xC20015 |
| be9297d1 MCC |
184 | #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 |
| 185 | #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 | |
| 186 | #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 | |
| be9297d1 | 187 | #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 |
| be9297d1 | 188 | #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 |
| be9297d1 | 189 | #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A |
| be9297d1 | 190 | #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B |
| be9297d1 | 191 | #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 |
| be9297d1 | 192 | #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 |
| be9297d1 | 193 | #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 |
| be9297d1 | 194 | #define FE_AG_REG_EGC_SET_LVL__M 0x1FF |
| be9297d1 | 195 | #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 |
| be9297d1 | 196 | #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 |
| be9297d1 | 197 | #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 |
| be9297d1 | 198 | #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 |
| be9297d1 | 199 | #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A |
| be9297d1 | 200 | #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B |
| be9297d1 | 201 | #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C |
| be9297d1 | 202 | #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D |
| be9297d1 | 203 | #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E |
| be9297d1 | 204 | #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 |
| be9297d1 | 205 | #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF |
| be9297d1 | 206 | #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 |
| be9297d1 | 207 | #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 |
| be9297d1 | 208 | #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 |
| be9297d1 | 209 | #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 |
| be9297d1 | 210 | #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 |
| be9297d1 | 211 | #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF |
| be9297d1 | 212 | #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 |
| be9297d1 | 213 | #define FE_AG_REG_IND_WIN__A 0xC2003C |
| be9297d1 | 214 | #define FE_AG_REG_IND_THD_LOL__A 0xC2003D |
| be9297d1 | 215 | #define FE_AG_REG_IND_THD_HIL__A 0xC2003E |
| be9297d1 | 216 | #define FE_AG_REG_IND_DEL__A 0xC2003F |
| be9297d1 | 217 | #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 |
| be9297d1 | 218 | #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 |
| be9297d1 | 219 | #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 |
| be9297d1 | 220 | #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 |
| be9297d1 | 221 | #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 |
| be9297d1 | 222 | #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 |
| be9297d1 | 223 | #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 |
| be9297d1 | 224 | #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 |
| be9297d1 | 225 | #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 |
| be9297d1 | 226 | #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 |
| be9297d1 | 227 | #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A |
| be9297d1 | 228 | #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B |
| be9297d1 | 229 | #define FE_AG_REG_PDC_MAX__A 0xC2004C |
| be9297d1 | 230 | #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D |
| be9297d1 | 231 | #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E |
| be9297d1 | 232 | #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F |
| be9297d1 | 233 | #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 |
| be9297d1 | 234 | #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 |
| be9297d1 | 235 | #define FE_AG_REG_TGC_SET_LVL__M 0x3F |
| be9297d1 | 236 | #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 |
| be9297d1 | 237 | #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 |
| be9297d1 | 238 | #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 |
| be9297d1 | 239 | #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 |
| be9297d1 | 240 | #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 |
| be9297d1 | 241 | #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 |
| be9297d1 | 242 | #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 |
| be9297d1 | 243 | #define FE_AG_REG_FGM_WRI__A 0xC20061 |
| be9297d1 | 244 | #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 |
| be9297d1 | 245 | #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 |
| be9297d1 | 246 | #define FE_FS_REG_COMM_EXEC__A 0xC30000 |
| be9297d1 | 247 | #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 |
| be9297d1 | 248 | #define FE_FD_REG_COMM_EXEC__A 0xC40000 |
| be9297d1 | 249 | #define FE_FD_REG_SCL__A 0xC40010 |
| be9297d1 | 250 | #define FE_FD_REG_MAX_LEV__A 0xC40011 |
| be9297d1 | 251 | #define FE_FD_REG_NR__A 0xC40012 |
| be9297d1 | 252 | #define FE_FD_REG_MEAS_VAL__A 0xC40014 |
| be9297d1 | 253 | #define FE_IF_REG_COMM_EXEC__A 0xC50000 |
| be9297d1 MCC |
254 | #define FE_IF_REG_INCR0__A 0xC50010 |
| 255 | #define FE_IF_REG_INCR0__W 16 | |
| 256 | #define FE_IF_REG_INCR0__M 0xFFFF | |
| be9297d1 | 257 | #define FE_IF_REG_INCR1__A 0xC50011 |
| be9297d1 | 258 | #define FE_IF_REG_INCR1__M 0xFF |
| be9297d1 | 259 | #define FE_CF_REG_COMM_EXEC__A 0xC60000 |
| be9297d1 | 260 | #define FE_CF_REG_SCL__A 0xC60010 |
| be9297d1 | 261 | #define FE_CF_REG_MAX_LEV__A 0xC60011 |
| be9297d1 | 262 | #define FE_CF_REG_NR__A 0xC60012 |
| be9297d1 | 263 | #define FE_CF_REG_IMP_VAL__A 0xC60013 |
| be9297d1 | 264 | #define FE_CF_REG_MEAS_VAL__A 0xC60014 |
| be9297d1 | 265 | #define FE_CU_REG_COMM_EXEC__A 0xC70000 |
| be9297d1 | 266 | #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 |
| be9297d1 | 267 | #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 |
| be9297d1 | 268 | #define FT_COMM_EXEC__A 0x1000000 |
| be9297d1 | 269 | #define FT_REG_COMM_EXEC__A 0x1010000 |
| be9297d1 | 270 | #define CP_COMM_EXEC__A 0x1400000 |
| be9297d1 | 271 | #define CP_REG_COMM_EXEC__A 0x1410000 |
| be9297d1 | 272 | #define CP_REG_INTERVAL__A 0x1410011 |
| be9297d1 | 273 | #define CP_REG_BR_SPL_OFFSET__A 0x1410023 |
| be9297d1 | 274 | #define CP_REG_BR_STR_DEL__A 0x1410024 |
| be9297d1 | 275 | #define CP_REG_RT_ANG_INC0__A 0x1410030 |
| be9297d1 | 276 | #define CP_REG_RT_ANG_INC1__A 0x1410031 |
| be9297d1 | 277 | #define CP_REG_RT_DETECT_ENA__A 0x1410032 |
| be9297d1 | 278 | #define CP_REG_RT_DETECT_TRH__A 0x1410033 |
| be9297d1 | 279 | #define CP_REG_RT_EXP_MARG__A 0x141003E |
| be9297d1 | 280 | #define CP_REG_AC_NEXP_OFFS__A 0x1410040 |
| be9297d1 | 281 | #define CP_REG_AC_AVER_POW__A 0x1410041 |
| be9297d1 | 282 | #define CP_REG_AC_MAX_POW__A 0x1410042 |
| be9297d1 | 283 | #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 |
| be9297d1 | 284 | #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 |
| be9297d1 | 285 | #define CP_REG_AC_AMP_MODE__A 0x1410047 |
| be9297d1 | 286 | #define CP_REG_AC_AMP_FIX__A 0x1410048 |
| be9297d1 | 287 | #define CP_REG_AC_ANG_MODE__A 0x141004A |
| be9297d1 | 288 | #define CE_COMM_EXEC__A 0x1800000 |
| be9297d1 | 289 | #define CE_REG_COMM_EXEC__A 0x1810000 |
| be9297d1 | 290 | #define CE_REG_TAPSET__A 0x1810011 |
| be9297d1 | 291 | #define CE_REG_AVG_POW__A 0x1810012 |
| be9297d1 | 292 | #define CE_REG_MAX_POW__A 0x1810013 |
| be9297d1 | 293 | #define CE_REG_ATT__A 0x1810014 |
| be9297d1 | 294 | #define CE_REG_NRED__A 0x1810015 |
| be9297d1 | 295 | #define CE_REG_NE_ERR_SELECT__A 0x1810043 |
| be9297d1 | 296 | #define CE_REG_NE_TD_CAL__A 0x1810044 |
| be9297d1 | 297 | #define CE_REG_NE_MIXAVG__A 0x1810046 |
| be9297d1 | 298 | #define CE_REG_NE_NUPD_OFS__A 0x1810047 |
| be9297d1 | 299 | #define CE_REG_PE_NEXP_OFFS__A 0x1810050 |
| be9297d1 | 300 | #define CE_REG_PE_TIMESHIFT__A 0x1810051 |
| be9297d1 | 301 | #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 |
| be9297d1 | 302 | #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 |
| be9297d1 | 303 | #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 |
| be9297d1 | 304 | #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 |
| be9297d1 | 305 | #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 |
| be9297d1 | 306 | #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A |
| be9297d1 | 307 | #define CE_REG_TI_NEXP_OFFS__A 0x1810070 |
| be9297d1 | 308 | #define CE_REG_FI_SHT_INCR__A 0x1810090 |
| be9297d1 | 309 | #define CE_REG_FI_EXP_NORM__A 0x1810091 |
| be9297d1 | 310 | #define CE_REG_IR_INPUTSEL__A 0x18100A0 |
| be9297d1 | 311 | #define CE_REG_IR_STARTPOS__A 0x18100A1 |
| be9297d1 | 312 | #define CE_REG_IR_NEXP_THRES__A 0x18100A2 |
| be9297d1 | 313 | #define CE_REG_FR_TREAL00__A 0x1820010 |
| be9297d1 | 314 | #define CE_REG_FR_TIMAG00__A 0x1820011 |
| be9297d1 | 315 | #define CE_REG_FR_TREAL01__A 0x1820012 |
| be9297d1 | 316 | #define CE_REG_FR_TIMAG01__A 0x1820013 |
| be9297d1 | 317 | #define CE_REG_FR_TREAL02__A 0x1820014 |
| be9297d1 | 318 | #define CE_REG_FR_TIMAG02__A 0x1820015 |
| be9297d1 | 319 | #define CE_REG_FR_TREAL03__A 0x1820016 |
| be9297d1 | 320 | #define CE_REG_FR_TIMAG03__A 0x1820017 |
| be9297d1 | 321 | #define CE_REG_FR_TREAL04__A 0x1820018 |
| be9297d1 | 322 | #define CE_REG_FR_TIMAG04__A 0x1820019 |
| be9297d1 | 323 | #define CE_REG_FR_TREAL05__A 0x182001A |
| be9297d1 | 324 | #define CE_REG_FR_TIMAG05__A 0x182001B |
| be9297d1 | 325 | #define CE_REG_FR_TREAL06__A 0x182001C |
| be9297d1 | 326 | #define CE_REG_FR_TIMAG06__A 0x182001D |
| be9297d1 | 327 | #define CE_REG_FR_TREAL07__A 0x182001E |
| be9297d1 | 328 | #define CE_REG_FR_TIMAG07__A 0x182001F |
| be9297d1 | 329 | #define CE_REG_FR_TREAL08__A 0x1820020 |
| be9297d1 | 330 | #define CE_REG_FR_TIMAG08__A 0x1820021 |
| be9297d1 | 331 | #define CE_REG_FR_TREAL09__A 0x1820022 |
| be9297d1 | 332 | #define CE_REG_FR_TIMAG09__A 0x1820023 |
| be9297d1 | 333 | #define CE_REG_FR_TREAL10__A 0x1820024 |
| be9297d1 | 334 | #define CE_REG_FR_TIMAG10__A 0x1820025 |
| be9297d1 | 335 | #define CE_REG_FR_TREAL11__A 0x1820026 |
| be9297d1 | 336 | #define CE_REG_FR_TIMAG11__A 0x1820027 |
| be9297d1 | 337 | #define CE_REG_FR_MID_TAP__A 0x1820028 |
| be9297d1 | 338 | #define CE_REG_FR_SQS_G00__A 0x1820029 |
| be9297d1 | 339 | #define CE_REG_FR_SQS_G01__A 0x182002A |
| be9297d1 | 340 | #define CE_REG_FR_SQS_G02__A 0x182002B |
| be9297d1 | 341 | #define CE_REG_FR_SQS_G03__A 0x182002C |
| be9297d1 | 342 | #define CE_REG_FR_SQS_G04__A 0x182002D |
| be9297d1 | 343 | #define CE_REG_FR_SQS_G05__A 0x182002E |
| be9297d1 | 344 | #define CE_REG_FR_SQS_G06__A 0x182002F |
| be9297d1 | 345 | #define CE_REG_FR_SQS_G07__A 0x1820030 |
| be9297d1 | 346 | #define CE_REG_FR_SQS_G08__A 0x1820031 |
| be9297d1 | 347 | #define CE_REG_FR_SQS_G09__A 0x1820032 |
| be9297d1 | 348 | #define CE_REG_FR_SQS_G10__A 0x1820033 |
| be9297d1 | 349 | #define CE_REG_FR_SQS_G11__A 0x1820034 |
| be9297d1 | 350 | #define CE_REG_FR_SQS_G12__A 0x1820035 |
| be9297d1 | 351 | #define CE_REG_FR_RIO_G00__A 0x1820036 |
| be9297d1 | 352 | #define CE_REG_FR_RIO_G01__A 0x1820037 |
| be9297d1 | 353 | #define CE_REG_FR_RIO_G02__A 0x1820038 |
| be9297d1 | 354 | #define CE_REG_FR_RIO_G03__A 0x1820039 |
| be9297d1 | 355 | #define CE_REG_FR_RIO_G04__A 0x182003A |
| be9297d1 | 356 | #define CE_REG_FR_RIO_G05__A 0x182003B |
| be9297d1 | 357 | #define CE_REG_FR_RIO_G06__A 0x182003C |
| be9297d1 | 358 | #define CE_REG_FR_RIO_G07__A 0x182003D |
| be9297d1 | 359 | #define CE_REG_FR_RIO_G08__A 0x182003E |
| be9297d1 | 360 | #define CE_REG_FR_RIO_G09__A 0x182003F |
| be9297d1 | 361 | #define CE_REG_FR_RIO_G10__A 0x1820040 |
| be9297d1 | 362 | #define CE_REG_FR_MODE__A 0x1820041 |
| be9297d1 | 363 | #define CE_REG_FR_SQS_TRH__A 0x1820042 |
| be9297d1 | 364 | #define CE_REG_FR_RIO_GAIN__A 0x1820043 |
| be9297d1 | 365 | #define CE_REG_FR_BYPASS__A 0x1820044 |
| be9297d1 | 366 | #define CE_REG_FR_PM_SET__A 0x1820045 |
| be9297d1 | 367 | #define CE_REG_FR_ERR_SH__A 0x1820046 |
| be9297d1 | 368 | #define CE_REG_FR_MAN_SH__A 0x1820047 |
| be9297d1 | 369 | #define CE_REG_FR_TAP_SH__A 0x1820048 |
| be9297d1 | 370 | #define EQ_COMM_EXEC__A 0x1C00000 |
| be9297d1 | 371 | #define EQ_REG_COMM_EXEC__A 0x1C10000 |
| be9297d1 | 372 | #define EQ_REG_COMM_MB__A 0x1C10002 |
| be9297d1 | 373 | #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 |
| be9297d1 | 374 | #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 |
| be9297d1 | 375 | #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 |
| be9297d1 | 376 | #define EQ_REG_SN_CEGAIN__A 0x1C1002A |
| be9297d1 | 377 | #define EQ_REG_SN_OFFSET__A 0x1C1002B |
| be9297d1 | 378 | #define EQ_REG_RC_SEL_CAR__A 0x1C10032 |
| be9297d1 | 379 | #define EQ_REG_RC_SEL_CAR_INIT 0x0 |
| be9297d1 | 380 | #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 |
| be9297d1 MCC |
381 | #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 |
| 382 | #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 | |
| be9297d1 MCC |
383 | #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 |
| 384 | #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 | |
| be9297d1 MCC |
385 | #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 |
| 386 | #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 | |
| be9297d1 | 387 | #define EQ_REG_OT_CONST__A 0x1C10046 |
| be9297d1 | 388 | #define EQ_REG_OT_ALPHA__A 0x1C10047 |
| be9297d1 | 389 | #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 |
| be9297d1 | 390 | #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 |
| be9297d1 | 391 | #define EQ_REG_OT_CSI_STEP__A 0x1C1004A |
| be9297d1 | 392 | #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B |
| be9297d1 | 393 | #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 |
| be9297d1 | 394 | #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 |
| be9297d1 | 395 | #define EC_SB_REG_COMM_EXEC__A 0x2010000 |
| be9297d1 | 396 | #define EC_SB_REG_TR_MODE__A 0x2010010 |
| be9297d1 MCC |
397 | #define EC_SB_REG_TR_MODE_8K 0x0 |
| 398 | #define EC_SB_REG_TR_MODE_2K 0x1 | |
| be9297d1 | 399 | #define EC_SB_REG_CONST__A 0x2010011 |
| be9297d1 MCC |
400 | #define EC_SB_REG_CONST_QPSK 0x0 |
| 401 | #define EC_SB_REG_CONST_16QAM 0x1 | |
| 402 | #define EC_SB_REG_CONST_64QAM 0x2 | |
| be9297d1 | 403 | #define EC_SB_REG_ALPHA__A 0x2010012 |
| be9297d1 | 404 | #define EC_SB_REG_PRIOR__A 0x2010013 |
| be9297d1 MCC |
405 | #define EC_SB_REG_PRIOR_HI 0x0 |
| 406 | #define EC_SB_REG_PRIOR_LO 0x1 | |
| be9297d1 | 407 | #define EC_SB_REG_CSI_HI__A 0x2010014 |
| be9297d1 | 408 | #define EC_SB_REG_CSI_LO__A 0x2010015 |
| be9297d1 | 409 | #define EC_SB_REG_SMB_TGL__A 0x2010016 |
| be9297d1 | 410 | #define EC_SB_REG_SNR_HI__A 0x2010017 |
| be9297d1 | 411 | #define EC_SB_REG_SNR_MID__A 0x2010018 |
| be9297d1 | 412 | #define EC_SB_REG_SNR_LO__A 0x2010019 |
| be9297d1 | 413 | #define EC_SB_REG_SCALE_MSB__A 0x201001A |
| be9297d1 | 414 | #define EC_SB_REG_SCALE_BIT2__A 0x201001B |
| be9297d1 | 415 | #define EC_SB_REG_SCALE_LSB__A 0x201001C |
| be9297d1 | 416 | #define EC_SB_REG_CSI_OFS__A 0x201001D |
| be9297d1 | 417 | #define EC_VD_REG_COMM_EXEC__A 0x2090000 |
| be9297d1 | 418 | #define EC_VD_REG_FORCE__A 0x2090010 |
| be9297d1 | 419 | #define EC_VD_REG_SET_CODERATE__A 0x2090011 |
| be9297d1 MCC |
420 | #define EC_VD_REG_SET_CODERATE_C1_2 0x0 |
| 421 | #define EC_VD_REG_SET_CODERATE_C2_3 0x1 | |
| 422 | #define EC_VD_REG_SET_CODERATE_C3_4 0x2 | |
| 423 | #define EC_VD_REG_SET_CODERATE_C5_6 0x3 | |
| 424 | #define EC_VD_REG_SET_CODERATE_C7_8 0x4 | |
| be9297d1 | 425 | #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 |
| be9297d1 | 426 | #define EC_VD_REG_RLK_ENA__A 0x2090014 |
| be9297d1 | 427 | #define EC_OD_REG_COMM_EXEC__A 0x2110000 |
| be9297d1 | 428 | #define EC_OD_REG_SYNC__A 0x2110010 |
| be9297d1 | 429 | #define EC_OD_DEINT_RAM__A 0x2120000 |
| be9297d1 | 430 | #define EC_RS_REG_COMM_EXEC__A 0x2130000 |
| be9297d1 | 431 | #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 |
| be9297d1 | 432 | #define EC_RS_REG_VAL__A 0x2130011 |
| be9297d1 | 433 | #define EC_RS_REG_VAL_PCK 0x1 |
| be9297d1 | 434 | #define EC_RS_EC_RAM__A 0x2140000 |
| be9297d1 | 435 | #define EC_OC_REG_COMM_EXEC__A 0x2150000 |
| be9297d1 MCC |
436 | #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 437 | #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 | |
| be9297d1 | 438 | #define EC_OC_REG_COMM_INT_STA__A 0x2150007 |
| be9297d1 | 439 | #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 |
| be9297d1 MCC |
440 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 |
| 441 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 | |
| 442 | #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 | |
| be9297d1 MCC |
443 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 |
| 444 | #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 | |
| be9297d1 | 445 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 |
| be9297d1 | 446 | #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 |
| be9297d1 | 447 | #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 |
| be9297d1 | 448 | #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 |
| be9297d1 MCC |
449 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 |
| 450 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 | |
| 451 | #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 | |
| be9297d1 | 452 | #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 |
| be9297d1 | 453 | #define EC_OC_REG_OC_MPG_SIO__M 0xFFF |
| be9297d1 | 454 | #define EC_OC_REG_OC_MON_SIO__A 0x2150013 |
| be9297d1 | 455 | #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 |
| be9297d1 | 456 | #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 |
| be9297d1 | 457 | #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 |
| be9297d1 | 458 | #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 |
| be9297d1 | 459 | #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D |
| be9297d1 | 460 | #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E |
| be9297d1 | 461 | #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F |
| be9297d1 | 462 | #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 |
| be9297d1 | 463 | #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 |
| be9297d1 | 464 | #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 |
| be9297d1 | 465 | #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 |
| be9297d1 | 466 | #define EC_OC_REG_RCN_MODE__A 0x2150027 |
| be9297d1 | 467 | #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 |
| be9297d1 | 468 | #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 |
| be9297d1 | 469 | #define EC_OC_REG_RCN_CST_LOP__A 0x215002A |
| be9297d1 | 470 | #define EC_OC_REG_RCN_CST_HIP__A 0x215002B |
| 935c630c MCC |
471 | #define EC_OC_REG_RCN_SET_LVL__A 0x215002C |
| 472 | #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D | |
| 473 | #define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 | |
| 474 | #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 | |
| 475 | #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 | |
| 476 | #define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 | |
| 477 | #define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 | |
| 478 | #define EC_OC_REG_OCR_MPG_UOS__M 0xFFF | |
| 479 | #define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 | |
| be9297d1 | 480 | #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 |
| be9297d1 | 481 | #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 |
| be9297d1 | 482 | #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 |
| be9297d1 | 483 | #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 |
| be9297d1 | 484 | #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 |
| be9297d1 | 485 | #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 |
| be9297d1 | 486 | #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 |
| be9297d1 | 487 | #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 |
| be9297d1 | 488 | #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 |
| be9297d1 | 489 | #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 |
| be9297d1 | 490 | #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 |
| be9297d1 | 491 | #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 |
| be9297d1 | 492 | #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 |
| be9297d1 | 493 | #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 |
| be9297d1 | 494 | #define EC_OC_REG_OCR_MON_WRI__A 0x215003A |
| be9297d1 | 495 | #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 |
| be9297d1 | 496 | #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 |
| be9297d1 | 497 | #define CC_REG_OSC_MODE__A 0x2410010 |
| be9297d1 | 498 | #define CC_REG_OSC_MODE_M20 0x1 |
| be9297d1 | 499 | #define CC_REG_PLL_MODE__A 0x2410011 |
| be9297d1 | 500 | #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 |
| be9297d1 | 501 | #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 |
| be9297d1 | 502 | #define CC_REG_REF_DIVIDE__A 0x2410012 |
| be9297d1 | 503 | #define CC_REG_PWD_MODE__A 0x2410015 |
| be9297d1 | 504 | #define CC_REG_PWD_MODE_DOWN_PLL 0x2 |
| be9297d1 | 505 | #define CC_REG_UPDATE__A 0x2410017 |
| be9297d1 | 506 | #define CC_REG_UPDATE_KEY 0x3973 |
| be9297d1 | 507 | #define CC_REG_JTAGID_L__A 0x2410019 |
| be9297d1 | 508 | #define LC_COMM_EXEC__A 0x2800000 |
| be9297d1 | 509 | #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C |
| be9297d1 | 510 | #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A |
| be9297d1 | 511 | #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 |
| be9297d1 | 512 | #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 |
| be9297d1 MCC |
513 | #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 |
| 514 | #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 | |
| be9297d1 | 515 | #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 |
| be9297d1 | 516 | #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 |
| be9297d1 MCC |
517 | #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 |
| 518 | #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 | |
| be9297d1 | 519 | #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 |
| be9297d1 | 520 | #define B_HI_COMM_EXEC__A 0x400000 |
| be9297d1 | 521 | #define B_HI_COMM_MB__A 0x400002 |
| be9297d1 | 522 | #define B_HI_CT_REG_COMM_STATE__A 0x410001 |
| be9297d1 | 523 | #define B_HI_RA_RAM_SRV_RES__A 0x420031 |
| be9297d1 | 524 | #define B_HI_RA_RAM_SRV_CMD__A 0x420032 |
| be9297d1 MCC |
525 | #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 |
| 526 | #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 | |
| be9297d1 | 527 | #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 |
| be9297d1 | 528 | #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 |
| be9297d1 | 529 | #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 |
| be9297d1 | 530 | #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 |
| be9297d1 | 531 | #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 |
| be9297d1 | 532 | #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 |
| be9297d1 | 533 | #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 |
| be9297d1 | 534 | #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 |
| be9297d1 | 535 | #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 |
| be9297d1 MCC |
536 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 |
| 537 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 | |
| 538 | #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 | |
| be9297d1 | 539 | #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 |
| be9297d1 | 540 | #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 |
| be9297d1 | 541 | #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 |
| be9297d1 | 542 | #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 |
| be9297d1 | 543 | #define B_SC_COMM_EXEC__A 0x800000 |
| be9297d1 | 544 | #define B_SC_COMM_EXEC_CTL_STOP 0x0 |
| be9297d1 | 545 | #define B_SC_COMM_STATE__A 0x800001 |
| be9297d1 | 546 | #define B_SC_RA_RAM_PARAM0__A 0x820040 |
| be9297d1 | 547 | #define B_SC_RA_RAM_PARAM1__A 0x820041 |
| be9297d1 | 548 | #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 |
| be9297d1 | 549 | #define B_SC_RA_RAM_CMD__A 0x820043 |
| be9297d1 | 550 | #define B_SC_RA_RAM_CMD_PROC_START 0x1 |
| be9297d1 | 551 | #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 |
| be9297d1 | 552 | #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 |
| be9297d1 | 553 | #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 |
| be9297d1 | 554 | #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 |
| be9297d1 MCC |
555 | #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 |
| 556 | #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 | |
| be9297d1 MCC |
557 | #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 |
| 558 | #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 | |
| 559 | #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 | |
| 560 | #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC | |
| be9297d1 MCC |
561 | #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 |
| 562 | #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 | |
| 563 | #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 | |
| be9297d1 MCC |
564 | #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 |
| 565 | #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 | |
| 566 | #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 | |
| 567 | #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 | |
| be9297d1 MCC |
568 | #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 |
| 569 | #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 | |
| 570 | #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 | |
| 571 | #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 | |
| 572 | #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 | |
| be9297d1 MCC |
573 | #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 |
| 574 | #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 | |
| be9297d1 | 575 | #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 |
| be9297d1 | 576 | #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 |
| be9297d1 | 577 | #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 |
| be9297d1 | 578 | #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 |
| be9297d1 | 579 | #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 |
| be9297d1 | 580 | #define B_SC_RA_RAM_LOCK__A 0x82004B |
| be9297d1 | 581 | #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 |
| be9297d1 | 582 | #define B_SC_RA_RAM_LOCK_FEC__M 0x2 |
| be9297d1 | 583 | #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 |
| be9297d1 | 584 | #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C |
| be9297d1 | 585 | #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 |
| be9297d1 | 586 | #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D |
| be9297d1 | 587 | #define B_SC_RA_RAM_CONFIG__A 0x820050 |
| be9297d1 | 588 | #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 |
| be9297d1 | 589 | #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 |
| be9297d1 | 590 | #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 |
| be9297d1 | 591 | #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 |
| be9297d1 | 592 | #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 |
| be9297d1 | 593 | #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D |
| be9297d1 | 594 | #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E |
| be9297d1 | 595 | #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E |
| be9297d1 | 596 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 |
| be9297d1 | 597 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 |
| be9297d1 | 598 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A |
| be9297d1 | 599 | #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B |
| be9297d1 | 600 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C |
| be9297d1 | 601 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D |
| be9297d1 | 602 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E |
| be9297d1 | 603 | #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F |
| be9297d1 | 604 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 |
| be9297d1 MCC |
605 | #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 |
| 606 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 | |
| be9297d1 MCC |
607 | #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 |
| 608 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 | |
| be9297d1 | 609 | #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 |
| be9297d1 | 610 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 |
| be9297d1 MCC |
611 | #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 |
| 612 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 | |
| be9297d1 MCC |
613 | #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 |
| 614 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 | |
| be9297d1 | 615 | #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 |
| be9297d1 | 616 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 |
| be9297d1 MCC |
617 | #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 |
| 618 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 | |
| be9297d1 MCC |
619 | #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 |
| 620 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 | |
| be9297d1 | 621 | #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 |
| be9297d1 | 622 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA |
| be9297d1 MCC |
623 | #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB |
| 624 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB | |
| be9297d1 MCC |
625 | #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 |
| 626 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC | |
| be9297d1 | 627 | #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 |
| be9297d1 | 628 | #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD |
| be9297d1 | 629 | #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 |
| be9297d1 | 630 | #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 |
| be9297d1 | 631 | #define B_SC_RA_RAM_BAND__A 0x8200EC |
| be9297d1 | 632 | #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 |
| be9297d1 MCC |
633 | #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F |
| 634 | #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 | |
| be9297d1 | 635 | #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F |
| be9297d1 | 636 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 |
| be9297d1 | 637 | #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 |
| be9297d1 | 638 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 |
| be9297d1 | 639 | #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 |
| be9297d1 | 640 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D |
| be9297d1 | 641 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 |
| be9297d1 | 642 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D |
| be9297d1 | 643 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 |
| be9297d1 | 644 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 |
| be9297d1 | 645 | #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 |
| be9297d1 | 646 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 |
| be9297d1 | 647 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 |
| be9297d1 | 648 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A |
| be9297d1 | 649 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 |
| be9297d1 | 650 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB |
| be9297d1 MCC |
651 | #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 |
| 652 | #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE | |
| be9297d1 | 653 | #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 |
| be9297d1 | 654 | #define B_FE_COMM_EXEC__A 0xC00000 |
| be9297d1 | 655 | #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 |
| be9297d1 | 656 | #define B_FE_AD_REG_FDB_IN__A 0xC10012 |
| be9297d1 | 657 | #define B_FE_AD_REG_PD__A 0xC10013 |
| be9297d1 | 658 | #define B_FE_AD_REG_INVEXT__A 0xC10014 |
| be9297d1 | 659 | #define B_FE_AD_REG_CLKNEG__A 0xC10015 |
| be9297d1 | 660 | #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 |
| be9297d1 | 661 | #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 |
| be9297d1 MCC |
662 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 |
| 663 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 | |
| 664 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 | |
| be9297d1 MCC |
665 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 |
| 666 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 | |
| be9297d1 MCC |
667 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 |
| 668 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 | |
| 669 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 | |
| be9297d1 MCC |
670 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 |
| 671 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 | |
| 672 | #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 | |
| be9297d1 | 673 | #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 |
| be9297d1 MCC |
674 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 |
| 675 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 | |
| 676 | #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 | |
| be9297d1 | 677 | #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 |
| be9297d1 MCC |
678 | #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 |
| 679 | #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 | |
| be9297d1 | 680 | #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 |
| be9297d1 MCC |
681 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 |
| 682 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 | |
| 683 | #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 | |
| 935c630c | 684 | #define B_FE_AG_REG_AG_PWD__A 0xC20015 |
| be9297d1 MCC |
685 | #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 |
| 686 | #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 | |
| 687 | #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 | |
| be9297d1 | 688 | #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 |
| be9297d1 | 689 | #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 |
| be9297d1 | 690 | #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A |
| be9297d1 | 691 | #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B |
| be9297d1 | 692 | #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 |
| be9297d1 | 693 | #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 |
| be9297d1 | 694 | #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 |
| be9297d1 | 695 | #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF |
| be9297d1 | 696 | #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 |
| be9297d1 | 697 | #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 |
| be9297d1 | 698 | #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 |
| be9297d1 | 699 | #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 |
| be9297d1 | 700 | #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A |
| be9297d1 | 701 | #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B |
| be9297d1 | 702 | #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C |
| be9297d1 | 703 | #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D |
| be9297d1 | 704 | #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E |
| be9297d1 | 705 | #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 |
| be9297d1 | 706 | #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF |
| be9297d1 | 707 | #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 |
| be9297d1 | 708 | #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 |
| be9297d1 | 709 | #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 |
| be9297d1 | 710 | #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 |
| be9297d1 | 711 | #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 |
| be9297d1 | 712 | #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF |
| be9297d1 | 713 | #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 |
| be9297d1 | 714 | #define B_FE_AG_REG_IND_WIN__A 0xC2003C |
| be9297d1 | 715 | #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D |
| be9297d1 | 716 | #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E |
| be9297d1 | 717 | #define B_FE_AG_REG_IND_DEL__A 0xC2003F |
| be9297d1 | 718 | #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 |
| be9297d1 | 719 | #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 |
| be9297d1 | 720 | #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 |
| be9297d1 | 721 | #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 |
| be9297d1 | 722 | #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 |
| be9297d1 | 723 | #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 |
| be9297d1 | 724 | #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 |
| be9297d1 | 725 | #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 |
| be9297d1 | 726 | #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 |
| be9297d1 | 727 | #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 |
| be9297d1 | 728 | #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A |
| be9297d1 | 729 | #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B |
| be9297d1 | 730 | #define B_FE_AG_REG_PDC_MAX__A 0xC2004C |
| be9297d1 | 731 | #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D |
| be9297d1 | 732 | #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E |
| be9297d1 | 733 | #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F |
| be9297d1 | 734 | #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 |
| be9297d1 | 735 | #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 |
| be9297d1 | 736 | #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F |
| be9297d1 | 737 | #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 |
| be9297d1 | 738 | #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 |
| be9297d1 | 739 | #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 |
| be9297d1 | 740 | #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 |
| be9297d1 | 741 | #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 |
| be9297d1 | 742 | #define B_FE_AG_REG_FGM_WRI__A 0xC20061 |
| be9297d1 | 743 | #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 |
| be9297d1 | 744 | #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 |
| be9297d1 | 745 | #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 |
| be9297d1 | 746 | #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 |
| be9297d1 | 747 | #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 |
| be9297d1 | 748 | #define B_FE_FD_REG_SCL__A 0xC40010 |
| be9297d1 | 749 | #define B_FE_FD_REG_MAX_LEV__A 0xC40011 |
| be9297d1 | 750 | #define B_FE_FD_REG_NR__A 0xC40012 |
| be9297d1 | 751 | #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 |
| be9297d1 | 752 | #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 |
| be9297d1 MCC |
753 | #define B_FE_IF_REG_INCR0__A 0xC50010 |
| 754 | #define B_FE_IF_REG_INCR0__W 16 | |
| 755 | #define B_FE_IF_REG_INCR0__M 0xFFFF | |
| be9297d1 | 756 | #define B_FE_IF_REG_INCR1__A 0xC50011 |
| be9297d1 | 757 | #define B_FE_IF_REG_INCR1__M 0xFF |
| be9297d1 | 758 | #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 |
| be9297d1 | 759 | #define B_FE_CF_REG_SCL__A 0xC60010 |
| be9297d1 | 760 | #define B_FE_CF_REG_MAX_LEV__A 0xC60011 |
| be9297d1 | 761 | #define B_FE_CF_REG_NR__A 0xC60012 |
| be9297d1 | 762 | #define B_FE_CF_REG_IMP_VAL__A 0xC60013 |
| be9297d1 | 763 | #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 |
| be9297d1 | 764 | #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 |
| be9297d1 | 765 | #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 |
| be9297d1 | 766 | #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 |
| be9297d1 | 767 | #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 |
| be9297d1 | 768 | #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 |
| be9297d1 | 769 | #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 |
| be9297d1 | 770 | #define B_FT_COMM_EXEC__A 0x1000000 |
| be9297d1 | 771 | #define B_FT_REG_COMM_EXEC__A 0x1010000 |
| be9297d1 | 772 | #define B_CP_COMM_EXEC__A 0x1400000 |
| be9297d1 | 773 | #define B_CP_REG_COMM_EXEC__A 0x1410000 |
| be9297d1 | 774 | #define B_CP_REG_INTERVAL__A 0x1410011 |
| be9297d1 | 775 | #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 |
| be9297d1 | 776 | #define B_CP_REG_BR_STR_DEL__A 0x1410024 |
| be9297d1 | 777 | #define B_CP_REG_RT_ANG_INC0__A 0x1410030 |
| be9297d1 | 778 | #define B_CP_REG_RT_ANG_INC1__A 0x1410031 |
| be9297d1 | 779 | #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 |
| be9297d1 | 780 | #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 |
| be9297d1 | 781 | #define B_CP_REG_AC_AVER_POW__A 0x1410041 |
| be9297d1 | 782 | #define B_CP_REG_AC_MAX_POW__A 0x1410042 |
| be9297d1 | 783 | #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 |
| be9297d1 | 784 | #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 |
| be9297d1 | 785 | #define B_CP_REG_AC_AMP_MODE__A 0x1410047 |
| be9297d1 | 786 | #define B_CP_REG_AC_AMP_FIX__A 0x1410048 |
| be9297d1 | 787 | #define B_CP_REG_AC_ANG_MODE__A 0x141004A |
| be9297d1 | 788 | #define B_CE_COMM_EXEC__A 0x1800000 |
| 935c630c | 789 | #define B_CE_REG_COMM_EXEC__A 0x1810000 |
| be9297d1 | 790 | #define B_CE_REG_TAPSET__A 0x1810011 |
| be9297d1 | 791 | #define B_CE_REG_AVG_POW__A 0x1810012 |
| be9297d1 | 792 | #define B_CE_REG_MAX_POW__A 0x1810013 |
| be9297d1 | 793 | #define B_CE_REG_ATT__A 0x1810014 |
| be9297d1 | 794 | #define B_CE_REG_NRED__A 0x1810015 |
| be9297d1 | 795 | #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 |
| be9297d1 | 796 | #define B_CE_REG_NE_TD_CAL__A 0x1810044 |
| be9297d1 | 797 | #define B_CE_REG_NE_MIXAVG__A 0x1810046 |
| be9297d1 | 798 | #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 |
| be9297d1 | 799 | #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 |
| be9297d1 | 800 | #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 |
| be9297d1 | 801 | #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 |
| be9297d1 | 802 | #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 |
| be9297d1 | 803 | #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 |
| be9297d1 | 804 | #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 |
| be9297d1 | 805 | #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 |
| be9297d1 | 806 | #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A |
| be9297d1 | 807 | #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 |
| be9297d1 | 808 | #define B_CE_REG_FI_SHT_INCR__A 0x1810090 |
| be9297d1 | 809 | #define B_CE_REG_FI_EXP_NORM__A 0x1810091 |
| be9297d1 | 810 | #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 |
| be9297d1 | 811 | #define B_CE_REG_IR_STARTPOS__A 0x18100A1 |
| be9297d1 | 812 | #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 |
| be9297d1 | 813 | #define B_CE_REG_FR_TREAL00__A 0x1820010 |
| be9297d1 | 814 | #define B_CE_REG_FR_TIMAG00__A 0x1820011 |
| be9297d1 | 815 | #define B_CE_REG_FR_TREAL01__A 0x1820012 |
| be9297d1 | 816 | #define B_CE_REG_FR_TIMAG01__A 0x1820013 |
| be9297d1 | 817 | #define B_CE_REG_FR_TREAL02__A 0x1820014 |
| be9297d1 | 818 | #define B_CE_REG_FR_TIMAG02__A 0x1820015 |
| be9297d1 | 819 | #define B_CE_REG_FR_TREAL03__A 0x1820016 |
| be9297d1 | 820 | #define B_CE_REG_FR_TIMAG03__A 0x1820017 |
| be9297d1 | 821 | #define B_CE_REG_FR_TREAL04__A 0x1820018 |
| be9297d1 | 822 | #define B_CE_REG_FR_TIMAG04__A 0x1820019 |
| be9297d1 | 823 | #define B_CE_REG_FR_TREAL05__A 0x182001A |
| be9297d1 | 824 | #define B_CE_REG_FR_TIMAG05__A 0x182001B |
| be9297d1 | 825 | #define B_CE_REG_FR_TREAL06__A 0x182001C |
| be9297d1 | 826 | #define B_CE_REG_FR_TIMAG06__A 0x182001D |
| be9297d1 | 827 | #define B_CE_REG_FR_TREAL07__A 0x182001E |
| be9297d1 | 828 | #define B_CE_REG_FR_TIMAG07__A 0x182001F |
| be9297d1 | 829 | #define B_CE_REG_FR_TREAL08__A 0x1820020 |
| be9297d1 | 830 | #define B_CE_REG_FR_TIMAG08__A 0x1820021 |
| be9297d1 | 831 | #define B_CE_REG_FR_TREAL09__A 0x1820022 |
| be9297d1 | 832 | #define B_CE_REG_FR_TIMAG09__A 0x1820023 |
| be9297d1 | 833 | #define B_CE_REG_FR_TREAL10__A 0x1820024 |
| be9297d1 | 834 | #define B_CE_REG_FR_TIMAG10__A 0x1820025 |
| be9297d1 | 835 | #define B_CE_REG_FR_TREAL11__A 0x1820026 |
| be9297d1 | 836 | #define B_CE_REG_FR_TIMAG11__A 0x1820027 |
| be9297d1 | 837 | #define B_CE_REG_FR_MID_TAP__A 0x1820028 |
| be9297d1 | 838 | #define B_CE_REG_FR_SQS_G00__A 0x1820029 |
| be9297d1 | 839 | #define B_CE_REG_FR_SQS_G01__A 0x182002A |
| be9297d1 | 840 | #define B_CE_REG_FR_SQS_G02__A 0x182002B |
| be9297d1 | 841 | #define B_CE_REG_FR_SQS_G03__A 0x182002C |
| be9297d1 | 842 | #define B_CE_REG_FR_SQS_G04__A 0x182002D |
| be9297d1 | 843 | #define B_CE_REG_FR_SQS_G05__A 0x182002E |
| be9297d1 | 844 | #define B_CE_REG_FR_SQS_G06__A 0x182002F |
| be9297d1 | 845 | #define B_CE_REG_FR_SQS_G07__A 0x1820030 |
| be9297d1 | 846 | #define B_CE_REG_FR_SQS_G08__A 0x1820031 |
| be9297d1 | 847 | #define B_CE_REG_FR_SQS_G09__A 0x1820032 |
| be9297d1 | 848 | #define B_CE_REG_FR_SQS_G10__A 0x1820033 |
| be9297d1 | 849 | #define B_CE_REG_FR_SQS_G11__A 0x1820034 |
| be9297d1 | 850 | #define B_CE_REG_FR_SQS_G12__A 0x1820035 |
| be9297d1 | 851 | #define B_CE_REG_FR_RIO_G00__A 0x1820036 |
| be9297d1 | 852 | #define B_CE_REG_FR_RIO_G01__A 0x1820037 |
| be9297d1 | 853 | #define B_CE_REG_FR_RIO_G02__A 0x1820038 |
| be9297d1 | 854 | #define B_CE_REG_FR_RIO_G03__A 0x1820039 |
| be9297d1 | 855 | #define B_CE_REG_FR_RIO_G04__A 0x182003A |
| be9297d1 | 856 | #define B_CE_REG_FR_RIO_G05__A 0x182003B |
| be9297d1 | 857 | #define B_CE_REG_FR_RIO_G06__A 0x182003C |
| be9297d1 | 858 | #define B_CE_REG_FR_RIO_G07__A 0x182003D |
| be9297d1 | 859 | #define B_CE_REG_FR_RIO_G08__A 0x182003E |
| be9297d1 | 860 | #define B_CE_REG_FR_RIO_G09__A 0x182003F |
| be9297d1 | 861 | #define B_CE_REG_FR_RIO_G10__A 0x1820040 |
| be9297d1 | 862 | #define B_CE_REG_FR_MODE__A 0x1820041 |
| be9297d1 | 863 | #define B_CE_REG_FR_SQS_TRH__A 0x1820042 |
| be9297d1 | 864 | #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 |
| be9297d1 | 865 | #define B_CE_REG_FR_BYPASS__A 0x1820044 |
| be9297d1 | 866 | #define B_CE_REG_FR_PM_SET__A 0x1820045 |
| be9297d1 | 867 | #define B_CE_REG_FR_ERR_SH__A 0x1820046 |
| be9297d1 | 868 | #define B_CE_REG_FR_MAN_SH__A 0x1820047 |
| be9297d1 | 869 | #define B_CE_REG_FR_TAP_SH__A 0x1820048 |
| be9297d1 | 870 | #define B_EQ_COMM_EXEC__A 0x1C00000 |
| be9297d1 | 871 | #define B_EQ_REG_COMM_EXEC__A 0x1C10000 |
| be9297d1 | 872 | #define B_EQ_REG_COMM_MB__A 0x1C10002 |
| be9297d1 | 873 | #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 |
| be9297d1 | 874 | #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 |
| be9297d1 | 875 | #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 |
| be9297d1 | 876 | #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A |
| be9297d1 | 877 | #define B_EQ_REG_SN_OFFSET__A 0x1C1002B |
| be9297d1 | 878 | #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 |
| be9297d1 | 879 | #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 |
| be9297d1 | 880 | #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 |
| be9297d1 MCC |
881 | #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 |
| 882 | #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 | |
| be9297d1 MCC |
883 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 |
| 884 | #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 | |
| be9297d1 MCC |
885 | #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 |
| 886 | #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 | |
| be9297d1 | 887 | #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 |
| be9297d1 | 888 | #define B_EQ_REG_OT_CONST__A 0x1C10046 |
| 935c630c MCC |
889 | #define B_EQ_REG_OT_ALPHA__A 0x1C10047 |
| 890 | #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 | |
| 891 | #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 | |
| 892 | #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A | |
| 893 | #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B | |
| be9297d1 | 894 | #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 |
| be9297d1 | 895 | #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 |
| be9297d1 | 896 | #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 |
| be9297d1 | 897 | #define B_EC_SB_REG_TR_MODE__A 0x2010010 |
| be9297d1 MCC |
898 | #define B_EC_SB_REG_TR_MODE_8K 0x0 |
| 899 | #define B_EC_SB_REG_TR_MODE_2K 0x1 | |
| be9297d1 | 900 | #define B_EC_SB_REG_CONST__A 0x2010011 |
| be9297d1 MCC |
901 | #define B_EC_SB_REG_CONST_QPSK 0x0 |
| 902 | #define B_EC_SB_REG_CONST_16QAM 0x1 | |
| 903 | #define B_EC_SB_REG_CONST_64QAM 0x2 | |
| be9297d1 | 904 | #define B_EC_SB_REG_ALPHA__A 0x2010012 |
| be9297d1 | 905 | #define B_EC_SB_REG_PRIOR__A 0x2010013 |
| be9297d1 MCC |
906 | #define B_EC_SB_REG_PRIOR_HI 0x0 |
| 907 | #define B_EC_SB_REG_PRIOR_LO 0x1 | |
| be9297d1 | 908 | #define B_EC_SB_REG_CSI_HI__A 0x2010014 |
| be9297d1 | 909 | #define B_EC_SB_REG_CSI_LO__A 0x2010015 |
| be9297d1 | 910 | #define B_EC_SB_REG_SMB_TGL__A 0x2010016 |
| be9297d1 | 911 | #define B_EC_SB_REG_SNR_HI__A 0x2010017 |
| be9297d1 | 912 | #define B_EC_SB_REG_SNR_MID__A 0x2010018 |
| be9297d1 | 913 | #define B_EC_SB_REG_SNR_LO__A 0x2010019 |
| be9297d1 | 914 | #define B_EC_SB_REG_SCALE_MSB__A 0x201001A |
| be9297d1 | 915 | #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B |
| be9297d1 | 916 | #define B_EC_SB_REG_SCALE_LSB__A 0x201001C |
| be9297d1 | 917 | #define B_EC_SB_REG_CSI_OFS0__A 0x201001D |
| be9297d1 | 918 | #define B_EC_SB_REG_CSI_OFS1__A 0x201001E |
| be9297d1 | 919 | #define B_EC_SB_REG_CSI_OFS2__A 0x201001F |
| be9297d1 | 920 | #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 |
| be9297d1 | 921 | #define B_EC_VD_REG_FORCE__A 0x2090010 |
| be9297d1 | 922 | #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 |
| be9297d1 MCC |
923 | #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 |
| 924 | #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 | |
| 925 | #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 | |
| 926 | #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 | |
| 927 | #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 | |
| be9297d1 | 928 | #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 |
| be9297d1 | 929 | #define B_EC_VD_REG_RLK_ENA__A 0x2090014 |
| be9297d1 | 930 | #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 |
| be9297d1 | 931 | #define B_EC_OD_REG_SYNC__A 0x2110664 |
| be9297d1 | 932 | #define B_EC_OD_DEINT_RAM__A 0x2120000 |
| be9297d1 | 933 | #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 |
| be9297d1 | 934 | #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 |
| be9297d1 | 935 | #define B_EC_RS_REG_VAL__A 0x2130011 |
| be9297d1 | 936 | #define B_EC_RS_REG_VAL_PCK 0x1 |
| be9297d1 | 937 | #define B_EC_RS_EC_RAM__A 0x2140000 |
| be9297d1 | 938 | #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 |
| be9297d1 MCC |
939 | #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 |
| 940 | #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 | |
| be9297d1 | 941 | #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 |
| be9297d1 | 942 | #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 |
| be9297d1 MCC |
943 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 |
| 944 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 | |
| 945 | #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 | |
| be9297d1 MCC |
946 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 |
| 947 | #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 | |
| be9297d1 | 948 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 |
| be9297d1 | 949 | #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 |
| be9297d1 | 950 | #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 |
| be9297d1 | 951 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 |
| be9297d1 MCC |
952 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 |
| 953 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 | |
| 954 | #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 | |
| be9297d1 | 955 | #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 |
| be9297d1 | 956 | #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF |
| be9297d1 | 957 | #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 |
| be9297d1 | 958 | #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 |
| be9297d1 | 959 | #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 |
| be9297d1 | 960 | #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 |
| be9297d1 | 961 | #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D |
| be9297d1 | 962 | #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E |
| be9297d1 | 963 | #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F |
| be9297d1 | 964 | #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 |
| be9297d1 | 965 | #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 |
| be9297d1 | 966 | #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 |
| be9297d1 | 967 | #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 |
| be9297d1 | 968 | #define B_EC_OC_REG_RCN_MODE__A 0x2150027 |
| be9297d1 | 969 | #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 |
| be9297d1 | 970 | #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 |
| be9297d1 | 971 | #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A |
| be9297d1 | 972 | #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B |
| be9297d1 | 973 | #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C |
| be9297d1 | 974 | #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D |
| be9297d1 | 975 | #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 |
| be9297d1 | 976 | #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 |
| be9297d1 | 977 | #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 |
| be9297d1 | 978 | #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 |
| be9297d1 | 979 | #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 |
| be9297d1 MCC |
980 | #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF |
| 981 | #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 | |
| be9297d1 | 982 | #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 |
| be9297d1 | 983 | #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 |
| be9297d1 | 984 | #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 |
| be9297d1 | 985 | #define B_EC_OC_REG_DTO_PER__A 0x2150048 |
| be9297d1 | 986 | #define B_EC_OC_REG_DTO_BUR__A 0x2150049 |
| be9297d1 | 987 | #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A |
| be9297d1 | 988 | #define B_CC_REG_OSC_MODE__A 0x2410010 |
| be9297d1 | 989 | #define B_CC_REG_OSC_MODE_M20 0x1 |
| be9297d1 | 990 | #define B_CC_REG_PLL_MODE__A 0x2410011 |
| be9297d1 | 991 | #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 |
| be9297d1 | 992 | #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 |
| be9297d1 | 993 | #define B_CC_REG_REF_DIVIDE__A 0x2410012 |
| be9297d1 | 994 | #define B_CC_REG_PWD_MODE__A 0x2410015 |
| be9297d1 | 995 | #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 |
| be9297d1 | 996 | #define B_CC_REG_UPDATE__A 0x2410017 |
| be9297d1 | 997 | #define B_CC_REG_UPDATE_KEY 0x3973 |
| be9297d1 | 998 | #define B_CC_REG_JTAGID_L__A 0x2410019 |
| be9297d1 | 999 | #define B_CC_REG_DIVERSITY__A 0x241001B |
| be9297d1 | 1000 | #define B_LC_COMM_EXEC__A 0x2800000 |
| be9297d1 | 1001 | #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C |
| be9297d1 | 1002 | #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A |
| be9297d1 | 1003 | #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 |
| be9297d1 | 1004 | #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 |
| be9297d1 MCC |
1005 | #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 |
| 1006 | #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 | |
| be9297d1 | 1007 | #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 |
| be9297d1 | 1008 | #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 |
| be9297d1 MCC |
1009 | #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 |
| 1010 | #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 | |
| be9297d1 | 1011 | #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 |
| 126f1e61 | 1012 | |
| 126f1e61 | 1013 | #endif |