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Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next
[mirror_ubuntu-focal-kernel.git] / drivers / media / dvb-frontends / drxk_hard.c
CommitLineData
43dd07f7
RM		 1/*
2 * drxk_hard: DRX-K DVB-C/T demodulator driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
bcb63314
SA		 16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
43dd07f7
RM		 18 */
19
3a4398f5
MCC		 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
43dd07f7
RM		 22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/firmware.h>
28#include <linux/i2c.h>
20bfe7ae 29#include <linux/hardirq.h>
43dd07f7
RM		 30#include <asm/div64.h>
31
32#include "dvb_frontend.h"
33#include "drxk.h"
34#include "drxk_hard.h"
b5e9eb6f 35#include "dvb_math.h"
43dd07f7 36
cd7a67a4
MCC		 37static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
38static int power_down_qam(struct drxk_state *state);
39static int set_dvbt_standard(struct drxk_state *state,
40 enum operation_mode o_mode);
41static int set_qam_standard(struct drxk_state *state,
42 enum operation_mode o_mode);
43static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
44 s32 tuner_freq_offset);
45static int set_dvbt_standard(struct drxk_state *state,
46 enum operation_mode o_mode);
47static int dvbt_start(struct drxk_state *state);
48static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
49 s32 tuner_freq_offset);
50static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
51static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
52static int switch_antenna_to_qam(struct drxk_state *state);
53static int switch_antenna_to_dvbt(struct drxk_state *state);
54
55static bool is_dvbt(struct drxk_state *state)
43dd07f7 56{
cd7a67a4 57 return state->m_operation_mode == OM_DVBT;
43dd07f7
RM		 58}
59
cd7a67a4 60static bool is_qam(struct drxk_state *state)
43dd07f7 61{
cd7a67a4
MCC		 62 return state->m_operation_mode == OM_QAM_ITU_A ||
63 state->m_operation_mode == OM_QAM_ITU_B ||
64 state->m_operation_mode == OM_QAM_ITU_C;
43dd07f7
RM		 65}
66
43dd07f7
RM		 67#define NOA1ROM 0
68
43dd07f7
RM		 69#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
70#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
71
72#define DEFAULT_MER_83 165
73#define DEFAULT_MER_93 250
74
75#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
76#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
77#endif
78
79#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
80#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
81#endif
82
43dd07f7
RM		 83#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
84#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
85
86#ifndef DRXK_KI_RAGC_ATV
87#define DRXK_KI_RAGC_ATV 4
88#endif
89#ifndef DRXK_KI_IAGC_ATV
90#define DRXK_KI_IAGC_ATV 6
91#endif
92#ifndef DRXK_KI_DAGC_ATV
93#define DRXK_KI_DAGC_ATV 7
94#endif
95
96#ifndef DRXK_KI_RAGC_QAM
97#define DRXK_KI_RAGC_QAM 3
98#endif
99#ifndef DRXK_KI_IAGC_QAM
100#define DRXK_KI_IAGC_QAM 4
101#endif
102#ifndef DRXK_KI_DAGC_QAM
103#define DRXK_KI_DAGC_QAM 7
104#endif
105#ifndef DRXK_KI_RAGC_DVBT
106#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
107#endif
108#ifndef DRXK_KI_IAGC_DVBT
109#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
110#endif
111#ifndef DRXK_KI_DAGC_DVBT
112#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
113#endif
114
115#ifndef DRXK_AGC_DAC_OFFSET
116#define DRXK_AGC_DAC_OFFSET (0x800)
117#endif
118
119#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
120#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
121#endif
122
123#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
124#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
125#endif
126
127#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
128#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
129#endif
130
131#ifndef DRXK_QAM_SYMBOLRATE_MAX
132#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
133#endif
134
135#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
136#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
137#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
138#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
139#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
140#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
141#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
142#define DRXK_BL_ROM_OFFSET_UCODE 0
143
144#define DRXK_BLC_TIMEOUT 100
145
146#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
147#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
148
149#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
150
151#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
152#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
153#endif
154
155#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
156#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
157#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
158#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
159#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
160
2da67501
MCC		 161static unsigned int debug;
162module_param(debug, int, 0644);
163MODULE_PARM_DESC(debug, "enable debug messages");
164
52ee29fe
MCC		 165#define dprintk(level, fmt, arg...) do { \
166if (debug >= level) \
167 printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
2da67501
MCC		 168} while (0)
169
170
b01fbc10 171static inline u32 MulDiv32(u32 a, u32 b, u32 c)
43dd07f7
RM		 172{
173 u64 tmp64;
174
ebc7de22 175 tmp64 = (u64) a * (u64) b;
43dd07f7
RM		 176 do_div(tmp64, c);
177
178 return (u32) tmp64;
179}
180
ff38c216 181static inline u32 Frac28a(u32 a, u32 c)
43dd07f7
RM		 182{
183 int i = 0;
184 u32 Q1 = 0;
185 u32 R0 = 0;
186
ebc7de22 187 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
ab5060cd
MCC		 188 Q1 = a / c; /*
189 * integer part, only the 4 least significant
190 * bits will be visible in the result
191 */
43dd07f7
RM		 192
193 /* division using radix 16, 7 nibbles in the result */
194 for (i = 0; i < 7; i++) {
195 Q1 = (Q1 << 4) | (R0 / c);
196 R0 = (R0 % c) << 4;
197 }
198 /* rounding */
199 if ((R0 >> 3) >= c)
200 Q1++;
201
202 return Q1;
203}
204
b5e9eb6f 205static inline u32 log10times100(u32 value)
43dd07f7 206{
b5e9eb6f 207 return (100L * intlog10(value)) >> 24;
43dd07f7
RM		 208}
209
34eb9751 210/***************************************************************************/
43dd07f7 211/* I2C **********************************************************************/
34eb9751 212/***************************************************************************/
43dd07f7 213
20bfe7ae
MCC		 214static int drxk_i2c_lock(struct drxk_state *state)
215{
216 i2c_lock_adapter(state->i2c);
217 state->drxk_i2c_exclusive_lock = true;
218
219 return 0;
220}
221
222static void drxk_i2c_unlock(struct drxk_state *state)
223{
224 if (!state->drxk_i2c_exclusive_lock)
225 return;
226
227 i2c_unlock_adapter(state->i2c);
228 state->drxk_i2c_exclusive_lock = false;
229}
230
2a5f6720
MCC		 231static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
232 unsigned len)
233{
20bfe7ae
MCC		 234 if (state->drxk_i2c_exclusive_lock)
235 return __i2c_transfer(state->i2c, msgs, len);
236 else
237 return i2c_transfer(state->i2c, msgs, len);
2a5f6720
MCC		 238}
239
240static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
43dd07f7 241{
ebc7de22
OE		 242 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
243 .buf = val, .len = 1}
244 };
be44eb28 245
2a5f6720 246 return drxk_i2c_transfer(state, msgs, 1);
43dd07f7
RM		 247}
248
2a5f6720 249static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
43dd07f7 250{
be44eb28 251 int status;
ebc7de22
OE		 252 struct i2c_msg msg = {
253 .addr = adr, .flags = 0, .buf = data, .len = len };
43dd07f7 254
2da67501
MCC		 255 dprintk(3, ":");
256 if (debug > 2) {
257 int i;
258 for (i = 0; i < len; i++)
0fb220f2
MCC		 259 pr_cont(" %02x", data[i]);
260 pr_cont("\n");
2da67501 261 }
2a5f6720 262 status = drxk_i2c_transfer(state, &msg, 1);
be44eb28
MCC		 263 if (status >= 0 && status != 1)
264 status = -EIO;
265
266 if (status < 0)
3a4398f5 267 pr_err("i2c write error at addr 0x%02x\n", adr);
be44eb28
MCC		 268
269 return status;
43dd07f7
RM		 270}
271
2a5f6720 272static int i2c_read(struct drxk_state *state,
43dd07f7
RM		 273 u8 adr, u8 *msg, int len, u8 *answ, int alen)
274{
be44eb28 275 int status;
e4f4f875
MCC		 276 struct i2c_msg msgs[2] = {
277 {.addr = adr, .flags = 0,
ebc7de22 278 .buf = msg, .len = len},
e4f4f875
MCC		 279 {.addr = adr, .flags = I2C_M_RD,
280 .buf = answ, .len = alen}
ebc7de22 281 };
f07a0bc1 282
2a5f6720 283 status = drxk_i2c_transfer(state, msgs, 2);
be44eb28 284 if (status != 2) {
2da67501 285 if (debug > 2)
0fb220f2 286 pr_cont(": ERROR!\n");
be44eb28
MCC		 287 if (status >= 0)
288 status = -EIO;
2da67501 289
3a4398f5 290 pr_err("i2c read error at addr 0x%02x\n", adr);
be44eb28 291 return status;
43dd07f7 292 }
2da67501
MCC		 293 if (debug > 2) {
294 int i;
0d3e6fe7 295 dprintk(2, ": read from");
2da67501 296 for (i = 0; i < len; i++)
0fb220f2
MCC		 297 pr_cont(" %02x", msg[i]);
298 pr_cont(", value = ");
f07a0bc1 299 for (i = 0; i < alen; i++)
0fb220f2
MCC		 300 pr_cont(" %02x", answ[i]);
301 pr_cont("\n");
2da67501 302 }
43dd07f7
RM		 303 return 0;
304}
305
5e66b878 306static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
43dd07f7 307{
be44eb28 308 int status;
ebc7de22 309 u8 adr = state->demod_address, mm1[4], mm2[2], len;
e076c92e
MCC		 310
311 if (state->single_master)
312 flags |= 0xC0;
313
43dd07f7
RM		 314 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
315 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
316 mm1[1] = ((reg >> 16) & 0xFF);
317 mm1[2] = ((reg >> 24) & 0xFF) | flags;
318 mm1[3] = ((reg >> 7) & 0xFF);
319 len = 4;
320 } else {
321 mm1[0] = ((reg << 1) & 0xFF);
322 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
323 len = 2;
324 }
2da67501 325 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
2a5f6720 326 status = i2c_read(state, adr, mm1, len, mm2, 2);
be44eb28
MCC		 327 if (status < 0)
328 return status;
43dd07f7
RM		 329 if (data)
330 *data = mm2[0] | (mm2[1] << 8);
2da67501 331
43dd07f7
RM		 332 return 0;
333}
334
5e66b878 335static int read16(struct drxk_state *state, u32 reg, u16 *data)
43dd07f7 336{
5e66b878 337 return read16_flags(state, reg, data, 0);
43dd07f7
RM		 338}
339
5e66b878 340static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
43dd07f7 341{
be44eb28 342 int status;
43dd07f7 343 u8 adr = state->demod_address, mm1[4], mm2[4], len;
e076c92e
MCC		 344
345 if (state->single_master)
346 flags |= 0xC0;
347
43dd07f7
RM		 348 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
349 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
350 mm1[1] = ((reg >> 16) & 0xFF);
351 mm1[2] = ((reg >> 24) & 0xFF) | flags;
352 mm1[3] = ((reg >> 7) & 0xFF);
353 len = 4;
354 } else {
355 mm1[0] = ((reg << 1) & 0xFF);
356 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
357 len = 2;
358 }
2da67501 359 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
2a5f6720 360 status = i2c_read(state, adr, mm1, len, mm2, 4);
be44eb28
MCC		 361 if (status < 0)
362 return status;
43dd07f7
RM		 363 if (data)
364 *data = mm2[0] | (mm2[1] << 8) |
ebc7de22 365 (mm2[2] << 16) | (mm2[3] << 24);
2da67501 366
43dd07f7
RM		 367 return 0;
368}
369
5e66b878
MCC		 370static int read32(struct drxk_state *state, u32 reg, u32 *data)
371{
372 return read32_flags(state, reg, data, 0);
373}
374
375static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
43dd07f7
RM		 376{
377 u8 adr = state->demod_address, mm[6], len;
e076c92e
MCC		 378
379 if (state->single_master)
380 flags |= 0xC0;
43dd07f7
RM		 381 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
382 mm[0] = (((reg << 1) & 0xFF) | 0x01);
383 mm[1] = ((reg >> 16) & 0xFF);
384 mm[2] = ((reg >> 24) & 0xFF) | flags;
385 mm[3] = ((reg >> 7) & 0xFF);
386 len = 4;
387 } else {
388 mm[0] = ((reg << 1) & 0xFF);
389 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
390 len = 2;
391 }
392 mm[len] = data & 0xff;
ebc7de22 393 mm[len + 1] = (data >> 8) & 0xff;
2da67501
MCC		 394
395 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
2a5f6720 396 return i2c_write(state, adr, mm, len + 2);
43dd07f7
RM		 397}
398
5e66b878 399static int write16(struct drxk_state *state, u32 reg, u16 data)
43dd07f7 400{
5e66b878 401 return write16_flags(state, reg, data, 0);
43dd07f7
RM		 402}
403
5e66b878 404static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
43dd07f7
RM		 405{
406 u8 adr = state->demod_address, mm[8], len;
e076c92e
MCC		 407
408 if (state->single_master)
409 flags |= 0xC0;
43dd07f7
RM		 410 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
411 mm[0] = (((reg << 1) & 0xFF) | 0x01);
412 mm[1] = ((reg >> 16) & 0xFF);
413 mm[2] = ((reg >> 24) & 0xFF) | flags;
414 mm[3] = ((reg >> 7) & 0xFF);
415 len = 4;
416 } else {
417 mm[0] = ((reg << 1) & 0xFF);
418 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
419 len = 2;
420 }
421 mm[len] = data & 0xff;
ebc7de22
OE		 422 mm[len + 1] = (data >> 8) & 0xff;
423 mm[len + 2] = (data >> 16) & 0xff;
424 mm[len + 3] = (data >> 24) & 0xff;
2da67501 425 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
be44eb28 426
2a5f6720 427 return i2c_write(state, adr, mm, len + 4);
43dd07f7
RM		 428}
429
5e66b878
MCC		 430static int write32(struct drxk_state *state, u32 reg, u32 data)
431{
432 return write32_flags(state, reg, data, 0);
433}
434
cd7a67a4
MCC		 435static int write_block(struct drxk_state *state, u32 address,
436 const int block_size, const u8 p_block[])
43dd07f7 437{
cd7a67a4
MCC		 438 int status = 0, blk_size = block_size;
439 u8 flags = 0;
e076c92e
MCC		 440
441 if (state->single_master)
cd7a67a4
MCC		 442 flags |= 0xC0;
443
444 while (blk_size > 0) {
445 int chunk = blk_size > state->m_chunk_size ?
446 state->m_chunk_size : blk_size;
447 u8 *adr_buf = &state->chunk[0];
448 u32 adr_length = 0;
449
450 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
451 adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
452 adr_buf[1] = ((address >> 16) & 0xFF);
453 adr_buf[2] = ((address >> 24) & 0xFF);
454 adr_buf[3] = ((address >> 7) & 0xFF);
455 adr_buf[2] |= flags;
456 adr_length = 4;
457 if (chunk == state->m_chunk_size)
458 chunk -= 2;
ebc7de22 459 } else {
cd7a67a4
MCC		 460 adr_buf[0] = ((address << 1) & 0xFF);
461 adr_buf[1] = (((address >> 16) & 0x0F) |
462 ((address >> 18) & 0xF0));
463 adr_length = 2;
43dd07f7 464 }
cd7a67a4
MCC		 465 memcpy(&state->chunk[adr_length], p_block, chunk);
466 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
2da67501
MCC		 467 if (debug > 1) {
468 int i;
cd7a67a4
MCC		 469 if (p_block)
470 for (i = 0; i < chunk; i++)
0fb220f2
MCC		 471 pr_cont(" %02x", p_block[i]);
472 pr_cont("\n");
2da67501 473 }
2a5f6720 474 status = i2c_write(state, state->demod_address,
cd7a67a4 475 &state->chunk[0], chunk + adr_length);
ebc7de22 476 if (status < 0) {
3a4398f5 477 pr_err("%s: i2c write error at addr 0x%02x\n",
cd7a67a4 478 __func__, address);
43dd07f7
RM		 479 break;
480 }
cd7a67a4
MCC		 481 p_block += chunk;
482 address += (chunk >> 1);
483 blk_size -= chunk;
43dd07f7 484 }
ebc7de22 485 return status;
43dd07f7
RM		 486}
487
488#ifndef DRXK_MAX_RETRIES_POWERUP
489#define DRXK_MAX_RETRIES_POWERUP 20
490#endif
491
cd7a67a4 492static int power_up_device(struct drxk_state *state)
43dd07f7
RM		 493{
494 int status;
495 u8 data = 0;
cd7a67a4 496 u16 retry_count = 0;
43dd07f7 497
2da67501
MCC		 498 dprintk(1, "\n");
499
2a5f6720 500 status = i2c_read1(state, state->demod_address, &data);
be44eb28 501 if (status < 0) {
43dd07f7
RM		 502 do {
503 data = 0;
2a5f6720 504 status = i2c_write(state, state->demod_address,
be44eb28 505 &data, 1);
b72852ba 506 usleep_range(10000, 11000);
cd7a67a4 507 retry_count++;
be44eb28
MCC		 508 if (status < 0)
509 continue;
2a5f6720 510 status = i2c_read1(state, state->demod_address,
be44eb28
MCC		 511 &data);
512 } while (status < 0 &&
cd7a67a4
MCC		 513 (retry_count < DRXK_MAX_RETRIES_POWERUP));
514 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
be44eb28
MCC		 515 goto error;
516 }
517
518 /* Make sure all clk domains are active */
519 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
520 if (status < 0)
521 goto error;
522 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
523 if (status < 0)
524 goto error;
525 /* Enable pll lock tests */
526 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
527 if (status < 0)
528 goto error;
529
cd7a67a4 530 state->m_current_power_mode = DRX_POWER_UP;
be44eb28
MCC		 531
532error:
533 if (status < 0)
3a4398f5 534 pr_err("Error %d on %s\n", status, __func__);
be44eb28 535
43dd07f7
RM		 536 return status;
537}
538
539
540static int init_state(struct drxk_state *state)
541{
147e110b 542 /*
5a13e40b 543 * FIXME: most (all?) of the values below should be moved into
147e110b
MCC		 544 * struct drxk_config, as they are probably board-specific
545 */
cd7a67a4
MCC		 546 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
547 u32 ul_vsb_if_agc_output_level = 0;
548 u32 ul_vsb_if_agc_min_level = 0;
549 u32 ul_vsb_if_agc_max_level = 0x7FFF;
550 u32 ul_vsb_if_agc_speed = 3;
551
552 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
553 u32 ul_vsb_rf_agc_output_level = 0;
554 u32 ul_vsb_rf_agc_min_level = 0;
555 u32 ul_vsb_rf_agc_max_level = 0x7FFF;
556 u32 ul_vsb_rf_agc_speed = 3;
557 u32 ul_vsb_rf_agc_top = 9500;
558 u32 ul_vsb_rf_agc_cut_off_current = 4000;
559
560 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
561 u32 ul_atv_if_agc_output_level = 0;
562 u32 ul_atv_if_agc_min_level = 0;
563 u32 ul_atv_if_agc_max_level = 0;
564 u32 ul_atv_if_agc_speed = 3;
565
566 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
567 u32 ul_atv_rf_agc_output_level = 0;
568 u32 ul_atv_rf_agc_min_level = 0;
569 u32 ul_atv_rf_agc_max_level = 0;
570 u32 ul_atv_rf_agc_top = 9500;
571 u32 ul_atv_rf_agc_cut_off_current = 4000;
572 u32 ul_atv_rf_agc_speed = 3;
43dd07f7
RM		 573
574 u32 ulQual83 = DEFAULT_MER_83;
575 u32 ulQual93 = DEFAULT_MER_93;
576
cd7a67a4
MCC		 577 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
578 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
43dd07f7
RM		 579
580 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
581 /* io_pad_cfg_mode output mode is drive always */
582 /* io_pad_cfg_drive is set to power 2 (23 mA) */
cd7a67a4
MCC		 583 u32 ul_gpio_cfg = 0x0113;
584 u32 ul_invert_ts_clock = 0;
585 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
586 u32 ul_dvbt_bitrate = 50000000;
587 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
43dd07f7 588
cd7a67a4 589 u32 ul_insert_rs_byte = 0;
43dd07f7 590
cd7a67a4
MCC		 591 u32 ul_rf_mirror = 1;
592 u32 ul_power_down = 0;
43dd07f7 593
2da67501
MCC		 594 dprintk(1, "\n");
595
cd7a67a4
MCC		 596 state->m_has_lna = false;
597 state->m_has_dvbt = false;
598 state->m_has_dvbc = false;
599 state->m_has_atv = false;
600 state->m_has_oob = false;
601 state->m_has_audio = false;
43dd07f7 602
cd7a67a4
MCC		 603 if (!state->m_chunk_size)
604 state->m_chunk_size = 124;
43dd07f7 605
cd7a67a4
MCC		 606 state->m_osc_clock_freq = 0;
607 state->m_smart_ant_inverted = false;
608 state->m_b_p_down_open_bridge = false;
43dd07f7
RM		 609
610 /* real system clock frequency in kHz */
cd7a67a4 611 state->m_sys_clock_freq = 151875;
43dd07f7
RM		 612 /* Timing div, 250ns/Psys */
613 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
cd7a67a4 614 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
43dd07f7
RM		 615 HI_I2C_DELAY) / 1000;
616 /* Clipping */
cd7a67a4
MCC		 617 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
618 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
619 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
43dd07f7 620 /* port/bridge/power down ctrl */
cd7a67a4 621 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
43dd07f7 622
cd7a67a4 623 state->m_b_power_down = (ul_power_down != 0);
43dd07f7 624
cd7a67a4 625 state->m_drxk_a3_patch_code = false;
43dd07f7
RM		 626
627 /* Init AGC and PGA parameters */
628 /* VSB IF */
949dd08d
MCC		 629 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
630 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
631 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
632 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
633 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
cd7a67a4 634 state->m_vsb_pga_cfg = 140;
43dd07f7
RM		 635
636 /* VSB RF */
949dd08d
MCC		 637 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
638 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
639 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
640 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
641 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
642 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
643 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
cd7a67a4
MCC		 644 state->m_vsb_pre_saw_cfg.reference = 0x07;
645 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
43dd07f7
RM		 646
647 state->m_Quality83percent = DEFAULT_MER_83;
648 state->m_Quality93percent = DEFAULT_MER_93;
649 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
650 state->m_Quality83percent = ulQual83;
651 state->m_Quality93percent = ulQual93;
652 }
653
654 /* ATV IF */
949dd08d
MCC		 655 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
656 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
657 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
658 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
659 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
43dd07f7
RM		 660
661 /* ATV RF */
949dd08d
MCC		 662 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
663 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
664 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
665 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
666 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
667 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
668 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
cd7a67a4
MCC		 669 state->m_atv_pre_saw_cfg.reference = 0x04;
670 state->m_atv_pre_saw_cfg.use_pre_saw = true;
43dd07f7
RM		 671
672
673 /* DVBT RF */
cd7a67a4
MCC		 674 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
675 state->m_dvbt_rf_agc_cfg.output_level = 0;
676 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
677 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
678 state->m_dvbt_rf_agc_cfg.top = 0x2100;
679 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
680 state->m_dvbt_rf_agc_cfg.speed = 1;
43dd07f7
RM		 681
682
683 /* DVBT IF */
cd7a67a4
MCC		 684 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
685 state->m_dvbt_if_agc_cfg.output_level = 0;
686 state->m_dvbt_if_agc_cfg.min_output_level = 0;
687 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
688 state->m_dvbt_if_agc_cfg.top = 13424;
689 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
690 state->m_dvbt_if_agc_cfg.speed = 3;
691 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
692 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
ebc7de22 693 /* state->m_dvbtPgaCfg = 140; */
43dd07f7 694
cd7a67a4
MCC		 695 state->m_dvbt_pre_saw_cfg.reference = 4;
696 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
43dd07f7
RM		 697
698 /* QAM RF */
cd7a67a4
MCC		 699 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
700 state->m_qam_rf_agc_cfg.output_level = 0;
701 state->m_qam_rf_agc_cfg.min_output_level = 6023;
702 state->m_qam_rf_agc_cfg.max_output_level = 27000;
703 state->m_qam_rf_agc_cfg.top = 0x2380;
704 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
705 state->m_qam_rf_agc_cfg.speed = 3;
43dd07f7
RM		 706
707 /* QAM IF */
cd7a67a4
MCC		 708 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
709 state->m_qam_if_agc_cfg.output_level = 0;
710 state->m_qam_if_agc_cfg.min_output_level = 0;
711 state->m_qam_if_agc_cfg.max_output_level = 9000;
712 state->m_qam_if_agc_cfg.top = 0x0511;
713 state->m_qam_if_agc_cfg.cut_off_current = 0;
714 state->m_qam_if_agc_cfg.speed = 3;
715 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
716 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
717
718 state->m_qam_pga_cfg = 140;
719 state->m_qam_pre_saw_cfg.reference = 4;
720 state->m_qam_pre_saw_cfg.use_pre_saw = false;
721
722 state->m_operation_mode = OM_NONE;
723 state->m_drxk_state = DRXK_UNINITIALIZED;
43dd07f7
RM		 724
725 /* MPEG output configuration */
cd7a67a4
MCC		 726 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */
727 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
728 state->m_invert_data = false; /* If TRUE; invert DATA signals */
729 state->m_invert_err = false; /* If TRUE; invert ERR signal */
730 state->m_invert_str = false; /* If TRUE; invert STR signals */
731 state->m_invert_val = false; /* If TRUE; invert VAL signals */
732 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
67f04617 733
43dd07f7
RM		 734 /* If TRUE; static MPEG clockrate will be used;
735 otherwise clockrate will adapt to the bitrate of the TS */
736
cd7a67a4
MCC		 737 state->m_dvbt_bitrate = ul_dvbt_bitrate;
738 state->m_dvbc_bitrate = ul_dvbc_bitrate;
43dd07f7 739
cd7a67a4 740 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
43dd07f7
RM		 741
742 /* Maximum bitrate in b/s in case static clockrate is selected */
cd7a67a4
MCC		 743 state->m_mpeg_ts_static_bitrate = 19392658;
744 state->m_disable_te_ihandling = false;
43dd07f7 745
cd7a67a4
MCC		 746 if (ul_insert_rs_byte)
747 state->m_insert_rs_byte = true;
43dd07f7 748
cd7a67a4
MCC		 749 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
750 if (ul_mpeg_lock_time_out < 10000)
751 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
752 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
753 if (ul_demod_lock_time_out < 10000)
754 state->m_demod_lock_time_out = ul_demod_lock_time_out;
43dd07f7 755
ebc7de22 756 /* QAM defaults */
cd7a67a4
MCC		 757 state->m_constellation = DRX_CONSTELLATION_AUTO;
758 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
759 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
760 state->m_fec_rs_prescale = 1;
43dd07f7 761
cd7a67a4
MCC		 762 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
763 state->m_agcfast_clip_ctrl_delay = 0;
43dd07f7 764
949dd08d 765 state->m_gpio_cfg = ul_gpio_cfg;
43dd07f7 766
cd7a67a4
MCC		 767 state->m_b_power_down = false;
768 state->m_current_power_mode = DRX_POWER_DOWN;
43dd07f7 769
cd7a67a4
MCC		 770 state->m_rfmirror = (ul_rf_mirror == 0);
771 state->m_if_agc_pol = false;
43dd07f7
RM		 772 return 0;
773}
774
cd7a67a4 775static int drxx_open(struct drxk_state *state)
43dd07f7
RM		 776{
777 int status = 0;
778 u32 jtag = 0;
779 u16 bid = 0;
780 u16 key = 0;
781
2da67501 782 dprintk(1, "\n");
be44eb28 783 /* stop lock indicator process */
ab5060cd
MCC		 784 status = write16(state, SCU_RAM_GPIO__A,
785 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
be44eb28
MCC		 786 if (status < 0)
787 goto error;
788 /* Check device id */
789 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
790 if (status < 0)
791 goto error;
792 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
793 if (status < 0)
794 goto error;
795 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
796 if (status < 0)
797 goto error;
798 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
799 if (status < 0)
800 goto error;
801 status = write16(state, SIO_TOP_COMM_KEY__A, key);
802error:
803 if (status < 0)
3a4398f5 804 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 805 return status;
806}
807
cd7a67a4 808static int get_device_capabilities(struct drxk_state *state)
43dd07f7 809{
cd7a67a4
MCC		 810 u16 sio_pdr_ohw_cfg = 0;
811 u32 sio_top_jtagid_lo = 0;
43dd07f7 812 int status;
9c6e1828 813 const char *spin = "";
43dd07f7 814
2da67501 815 dprintk(1, "\n");
43dd07f7 816
be44eb28
MCC		 817 /* driver 0.9.0 */
818 /* stop lock indicator process */
ab5060cd
MCC		 819 status = write16(state, SCU_RAM_GPIO__A,
820 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
be44eb28
MCC		 821 if (status < 0)
822 goto error;
8418366d 823 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
be44eb28
MCC		 824 if (status < 0)
825 goto error;
cd7a67a4 826 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
be44eb28
MCC		 827 if (status < 0)
828 goto error;
829 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
830 if (status < 0)
831 goto error;
43dd07f7 832
cd7a67a4 833 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
be44eb28
MCC		 834 case 0:
835 /* ignore (bypass ?) */
836 break;
837 case 1:
838 /* 27 MHz */
cd7a67a4 839 state->m_osc_clock_freq = 27000;
be44eb28
MCC		 840 break;
841 case 2:
842 /* 20.25 MHz */
cd7a67a4 843 state->m_osc_clock_freq = 20250;
be44eb28
MCC		 844 break;
845 case 3:
846 /* 4 MHz */
cd7a67a4 847 state->m_osc_clock_freq = 20250;
be44eb28
MCC		 848 break;
849 default:
3a4398f5 850 pr_err("Clock Frequency is unknown\n");
be44eb28
MCC		 851 return -EINVAL;
852 }
853 /*
854 Determine device capabilities
855 Based on pinning v14
856 */
cd7a67a4 857 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
be44eb28
MCC		 858 if (status < 0)
859 goto error;
0d3e6fe7 860
3a4398f5 861 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
0d3e6fe7 862
be44eb28 863 /* driver 0.9.0 */
cd7a67a4 864 switch ((sio_top_jtagid_lo >> 29) & 0xF) {
be44eb28 865 case 0:
cd7a67a4 866 state->m_device_spin = DRXK_SPIN_A1;
9c6e1828 867 spin = "A1";
be44eb28
MCC		 868 break;
869 case 2:
cd7a67a4 870 state->m_device_spin = DRXK_SPIN_A2;
9c6e1828 871 spin = "A2";
be44eb28
MCC		 872 break;
873 case 3:
cd7a67a4 874 state->m_device_spin = DRXK_SPIN_A3;
9c6e1828 875 spin = "A3";
be44eb28
MCC		 876 break;
877 default:
cd7a67a4 878 state->m_device_spin = DRXK_SPIN_UNKNOWN;
be44eb28 879 status = -EINVAL;
3a4398f5 880 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
be44eb28
MCC		 881 goto error2;
882 }
cd7a67a4 883 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
be44eb28
MCC		 884 case 0x13:
885 /* typeId = DRX3913K_TYPE_ID */
cd7a67a4
MCC		 886 state->m_has_lna = false;
887 state->m_has_oob = false;
888 state->m_has_atv = false;
889 state->m_has_audio = false;
890 state->m_has_dvbt = true;
891 state->m_has_dvbc = true;
892 state->m_has_sawsw = true;
893 state->m_has_gpio2 = false;
894 state->m_has_gpio1 = false;
895 state->m_has_irqn = false;
be44eb28
MCC		 896 break;
897 case 0x15:
898 /* typeId = DRX3915K_TYPE_ID */
cd7a67a4
MCC		 899 state->m_has_lna = false;
900 state->m_has_oob = false;
901 state->m_has_atv = true;
902 state->m_has_audio = false;
903 state->m_has_dvbt = true;
904 state->m_has_dvbc = false;
905 state->m_has_sawsw = true;
906 state->m_has_gpio2 = true;
907 state->m_has_gpio1 = true;
908 state->m_has_irqn = false;
be44eb28
MCC		 909 break;
910 case 0x16:
911 /* typeId = DRX3916K_TYPE_ID */
cd7a67a4
MCC		 912 state->m_has_lna = false;
913 state->m_has_oob = false;
914 state->m_has_atv = true;
915 state->m_has_audio = false;
916 state->m_has_dvbt = true;
917 state->m_has_dvbc = false;
918 state->m_has_sawsw = true;
919 state->m_has_gpio2 = true;
920 state->m_has_gpio1 = true;
921 state->m_has_irqn = false;
be44eb28
MCC		 922 break;
923 case 0x18:
924 /* typeId = DRX3918K_TYPE_ID */
cd7a67a4
MCC		 925 state->m_has_lna = false;
926 state->m_has_oob = false;
927 state->m_has_atv = true;
928 state->m_has_audio = true;
929 state->m_has_dvbt = true;
930 state->m_has_dvbc = false;
931 state->m_has_sawsw = true;
932 state->m_has_gpio2 = true;
933 state->m_has_gpio1 = true;
934 state->m_has_irqn = false;
be44eb28
MCC		 935 break;
936 case 0x21:
937 /* typeId = DRX3921K_TYPE_ID */
cd7a67a4
MCC		 938 state->m_has_lna = false;
939 state->m_has_oob = false;
940 state->m_has_atv = true;
941 state->m_has_audio = true;
942 state->m_has_dvbt = true;
943 state->m_has_dvbc = true;
944 state->m_has_sawsw = true;
945 state->m_has_gpio2 = true;
946 state->m_has_gpio1 = true;
947 state->m_has_irqn = false;
be44eb28
MCC		 948 break;
949 case 0x23:
950 /* typeId = DRX3923K_TYPE_ID */
cd7a67a4
MCC		 951 state->m_has_lna = false;
952 state->m_has_oob = false;
953 state->m_has_atv = true;
954 state->m_has_audio = true;
955 state->m_has_dvbt = true;
956 state->m_has_dvbc = true;
957 state->m_has_sawsw = true;
958 state->m_has_gpio2 = true;
959 state->m_has_gpio1 = true;
960 state->m_has_irqn = false;
be44eb28
MCC		 961 break;
962 case 0x25:
963 /* typeId = DRX3925K_TYPE_ID */
cd7a67a4
MCC		 964 state->m_has_lna = false;
965 state->m_has_oob = false;
966 state->m_has_atv = true;
967 state->m_has_audio = true;
968 state->m_has_dvbt = true;
969 state->m_has_dvbc = true;
970 state->m_has_sawsw = true;
971 state->m_has_gpio2 = true;
972 state->m_has_gpio1 = true;
973 state->m_has_irqn = false;
be44eb28
MCC		 974 break;
975 case 0x26:
976 /* typeId = DRX3926K_TYPE_ID */
cd7a67a4
MCC		 977 state->m_has_lna = false;
978 state->m_has_oob = false;
979 state->m_has_atv = true;
980 state->m_has_audio = false;
981 state->m_has_dvbt = true;
982 state->m_has_dvbc = true;
983 state->m_has_sawsw = true;
984 state->m_has_gpio2 = true;
985 state->m_has_gpio1 = true;
986 state->m_has_irqn = false;
be44eb28
MCC		 987 break;
988 default:
3a4398f5 989 pr_err("DeviceID 0x%02x not supported\n",
cd7a67a4 990 ((sio_top_jtagid_lo >> 12) & 0xFF));
be44eb28
MCC		 991 status = -EINVAL;
992 goto error2;
993 }
994
3a4398f5 995 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
cd7a67a4
MCC		 996 ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
997 state->m_osc_clock_freq / 1000,
998 state->m_osc_clock_freq % 1000);
9c6e1828 999
be44eb28
MCC		 1000error:
1001 if (status < 0)
3a4398f5 1002 pr_err("Error %d on %s\n", status, __func__);
be44eb28
MCC		 1003
1004error2:
43dd07f7
RM		 1005 return status;
1006}
1007
cd7a67a4 1008static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
43dd07f7
RM		 1009{
1010 int status;
1011 bool powerdown_cmd;
1012
2da67501
MCC		 1013 dprintk(1, "\n");
1014
43dd07f7 1015 /* Write command */
5e66b878 1016 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
43dd07f7 1017 if (status < 0)
be44eb28 1018 goto error;
43dd07f7 1019 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
b72852ba 1020 usleep_range(1000, 2000);
43dd07f7
RM		 1021
1022 powerdown_cmd =
ebc7de22 1023 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
cd7a67a4 1024 ((state->m_hi_cfg_ctrl) &
ebc7de22
OE		 1025 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1026 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
5a7f7b79 1027 if (!powerdown_cmd) {
43dd07f7 1028 /* Wait until command rdy */
cd7a67a4
MCC		 1029 u32 retry_count = 0;
1030 u16 wait_cmd;
43dd07f7
RM		 1031
1032 do {
b72852ba 1033 usleep_range(1000, 2000);
cd7a67a4 1034 retry_count += 1;
5e66b878 1035 status = read16(state, SIO_HI_RA_RAM_CMD__A,
cd7a67a4
MCC		 1036 &wait_cmd);
1037 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1038 && (wait_cmd != 0));
be44eb28
MCC		 1039 if (status < 0)
1040 goto error;
cd7a67a4 1041 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
43dd07f7 1042 }
be44eb28
MCC		 1043error:
1044 if (status < 0)
3a4398f5 1045 pr_err("Error %d on %s\n", status, __func__);
be44eb28 1046
43dd07f7
RM		 1047 return status;
1048}
1049
cd7a67a4 1050static int hi_cfg_command(struct drxk_state *state)
43dd07f7
RM		 1051{
1052 int status;
1053
2da67501
MCC		 1054 dprintk(1, "\n");
1055
43dd07f7 1056 mutex_lock(&state->mutex);
43dd07f7 1057
ab5060cd
MCC		 1058 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1059 state->m_hi_cfg_timeout);
be44eb28
MCC		 1060 if (status < 0)
1061 goto error;
ab5060cd
MCC		 1062 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1063 state->m_hi_cfg_ctrl);
be44eb28
MCC		 1064 if (status < 0)
1065 goto error;
ab5060cd
MCC		 1066 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1067 state->m_hi_cfg_wake_up_key);
be44eb28
MCC		 1068 if (status < 0)
1069 goto error;
ab5060cd
MCC		 1070 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1071 state->m_hi_cfg_bridge_delay);
be44eb28
MCC		 1072 if (status < 0)
1073 goto error;
ab5060cd
MCC		 1074 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1075 state->m_hi_cfg_timing_div);
be44eb28
MCC		 1076 if (status < 0)
1077 goto error;
ab5060cd
MCC		 1078 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1079 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
be44eb28
MCC		 1080 if (status < 0)
1081 goto error;
b1cf2019 1082 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
be44eb28
MCC		 1083 if (status < 0)
1084 goto error;
1085
cd7a67a4 1086 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
be44eb28 1087error:
43dd07f7 1088 mutex_unlock(&state->mutex);
be44eb28 1089 if (status < 0)
3a4398f5 1090 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1091 return status;
1092}
1093
cd7a67a4 1094static int init_hi(struct drxk_state *state)
43dd07f7 1095{
2da67501
MCC		 1096 dprintk(1, "\n");
1097
cd7a67a4
MCC		 1098 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1099 state->m_hi_cfg_timeout = 0x96FF;
43dd07f7 1100 /* port/bridge/power down ctrl */
cd7a67a4 1101 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
be44eb28 1102
cd7a67a4 1103 return hi_cfg_command(state);
43dd07f7
RM		 1104}
1105
cd7a67a4 1106static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
43dd07f7
RM		 1107{
1108 int status = -1;
cd7a67a4
MCC		 1109 u16 sio_pdr_mclk_cfg = 0;
1110 u16 sio_pdr_mdx_cfg = 0;
d5856813 1111 u16 err_cfg = 0;
43dd07f7 1112
534e0481 1113 dprintk(1, ": mpeg %s, %s mode\n",
cd7a67a4
MCC		 1114 mpeg_enable ? "enable" : "disable",
1115 state->m_enable_parallel ? "parallel" : "serial");
43dd07f7 1116
be44eb28 1117 /* stop lock indicator process */
ab5060cd
MCC		 1118 status = write16(state, SCU_RAM_GPIO__A,
1119 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
be44eb28
MCC		 1120 if (status < 0)
1121 goto error;
1122
1123 /* MPEG TS pad configuration */
8418366d 1124 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
be44eb28
MCC		 1125 if (status < 0)
1126 goto error;
1127
5a7f7b79 1128 if (!mpeg_enable) {
be44eb28
MCC		 1129 /* Set MPEG TS pads to inputmode */
1130 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
ea90f011 1131 if (status < 0)
be44eb28
MCC		 1132 goto error;
1133 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1134 if (status < 0)
1135 goto error;
1136 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1137 if (status < 0)
1138 goto error;
1139 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1140 if (status < 0)
1141 goto error;
1142 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1143 if (status < 0)
1144 goto error;
1145 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1146 if (status < 0)
1147 goto error;
1148 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1149 if (status < 0)
1150 goto error;
1151 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1152 if (status < 0)
1153 goto error;
1154 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1155 if (status < 0)
1156 goto error;
1157 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1158 if (status < 0)
1159 goto error;
1160 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1161 if (status < 0)
1162 goto error;
1163 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1164 if (status < 0)
1165 goto error;
1166 } else {
1167 /* Enable MPEG output */
cd7a67a4
MCC		 1168 sio_pdr_mdx_cfg =
1169 ((state->m_ts_data_strength <<
be44eb28 1170 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
cd7a67a4 1171 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
be44eb28
MCC		 1172 SIO_PDR_MCLK_CFG_DRIVE__B) |
1173 0x0003);
43dd07f7 1174
cd7a67a4 1175 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
be44eb28
MCC		 1176 if (status < 0)
1177 goto error;
d5856813
MCC		 1178
1179 if (state->enable_merr_cfg)
cd7a67a4 1180 err_cfg = sio_pdr_mdx_cfg;
d5856813
MCC		 1181
1182 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
be44eb28
MCC		 1183 if (status < 0)
1184 goto error;
d5856813 1185 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
be44eb28
MCC		 1186 if (status < 0)
1187 goto error;
d5856813 1188
5a7f7b79 1189 if (state->m_enable_parallel) {
39c1cb2b 1190 /* parallel -> enable MD1 to MD7 */
ab5060cd
MCC		 1191 status = write16(state, SIO_PDR_MD1_CFG__A,
1192 sio_pdr_mdx_cfg);
ea90f011 1193 if (status < 0)
be44eb28 1194 goto error;
ab5060cd
MCC		 1195 status = write16(state, SIO_PDR_MD2_CFG__A,
1196 sio_pdr_mdx_cfg);
ea90f011 1197 if (status < 0)
be44eb28 1198 goto error;
ab5060cd
MCC		 1199 status = write16(state, SIO_PDR_MD3_CFG__A,
1200 sio_pdr_mdx_cfg);
ea90f011 1201 if (status < 0)
be44eb28 1202 goto error;
ab5060cd
MCC		 1203 status = write16(state, SIO_PDR_MD4_CFG__A,
1204 sio_pdr_mdx_cfg);
ea90f011 1205 if (status < 0)
be44eb28 1206 goto error;
ab5060cd
MCC		 1207 status = write16(state, SIO_PDR_MD5_CFG__A,
1208 sio_pdr_mdx_cfg);
ea90f011 1209 if (status < 0)
be44eb28 1210 goto error;
ab5060cd
MCC		 1211 status = write16(state, SIO_PDR_MD6_CFG__A,
1212 sio_pdr_mdx_cfg);
be44eb28
MCC		 1213 if (status < 0)
1214 goto error;
ab5060cd
MCC		 1215 status = write16(state, SIO_PDR_MD7_CFG__A,
1216 sio_pdr_mdx_cfg);
be44eb28
MCC		 1217 if (status < 0)
1218 goto error;
1219 } else {
cd7a67a4 1220 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
be44eb28
MCC		 1221 SIO_PDR_MD0_CFG_DRIVE__B)
1222 | 0x0003);
1223 /* serial -> disable MD1 to MD7 */
5e66b878 1224 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
ea90f011 1225 if (status < 0)
be44eb28 1226 goto error;
5e66b878 1227 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
ea90f011 1228 if (status < 0)
be44eb28 1229 goto error;
5e66b878 1230 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
ea90f011 1231 if (status < 0)
be44eb28 1232 goto error;
5e66b878 1233 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
ea90f011 1234 if (status < 0)
be44eb28 1235 goto error;
5e66b878 1236 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
ea90f011 1237 if (status < 0)
be44eb28 1238 goto error;
5e66b878 1239 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
ea90f011 1240 if (status < 0)
be44eb28 1241 goto error;
5e66b878 1242 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
ea90f011 1243 if (status < 0)
be44eb28 1244 goto error;
43dd07f7 1245 }
cd7a67a4 1246 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
ea90f011 1247 if (status < 0)
be44eb28 1248 goto error;
cd7a67a4 1249 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
ea90f011 1250 if (status < 0)
be44eb28
MCC		 1251 goto error;
1252 }
1253 /* Enable MB output over MPEG pads and ctl input */
1254 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1255 if (status < 0)
1256 goto error;
1257 /* Write nomagic word to enable pdr reg write */
1258 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1259error:
1260 if (status < 0)
3a4398f5 1261 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1262 return status;
1263}
1264
cd7a67a4 1265static int mpegts_disable(struct drxk_state *state)
43dd07f7 1266{
2da67501
MCC		 1267 dprintk(1, "\n");
1268
cd7a67a4 1269 return mpegts_configure_pins(state, false);
43dd07f7
RM		 1270}
1271
cd7a67a4
MCC		 1272static int bl_chain_cmd(struct drxk_state *state,
1273 u16 rom_offset, u16 nr_of_elements, u32 time_out)
43dd07f7 1274{
cd7a67a4 1275 u16 bl_status = 0;
43dd07f7
RM		 1276 int status;
1277 unsigned long end;
1278
2da67501 1279 dprintk(1, "\n");
43dd07f7 1280 mutex_lock(&state->mutex);
be44eb28
MCC		 1281 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1282 if (status < 0)
1283 goto error;
cd7a67a4 1284 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
be44eb28
MCC		 1285 if (status < 0)
1286 goto error;
cd7a67a4 1287 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
be44eb28
MCC		 1288 if (status < 0)
1289 goto error;
1290 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1291 if (status < 0)
1292 goto error;
1293
cd7a67a4 1294 end = jiffies + msecs_to_jiffies(time_out);
43dd07f7 1295 do {
b72852ba 1296 usleep_range(1000, 2000);
cd7a67a4 1297 status = read16(state, SIO_BL_STATUS__A, &bl_status);
ea90f011 1298 if (status < 0)
be44eb28 1299 goto error;
cd7a67a4 1300 } while ((bl_status == 0x1) &&
be44eb28 1301 ((time_is_after_jiffies(end))));
43dd07f7 1302
cd7a67a4 1303 if (bl_status == 0x1) {
3a4398f5 1304 pr_err("SIO not ready\n");
be44eb28
MCC		 1305 status = -EINVAL;
1306 goto error2;
1307 }
1308error:
1309 if (status < 0)
3a4398f5 1310 pr_err("Error %d on %s\n", status, __func__);
be44eb28 1311error2:
43dd07f7
RM		 1312 mutex_unlock(&state->mutex);
1313 return status;
1314}
1315
1316
cd7a67a4
MCC		 1317static int download_microcode(struct drxk_state *state,
1318 const u8 p_mc_image[], u32 length)
43dd07f7 1319{
cd7a67a4
MCC		 1320 const u8 *p_src = p_mc_image;
1321 u32 address;
1322 u16 n_blocks;
1323 u16 block_size;
43dd07f7
RM		 1324 u32 offset = 0;
1325 u32 i;
1bd09ddc 1326 int status = 0;
43dd07f7 1327
2da67501
MCC		 1328 dprintk(1, "\n");
1329
5becbc58
HV		 1330 /* down the drain (we don't care about MAGIC_WORD) */
1331#if 0
1332 /* For future reference */
cd7a67a4 1333 drain = (p_src[0] << 8) | p_src[1];
5becbc58 1334#endif
cd7a67a4 1335 p_src += sizeof(u16);
ebc7de22 1336 offset += sizeof(u16);
cd7a67a4
MCC		 1337 n_blocks = (p_src[0] << 8) | p_src[1];
1338 p_src += sizeof(u16);
ebc7de22 1339 offset += sizeof(u16);
43dd07f7 1340
cd7a67a4
MCC		 1341 for (i = 0; i < n_blocks; i += 1) {
1342 address = (p_src[0] << 24) | (p_src[1] << 16) |
1343 (p_src[2] << 8) | p_src[3];
1344 p_src += sizeof(u32);
ebc7de22 1345 offset += sizeof(u32);
43dd07f7 1346
cd7a67a4
MCC		 1347 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1348 p_src += sizeof(u16);
ebc7de22 1349 offset += sizeof(u16);
43dd07f7 1350
5becbc58
HV		 1351#if 0
1352 /* For future reference */
cd7a67a4 1353 flags = (p_src[0] << 8) | p_src[1];
5becbc58 1354#endif
cd7a67a4 1355 p_src += sizeof(u16);
ebc7de22 1356 offset += sizeof(u16);
43dd07f7 1357
5becbc58
HV		 1358#if 0
1359 /* For future reference */
cd7a67a4 1360 block_crc = (p_src[0] << 8) | p_src[1];
5becbc58 1361#endif
cd7a67a4 1362 p_src += sizeof(u16);
ebc7de22 1363 offset += sizeof(u16);
bcd2ebb7 1364
cd7a67a4 1365 if (offset + block_size > length) {
3a4398f5 1366 pr_err("Firmware is corrupted.\n");
bcd2ebb7
MCC		 1367 return -EINVAL;
1368 }
1369
cd7a67a4 1370 status = write_block(state, address, block_size, p_src);
39624f7e 1371 if (status < 0) {
3a4398f5 1372 pr_err("Error %d while loading firmware\n", status);
43dd07f7 1373 break;
39624f7e 1374 }
cd7a67a4
MCC		 1375 p_src += block_size;
1376 offset += block_size;
43dd07f7
RM		 1377 }
1378 return status;
1379}
1380
cd7a67a4 1381static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
43dd07f7
RM		 1382{
1383 int status;
ebc7de22 1384 u16 data = 0;
cd7a67a4
MCC		 1385 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1386 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
43dd07f7
RM		 1387 unsigned long end;
1388
2da67501
MCC		 1389 dprintk(1, "\n");
1390
5a7f7b79 1391 if (!enable) {
cd7a67a4
MCC		 1392 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1393 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
43dd07f7
RM		 1394 }
1395
be44eb28 1396 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
cd7a67a4 1397 if (status >= 0 && data == desired_status) {
43dd07f7
RM		 1398 /* tokenring already has correct status */
1399 return status;
1400 }
1401 /* Disable/enable dvbt tokenring bridge */
cd7a67a4 1402 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
43dd07f7 1403
ebc7de22 1404 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
ea90f011 1405 do {
5e66b878 1406 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
ab5060cd
MCC		 1407 if ((status >= 0 && data == desired_status)
1408 || time_is_after_jiffies(end))
ea90f011 1409 break;
b72852ba 1410 usleep_range(1000, 2000);
be44eb28 1411 } while (1);
cd7a67a4 1412 if (data != desired_status) {
3a4398f5 1413 pr_err("SIO not ready\n");
be44eb28 1414 return -EINVAL;
43dd07f7
RM		 1415 }
1416 return status;
1417}
1418
cd7a67a4 1419static int mpegts_stop(struct drxk_state *state)
43dd07f7
RM		 1420{
1421 int status = 0;
cd7a67a4
MCC		 1422 u16 fec_oc_snc_mode = 0;
1423 u16 fec_oc_ipr_mode = 0;
43dd07f7 1424
2da67501
MCC		 1425 dprintk(1, "\n");
1426
39c1cb2b 1427 /* Graceful shutdown (byte boundaries) */
cd7a67a4 1428 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
be44eb28
MCC		 1429 if (status < 0)
1430 goto error;
cd7a67a4
MCC		 1431 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1432 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
be44eb28
MCC		 1433 if (status < 0)
1434 goto error;
1435
1436 /* Suppress MCLK during absence of data */
cd7a67a4 1437 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
be44eb28
MCC		 1438 if (status < 0)
1439 goto error;
cd7a67a4
MCC		 1440 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1441 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
be44eb28
MCC		 1442
1443error:
1444 if (status < 0)
3a4398f5 1445 pr_err("Error %d on %s\n", status, __func__);
43dd07f7 1446
43dd07f7
RM		 1447 return status;
1448}
1449
1450static int scu_command(struct drxk_state *state,
cd7a67a4
MCC		 1451 u16 cmd, u8 parameter_len,
1452 u16 *parameter, u8 result_len, u16 *result)
43dd07f7
RM		 1453{
1454#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1455#error DRXK register mapping no longer compatible with this routine!
1456#endif
cd7a67a4 1457 u16 cur_cmd = 0;
be44eb28 1458 int status = -EINVAL;
43dd07f7 1459 unsigned long end;
be44eb28
MCC		 1460 u8 buffer[34];
1461 int cnt = 0, ii;
7558977a
MCC		 1462 const char *p;
1463 char errname[30];
43dd07f7 1464
2da67501
MCC		 1465 dprintk(1, "\n");
1466
cd7a67a4
MCC		 1467 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1468 ((result_len > 0) && (result == NULL))) {
3a4398f5 1469 pr_err("Error %d on %s\n", status, __func__);
e4459e16
AK		 1470 return status;
1471 }
43dd07f7
RM		 1472
1473 mutex_lock(&state->mutex);
be44eb28
MCC		 1474
1475 /* assume that the command register is ready
1476 since it is checked afterwards */
cd7a67a4 1477 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
be44eb28
MCC		 1478 buffer[cnt++] = (parameter[ii] & 0xFF);
1479 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1480 }
1481 buffer[cnt++] = (cmd & 0xFF);
1482 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1483
1484 write_block(state, SCU_RAM_PARAM_0__A -
cd7a67a4 1485 (parameter_len - 1), cnt, buffer);
be44eb28
MCC		 1486 /* Wait until SCU has processed command */
1487 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
43dd07f7 1488 do {
b72852ba 1489 usleep_range(1000, 2000);
cd7a67a4 1490 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
be44eb28
MCC		 1491 if (status < 0)
1492 goto error;
cd7a67a4
MCC		 1493 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1494 if (cur_cmd != DRX_SCU_READY) {
3a4398f5 1495 pr_err("SCU not ready\n");
be44eb28
MCC		 1496 status = -EIO;
1497 goto error2;
1498 }
1499 /* read results */
cd7a67a4 1500 if ((result_len > 0) && (result != NULL)) {
be44eb28
MCC		 1501 s16 err;
1502 int ii;
43dd07f7 1503
cd7a67a4 1504 for (ii = result_len - 1; ii >= 0; ii -= 1) {
ab5060cd
MCC		 1505 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1506 &result[ii]);
ea90f011 1507 if (status < 0)
be44eb28 1508 goto error;
43dd07f7 1509 }
be44eb28
MCC		 1510
1511 /* Check if an error was reported by SCU */
1512 err = (s16)result[0];
7558977a
MCC		 1513 if (err >= 0)
1514 goto error;
be44eb28 1515
7558977a
MCC		 1516 /* check for the known error codes */
1517 switch (err) {
1518 case SCU_RESULT_UNKCMD:
1519 p = "SCU_RESULT_UNKCMD";
1520 break;
1521 case SCU_RESULT_UNKSTD:
1522 p = "SCU_RESULT_UNKSTD";
1523 break;
1524 case SCU_RESULT_SIZE:
1525 p = "SCU_RESULT_SIZE";
1526 break;
1527 case SCU_RESULT_INVPAR:
1528 p = "SCU_RESULT_INVPAR";
1529 break;
1530 default: /* Other negative values are errors */
1531 sprintf(errname, "ERROR: %d\n", err);
1532 p = errname;
43dd07f7 1533 }
3a4398f5 1534 pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
7558977a
MCC		 1535 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1536 status = -EINVAL;
1537 goto error2;
be44eb28
MCC		 1538 }
1539
1540error:
ebc7de22 1541 if (status < 0)
3a4398f5 1542 pr_err("Error %d on %s\n", status, __func__);
be44eb28
MCC		 1543error2:
1544 mutex_unlock(&state->mutex);
43dd07f7
RM		 1545 return status;
1546}
1547
cd7a67a4 1548static int set_iqm_af(struct drxk_state *state, bool active)
43dd07f7
RM		 1549{
1550 u16 data = 0;
1551 int status;
1552
2da67501
MCC		 1553 dprintk(1, "\n");
1554
be44eb28
MCC		 1555 /* Configure IQM */
1556 status = read16(state, IQM_AF_STDBY__A, &data);
1557 if (status < 0)
1558 goto error;
1559
1560 if (!active) {
1561 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1562 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1563 | IQM_AF_STDBY_STDBY_PD_STANDBY
1564 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1565 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1566 } else {
1567 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1568 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1569 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1570 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1571 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1572 );
1573 }
1574 status = write16(state, IQM_AF_STDBY__A, data);
1575
1576error:
1577 if (status < 0)
3a4398f5 1578 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1579 return status;
1580}
1581
cd7a67a4 1582static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
43dd07f7
RM		 1583{
1584 int status = 0;
cd7a67a4 1585 u16 sio_cc_pwd_mode = 0;
43dd07f7 1586
2da67501
MCC		 1587 dprintk(1, "\n");
1588
43dd07f7
RM		 1589 /* Check arguments */
1590 if (mode == NULL)
be44eb28 1591 return -EINVAL;
43dd07f7
RM		 1592
1593 switch (*mode) {
1594 case DRX_POWER_UP:
cd7a67a4 1595 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
43dd07f7
RM		 1596 break;
1597 case DRXK_POWER_DOWN_OFDM:
cd7a67a4 1598 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
43dd07f7
RM		 1599 break;
1600 case DRXK_POWER_DOWN_CORE:
cd7a67a4 1601 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
43dd07f7
RM		 1602 break;
1603 case DRXK_POWER_DOWN_PLL:
cd7a67a4 1604 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
43dd07f7
RM		 1605 break;
1606 case DRX_POWER_DOWN:
cd7a67a4 1607 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
43dd07f7
RM		 1608 break;
1609 default:
1610 /* Unknow sleep mode */
be44eb28 1611 return -EINVAL;
43dd07f7
RM		 1612 }
1613
1614 /* If already in requested power mode, do nothing */
cd7a67a4 1615 if (state->m_current_power_mode == *mode)
43dd07f7
RM		 1616 return 0;
1617
1618 /* For next steps make sure to start from DRX_POWER_UP mode */
cd7a67a4
MCC		 1619 if (state->m_current_power_mode != DRX_POWER_UP) {
1620 status = power_up_device(state);
be44eb28
MCC		 1621 if (status < 0)
1622 goto error;
cd7a67a4 1623 status = dvbt_enable_ofdm_token_ring(state, true);
be44eb28
MCC		 1624 if (status < 0)
1625 goto error;
43dd07f7
RM		 1626 }
1627
1628 if (*mode == DRX_POWER_UP) {
2c149601 1629 /* Restore analog & pin configuration */
43dd07f7
RM		 1630 } else {
1631 /* Power down to requested mode */
1632 /* Backup some register settings */
1633 /* Set pins with possible pull-ups connected
1634 to them in input mode */
1635 /* Analog power down */
1636 /* ADC power down */
1637 /* Power down device */
1638 /* stop all comm_exec */
1639 /* Stop and power down previous standard */
cd7a67a4 1640 switch (state->m_operation_mode) {
be44eb28 1641 case OM_DVBT:
cd7a67a4 1642 status = mpegts_stop(state);
ea90f011 1643 if (status < 0)
be44eb28 1644 goto error;
cd7a67a4 1645 status = power_down_dvbt(state, false);
ea90f011 1646 if (status < 0)
be44eb28
MCC		 1647 goto error;
1648 break;
1649 case OM_QAM_ITU_A:
1650 case OM_QAM_ITU_C:
cd7a67a4 1651 status = mpegts_stop(state);
ea90f011 1652 if (status < 0)
be44eb28 1653 goto error;
cd7a67a4 1654 status = power_down_qam(state);
be44eb28
MCC		 1655 if (status < 0)
1656 goto error;
1657 break;
1658 default:
1659 break;
1660 }
cd7a67a4 1661 status = dvbt_enable_ofdm_token_ring(state, false);
be44eb28
MCC		 1662 if (status < 0)
1663 goto error;
cd7a67a4 1664 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
be44eb28
MCC		 1665 if (status < 0)
1666 goto error;
1667 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1668 if (status < 0)
1669 goto error;
43dd07f7 1670
be44eb28 1671 if (*mode != DRXK_POWER_DOWN_OFDM) {
cd7a67a4 1672 state->m_hi_cfg_ctrl |=
be44eb28 1673 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
cd7a67a4 1674 status = hi_cfg_command(state);
be44eb28
MCC		 1675 if (status < 0)
1676 goto error;
1677 }
43dd07f7 1678 }
cd7a67a4 1679 state->m_current_power_mode = *mode;
be44eb28
MCC		 1680
1681error:
1682 if (status < 0)
3a4398f5 1683 pr_err("Error %d on %s\n", status, __func__);
be44eb28 1684
ebc7de22 1685 return status;
43dd07f7
RM		 1686}
1687
cd7a67a4 1688static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
43dd07f7 1689{
cd7a67a4
MCC		 1690 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1691 u16 cmd_result = 0;
43dd07f7
RM		 1692 u16 data = 0;
1693 int status;
1694
2da67501
MCC		 1695 dprintk(1, "\n");
1696
be44eb28
MCC		 1697 status = read16(state, SCU_COMM_EXEC__A, &data);
1698 if (status < 0)
1699 goto error;
1700 if (data == SCU_COMM_EXEC_ACTIVE) {
1701 /* Send OFDM stop command */
ab5060cd
MCC		 1702 status = scu_command(state,
1703 SCU_RAM_COMMAND_STANDARD_OFDM
1704 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1705 0, NULL, 1, &cmd_result);
ea90f011 1706 if (status < 0)
be44eb28
MCC		 1707 goto error;
1708 /* Send OFDM reset command */
ab5060cd
MCC		 1709 status = scu_command(state,
1710 SCU_RAM_COMMAND_STANDARD_OFDM
1711 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1712 0, NULL, 1, &cmd_result);
ea90f011 1713 if (status < 0)
be44eb28
MCC		 1714 goto error;
1715 }
43dd07f7 1716
be44eb28
MCC		 1717 /* Reset datapath for OFDM, processors first */
1718 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1719 if (status < 0)
1720 goto error;
1721 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1722 if (status < 0)
1723 goto error;
1724 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1725 if (status < 0)
1726 goto error;
43dd07f7 1727
be44eb28 1728 /* powerdown AFE */
cd7a67a4 1729 status = set_iqm_af(state, false);
be44eb28
MCC		 1730 if (status < 0)
1731 goto error;
1732
1733 /* powerdown to OFDM mode */
cd7a67a4
MCC		 1734 if (set_power_mode) {
1735 status = ctrl_power_mode(state, &power_mode);
be44eb28
MCC		 1736 if (status < 0)
1737 goto error;
1738 }
1739error:
1740 if (status < 0)
3a4398f5 1741 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1742 return status;
1743}
1744
cd7a67a4
MCC		 1745static int setoperation_mode(struct drxk_state *state,
1746 enum operation_mode o_mode)
43dd07f7
RM		 1747{
1748 int status = 0;
1749
2da67501 1750 dprintk(1, "\n");
43dd07f7 1751 /*
ebc7de22
OE		 1752 Stop and power down previous standard
1753 TODO investigate total power down instead of partial
1754 power down depending on "previous" standard.
1755 */
43dd07f7 1756
be44eb28 1757 /* disable HW lock indicator */
ab5060cd
MCC		 1758 status = write16(state, SCU_RAM_GPIO__A,
1759 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
be44eb28
MCC		 1760 if (status < 0)
1761 goto error;
43dd07f7 1762
f1b82970 1763 /* Device is already at the required mode */
cd7a67a4 1764 if (state->m_operation_mode == o_mode)
f1b82970
MCC		 1765 return 0;
1766
cd7a67a4 1767 switch (state->m_operation_mode) {
f1b82970
MCC		 1768 /* OM_NONE was added for start up */
1769 case OM_NONE:
1770 break;
1771 case OM_DVBT:
cd7a67a4 1772 status = mpegts_stop(state);
f1b82970 1773 if (status < 0)
be44eb28 1774 goto error;
cd7a67a4 1775 status = power_down_dvbt(state, true);
f1b82970
MCC		 1776 if (status < 0)
1777 goto error;
cd7a67a4 1778 state->m_operation_mode = OM_NONE;
f1b82970
MCC		 1779 break;
1780 case OM_QAM_ITU_A: /* fallthrough */
1781 case OM_QAM_ITU_C:
cd7a67a4 1782 status = mpegts_stop(state);
f1b82970
MCC		 1783 if (status < 0)
1784 goto error;
cd7a67a4 1785 status = power_down_qam(state);
f1b82970
MCC		 1786 if (status < 0)
1787 goto error;
cd7a67a4 1788 state->m_operation_mode = OM_NONE;
f1b82970
MCC		 1789 break;
1790 case OM_QAM_ITU_B:
1791 default:
1792 status = -EINVAL;
1793 goto error;
1794 }
be44eb28 1795
f1b82970
MCC		 1796 /*
1797 Power up new standard
1798 */
cd7a67a4 1799 switch (o_mode) {
f1b82970 1800 case OM_DVBT:
48763e2c 1801 dprintk(1, ": DVB-T\n");
cd7a67a4
MCC		 1802 state->m_operation_mode = o_mode;
1803 status = set_dvbt_standard(state, o_mode);
f1b82970
MCC		 1804 if (status < 0)
1805 goto error;
1806 break;
1807 case OM_QAM_ITU_A: /* fallthrough */
1808 case OM_QAM_ITU_C:
48763e2c 1809 dprintk(1, ": DVB-C Annex %c\n",
cd7a67a4
MCC		 1810 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1811 state->m_operation_mode = o_mode;
1812 status = set_qam_standard(state, o_mode);
f1b82970
MCC		 1813 if (status < 0)
1814 goto error;
1815 break;
1816 case OM_QAM_ITU_B:
1817 default:
1818 status = -EINVAL;
be44eb28
MCC		 1819 }
1820error:
1821 if (status < 0)
3a4398f5 1822 pr_err("Error %d on %s\n", status, __func__);
be44eb28 1823 return status;
43dd07f7
RM		 1824}
1825
cd7a67a4
MCC		 1826static int start(struct drxk_state *state, s32 offset_freq,
1827 s32 intermediate_frequency)
43dd07f7 1828{
be44eb28
MCC		 1829 int status = -EINVAL;
1830
cd7a67a4
MCC		 1831 u16 i_freqk_hz;
1832 s32 offsetk_hz = offset_freq / 1000;
43dd07f7 1833
2da67501 1834 dprintk(1, "\n");
cd7a67a4
MCC		 1835 if (state->m_drxk_state != DRXK_STOPPED &&
1836 state->m_drxk_state != DRXK_DTV_STARTED)
be44eb28 1837 goto error;
43dd07f7 1838
cd7a67a4 1839 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
43dd07f7 1840
cd7a67a4
MCC		 1841 if (intermediate_frequency < 0) {
1842 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1843 intermediate_frequency = -intermediate_frequency;
be44eb28 1844 }
43dd07f7 1845
cd7a67a4 1846 switch (state->m_operation_mode) {
be44eb28
MCC		 1847 case OM_QAM_ITU_A:
1848 case OM_QAM_ITU_C:
cd7a67a4
MCC		 1849 i_freqk_hz = (intermediate_frequency / 1000);
1850 status = set_qam(state, i_freqk_hz, offsetk_hz);
be44eb28
MCC		 1851 if (status < 0)
1852 goto error;
cd7a67a4 1853 state->m_drxk_state = DRXK_DTV_STARTED;
be44eb28
MCC		 1854 break;
1855 case OM_DVBT:
cd7a67a4
MCC		 1856 i_freqk_hz = (intermediate_frequency / 1000);
1857 status = mpegts_stop(state);
be44eb28
MCC		 1858 if (status < 0)
1859 goto error;
cd7a67a4 1860 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
be44eb28
MCC		 1861 if (status < 0)
1862 goto error;
cd7a67a4 1863 status = dvbt_start(state);
be44eb28
MCC		 1864 if (status < 0)
1865 goto error;
cd7a67a4 1866 state->m_drxk_state = DRXK_DTV_STARTED;
be44eb28
MCC		 1867 break;
1868 default:
1869 break;
1870 }
1871error:
1872 if (status < 0)
3a4398f5 1873 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1874 return status;
1875}
1876
cd7a67a4 1877static int shut_down(struct drxk_state *state)
43dd07f7 1878{
2da67501
MCC		 1879 dprintk(1, "\n");
1880
cd7a67a4 1881 mpegts_stop(state);
43dd07f7
RM		 1882 return 0;
1883}
1884
cd7a67a4 1885static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
43dd07f7 1886{
be44eb28 1887 int status = -EINVAL;
43dd07f7 1888
2da67501
MCC		 1889 dprintk(1, "\n");
1890
cd7a67a4 1891 if (p_lock_status == NULL)
be44eb28 1892 goto error;
43dd07f7 1893
cd7a67a4 1894 *p_lock_status = NOT_LOCKED;
43dd07f7
RM		 1895
1896 /* define the SCU command code */
cd7a67a4 1897 switch (state->m_operation_mode) {
43dd07f7
RM		 1898 case OM_QAM_ITU_A:
1899 case OM_QAM_ITU_B:
1900 case OM_QAM_ITU_C:
cd7a67a4 1901 status = get_qam_lock_status(state, p_lock_status);
43dd07f7
RM		 1902 break;
1903 case OM_DVBT:
cd7a67a4 1904 status = get_dvbt_lock_status(state, p_lock_status);
43dd07f7
RM		 1905 break;
1906 default:
b73bb2ab
DS		 1907 pr_debug("Unsupported operation mode %d in %s\n",
1908 state->m_operation_mode, __func__);
1909 return 0;
43dd07f7 1910 }
be44eb28
MCC		 1911error:
1912 if (status < 0)
3a4398f5 1913 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1914 return status;
1915}
1916
cd7a67a4 1917static int mpegts_start(struct drxk_state *state)
43dd07f7 1918{
be44eb28 1919 int status;
43dd07f7 1920
cd7a67a4 1921 u16 fec_oc_snc_mode = 0;
43dd07f7 1922
be44eb28 1923 /* Allow OC to sync again */
cd7a67a4 1924 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
be44eb28
MCC		 1925 if (status < 0)
1926 goto error;
cd7a67a4
MCC		 1927 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1928 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
be44eb28
MCC		 1929 if (status < 0)
1930 goto error;
1931 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1932error:
1933 if (status < 0)
3a4398f5 1934 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 1935 return status;
1936}
1937
cd7a67a4 1938static int mpegts_dto_init(struct drxk_state *state)
43dd07f7 1939{
be44eb28 1940 int status;
43dd07f7 1941
2da67501
MCC		 1942 dprintk(1, "\n");
1943
be44eb28
MCC		 1944 /* Rate integration settings */
1945 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1946 if (status < 0)
1947 goto error;
1948 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1949 if (status < 0)
1950 goto error;
1951 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1952 if (status < 0)
1953 goto error;
1954 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1955 if (status < 0)
1956 goto error;
1957 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1958 if (status < 0)
1959 goto error;
1960 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1961 if (status < 0)
1962 goto error;
1963 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1964 if (status < 0)
1965 goto error;
1966 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1967 if (status < 0)
1968 goto error;
1969
1970 /* Additional configuration */
1971 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1972 if (status < 0)
1973 goto error;
1974 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1975 if (status < 0)
1976 goto error;
1977 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1978error:
1979 if (status < 0)
3a4398f5 1980 pr_err("Error %d on %s\n", status, __func__);
43dd07f7 1981
43dd07f7
RM		 1982 return status;
1983}
1984
cd7a67a4
MCC		 1985static int mpegts_dto_setup(struct drxk_state *state,
1986 enum operation_mode o_mode)
43dd07f7 1987{
be44eb28 1988 int status;
43dd07f7 1989
cd7a67a4
MCC		 1990 u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */
1991 u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */
1992 u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */
1993 u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */
1994 u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */
1995 u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1996 u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */
1997 u16 fec_oc_tmd_mode = 0;
1998 u16 fec_oc_tmd_int_upd_rate = 0;
1999 u32 max_bit_rate = 0;
2000 bool static_clk = false;
43dd07f7 2001
2da67501
MCC		 2002 dprintk(1, "\n");
2003
be44eb28 2004 /* Check insertion of the Reed-Solomon parity bytes */
cd7a67a4 2005 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
be44eb28
MCC		 2006 if (status < 0)
2007 goto error;
cd7a67a4 2008 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
be44eb28
MCC		 2009 if (status < 0)
2010 goto error;
cd7a67a4
MCC		 2011 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2012 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
5a7f7b79 2013 if (state->m_insert_rs_byte) {
be44eb28 2014 /* enable parity symbol forward */
cd7a67a4 2015 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
be44eb28 2016 /* MVAL disable during parity bytes */
cd7a67a4 2017 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
be44eb28 2018 /* TS burst length to 204 */
cd7a67a4 2019 fec_oc_dto_burst_len = 204;
be44eb28 2020 }
43dd07f7 2021
39c1cb2b 2022 /* Check serial or parallel output */
cd7a67a4 2023 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
5a7f7b79 2024 if (!state->m_enable_parallel) {
be44eb28 2025 /* MPEG data output is serial -> set ipr_mode[0] */
cd7a67a4 2026 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
be44eb28 2027 }
43dd07f7 2028
cd7a67a4 2029 switch (o_mode) {
be44eb28 2030 case OM_DVBT:
cd7a67a4
MCC		 2031 max_bit_rate = state->m_dvbt_bitrate;
2032 fec_oc_tmd_mode = 3;
2033 fec_oc_rcn_ctl_rate = 0xC00000;
2034 static_clk = state->m_dvbt_static_clk;
be44eb28
MCC		 2035 break;
2036 case OM_QAM_ITU_A: /* fallthrough */
2037 case OM_QAM_ITU_C:
cd7a67a4
MCC		 2038 fec_oc_tmd_mode = 0x0004;
2039 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2040 max_bit_rate = state->m_dvbc_bitrate;
2041 static_clk = state->m_dvbc_static_clk;
be44eb28
MCC		 2042 break;
2043 default:
2044 status = -EINVAL;
2045 } /* switch (standard) */
2046 if (status < 0)
2047 goto error;
2048
2049 /* Configure DTO's */
cd7a67a4
MCC		 2050 if (static_clk) {
2051 u32 bit_rate = 0;
be44eb28
MCC		 2052
2053 /* Rational DTO for MCLK source (static MCLK rate),
2054 Dynamic DTO for optimal grouping
2055 (avoid intra-packet gaps),
2056 DTO offset enable to sync TS burst with MSTRT */
cd7a67a4 2057 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
be44eb28 2058 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
cd7a67a4 2059 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
be44eb28
MCC		 2060 FEC_OC_FCT_MODE_VIRT_ENA__M);
2061
2062 /* Check user defined bitrate */
cd7a67a4
MCC		 2063 bit_rate = max_bit_rate;
2064 if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */
2065 bit_rate = 75900000UL;
43dd07f7 2066 }
be44eb28
MCC		 2067 /* Rational DTO period:
2068 dto_period = (Fsys / bitrate) - 2
2069
cd7a67a4 2070 result should be floored,
be44eb28
MCC		 2071 to make sure >= requested bitrate
2072 */
cd7a67a4
MCC		 2073 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2074 * 1000) / bit_rate);
2075 if (fec_oc_dto_period <= 2)
2076 fec_oc_dto_period = 0;
be44eb28 2077 else
cd7a67a4
MCC		 2078 fec_oc_dto_period -= 2;
2079 fec_oc_tmd_int_upd_rate = 8;
be44eb28 2080 } else {
cd7a67a4
MCC		 2081 /* (commonAttr->static_clk == false) => dynamic mode */
2082 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2083 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2084 fec_oc_tmd_int_upd_rate = 5;
be44eb28 2085 }
43dd07f7 2086
be44eb28 2087 /* Write appropriate registers with requested configuration */
cd7a67a4 2088 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
be44eb28
MCC		 2089 if (status < 0)
2090 goto error;
cd7a67a4 2091 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
be44eb28
MCC		 2092 if (status < 0)
2093 goto error;
cd7a67a4 2094 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
be44eb28
MCC		 2095 if (status < 0)
2096 goto error;
cd7a67a4 2097 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
be44eb28
MCC		 2098 if (status < 0)
2099 goto error;
cd7a67a4 2100 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
be44eb28
MCC		 2101 if (status < 0)
2102 goto error;
cd7a67a4 2103 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
be44eb28
MCC		 2104 if (status < 0)
2105 goto error;
43dd07f7 2106
be44eb28 2107 /* Rate integration settings */
cd7a67a4 2108 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
be44eb28
MCC		 2109 if (status < 0)
2110 goto error;
ab5060cd
MCC		 2111 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2112 fec_oc_tmd_int_upd_rate);
be44eb28
MCC		 2113 if (status < 0)
2114 goto error;
cd7a67a4 2115 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
be44eb28
MCC		 2116error:
2117 if (status < 0)
3a4398f5 2118 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2119 return status;
2120}
2121
cd7a67a4 2122static int mpegts_configure_polarity(struct drxk_state *state)
43dd07f7 2123{
cd7a67a4 2124 u16 fec_oc_reg_ipr_invert = 0;
43dd07f7
RM		 2125
2126 /* Data mask for the output data byte */
cd7a67a4 2127 u16 invert_data_mask =
ebc7de22
OE		 2128 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2129 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2130 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2131 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
43dd07f7 2132
be44eb28
MCC		 2133 dprintk(1, "\n");
2134
43dd07f7 2135 /* Control selective inversion of output bits */
cd7a67a4 2136 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
5a7f7b79 2137 if (state->m_invert_data)
cd7a67a4
MCC		 2138 fec_oc_reg_ipr_invert |= invert_data_mask;
2139 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
5a7f7b79 2140 if (state->m_invert_err)
cd7a67a4
MCC		 2141 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2142 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
5a7f7b79 2143 if (state->m_invert_str)
cd7a67a4
MCC		 2144 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2145 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
5a7f7b79 2146 if (state->m_invert_val)
cd7a67a4
MCC		 2147 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2148 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
5a7f7b79 2149 if (state->m_invert_clk)
cd7a67a4
MCC		 2150 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2151
2152 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
43dd07f7
RM		 2153}
2154
2155#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2156
cd7a67a4
MCC		 2157static int set_agc_rf(struct drxk_state *state,
2158 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
43dd07f7 2159{
be44eb28
MCC		 2160 int status = -EINVAL;
2161 u16 data = 0;
cd7a67a4 2162 struct s_cfg_agc *p_if_agc_settings;
43dd07f7 2163
2da67501
MCC		 2164 dprintk(1, "\n");
2165
cd7a67a4 2166 if (p_agc_cfg == NULL)
be44eb28 2167 goto error;
43dd07f7 2168
cd7a67a4 2169 switch (p_agc_cfg->ctrl_mode) {
be44eb28
MCC		 2170 case DRXK_AGC_CTRL_AUTO:
2171 /* Enable RF AGC DAC */
2172 status = read16(state, IQM_AF_STDBY__A, &data);
2173 if (status < 0)
2174 goto error;
2175 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2176 status = write16(state, IQM_AF_STDBY__A, data);
2177 if (status < 0)
2178 goto error;
2179 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2180 if (status < 0)
2181 goto error;
43dd07f7 2182
be44eb28
MCC		 2183 /* Enable SCU RF AGC loop */
2184 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
43dd07f7 2185
be44eb28 2186 /* Polarity */
cd7a67a4 2187 if (state->m_rf_agc_pol)
be44eb28
MCC		 2188 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2189 else
2190 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2191 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2192 if (status < 0)
2193 goto error;
43dd07f7 2194
be44eb28
MCC		 2195 /* Set speed (using complementary reduction value) */
2196 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2197 if (status < 0)
2198 goto error;
43dd07f7 2199
be44eb28 2200 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
cd7a67a4 2201 data |= (~(p_agc_cfg->speed <<
be44eb28
MCC		 2202 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2203 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
43dd07f7 2204
be44eb28
MCC		 2205 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2206 if (status < 0)
2207 goto error;
43dd07f7 2208
cd7a67a4
MCC		 2209 if (is_dvbt(state))
2210 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2211 else if (is_qam(state))
2212 p_if_agc_settings = &state->m_qam_if_agc_cfg;
be44eb28 2213 else
cd7a67a4
MCC		 2214 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2215 if (p_if_agc_settings == NULL) {
be44eb28
MCC		 2216 status = -EINVAL;
2217 goto error;
2218 }
43dd07f7 2219
be44eb28 2220 /* Set TOP, only if IF-AGC is in AUTO mode */
89fffac8 2221 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
ab5060cd
MCC		 2222 status = write16(state,
2223 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2224 p_agc_cfg->top);
ea90f011 2225 if (status < 0)
be44eb28 2226 goto error;
89fffac8 2227 }
43dd07f7 2228
be44eb28 2229 /* Cut-Off current */
ab5060cd
MCC		 2230 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2231 p_agc_cfg->cut_off_current);
be44eb28
MCC		 2232 if (status < 0)
2233 goto error;
43dd07f7 2234
be44eb28 2235 /* Max. output level */
ab5060cd
MCC		 2236 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2237 p_agc_cfg->max_output_level);
be44eb28
MCC		 2238 if (status < 0)
2239 goto error;
43dd07f7 2240
be44eb28 2241 break;
43dd07f7 2242
be44eb28
MCC		 2243 case DRXK_AGC_CTRL_USER:
2244 /* Enable RF AGC DAC */
2245 status = read16(state, IQM_AF_STDBY__A, &data);
2246 if (status < 0)
2247 goto error;
2248 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2249 status = write16(state, IQM_AF_STDBY__A, data);
2250 if (status < 0)
2251 goto error;
43dd07f7 2252
be44eb28
MCC		 2253 /* Disable SCU RF AGC loop */
2254 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2255 if (status < 0)
2256 goto error;
2257 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
cd7a67a4 2258 if (state->m_rf_agc_pol)
be44eb28
MCC		 2259 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2260 else
2261 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2262 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2263 if (status < 0)
2264 goto error;
43dd07f7 2265
be44eb28
MCC		 2266 /* SCU c.o.c. to 0, enabling full control range */
2267 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2268 if (status < 0)
2269 goto error;
43dd07f7 2270
be44eb28 2271 /* Write value to output pin */
ab5060cd
MCC		 2272 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2273 p_agc_cfg->output_level);
be44eb28
MCC		 2274 if (status < 0)
2275 goto error;
2276 break;
43dd07f7 2277
be44eb28
MCC		 2278 case DRXK_AGC_CTRL_OFF:
2279 /* Disable RF AGC DAC */
2280 status = read16(state, IQM_AF_STDBY__A, &data);
2281 if (status < 0)
2282 goto error;
2283 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2284 status = write16(state, IQM_AF_STDBY__A, data);
2285 if (status < 0)
2286 goto error;
43dd07f7 2287
be44eb28
MCC		 2288 /* Disable SCU RF AGC loop */
2289 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2290 if (status < 0)
2291 goto error;
2292 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2293 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2294 if (status < 0)
2295 goto error;
2296 break;
43dd07f7 2297
be44eb28
MCC		 2298 default:
2299 status = -EINVAL;
43dd07f7 2300
be44eb28
MCC		 2301 }
2302error:
2303 if (status < 0)
3a4398f5 2304 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2305 return status;
2306}
2307
2308#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2309
cd7a67a4
MCC		 2310static int set_agc_if(struct drxk_state *state,
2311 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
43dd07f7
RM		 2312{
2313 u16 data = 0;
2314 int status = 0;
cd7a67a4 2315 struct s_cfg_agc *p_rf_agc_settings;
43dd07f7 2316
2da67501
MCC		 2317 dprintk(1, "\n");
2318
cd7a67a4 2319 switch (p_agc_cfg->ctrl_mode) {
be44eb28 2320 case DRXK_AGC_CTRL_AUTO:
43dd07f7 2321
be44eb28
MCC		 2322 /* Enable IF AGC DAC */
2323 status = read16(state, IQM_AF_STDBY__A, &data);
2324 if (status < 0)
2325 goto error;
2326 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2327 status = write16(state, IQM_AF_STDBY__A, data);
2328 if (status < 0)
2329 goto error;
43dd07f7 2330
be44eb28
MCC		 2331 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2332 if (status < 0)
2333 goto error;
43dd07f7 2334
be44eb28
MCC		 2335 /* Enable SCU IF AGC loop */
2336 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
43dd07f7 2337
be44eb28 2338 /* Polarity */
cd7a67a4 2339 if (state->m_if_agc_pol)
be44eb28
MCC		 2340 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2341 else
2342 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2343 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2344 if (status < 0)
2345 goto error;
43dd07f7 2346
be44eb28
MCC		 2347 /* Set speed (using complementary reduction value) */
2348 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2349 if (status < 0)
2350 goto error;
2351 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
cd7a67a4 2352 data |= (~(p_agc_cfg->speed <<
be44eb28
MCC		 2353 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2354 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
43dd07f7 2355
be44eb28
MCC		 2356 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2357 if (status < 0)
2358 goto error;
43dd07f7 2359
cd7a67a4
MCC		 2360 if (is_qam(state))
2361 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
be44eb28 2362 else
cd7a67a4
MCC		 2363 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2364 if (p_rf_agc_settings == NULL)
be44eb28
MCC		 2365 return -1;
2366 /* Restore TOP */
ab5060cd
MCC		 2367 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2368 p_rf_agc_settings->top);
be44eb28
MCC		 2369 if (status < 0)
2370 goto error;
2371 break;
43dd07f7 2372
be44eb28 2373 case DRXK_AGC_CTRL_USER:
43dd07f7 2374
be44eb28
MCC		 2375 /* Enable IF AGC DAC */
2376 status = read16(state, IQM_AF_STDBY__A, &data);
2377 if (status < 0)
2378 goto error;
2379 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2380 status = write16(state, IQM_AF_STDBY__A, data);
2381 if (status < 0)
2382 goto error;
43dd07f7 2383
be44eb28
MCC		 2384 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2385 if (status < 0)
2386 goto error;
43dd07f7 2387
be44eb28
MCC		 2388 /* Disable SCU IF AGC loop */
2389 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
43dd07f7 2390
be44eb28 2391 /* Polarity */
cd7a67a4 2392 if (state->m_if_agc_pol)
be44eb28
MCC		 2393 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2394 else
2395 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2396 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2397 if (status < 0)
2398 goto error;
43dd07f7 2399
be44eb28 2400 /* Write value to output pin */
ab5060cd
MCC		 2401 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2402 p_agc_cfg->output_level);
be44eb28
MCC		 2403 if (status < 0)
2404 goto error;
2405 break;
43dd07f7 2406
be44eb28 2407 case DRXK_AGC_CTRL_OFF:
43dd07f7 2408
be44eb28
MCC		 2409 /* Disable If AGC DAC */
2410 status = read16(state, IQM_AF_STDBY__A, &data);
ea90f011 2411 if (status < 0)
be44eb28
MCC		 2412 goto error;
2413 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2414 status = write16(state, IQM_AF_STDBY__A, data);
2415 if (status < 0)
2416 goto error;
43dd07f7 2417
be44eb28
MCC		 2418 /* Disable SCU IF AGC loop */
2419 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2420 if (status < 0)
2421 goto error;
2422 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2423 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2424 if (status < 0)
2425 goto error;
2426 break;
cd7a67a4 2427 } /* switch (agcSettingsIf->ctrl_mode) */
43dd07f7 2428
be44eb28
MCC		 2429 /* always set the top to support
2430 configurations without if-loop */
cd7a67a4 2431 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
be44eb28
MCC		 2432error:
2433 if (status < 0)
3a4398f5 2434 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2435 return status;
2436}
2437
cd7a67a4
MCC		 2438static int get_qam_signal_to_noise(struct drxk_state *state,
2439 s32 *p_signal_to_noise)
43dd07f7
RM		 2440{
2441 int status = 0;
cd7a67a4 2442 u16 qam_sl_err_power = 0; /* accum. error between
be44eb28 2443 raw and sliced symbols */
cd7a67a4 2444 u32 qam_sl_sig_power = 0; /* used for MER, depends of
ed5452a2 2445 QAM modulation */
cd7a67a4 2446 u32 qam_sl_mer = 0; /* QAM MER */
43dd07f7 2447
2da67501
MCC		 2448 dprintk(1, "\n");
2449
be44eb28 2450 /* MER calculation */
43dd07f7 2451
be44eb28 2452 /* get the register value needed for MER */
cd7a67a4 2453 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
be44eb28 2454 if (status < 0) {
3a4398f5 2455 pr_err("Error %d on %s\n", status, __func__);
be44eb28
MCC		 2456 return -EINVAL;
2457 }
2458
ed5452a2 2459 switch (state->props.modulation) {
be44eb28 2460 case QAM_16:
cd7a67a4 2461 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
be44eb28
MCC		 2462 break;
2463 case QAM_32:
cd7a67a4 2464 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
be44eb28
MCC		 2465 break;
2466 case QAM_64:
cd7a67a4 2467 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
be44eb28
MCC		 2468 break;
2469 case QAM_128:
cd7a67a4 2470 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
be44eb28
MCC		 2471 break;
2472 default:
2473 case QAM_256:
cd7a67a4 2474 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
be44eb28
MCC		 2475 break;
2476 }
2477
cd7a67a4
MCC		 2478 if (qam_sl_err_power > 0) {
2479 qam_sl_mer = log10times100(qam_sl_sig_power) -
2480 log10times100((u32) qam_sl_err_power);
be44eb28 2481 }
cd7a67a4 2482 *p_signal_to_noise = qam_sl_mer;
43dd07f7 2483
43dd07f7
RM		 2484 return status;
2485}
2486
cd7a67a4
MCC		 2487static int get_dvbt_signal_to_noise(struct drxk_state *state,
2488 s32 *p_signal_to_noise)
43dd07f7 2489{
be44eb28 2490 int status;
cd7a67a4
MCC		 2491 u16 reg_data = 0;
2492 u32 eq_reg_td_sqr_err_i = 0;
2493 u32 eq_reg_td_sqr_err_q = 0;
2494 u16 eq_reg_td_sqr_err_exp = 0;
2495 u16 eq_reg_td_tps_pwr_ofs = 0;
2496 u16 eq_reg_td_req_smb_cnt = 0;
2497 u32 tps_cnt = 0;
2498 u32 sqr_err_iq = 0;
ebc7de22
OE		 2499 u32 a = 0;
2500 u32 b = 0;
2501 u32 c = 0;
cd7a67a4
MCC		 2502 u32 i_mer = 0;
2503 u16 transmission_params = 0;
43dd07f7 2504
2da67501 2505 dprintk(1, "\n");
43dd07f7 2506
ab5060cd
MCC		 2507 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2508 &eq_reg_td_tps_pwr_ofs);
be44eb28
MCC		 2509 if (status < 0)
2510 goto error;
ab5060cd
MCC		 2511 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2512 &eq_reg_td_req_smb_cnt);
be44eb28
MCC		 2513 if (status < 0)
2514 goto error;
ab5060cd
MCC		 2515 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2516 &eq_reg_td_sqr_err_exp);
be44eb28
MCC		 2517 if (status < 0)
2518 goto error;
ab5060cd
MCC		 2519 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2520 &reg_data);
be44eb28
MCC		 2521 if (status < 0)
2522 goto error;
2523 /* Extend SQR_ERR_I operational range */
cd7a67a4
MCC		 2524 eq_reg_td_sqr_err_i = (u32) reg_data;
2525 if ((eq_reg_td_sqr_err_exp > 11) &&
2526 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2527 eq_reg_td_sqr_err_i += 0x00010000UL;
be44eb28 2528 }
cd7a67a4 2529 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
be44eb28
MCC		 2530 if (status < 0)
2531 goto error;
2532 /* Extend SQR_ERR_Q operational range */
cd7a67a4
MCC		 2533 eq_reg_td_sqr_err_q = (u32) reg_data;
2534 if ((eq_reg_td_sqr_err_exp > 11) &&
2535 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2536 eq_reg_td_sqr_err_q += 0x00010000UL;
be44eb28 2537
ab5060cd
MCC		 2538 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2539 &transmission_params);
be44eb28
MCC		 2540 if (status < 0)
2541 goto error;
2542
2543 /* Check input data for MER */
2544
2545 /* MER calculation (in 0.1 dB) without math.h */
cd7a67a4
MCC		 2546 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2547 i_mer = 0;
2548 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
be44eb28
MCC		 2549 /* No error at all, this must be the HW reset value
2550 * Apparently no first measurement yet
2551 * Set MER to 0.0 */
cd7a67a4 2552 i_mer = 0;
be44eb28 2553 } else {
cd7a67a4
MCC		 2554 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2555 eq_reg_td_sqr_err_exp;
2556 if ((transmission_params &
be44eb28
MCC		 2557 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2558 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
cd7a67a4 2559 tps_cnt = 17;
be44eb28 2560 else
cd7a67a4 2561 tps_cnt = 68;
be44eb28
MCC		 2562
2563 /* IMER = 100 * log10 (x)
cd7a67a4
MCC		 2564 where x = (eq_reg_td_tps_pwr_ofs^2 *
2565 eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
be44eb28
MCC		 2566
2567 => IMER = a + b -c
cd7a67a4
MCC		 2568 where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2569 b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2570 c = 100 * log10 (sqr_err_iq)
be44eb28
MCC		 2571 */
2572
2573 /* log(x) x = 9bits * 9bits->18 bits */
cd7a67a4
MCC		 2574 a = log10times100(eq_reg_td_tps_pwr_ofs *
2575 eq_reg_td_tps_pwr_ofs);
be44eb28 2576 /* log(x) x = 16bits * 7bits->23 bits */
cd7a67a4 2577 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
be44eb28 2578 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
cd7a67a4 2579 c = log10times100(sqr_err_iq);
be44eb28 2580
cd7a67a4 2581 i_mer = a + b - c;
be44eb28 2582 }
cd7a67a4 2583 *p_signal_to_noise = i_mer;
43dd07f7 2584
be44eb28
MCC		 2585error:
2586 if (status < 0)
3a4398f5 2587 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2588 return status;
2589}
2590
cd7a67a4 2591static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
43dd07f7 2592{
2da67501
MCC		 2593 dprintk(1, "\n");
2594
cd7a67a4
MCC		 2595 *p_signal_to_noise = 0;
2596 switch (state->m_operation_mode) {
43dd07f7 2597 case OM_DVBT:
cd7a67a4 2598 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
43dd07f7
RM		 2599 case OM_QAM_ITU_A:
2600 case OM_QAM_ITU_C:
cd7a67a4 2601 return get_qam_signal_to_noise(state, p_signal_to_noise);
43dd07f7
RM		 2602 default:
2603 break;
2604 }
2605 return 0;
2606}
2607
2608#if 0
cd7a67a4 2609static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
43dd07f7
RM		 2610{
2611 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2612 int status = 0;
2613
2da67501
MCC		 2614 dprintk(1, "\n");
2615
ebc7de22
OE		 2616 static s32 QE_SN[] = {
2617 51, /* QPSK 1/2 */
2618 69, /* QPSK 2/3 */
2619 79, /* QPSK 3/4 */
2620 89, /* QPSK 5/6 */
2621 97, /* QPSK 7/8 */
2622 108, /* 16-QAM 1/2 */
2623 131, /* 16-QAM 2/3 */
2624 146, /* 16-QAM 3/4 */
2625 156, /* 16-QAM 5/6 */
2626 160, /* 16-QAM 7/8 */
2627 165, /* 64-QAM 1/2 */
2628 187, /* 64-QAM 2/3 */
2629 202, /* 64-QAM 3/4 */
2630 216, /* 64-QAM 5/6 */
2631 225, /* 64-QAM 7/8 */
2632 };
43dd07f7 2633
cd7a67a4 2634 *p_quality = 0;
43dd07f7
RM		 2635
2636 do {
cd7a67a4
MCC		 2637 s32 signal_to_noise = 0;
2638 u16 constellation = 0;
2639 u16 code_rate = 0;
2640 u32 signal_to_noise_rel;
2641 u32 ber_quality;
43dd07f7 2642
cd7a67a4 2643 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
ea90f011
MCC		 2644 if (status < 0)
2645 break;
ab5060cd
MCC		 2646 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2647 &constellation);
ea90f011
MCC		 2648 if (status < 0)
2649 break;
cd7a67a4 2650 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
43dd07f7 2651
ab5060cd
MCC		 2652 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2653 &code_rate);
ea90f011
MCC		 2654 if (status < 0)
2655 break;
cd7a67a4 2656 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
43dd07f7 2657
cd7a67a4
MCC		 2658 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2659 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
43dd07f7 2660 break;
cd7a67a4
MCC		 2661 signal_to_noise_rel = signal_to_noise -
2662 QE_SN[constellation * 5 + code_rate];
2663 ber_quality = 100;
2664
2665 if (signal_to_noise_rel < -70)
2666 *p_quality = 0;
2667 else if (signal_to_noise_rel < 30)
2668 *p_quality = ((signal_to_noise_rel + 70) *
2669 ber_quality) / 100;
43dd07f7 2670 else
cd7a67a4 2671 *p_quality = ber_quality;
ebc7de22 2672 } while (0);
43dd07f7
RM		 2673 return 0;
2674};
2675
cd7a67a4 2676static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
43dd07f7
RM		 2677{
2678 int status = 0;
cd7a67a4 2679 *p_quality = 0;
43dd07f7 2680
2da67501
MCC		 2681 dprintk(1, "\n");
2682
43dd07f7 2683 do {
cd7a67a4
MCC		 2684 u32 signal_to_noise = 0;
2685 u32 ber_quality = 100;
2686 u32 signal_to_noise_rel = 0;
43dd07f7 2687
cd7a67a4 2688 status = get_qam_signal_to_noise(state, &signal_to_noise);
ea90f011
MCC		 2689 if (status < 0)
2690 break;
43dd07f7 2691
ed5452a2 2692 switch (state->props.modulation) {
43dd07f7 2693 case QAM_16:
cd7a67a4 2694 signal_to_noise_rel = signal_to_noise - 200;
43dd07f7
RM		 2695 break;
2696 case QAM_32:
cd7a67a4 2697 signal_to_noise_rel = signal_to_noise - 230;
ebc7de22 2698 break; /* Not in NorDig */
43dd07f7 2699 case QAM_64:
cd7a67a4 2700 signal_to_noise_rel = signal_to_noise - 260;
43dd07f7
RM		 2701 break;
2702 case QAM_128:
cd7a67a4 2703 signal_to_noise_rel = signal_to_noise - 290;
43dd07f7
RM		 2704 break;
2705 default:
2706 case QAM_256:
cd7a67a4 2707 signal_to_noise_rel = signal_to_noise - 320;
43dd07f7
RM		 2708 break;
2709 }
2710
cd7a67a4
MCC		 2711 if (signal_to_noise_rel < -70)
2712 *p_quality = 0;
2713 else if (signal_to_noise_rel < 30)
2714 *p_quality = ((signal_to_noise_rel + 70) *
2715 ber_quality) / 100;
43dd07f7 2716 else
cd7a67a4 2717 *p_quality = ber_quality;
ebc7de22 2718 } while (0);
43dd07f7
RM		 2719
2720 return status;
2721}
2722
cd7a67a4 2723static int get_quality(struct drxk_state *state, s32 *p_quality)
43dd07f7 2724{
2da67501
MCC		 2725 dprintk(1, "\n");
2726
cd7a67a4 2727 switch (state->m_operation_mode) {
ebc7de22 2728 case OM_DVBT:
cd7a67a4 2729 return get_dvbt_quality(state, p_quality);
ebc7de22 2730 case OM_QAM_ITU_A:
cd7a67a4 2731 return get_dvbc_quality(state, p_quality);
43dd07f7
RM		 2732 default:
2733 break;
2734 }
2735
2736 return 0;
2737}
2738#endif
2739
2740/* Free data ram in SIO HI */
2741#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2742#define SIO_HI_RA_RAM_USR_END__A 0x420060
2743
2744#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2745#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2746#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2747#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2748
2749#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2750#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2751#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2752
cd7a67a4 2753static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
43dd07f7 2754{
be44eb28 2755 int status = -EINVAL;
43dd07f7 2756
2da67501
MCC		 2757 dprintk(1, "\n");
2758
cd7a67a4 2759 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8 2760 return 0;
cd7a67a4 2761 if (state->m_drxk_state == DRXK_POWERED_DOWN)
be44eb28 2762 goto error;
43dd07f7 2763
f1fe1b75
MCC		 2764 if (state->no_i2c_bridge)
2765 return 0;
43dd07f7 2766
ab5060cd
MCC		 2767 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2768 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
be44eb28
MCC		 2769 if (status < 0)
2770 goto error;
cd7a67a4 2771 if (b_enable_bridge) {
ab5060cd
MCC		 2772 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2773 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
ea90f011 2774 if (status < 0)
be44eb28
MCC		 2775 goto error;
2776 } else {
ab5060cd
MCC		 2777 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2778 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
be44eb28
MCC		 2779 if (status < 0)
2780 goto error;
2781 }
2782
b1cf2019 2783 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
be44eb28
MCC		 2784
2785error:
2786 if (status < 0)
3a4398f5 2787 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2788 return status;
2789}
2790
cd7a67a4
MCC		 2791static int set_pre_saw(struct drxk_state *state,
2792 struct s_cfg_pre_saw *p_pre_saw_cfg)
43dd07f7 2793{
be44eb28 2794 int status = -EINVAL;
43dd07f7 2795
2da67501
MCC		 2796 dprintk(1, "\n");
2797
cd7a67a4
MCC		 2798 if ((p_pre_saw_cfg == NULL)
2799 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
be44eb28 2800 goto error;
43dd07f7 2801
cd7a67a4 2802 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
be44eb28
MCC		 2803error:
2804 if (status < 0)
3a4398f5 2805 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2806 return status;
2807}
2808
cd7a67a4
MCC		 2809static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2810 u16 rom_offset, u16 nr_of_elements, u32 time_out)
43dd07f7 2811{
cd7a67a4
MCC		 2812 u16 bl_status = 0;
2813 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2814 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
ebc7de22 2815 int status;
43dd07f7
RM		 2816 unsigned long end;
2817
2da67501
MCC		 2818 dprintk(1, "\n");
2819
43dd07f7 2820 mutex_lock(&state->mutex);
be44eb28
MCC		 2821 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2822 if (status < 0)
2823 goto error;
2824 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2825 if (status < 0)
2826 goto error;
2827 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2828 if (status < 0)
2829 goto error;
cd7a67a4 2830 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
be44eb28
MCC		 2831 if (status < 0)
2832 goto error;
cd7a67a4 2833 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
be44eb28
MCC		 2834 if (status < 0)
2835 goto error;
2836 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2837 if (status < 0)
2838 goto error;
2839
cd7a67a4 2840 end = jiffies + msecs_to_jiffies(time_out);
43dd07f7 2841 do {
cd7a67a4 2842 status = read16(state, SIO_BL_STATUS__A, &bl_status);
ea90f011 2843 if (status < 0)
be44eb28 2844 goto error;
cd7a67a4
MCC		 2845 } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2846 if (bl_status == 0x1) {
3a4398f5 2847 pr_err("SIO not ready\n");
be44eb28
MCC		 2848 status = -EINVAL;
2849 goto error2;
2850 }
2851error:
2852 if (status < 0)
3a4398f5 2853 pr_err("Error %d on %s\n", status, __func__);
be44eb28 2854error2:
43dd07f7
RM		 2855 mutex_unlock(&state->mutex);
2856 return status;
2857
2858}
2859
cd7a67a4 2860static int adc_sync_measurement(struct drxk_state *state, u16 *count)
43dd07f7
RM		 2861{
2862 u16 data = 0;
2863 int status;
2864
2da67501
MCC		 2865 dprintk(1, "\n");
2866
cd7a67a4 2867 /* start measurement */
be44eb28
MCC		 2868 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2869 if (status < 0)
2870 goto error;
2871 status = write16(state, IQM_AF_START_LOCK__A, 1);
2872 if (status < 0)
2873 goto error;
43dd07f7 2874
be44eb28
MCC		 2875 *count = 0;
2876 status = read16(state, IQM_AF_PHASE0__A, &data);
2877 if (status < 0)
2878 goto error;
2879 if (data == 127)
2880 *count = *count + 1;
2881 status = read16(state, IQM_AF_PHASE1__A, &data);
2882 if (status < 0)
2883 goto error;
2884 if (data == 127)
2885 *count = *count + 1;
2886 status = read16(state, IQM_AF_PHASE2__A, &data);
2887 if (status < 0)
2888 goto error;
2889 if (data == 127)
2890 *count = *count + 1;
2891
2892error:
2893 if (status < 0)
3a4398f5 2894 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2895 return status;
2896}
2897
cd7a67a4 2898static int adc_synchronization(struct drxk_state *state)
43dd07f7
RM		 2899{
2900 u16 count = 0;
2901 int status;
2902
2da67501
MCC		 2903 dprintk(1, "\n");
2904
cd7a67a4 2905 status = adc_sync_measurement(state, &count);
be44eb28
MCC		 2906 if (status < 0)
2907 goto error;
43dd07f7 2908
be44eb28 2909 if (count == 1) {
39c1cb2b 2910 /* Try sampling on a different edge */
cd7a67a4 2911 u16 clk_neg = 0;
43dd07f7 2912
cd7a67a4 2913 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
be44eb28
MCC		 2914 if (status < 0)
2915 goto error;
cd7a67a4 2916 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
be44eb28 2917 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
cd7a67a4
MCC		 2918 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2919 clk_neg |=
be44eb28
MCC		 2920 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2921 } else {
cd7a67a4
MCC		 2922 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2923 clk_neg |=
be44eb28 2924 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
43dd07f7 2925 }
cd7a67a4 2926 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
be44eb28
MCC		 2927 if (status < 0)
2928 goto error;
cd7a67a4 2929 status = adc_sync_measurement(state, &count);
be44eb28
MCC		 2930 if (status < 0)
2931 goto error;
2932 }
43dd07f7 2933
be44eb28
MCC		 2934 if (count < 2)
2935 status = -EINVAL;
2936error:
2937 if (status < 0)
3a4398f5 2938 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 2939 return status;
2940}
2941
cd7a67a4
MCC		 2942static int set_frequency_shifter(struct drxk_state *state,
2943 u16 intermediate_freqk_hz,
2944 s32 tuner_freq_offset, bool is_dtv)
43dd07f7 2945{
cd7a67a4
MCC		 2946 bool select_pos_image = false;
2947 u32 rf_freq_residual = tuner_freq_offset;
2948 u32 fm_frequency_shift = 0;
2949 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2950 u32 adc_freq;
2951 bool adc_flip;
43dd07f7 2952 int status;
cd7a67a4
MCC		 2953 u32 if_freq_actual;
2954 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2955 u32 frequency_shift;
2956 bool image_to_select;
43dd07f7 2957
2da67501
MCC		 2958 dprintk(1, "\n");
2959
43dd07f7 2960 /*
ebc7de22
OE		 2961 Program frequency shifter
2962 No need to account for mirroring on RF
2963 */
cd7a67a4
MCC		 2964 if (is_dtv) {
2965 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2966 (state->m_operation_mode == OM_QAM_ITU_C) ||
2967 (state->m_operation_mode == OM_DVBT))
2968 select_pos_image = true;
ebc7de22 2969 else
cd7a67a4 2970 select_pos_image = false;
43dd07f7 2971 }
cd7a67a4 2972 if (tuner_mirror)
43dd07f7 2973 /* tuner doesn't mirror */
cd7a67a4
MCC		 2974 if_freq_actual = intermediate_freqk_hz +
2975 rf_freq_residual + fm_frequency_shift;
43dd07f7
RM		 2976 else
2977 /* tuner mirrors */
cd7a67a4
MCC		 2978 if_freq_actual = intermediate_freqk_hz -
2979 rf_freq_residual - fm_frequency_shift;
2980 if (if_freq_actual > sampling_frequency / 2) {
43dd07f7 2981 /* adc mirrors */
cd7a67a4
MCC		 2982 adc_freq = sampling_frequency - if_freq_actual;
2983 adc_flip = true;
43dd07f7
RM		 2984 } else {
2985 /* adc doesn't mirror */
cd7a67a4
MCC		 2986 adc_freq = if_freq_actual;
2987 adc_flip = false;
43dd07f7
RM		 2988 }
2989
cd7a67a4
MCC		 2990 frequency_shift = adc_freq;
2991 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2992 adc_flip ^ select_pos_image;
2993 state->m_iqm_fs_rate_ofs =
2994 Frac28a((frequency_shift), sampling_frequency);
43dd07f7 2995
cd7a67a4
MCC		 2996 if (image_to_select)
2997 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
43dd07f7
RM		 2998
2999 /* Program frequency shifter with tuner offset compensation */
cd7a67a4 3000 /* frequency_shift += tuner_freq_offset; TODO */
5e66b878 3001 status = write32(state, IQM_FS_RATE_OFS_LO__A,
cd7a67a4 3002 state->m_iqm_fs_rate_ofs);
be44eb28 3003 if (status < 0)
3a4398f5 3004 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3005 return status;
3006}
3007
cd7a67a4 3008static int init_agc(struct drxk_state *state, bool is_dtv)
43dd07f7 3009{
cd7a67a4
MCC		 3010 u16 ingain_tgt = 0;
3011 u16 ingain_tgt_min = 0;
3012 u16 ingain_tgt_max = 0;
3013 u16 clp_cyclen = 0;
3014 u16 clp_sum_min = 0;
3015 u16 clp_dir_to = 0;
3016 u16 sns_sum_min = 0;
3017 u16 sns_sum_max = 0;
3018 u16 clp_sum_max = 0;
3019 u16 sns_dir_to = 0;
3020 u16 ki_innergain_min = 0;
3021 u16 if_iaccu_hi_tgt = 0;
3022 u16 if_iaccu_hi_tgt_min = 0;
3023 u16 if_iaccu_hi_tgt_max = 0;
ebc7de22 3024 u16 data = 0;
cd7a67a4
MCC		 3025 u16 fast_clp_ctrl_delay = 0;
3026 u16 clp_ctrl_mode = 0;
43dd07f7
RM		 3027 int status = 0;
3028
2da67501
MCC		 3029 dprintk(1, "\n");
3030
be44eb28 3031 /* Common settings */
cd7a67a4
MCC		 3032 sns_sum_max = 1023;
3033 if_iaccu_hi_tgt_min = 2047;
3034 clp_cyclen = 500;
3035 clp_sum_max = 1023;
be44eb28 3036
f1b82970 3037 /* AGCInit() not available for DVBT; init done in microcode */
cd7a67a4 3038 if (!is_qam(state)) {
3a4398f5
MCC		 3039 pr_err("%s: mode %d is not DVB-C\n",
3040 __func__, state->m_operation_mode);
f1b82970 3041 return -EINVAL;
be44eb28 3042 }
f1b82970
MCC		 3043
3044 /* FIXME: Analog TV AGC require different settings */
3045
3046 /* Standard specific settings */
cd7a67a4
MCC		 3047 clp_sum_min = 8;
3048 clp_dir_to = (u16) -9;
3049 clp_ctrl_mode = 0;
3050 sns_sum_min = 8;
3051 sns_dir_to = (u16) -9;
3052 ki_innergain_min = (u16) -1030;
3053 if_iaccu_hi_tgt_max = 0x2380;
3054 if_iaccu_hi_tgt = 0x2380;
3055 ingain_tgt_min = 0x0511;
3056 ingain_tgt = 0x0511;
3057 ingain_tgt_max = 5119;
3058 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
f1b82970 3059
ab5060cd
MCC		 3060 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3061 fast_clp_ctrl_delay);
be44eb28
MCC		 3062 if (status < 0)
3063 goto error;
ea90f011 3064
cd7a67a4 3065 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
be44eb28
MCC		 3066 if (status < 0)
3067 goto error;
cd7a67a4 3068 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
be44eb28
MCC		 3069 if (status < 0)
3070 goto error;
cd7a67a4 3071 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
be44eb28
MCC		 3072 if (status < 0)
3073 goto error;
cd7a67a4 3074 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
be44eb28
MCC		 3075 if (status < 0)
3076 goto error;
ab5060cd
MCC		 3077 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3078 if_iaccu_hi_tgt_min);
be44eb28
MCC		 3079 if (status < 0)
3080 goto error;
ab5060cd
MCC		 3081 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3082 if_iaccu_hi_tgt_max);
be44eb28
MCC		 3083 if (status < 0)
3084 goto error;
3085 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3086 if (status < 0)
3087 goto error;
3088 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3089 if (status < 0)
3090 goto error;
3091 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3092 if (status < 0)
3093 goto error;
3094 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3095 if (status < 0)
3096 goto error;
cd7a67a4 3097 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
be44eb28
MCC		 3098 if (status < 0)
3099 goto error;
cd7a67a4 3100 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
be44eb28
MCC		 3101 if (status < 0)
3102 goto error;
ea90f011 3103
ab5060cd
MCC		 3104 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3105 ki_innergain_min);
be44eb28
MCC		 3106 if (status < 0)
3107 goto error;
ab5060cd
MCC		 3108 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3109 if_iaccu_hi_tgt);
be44eb28
MCC		 3110 if (status < 0)
3111 goto error;
cd7a67a4 3112 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
be44eb28
MCC		 3113 if (status < 0)
3114 goto error;
ea90f011 3115
be44eb28
MCC		 3116 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3117 if (status < 0)
3118 goto error;
3119 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3120 if (status < 0)
3121 goto error;
3122 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3123 if (status < 0)
3124 goto error;
ea90f011 3125
be44eb28
MCC		 3126 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3127 if (status < 0)
3128 goto error;
cd7a67a4 3129 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
be44eb28
MCC		 3130 if (status < 0)
3131 goto error;
cd7a67a4 3132 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
be44eb28
MCC		 3133 if (status < 0)
3134 goto error;
cd7a67a4 3135 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
be44eb28
MCC		 3136 if (status < 0)
3137 goto error;
cd7a67a4 3138 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
be44eb28
MCC		 3139 if (status < 0)
3140 goto error;
3141 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3142 if (status < 0)
3143 goto error;
3144 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3145 if (status < 0)
3146 goto error;
3147 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3148 if (status < 0)
3149 goto error;
3150 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3151 if (status < 0)
3152 goto error;
3153 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3154 if (status < 0)
3155 goto error;
3156 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3157 if (status < 0)
3158 goto error;
3159 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3160 if (status < 0)
3161 goto error;
3162 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3163 if (status < 0)
3164 goto error;
3165 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3166 if (status < 0)
3167 goto error;
3168 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3169 if (status < 0)
3170 goto error;
3171 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3172 if (status < 0)
3173 goto error;
3174 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3175 if (status < 0)
3176 goto error;
3177 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3178 if (status < 0)
3179 goto error;
3180 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3181 if (status < 0)
3182 goto error;
43dd07f7 3183
be44eb28
MCC		 3184 /* Initialize inner-loop KI gain factors */
3185 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3186 if (status < 0)
3187 goto error;
f1b82970
MCC		 3188
3189 data = 0x0657;
3190 data &= ~SCU_RAM_AGC_KI_RF__M;
3191 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3192 data &= ~SCU_RAM_AGC_KI_IF__M;
3193 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3194
be44eb28
MCC		 3195 status = write16(state, SCU_RAM_AGC_KI__A, data);
3196error:
3197 if (status < 0)
3a4398f5 3198 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3199 return status;
3200}
3201
cd7a67a4 3202static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
43dd07f7
RM		 3203{
3204 int status;
3205
2da67501 3206 dprintk(1, "\n");
cd7a67a4 3207 if (packet_err == NULL)
be44eb28
MCC		 3208 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3209 else
ab5060cd
MCC		 3210 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3211 packet_err);
be44eb28 3212 if (status < 0)
3a4398f5 3213 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3214 return status;
3215}
3216
cd7a67a4 3217static int dvbt_sc_command(struct drxk_state *state,
43dd07f7
RM		 3218 u16 cmd, u16 subcmd,
3219 u16 param0, u16 param1, u16 param2,
3220 u16 param3, u16 param4)
3221{
cd7a67a4
MCC		 3222 u16 cur_cmd = 0;
3223 u16 err_code = 0;
3224 u16 retry_cnt = 0;
3225 u16 sc_exec = 0;
ebc7de22 3226 int status;
43dd07f7 3227
2da67501 3228 dprintk(1, "\n");
cd7a67a4
MCC		 3229 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3230 if (sc_exec != 1) {
43dd07f7 3231 /* SC is not running */
be44eb28 3232 status = -EINVAL;
43dd07f7 3233 }
be44eb28
MCC		 3234 if (status < 0)
3235 goto error;
43dd07f7
RM		 3236
3237 /* Wait until sc is ready to receive command */
cd7a67a4 3238 retry_cnt = 0;
43dd07f7 3239 do {
b72852ba 3240 usleep_range(1000, 2000);
cd7a67a4
MCC		 3241 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3242 retry_cnt++;
3243 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3244 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
be44eb28
MCC		 3245 goto error;
3246
43dd07f7
RM		 3247 /* Write sub-command */
3248 switch (cmd) {
3249 /* All commands using sub-cmd */
3250 case OFDM_SC_RA_RAM_CMD_PROC_START:
3251 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3252 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
be44eb28
MCC		 3253 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3254 if (status < 0)
3255 goto error;
43dd07f7
RM		 3256 break;
3257 default:
3258 /* Do nothing */
3259 break;
be44eb28 3260 }
43dd07f7
RM		 3261
3262 /* Write needed parameters and the command */
2f60f13c 3263 status = 0;
43dd07f7
RM		 3264 switch (cmd) {
3265 /* All commands using 5 parameters */
3266 /* All commands using 4 parameters */
3267 /* All commands using 3 parameters */
3268 /* All commands using 2 parameters */
3269 case OFDM_SC_RA_RAM_CMD_PROC_START:
3270 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3271 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
2f60f13c 3272 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
43dd07f7 3273 /* All commands using 1 parameters */
06eeefe8 3274 /* fall through */
43dd07f7
RM		 3275 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3276 case OFDM_SC_RA_RAM_CMD_USER_IO:
2f60f13c 3277 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
43dd07f7 3278 /* All commands using 0 parameters */
06eeefe8 3279 /* fall through */
43dd07f7
RM		 3280 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3281 case OFDM_SC_RA_RAM_CMD_NULL:
3282 /* Write command */
2f60f13c 3283 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
43dd07f7
RM		 3284 break;
3285 default:
3286 /* Unknown command */
be44eb28
MCC		 3287 status = -EINVAL;
3288 }
3289 if (status < 0)
3290 goto error;
43dd07f7
RM		 3291
3292 /* Wait until sc is ready processing command */
cd7a67a4 3293 retry_cnt = 0;
ebc7de22 3294 do {
b72852ba 3295 usleep_range(1000, 2000);
cd7a67a4
MCC		 3296 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3297 retry_cnt++;
3298 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3299 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
be44eb28 3300 goto error;
43dd07f7
RM		 3301
3302 /* Check for illegal cmd */
cd7a67a4
MCC		 3303 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3304 if (err_code == 0xFFFF) {
43dd07f7 3305 /* illegal command */
be44eb28 3306 status = -EINVAL;
43dd07f7 3307 }
be44eb28
MCC		 3308 if (status < 0)
3309 goto error;
43dd07f7 3310
39c1cb2b 3311 /* Retrieve results parameters from SC */
43dd07f7
RM		 3312 switch (cmd) {
3313 /* All commands yielding 5 results */
3314 /* All commands yielding 4 results */
3315 /* All commands yielding 3 results */
3316 /* All commands yielding 2 results */
3317 /* All commands yielding 1 result */
3318 case OFDM_SC_RA_RAM_CMD_USER_IO:
3319 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
be44eb28 3320 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
43dd07f7
RM		 3321 /* All commands yielding 0 results */
3322 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3323 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3324 case OFDM_SC_RA_RAM_CMD_PROC_START:
3325 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3326 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3327 case OFDM_SC_RA_RAM_CMD_NULL:
3328 break;
3329 default:
3330 /* Unknown command */
be44eb28 3331 status = -EINVAL;
43dd07f7 3332 break;
ebc7de22 3333 } /* switch (cmd->cmd) */
be44eb28
MCC		 3334error:
3335 if (status < 0)
3a4398f5 3336 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3337 return status;
3338}
3339
cd7a67a4 3340static int power_up_dvbt(struct drxk_state *state)
43dd07f7 3341{
cd7a67a4 3342 enum drx_power_mode power_mode = DRX_POWER_UP;
43dd07f7
RM		 3343 int status;
3344
2da67501 3345 dprintk(1, "\n");
cd7a67a4 3346 status = ctrl_power_mode(state, &power_mode);
be44eb28 3347 if (status < 0)
3a4398f5 3348 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3349 return status;
3350}
3351
cd7a67a4 3352static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
43dd07f7 3353{
ebc7de22
OE		 3354 int status;
3355
2da67501 3356 dprintk(1, "\n");
5a7f7b79 3357 if (*enabled)
5e66b878 3358 status = write16(state, IQM_CF_BYPASSDET__A, 0);
ebc7de22 3359 else
5e66b878 3360 status = write16(state, IQM_CF_BYPASSDET__A, 1);
be44eb28 3361 if (status < 0)
3a4398f5 3362 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 3363 return status;
43dd07f7 3364}
ebc7de22
OE		 3365
3366#define DEFAULT_FR_THRES_8K 4000
cd7a67a4 3367static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
43dd07f7
RM		 3368{
3369
ebc7de22
OE		 3370 int status;
3371
2da67501 3372 dprintk(1, "\n");
5a7f7b79 3373 if (*enabled) {
ebc7de22 3374 /* write mask to 1 */
5e66b878 3375 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
ebc7de22
OE		 3376 DEFAULT_FR_THRES_8K);
3377 } else {
3378 /* write mask to 0 */
5e66b878 3379 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
ebc7de22 3380 }
be44eb28 3381 if (status < 0)
3a4398f5 3382 pr_err("Error %d on %s\n", status, __func__);
ebc7de22
OE		 3383
3384 return status;
43dd07f7
RM		 3385}
3386
cd7a67a4 3387static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
ab5060cd 3388 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
43dd07f7 3389{
ebc7de22 3390 u16 data = 0;
43dd07f7 3391 int status;
43dd07f7 3392
2da67501 3393 dprintk(1, "\n");
be44eb28
MCC		 3394 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3395 if (status < 0)
3396 goto error;
3397
cd7a67a4 3398 switch (echo_thres->fft_mode) {
be44eb28
MCC		 3399 case DRX_FFTMODE_2K:
3400 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
cd7a67a4 3401 data |= ((echo_thres->threshold <<
be44eb28
MCC		 3402 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3403 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
320ed23e 3404 break;
be44eb28
MCC		 3405 case DRX_FFTMODE_8K:
3406 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
cd7a67a4 3407 data |= ((echo_thres->threshold <<
be44eb28
MCC		 3408 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3409 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
320ed23e 3410 break;
be44eb28
MCC		 3411 default:
3412 return -EINVAL;
be44eb28 3413 }
ebc7de22 3414
be44eb28
MCC		 3415 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3416error:
3417 if (status < 0)
3a4398f5 3418 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 3419 return status;
43dd07f7
RM		 3420}
3421
cd7a67a4
MCC		 3422static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3423 enum drxk_cfg_dvbt_sqi_speed *speed)
43dd07f7 3424{
be44eb28 3425 int status = -EINVAL;
43dd07f7 3426
2da67501
MCC		 3427 dprintk(1, "\n");
3428
43dd07f7
RM		 3429 switch (*speed) {
3430 case DRXK_DVBT_SQI_SPEED_FAST:
3431 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3432 case DRXK_DVBT_SQI_SPEED_SLOW:
3433 break;
3434 default:
be44eb28 3435 goto error;
43dd07f7 3436 }
5e66b878 3437 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
ebc7de22 3438 (u16) *speed);
be44eb28
MCC		 3439error:
3440 if (status < 0)
3a4398f5 3441 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3442 return status;
3443}
3444
3445/*============================================================================*/
3446
34eb9751 3447/*
43dd07f7
RM		 3448* \brief Activate DVBT specific presets
3449* \param demod instance of demodulator.
3450* \return DRXStatus_t.
3451*
3452* Called in DVBTSetStandard
3453*
3454*/
cd7a67a4 3455static int dvbt_activate_presets(struct drxk_state *state)
43dd07f7 3456{
ebc7de22 3457 int status;
be44eb28
MCC		 3458 bool setincenable = false;
3459 bool setfrenable = true;
ebc7de22 3460
cd7a67a4
MCC		 3461 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3462 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
ebc7de22 3463
2da67501 3464 dprintk(1, "\n");
cd7a67a4 3465 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
be44eb28
MCC		 3466 if (status < 0)
3467 goto error;
cd7a67a4 3468 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
be44eb28
MCC		 3469 if (status < 0)
3470 goto error;
cd7a67a4 3471 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
be44eb28
MCC		 3472 if (status < 0)
3473 goto error;
cd7a67a4 3474 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
be44eb28
MCC		 3475 if (status < 0)
3476 goto error;
ab5060cd
MCC		 3477 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3478 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
be44eb28
MCC		 3479error:
3480 if (status < 0)
3a4398f5 3481 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 3482 return status;
43dd07f7 3483}
ebc7de22 3484
43dd07f7
RM		 3485/*============================================================================*/
3486
34eb9751 3487/*
43dd07f7
RM		 3488* \brief Initialize channelswitch-independent settings for DVBT.
3489* \param demod instance of demodulator.
3490* \return DRXStatus_t.
3491*
3492* For ROM code channel filter taps are loaded from the bootloader. For microcode
3493* the DVB-T taps from the drxk_filters.h are used.
3494*/
cd7a67a4
MCC		 3495static int set_dvbt_standard(struct drxk_state *state,
3496 enum operation_mode o_mode)
43dd07f7 3497{
cd7a67a4 3498 u16 cmd_result = 0;
ebc7de22
OE		 3499 u16 data = 0;
3500 int status;
43dd07f7 3501
2da67501 3502 dprintk(1, "\n");
43dd07f7 3503
cd7a67a4 3504 power_up_dvbt(state);
be44eb28 3505 /* added antenna switch */
cd7a67a4 3506 switch_antenna_to_dvbt(state);
be44eb28 3507 /* send OFDM reset command */
ab5060cd
MCC		 3508 status = scu_command(state,
3509 SCU_RAM_COMMAND_STANDARD_OFDM
3510 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3511 0, NULL, 1, &cmd_result);
be44eb28
MCC		 3512 if (status < 0)
3513 goto error;
43dd07f7 3514
be44eb28 3515 /* send OFDM setenv command */
ab5060cd
MCC		 3516 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3517 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3518 0, NULL, 1, &cmd_result);
be44eb28
MCC		 3519 if (status < 0)
3520 goto error;
43dd07f7 3521
be44eb28
MCC		 3522 /* reset datapath for OFDM, processors first */
3523 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3524 if (status < 0)
3525 goto error;
3526 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3527 if (status < 0)
3528 goto error;
3529 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3530 if (status < 0)
3531 goto error;
43dd07f7 3532
be44eb28
MCC		 3533 /* IQM setup */
3534 /* synchronize on ofdstate->m_festart */
3535 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3536 if (status < 0)
3537 goto error;
3538 /* window size for clipping ADC detection */
3539 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3540 if (status < 0)
3541 goto error;
3542 /* window size for for sense pre-SAW detection */
3543 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3544 if (status < 0)
3545 goto error;
3546 /* sense threshold for sense pre-SAW detection */
3547 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3548 if (status < 0)
3549 goto error;
cd7a67a4 3550 status = set_iqm_af(state, true);
be44eb28
MCC		 3551 if (status < 0)
3552 goto error;
43dd07f7 3553
be44eb28
MCC		 3554 status = write16(state, IQM_AF_AGC_RF__A, 0);
3555 if (status < 0)
3556 goto error;
43dd07f7 3557
be44eb28
MCC		 3558 /* Impulse noise cruncher setup */
3559 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3560 if (status < 0)
3561 goto error;
3562 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3563 if (status < 0)
3564 goto error;
3565 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3566 if (status < 0)
3567 goto error;
43dd07f7 3568
be44eb28
MCC		 3569 status = write16(state, IQM_RC_STRETCH__A, 16);
3570 if (status < 0)
3571 goto error;
ab5060cd 3572 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
be44eb28
MCC		 3573 if (status < 0)
3574 goto error;
3575 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3576 if (status < 0)
3577 goto error;
3578 status = write16(state, IQM_CF_SCALE__A, 1600);
3579 if (status < 0)
3580 goto error;
3581 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3582 if (status < 0)
3583 goto error;
43dd07f7 3584
be44eb28
MCC		 3585 /* virtual clipping threshold for clipping ADC detection */
3586 status = write16(state, IQM_AF_CLP_TH__A, 448);
3587 if (status < 0)
3588 goto error;
3589 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3590 if (status < 0)
3591 goto error;
43dd07f7 3592
ab5060cd
MCC		 3593 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3594 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
be44eb28
MCC		 3595 if (status < 0)
3596 goto error;
43dd07f7 3597
be44eb28
MCC		 3598 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3599 if (status < 0)
3600 goto error;
3601 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3602 if (status < 0)
3603 goto error;
3604 /* enable power measurement interrupt */
3605 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3606 if (status < 0)
3607 goto error;
3608 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3609 if (status < 0)
3610 goto error;
43dd07f7 3611
be44eb28 3612 /* IQM will not be reset from here, sync ADC and update/init AGC */
cd7a67a4 3613 status = adc_synchronization(state);
be44eb28
MCC		 3614 if (status < 0)
3615 goto error;
cd7a67a4 3616 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
be44eb28
MCC		 3617 if (status < 0)
3618 goto error;
43dd07f7 3619
be44eb28
MCC		 3620 /* Halt SCU to enable safe non-atomic accesses */
3621 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3622 if (status < 0)
3623 goto error;
43dd07f7 3624
cd7a67a4 3625 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
be44eb28
MCC		 3626 if (status < 0)
3627 goto error;
cd7a67a4 3628 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
be44eb28
MCC		 3629 if (status < 0)
3630 goto error;
43dd07f7 3631
be44eb28
MCC		 3632 /* Set Noise Estimation notch width and enable DC fix */
3633 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3634 if (status < 0)
3635 goto error;
3636 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3637 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3638 if (status < 0)
3639 goto error;
43dd07f7 3640
be44eb28
MCC		 3641 /* Activate SCU to enable SCU commands */
3642 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3643 if (status < 0)
3644 goto error;
43dd07f7 3645
cd7a67a4
MCC		 3646 if (!state->m_drxk_a3_rom_code) {
3647 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
ab5060cd
MCC		 3648 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3649 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
be44eb28
MCC		 3650 if (status < 0)
3651 goto error;
3652 }
43dd07f7 3653
be44eb28 3654 /* OFDM_SC setup */
43dd07f7 3655#ifdef COMPILE_FOR_NONRT
be44eb28
MCC		 3656 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3657 if (status < 0)
3658 goto error;
3659 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3660 if (status < 0)
3661 goto error;
43dd07f7
RM		 3662#endif
3663
be44eb28
MCC		 3664 /* FEC setup */
3665 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3666 if (status < 0)
3667 goto error;
43dd07f7
RM		 3668
3669
3670#ifdef COMPILE_FOR_NONRT
be44eb28
MCC		 3671 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3672 if (status < 0)
3673 goto error;
43dd07f7 3674#else
be44eb28
MCC		 3675 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3676 if (status < 0)
3677 goto error;
43dd07f7 3678#endif
be44eb28
MCC		 3679 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3680 if (status < 0)
3681 goto error;
43dd07f7 3682
be44eb28 3683 /* Setup MPEG bus */
cd7a67a4 3684 status = mpegts_dto_setup(state, OM_DVBT);
ebc7de22 3685 if (status < 0)
be44eb28
MCC		 3686 goto error;
3687 /* Set DVBT Presets */
cd7a67a4 3688 status = dvbt_activate_presets(state);
be44eb28
MCC		 3689 if (status < 0)
3690 goto error;
43dd07f7 3691
be44eb28
MCC		 3692error:
3693 if (status < 0)
3a4398f5 3694 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 3695 return status;
3696}
3697
3698/*============================================================================*/
34eb9751 3699/*
cd7a67a4 3700* \brief start dvbt demodulating for channel.
43dd07f7
RM		 3701* \param demod instance of demodulator.
3702* \return DRXStatus_t.
3703*/
cd7a67a4 3704static int dvbt_start(struct drxk_state *state)
43dd07f7 3705{
ebc7de22
OE		 3706 u16 param1;
3707 int status;
cd7a67a4 3708 /* drxk_ofdm_sc_cmd_t scCmd; */
ebc7de22 3709
2da67501 3710 dprintk(1, "\n");
cd7a67a4 3711 /* start correct processes to get in lock */
ebc7de22 3712 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
be44eb28 3713 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
ab5060cd
MCC		 3714 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3715 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3716 0, 0, 0);
be44eb28
MCC		 3717 if (status < 0)
3718 goto error;
cd7a67a4
MCC		 3719 /* start FEC OC */
3720 status = mpegts_start(state);
be44eb28
MCC		 3721 if (status < 0)
3722 goto error;
3723 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3724 if (status < 0)
3725 goto error;
3726error:
3727 if (status < 0)
3a4398f5 3728 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 3729 return status;
43dd07f7
RM		 3730}
3731
3732
3733/*============================================================================*/
3734
34eb9751 3735/*
43dd07f7
RM		 3736* \brief Set up dvbt demodulator for channel.
3737* \param demod instance of demodulator.
3738* \return DRXStatus_t.
3739* // original DVBTSetChannel()
3740*/
cd7a67a4
MCC		 3741static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3742 s32 tuner_freq_offset)
43dd07f7 3743{
cd7a67a4
MCC		 3744 u16 cmd_result = 0;
3745 u16 transmission_params = 0;
3746 u16 operation_mode = 0;
3747 u32 iqm_rc_rate_ofs = 0;
ebc7de22
OE		 3748 u32 bandwidth = 0;
3749 u16 param1;
43dd07f7
RM		 3750 int status;
3751
ab5060cd
MCC		 3752 dprintk(1, "IF =%d, TFO = %d\n",
3753 intermediate_freqk_hz, tuner_freq_offset);
43dd07f7 3754
ab5060cd
MCC		 3755 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3756 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3757 0, NULL, 1, &cmd_result);
be44eb28
MCC		 3758 if (status < 0)
3759 goto error;
43dd07f7 3760
be44eb28
MCC		 3761 /* Halt SCU to enable safe non-atomic accesses */
3762 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3763 if (status < 0)
3764 goto error;
43dd07f7 3765
be44eb28
MCC		 3766 /* Stop processors */
3767 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3768 if (status < 0)
3769 goto error;
3770 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3771 if (status < 0)
3772 goto error;
43dd07f7 3773
be44eb28
MCC		 3774 /* Mandatory fix, always stop CP, required to set spl offset back to
3775 hardware default (is set to 0 by ucode during pilot detection */
3776 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3777 if (status < 0)
3778 goto error;
43dd07f7 3779
ab5060cd 3780 /*== Write channel settings to device ================================*/
43dd07f7 3781
be44eb28 3782 /* mode */
ed5452a2 3783 switch (state->props.transmission_mode) {
be44eb28
MCC		 3784 case TRANSMISSION_MODE_AUTO:
3785 default:
cd7a67a4 3786 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
06eeefe8
MCC		 3787 /* try first guess DRX_FFTMODE_8K */
3788 /* fall through */
be44eb28 3789 case TRANSMISSION_MODE_8K:
cd7a67a4 3790 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
320ed23e 3791 break;
be44eb28 3792 case TRANSMISSION_MODE_2K:
cd7a67a4 3793 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
320ed23e 3794 break;
be44eb28 3795 }
43dd07f7 3796
be44eb28 3797 /* guard */
ed5452a2 3798 switch (state->props.guard_interval) {
be44eb28
MCC		 3799 default:
3800 case GUARD_INTERVAL_AUTO:
cd7a67a4 3801 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
06eeefe8
MCC		 3802 /* try first guess DRX_GUARD_1DIV4 */
3803 /* fall through */
be44eb28 3804 case GUARD_INTERVAL_1_4:
cd7a67a4 3805 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
320ed23e 3806 break;
be44eb28 3807 case GUARD_INTERVAL_1_32:
cd7a67a4 3808 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
320ed23e 3809 break;
be44eb28 3810 case GUARD_INTERVAL_1_16:
cd7a67a4 3811 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
320ed23e 3812 break;
be44eb28 3813 case GUARD_INTERVAL_1_8:
cd7a67a4 3814 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
320ed23e 3815 break;
be44eb28 3816 }
43dd07f7 3817
be44eb28 3818 /* hierarchy */
ed5452a2 3819 switch (state->props.hierarchy) {
be44eb28
MCC		 3820 case HIERARCHY_AUTO:
3821 case HIERARCHY_NONE:
3822 default:
cd7a67a4 3823 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
06eeefe8 3824 /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
cd7a67a4 3825 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
06eeefe8 3826 /* fall through */
be44eb28 3827 case HIERARCHY_1:
cd7a67a4 3828 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
be44eb28
MCC		 3829 break;
3830 case HIERARCHY_2:
cd7a67a4 3831 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
be44eb28
MCC		 3832 break;
3833 case HIERARCHY_4:
cd7a67a4 3834 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
be44eb28
MCC		 3835 break;
3836 }
3837
3838
ed5452a2
MCC		 3839 /* modulation */
3840 switch (state->props.modulation) {
be44eb28
MCC		 3841 case QAM_AUTO:
3842 default:
cd7a67a4 3843 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
06eeefe8
MCC		 3844 /* try first guess DRX_CONSTELLATION_QAM64 */
3845 /* fall through */
be44eb28 3846 case QAM_64:
cd7a67a4 3847 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
be44eb28
MCC		 3848 break;
3849 case QPSK:
cd7a67a4 3850 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
be44eb28
MCC		 3851 break;
3852 case QAM_16:
cd7a67a4 3853 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
be44eb28
MCC		 3854 break;
3855 }
43dd07f7 3856#if 0
39c1cb2b 3857 /* No hierarchical channels support in BDA */
be44eb28
MCC		 3858 /* Priority (only for hierarchical channels) */
3859 switch (channel->priority) {
3860 case DRX_PRIORITY_LOW:
cd7a67a4
MCC		 3861 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3862 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
be44eb28
MCC		 3863 OFDM_EC_SB_PRIOR_LO);
3864 break;
3865 case DRX_PRIORITY_HIGH:
cd7a67a4
MCC		 3866 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3867 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
be44eb28
MCC		 3868 OFDM_EC_SB_PRIOR_HI));
3869 break;
3870 case DRX_PRIORITY_UNKNOWN: /* fall through */
3871 default:
3872 status = -EINVAL;
3873 goto error;
3874 }
3875#else
3876 /* Set Priorty high */
cd7a67a4 3877 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
be44eb28
MCC		 3878 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3879 if (status < 0)
3880 goto error;
43dd07f7
RM		 3881#endif
3882
be44eb28 3883 /* coderate */
ed5452a2 3884 switch (state->props.code_rate_HP) {
be44eb28
MCC		 3885 case FEC_AUTO:
3886 default:
cd7a67a4 3887 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
06eeefe8
MCC		 3888 /* try first guess DRX_CODERATE_2DIV3 */
3889 /* fall through */
be44eb28 3890 case FEC_2_3:
cd7a67a4 3891 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
be44eb28
MCC		 3892 break;
3893 case FEC_1_2:
cd7a67a4 3894 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
be44eb28
MCC		 3895 break;
3896 case FEC_3_4:
cd7a67a4 3897 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
be44eb28
MCC		 3898 break;
3899 case FEC_5_6:
cd7a67a4 3900 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
be44eb28
MCC		 3901 break;
3902 case FEC_7_8:
cd7a67a4 3903 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
be44eb28
MCC		 3904 break;
3905 }
43dd07f7 3906
ab5060cd
MCC		 3907 /*
3908 * SAW filter selection: normaly not necesarry, but if wanted
3909 * the application can select a SAW filter via the driver by
3910 * using UIOs
3911 */
3912
be44eb28
MCC		 3913 /* First determine real bandwidth (Hz) */
3914 /* Also set delay for impulse noise cruncher */
ab5060cd
MCC		 3915 /*
3916 * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3917 * changed by SC for fix for some 8K,1/8 guard but is restored by
3918 * InitEC and ResetEC functions
3919 */
ed5452a2
MCC		 3920 switch (state->props.bandwidth_hz) {
3921 case 0:
3922 state->props.bandwidth_hz = 8000000;
06eeefe8 3923 /* fall through */
ed5452a2 3924 case 8000000:
be44eb28 3925 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
ab5060cd
MCC		 3926 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3927 3052);
be44eb28
MCC		 3928 if (status < 0)
3929 goto error;
3930 /* cochannel protection for PAL 8 MHz */
ab5060cd
MCC		 3931 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3932 7);
be44eb28
MCC		 3933 if (status < 0)
3934 goto error;
ab5060cd
MCC		 3935 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3936 7);
be44eb28
MCC		 3937 if (status < 0)
3938 goto error;
ab5060cd
MCC		 3939 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3940 7);
be44eb28
MCC		 3941 if (status < 0)
3942 goto error;
ab5060cd
MCC		 3943 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3944 1);
be44eb28
MCC		 3945 if (status < 0)
3946 goto error;
3947 break;
ed5452a2 3948 case 7000000:
be44eb28 3949 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
ab5060cd
MCC		 3950 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3951 3491);
be44eb28
MCC		 3952 if (status < 0)
3953 goto error;
3954 /* cochannel protection for PAL 7 MHz */
ab5060cd
MCC		 3955 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3956 8);
be44eb28
MCC		 3957 if (status < 0)
3958 goto error;
ab5060cd
MCC		 3959 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3960 8);
be44eb28
MCC		 3961 if (status < 0)
3962 goto error;
ab5060cd
MCC		 3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3964 4);
be44eb28
MCC		 3965 if (status < 0)
3966 goto error;
ab5060cd
MCC		 3967 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3968 1);
be44eb28
MCC		 3969 if (status < 0)
3970 goto error;
3971 break;
ed5452a2 3972 case 6000000:
be44eb28 3973 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
ab5060cd
MCC		 3974 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3975 4073);
be44eb28
MCC		 3976 if (status < 0)
3977 goto error;
3978 /* cochannel protection for NTSC 6 MHz */
ab5060cd
MCC		 3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3980 19);
be44eb28
MCC		 3981 if (status < 0)
3982 goto error;
ab5060cd
MCC		 3983 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3984 19);
be44eb28
MCC		 3985 if (status < 0)
3986 goto error;
ab5060cd
MCC		 3987 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3988 14);
be44eb28
MCC		 3989 if (status < 0)
3990 goto error;
ab5060cd
MCC		 3991 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3992 1);
be44eb28
MCC		 3993 if (status < 0)
3994 goto error;
3995 break;
3996 default:
3997 status = -EINVAL;
3998 goto error;
3999 }
43dd07f7 4000
cd7a67a4 4001 if (iqm_rc_rate_ofs == 0) {
be44eb28
MCC		 4002 /* Now compute IQM_RC_RATE_OFS
4003 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4004 =>
4005 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4006 */
4007 /* (SysFreq / BandWidth) * (2^28) */
ab5060cd
MCC		 4008 /*
4009 * assert (MAX(sysClk)/MIN(bandwidth) < 16)
4010 * => assert(MAX(sysClk) < 16*MIN(bandwidth))
4011 * => assert(109714272 > 48000000) = true
4012 * so Frac 28 can be used
4013 */
cd7a67a4
MCC		 4014 iqm_rc_rate_ofs = Frac28a((u32)
4015 ((state->m_sys_clock_freq *
be44eb28 4016 1000) / 3), bandwidth);
ab5060cd 4017 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
cd7a67a4
MCC		 4018 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
4019 iqm_rc_rate_ofs += 0x80L;
4020 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
be44eb28 4021 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
cd7a67a4 4022 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
be44eb28 4023 }
43dd07f7 4024
cd7a67a4 4025 iqm_rc_rate_ofs &=
be44eb28
MCC		 4026 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4027 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
cd7a67a4 4028 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
be44eb28
MCC		 4029 if (status < 0)
4030 goto error;
43dd07f7 4031
be44eb28 4032 /* Bandwidth setting done */
43dd07f7 4033
ea90f011 4034#if 0
cd7a67a4 4035 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
be44eb28
MCC		 4036 if (status < 0)
4037 goto error;
ea90f011 4038#endif
ab5060cd
MCC		 4039 status = set_frequency_shifter(state, intermediate_freqk_hz,
4040 tuner_freq_offset, true);
be44eb28
MCC		 4041 if (status < 0)
4042 goto error;
43dd07f7 4043
ab5060cd 4044 /*== start SC, write channel settings to SC ==========================*/
43dd07f7 4045
be44eb28
MCC		 4046 /* Activate SCU to enable SCU commands */
4047 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4048 if (status < 0)
4049 goto error;
43dd07f7 4050
be44eb28
MCC		 4051 /* Enable SC after setting all other parameters */
4052 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4053 if (status < 0)
4054 goto error;
4055 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4056 if (status < 0)
4057 goto error;
43dd07f7 4058
43dd07f7 4059
ab5060cd
MCC		 4060 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4061 | SCU_RAM_COMMAND_CMD_DEMOD_START,
4062 0, NULL, 1, &cmd_result);
be44eb28
MCC		 4063 if (status < 0)
4064 goto error;
4065
4066 /* Write SC parameter registers, set all AUTO flags in operation mode */
4067 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4068 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4069 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4070 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4071 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
cd7a67a4
MCC		 4072 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4073 0, transmission_params, param1, 0, 0, 0);
be44eb28
MCC		 4074 if (status < 0)
4075 goto error;
43dd07f7 4076
cd7a67a4
MCC		 4077 if (!state->m_drxk_a3_rom_code)
4078 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
be44eb28
MCC		 4079error:
4080 if (status < 0)
3a4398f5 4081 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 4082
4083 return status;
4084}
4085
4086
4087/*============================================================================*/
4088
34eb9751 4089/*
39c1cb2b 4090* \brief Retrieve lock status .
43dd07f7
RM		 4091* \param demod Pointer to demodulator instance.
4092* \param lockStat Pointer to lock status structure.
4093* \return DRXStatus_t.
4094*
4095*/
cd7a67a4 4096static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
43dd07f7 4097{
ebc7de22
OE		 4098 int status;
4099 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4100 OFDM_SC_RA_RAM_LOCK_FEC__M);
4101 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4102 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4103
cd7a67a4
MCC		 4104 u16 sc_ra_ram_lock = 0;
4105 u16 sc_comm_exec = 0;
ebc7de22 4106
2da67501
MCC		 4107 dprintk(1, "\n");
4108
cd7a67a4 4109 *p_lock_status = NOT_LOCKED;
ebc7de22
OE		 4110 /* driver 0.9.0 */
4111 /* Check if SC is running */
cd7a67a4 4112 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
be44eb28
MCC		 4113 if (status < 0)
4114 goto end;
cd7a67a4 4115 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
be44eb28 4116 goto end;
ebc7de22 4117
cd7a67a4 4118 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
be44eb28
MCC		 4119 if (status < 0)
4120 goto end;
ebc7de22 4121
cd7a67a4
MCC		 4122 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4123 *p_lock_status = MPEG_LOCK;
4124 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4125 *p_lock_status = FEC_LOCK;
4126 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4127 *p_lock_status = DEMOD_LOCK;
4128 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4129 *p_lock_status = NEVER_LOCK;
be44eb28
MCC		 4130end:
4131 if (status < 0)
3a4398f5 4132 pr_err("Error %d on %s\n", status, __func__);
ebc7de22
OE		 4133
4134 return status;
43dd07f7
RM		 4135}
4136
cd7a67a4 4137static int power_up_qam(struct drxk_state *state)
43dd07f7 4138{
cd7a67a4 4139 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
be44eb28 4140 int status;
43dd07f7 4141
2da67501 4142 dprintk(1, "\n");
cd7a67a4 4143 status = ctrl_power_mode(state, &power_mode);
be44eb28 4144 if (status < 0)
3a4398f5 4145 pr_err("Error %d on %s\n", status, __func__);
43dd07f7 4146
ebc7de22 4147 return status;
43dd07f7
RM		 4148}
4149
4150
34eb9751 4151/* Power Down QAM */
cd7a67a4 4152static int power_down_qam(struct drxk_state *state)
43dd07f7 4153{
ebc7de22 4154 u16 data = 0;
cd7a67a4 4155 u16 cmd_result;
ebc7de22
OE		 4156 int status = 0;
4157
2da67501 4158 dprintk(1, "\n");
be44eb28
MCC		 4159 status = read16(state, SCU_COMM_EXEC__A, &data);
4160 if (status < 0)
4161 goto error;
4162 if (data == SCU_COMM_EXEC_ACTIVE) {
4163 /*
4164 STOP demodulator
4165 QAM and HW blocks
4166 */
4167 /* stop all comstate->m_exec */
4168 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
ea90f011 4169 if (status < 0)
be44eb28 4170 goto error;
ab5060cd
MCC		 4171 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4172 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4173 0, NULL, 1, &cmd_result);
ea90f011 4174 if (status < 0)
be44eb28
MCC		 4175 goto error;
4176 }
4177 /* powerdown AFE */
cd7a67a4 4178 status = set_iqm_af(state, false);
be44eb28
MCC		 4179
4180error:
4181 if (status < 0)
3a4398f5 4182 pr_err("Error %d on %s\n", status, __func__);
ebc7de22
OE		 4183
4184 return status;
43dd07f7 4185}
ebc7de22 4186
43dd07f7
RM		 4187/*============================================================================*/
4188
34eb9751 4189/*
43dd07f7
RM		 4190* \brief Setup of the QAM Measurement intervals for signal quality
4191* \param demod instance of demod.
ed5452a2 4192* \param modulation current modulation.
43dd07f7
RM		 4193* \return DRXStatus_t.
4194*
4195* NOTE:
4196* Take into account that for certain settings the errorcounters can overflow.
4197* The implementation does not check this.
4198*
4199*/
cd7a67a4
MCC		 4200static int set_qam_measurement(struct drxk_state *state,
4201 enum e_drxk_constellation modulation,
4202 u32 symbol_rate)
43dd07f7 4203{
cd7a67a4
MCC		 4204 u32 fec_bits_desired = 0; /* BER accounting period */
4205 u32 fec_rs_period_total = 0; /* Total period */
4206 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
4207 u16 fec_rs_period = 0; /* Value for corresponding I2C register */
43dd07f7
RM		 4208 int status = 0;
4209
2da67501 4210 dprintk(1, "\n");
43dd07f7 4211
cd7a67a4
MCC		 4212 fec_rs_prescale = 1;
4213 /* fec_bits_desired = symbol_rate [kHz] *
be44eb28 4214 FrameLenght [ms] *
ed5452a2 4215 (modulation + 1) *
be44eb28
MCC		 4216 SyncLoss (== 1) *
4217 ViterbiLoss (==1)
4218 */
ed5452a2 4219 switch (modulation) {
be44eb28 4220 case DRX_CONSTELLATION_QAM16:
cd7a67a4 4221 fec_bits_desired = 4 * symbol_rate;
be44eb28
MCC		 4222 break;
4223 case DRX_CONSTELLATION_QAM32:
cd7a67a4 4224 fec_bits_desired = 5 * symbol_rate;
be44eb28
MCC		 4225 break;
4226 case DRX_CONSTELLATION_QAM64:
cd7a67a4 4227 fec_bits_desired = 6 * symbol_rate;
be44eb28
MCC		 4228 break;
4229 case DRX_CONSTELLATION_QAM128:
cd7a67a4 4230 fec_bits_desired = 7 * symbol_rate;
be44eb28
MCC		 4231 break;
4232 case DRX_CONSTELLATION_QAM256:
cd7a67a4 4233 fec_bits_desired = 8 * symbol_rate;
be44eb28
MCC		 4234 break;
4235 default:
4236 status = -EINVAL;
4237 }
4238 if (status < 0)
4239 goto error;
43dd07f7 4240
ab5060cd 4241 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
cd7a67a4 4242 fec_bits_desired *= 500; /* meas. period [ms] */
43dd07f7 4243
be44eb28 4244 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
cd7a67a4
MCC		 4245 /* fec_rs_period_total = fec_bits_desired / 1632 */
4246 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */
43dd07f7 4247
cd7a67a4
MCC		 4248 /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */
4249 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4250 if (fec_rs_prescale == 0) {
be44eb28
MCC		 4251 /* Divide by zero (though impossible) */
4252 status = -EINVAL;
ea90f011 4253 if (status < 0)
be44eb28
MCC		 4254 goto error;
4255 }
cd7a67a4
MCC		 4256 fec_rs_period =
4257 ((u16) fec_rs_period_total +
4258 (fec_rs_prescale >> 1)) / fec_rs_prescale;
43dd07f7 4259
be44eb28 4260 /* write corresponding registers */
cd7a67a4 4261 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
ebc7de22 4262 if (status < 0)
be44eb28 4263 goto error;
ab5060cd
MCC		 4264 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4265 fec_rs_prescale);
be44eb28
MCC		 4266 if (status < 0)
4267 goto error;
cd7a67a4 4268 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
be44eb28
MCC		 4269error:
4270 if (status < 0)
3a4398f5 4271 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 4272 return status;
4273}
4274
cd7a67a4 4275static int set_qam16(struct drxk_state *state)
43dd07f7 4276{
ebc7de22
OE		 4277 int status = 0;
4278
2da67501 4279 dprintk(1, "\n");
be44eb28
MCC		 4280 /* QAM Equalizer Setup */
4281 /* Equalizer */
4282 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4283 if (status < 0)
4284 goto error;
4285 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4286 if (status < 0)
4287 goto error;
4288 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4289 if (status < 0)
4290 goto error;
4291 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4292 if (status < 0)
4293 goto error;
4294 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4295 if (status < 0)
4296 goto error;
4297 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4298 if (status < 0)
4299 goto error;
4300 /* Decision Feedback Equalizer */
4301 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4302 if (status < 0)
4303 goto error;
4304 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4305 if (status < 0)
4306 goto error;
4307 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4308 if (status < 0)
4309 goto error;
4310 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4311 if (status < 0)
4312 goto error;
4313 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4314 if (status < 0)
4315 goto error;
4316 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4317 if (status < 0)
4318 goto error;
ebc7de22 4319
be44eb28
MCC		 4320 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4321 if (status < 0)
4322 goto error;
4323 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4324 if (status < 0)
4325 goto error;
4326 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4327 if (status < 0)
4328 goto error;
ebc7de22 4329
be44eb28 4330 /* QAM Slicer Settings */
ab5060cd
MCC		 4331 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4332 DRXK_QAM_SL_SIG_POWER_QAM16);
be44eb28
MCC		 4333 if (status < 0)
4334 goto error;
ebc7de22 4335
be44eb28
MCC		 4336 /* QAM Loop Controller Coeficients */
4337 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4338 if (status < 0)
4339 goto error;
4340 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4341 if (status < 0)
4342 goto error;
4343 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4344 if (status < 0)
4345 goto error;
4346 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4347 if (status < 0)
4348 goto error;
4349 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4350 if (status < 0)
4351 goto error;
4352 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4353 if (status < 0)
4354 goto error;
4355 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4356 if (status < 0)
4357 goto error;
4358 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4359 if (status < 0)
4360 goto error;
ea90f011 4361
be44eb28
MCC		 4362 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4363 if (status < 0)
4364 goto error;
4365 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4366 if (status < 0)
4367 goto error;
4368 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4369 if (status < 0)
4370 goto error;
4371 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4372 if (status < 0)
4373 goto error;
4374 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4375 if (status < 0)
4376 goto error;
4377 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4378 if (status < 0)
4379 goto error;
4380 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4381 if (status < 0)
4382 goto error;
4383 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4384 if (status < 0)
4385 goto error;
4386 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4387 if (status < 0)
4388 goto error;
4389 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4390 if (status < 0)
4391 goto error;
4392 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4393 if (status < 0)
4394 goto error;
4395 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4396 if (status < 0)
4397 goto error;
ebc7de22
OE		 4398
4399
be44eb28 4400 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4401
be44eb28
MCC		 4402 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4403 if (status < 0)
4404 goto error;
4405 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4406 if (status < 0)
4407 goto error;
4408 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4409 if (status < 0)
4410 goto error;
4411 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4412 if (status < 0)
4413 goto error;
4414 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4415 if (status < 0)
4416 goto error;
4417 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4418 if (status < 0)
4419 goto error;
ebc7de22 4420
be44eb28
MCC		 4421 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4422 if (status < 0)
4423 goto error;
4424 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4425 if (status < 0)
4426 goto error;
4427 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4428 if (status < 0)
4429 goto error;
ebc7de22
OE		 4430
4431
be44eb28 4432 /* QAM FSM Tracking Parameters */
ebc7de22 4433
be44eb28
MCC		 4434 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4435 if (status < 0)
4436 goto error;
4437 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4438 if (status < 0)
4439 goto error;
4440 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4441 if (status < 0)
4442 goto error;
4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4444 if (status < 0)
4445 goto error;
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4447 if (status < 0)
4448 goto error;
4449 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4450 if (status < 0)
4451 goto error;
4452 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4453 if (status < 0)
4454 goto error;
ebc7de22 4455
be44eb28
MCC		 4456error:
4457 if (status < 0)
3a4398f5 4458 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 4459 return status;
43dd07f7
RM		 4460}
4461
4462/*============================================================================*/
4463
34eb9751 4464/*
43dd07f7
RM		 4465* \brief QAM32 specific setup
4466* \param demod instance of demod.
4467* \return DRXStatus_t.
4468*/
cd7a67a4 4469static int set_qam32(struct drxk_state *state)
43dd07f7 4470{
ebc7de22
OE		 4471 int status = 0;
4472
2da67501 4473 dprintk(1, "\n");
ebc7de22 4474
be44eb28
MCC		 4475 /* QAM Equalizer Setup */
4476 /* Equalizer */
4477 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4478 if (status < 0)
4479 goto error;
4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4481 if (status < 0)
4482 goto error;
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4484 if (status < 0)
4485 goto error;
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4487 if (status < 0)
4488 goto error;
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4490 if (status < 0)
4491 goto error;
4492 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4493 if (status < 0)
4494 goto error;
ebc7de22 4495
be44eb28
MCC		 4496 /* Decision Feedback Equalizer */
4497 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4498 if (status < 0)
4499 goto error;
4500 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4501 if (status < 0)
4502 goto error;
4503 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4504 if (status < 0)
4505 goto error;
4506 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4507 if (status < 0)
4508 goto error;
4509 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4510 if (status < 0)
4511 goto error;
4512 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4513 if (status < 0)
4514 goto error;
ebc7de22 4515
be44eb28
MCC		 4516 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4517 if (status < 0)
4518 goto error;
4519 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4520 if (status < 0)
4521 goto error;
4522 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4523 if (status < 0)
4524 goto error;
ebc7de22 4525
be44eb28 4526 /* QAM Slicer Settings */
ebc7de22 4527
ab5060cd
MCC		 4528 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4529 DRXK_QAM_SL_SIG_POWER_QAM32);
be44eb28
MCC		 4530 if (status < 0)
4531 goto error;
ebc7de22 4532
ebc7de22 4533
be44eb28 4534 /* QAM Loop Controller Coeficients */
ea90f011 4535
be44eb28
MCC		 4536 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4537 if (status < 0)
4538 goto error;
4539 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4540 if (status < 0)
4541 goto error;
4542 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4543 if (status < 0)
4544 goto error;
4545 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4546 if (status < 0)
4547 goto error;
4548 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4549 if (status < 0)
4550 goto error;
4551 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4552 if (status < 0)
4553 goto error;
4554 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4555 if (status < 0)
4556 goto error;
4557 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4558 if (status < 0)
4559 goto error;
ebc7de22 4560
be44eb28
MCC		 4561 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4562 if (status < 0)
4563 goto error;
4564 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4565 if (status < 0)
4566 goto error;
4567 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4568 if (status < 0)
4569 goto error;
4570 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4571 if (status < 0)
4572 goto error;
4573 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4574 if (status < 0)
4575 goto error;
4576 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4577 if (status < 0)
4578 goto error;
4579 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4580 if (status < 0)
4581 goto error;
4582 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4583 if (status < 0)
4584 goto error;
4585 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4586 if (status < 0)
4587 goto error;
4588 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4589 if (status < 0)
4590 goto error;
4591 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4592 if (status < 0)
4593 goto error;
4594 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4595 if (status < 0)
4596 goto error;
ebc7de22 4597
ebc7de22 4598
be44eb28 4599 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4600
be44eb28
MCC		 4601 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4602 if (status < 0)
4603 goto error;
4604 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4605 if (status < 0)
4606 goto error;
4607 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4608 if (status < 0)
4609 goto error;
4610 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4611 if (status < 0)
4612 goto error;
4613 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4614 if (status < 0)
4615 goto error;
4616 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4617 if (status < 0)
4618 goto error;
ebc7de22 4619
be44eb28
MCC		 4620 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4621 if (status < 0)
4622 goto error;
4623 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4624 if (status < 0)
4625 goto error;
4626 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4627 if (status < 0)
4628 goto error;
ebc7de22 4629
ebc7de22 4630
be44eb28 4631 /* QAM FSM Tracking Parameters */
ebc7de22 4632
be44eb28
MCC		 4633 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4634 if (status < 0)
4635 goto error;
4636 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4637 if (status < 0)
4638 goto error;
4639 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4640 if (status < 0)
4641 goto error;
4642 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4643 if (status < 0)
4644 goto error;
4645 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4646 if (status < 0)
4647 goto error;
4648 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4649 if (status < 0)
4650 goto error;
4651 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4652error:
4653 if (status < 0)
3a4398f5 4654 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 4655 return status;
43dd07f7
RM		 4656}
4657
4658/*============================================================================*/
4659
34eb9751 4660/*
43dd07f7
RM		 4661* \brief QAM64 specific setup
4662* \param demod instance of demod.
4663* \return DRXStatus_t.
4664*/
cd7a67a4 4665static int set_qam64(struct drxk_state *state)
43dd07f7 4666{
ebc7de22
OE		 4667 int status = 0;
4668
2da67501 4669 dprintk(1, "\n");
be44eb28
MCC		 4670 /* QAM Equalizer Setup */
4671 /* Equalizer */
4672 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4673 if (status < 0)
4674 goto error;
4675 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4676 if (status < 0)
4677 goto error;
4678 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4679 if (status < 0)
4680 goto error;
4681 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4682 if (status < 0)
4683 goto error;
4684 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4685 if (status < 0)
4686 goto error;
4687 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4688 if (status < 0)
4689 goto error;
ebc7de22 4690
be44eb28
MCC		 4691 /* Decision Feedback Equalizer */
4692 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4693 if (status < 0)
4694 goto error;
4695 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4696 if (status < 0)
4697 goto error;
4698 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4699 if (status < 0)
4700 goto error;
4701 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4702 if (status < 0)
4703 goto error;
4704 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4705 if (status < 0)
4706 goto error;
4707 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4708 if (status < 0)
4709 goto error;
ebc7de22 4710
be44eb28
MCC		 4711 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4712 if (status < 0)
4713 goto error;
4714 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4715 if (status < 0)
4716 goto error;
4717 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4718 if (status < 0)
4719 goto error;
ebc7de22 4720
be44eb28 4721 /* QAM Slicer Settings */
ab5060cd
MCC		 4722 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4723 DRXK_QAM_SL_SIG_POWER_QAM64);
be44eb28
MCC		 4724 if (status < 0)
4725 goto error;
ebc7de22
OE		 4726
4727
be44eb28 4728 /* QAM Loop Controller Coeficients */
ebc7de22 4729
be44eb28
MCC		 4730 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4731 if (status < 0)
4732 goto error;
4733 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4734 if (status < 0)
4735 goto error;
4736 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4737 if (status < 0)
4738 goto error;
4739 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4740 if (status < 0)
4741 goto error;
4742 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4743 if (status < 0)
4744 goto error;
4745 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4746 if (status < 0)
4747 goto error;
4748 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4749 if (status < 0)
4750 goto error;
4751 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4752 if (status < 0)
4753 goto error;
ea90f011 4754
be44eb28
MCC		 4755 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4756 if (status < 0)
4757 goto error;
4758 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4759 if (status < 0)
4760 goto error;
4761 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4762 if (status < 0)
4763 goto error;
4764 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4765 if (status < 0)
4766 goto error;
4767 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4768 if (status < 0)
4769 goto error;
4770 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4771 if (status < 0)
4772 goto error;
4773 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4774 if (status < 0)
4775 goto error;
4776 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4777 if (status < 0)
4778 goto error;
4779 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4780 if (status < 0)
4781 goto error;
4782 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4783 if (status < 0)
4784 goto error;
4785 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4786 if (status < 0)
4787 goto error;
4788 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4789 if (status < 0)
4790 goto error;
ebc7de22
OE		 4791
4792
be44eb28 4793 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4794
be44eb28
MCC		 4795 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4796 if (status < 0)
4797 goto error;
4798 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4799 if (status < 0)
4800 goto error;
4801 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4802 if (status < 0)
4803 goto error;
4804 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4805 if (status < 0)
4806 goto error;
4807 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4808 if (status < 0)
4809 goto error;
4810 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4811 if (status < 0)
4812 goto error;
ebc7de22 4813
be44eb28
MCC		 4814 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4815 if (status < 0)
4816 goto error;
4817 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4818 if (status < 0)
4819 goto error;
4820 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4821 if (status < 0)
4822 goto error;
ebc7de22
OE		 4823
4824
be44eb28 4825 /* QAM FSM Tracking Parameters */
ebc7de22 4826
be44eb28
MCC		 4827 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4828 if (status < 0)
4829 goto error;
4830 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4831 if (status < 0)
4832 goto error;
4833 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4834 if (status < 0)
4835 goto error;
4836 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4837 if (status < 0)
4838 goto error;
4839 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4840 if (status < 0)
4841 goto error;
4842 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4843 if (status < 0)
4844 goto error;
4845 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4846error:
4847 if (status < 0)
3a4398f5 4848 pr_err("Error %d on %s\n", status, __func__);
ebc7de22
OE		 4849
4850 return status;
43dd07f7
RM		 4851}
4852
4853/*============================================================================*/
4854
34eb9751 4855/*
43dd07f7
RM		 4856* \brief QAM128 specific setup
4857* \param demod: instance of demod.
4858* \return DRXStatus_t.
4859*/
cd7a67a4 4860static int set_qam128(struct drxk_state *state)
43dd07f7 4861{
ebc7de22
OE		 4862 int status = 0;
4863
2da67501 4864 dprintk(1, "\n");
be44eb28
MCC		 4865 /* QAM Equalizer Setup */
4866 /* Equalizer */
4867 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4868 if (status < 0)
4869 goto error;
4870 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4871 if (status < 0)
4872 goto error;
4873 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4874 if (status < 0)
4875 goto error;
4876 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4877 if (status < 0)
4878 goto error;
4879 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4880 if (status < 0)
4881 goto error;
4882 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4883 if (status < 0)
4884 goto error;
ebc7de22 4885
be44eb28
MCC		 4886 /* Decision Feedback Equalizer */
4887 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4888 if (status < 0)
4889 goto error;
4890 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4891 if (status < 0)
4892 goto error;
4893 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4894 if (status < 0)
4895 goto error;
4896 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4897 if (status < 0)
4898 goto error;
4899 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4900 if (status < 0)
4901 goto error;
4902 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4903 if (status < 0)
4904 goto error;
ebc7de22 4905
be44eb28
MCC		 4906 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4907 if (status < 0)
4908 goto error;
4909 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4910 if (status < 0)
4911 goto error;
4912 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4913 if (status < 0)
4914 goto error;
ebc7de22 4915
ebc7de22 4916
be44eb28 4917 /* QAM Slicer Settings */
ebc7de22 4918
ab5060cd
MCC		 4919 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4920 DRXK_QAM_SL_SIG_POWER_QAM128);
be44eb28
MCC		 4921 if (status < 0)
4922 goto error;
ebc7de22 4923
ebc7de22 4924
be44eb28 4925 /* QAM Loop Controller Coeficients */
ea90f011 4926
be44eb28
MCC		 4927 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4928 if (status < 0)
4929 goto error;
4930 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4931 if (status < 0)
4932 goto error;
4933 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4934 if (status < 0)
4935 goto error;
4936 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4937 if (status < 0)
4938 goto error;
4939 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4940 if (status < 0)
4941 goto error;
4942 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4943 if (status < 0)
4944 goto error;
4945 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4946 if (status < 0)
4947 goto error;
4948 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4949 if (status < 0)
4950 goto error;
4951
4952 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4953 if (status < 0)
4954 goto error;
4955 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4956 if (status < 0)
4957 goto error;
4958 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4959 if (status < 0)
4960 goto error;
4961 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4962 if (status < 0)
4963 goto error;
4964 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4965 if (status < 0)
4966 goto error;
4967 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4968 if (status < 0)
4969 goto error;
4970 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4971 if (status < 0)
4972 goto error;
4973 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4974 if (status < 0)
4975 goto error;
4976 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4977 if (status < 0)
4978 goto error;
4979 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4980 if (status < 0)
4981 goto error;
4982 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4983 if (status < 0)
4984 goto error;
4985 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4986 if (status < 0)
4987 goto error;
ebc7de22
OE		 4988
4989
be44eb28 4990 /* QAM State Machine (FSM) Thresholds */
ebc7de22 4991
be44eb28
MCC		 4992 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4993 if (status < 0)
4994 goto error;
4995 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4996 if (status < 0)
4997 goto error;
4998 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4999 if (status < 0)
5000 goto error;
5001 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5002 if (status < 0)
5003 goto error;
5004 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5005 if (status < 0)
5006 goto error;
5007 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5008 if (status < 0)
5009 goto error;
ebc7de22 5010
be44eb28
MCC		 5011 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5012 if (status < 0)
5013 goto error;
5014 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5015 if (status < 0)
5016 goto error;
ebc7de22 5017
be44eb28
MCC		 5018 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5019 if (status < 0)
5020 goto error;
ebc7de22 5021
be44eb28 5022 /* QAM FSM Tracking Parameters */
ebc7de22 5023
be44eb28
MCC		 5024 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5025 if (status < 0)
5026 goto error;
5027 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5028 if (status < 0)
5029 goto error;
5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5031 if (status < 0)
5032 goto error;
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5034 if (status < 0)
5035 goto error;
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5037 if (status < 0)
5038 goto error;
5039 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5040 if (status < 0)
5041 goto error;
5042 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5043error:
5044 if (status < 0)
3a4398f5 5045 pr_err("Error %d on %s\n", status, __func__);
ebc7de22
OE		 5046
5047 return status;
43dd07f7
RM		 5048}
5049
5050/*============================================================================*/
5051
34eb9751 5052/*
43dd07f7
RM		 5053* \brief QAM256 specific setup
5054* \param demod: instance of demod.
5055* \return DRXStatus_t.
5056*/
cd7a67a4 5057static int set_qam256(struct drxk_state *state)
43dd07f7 5058{
ebc7de22
OE		 5059 int status = 0;
5060
2da67501 5061 dprintk(1, "\n");
be44eb28
MCC		 5062 /* QAM Equalizer Setup */
5063 /* Equalizer */
5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5065 if (status < 0)
5066 goto error;
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5068 if (status < 0)
5069 goto error;
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5071 if (status < 0)
5072 goto error;
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5074 if (status < 0)
5075 goto error;
5076 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5077 if (status < 0)
5078 goto error;
5079 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5080 if (status < 0)
5081 goto error;
ebc7de22 5082
be44eb28
MCC		 5083 /* Decision Feedback Equalizer */
5084 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5085 if (status < 0)
5086 goto error;
5087 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5088 if (status < 0)
5089 goto error;
5090 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5091 if (status < 0)
5092 goto error;
5093 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5094 if (status < 0)
5095 goto error;
5096 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5097 if (status < 0)
5098 goto error;
5099 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5100 if (status < 0)
5101 goto error;
ebc7de22 5102
be44eb28
MCC		 5103 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5104 if (status < 0)
5105 goto error;
5106 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5107 if (status < 0)
5108 goto error;
5109 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5110 if (status < 0)
5111 goto error;
ebc7de22 5112
be44eb28 5113 /* QAM Slicer Settings */
ebc7de22 5114
ab5060cd
MCC		 5115 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5116 DRXK_QAM_SL_SIG_POWER_QAM256);
be44eb28
MCC		 5117 if (status < 0)
5118 goto error;
ebc7de22 5119
ebc7de22 5120
be44eb28 5121 /* QAM Loop Controller Coeficients */
ea90f011 5122
be44eb28
MCC		 5123 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5124 if (status < 0)
5125 goto error;
5126 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5127 if (status < 0)
5128 goto error;
5129 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5130 if (status < 0)
5131 goto error;
5132 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5133 if (status < 0)
5134 goto error;
5135 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5136 if (status < 0)
5137 goto error;
5138 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5139 if (status < 0)
5140 goto error;
5141 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5142 if (status < 0)
5143 goto error;
5144 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5145 if (status < 0)
5146 goto error;
ebc7de22 5147
be44eb28
MCC		 5148 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5149 if (status < 0)
5150 goto error;
5151 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5152 if (status < 0)
5153 goto error;
5154 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5155 if (status < 0)
5156 goto error;
5157 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5158 if (status < 0)
5159 goto error;
5160 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5161 if (status < 0)
5162 goto error;
5163 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5164 if (status < 0)
5165 goto error;
5166 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5167 if (status < 0)
5168 goto error;
5169 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5170 if (status < 0)
5171 goto error;
5172 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5173 if (status < 0)
5174 goto error;
5175 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5176 if (status < 0)
5177 goto error;
5178 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5179 if (status < 0)
5180 goto error;
5181 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5182 if (status < 0)
5183 goto error;
ebc7de22 5184
ebc7de22 5185
be44eb28 5186 /* QAM State Machine (FSM) Thresholds */
ebc7de22 5187
be44eb28
MCC		 5188 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5189 if (status < 0)
5190 goto error;
5191 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5192 if (status < 0)
5193 goto error;
5194 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5195 if (status < 0)
5196 goto error;
5197 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5198 if (status < 0)
5199 goto error;
5200 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5201 if (status < 0)
5202 goto error;
5203 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5204 if (status < 0)
5205 goto error;
ebc7de22 5206
be44eb28
MCC		 5207 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5208 if (status < 0)
5209 goto error;
5210 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5211 if (status < 0)
5212 goto error;
5213 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5214 if (status < 0)
5215 goto error;
ebc7de22 5216
ebc7de22 5217
be44eb28 5218 /* QAM FSM Tracking Parameters */
ebc7de22 5219
be44eb28
MCC		 5220 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5221 if (status < 0)
5222 goto error;
5223 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5224 if (status < 0)
5225 goto error;
5226 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5227 if (status < 0)
5228 goto error;
5229 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5230 if (status < 0)
5231 goto error;
5232 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5233 if (status < 0)
5234 goto error;
5235 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5236 if (status < 0)
5237 goto error;
5238 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5239error:
5240 if (status < 0)
3a4398f5 5241 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5242 return status;
43dd07f7
RM		 5243}
5244
5245
5246/*============================================================================*/
34eb9751 5247/*
43dd07f7
RM		 5248* \brief Reset QAM block.
5249* \param demod: instance of demod.
5250* \param channel: pointer to channel data.
5251* \return DRXStatus_t.
5252*/
cd7a67a4 5253static int qam_reset_qam(struct drxk_state *state)
43dd07f7 5254{
ebc7de22 5255 int status;
cd7a67a4 5256 u16 cmd_result;
43dd07f7 5257
2da67501 5258 dprintk(1, "\n");
be44eb28
MCC		 5259 /* Stop QAM comstate->m_exec */
5260 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5261 if (status < 0)
5262 goto error;
43dd07f7 5263
ab5060cd
MCC		 5264 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5265 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5266 0, NULL, 1, &cmd_result);
be44eb28
MCC		 5267error:
5268 if (status < 0)
3a4398f5 5269 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5270 return status;
43dd07f7
RM		 5271}
5272
5273/*============================================================================*/
5274
34eb9751 5275/*
43dd07f7
RM		 5276* \brief Set QAM symbolrate.
5277* \param demod: instance of demod.
5278* \param channel: pointer to channel data.
5279* \return DRXStatus_t.
5280*/
cd7a67a4 5281static int qam_set_symbolrate(struct drxk_state *state)
43dd07f7 5282{
cd7a67a4
MCC		 5283 u32 adc_frequency = 0;
5284 u32 symb_freq = 0;
5285 u32 iqm_rc_rate = 0;
ebc7de22 5286 u16 ratesel = 0;
cd7a67a4 5287 u32 lc_symb_rate = 0;
ebc7de22
OE		 5288 int status;
5289
2da67501 5290 dprintk(1, "\n");
be44eb28 5291 /* Select & calculate correct IQM rate */
cd7a67a4 5292 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
be44eb28 5293 ratesel = 0;
ed5452a2 5294 if (state->props.symbol_rate <= 1188750)
be44eb28 5295 ratesel = 3;
ed5452a2 5296 else if (state->props.symbol_rate <= 2377500)
be44eb28 5297 ratesel = 2;
ed5452a2 5298 else if (state->props.symbol_rate <= 4755000)
be44eb28
MCC		 5299 ratesel = 1;
5300 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5301 if (status < 0)
5302 goto error;
ebc7de22 5303
be44eb28
MCC		 5304 /*
5305 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5306 */
cd7a67a4
MCC		 5307 symb_freq = state->props.symbol_rate * (1 << ratesel);
5308 if (symb_freq == 0) {
be44eb28
MCC		 5309 /* Divide by zero */
5310 status = -EINVAL;
5311 goto error;
5312 }
cd7a67a4
MCC		 5313 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5314 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
be44eb28 5315 (1 << 23);
cd7a67a4 5316 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
be44eb28
MCC		 5317 if (status < 0)
5318 goto error;
cd7a67a4 5319 state->m_iqm_rc_rate = iqm_rc_rate;
be44eb28 5320 /*
cd7a67a4 5321 LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15))
be44eb28 5322 */
cd7a67a4
MCC		 5323 symb_freq = state->props.symbol_rate;
5324 if (adc_frequency == 0) {
be44eb28
MCC		 5325 /* Divide by zero */
5326 status = -EINVAL;
5327 goto error;
5328 }
cd7a67a4
MCC		 5329 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5330 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
be44eb28 5331 16);
cd7a67a4
MCC		 5332 if (lc_symb_rate > 511)
5333 lc_symb_rate = 511;
5334 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
be44eb28
MCC		 5335
5336error:
5337 if (status < 0)
3a4398f5 5338 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5339 return status;
43dd07f7
RM		 5340}
5341
5342/*============================================================================*/
5343
34eb9751 5344/*
43dd07f7
RM		 5345* \brief Get QAM lock status.
5346* \param demod: instance of demod.
5347* \param channel: pointer to channel data.
5348* \return DRXStatus_t.
5349*/
5350
cd7a67a4 5351static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
43dd07f7
RM		 5352{
5353 int status;
cd7a67a4 5354 u16 result[2] = { 0, 0 };
43dd07f7 5355
2da67501 5356 dprintk(1, "\n");
cd7a67a4 5357 *p_lock_status = NOT_LOCKED;
be44eb28 5358 status = scu_command(state,
ebc7de22
OE		 5359 SCU_RAM_COMMAND_STANDARD_QAM |
5360 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
cd7a67a4 5361 result);
ebc7de22 5362 if (status < 0)
3a4398f5 5363 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5364
cd7a67a4 5365 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
43dd07f7 5366 /* 0x0000 NOT LOCKED */
cd7a67a4 5367 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
43dd07f7 5368 /* 0x4000 DEMOD LOCKED */
cd7a67a4
MCC		 5369 *p_lock_status = DEMOD_LOCK;
5370 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
43dd07f7 5371 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
cd7a67a4 5372 *p_lock_status = MPEG_LOCK;
ebc7de22 5373 } else {
43dd07f7
RM		 5374 /* 0xC000 NEVER LOCKED */
5375 /* (system will never be able to lock to the signal) */
ab5060cd
MCC		 5376 /*
5377 * TODO: check this, intermediate & standard specific lock
5378 * states are not taken into account here
5379 */
cd7a67a4 5380 *p_lock_status = NEVER_LOCK;
43dd07f7
RM		 5381 }
5382 return status;
5383}
5384
5385#define QAM_MIRROR__M 0x03
5386#define QAM_MIRROR_NORMAL 0x00
5387#define QAM_MIRRORED 0x01
5388#define QAM_MIRROR_AUTO_ON 0x02
5389#define QAM_LOCKRANGE__M 0x10
5390#define QAM_LOCKRANGE_NORMAL 0x10
5391
cd7a67a4
MCC		 5392static int qam_demodulator_command(struct drxk_state *state,
5393 int number_of_parameters)
9e23f50a
MB		 5394{
5395 int status;
cd7a67a4
MCC		 5396 u16 cmd_result;
5397 u16 set_param_parameters[4] = { 0, 0, 0, 0 };
9e23f50a 5398
cd7a67a4
MCC		 5399 set_param_parameters[0] = state->m_constellation; /* modulation */
5400 set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
9e23f50a 5401
cd7a67a4
MCC		 5402 if (number_of_parameters == 2) {
5403 u16 set_env_parameters[1] = { 0 };
9e23f50a 5404
cd7a67a4
MCC		 5405 if (state->m_operation_mode == OM_QAM_ITU_C)
5406 set_env_parameters[0] = QAM_TOP_ANNEX_C;
9e23f50a 5407 else
cd7a67a4 5408 set_env_parameters[0] = QAM_TOP_ANNEX_A;
9e23f50a
MB		 5409
5410 status = scu_command(state,
ab5060cd
MCC		 5411 SCU_RAM_COMMAND_STANDARD_QAM
5412 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
cd7a67a4 5413 1, set_env_parameters, 1, &cmd_result);
9e23f50a
MB		 5414 if (status < 0)
5415 goto error;
5416
5417 status = scu_command(state,
ab5060cd
MCC		 5418 SCU_RAM_COMMAND_STANDARD_QAM
5419 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
cd7a67a4
MCC		 5420 number_of_parameters, set_param_parameters,
5421 1, &cmd_result);
5422 } else if (number_of_parameters == 4) {
5423 if (state->m_operation_mode == OM_QAM_ITU_C)
5424 set_param_parameters[2] = QAM_TOP_ANNEX_C;
9e23f50a 5425 else
cd7a67a4 5426 set_param_parameters[2] = QAM_TOP_ANNEX_A;
9e23f50a 5427
cd7a67a4 5428 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
9e23f50a
MB		 5429 /* Env parameters */
5430 /* check for LOCKRANGE Extented */
cd7a67a4 5431 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
9e23f50a
MB		 5432
5433 status = scu_command(state,
ab5060cd
MCC		 5434 SCU_RAM_COMMAND_STANDARD_QAM
5435 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
cd7a67a4
MCC		 5436 number_of_parameters, set_param_parameters,
5437 1, &cmd_result);
9e23f50a 5438 } else {
3a4398f5
MCC		 5439 pr_warn("Unknown QAM demodulator parameter count %d\n",
5440 number_of_parameters);
94af1b63 5441 status = -EINVAL;
9e23f50a
MB		 5442 }
5443
5444error:
5445 if (status < 0)
3a4398f5 5446 pr_warn("Warning %d on %s\n", status, __func__);
9e23f50a
MB		 5447 return status;
5448}
5449
cd7a67a4
MCC		 5450static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5451 s32 tuner_freq_offset)
43dd07f7 5452{
be44eb28 5453 int status;
cd7a67a4
MCC		 5454 u16 cmd_result;
5455 int qam_demod_param_count = state->qam_demod_parameter_count;
43dd07f7 5456
2da67501 5457 dprintk(1, "\n");
be44eb28 5458 /*
119faf90
MCC		 5459 * STEP 1: reset demodulator
5460 * resets FEC DI and FEC RS
5461 * resets QAM block
5462 * resets SCU variables
5463 */
be44eb28
MCC		 5464 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5465 if (status < 0)
5466 goto error;
5467 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5468 if (status < 0)
5469 goto error;
cd7a67a4 5470 status = qam_reset_qam(state);
be44eb28
MCC		 5471 if (status < 0)
5472 goto error;
43dd07f7 5473
be44eb28 5474 /*
119faf90
MCC		 5475 * STEP 2: configure demodulator
5476 * -set params; resets IQM,QAM,FEC HW; initializes some
5477 * SCU variables
5478 */
cd7a67a4 5479 status = qam_set_symbolrate(state);
be44eb28
MCC		 5480 if (status < 0)
5481 goto error;
5482
be44eb28 5483 /* Set params */
ed5452a2 5484 switch (state->props.modulation) {
be44eb28 5485 case QAM_256:
cd7a67a4 5486 state->m_constellation = DRX_CONSTELLATION_QAM256;
be44eb28
MCC		 5487 break;
5488 case QAM_AUTO:
5489 case QAM_64:
cd7a67a4 5490 state->m_constellation = DRX_CONSTELLATION_QAM64;
be44eb28
MCC		 5491 break;
5492 case QAM_16:
cd7a67a4 5493 state->m_constellation = DRX_CONSTELLATION_QAM16;
be44eb28
MCC		 5494 break;
5495 case QAM_32:
cd7a67a4 5496 state->m_constellation = DRX_CONSTELLATION_QAM32;
be44eb28
MCC		 5497 break;
5498 case QAM_128:
cd7a67a4 5499 state->m_constellation = DRX_CONSTELLATION_QAM128;
be44eb28
MCC		 5500 break;
5501 default:
5502 status = -EINVAL;
5503 break;
5504 }
5505 if (status < 0)
5506 goto error;
43dd07f7 5507
9e23f50a
MB		 5508 /* Use the 4-parameter if it's requested or we're probing for
5509 * the correct command. */
5510 if (state->qam_demod_parameter_count == 4
5511 || !state->qam_demod_parameter_count) {
cd7a67a4
MCC		 5512 qam_demod_param_count = 4;
5513 status = qam_demodulator_command(state, qam_demod_param_count);
9e23f50a 5514 }
43dd07f7 5515
9e23f50a
MB		 5516 /* Use the 2-parameter command if it was requested or if we're
5517 * probing for the correct command and the 4-parameter command
5518 * failed. */
5519 if (state->qam_demod_parameter_count == 2
5520 || (!state->qam_demod_parameter_count && status < 0)) {
cd7a67a4
MCC		 5521 qam_demod_param_count = 2;
5522 status = qam_demodulator_command(state, qam_demod_param_count);
5eee2bb2 5523 }
9e23f50a
MB		 5524
5525 if (status < 0) {
0fb220f2
MCC		 5526 dprintk(1, "Could not set demodulator parameters.\n");
5527 dprintk(1,
5528 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
9e23f50a
MB		 5529 state->qam_demod_parameter_count,
5530 state->microcode_name);
5eee2bb2 5531 goto error;
9e23f50a 5532 } else if (!state->qam_demod_parameter_count) {
0fb220f2
MCC		 5533 dprintk(1,
5534 "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
cd7a67a4 5535 qam_demod_param_count);
9e23f50a 5536
7eaf7188
MCC		 5537 /*
5538 * One of our commands was successful. We don't need to
5539 * auto-probe anymore, now that we got the correct command.
5540 */
cd7a67a4 5541 state->qam_demod_parameter_count = qam_demod_param_count;
9e23f50a 5542 }
43dd07f7 5543
119faf90
MCC		 5544 /*
5545 * STEP 3: enable the system in a mode where the ADC provides valid
ed5452a2 5546 * signal setup modulation independent registers
119faf90 5547 */
ea90f011 5548#if 0
cd7a67a4 5549 status = set_frequency(channel, tuner_freq_offset));
be44eb28
MCC		 5550 if (status < 0)
5551 goto error;
ea90f011 5552#endif
ab5060cd
MCC		 5553 status = set_frequency_shifter(state, intermediate_freqk_hz,
5554 tuner_freq_offset, true);
be44eb28
MCC		 5555 if (status < 0)
5556 goto error;
43dd07f7 5557
be44eb28 5558 /* Setup BER measurement */
ab5060cd
MCC		 5559 status = set_qam_measurement(state, state->m_constellation,
5560 state->props.symbol_rate);
be44eb28
MCC		 5561 if (status < 0)
5562 goto error;
ebc7de22 5563
be44eb28
MCC		 5564 /* Reset default values */
5565 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5566 if (status < 0)
5567 goto error;
5568 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5569 if (status < 0)
5570 goto error;
ea90f011 5571
be44eb28
MCC		 5572 /* Reset default LC values */
5573 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5574 if (status < 0)
5575 goto error;
5576 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5577 if (status < 0)
5578 goto error;
5579 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5580 if (status < 0)
5581 goto error;
5582 status = write16(state, QAM_LC_MODE__A, 7);
5583 if (status < 0)
5584 goto error;
ebc7de22 5585
be44eb28
MCC		 5586 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5587 if (status < 0)
5588 goto error;
5589 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5590 if (status < 0)
5591 goto error;
5592 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5593 if (status < 0)
5594 goto error;
5595 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5596 if (status < 0)
5597 goto error;
5598 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5599 if (status < 0)
5600 goto error;
5601 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5602 if (status < 0)
5603 goto error;
5604 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5605 if (status < 0)
5606 goto error;
5607 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5608 if (status < 0)
5609 goto error;
5610 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5611 if (status < 0)
5612 goto error;
5613 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5614 if (status < 0)
5615 goto error;
5616 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5617 if (status < 0)
5618 goto error;
5619 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5620 if (status < 0)
5621 goto error;
5622 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5623 if (status < 0)
5624 goto error;
5625 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5626 if (status < 0)
5627 goto error;
5628 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5629 if (status < 0)
5630 goto error;
ebc7de22 5631
be44eb28 5632 /* Mirroring, QAM-block starting point not inverted */
ab5060cd
MCC		 5633 status = write16(state, QAM_SY_SP_INV__A,
5634 QAM_SY_SP_INV_SPECTRUM_INV_DIS);
be44eb28
MCC		 5635 if (status < 0)
5636 goto error;
ebc7de22 5637
be44eb28
MCC		 5638 /* Halt SCU to enable safe non-atomic accesses */
5639 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5640 if (status < 0)
5641 goto error;
ebc7de22 5642
ed5452a2
MCC		 5643 /* STEP 4: modulation specific setup */
5644 switch (state->props.modulation) {
be44eb28 5645 case QAM_16:
cd7a67a4 5646 status = set_qam16(state);
be44eb28
MCC		 5647 break;
5648 case QAM_32:
cd7a67a4 5649 status = set_qam32(state);
be44eb28
MCC		 5650 break;
5651 case QAM_AUTO:
5652 case QAM_64:
cd7a67a4 5653 status = set_qam64(state);
be44eb28
MCC		 5654 break;
5655 case QAM_128:
cd7a67a4 5656 status = set_qam128(state);
be44eb28
MCC		 5657 break;
5658 case QAM_256:
cd7a67a4 5659 status = set_qam256(state);
be44eb28
MCC		 5660 break;
5661 default:
5662 status = -EINVAL;
5663 break;
5664 }
5665 if (status < 0)
5666 goto error;
ebc7de22 5667
be44eb28
MCC		 5668 /* Activate SCU to enable SCU commands */
5669 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5670 if (status < 0)
5671 goto error;
ebc7de22 5672
be44eb28 5673 /* Re-configure MPEG output, requires knowledge of channel bitrate */
ed5452a2 5674 /* extAttr->currentChannel.modulation = channel->modulation; */
be44eb28 5675 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
cd7a67a4 5676 status = mpegts_dto_setup(state, state->m_operation_mode);
be44eb28
MCC		 5677 if (status < 0)
5678 goto error;
ebc7de22 5679
cd7a67a4
MCC		 5680 /* start processes */
5681 status = mpegts_start(state);
be44eb28
MCC		 5682 if (status < 0)
5683 goto error;
5684 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5685 if (status < 0)
5686 goto error;
5687 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5688 if (status < 0)
5689 goto error;
5690 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5691 if (status < 0)
5692 goto error;
ebc7de22 5693
be44eb28 5694 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
ab5060cd
MCC		 5695 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5696 | SCU_RAM_COMMAND_CMD_DEMOD_START,
5697 0, NULL, 1, &cmd_result);
be44eb28
MCC		 5698 if (status < 0)
5699 goto error;
ebc7de22 5700
be44eb28
MCC		 5701 /* update global DRXK data container */
5702/*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
ebc7de22 5703
be44eb28 5704error:
ebc7de22 5705 if (status < 0)
3a4398f5 5706 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5707 return status;
43dd07f7
RM		 5708}
5709
cd7a67a4
MCC		 5710static int set_qam_standard(struct drxk_state *state,
5711 enum operation_mode o_mode)
43dd07f7 5712{
be44eb28 5713 int status;
43dd07f7
RM		 5714#ifdef DRXK_QAM_TAPS
5715#define DRXK_QAMA_TAPS_SELECT
5716#include "drxk_filters.h"
5717#undef DRXK_QAMA_TAPS_SELECT
43dd07f7
RM		 5718#endif
5719
f1b82970
MCC		 5720 dprintk(1, "\n");
5721
be44eb28 5722 /* added antenna switch */
cd7a67a4 5723 switch_antenna_to_qam(state);
ebc7de22 5724
be44eb28 5725 /* Ensure correct power-up mode */
cd7a67a4 5726 status = power_up_qam(state);
be44eb28
MCC		 5727 if (status < 0)
5728 goto error;
5729 /* Reset QAM block */
cd7a67a4 5730 status = qam_reset_qam(state);
be44eb28
MCC		 5731 if (status < 0)
5732 goto error;
ebc7de22 5733
be44eb28 5734 /* Setup IQM */
ebc7de22 5735
be44eb28
MCC		 5736 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5737 if (status < 0)
5738 goto error;
5739 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5740 if (status < 0)
5741 goto error;
ebc7de22 5742
be44eb28
MCC		 5743 /* Upload IQM Channel Filter settings by
5744 boot loader from ROM table */
cd7a67a4 5745 switch (o_mode) {
be44eb28 5746 case OM_QAM_ITU_A:
ab5060cd
MCC		 5747 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5748 DRXK_BLCC_NR_ELEMENTS_TAPS,
5749 DRXK_BLC_TIMEOUT);
be44eb28
MCC		 5750 break;
5751 case OM_QAM_ITU_C:
ab5060cd
MCC		 5752 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5753 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5754 DRXK_BLDC_NR_ELEMENTS_TAPS,
5755 DRXK_BLC_TIMEOUT);
ea90f011 5756 if (status < 0)
be44eb28 5757 goto error;
ab5060cd
MCC		 5758 status = bl_direct_cmd(state,
5759 IQM_CF_TAP_IM0__A,
5760 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5761 DRXK_BLDC_NR_ELEMENTS_TAPS,
5762 DRXK_BLC_TIMEOUT);
be44eb28
MCC		 5763 break;
5764 default:
5765 status = -EINVAL;
5766 }
5767 if (status < 0)
5768 goto error;
ea90f011 5769
ab5060cd 5770 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
be44eb28
MCC		 5771 if (status < 0)
5772 goto error;
5773 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5774 if (status < 0)
5775 goto error;
ab5060cd
MCC		 5776 status = write16(state, IQM_CF_MIDTAP__A,
5777 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
be44eb28
MCC		 5778 if (status < 0)
5779 goto error;
ea90f011 5780
be44eb28
MCC		 5781 status = write16(state, IQM_RC_STRETCH__A, 21);
5782 if (status < 0)
5783 goto error;
5784 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5785 if (status < 0)
5786 goto error;
5787 status = write16(state, IQM_AF_CLP_TH__A, 448);
5788 if (status < 0)
5789 goto error;
5790 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5791 if (status < 0)
5792 goto error;
5793 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5794 if (status < 0)
5795 goto error;
ea90f011 5796
be44eb28
MCC		 5797 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5798 if (status < 0)
5799 goto error;
5800 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5801 if (status < 0)
5802 goto error;
5803 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5804 if (status < 0)
5805 goto error;
5806 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5807 if (status < 0)
5808 goto error;
ebc7de22 5809
be44eb28
MCC		 5810 /* IQM Impulse Noise Processing Unit */
5811 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5812 if (status < 0)
5813 goto error;
5814 status = write16(state, IQM_CF_DATATH__A, 1000);
5815 if (status < 0)
5816 goto error;
5817 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5818 if (status < 0)
5819 goto error;
5820 status = write16(state, IQM_CF_DET_LCT__A, 0);
5821 if (status < 0)
5822 goto error;
5823 status = write16(state, IQM_CF_WND_LEN__A, 1);
5824 if (status < 0)
5825 goto error;
5826 status = write16(state, IQM_CF_PKDTH__A, 1);
5827 if (status < 0)
5828 goto error;
5829 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5830 if (status < 0)
5831 goto error;
ebc7de22 5832
be44eb28 5833 /* turn on IQMAF. Must be done before setAgc**() */
cd7a67a4 5834 status = set_iqm_af(state, true);
be44eb28
MCC		 5835 if (status < 0)
5836 goto error;
5837 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5838 if (status < 0)
5839 goto error;
ebc7de22 5840
be44eb28 5841 /* IQM will not be reset from here, sync ADC and update/init AGC */
cd7a67a4 5842 status = adc_synchronization(state);
be44eb28
MCC		 5843 if (status < 0)
5844 goto error;
ebc7de22 5845
be44eb28
MCC		 5846 /* Set the FSM step period */
5847 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5848 if (status < 0)
5849 goto error;
ebc7de22 5850
be44eb28
MCC		 5851 /* Halt SCU to enable safe non-atomic accesses */
5852 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5853 if (status < 0)
5854 goto error;
ebc7de22 5855
be44eb28
MCC		 5856 /* No more resets of the IQM, current standard correctly set =>
5857 now AGCs can be configured. */
ebc7de22 5858
cd7a67a4 5859 status = init_agc(state, true);
be44eb28
MCC		 5860 if (status < 0)
5861 goto error;
cd7a67a4 5862 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
be44eb28
MCC		 5863 if (status < 0)
5864 goto error;
ebc7de22 5865
be44eb28 5866 /* Configure AGC's */
cd7a67a4 5867 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
be44eb28
MCC		 5868 if (status < 0)
5869 goto error;
cd7a67a4 5870 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
be44eb28
MCC		 5871 if (status < 0)
5872 goto error;
ebc7de22 5873
be44eb28
MCC		 5874 /* Activate SCU to enable SCU commands */
5875 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5876error:
5877 if (status < 0)
3a4398f5 5878 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5879 return status;
43dd07f7
RM		 5880}
5881
cd7a67a4 5882static int write_gpio(struct drxk_state *state)
43dd07f7 5883{
ebc7de22
OE		 5884 int status;
5885 u16 value = 0;
5886
2da67501 5887 dprintk(1, "\n");
be44eb28 5888 /* stop lock indicator process */
ab5060cd
MCC		 5889 status = write16(state, SCU_RAM_GPIO__A,
5890 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
be44eb28
MCC		 5891 if (status < 0)
5892 goto error;
ebc7de22 5893
be44eb28
MCC		 5894 /* Write magic word to enable pdr reg write */
5895 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5896 if (status < 0)
5897 goto error;
ebc7de22 5898
cd7a67a4
MCC		 5899 if (state->m_has_sawsw) {
5900 if (state->uio_mask & 0x0001) { /* UIO-1 */
90796aca 5901 /* write to io pad configuration register - output mode */
ab5060cd
MCC		 5902 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5903 state->m_gpio_cfg);
90796aca
MCC		 5904 if (status < 0)
5905 goto error;
ebc7de22 5906
90796aca
MCC		 5907 /* use corresponding bit in io data output registar */
5908 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5909 if (status < 0)
5910 goto error;
cd7a67a4 5911 if ((state->m_gpio & 0x0001) == 0)
90796aca
MCC		 5912 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5913 else
5914 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5915 /* write back to io data output register */
5916 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5917 if (status < 0)
5918 goto error;
5919 }
cd7a67a4 5920 if (state->uio_mask & 0x0002) { /* UIO-2 */
90796aca 5921 /* write to io pad configuration register - output mode */
ab5060cd
MCC		 5922 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5923 state->m_gpio_cfg);
90796aca
MCC		 5924 if (status < 0)
5925 goto error;
be44eb28 5926
90796aca
MCC		 5927 /* use corresponding bit in io data output registar */
5928 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5929 if (status < 0)
5930 goto error;
cd7a67a4 5931 if ((state->m_gpio & 0x0002) == 0)
90796aca
MCC		 5932 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5933 else
5934 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5935 /* write back to io data output register */
5936 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5937 if (status < 0)
5938 goto error;
5939 }
cd7a67a4 5940 if (state->uio_mask & 0x0004) { /* UIO-3 */
90796aca 5941 /* write to io pad configuration register - output mode */
ab5060cd
MCC		 5942 status = write16(state, SIO_PDR_GPIO_CFG__A,
5943 state->m_gpio_cfg);
90796aca
MCC		 5944 if (status < 0)
5945 goto error;
5946
5947 /* use corresponding bit in io data output registar */
5948 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5949 if (status < 0)
5950 goto error;
cd7a67a4 5951 if ((state->m_gpio & 0x0004) == 0)
90796aca
MCC		 5952 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5953 else
5954 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5955 /* write back to io data output register */
5956 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5957 if (status < 0)
5958 goto error;
5959 }
be44eb28
MCC		 5960 }
5961 /* Write magic word to disable pdr reg write */
5962 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5963error:
5964 if (status < 0)
3a4398f5 5965 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5966 return status;
43dd07f7
RM		 5967}
5968
cd7a67a4 5969static int switch_antenna_to_qam(struct drxk_state *state)
43dd07f7 5970{
147e110b 5971 int status = 0;
90796aca 5972 bool gpio_state;
ebc7de22 5973
2da67501 5974 dprintk(1, "\n");
147e110b 5975
90796aca
MCC		 5976 if (!state->antenna_gpio)
5977 return 0;
5978
cd7a67a4 5979 gpio_state = state->m_gpio & state->antenna_gpio;
90796aca
MCC		 5980
5981 if (state->antenna_dvbt ^ gpio_state) {
5982 /* Antenna is on DVB-T mode. Switch */
5983 if (state->antenna_dvbt)
cd7a67a4 5984 state->m_gpio &= ~state->antenna_gpio;
90796aca 5985 else
cd7a67a4
MCC		 5986 state->m_gpio |= state->antenna_gpio;
5987 status = write_gpio(state);
ebc7de22 5988 }
be44eb28 5989 if (status < 0)
3a4398f5 5990 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 5991 return status;
43dd07f7
RM		 5992}
5993
cd7a67a4 5994static int switch_antenna_to_dvbt(struct drxk_state *state)
43dd07f7 5995{
147e110b 5996 int status = 0;
90796aca 5997 bool gpio_state;
ebc7de22 5998
2da67501 5999 dprintk(1, "\n");
90796aca
MCC		 6000
6001 if (!state->antenna_gpio)
6002 return 0;
6003
cd7a67a4 6004 gpio_state = state->m_gpio & state->antenna_gpio;
90796aca
MCC		 6005
6006 if (!(state->antenna_dvbt ^ gpio_state)) {
6007 /* Antenna is on DVB-C mode. Switch */
6008 if (state->antenna_dvbt)
cd7a67a4 6009 state->m_gpio |= state->antenna_gpio;
90796aca 6010 else
cd7a67a4
MCC		 6011 state->m_gpio &= ~state->antenna_gpio;
6012 status = write_gpio(state);
43dd07f7 6013 }
be44eb28 6014 if (status < 0)
3a4398f5 6015 pr_err("Error %d on %s\n", status, __func__);
43dd07f7
RM		 6016 return status;
6017}
6018
6019
cd7a67a4 6020static int power_down_device(struct drxk_state *state)
43dd07f7
RM		 6021{
6022 /* Power down to requested mode */
6023 /* Backup some register settings */
6024 /* Set pins with possible pull-ups connected to them in input mode */
6025 /* Analog power down */
6026 /* ADC power down */
6027 /* Power down device */
6028 int status;
2da67501
MCC		 6029
6030 dprintk(1, "\n");
cd7a67a4 6031 if (state->m_b_p_down_open_bridge) {
be44eb28
MCC		 6032 /* Open I2C bridge before power down of DRXK */
6033 status = ConfigureI2CBridge(state, true);
ea90f011 6034 if (status < 0)
be44eb28
MCC		 6035 goto error;
6036 }
6037 /* driver 0.9.0 */
cd7a67a4 6038 status = dvbt_enable_ofdm_token_ring(state, false);
be44eb28
MCC		 6039 if (status < 0)
6040 goto error;
43dd07f7 6041
ab5060cd
MCC		 6042 status = write16(state, SIO_CC_PWD_MODE__A,
6043 SIO_CC_PWD_MODE_LEVEL_CLOCK);
ebc7de22 6044 if (status < 0)
be44eb28
MCC		 6045 goto error;
6046 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6047 if (status < 0)
6048 goto error;
cd7a67a4
MCC		 6049 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6050 status = hi_cfg_command(state);
be44eb28
MCC		 6051error:
6052 if (status < 0)
3a4398f5 6053 pr_err("Error %d on %s\n", status, __func__);
ebc7de22 6054
be44eb28 6055 return status;
43dd07f7
RM		 6056}
6057
43dd07f7
RM		 6058static int init_drxk(struct drxk_state *state)
6059{
177bc7da 6060 int status = 0, n = 0;
cd7a67a4
MCC		 6061 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6062 u16 driver_version;
43dd07f7 6063
2da67501 6064 dprintk(1, "\n");
cd7a67a4 6065 if ((state->m_drxk_state == DRXK_UNINITIALIZED)) {
20bfe7ae 6066 drxk_i2c_lock(state);
cd7a67a4 6067 status = power_up_device(state);
be44eb28
MCC		 6068 if (status < 0)
6069 goto error;
cd7a67a4 6070 status = drxx_open(state);
be44eb28
MCC		 6071 if (status < 0)
6072 goto error;
6073 /* Soft reset of OFDM-, sys- and osc-clockdomain */
ab5060cd
MCC		 6074 status = write16(state, SIO_CC_SOFT_RST__A,
6075 SIO_CC_SOFT_RST_OFDM__M
6076 | SIO_CC_SOFT_RST_SYS__M
6077 | SIO_CC_SOFT_RST_OSC__M);
be44eb28
MCC		 6078 if (status < 0)
6079 goto error;
6080 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6081 if (status < 0)
6082 goto error;
ab5060cd
MCC		 6083 /*
6084 * TODO is this needed? If yes, how much delay in
6085 * worst case scenario
6086 */
b72852ba 6087 usleep_range(1000, 2000);
cd7a67a4
MCC		 6088 state->m_drxk_a3_patch_code = true;
6089 status = get_device_capabilities(state);
be44eb28
MCC		 6090 if (status < 0)
6091 goto error;
6092
6093 /* Bridge delay, uses oscilator clock */
6094 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6095 /* SDA brdige delay */
cd7a67a4
MCC		 6096 state->m_hi_cfg_bridge_delay =
6097 (u16) ((state->m_osc_clock_freq / 1000) *
be44eb28
MCC		 6098 HI_I2C_BRIDGE_DELAY) / 1000;
6099 /* Clipping */
cd7a67a4 6100 if (state->m_hi_cfg_bridge_delay >
be44eb28 6101 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
cd7a67a4 6102 state->m_hi_cfg_bridge_delay =
be44eb28
MCC		 6103 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6104 }
6105 /* SCL bridge delay, same as SDA for now */
cd7a67a4
MCC		 6106 state->m_hi_cfg_bridge_delay +=
6107 state->m_hi_cfg_bridge_delay <<
be44eb28
MCC		 6108 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6109
cd7a67a4 6110 status = init_hi(state);
be44eb28
MCC		 6111 if (status < 0)
6112 goto error;
6113 /* disable various processes */
43dd07f7 6114#if NOA1ROM
be44eb28
MCC		 6115 if (!(state->m_DRXK_A1_ROM_CODE)
6116 && !(state->m_DRXK_A2_ROM_CODE))
43dd07f7 6117#endif
be44eb28 6118 {
ab5060cd
MCC		 6119 status = write16(state, SCU_RAM_GPIO__A,
6120 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
ea90f011 6121 if (status < 0)
be44eb28
MCC		 6122 goto error;
6123 }
43dd07f7 6124
be44eb28 6125 /* disable MPEG port */
cd7a67a4 6126 status = mpegts_disable(state);
be44eb28
MCC		 6127 if (status < 0)
6128 goto error;
43dd07f7 6129
be44eb28
MCC		 6130 /* Stop AUD and SCU */
6131 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6132 if (status < 0)
6133 goto error;
6134 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6135 if (status < 0)
6136 goto error;
e4f4f875 6137
be44eb28 6138 /* enable token-ring bus through OFDM block for possible ucode upload */
ab5060cd
MCC		 6139 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6140 SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
be44eb28
MCC		 6141 if (status < 0)
6142 goto error;
43dd07f7 6143
be44eb28 6144 /* include boot loader section */
ab5060cd
MCC		 6145 status = write16(state, SIO_BL_COMM_EXEC__A,
6146 SIO_BL_COMM_EXEC_ACTIVE);
be44eb28
MCC		 6147 if (status < 0)
6148 goto error;
cd7a67a4 6149 status = bl_chain_cmd(state, 0, 6, 100);
be44eb28
MCC		 6150 if (status < 0)
6151 goto error;
43dd07f7 6152
177bc7da 6153 if (state->fw) {
cd7a67a4 6154 status = download_microcode(state, state->fw->data,
177bc7da
MCC		 6155 state->fw->size);
6156 if (status < 0)
6157 goto error;
6158 }
43dd07f7 6159
be44eb28 6160 /* disable token-ring bus through OFDM block for possible ucode upload */
ab5060cd
MCC		 6161 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6162 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
be44eb28
MCC		 6163 if (status < 0)
6164 goto error;
ebc7de22 6165
be44eb28
MCC		 6166 /* Run SCU for a little while to initialize microcode version numbers */
6167 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6168 if (status < 0)
6169 goto error;
cd7a67a4 6170 status = drxx_open(state);
be44eb28
MCC		 6171 if (status < 0)
6172 goto error;
6173 /* added for test */
6174 msleep(30);
43dd07f7 6175
cd7a67a4
MCC		 6176 power_mode = DRXK_POWER_DOWN_OFDM;
6177 status = ctrl_power_mode(state, &power_mode);
be44eb28
MCC		 6178 if (status < 0)
6179 goto error;
6180
6181 /* Stamp driver version number in SCU data RAM in BCD code
39c1cb2b 6182 Done to enable field application engineers to retrieve drxdriver version
be44eb28
MCC		 6183 via I2C from SCU RAM.
6184 Not using SCU command interface for SCU register access since no
6185 microcode may be present.
6186 */
cd7a67a4 6187 driver_version =
be44eb28
MCC		 6188 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6189 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6190 ((DRXK_VERSION_MAJOR % 10) << 4) +
6191 (DRXK_VERSION_MINOR % 10);
ab5060cd
MCC		 6192 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6193 driver_version);
be44eb28
MCC		 6194 if (status < 0)
6195 goto error;
cd7a67a4 6196 driver_version =
be44eb28
MCC		 6197 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6198 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6199 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6200 (DRXK_VERSION_PATCH % 10);
ab5060cd
MCC		 6201 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6202 driver_version);
be44eb28
MCC		 6203 if (status < 0)
6204 goto error;
6205
3a4398f5 6206 pr_info("DRXK driver version %d.%d.%d\n",
be44eb28
MCC		 6207 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6208 DRXK_VERSION_PATCH);
6209
ab5060cd
MCC		 6210 /*
6211 * Dirty fix of default values for ROM/PATCH microcode
6212 * Dirty because this fix makes it impossible to setup
6213 * suitable values before calling DRX_Open. This solution
6214 * requires changes to RF AGC speed to be done via the CTRL
6215 * function after calling DRX_Open
6216 */
be44eb28 6217
cd7a67a4 6218 /* m_dvbt_rf_agc_cfg.speed = 3; */
be44eb28
MCC		 6219
6220 /* Reset driver debug flags to 0 */
6221 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6222 if (status < 0)
6223 goto error;
6224 /* driver 0.9.0 */
6225 /* Setup FEC OC:
6226 NOTE: No more full FEC resets allowed afterwards!! */
6227 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6228 if (status < 0)
6229 goto error;
6230 /* MPEGTS functions are still the same */
cd7a67a4 6231 status = mpegts_dto_init(state);
be44eb28
MCC		 6232 if (status < 0)
6233 goto error;
cd7a67a4 6234 status = mpegts_stop(state);
be44eb28
MCC		 6235 if (status < 0)
6236 goto error;
cd7a67a4 6237 status = mpegts_configure_polarity(state);
be44eb28
MCC		 6238 if (status < 0)
6239 goto error;
cd7a67a4 6240 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
be44eb28
MCC		 6241 if (status < 0)
6242 goto error;
6243 /* added: configure GPIO */
cd7a67a4 6244 status = write_gpio(state);
be44eb28
MCC		 6245 if (status < 0)
6246 goto error;
43dd07f7 6247
cd7a67a4 6248 state->m_drxk_state = DRXK_STOPPED;
43dd07f7 6249
cd7a67a4
MCC		 6250 if (state->m_b_power_down) {
6251 status = power_down_device(state);
ea90f011 6252 if (status < 0)
be44eb28 6253 goto error;
cd7a67a4 6254 state->m_drxk_state = DRXK_POWERED_DOWN;
be44eb28 6255 } else
cd7a67a4 6256 state->m_drxk_state = DRXK_STOPPED;
177bc7da
MCC		 6257
6258 /* Initialize the supported delivery systems */
6259 n = 0;
cd7a67a4 6260 if (state->m_has_dvbc) {
177bc7da
MCC		 6261 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6262 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6263 strlcat(state->frontend.ops.info.name, " DVB-C",
6264 sizeof(state->frontend.ops.info.name));
6265 }
cd7a67a4 6266 if (state->m_has_dvbt) {
177bc7da
MCC		 6267 state->frontend.ops.delsys[n++] = SYS_DVBT;
6268 strlcat(state->frontend.ops.info.name, " DVB-T",
6269 sizeof(state->frontend.ops.info.name));
6270 }
20bfe7ae 6271 drxk_i2c_unlock(state);
43dd07f7 6272 }
be44eb28 6273error:
20bfe7ae 6274 if (status < 0) {
cd7a67a4 6275 state->m_drxk_state = DRXK_NO_DEV;
20bfe7ae 6276 drxk_i2c_unlock(state);
3a4398f5 6277 pr_err("Error %d on %s\n", status, __func__);
20bfe7ae 6278 }
43dd07f7 6279
e716adac 6280 return status;
43dd07f7
RM		 6281}
6282
177bc7da
MCC		 6283static void load_firmware_cb(const struct firmware *fw,
6284 void *context)
6285{
6286 struct drxk_state *state = context;
6287
704a28e8 6288 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
177bc7da 6289 if (!fw) {
3a4398f5 6290 pr_err("Could not load firmware file %s.\n",
177bc7da 6291 state->microcode_name);
3a4398f5 6292 pr_info("Copy %s to your hotplug directory!\n",
177bc7da
MCC		 6293 state->microcode_name);
6294 state->microcode_name = NULL;
6295
6296 /*
6297 * As firmware is now load asynchronous, it is not possible
6298 * anymore to fail at frontend attach. We might silently
6299 * return here, and hope that the driver won't crash.
6300 * We might also change all DVB callbacks to return -ENODEV
6301 * if the device is not initialized.
6302 * As the DRX-K devices have their own internal firmware,
6303 * let's just hope that it will match a firmware revision
6304 * compatible with this driver and proceed.
6305 */
6306 }
6307 state->fw = fw;
6308
6309 init_drxk(state);
6310}
6311
fa4b2a17 6312static void drxk_release(struct dvb_frontend *fe)
43dd07f7 6313{
ebc7de22
OE		 6314 struct drxk_state *state = fe->demodulator_priv;
6315
2da67501 6316 dprintk(1, "\n");
9bc2dd7e 6317 release_firmware(state->fw);
177bc7da 6318
43dd07f7
RM		 6319 kfree(state);
6320}
6321
fa4b2a17 6322static int drxk_sleep(struct dvb_frontend *fe)
43dd07f7 6323{
ebc7de22 6324 struct drxk_state *state = fe->demodulator_priv;
43dd07f7 6325
2da67501 6326 dprintk(1, "\n");
704a28e8 6327
cd7a67a4 6328 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8 6329 return -ENODEV;
cd7a67a4 6330 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6331 return 0;
6332
cd7a67a4 6333 shut_down(state);
43dd07f7
RM		 6334 return 0;
6335}
6336
ebc7de22 6337static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
43dd07f7
RM		 6338{
6339 struct drxk_state *state = fe->demodulator_priv;
6340
257ee97e 6341 dprintk(1, ": %s\n", enable ? "enable" : "disable");
704a28e8 6342
cd7a67a4 6343 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8
MCC		 6344 return -ENODEV;
6345
43dd07f7
RM		 6346 return ConfigureI2CBridge(state, enable ? true : false);
6347}
6348
ed5452a2 6349static int drxk_set_parameters(struct dvb_frontend *fe)
43dd07f7 6350{
ed5452a2 6351 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6cb393c8 6352 u32 delsys = p->delivery_system, old_delsys;
43dd07f7
RM		 6353 struct drxk_state *state = fe->demodulator_priv;
6354 u32 IF;
6355
2da67501 6356 dprintk(1, "\n");
8513e144 6357
cd7a67a4 6358 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8
MCC		 6359 return -ENODEV;
6360
cd7a67a4 6361 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6362 return -EAGAIN;
6363
8513e144 6364 if (!fe->ops.tuner_ops.get_if_frequency) {
3a4398f5 6365 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
8513e144
MCC		 6366 return -EINVAL;
6367 }
6368
fa4b2a17
MCC		 6369 if (fe->ops.i2c_gate_ctrl)
6370 fe->ops.i2c_gate_ctrl(fe, 1);
6371 if (fe->ops.tuner_ops.set_params)
6372 fe->ops.tuner_ops.set_params(fe);
6373 if (fe->ops.i2c_gate_ctrl)
6374 fe->ops.i2c_gate_ctrl(fe, 0);
6cb393c8
MCC		 6375
6376 old_delsys = state->props.delivery_system;
fa4b2a17
MCC		 6377 state->props = *p;
6378
6cb393c8 6379 if (old_delsys != delsys) {
cd7a67a4 6380 shut_down(state);
6cb393c8
MCC		 6381 switch (delsys) {
6382 case SYS_DVBC_ANNEX_A:
6383 case SYS_DVBC_ANNEX_C:
cd7a67a4 6384 if (!state->m_has_dvbc)
6cb393c8 6385 return -EINVAL;
ab5060cd
MCC		 6386 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6387 true : false;
6cb393c8 6388 if (state->m_itut_annex_c)
cd7a67a4 6389 setoperation_mode(state, OM_QAM_ITU_C);
6cb393c8 6390 else
cd7a67a4 6391 setoperation_mode(state, OM_QAM_ITU_A);
fa4b2a17 6392 break;
6cb393c8 6393 case SYS_DVBT:
cd7a67a4 6394 if (!state->m_has_dvbt)
6cb393c8 6395 return -EINVAL;
cd7a67a4 6396 setoperation_mode(state, OM_DVBT);
6cb393c8
MCC		 6397 break;
6398 default:
fa4b2a17 6399 return -EINVAL;
6cb393c8 6400 }
2440f7af 6401 }
8513e144 6402
8513e144 6403 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
cd7a67a4 6404 start(state, 0, IF);
43dd07f7 6405
39c1cb2b 6406 /* After set_frontend, stats aren't available */
8f3741e0
MCC		 6407 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6408 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6409 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6410 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6411 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6412 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6413 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6414 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6415
e0e6ecaf 6416 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
ebc7de22 6417
43dd07f7
RM		 6418 return 0;
6419}
6420
59a7a23c
MCC		 6421static int get_strength(struct drxk_state *state, u64 *strength)
6422{
6423 int status;
cd7a67a4
MCC		 6424 struct s_cfg_agc rf_agc, if_agc;
6425 u32 total_gain = 0;
59a7a23c 6426 u32 atten = 0;
cd7a67a4 6427 u32 agc_range = 0;
59a7a23c
MCC		 6428 u16 scu_lvl = 0;
6429 u16 scu_coc = 0;
6430 /* FIXME: those are part of the tuner presets */
cd7a67a4
MCC		 6431 u16 tuner_rf_gain = 50; /* Default value on az6007 driver */
6432 u16 tuner_if_gain = 40; /* Default value on az6007 driver */
59a7a23c
MCC		 6433
6434 *strength = 0;
6435
cd7a67a4
MCC		 6436 if (is_dvbt(state)) {
6437 rf_agc = state->m_dvbt_rf_agc_cfg;
6438 if_agc = state->m_dvbt_if_agc_cfg;
6439 } else if (is_qam(state)) {
6440 rf_agc = state->m_qam_rf_agc_cfg;
6441 if_agc = state->m_qam_if_agc_cfg;
59a7a23c 6442 } else {
cd7a67a4
MCC		 6443 rf_agc = state->m_atv_rf_agc_cfg;
6444 if_agc = state->m_atv_if_agc_cfg;
59a7a23c
MCC		 6445 }
6446
cd7a67a4
MCC		 6447 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6448 /* SCU output_level */
59a7a23c
MCC		 6449 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6450 if (status < 0)
6451 return status;
6452
6453 /* SCU c.o.c. */
d259a5ee 6454 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
59a7a23c
MCC		 6455 if (status < 0)
6456 return status;
6457
6458 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
cd7a67a4 6459 rf_agc.output_level = scu_lvl + scu_coc;
59a7a23c 6460 else
cd7a67a4 6461 rf_agc.output_level = 0xffff;
59a7a23c
MCC		 6462
6463 /* Take RF gain into account */
cd7a67a4 6464 total_gain += tuner_rf_gain;
59a7a23c
MCC		 6465
6466 /* clip output value */
cd7a67a4
MCC		 6467 if (rf_agc.output_level < rf_agc.min_output_level)
6468 rf_agc.output_level = rf_agc.min_output_level;
6469 if (rf_agc.output_level > rf_agc.max_output_level)
6470 rf_agc.output_level = rf_agc.max_output_level;
59a7a23c 6471
cd7a67a4
MCC		 6472 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6473 if (agc_range > 0) {
59a7a23c 6474 atten += 100UL *
cd7a67a4
MCC		 6475 ((u32)(tuner_rf_gain)) *
6476 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6477 / agc_range;
59a7a23c
MCC		 6478 }
6479 }
6480
cd7a67a4 6481 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
59a7a23c 6482 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
cd7a67a4 6483 &if_agc.output_level);
59a7a23c
MCC		 6484 if (status < 0)
6485 return status;
6486
6487 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
cd7a67a4 6488 &if_agc.top);
59a7a23c
MCC		 6489 if (status < 0)
6490 return status;
6491
6492 /* Take IF gain into account */
cd7a67a4 6493 total_gain += (u32) tuner_if_gain;
59a7a23c
MCC		 6494
6495 /* clip output value */
cd7a67a4
MCC		 6496 if (if_agc.output_level < if_agc.min_output_level)
6497 if_agc.output_level = if_agc.min_output_level;
6498 if (if_agc.output_level > if_agc.max_output_level)
6499 if_agc.output_level = if_agc.max_output_level;
59a7a23c 6500
ab5060cd 6501 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
cd7a67a4 6502 if (agc_range > 0) {
59a7a23c 6503 atten += 100UL *
cd7a67a4
MCC		 6504 ((u32)(tuner_if_gain)) *
6505 ((u32)(if_agc.output_level - if_agc.min_output_level))
6506 / agc_range;
59a7a23c
MCC		 6507 }
6508 }
6509
6510 /*
6511 * Convert to 0..65535 scale.
6512 * If it can't be measured (AGC is disabled), just show 100%.
6513 */
cd7a67a4
MCC		 6514 if (total_gain > 0)
6515 *strength = (65535UL * atten / total_gain / 100);
59a7a23c
MCC		 6516 else
6517 *strength = 65535;
6518
6519 return 0;
6520}
6521
8f3741e0 6522static int drxk_get_stats(struct dvb_frontend *fe)
43dd07f7 6523{
8f3741e0 6524 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
43dd07f7 6525 struct drxk_state *state = fe->demodulator_priv;
8f3741e0 6526 int status;
43dd07f7 6527 u32 stat;
8f3741e0
MCC		 6528 u16 reg16;
6529 u32 post_bit_count;
6530 u32 post_bit_err_count;
6531 u32 post_bit_error_scale;
6532 u32 pre_bit_err_count;
6533 u32 pre_bit_count;
6534 u32 pkt_count;
6535 u32 pkt_error_count;
59a7a23c 6536 s32 cnr;
704a28e8 6537
cd7a67a4 6538 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8 6539 return -ENODEV;
cd7a67a4 6540 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6541 return -EAGAIN;
6542
8f3741e0
MCC		 6543 /* get status */
6544 state->fe_status = 0;
cd7a67a4 6545 get_lock_status(state, &stat);
ebc7de22 6546 if (stat == MPEG_LOCK)
8f3741e0 6547 state->fe_status |= 0x1f;
ebc7de22 6548 if (stat == FEC_LOCK)
8f3741e0 6549 state->fe_status |= 0x0f;
ebc7de22 6550 if (stat == DEMOD_LOCK)
8f3741e0
MCC		 6551 state->fe_status |= 0x07;
6552
59a7a23c
MCC		 6553 /*
6554 * Estimate signal strength from AGC
6555 */
6556 get_strength(state, &c->strength.stat[0].uvalue);
6557 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6558
6559
8f3741e0 6560 if (stat >= DEMOD_LOCK) {
cd7a67a4 6561 get_signal_to_noise(state, &cnr);
8f3741e0
MCC		 6562 c->cnr.stat[0].svalue = cnr * 100;
6563 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6564 } else {
6565 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6566 }
6567
6568 if (stat < FEC_LOCK) {
6569 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6570 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6571 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6572 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6573 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6574 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6575 return 0;
6576 }
6577
6578 /* Get post BER */
6579
6580 /* BER measurement is valid if at least FEC lock is achieved */
6581
ab5060cd
MCC		 6582 /*
6583 * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6584 * written to set nr of symbols or bits over which to measure
6585 * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6586 */
8f3741e0
MCC		 6587
6588 /* Read registers for post/preViterbi BER calculation */
6589 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
6590 if (status < 0)
6591 goto error;
6592 pre_bit_err_count = reg16;
6593
6594 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);
6595 if (status < 0)
6596 goto error;
6597 pre_bit_count = reg16;
6598
6599 /* Number of bit-errors */
6600 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);
6601 if (status < 0)
6602 goto error;
6603 post_bit_err_count = reg16;
6604
6605 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);
6606 if (status < 0)
6607 goto error;
6608 post_bit_error_scale = reg16;
6609
6610 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);
6611 if (status < 0)
6612 goto error;
6613 pkt_count = reg16;
6614
6615 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);
6616 if (status < 0)
6617 goto error;
6618 pkt_error_count = reg16;
6619 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6620
6621 post_bit_err_count *= post_bit_error_scale;
6622
6623 post_bit_count = pkt_count * 204 * 8;
6624
6625 /* Store the results */
6626 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6627 c->block_error.stat[0].uvalue += pkt_error_count;
6628 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6629 c->block_count.stat[0].uvalue += pkt_count;
6630
6631 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6632 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6633 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6634 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6635
6636 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6637 c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6638 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6639 c->post_bit_count.stat[0].uvalue += post_bit_count;
6640
8f3741e0
MCC		 6641error:
6642 return status;
6643}
6644
6645
0df289a2 6646static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
8f3741e0
MCC		 6647{
6648 struct drxk_state *state = fe->demodulator_priv;
6649 int rc;
6650
6651 dprintk(1, "\n");
6652
6653 rc = drxk_get_stats(fe);
6654 if (rc < 0)
6655 return rc;
6656
6657 *status = state->fe_status;
6658
43dd07f7
RM		 6659 return 0;
6660}
6661
ebc7de22
OE		 6662static int drxk_read_signal_strength(struct dvb_frontend *fe,
6663 u16 *strength)
43dd07f7
RM		 6664{
6665 struct drxk_state *state = fe->demodulator_priv;
340e7696 6666 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
43dd07f7 6667
2da67501 6668 dprintk(1, "\n");
704a28e8 6669
cd7a67a4 6670 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8 6671 return -ENODEV;
cd7a67a4 6672 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6673 return -EAGAIN;
6674
340e7696 6675 *strength = c->strength.stat[0].uvalue;
43dd07f7
RM		 6676 return 0;
6677}
6678
6679static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6680{
6681 struct drxk_state *state = fe->demodulator_priv;
6682 s32 snr2;
6683
2da67501 6684 dprintk(1, "\n");
704a28e8 6685
cd7a67a4 6686 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8 6687 return -ENODEV;
cd7a67a4 6688 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6689 return -EAGAIN;
6690
cd7a67a4 6691 get_signal_to_noise(state, &snr2);
8f3741e0
MCC		 6692
6693 /* No negative SNR, clip to zero */
6694 if (snr2 < 0)
6695 snr2 = 0;
ebc7de22 6696 *snr = snr2 & 0xffff;
43dd07f7
RM		 6697 return 0;
6698}
6699
6700static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6701{
6702 struct drxk_state *state = fe->demodulator_priv;
6703 u16 err;
6704
2da67501 6705 dprintk(1, "\n");
704a28e8 6706
cd7a67a4 6707 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8 6708 return -ENODEV;
cd7a67a4 6709 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6710 return -EAGAIN;
6711
cd7a67a4 6712 dvbtqam_get_acc_pkt_err(state, &err);
43dd07f7
RM		 6713 *ucblocks = (u32) err;
6714 return 0;
6715}
6716
ab5060cd
MCC		 6717static int drxk_get_tune_settings(struct dvb_frontend *fe,
6718 struct dvb_frontend_tune_settings *sets)
43dd07f7 6719{
704a28e8 6720 struct drxk_state *state = fe->demodulator_priv;
fa4b2a17 6721 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2da67501
MCC		 6722
6723 dprintk(1, "\n");
704a28e8 6724
cd7a67a4 6725 if (state->m_drxk_state == DRXK_NO_DEV)
704a28e8 6726 return -ENODEV;
cd7a67a4 6727 if (state->m_drxk_state == DRXK_UNINITIALIZED)
704a28e8
MCC		 6728 return -EAGAIN;
6729
fa4b2a17
MCC		 6730 switch (p->delivery_system) {
6731 case SYS_DVBC_ANNEX_A:
6732 case SYS_DVBC_ANNEX_C:
dc66d7f4 6733 case SYS_DVBT:
fa4b2a17
MCC		 6734 sets->min_delay_ms = 3000;
6735 sets->max_drift = 0;
6736 sets->step_size = 0;
6737 return 0;
6738 default:
fa4b2a17
MCC		 6739 return -EINVAL;
6740 }
43dd07f7
RM		 6741}
6742
bd336e63 6743static const struct dvb_frontend_ops drxk_ops = {
fa4b2a17 6744 /* .delsys will be filled dynamically */
43dd07f7 6745 .info = {
fa4b2a17
MCC		 6746 .name = "DRXK",
6747 .frequency_min = 47000000,
6748 .frequency_max = 865000000,
6749 /* For DVB-C */
6750 .symbol_rate_min = 870000,
6751 .symbol_rate_max = 11700000,
6752 /* For DVB-T */
6753 .frequency_stepsize = 166667,
6754
6755 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6756 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6757 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6758 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6759 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6760 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6761 },
6762
6763 .release = drxk_release,
6764 .sleep = drxk_sleep,
43dd07f7
RM		 6765 .i2c_gate_ctrl = drxk_gate_ctrl,
6766
ed5452a2 6767 .set_frontend = drxk_set_parameters,
fa4b2a17 6768 .get_tune_settings = drxk_get_tune_settings,
43dd07f7
RM		 6769
6770 .read_status = drxk_read_status,
43dd07f7
RM		 6771 .read_signal_strength = drxk_read_signal_strength,
6772 .read_snr = drxk_read_snr,
6773 .read_ucblocks = drxk_read_ucblocks,
6774};
6775
0fc55e81 6776struct dvb_frontend *drxk_attach(const struct drxk_config *config,
fa4b2a17 6777 struct i2c_adapter *i2c)
43dd07f7 6778{
8f3741e0 6779 struct dtv_frontend_properties *p;
43dd07f7 6780 struct drxk_state *state = NULL;
0fc55e81 6781 u8 adr = config->adr;
177bc7da 6782 int status;
43dd07f7 6783
2da67501 6784 dprintk(1, "\n");
ebc7de22 6785 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
43dd07f7
RM		 6786 if (!state)
6787 return NULL;
6788
ebc7de22
OE		 6789 state->i2c = i2c;
6790 state->demod_address = adr;
e076c92e 6791 state->single_master = config->single_master;
e4f4f875 6792 state->microcode_name = config->microcode_name;
9e23f50a 6793 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
f1fe1b75 6794 state->no_i2c_bridge = config->no_i2c_bridge;
90796aca
MCC		 6795 state->antenna_gpio = config->antenna_gpio;
6796 state->antenna_dvbt = config->antenna_dvbt;
cd7a67a4 6797 state->m_chunk_size = config->chunk_size;
d5856813 6798 state->enable_merr_cfg = config->enable_merr_cfg;
90796aca 6799
67f04617 6800 if (config->dynamic_clk) {
5a7f7b79
MCC		 6801 state->m_dvbt_static_clk = false;
6802 state->m_dvbc_static_clk = false;
67f04617 6803 } else {
5a7f7b79
MCC		 6804 state->m_dvbt_static_clk = true;
6805 state->m_dvbc_static_clk = true;
67f04617
MCC		 6806 }
6807
6fb65a66
MCC		 6808
6809 if (config->mpeg_out_clk_strength)
cd7a67a4 6810 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6fb65a66 6811 else
cd7a67a4 6812 state->m_ts_clockk_strength = 0x06;
6fb65a66 6813
534e0481 6814 if (config->parallel_ts)
cd7a67a4 6815 state->m_enable_parallel = true;
534e0481 6816 else
cd7a67a4 6817 state->m_enable_parallel = false;
534e0481 6818
90796aca 6819 /* NOTE: as more UIO bits will be used, add them to the mask */
cd7a67a4 6820 state->uio_mask = config->antenna_gpio;
90796aca
MCC		 6821
6822 /* Default gpio to DVB-C */
6823 if (!state->antenna_dvbt && state->antenna_gpio)
cd7a67a4 6824 state->m_gpio |= state->antenna_gpio;
90796aca 6825 else
cd7a67a4 6826 state->m_gpio &= ~state->antenna_gpio;
43dd07f7
RM		 6827
6828 mutex_init(&state->mutex);
43dd07f7 6829
fa4b2a17
MCC		 6830 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6831 state->frontend.demodulator_priv = state;
43dd07f7
RM		 6832
6833 init_state(state);
cf694b14 6834
177bc7da
MCC		 6835 /* Load firmware and initialize DRX-K */
6836 if (state->microcode_name) {
4b819724 6837 const struct firmware *fw = NULL;
8e30783b 6838
4b819724
MCC		 6839 status = request_firmware(&fw, state->microcode_name,
6840 state->i2c->dev.parent);
6841 if (status < 0)
6842 fw = NULL;
6843 load_firmware_cb(fw, state);
177bc7da
MCC		 6844 } else if (init_drxk(state) < 0)
6845 goto error;
0d3e6fe7 6846
8f3741e0
MCC		 6847
6848 /* Initialize stats */
6849 p = &state->frontend.dtv_property_cache;
6850 p->strength.len = 1;
6851 p->cnr.len = 1;
6852 p->block_error.len = 1;
6853 p->block_count.len = 1;
6854 p->pre_bit_error.len = 1;
6855 p->pre_bit_count.len = 1;
6856 p->post_bit_error.len = 1;
6857 p->post_bit_count.len = 1;
6858
6859 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6860 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6861 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6862 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6863 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6864 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6865 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6866 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6867
3a4398f5 6868 pr_info("frontend initialized.\n");
fa4b2a17 6869 return &state->frontend;
43dd07f7
RM		 6870
6871error:
3a4398f5 6872 pr_err("not found\n");
43dd07f7
RM		 6873 kfree(state);
6874 return NULL;
6875}
ebc7de22 6876EXPORT_SYMBOL(drxk_attach);
43dd07f7
RM		 6877
6878MODULE_DESCRIPTION("DRX-K driver");
6879MODULE_AUTHOR("Ralph Metzler");
6880MODULE_LICENSE("GPL");
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