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[media] lgdt3306a: don't go past the buffer
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / lgdt3306a.c
CommitLineData
b63b36fa
FR		 1/*
2 * Support for LGDT3306A - 8VSB/QAM-B
3 *
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include <asm/div64.h>
25#include <linux/dvb/frontend.h>
26#include "dvb_math.h"
27#include "lgdt3306a.h"
28
29
30static int debug;
31module_param(debug, int, 0644);
32MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
33
34#define DBG_INFO 1
35#define DBG_REG 2
8e8cd34e 36#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
b63b36fa
FR		 37
38#define lg_printk(kern, fmt, arg...) \
39 printk(kern "%s(): " fmt, __func__, ##arg)
40
41#define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3306a: " fmt, ##arg)
42#define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
43#define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
44#define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
45 lg_printk(KERN_DEBUG, fmt, ##arg)
46#define lg_reg(fmt, arg...) if (debug & DBG_REG) \
47 lg_printk(KERN_DEBUG, fmt, ##arg)
48
49#define lg_chkerr(ret) \
50({ \
51 int __ret; \
52 __ret = (ret < 0); \
53 if (__ret) \
54 lg_err("error %d on line %d\n", ret, __LINE__); \
55 __ret; \
56})
57
58struct lgdt3306a_state {
59 struct i2c_adapter *i2c_adap;
60 const struct lgdt3306a_config *cfg;
61
62 struct dvb_frontend frontend;
63
64 fe_modulation_t current_modulation;
65 u32 current_frequency;
66 u32 snr;
67};
68
69/* -----------------------------------------------
70 LG3306A Register Usage
71 (LG does not really name the registers, so this code does not either)
72 0000 -> 00FF Common control and status
73 1000 -> 10FF Synchronizer control and status
74 1F00 -> 1FFF Smart Antenna control and status
75 2100 -> 21FF VSB Equalizer control and status
76 2800 -> 28FF QAM Equalizer control and status
77 3000 -> 30FF FEC control and status
78 ---------------------------------------------- */
79
f883d603
MIK		 80enum lgdt3306a_lock_status {
81 LG3306_UNLOCK = 0x00,
82 LG3306_LOCK = 0x01,
4937ba94 83 LG3306_UNKNOWN_LOCK = 0xff
f883d603 84};
b63b36fa 85
f883d603 86enum lgdt3306a_neverlock_status {
b63b36fa
FR		 87 LG3306_NL_INIT = 0x00,
88 LG3306_NL_PROCESS = 0x01,
89 LG3306_NL_LOCK = 0x02,
90 LG3306_NL_FAIL = 0x03,
4937ba94 91 LG3306_NL_UNKNOWN = 0xff
f883d603 92};
b63b36fa 93
f883d603
MIK		 94enum lgdt3306a_modulation {
95 LG3306_VSB = 0x00,
96 LG3306_QAM64 = 0x01,
97 LG3306_QAM256 = 0x02,
4937ba94 98 LG3306_UNKNOWN_MODE = 0xff
f883d603 99};
b63b36fa 100
f883d603 101enum lgdt3306a_lock_check {
b63b36fa
FR		 102 LG3306_SYNC_LOCK,
103 LG3306_FEC_LOCK,
104 LG3306_TR_LOCK,
105 LG3306_AGC_LOCK,
f883d603 106};
b63b36fa
FR		 107
108
109#ifdef DBG_DUMP
110static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
111static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
112#endif
113
114
115static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
116{
117 int ret;
118 u8 buf[] = { reg >> 8, reg & 0xff, val };
119 struct i2c_msg msg = {
120 .addr = state->cfg->i2c_addr, .flags = 0,
121 .buf = buf, .len = 3,
122 };
123
124 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
125
126 ret = i2c_transfer(state->i2c_adap, &msg, 1);
127
128 if (ret != 1) {
129 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
130 msg.buf[0], msg.buf[1], msg.buf[2], ret);
131 if (ret < 0)
132 return ret;
133 else
134 return -EREMOTEIO;
135 }
136 return 0;
137}
138
139static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
140{
141 int ret;
142 u8 reg_buf[] = { reg >> 8, reg & 0xff };
143 struct i2c_msg msg[] = {
144 { .addr = state->cfg->i2c_addr,
145 .flags = 0, .buf = reg_buf, .len = 2 },
146 { .addr = state->cfg->i2c_addr,
147 .flags = I2C_M_RD, .buf = val, .len = 1 },
148 };
149
150 ret = i2c_transfer(state->i2c_adap, msg, 2);
151
152 if (ret != 2) {
153 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
154 state->cfg->i2c_addr, reg, ret);
155 if (ret < 0)
156 return ret;
157 else
158 return -EREMOTEIO;
159 }
160 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
161
162 return 0;
163}
164
165#define read_reg(state, reg) \
166({ \
167 u8 __val; \
168 int ret = lgdt3306a_read_reg(state, reg, &__val); \
169 if (lg_chkerr(ret)) \
170 __val = 0; \
171 __val; \
172})
173
174static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
175 u16 reg, int bit, int onoff)
176{
177 u8 val;
178 int ret;
179
180 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
181
182 ret = lgdt3306a_read_reg(state, reg, &val);
183 if (lg_chkerr(ret))
184 goto fail;
185
186 val &= ~(1 << bit);
187 val |= (onoff & 1) << bit;
188
189 ret = lgdt3306a_write_reg(state, reg, val);
190 lg_chkerr(ret);
191fail:
192 return ret;
193}
194
195/* ------------------------------------------------------------------------ */
196
197static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
198{
199 int ret;
200
201 lg_dbg("\n");
202
203 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
204 if (lg_chkerr(ret))
205 goto fail;
206
207 msleep(20);
208 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
209 lg_chkerr(ret);
210
211fail:
212 return ret;
213}
214
215static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
216 enum lgdt3306a_mpeg_mode mode)
217{
218 u8 val;
219 int ret;
220
221 lg_dbg("(%d)\n", mode);
8e8cd34e
MIK		 222 /* transport packet format */
223 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */
b63b36fa
FR		 224 if (lg_chkerr(ret))
225 goto fail;
226
8e8cd34e
MIK		 227 /* start of packet signal duration */
228 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */
b63b36fa
FR		 229 if (lg_chkerr(ret))
230 goto fail;
231
232 ret = lgdt3306a_read_reg(state, 0x0070, &val);
233 if (lg_chkerr(ret))
234 goto fail;
235
8e8cd34e 236 val |= 0x10; /* TPCLKSUPB=0x10 */
b63b36fa 237
8e8cd34e 238 if (mode == LGDT3306A_MPEG_PARALLEL)
b63b36fa
FR		 239 val &= ~0x10;
240
241 ret = lgdt3306a_write_reg(state, 0x0070, val);
242 lg_chkerr(ret);
243
244fail:
245 return ret;
246}
247
248static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
249 enum lgdt3306a_tp_clock_edge edge,
250 enum lgdt3306a_tp_valid_polarity valid)
251{
252 u8 val;
253 int ret;
254
255 lg_dbg("edge=%d, valid=%d\n", edge, valid);
256
257 ret = lgdt3306a_read_reg(state, 0x0070, &val);
258 if (lg_chkerr(ret))
259 goto fail;
260
8e8cd34e 261 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
b63b36fa 262
8e8cd34e 263 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
b63b36fa 264 val |= 0x04;
8e8cd34e 265 if (valid == LGDT3306A_TP_VALID_HIGH)
b63b36fa
FR		 266 val |= 0x02;
267
268 ret = lgdt3306a_write_reg(state, 0x0070, val);
269 lg_chkerr(ret);
270
271fail:
272 return ret;
273}
274
275static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
276 int mode)
277{
278 u8 val;
279 int ret;
280
281 lg_dbg("(%d)\n", mode);
282
8e8cd34e 283 if (mode) {
b63b36fa
FR		 284 ret = lgdt3306a_read_reg(state, 0x0070, &val);
285 if (lg_chkerr(ret))
286 goto fail;
4937ba94 287 val &= ~0xa8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */
b63b36fa
FR		 288 ret = lgdt3306a_write_reg(state, 0x0070, val);
289 if (lg_chkerr(ret))
290 goto fail;
291
8e8cd34e 292 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
b63b36fa
FR		 293 if (lg_chkerr(ret))
294 goto fail;
295
296 } else {
8e8cd34e 297 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */
b63b36fa
FR		 298 if (lg_chkerr(ret))
299 goto fail;
300
301 ret = lgdt3306a_read_reg(state, 0x0070, &val);
302 if (lg_chkerr(ret))
303 goto fail;
304
4937ba94 305 val |= 0xa8; /* enable bus */
b63b36fa
FR		 306 ret = lgdt3306a_write_reg(state, 0x0070, val);
307 if (lg_chkerr(ret))
308 goto fail;
309 }
310
311fail:
312 return ret;
313}
314
8e8cd34e 315static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
b63b36fa
FR		 316{
317 struct lgdt3306a_state *state = fe->demodulator_priv;
318
319 lg_dbg("acquire=%d\n", acquire);
320
321 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
322
323}
324
325static int lgdt3306a_power(struct lgdt3306a_state *state,
326 int mode)
327{
328 int ret;
329
330 lg_dbg("(%d)\n", mode);
331
8e8cd34e
MIK		 332 if (mode == 0) {
333 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */
b63b36fa
FR		 334 if (lg_chkerr(ret))
335 goto fail;
336
8e8cd34e 337 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */
b63b36fa
FR		 338 if (lg_chkerr(ret))
339 goto fail;
340
341 } else {
8e8cd34e 342 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */
b63b36fa
FR		 343 if (lg_chkerr(ret))
344 goto fail;
345
8e8cd34e 346 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */
b63b36fa
FR		 347 if (lg_chkerr(ret))
348 goto fail;
349 }
350
351#ifdef DBG_DUMP
352 lgdt3306a_DumpAllRegs(state);
353#endif
354fail:
355 return ret;
356}
357
358
359static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
360{
361 u8 val;
362 int ret;
363
364 lg_dbg("\n");
365
8e8cd34e 366 /* 0. Spectrum inversion detection manual; spectrum inverted */
b63b36fa 367 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 368 val &= 0xf7; /* SPECINVAUTO Off */
8e8cd34e 369 val |= 0x04; /* SPECINV On */
b63b36fa
FR		 370 ret = lgdt3306a_write_reg(state, 0x0002, val);
371 if (lg_chkerr(ret))
372 goto fail;
373
8e8cd34e 374 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 375 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
376 if (lg_chkerr(ret))
377 goto fail;
378
8e8cd34e 379 /* 2. Bandwidth mode for VSB(6MHz) */
b63b36fa 380 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94
MCC		 381 val &= 0xe3;
382 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
b63b36fa
FR		 383 ret = lgdt3306a_write_reg(state, 0x0009, val);
384 if (lg_chkerr(ret))
385 goto fail;
386
8e8cd34e 387 /* 3. QAM mode detection mode(None) */
b63b36fa 388 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 389 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
b63b36fa
FR		 390 ret = lgdt3306a_write_reg(state, 0x0009, val);
391 if (lg_chkerr(ret))
392 goto fail;
393
8e8cd34e 394 /* 4. ADC sampling frequency rate(2x sampling) */
4937ba94
MCC		 395 ret = lgdt3306a_read_reg(state, 0x000d, &val);
396 val &= 0xbf; /* SAMPLING4XFEN=0 */
397 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 398 if (lg_chkerr(ret))
399 goto fail;
400
8e8cd34e
MIK		 401#if 0
402 /* FGR - disable any AICC filtering, testing only */
403
b63b36fa
FR		 404 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
405 if (lg_chkerr(ret))
406 goto fail;
407
8e8cd34e 408 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 409 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
410 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 411 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
412
8e8cd34e 413 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 414 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
415 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
416 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 417
8e8cd34e 418 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 419 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
420 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 421 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 422
8e8cd34e 423 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 424 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
425 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
426 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
427
8e8cd34e
MIK		 428#else
429 /* FGR - this works well for HVR-1955,1975 */
430
431 /* 5. AICCOPMODE NT N-1 Adj. */
b63b36fa
FR		 432 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
433 if (lg_chkerr(ret))
434 goto fail;
435
8e8cd34e 436 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 437 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
438 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 439 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
440
8e8cd34e 441 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 442 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
443 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
444 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 445
8e8cd34e 446 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 447 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
448 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 449 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 450
8e8cd34e 451 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 452 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
453 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
454 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
455#endif
456
4937ba94
MCC		 457 ret = lgdt3306a_read_reg(state, 0x001e, &val);
458 val &= 0x0f;
459 val |= 0xa0;
460 ret = lgdt3306a_write_reg(state, 0x001e, val);
b63b36fa
FR		 461
462 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
463
464 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
465
4937ba94
MCC		 466 ret = lgdt3306a_read_reg(state, 0x211f, &val);
467 val &= 0xef;
468 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa
FR		 469
470 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
471
472 ret = lgdt3306a_read_reg(state, 0x1061, &val);
4937ba94 473 val &= 0xf8;
b63b36fa
FR		 474 val |= 0x04;
475 ret = lgdt3306a_write_reg(state, 0x1061, val);
476
4937ba94
MCC		 477 ret = lgdt3306a_read_reg(state, 0x103d, &val);
478 val &= 0xcf;
479 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa
FR		 480
481 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
482
483 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 484 val &= 0x3f;
b63b36fa
FR		 485 ret = lgdt3306a_write_reg(state, 0x2141, val);
486
487 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94 488 val &= 0x0f;
b63b36fa
FR		 489 val |= 0x70;
490 ret = lgdt3306a_write_reg(state, 0x2135, val);
491
492 ret = lgdt3306a_read_reg(state, 0x0003, &val);
4937ba94 493 val &= 0xf7;
b63b36fa
FR		 494 ret = lgdt3306a_write_reg(state, 0x0003, val);
495
4937ba94
MCC		 496 ret = lgdt3306a_read_reg(state, 0x001c, &val);
497 val &= 0x7f;
498 ret = lgdt3306a_write_reg(state, 0x001c, val);
b63b36fa 499
8e8cd34e 500 /* 6. EQ step size */
b63b36fa 501 ret = lgdt3306a_read_reg(state, 0x2179, &val);
4937ba94 502 val &= 0xf8;
b63b36fa
FR		 503 ret = lgdt3306a_write_reg(state, 0x2179, val);
504
4937ba94
MCC		 505 ret = lgdt3306a_read_reg(state, 0x217a, &val);
506 val &= 0xf8;
507 ret = lgdt3306a_write_reg(state, 0x217a, val);
b63b36fa 508
8e8cd34e 509 /* 7. Reset */
b63b36fa
FR		 510 ret = lgdt3306a_soft_reset(state);
511 if (lg_chkerr(ret))
512 goto fail;
513
514 lg_dbg("complete\n");
515fail:
516 return ret;
517}
518
519static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
520{
521 u8 val;
522 int ret;
523
524 lg_dbg("modulation=%d\n", modulation);
525
8e8cd34e 526 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 527 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
528 if (lg_chkerr(ret))
529 goto fail;
530
8e8cd34e 531 /* 1a. Spectrum inversion detection to Auto */
b63b36fa 532 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 533 val &= 0xfb; /* SPECINV Off */
8e8cd34e 534 val |= 0x08; /* SPECINVAUTO On */
b63b36fa
FR		 535 ret = lgdt3306a_write_reg(state, 0x0002, val);
536 if (lg_chkerr(ret))
537 goto fail;
538
8e8cd34e 539 /* 2. Bandwidth mode for QAM */
b63b36fa 540 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 541 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
b63b36fa
FR		 542 ret = lgdt3306a_write_reg(state, 0x0009, val);
543 if (lg_chkerr(ret))
544 goto fail;
545
8e8cd34e 546 /* 3. : 64QAM/256QAM detection(manual, auto) */
b63b36fa 547 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 548 val &= 0xfc;
8e8cd34e 549 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
b63b36fa
FR		 550 ret = lgdt3306a_write_reg(state, 0x0009, val);
551 if (lg_chkerr(ret))
552 goto fail;
553
8e8cd34e 554 /* 3a. : 64QAM/256QAM selection for manual */
b63b36fa 555 ret = lgdt3306a_read_reg(state, 0x101a, &val);
4937ba94 556 val &= 0xf8;
8e8cd34e
MIK		 557 if (modulation == QAM_64)
558 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
559 else
560 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
561
b63b36fa
FR		 562 ret = lgdt3306a_write_reg(state, 0x101a, val);
563 if (lg_chkerr(ret))
564 goto fail;
565
8e8cd34e 566 /* 4. ADC sampling frequency rate(4x sampling) */
4937ba94
MCC		 567 ret = lgdt3306a_read_reg(state, 0x000d, &val);
568 val &= 0xbf;
8e8cd34e 569 val |= 0x40; /* SAMPLING4XFEN=1 */
4937ba94 570 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 571 if (lg_chkerr(ret))
572 goto fail;
573
8e8cd34e 574 /* 5. No AICC operation in QAM mode */
b63b36fa
FR		 575 ret = lgdt3306a_read_reg(state, 0x0024, &val);
576 val &= 0x00;
577 ret = lgdt3306a_write_reg(state, 0x0024, val);
578 if (lg_chkerr(ret))
579 goto fail;
580
8e8cd34e 581 /* 6. Reset */
b63b36fa
FR		 582 ret = lgdt3306a_soft_reset(state);
583 if (lg_chkerr(ret))
584 goto fail;
585
586 lg_dbg("complete\n");
587fail:
588 return ret;
589}
590
591static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
592 struct dtv_frontend_properties *p)
593{
594 int ret;
595
596 lg_dbg("\n");
597
598 switch (p->modulation) {
599 case VSB_8:
600 ret = lgdt3306a_set_vsb(state);
601 break;
602 case QAM_64:
603 ret = lgdt3306a_set_qam(state, QAM_64);
604 break;
605 case QAM_256:
606 ret = lgdt3306a_set_qam(state, QAM_256);
607 break;
608 default:
609 return -EINVAL;
610 }
611 if (lg_chkerr(ret))
612 goto fail;
613
614 state->current_modulation = p->modulation;
615
616fail:
617 return ret;
618}
619
620/* ------------------------------------------------------------------------ */
621
622static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
623 struct dtv_frontend_properties *p)
624{
8e8cd34e 625 /* TODO: anything we want to do here??? */
b63b36fa
FR		 626 lg_dbg("\n");
627
628 switch (p->modulation) {
629 case VSB_8:
630 break;
631 case QAM_64:
632 case QAM_256:
633 break;
634 default:
635 return -EINVAL;
636 }
637 return 0;
638}
639
640/* ------------------------------------------------------------------------ */
641
642static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
643 int inversion)
644{
645 int ret;
646
647 lg_dbg("(%d)\n", inversion);
648
8e8cd34e 649 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
b63b36fa
FR		 650 return ret;
651}
652
653static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
654 int enabled)
655{
656 int ret;
657
658 lg_dbg("(%d)\n", enabled);
659
8e8cd34e
MIK		 660 /* 0=Manual 1=Auto(QAM only) */
661 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */
b63b36fa
FR		 662 return ret;
663}
664
665static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
666 struct dtv_frontend_properties *p,
667 int inversion)
668{
669 int ret = 0;
670
671 lg_dbg("(%d)\n", inversion);
8e8cd34e
MIK		 672#if 0
673/* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */
b63b36fa
FR		 674
675 ret = lgdt3306a_set_inversion(state, inversion);
676
677 switch (p->modulation) {
678 case VSB_8:
8e8cd34e 679 ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */
b63b36fa
FR		 680 break;
681 case QAM_64:
682 case QAM_256:
8e8cd34e 683 ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */
b63b36fa
FR		 684 break;
685 default:
686 ret = -EINVAL;
687 }
688#endif
689 return ret;
690}
691
692static int lgdt3306a_set_if(struct lgdt3306a_state *state,
693 struct dtv_frontend_properties *p)
694{
695 int ret;
696 u16 if_freq_khz;
697 u8 nco1, nco2;
698
699 switch (p->modulation) {
700 case VSB_8:
701 if_freq_khz = state->cfg->vsb_if_khz;
702 break;
703 case QAM_64:
704 case QAM_256:
705 if_freq_khz = state->cfg->qam_if_khz;
706 break;
707 default:
708 return -EINVAL;
709 }
710
8e8cd34e 711 switch (if_freq_khz) {
b63b36fa
FR		 712 default:
713 lg_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz);
8e8cd34e 714 /* fallthrough */
34a5a2f8 715 case 3250: /* 3.25Mhz */
b63b36fa
FR		 716 nco1 = 0x34;
717 nco2 = 0x00;
718 break;
34a5a2f8 719 case 3500: /* 3.50Mhz */
b63b36fa
FR		 720 nco1 = 0x38;
721 nco2 = 0x00;
722 break;
34a5a2f8 723 case 4000: /* 4.00Mhz */
b63b36fa
FR		 724 nco1 = 0x40;
725 nco2 = 0x00;
726 break;
34a5a2f8 727 case 5000: /* 5.00Mhz */
b63b36fa
FR		 728 nco1 = 0x50;
729 nco2 = 0x00;
730 break;
8e8cd34e 731 case 5380: /* 5.38Mhz */
b63b36fa
FR		 732 nco1 = 0x56;
733 nco2 = 0x14;
734 break;
735 }
736 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
737 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
738
739 lg_dbg("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
740
741 return 0;
742}
743
744/* ------------------------------------------------------------------------ */
745
746static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
747{
748 struct lgdt3306a_state *state = fe->demodulator_priv;
749
8e8cd34e 750 if (state->cfg->deny_i2c_rptr) {
b63b36fa
FR		 751 lg_dbg("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
752 return 0;
753 }
754 lg_dbg("(%d)\n", enable);
755
8e8cd34e 756 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */
b63b36fa
FR		 757}
758
759static int lgdt3306a_sleep(struct lgdt3306a_state *state)
760{
761 int ret;
762
763 lg_dbg("\n");
8e8cd34e 764 state->current_frequency = -1; /* force re-tune, when we wake */
b63b36fa 765
8e8cd34e 766 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
b63b36fa
FR		 767 if (lg_chkerr(ret))
768 goto fail;
769
8e8cd34e 770 ret = lgdt3306a_power(state, 0); /* power down */
b63b36fa
FR		 771 lg_chkerr(ret);
772
773fail:
774 return 0;
775}
776
777static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
778{
779 struct lgdt3306a_state *state = fe->demodulator_priv;
780
781 return lgdt3306a_sleep(state);
782}
783
784static int lgdt3306a_init(struct dvb_frontend *fe)
785{
786 struct lgdt3306a_state *state = fe->demodulator_priv;
787 u8 val;
788 int ret;
789
790 lg_dbg("\n");
791
8e8cd34e
MIK		 792 /* 1. Normal operation mode */
793 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
b63b36fa
FR		 794 if (lg_chkerr(ret))
795 goto fail;
796
8e8cd34e 797 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
b63b36fa
FR		 798 ret = lgdt3306a_set_inversion_auto(state, 0);
799 if (lg_chkerr(ret))
800 goto fail;
801
8e8cd34e 802 /* 3. Spectrum inversion(According to the tuner configuration) */
b63b36fa
FR		 803 ret = lgdt3306a_set_inversion(state, 1);
804 if (lg_chkerr(ret))
805 goto fail;
806
8e8cd34e
MIK		 807 /* 4. Peak-to-peak voltage of ADC input signal */
808 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
b63b36fa
FR		 809 if (lg_chkerr(ret))
810 goto fail;
811
8e8cd34e
MIK		 812 /* 5. ADC output data capture clock phase */
813 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */
b63b36fa
FR		 814 if (lg_chkerr(ret))
815 goto fail;
816
8e8cd34e
MIK		 817 /* 5a. ADC sampling clock source */
818 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
b63b36fa
FR		 819 if (lg_chkerr(ret))
820 goto fail;
821
8e8cd34e
MIK		 822 /* 6. Automatic PLL set */
823 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */
b63b36fa
FR		 824 if (lg_chkerr(ret))
825 goto fail;
826
8e8cd34e
MIK		 827 if (state->cfg->xtalMHz == 24) { /* 24MHz */
828 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
b63b36fa
FR		 829 ret = lgdt3306a_read_reg(state, 0x0005, &val);
830 if (lg_chkerr(ret))
831 goto fail;
4937ba94 832 val &= 0xc0;
b63b36fa
FR		 833 val |= 0x25;
834 ret = lgdt3306a_write_reg(state, 0x0005, val);
835 if (lg_chkerr(ret))
836 goto fail;
837 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
838 if (lg_chkerr(ret))
839 goto fail;
840
8e8cd34e 841 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
4937ba94 842 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 843 if (lg_chkerr(ret))
844 goto fail;
4937ba94 845 val &= 0xc0;
b63b36fa 846 val |= 0x18;
4937ba94 847 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 848 if (lg_chkerr(ret))
849 goto fail;
850
8e8cd34e
MIK		 851 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
852 /* 7. Frequency for PLL output */
b63b36fa
FR		 853 ret = lgdt3306a_read_reg(state, 0x0005, &val);
854 if (lg_chkerr(ret))
855 goto fail;
4937ba94 856 val &= 0xc0;
b63b36fa
FR		 857 val |= 0x25;
858 ret = lgdt3306a_write_reg(state, 0x0005, val);
859 if (lg_chkerr(ret))
860 goto fail;
861 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
862 if (lg_chkerr(ret))
863 goto fail;
864
8e8cd34e 865 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
4937ba94 866 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 867 if (lg_chkerr(ret))
868 goto fail;
4937ba94 869 val &= 0xc0;
b63b36fa 870 val |= 0x19;
4937ba94 871 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 872 if (lg_chkerr(ret))
873 goto fail;
874 } else {
875 lg_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
876 }
8e8cd34e 877#if 0
4937ba94
MCC		 878 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
879 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
8e8cd34e 880#endif
b63b36fa 881
8e8cd34e
MIK		 882 /* 9. Center frequency of input signal of ADC */
883 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
884 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
b63b36fa 885
8e8cd34e
MIK		 886 /* 10. Fixed gain error value */
887 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
b63b36fa 888
8e8cd34e 889 /* 10a. VSB TR BW gear shift initial step */
4937ba94
MCC		 890 ret = lgdt3306a_read_reg(state, 0x103c, &val);
891 val &= 0x0f;
8e8cd34e 892 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
4937ba94 893 ret = lgdt3306a_write_reg(state, 0x103c, val);
b63b36fa 894
8e8cd34e 895 /* 10b. Timing offset calibration in low temperature for VSB */
4937ba94
MCC		 896 ret = lgdt3306a_read_reg(state, 0x103d, &val);
897 val &= 0xfc;
b63b36fa 898 val |= 0x03;
4937ba94 899 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa 900
8e8cd34e 901 /* 10c. Timing offset calibration in low temperature for QAM */
b63b36fa 902 ret = lgdt3306a_read_reg(state, 0x1036, &val);
4937ba94
MCC		 903 val &= 0xf0;
904 val |= 0x0c;
b63b36fa
FR		 905 ret = lgdt3306a_write_reg(state, 0x1036, val);
906
8e8cd34e 907 /* 11. Using the imaginary part of CIR in CIR loading */
4937ba94
MCC		 908 ret = lgdt3306a_read_reg(state, 0x211f, &val);
909 val &= 0xef; /* do not use imaginary of CIR */
910 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa 911
8e8cd34e 912 /* 12. Control of no signal detector function */
b63b36fa 913 ret = lgdt3306a_read_reg(state, 0x2849, &val);
4937ba94 914 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
b63b36fa
FR		 915 ret = lgdt3306a_write_reg(state, 0x2849, val);
916
8e8cd34e 917 /* FGR - put demod in some known mode */
b63b36fa
FR		 918 ret = lgdt3306a_set_vsb(state);
919
8e8cd34e 920 /* 13. TP stream format */
b63b36fa
FR		 921 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
922
8e8cd34e 923 /* 14. disable output buses */
b63b36fa
FR		 924 ret = lgdt3306a_mpeg_tristate(state, 1);
925
8e8cd34e 926 /* 15. Sleep (in reset) */
b63b36fa
FR		 927 ret = lgdt3306a_sleep(state);
928 lg_chkerr(ret);
929
930fail:
931 return ret;
932}
933
934static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
935{
936 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
937 struct lgdt3306a_state *state = fe->demodulator_priv;
938 int ret;
939
940 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
941
8e8cd34e
MIK		 942 if (state->current_frequency == p->frequency &&
943 state->current_modulation == p->modulation) {
b63b36fa
FR		 944 lg_dbg(" (already set, skipping ...)\n");
945 return 0;
946 }
947 state->current_frequency = -1;
948 state->current_modulation = -1;
949
8e8cd34e 950 ret = lgdt3306a_power(state, 1); /* power up */
b63b36fa
FR		 951 if (lg_chkerr(ret))
952 goto fail;
953
954 if (fe->ops.tuner_ops.set_params) {
955 ret = fe->ops.tuner_ops.set_params(fe);
956 if (fe->ops.i2c_gate_ctrl)
957 fe->ops.i2c_gate_ctrl(fe, 0);
8e8cd34e
MIK		 958#if 0
959 if (lg_chkerr(ret))
960 goto fail;
961 state->current_frequency = p->frequency;
962#endif
b63b36fa
FR		 963 }
964
965 ret = lgdt3306a_set_modulation(state, p);
966 if (lg_chkerr(ret))
967 goto fail;
968
969 ret = lgdt3306a_agc_setup(state, p);
970 if (lg_chkerr(ret))
971 goto fail;
972
973 ret = lgdt3306a_set_if(state, p);
974 if (lg_chkerr(ret))
975 goto fail;
976
977 ret = lgdt3306a_spectral_inversion(state, p,
8e8cd34e 978 state->cfg->spectral_inversion ? 1 : 0);
b63b36fa
FR		 979 if (lg_chkerr(ret))
980 goto fail;
981
982 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
983 if (lg_chkerr(ret))
984 goto fail;
985
986 ret = lgdt3306a_mpeg_mode_polarity(state,
987 state->cfg->tpclk_edge,
988 state->cfg->tpvalid_polarity);
989 if (lg_chkerr(ret))
990 goto fail;
991
8e8cd34e 992 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
b63b36fa
FR		 993 if (lg_chkerr(ret))
994 goto fail;
995
996 ret = lgdt3306a_soft_reset(state);
997 if (lg_chkerr(ret))
998 goto fail;
999
1000#ifdef DBG_DUMP
1001 lgdt3306a_DumpAllRegs(state);
1002#endif
1003 state->current_frequency = p->frequency;
1004fail:
1005 return ret;
1006}
1007
1008static int lgdt3306a_get_frontend(struct dvb_frontend *fe)
1009{
1010 struct lgdt3306a_state *state = fe->demodulator_priv;
1011 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1012
1013 lg_dbg("(%u, %d)\n", state->current_frequency, state->current_modulation);
1014
1015 p->modulation = state->current_modulation;
1016 p->frequency = state->current_frequency;
1017 return 0;
1018}
1019
1020static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1021{
1022#if 1
1023 return DVBFE_ALGO_CUSTOM;
1024#else
1025 return DVBFE_ALGO_HW;
1026#endif
1027}
1028
1029/* ------------------------------------------------------------------------ */
1030static void lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1031{
1032 u8 val;
1033 int ret;
8e8cd34e
MIK		 1034 u8 snrRef, maxPowerMan, nCombDet;
1035 u16 fbDlyCir;
b63b36fa 1036
4937ba94
MCC		 1037 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1038 snrRef = val & 0x3f;
b63b36fa
FR		 1039
1040 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1041
1042 ret = lgdt3306a_read_reg(state, 0x2191, &val);
1043 nCombDet = (val & 0x80) >> 7;
1044
1045 ret = lgdt3306a_read_reg(state, 0x2180, &val);
1046 fbDlyCir = (val & 0x03) << 8;
1047 ret = lgdt3306a_read_reg(state, 0x2181, &val);
1048 fbDlyCir |= val;
1049
1050 lg_dbg("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1051 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1052
8e8cd34e 1053 /* Carrier offset sub loop bandwidth */
b63b36fa 1054 ret = lgdt3306a_read_reg(state, 0x1061, &val);
4937ba94 1055 val &= 0xf8;
b63b36fa 1056 if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
8e8cd34e
MIK		 1057 /* SNR is over 18dB and no ghosting */
1058 val |= 0x00; /* final bandwidth = 0 */
b63b36fa 1059 } else {
8e8cd34e 1060 val |= 0x04; /* final bandwidth = 4 */
b63b36fa
FR		 1061 }
1062 ret = lgdt3306a_write_reg(state, 0x1061, val);
1063
8e8cd34e 1064 /* Adjust Notch Filter */
b63b36fa 1065 ret = lgdt3306a_read_reg(state, 0x0024, &val);
4937ba94 1066 val &= 0x0f;
8e8cd34e 1067 if (nCombDet == 0) { /* Turn on the Notch Filter */
b63b36fa
FR		 1068 val |= 0x50;
1069 }
1070 ret = lgdt3306a_write_reg(state, 0x0024, val);
1071
8e8cd34e 1072 /* VSB Timing Recovery output normalization */
4937ba94
MCC		 1073 ret = lgdt3306a_read_reg(state, 0x103d, &val);
1074 val &= 0xcf;
b63b36fa 1075 val |= 0x20;
4937ba94 1076 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa
FR		 1077}
1078
f883d603 1079static enum lgdt3306a_modulation lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
b63b36fa
FR		 1080{
1081 u8 val = 0;
1082 int ret;
1083
1084 ret = lgdt3306a_read_reg(state, 0x0081, &val);
1085
1086 if (val & 0x80) {
1087 lg_dbg("VSB\n");
8e8cd34e 1088 return LG3306_VSB;
b63b36fa 1089 }
c714efe4 1090 if (val & 0x08) {
4937ba94 1091 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
b63b36fa
FR		 1092 val = val >> 2;
1093 if (val & 0x01) {
1094 lg_dbg("QAM256\n");
8e8cd34e 1095 return LG3306_QAM256;
b63b36fa
FR		 1096 } else {
1097 lg_dbg("QAM64\n");
8e8cd34e 1098 return LG3306_QAM64;
b63b36fa
FR		 1099 }
1100 }
1101 lg_warn("UNKNOWN\n");
8e8cd34e 1102 return LG3306_UNKNOWN_MODE;
b63b36fa
FR		 1103}
1104
f883d603
MIK		 1105static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1106 enum lgdt3306a_lock_check whatLock)
b63b36fa
FR		 1107{
1108 u8 val = 0;
1109 int ret;
f883d603
MIK		 1110 enum lgdt3306a_modulation modeOper;
1111 enum lgdt3306a_lock_status lockStatus;
b63b36fa
FR		 1112
1113 modeOper = LG3306_UNKNOWN_MODE;
1114
8e8cd34e
MIK		 1115 switch (whatLock) {
1116 case LG3306_SYNC_LOCK:
1117 {
4937ba94 1118 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
8e8cd34e
MIK		 1119
1120 if ((val & 0x80) == 0x80)
1121 lockStatus = LG3306_LOCK;
1122 else
1123 lockStatus = LG3306_UNLOCK;
1124
1125 lg_dbg("SYNC_LOCK=%x\n", lockStatus);
1126 break;
1127 }
1128 case LG3306_AGC_LOCK:
1129 {
1130 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1131
1132 if ((val & 0x40) == 0x40)
1133 lockStatus = LG3306_LOCK;
1134 else
1135 lockStatus = LG3306_UNLOCK;
1136
1137 lg_dbg("AGC_LOCK=%x\n", lockStatus);
1138 break;
1139 }
1140 case LG3306_TR_LOCK:
b63b36fa 1141 {
8e8cd34e
MIK		 1142 modeOper = lgdt3306a_check_oper_mode(state);
1143 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1144 ret = lgdt3306a_read_reg(state, 0x1094, &val);
b63b36fa
FR		 1145
1146 if ((val & 0x80) == 0x80)
1147 lockStatus = LG3306_LOCK;
1148 else
1149 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1150 } else
1151 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1152
8e8cd34e
MIK		 1153 lg_dbg("TR_LOCK=%x\n", lockStatus);
1154 break;
1155 }
1156 case LG3306_FEC_LOCK:
1157 {
1158 modeOper = lgdt3306a_check_oper_mode(state);
1159 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
b63b36fa
FR		 1160 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1161
8e8cd34e 1162 if ((val & 0x10) == 0x10)
b63b36fa
FR		 1163 lockStatus = LG3306_LOCK;
1164 else
1165 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1166 } else
1167 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1168
8e8cd34e
MIK		 1169 lg_dbg("FEC_LOCK=%x\n", lockStatus);
1170 break;
1171 }
b63b36fa 1172
8e8cd34e
MIK		 1173 default:
1174 lockStatus = LG3306_UNKNOWN_LOCK;
1175 lg_warn("UNKNOWN whatLock=%d\n", whatLock);
1176 break;
b63b36fa
FR		 1177 }
1178
8e8cd34e 1179 return lockStatus;
b63b36fa
FR		 1180}
1181
f883d603 1182static enum lgdt3306a_neverlock_status lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
b63b36fa
FR		 1183{
1184 u8 val = 0;
1185 int ret;
f883d603 1186 enum lgdt3306a_neverlock_status lockStatus;
b63b36fa
FR		 1187
1188 ret = lgdt3306a_read_reg(state, 0x0080, &val);
f883d603 1189 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
b63b36fa
FR		 1190
1191 lg_dbg("NeverLock=%d", lockStatus);
1192
8e8cd34e 1193 return lockStatus;
b63b36fa
FR		 1194}
1195
1196static void lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1197{
1198 u8 val = 0;
1199 int ret;
1200 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1201
8e8cd34e 1202 /* Channel variation */
4937ba94 1203 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
b63b36fa 1204
8e8cd34e 1205 /* SNR of Frame sync */
4937ba94
MCC		 1206 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1207 snrRef = val & 0x3f;
b63b36fa 1208
8e8cd34e 1209 /* Strong Main CIR */
b63b36fa
FR		 1210 ret = lgdt3306a_read_reg(state, 0x2199, &val);
1211 mainStrong = (val & 0x40) >> 6;
1212
1213 ret = lgdt3306a_read_reg(state, 0x0090, &val);
4937ba94 1214 aiccrejStatus = (val & 0xf0) >> 4;
b63b36fa
FR		 1215
1216 lg_dbg("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1217 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1218
8e8cd34e
MIK		 1219#if 0
1220 if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */
1221#endif
1222 if (mainStrong == 0) {
b63b36fa 1223 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94
MCC		 1224 val &= 0x0f;
1225 val |= 0xa0;
b63b36fa
FR		 1226 ret = lgdt3306a_write_reg(state, 0x2135, val);
1227
1228 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 1229 val &= 0x3f;
b63b36fa
FR		 1230 val |= 0x80;
1231 ret = lgdt3306a_write_reg(state, 0x2141, val);
1232
1233 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
8e8cd34e 1234 } else { /* Weak ghost or static channel */
b63b36fa 1235 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94 1236 val &= 0x0f;
b63b36fa
FR		 1237 val |= 0x70;
1238 ret = lgdt3306a_write_reg(state, 0x2135, val);
1239
1240 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 1241 val &= 0x3f;
b63b36fa
FR		 1242 val |= 0x40;
1243 ret = lgdt3306a_write_reg(state, 0x2141, val);
1244
1245 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1246 }
1247
1248}
1249
f883d603 1250static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1251{
f883d603 1252 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1253 int i;
1254
1255 for (i = 0; i < 2; i++) {
1256 msleep(30);
1257
1258 syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK);
1259
1260 if (syncLockStatus == LG3306_LOCK) {
1261 lg_dbg("locked(%d)\n", i);
8e8cd34e 1262 return LG3306_LOCK;
b63b36fa
FR		 1263 }
1264 }
1265 lg_dbg("not locked\n");
8e8cd34e 1266 return LG3306_UNLOCK;
b63b36fa
FR		 1267}
1268
f883d603 1269static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1270{
f883d603 1271 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1272 int i;
1273
1274 for (i = 0; i < 2; i++) {
1275 msleep(30);
1276
1277 FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK);
1278
1279 if (FECLockStatus == LG3306_LOCK) {
1280 lg_dbg("locked(%d)\n", i);
8e8cd34e 1281 return FECLockStatus;
b63b36fa
FR		 1282 }
1283 }
1284 lg_dbg("not locked\n");
8e8cd34e 1285 return FECLockStatus;
b63b36fa
FR		 1286}
1287
f883d603 1288static enum lgdt3306a_neverlock_status lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
b63b36fa 1289{
f883d603 1290 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
b63b36fa
FR		 1291 int i;
1292
8e8cd34e 1293 for (i = 0; i < 5; i++) {
b63b36fa
FR		 1294 msleep(30);
1295
1296 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1297
1298 if (NLLockStatus == LG3306_NL_LOCK) {
1299 lg_dbg("NL_LOCK(%d)\n", i);
8e8cd34e 1300 return NLLockStatus;
b63b36fa
FR		 1301 }
1302 }
1303 lg_dbg("NLLockStatus=%d\n", NLLockStatus);
8e8cd34e 1304 return NLLockStatus;
b63b36fa
FR		 1305}
1306
1307static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1308{
1309 u8 val;
1310 int ret;
1311
4937ba94 1312 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
b63b36fa 1313
8e8cd34e 1314 return val;
b63b36fa
FR		 1315}
1316
1317static u32 log10_x1000(u32 x)
1318{
8e8cd34e
MIK		 1319 static u32 valx_x10[] = { 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100 };
1320 static u32 log10x_x1000[] = { 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 };
1321 static u32 nelems = sizeof(valx_x10)/sizeof(valx_x10[0]);
a132fef8 1322 u32 diff_val, step_val, step_log10;
b63b36fa 1323 u32 log_val = 0;
8e8cd34e 1324 u32 i;
b63b36fa 1325
8e8cd34e
MIK		 1326 if (x <= 0)
1327 return -1000000; /* signal error */
b63b36fa 1328
8e8cd34e
MIK		 1329 if (x < 10) {
1330 while (x < 10) {
1331 x = x * 10;
b63b36fa
FR		 1332 log_val--;
1333 }
8e8cd34e
MIK		 1334 } else if (x == 10) {
1335 return 0; /* log(1)=0 */
b63b36fa 1336 } else {
8e8cd34e
MIK		 1337 while (x >= 100) {
1338 x = x / 10;
b63b36fa
FR		 1339 log_val++;
1340 }
8e8cd34e 1341 }
b63b36fa
FR		 1342 log_val *= 1000;
1343
8e8cd34e
MIK		 1344 if (x == 10) /* was our input an exact multiple of 10 */
1345 return log_val; /* don't need to interpolate */
b63b36fa 1346
8e8cd34e
MIK		 1347 /* find our place on the log curve */
1348 for (i = 1; i < nelems; i++) {
1349 if (valx_x10[i] >= x)
1350 break;
b63b36fa 1351 }
a132fef8
MCC		 1352 if (i == nelems)
1353 return log_val + log10x_x1000[i - 1];
b63b36fa 1354
a132fef8
MCC		 1355 diff_val = x - valx_x10[i-1];
1356 step_val = valx_x10[i] - valx_x10[i - 1];
1357 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1358
1359 /* do a linear interpolation to get in-between values */
1360 return log_val + log10x_x1000[i - 1] +
1361 ((diff_val*step_log10) / step_val);
b63b36fa
FR		 1362}
1363
1364static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1365{
34a5a2f8
MIK		 1366 u32 mse; /* Mean-Square Error */
1367 u32 pwr; /* Constelation power */
b63b36fa
FR		 1368 u32 snr_x100;
1369
4937ba94
MCC		 1370 mse = (read_reg(state, 0x00ec) << 8) |
1371 (read_reg(state, 0x00ed));
1372 pwr = (read_reg(state, 0x00e8) << 8) |
1373 (read_reg(state, 0x00e9));
b63b36fa
FR		 1374
1375 if (mse == 0) /* no signal */
1376 return 0;
1377
8e8cd34e 1378 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
b63b36fa
FR		 1379 lg_dbg("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1380
1381 return snr_x100;
1382}
1383
f883d603 1384static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1385{
8e8cd34e
MIK		 1386 u8 cnt = 0;
1387 u8 packet_error;
1388 u32 snr;
b63b36fa 1389
8e8cd34e 1390 while (1) {
b63b36fa
FR		 1391 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1392 lg_dbg("no sync lock!\n");
8e8cd34e 1393 return LG3306_UNLOCK;
b63b36fa
FR		 1394 } else {
1395 msleep(20);
1396 lgdt3306a_pre_monitoring(state);
1397
1398 packet_error = lgdt3306a_get_packet_error(state);
1399 snr = lgdt3306a_calculate_snr_x100(state);
8e8cd34e
MIK		 1400 lg_dbg("cnt=%d errors=%d snr=%d\n",
1401 cnt, packet_error, snr);
b63b36fa 1402
8e8cd34e 1403 if ((snr < 1500) || (packet_error >= 0xff))
b63b36fa 1404 cnt++;
8e8cd34e
MIK		 1405 else
1406 return LG3306_LOCK;
b63b36fa 1407
8e8cd34e 1408 if (cnt >= 10) {
b63b36fa 1409 lg_dbg("not locked!\n");
8e8cd34e 1410 return LG3306_UNLOCK;
b63b36fa
FR		 1411 }
1412 }
1413 }
8e8cd34e 1414 return LG3306_UNLOCK;
b63b36fa
FR		 1415}
1416
f883d603 1417static enum lgdt3306a_lock_status lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
b63b36fa
FR		 1418{
1419 u8 cnt = 0;
1420 u8 packet_error;
1421 u32 snr;
1422
8e8cd34e
MIK		 1423 while (1) {
1424 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
b63b36fa 1425 lg_dbg("no fec lock!\n");
8e8cd34e 1426 return LG3306_UNLOCK;
b63b36fa
FR		 1427 } else {
1428 msleep(20);
1429
1430 packet_error = lgdt3306a_get_packet_error(state);
1431 snr = lgdt3306a_calculate_snr_x100(state);
8e8cd34e
MIK		 1432 lg_dbg("cnt=%d errors=%d snr=%d\n",
1433 cnt, packet_error, snr);
b63b36fa 1434
8e8cd34e 1435 if ((snr < 1500) || (packet_error >= 0xff))
b63b36fa 1436 cnt++;
8e8cd34e
MIK		 1437 else
1438 return LG3306_LOCK;
b63b36fa 1439
8e8cd34e 1440 if (cnt >= 10) {
b63b36fa 1441 lg_dbg("not locked!\n");
8e8cd34e 1442 return LG3306_UNLOCK;
b63b36fa
FR		 1443 }
1444 }
1445 }
8e8cd34e 1446 return LG3306_UNLOCK;
b63b36fa
FR		 1447}
1448
1449static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status)
1450{
b63b36fa 1451 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1452 u16 strength = 0;
8e8cd34e
MIK		 1453 int ret = 0;
1454
b63b36fa
FR		 1455 if (fe->ops.tuner_ops.get_rf_strength) {
1456 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
8e8cd34e 1457 if (ret == 0) {
b63b36fa
FR		 1458 lg_dbg("strength=%d\n", strength);
1459 } else {
1460 lg_dbg("fe->ops.tuner_ops.get_rf_strength() failed\n");
1461 }
1462 }
1463
1464 *status = 0;
8e8cd34e 1465 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
b63b36fa
FR		 1466 *status |= FE_HAS_SIGNAL;
1467 *status |= FE_HAS_CARRIER;
1468
1469 switch (state->current_modulation) {
1470 case QAM_256:
1471 case QAM_64:
8e8cd34e 1472 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1473 *status |= FE_HAS_VITERBI;
1474 *status |= FE_HAS_SYNC;
1475
1476 *status |= FE_HAS_LOCK;
1477 }
1478 break;
1479 case VSB_8:
8e8cd34e 1480 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1481 *status |= FE_HAS_VITERBI;
1482 *status |= FE_HAS_SYNC;
1483
1484 *status |= FE_HAS_LOCK;
1485
1486 lgdt3306a_monitor_vsb(state);
1487 }
1488 break;
1489 default:
1490 ret = -EINVAL;
1491 }
1492 }
1493 return ret;
1494}
1495
1496
1497static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1498{
1499 struct lgdt3306a_state *state = fe->demodulator_priv;
1500
1501 state->snr = lgdt3306a_calculate_snr_x100(state);
1502 /* report SNR in dB * 10 */
1503 *snr = state->snr/10;
1504
1505 return 0;
1506}
1507
1508static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1509 u16 *strength)
1510{
1511 /*
1512 * Calculate some sort of "strength" from SNR
1513 */
1514 struct lgdt3306a_state *state = fe->demodulator_priv;
34a5a2f8 1515 u16 snr; /* snr_x10 */
b63b36fa 1516 int ret;
8e8cd34e 1517 u32 ref_snr; /* snr*100 */
b63b36fa
FR		 1518 u32 str;
1519
1520 *strength = 0;
1521
1522 switch (state->current_modulation) {
1523 case VSB_8:
8e8cd34e 1524 ref_snr = 1600; /* 16dB */
b63b36fa
FR		 1525 break;
1526 case QAM_64:
8e8cd34e 1527 ref_snr = 2200; /* 22dB */
b63b36fa
FR		 1528 break;
1529 case QAM_256:
8e8cd34e 1530 ref_snr = 2800; /* 28dB */
b63b36fa
FR		 1531 break;
1532 default:
1533 return -EINVAL;
1534 }
1535
1536 ret = fe->ops.read_snr(fe, &snr);
1537 if (lg_chkerr(ret))
1538 goto fail;
1539
8e8cd34e 1540 if (state->snr <= (ref_snr - 100))
b63b36fa 1541 str = 0;
8e8cd34e
MIK		 1542 else if (state->snr <= ref_snr)
1543 str = (0xffff * 65) / 100; /* 65% */
b63b36fa
FR		 1544 else {
1545 str = state->snr - ref_snr;
1546 str /= 50;
8e8cd34e
MIK		 1547 str += 78; /* 78%-100% */
1548 if (str > 100)
b63b36fa
FR		 1549 str = 100;
1550 str = (0xffff * str) / 100;
1551 }
1552 *strength = (u16)str;
1553 lg_dbg("strength=%u\n", *strength);
1554
1555fail:
1556 return ret;
1557}
1558
1559/* ------------------------------------------------------------------------ */
1560
1561static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1562{
1563 struct lgdt3306a_state *state = fe->demodulator_priv;
1564 u32 tmp;
1565
1566 *ber = 0;
1567#if 1
8e8cd34e
MIK		 1568 /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1569 * what is the scale of the value?? */
4937ba94
MCC		 1570 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1571 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1572 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1573 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
b63b36fa
FR		 1574 *ber = tmp;
1575 lg_dbg("ber=%u\n", tmp);
1576#endif
1577 return 0;
1578}
1579
1580static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1581{
1582 struct lgdt3306a_state *state = fe->demodulator_priv;
1583
8e8cd34e 1584 *ucblocks = 0;
b63b36fa 1585#if 1
8e8cd34e
MIK		 1586 /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1587 * what happens when value wraps? */
4937ba94 1588 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
b63b36fa
FR		 1589 lg_dbg("ucblocks=%u\n", *ucblocks);
1590#endif
1591
1592 return 0;
1593}
1594
1595static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1596{
1597 int ret = 0;
1598 struct lgdt3306a_state *state = fe->demodulator_priv;
1599
1600 lg_dbg("re_tune=%u\n", re_tune);
1601
1602 if (re_tune) {
8e8cd34e 1603 state->current_frequency = -1; /* force re-tune */
ae21e447
MIK		 1604 ret = lgdt3306a_set_parameters(fe);
1605 if (ret != 0)
b63b36fa 1606 return ret;
b63b36fa
FR		 1607 }
1608 *delay = 125;
1609 ret = lgdt3306a_read_status(fe, status);
1610
1611 return ret;
1612}
1613
1614static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
8e8cd34e
MIK		 1615 struct dvb_frontend_tune_settings
1616 *fe_tune_settings)
b63b36fa
FR		 1617{
1618 fe_tune_settings->min_delay_ms = 100;
1619 lg_dbg("\n");
1620 return 0;
1621}
1622
1623static int lgdt3306a_search(struct dvb_frontend *fe)
1624{
1625 fe_status_t status = 0;
1626 int i, ret;
1627
1628 /* set frontend */
1629 ret = lgdt3306a_set_parameters(fe);
1630 if (ret)
1631 goto error;
1632
1633 /* wait frontend lock */
1634 for (i = 20; i > 0; i--) {
1635 lg_dbg(": loop=%d\n", i);
1636 msleep(50);
1637 ret = lgdt3306a_read_status(fe, &status);
1638 if (ret)
1639 goto error;
1640
1641 if (status & FE_HAS_LOCK)
1642 break;
1643 }
1644
1645 /* check if we have a valid signal */
8e8cd34e 1646 if (status & FE_HAS_LOCK)
b63b36fa 1647 return DVBFE_ALGO_SEARCH_SUCCESS;
8e8cd34e 1648 else
b63b36fa 1649 return DVBFE_ALGO_SEARCH_AGAIN;
b63b36fa
FR		 1650
1651error:
1652 lg_dbg("failed (%d)\n", ret);
1653 return DVBFE_ALGO_SEARCH_ERROR;
1654}
1655
1656static void lgdt3306a_release(struct dvb_frontend *fe)
1657{
1658 struct lgdt3306a_state *state = fe->demodulator_priv;
8e8cd34e 1659
b63b36fa
FR		 1660 lg_dbg("\n");
1661 kfree(state);
1662}
1663
1664static struct dvb_frontend_ops lgdt3306a_ops;
1665
1666struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
c43e6512 1667 struct i2c_adapter *i2c_adap)
b63b36fa
FR		 1668{
1669 struct lgdt3306a_state *state = NULL;
1670 int ret;
1671 u8 val;
1672
1673 lg_dbg("(%d-%04x)\n",
1674 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1675 config ? config->i2c_addr : 0);
1676
1677 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1678 if (state == NULL)
1679 goto fail;
1680
1681 state->cfg = config;
1682 state->i2c_adap = i2c_adap;
1683
1684 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1685 sizeof(struct dvb_frontend_ops));
1686 state->frontend.demodulator_priv = state;
1687
1688 /* verify that we're talking to a lg3306a */
8e8cd34e
MIK		 1689 /* FGR - NOTE - there is no obvious ChipId to check; we check
1690 * some "known" bits after reset, but it's still just a guess */
b63b36fa
FR		 1691 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1692 if (lg_chkerr(ret))
1693 goto fail;
8e8cd34e 1694 if ((val & 0x74) != 0x74) {
b63b36fa 1695 lg_warn("expected 0x74, got 0x%x\n", (val & 0x74));
8e8cd34e
MIK		 1696#if 0
1697 goto fail; /* BUGBUG - re-enable when we know this is right */
1698#endif
b63b36fa
FR		 1699 }
1700 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1701 if (lg_chkerr(ret))
1702 goto fail;
4937ba94
MCC		 1703 if ((val & 0xf6) != 0xc6) {
1704 lg_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
8e8cd34e
MIK		 1705#if 0
1706 goto fail; /* BUGBUG - re-enable when we know this is right */
1707#endif
b63b36fa
FR		 1708 }
1709 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1710 if (lg_chkerr(ret))
1711 goto fail;
8e8cd34e 1712 if ((val & 0x73) != 0x03) {
b63b36fa 1713 lg_warn("expected 0x03, got 0x%x\n", (val & 0x73));
8e8cd34e
MIK		 1714#if 0
1715 goto fail; /* BUGBUG - re-enable when we know this is right */
1716#endif
b63b36fa
FR		 1717 }
1718
1719 state->current_frequency = -1;
1720 state->current_modulation = -1;
1721
1722 lgdt3306a_sleep(state);
1723
1724 return &state->frontend;
1725
1726fail:
1727 lg_warn("unable to detect LGDT3306A hardware\n");
1728 kfree(state);
1729 return NULL;
1730}
ebd9175e 1731EXPORT_SYMBOL(lgdt3306a_attach);
b63b36fa
FR		 1732
1733#ifdef DBG_DUMP
1734
1735static const short regtab[] = {
cb4671c8
MIK		 1736 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1737 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1738 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1739 0x0003, /* AGCRFOUT */
1740 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1741 0x0005, /* PLLINDIVSE */
1742 0x0006, /* PLLCTRL[7:0] 11100001 */
1743 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1744 0x0008, /* STDOPMODE[7:0] 10000000 */
1745 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
4937ba94
MCC		 1746 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1747 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1748 0x000d, /* x SAMPLING4 */
1749 0x000e, /* SAMFREQ[15:8] 00000000 */
1750 0x000f, /* SAMFREQ[7:0] 00000000 */
cb4671c8
MIK		 1751 0x0010, /* IFFREQ[15:8] 01100000 */
1752 0x0011, /* IFFREQ[7:0] 00000000 */
1753 0x0012, /* AGCEN AGCREFMO */
1754 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1755 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1756 0x0015, /* AGCREF[15:8] 00001010 */
1757 0x0016, /* AGCREF[7:0] 11100100 */
1758 0x0017, /* AGCDELAY[7:0] 00100000 */
1759 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1760 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
4937ba94
MCC		 1761 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1762 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1763 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1764 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
cb4671c8
MIK		 1765 0x0020, /* AICCDETTH[15:8] 01111100 */
1766 0x0021, /* AICCDETTH[7:0] 00000000 */
1767 0x0022, /* AICCOFFTH[15:8] 00000101 */
1768 0x0023, /* AICCOFFTH[7:0] 11100000 */
1769 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1770 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1771 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1772 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1773 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1774 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
4937ba94
MCC		 1775 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1776 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1777 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1778 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1779 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1780 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
cb4671c8
MIK		 1781 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1782 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1783 0x0032, /* DAGC1STEN DAGC1STER */
1784 0x0033, /* DAGC1STREF[15:8] 00001010 */
1785 0x0034, /* DAGC1STREF[7:0] 11100100 */
1786 0x0035, /* DAGC2NDE */
1787 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1788 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1789 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
4937ba94 1790 0x003d, /* 1'b1 SAMGEARS */
cb4671c8
MIK		 1791 0x0040, /* SAMLFGMA */
1792 0x0041, /* SAMLFBWM */
1793 0x0044, /* 1'b1 CRGEARSHE */
1794 0x0045, /* CRLFGMAN */
1795 0x0046, /* CFLFBWMA */
1796 0x0047, /* CRLFGMAN */
1797 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1798 0x0049, /* CRLFBWMA */
4937ba94 1799 0x004a, /* CRLFBWMA */
cb4671c8
MIK		 1800 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1801 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1802 0x0071, /* TPSENB TPSSOPBITE */
1803 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1804 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1805 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1806 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1807 0x0078, /* NBERPOLY[31:24] 00000000 */
1808 0x0079, /* NBERPOLY[23:16] 00000000 */
4937ba94
MCC		 1809 0x007a, /* NBERPOLY[15:8] 00000000 */
1810 0x007b, /* NBERPOLY[7:0] 00000000 */
1811 0x007c, /* NBERPED[31:24] 00000000 */
1812 0x007d, /* NBERPED[23:16] 00000000 */
1813 0x007e, /* NBERPED[15:8] 00000000 */
1814 0x007f, /* NBERPED[7:0] 00000000 */
cb4671c8
MIK		 1815 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1816 0x0085, /* SPECINVST */
1817 0x0088, /* SYSLOCKTIME[15:8] */
1818 0x0089, /* SYSLOCKTIME[7:0] */
4937ba94
MCC		 1819 0x008c, /* FECLOCKTIME[15:8] */
1820 0x008d, /* FECLOCKTIME[7:0] */
1821 0x008e, /* AGCACCOUT[15:8] */
1822 0x008f, /* AGCACCOUT[7:0] */
cb4671c8
MIK		 1823 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1824 0x0091, /* AICCVSYNC */
4937ba94
MCC		 1825 0x009c, /* CARRFREQOFFSET[15:8] */
1826 0x009d, /* CARRFREQOFFSET[7:0] */
1827 0x00a1, /* SAMFREQOFFSET[23:16] */
1828 0x00a2, /* SAMFREQOFFSET[15:8] */
1829 0x00a3, /* SAMFREQOFFSET[7:0] */
1830 0x00a6, /* SYNCLOCK SYNCLOCKH */
6da7ac98 1831#if 0 /* covered elsewhere */
4937ba94
MCC		 1832 0x00e8, /* CONSTPWR[15:8] */
1833 0x00e9, /* CONSTPWR[7:0] */
1834 0x00ea, /* BMSE[15:8] */
1835 0x00eb, /* BMSE[7:0] */
1836 0x00ec, /* MSE[15:8] */
1837 0x00ed, /* MSE[7:0] */
1838 0x00ee, /* CONSTI[7:0] */
1839 0x00ef, /* CONSTQ[7:0] */
b63b36fa 1840#endif
4937ba94
MCC		 1841 0x00f4, /* TPIFTPERRCNT[7:0] */
1842 0x00f5, /* TPCORREC */
1843 0x00f6, /* VBBER[15:8] */
1844 0x00f7, /* VBBER[7:0] */
1845 0x00f8, /* VABER[15:8] */
1846 0x00f9, /* VABER[7:0] */
1847 0x00fa, /* TPERRCNT[7:0] */
1848 0x00fb, /* NBERLOCK x x x x x x x */
1849 0x00fc, /* NBERVALUE[31:24] */
1850 0x00fd, /* NBERVALUE[23:16] */
1851 0x00fe, /* NBERVALUE[15:8] */
1852 0x00ff, /* NBERVALUE[7:0] */
cb4671c8
MIK		 1853 0x1000, /* 1'b0 WODAGCOU */
1854 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1855 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
4937ba94
MCC		 1856 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1857 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
cb4671c8 1858 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
4937ba94
MCC		 1859 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1860 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1861 0x103f, /* SAMZTEDSE */
1862 0x105d, /* EQSTATUSE */
1863 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
cb4671c8
MIK		 1864 0x1060, /* 1'b1 EQSTATUSE */
1865 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1866 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1867 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1868 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
4937ba94
MCC		 1869 0x106e, /* x x x x x CREPHNEN_ */
1870 0x106f, /* CREPHNTH_V[7:0] 00010101 */
cb4671c8
MIK		 1871 0x1072, /* CRSWEEPN */
1872 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1873 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1874 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1875 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
4937ba94
MCC		 1876 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1877 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
6da7ac98 1878#if 0 /* SMART_ANT */
4937ba94
MCC		 1879 0x1f00, /* MODEDETE */
1880 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1881 0x1f03, /* NUMOFANT[7:0] 10000000 */
1882 0x1f04, /* x SELMASK[6:0] x0000000 */
1883 0x1f05, /* x SETMASK[6:0] x0000000 */
1884 0x1f06, /* x TXDATA[6:0] x0000000 */
1885 0x1f07, /* x CHNUMBER[6:0] x0000000 */
1886 0x1f09, /* AGCTIME[23:16] 10011000 */
1887 0x1f0a, /* AGCTIME[15:8] 10010110 */
1888 0x1f0b, /* AGCTIME[7:0] 10000000 */
1889 0x1f0c, /* ANTTIME[31:24] 00000000 */
1890 0x1f0d, /* ANTTIME[23:16] 00000011 */
1891 0x1f0e, /* ANTTIME[15:8] 10010000 */
1892 0x1f0f, /* ANTTIME[7:0] 10010000 */
1893 0x1f11, /* SYNCTIME[23:16] 10011000 */
1894 0x1f12, /* SYNCTIME[15:8] 10010110 */
1895 0x1f13, /* SYNCTIME[7:0] 10000000 */
1896 0x1f14, /* SNRTIME[31:24] 00000001 */
1897 0x1f15, /* SNRTIME[23:16] 01111101 */
1898 0x1f16, /* SNRTIME[15:8] 01111000 */
1899 0x1f17, /* SNRTIME[7:0] 01000000 */
1900 0x1f19, /* FECTIME[23:16] 00000000 */
1901 0x1f1a, /* FECTIME[15:8] 01110010 */
1902 0x1f1b, /* FECTIME[7:0] 01110000 */
1903 0x1f1d, /* FECTHD[7:0] 00000011 */
1904 0x1f1f, /* SNRTHD[23:16] 00001000 */
1905 0x1f20, /* SNRTHD[15:8] 01111111 */
1906 0x1f21, /* SNRTHD[7:0] 10000101 */
1907 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
1908 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
1909 0x1f82, /* x x x SCANOPCD[4:0] */
1910 0x1f83, /* x x x x MAINOPCD[3:0] */
1911 0x1f84, /* x x RXDATA[13:8] */
1912 0x1f85, /* RXDATA[7:0] */
1913 0x1f86, /* x x SDTDATA[13:8] */
1914 0x1f87, /* SDTDATA[7:0] */
1915 0x1f89, /* ANTSNR[23:16] */
1916 0x1f8a, /* ANTSNR[15:8] */
1917 0x1f8b, /* ANTSNR[7:0] */
1918 0x1f8c, /* x x x x ANTFEC[13:8] */
1919 0x1f8d, /* ANTFEC[7:0] */
1920 0x1f8e, /* MAXCNT[7:0] */
1921 0x1f8f, /* SCANCNT[7:0] */
1922 0x1f91, /* MAXPW[23:16] */
1923 0x1f92, /* MAXPW[15:8] */
1924 0x1f93, /* MAXPW[7:0] */
1925 0x1f95, /* CURPWMSE[23:16] */
1926 0x1f96, /* CURPWMSE[15:8] */
1927 0x1f97, /* CURPWMSE[7:0] */
6da7ac98 1928#endif /* SMART_ANT */
4937ba94
MCC		 1929 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
1930 0x212a, /* EQAUTOST */
cb4671c8 1931 0x2122, /* CHFAST[7:0] 01100000 */
4937ba94
MCC		 1932 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
1933 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
1934 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
cb4671c8
MIK		 1935 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
1936 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
1937 0x2162, /* AICCCTRLE */
1938 0x2173, /* PHNCNFCNT[7:0] 00000100 */
1939 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
4937ba94
MCC		 1940 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
1941 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
1942 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
cb4671c8
MIK		 1943 0x2180, /* x x x x x x FBDLYCIR[9:8] */
1944 0x2181, /* FBDLYCIR[7:0] */
1945 0x2185, /* MAXPWRMAIN[7:0] */
1946 0x2191, /* NCOMBDET x x x x x x x */
1947 0x2199, /* x MAINSTRON */
4937ba94
MCC		 1948 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
1949 0x21a1, /* x x SNRREF[5:0] */
cb4671c8
MIK		 1950 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
1951 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
1952 0x2847, /* ENNOSIGDE */
1953 0x2849, /* 1'b1 1'b1 NOUSENOSI */
4937ba94 1954 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
cb4671c8
MIK		 1955 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
1956 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
1957 0x3031, /* FRAMELOC */
1958 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
4937ba94
MCC		 1959 0x30a9, /* VDLOCK_Q FRAMELOCK */
1960 0x30aa, /* MPEGLOCK */
b63b36fa
FR		 1961};
1962
34a5a2f8 1963#define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
b63b36fa
FR		 1964static u8 regval1[numDumpRegs] = {0, };
1965static u8 regval2[numDumpRegs] = {0, };
1966
1967static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
1968{
1969 memset(regval2, 0xff, sizeof(regval2));
1970 lgdt3306a_DumpRegs(state);
1971}
1972
1973static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
1974{
1975 int i;
1976 int sav_debug = debug;
8e8cd34e 1977
b63b36fa
FR		 1978 if ((debug & DBG_DUMP) == 0)
1979 return;
831a9112 1980 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
b63b36fa
FR		 1981
1982 lg_info("\n");
1983
8e8cd34e 1984 for (i = 0; i < numDumpRegs; i++) {
b63b36fa 1985 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
8e8cd34e
MIK		 1986 if (regval1[i] != regval2[i]) {
1987 lg_info(" %04X = %02X\n", regtab[i], regval1[i]);
1988 regval2[i] = regval1[i];
b63b36fa
FR		 1989 }
1990 }
1991 debug = sav_debug;
1992}
8e8cd34e 1993#endif /* DBG_DUMP */
b63b36fa
FR		 1994
1995
1996
b63b36fa
FR		 1997static struct dvb_frontend_ops lgdt3306a_ops = {
1998 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1999 .info = {
2000 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
8e8cd34e
MIK		 2001#if 0
2002 .type = FE_ATSC,
2003#endif
b63b36fa 2004 .frequency_min = 54000000,
8e8cd34e 2005 .frequency_max = 858000000,
b63b36fa
FR		 2006 .frequency_stepsize = 62500,
2007 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2008 },
2009 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2010 .init = lgdt3306a_init,
2011 .sleep = lgdt3306a_fe_sleep,
2012 /* if this is set, it overrides the default swzigzag */
2013 .tune = lgdt3306a_tune,
2014 .set_frontend = lgdt3306a_set_parameters,
2015 .get_frontend = lgdt3306a_get_frontend,
2016 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2017 .get_tune_settings = lgdt3306a_get_tune_settings,
2018 .read_status = lgdt3306a_read_status,
2019 .read_ber = lgdt3306a_read_ber,
2020 .read_signal_strength = lgdt3306a_read_signal_strength,
2021 .read_snr = lgdt3306a_read_snr,
2022 .read_ucblocks = lgdt3306a_read_ucblocks,
2023 .release = lgdt3306a_release,
2024 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2025 .search = lgdt3306a_search,
2026};
2027
2028MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2029MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2030MODULE_LICENSE("GPL");
2031MODULE_VERSION("0.2");
2032
2033/*
2034 * Local variables:
2035 * c-basic-offset: 8
2036 * End:
2037 */
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