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Commit | Line | Data |
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d8667cbb | 1 | /* |
1963c907 | 2 | * Support for LGDT3302 and LGDT3303 - VSB/QAM |
d8667cbb MM |
3 | * |
4 | * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net> | |
5 | * | |
d8667cbb MM |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | ||
22 | /* | |
23 | * NOTES ABOUT THIS DRIVER | |
24 | * | |
1963c907 MK |
25 | * This Linux driver supports: |
26 | * DViCO FusionHDTV 3 Gold-Q | |
27 | * DViCO FusionHDTV 3 Gold-T | |
28 | * DViCO FusionHDTV 5 Gold | |
3cff00d9 | 29 | * DViCO FusionHDTV 5 Lite |
d8e6acf2 | 30 | * DViCO FusionHDTV 5 USB Gold |
c0b11b91 | 31 | * Air2PC/AirStar 2 ATSC 3rd generation (HD5000) |
20fe4f65 | 32 | * pcHDTV HD5500 |
d8667cbb | 33 | * |
d8667cbb MM |
34 | */ |
35 | ||
d8667cbb MM |
36 | #include <linux/kernel.h> |
37 | #include <linux/module.h> | |
d8667cbb MM |
38 | #include <linux/init.h> |
39 | #include <linux/delay.h> | |
4e57b681 TS |
40 | #include <linux/string.h> |
41 | #include <linux/slab.h> | |
d8667cbb MM |
42 | #include <asm/byteorder.h> |
43 | ||
44 | #include "dvb_frontend.h" | |
19be685a | 45 | #include "dvb_math.h" |
6ddcc919 MK |
46 | #include "lgdt330x_priv.h" |
47 | #include "lgdt330x.h" | |
d8667cbb | 48 | |
19be685a TP |
49 | /* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */ |
50 | /* #define USE_EQMSE */ | |
51 | ||
ff699e6b | 52 | static int debug; |
d8667cbb | 53 | module_param(debug, int, 0644); |
6ddcc919 | 54 | MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off)."); |
d8667cbb MM |
55 | #define dprintk(args...) \ |
56 | do { \ | |
6ddcc919 | 57 | if (debug) printk(KERN_DEBUG "lgdt330x: " args); \ |
d8667cbb MM |
58 | } while (0) |
59 | ||
6ddcc919 | 60 | struct lgdt330x_state |
d8667cbb MM |
61 | { |
62 | struct i2c_adapter* i2c; | |
d8667cbb MM |
63 | |
64 | /* Configuration settings */ | |
6ddcc919 | 65 | const struct lgdt330x_config* config; |
d8667cbb MM |
66 | |
67 | struct dvb_frontend frontend; | |
68 | ||
69 | /* Demodulator private data */ | |
70 | fe_modulation_t current_modulation; | |
19be685a | 71 | u32 snr; /* Result of last SNR calculation */ |
d8667cbb MM |
72 | |
73 | /* Tuner private data */ | |
74 | u32 current_frequency; | |
75 | }; | |
76 | ||
1963c907 | 77 | static int i2c_write_demod_bytes (struct lgdt330x_state* state, |
dc9ca2af MK |
78 | u8 *buf, /* data bytes to send */ |
79 | int len /* number of bytes to send */ ) | |
d8667cbb | 80 | { |
b6aef071 | 81 | struct i2c_msg msg = |
1963c907 MK |
82 | { .addr = state->config->demod_address, |
83 | .flags = 0, | |
84 | .buf = buf, | |
85 | .len = 2 }; | |
b6aef071 | 86 | int i; |
1963c907 | 87 | int err; |
d8667cbb | 88 | |
1963c907 | 89 | for (i=0; i<len-1; i+=2){ |
d8667cbb | 90 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
271ddbf7 | 91 | printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __func__, msg.buf[0], msg.buf[1], err); |
58ba006b MK |
92 | if (err < 0) |
93 | return err; | |
94 | else | |
95 | return -EREMOTEIO; | |
d8667cbb | 96 | } |
1963c907 | 97 | msg.buf += 2; |
d8667cbb MM |
98 | } |
99 | return 0; | |
100 | } | |
101 | ||
102 | /* | |
103 | * This routine writes the register (reg) to the demod bus | |
104 | * then reads the data returned for (len) bytes. | |
105 | */ | |
106 | ||
34817174 XW |
107 | static int i2c_read_demod_bytes(struct lgdt330x_state *state, |
108 | enum I2C_REG reg, u8 *buf, int len) | |
d8667cbb MM |
109 | { |
110 | u8 wr [] = { reg }; | |
111 | struct i2c_msg msg [] = { | |
112 | { .addr = state->config->demod_address, | |
113 | .flags = 0, .buf = wr, .len = 1 }, | |
114 | { .addr = state->config->demod_address, | |
115 | .flags = I2C_M_RD, .buf = buf, .len = len }, | |
116 | }; | |
117 | int ret; | |
118 | ret = i2c_transfer(state->i2c, msg, 2); | |
119 | if (ret != 2) { | |
271ddbf7 | 120 | printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __func__, state->config->demod_address, reg, ret); |
34817174 XW |
121 | if (ret >= 0) |
122 | ret = -EIO; | |
d8667cbb MM |
123 | } else { |
124 | ret = 0; | |
125 | } | |
126 | return ret; | |
127 | } | |
128 | ||
129 | /* Software reset */ | |
1963c907 | 130 | static int lgdt3302_SwReset(struct lgdt330x_state* state) |
d8667cbb MM |
131 | { |
132 | u8 ret; | |
133 | u8 reset[] = { | |
134 | IRQ_MASK, | |
135 | 0x00 /* bit 6 is active low software reset | |
136 | * bits 5-0 are 1 to mask interrupts */ | |
137 | }; | |
138 | ||
1963c907 | 139 | ret = i2c_write_demod_bytes(state, |
dc9ca2af | 140 | reset, sizeof(reset)); |
d8667cbb | 141 | if (ret == 0) { |
1963c907 MK |
142 | |
143 | /* force reset high (inactive) and unmask interrupts */ | |
144 | reset[1] = 0x7f; | |
145 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 146 | reset, sizeof(reset)); |
d8667cbb | 147 | } |
d8667cbb MM |
148 | return ret; |
149 | } | |
150 | ||
1963c907 MK |
151 | static int lgdt3303_SwReset(struct lgdt330x_state* state) |
152 | { | |
153 | u8 ret; | |
154 | u8 reset[] = { | |
155 | 0x02, | |
156 | 0x00 /* bit 0 is active low software reset */ | |
157 | }; | |
158 | ||
159 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 160 | reset, sizeof(reset)); |
1963c907 MK |
161 | if (ret == 0) { |
162 | ||
163 | /* force reset high (inactive) */ | |
164 | reset[1] = 0x01; | |
165 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 166 | reset, sizeof(reset)); |
1963c907 MK |
167 | } |
168 | return ret; | |
169 | } | |
170 | ||
171 | static int lgdt330x_SwReset(struct lgdt330x_state* state) | |
172 | { | |
173 | switch (state->config->demod_chip) { | |
174 | case LGDT3302: | |
175 | return lgdt3302_SwReset(state); | |
176 | case LGDT3303: | |
177 | return lgdt3303_SwReset(state); | |
178 | default: | |
179 | return -ENODEV; | |
180 | } | |
181 | } | |
182 | ||
6ddcc919 | 183 | static int lgdt330x_init(struct dvb_frontend* fe) |
d8667cbb MM |
184 | { |
185 | /* Hardware reset is done using gpio[0] of cx23880x chip. | |
186 | * I'd like to do it here, but don't know how to find chip address. | |
187 | * cx88-cards.c arranges for the reset bit to be inactive (high). | |
188 | * Maybe there needs to be a callable function in cx88-core or | |
189 | * the caller of this function needs to do it. */ | |
190 | ||
1963c907 MK |
191 | /* |
192 | * Array of byte pairs <address, value> | |
193 | * to initialize each different chip | |
194 | */ | |
195 | static u8 lgdt3302_init_data[] = { | |
196 | /* Use 50MHz parameter values from spec sheet since xtal is 50 */ | |
197 | /* Change the value of NCOCTFV[25:0] of carrier | |
198 | recovery center frequency register */ | |
199 | VSB_CARRIER_FREQ0, 0x00, | |
200 | VSB_CARRIER_FREQ1, 0x87, | |
201 | VSB_CARRIER_FREQ2, 0x8e, | |
202 | VSB_CARRIER_FREQ3, 0x01, | |
203 | /* Change the TPCLK pin polarity | |
204 | data is valid on falling clock */ | |
205 | DEMUX_CONTROL, 0xfb, | |
206 | /* Change the value of IFBW[11:0] of | |
207 | AGC IF/RF loop filter bandwidth register */ | |
208 | AGC_RF_BANDWIDTH0, 0x40, | |
209 | AGC_RF_BANDWIDTH1, 0x93, | |
210 | AGC_RF_BANDWIDTH2, 0x00, | |
211 | /* Change the value of bit 6, 'nINAGCBY' and | |
212 | 'NSSEL[1:0] of ACG function control register 2 */ | |
213 | AGC_FUNC_CTRL2, 0xc6, | |
214 | /* Change the value of bit 6 'RFFIX' | |
215 | of AGC function control register 3 */ | |
216 | AGC_FUNC_CTRL3, 0x40, | |
217 | /* Set the value of 'INLVTHD' register 0x2a/0x2c | |
218 | to 0x7fe */ | |
219 | AGC_DELAY0, 0x07, | |
220 | AGC_DELAY2, 0xfe, | |
221 | /* Change the value of IAGCBW[15:8] | |
9aaeded7 | 222 | of inner AGC loop filter bandwidth */ |
1963c907 MK |
223 | AGC_LOOP_BANDWIDTH0, 0x08, |
224 | AGC_LOOP_BANDWIDTH1, 0x9a | |
225 | }; | |
226 | ||
227 | static u8 lgdt3303_init_data[] = { | |
228 | 0x4c, 0x14 | |
229 | }; | |
230 | ||
c0f4c0ad | 231 | static u8 flip_1_lgdt3303_init_data[] = { |
c0b11b91 MK |
232 | 0x4c, 0x14, |
233 | 0x87, 0xf3 | |
234 | }; | |
235 | ||
c0f4c0ad MK |
236 | static u8 flip_2_lgdt3303_init_data[] = { |
237 | 0x4c, 0x14, | |
238 | 0x87, 0xda | |
239 | }; | |
240 | ||
1963c907 MK |
241 | struct lgdt330x_state* state = fe->demodulator_priv; |
242 | char *chip_name; | |
243 | int err; | |
244 | ||
245 | switch (state->config->demod_chip) { | |
246 | case LGDT3302: | |
247 | chip_name = "LGDT3302"; | |
248 | err = i2c_write_demod_bytes(state, lgdt3302_init_data, | |
dc9ca2af MK |
249 | sizeof(lgdt3302_init_data)); |
250 | break; | |
1963c907 MK |
251 | case LGDT3303: |
252 | chip_name = "LGDT3303"; | |
c0f4c0ad MK |
253 | switch (state->config->clock_polarity_flip) { |
254 | case 2: | |
255 | err = i2c_write_demod_bytes(state, | |
256 | flip_2_lgdt3303_init_data, | |
257 | sizeof(flip_2_lgdt3303_init_data)); | |
258 | break; | |
259 | case 1: | |
260 | err = i2c_write_demod_bytes(state, | |
261 | flip_1_lgdt3303_init_data, | |
262 | sizeof(flip_1_lgdt3303_init_data)); | |
263 | break; | |
264 | case 0: | |
265 | default: | |
c0b11b91 MK |
266 | err = i2c_write_demod_bytes(state, lgdt3303_init_data, |
267 | sizeof(lgdt3303_init_data)); | |
268 | } | |
dc9ca2af | 269 | break; |
1963c907 MK |
270 | default: |
271 | chip_name = "undefined"; | |
272 | printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n"); | |
273 | err = -ENODEV; | |
274 | } | |
271ddbf7 | 275 | dprintk("%s entered as %s\n", __func__, chip_name); |
1963c907 MK |
276 | if (err < 0) |
277 | return err; | |
278 | return lgdt330x_SwReset(state); | |
d8667cbb MM |
279 | } |
280 | ||
6ddcc919 | 281 | static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber) |
d8667cbb | 282 | { |
1963c907 | 283 | *ber = 0; /* Not supplied by the demod chips */ |
d8667cbb MM |
284 | return 0; |
285 | } | |
286 | ||
6ddcc919 | 287 | static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
d8667cbb | 288 | { |
1963c907 MK |
289 | struct lgdt330x_state* state = fe->demodulator_priv; |
290 | int err; | |
d8667cbb MM |
291 | u8 buf[2]; |
292 | ||
26110dac MK |
293 | *ucblocks = 0; |
294 | ||
1963c907 MK |
295 | switch (state->config->demod_chip) { |
296 | case LGDT3302: | |
297 | err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1, | |
dc9ca2af MK |
298 | buf, sizeof(buf)); |
299 | break; | |
1963c907 MK |
300 | case LGDT3303: |
301 | err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1, | |
dc9ca2af MK |
302 | buf, sizeof(buf)); |
303 | break; | |
1963c907 MK |
304 | default: |
305 | printk(KERN_WARNING | |
dc9ca2af | 306 | "Only LGDT3302 and LGDT3303 are supported chips.\n"); |
1963c907 MK |
307 | err = -ENODEV; |
308 | } | |
26110dac MK |
309 | if (err < 0) |
310 | return err; | |
d8667cbb MM |
311 | |
312 | *ucblocks = (buf[0] << 8) | buf[1]; | |
313 | return 0; | |
314 | } | |
315 | ||
ca7072dd | 316 | static int lgdt330x_set_parameters(struct dvb_frontend *fe) |
d8667cbb | 317 | { |
ca7072dd | 318 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
1963c907 MK |
319 | /* |
320 | * Array of byte pairs <address, value> | |
321 | * to initialize 8VSB for lgdt3303 chip 50 MHz IF | |
322 | */ | |
323 | static u8 lgdt3303_8vsb_44_data[] = { | |
324 | 0x04, 0x00, | |
325 | 0x0d, 0x40, | |
0b6389ff MK |
326 | 0x0e, 0x87, |
327 | 0x0f, 0x8e, | |
328 | 0x10, 0x01, | |
329 | 0x47, 0x8b }; | |
1963c907 MK |
330 | |
331 | /* | |
332 | * Array of byte pairs <address, value> | |
333 | * to initialize QAM for lgdt3303 chip | |
334 | */ | |
335 | static u8 lgdt3303_qam_data[] = { | |
336 | 0x04, 0x00, | |
337 | 0x0d, 0x00, | |
338 | 0x0e, 0x00, | |
339 | 0x0f, 0x00, | |
340 | 0x10, 0x00, | |
341 | 0x51, 0x63, | |
342 | 0x47, 0x66, | |
343 | 0x48, 0x66, | |
344 | 0x4d, 0x1a, | |
345 | 0x49, 0x08, | |
346 | 0x4a, 0x9b }; | |
347 | ||
348 | struct lgdt330x_state* state = fe->demodulator_priv; | |
d8667cbb | 349 | |
d8667cbb | 350 | static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 }; |
d8667cbb | 351 | |
54828d19 | 352 | int err = 0; |
d8667cbb | 353 | /* Change only if we are actually changing the modulation */ |
ca7072dd MCC |
354 | if (state->current_modulation != p->modulation) { |
355 | switch (p->modulation) { | |
d8667cbb | 356 | case VSB_8: |
271ddbf7 | 357 | dprintk("%s: VSB_8 MODE\n", __func__); |
d8667cbb | 358 | |
1963c907 MK |
359 | /* Select VSB mode */ |
360 | top_ctrl_cfg[1] = 0x03; | |
0ccef6db MK |
361 | |
362 | /* Select ANT connector if supported by card */ | |
363 | if (state->config->pll_rf_set) | |
364 | state->config->pll_rf_set(fe, 1); | |
1963c907 MK |
365 | |
366 | if (state->config->demod_chip == LGDT3303) { | |
367 | err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data, | |
dc9ca2af | 368 | sizeof(lgdt3303_8vsb_44_data)); |
1963c907 | 369 | } |
d8667cbb MM |
370 | break; |
371 | ||
372 | case QAM_64: | |
271ddbf7 | 373 | dprintk("%s: QAM_64 MODE\n", __func__); |
d8667cbb | 374 | |
1963c907 MK |
375 | /* Select QAM_64 mode */ |
376 | top_ctrl_cfg[1] = 0x00; | |
0ccef6db MK |
377 | |
378 | /* Select CABLE connector if supported by card */ | |
379 | if (state->config->pll_rf_set) | |
380 | state->config->pll_rf_set(fe, 0); | |
1963c907 MK |
381 | |
382 | if (state->config->demod_chip == LGDT3303) { | |
383 | err = i2c_write_demod_bytes(state, lgdt3303_qam_data, | |
384 | sizeof(lgdt3303_qam_data)); | |
385 | } | |
d8667cbb MM |
386 | break; |
387 | ||
388 | case QAM_256: | |
271ddbf7 | 389 | dprintk("%s: QAM_256 MODE\n", __func__); |
d8667cbb | 390 | |
1963c907 MK |
391 | /* Select QAM_256 mode */ |
392 | top_ctrl_cfg[1] = 0x01; | |
0ccef6db MK |
393 | |
394 | /* Select CABLE connector if supported by card */ | |
395 | if (state->config->pll_rf_set) | |
396 | state->config->pll_rf_set(fe, 0); | |
1963c907 MK |
397 | |
398 | if (state->config->demod_chip == LGDT3303) { | |
399 | err = i2c_write_demod_bytes(state, lgdt3303_qam_data, | |
400 | sizeof(lgdt3303_qam_data)); | |
401 | } | |
d8667cbb MM |
402 | break; |
403 | default: | |
ca7072dd | 404 | printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, p->modulation); |
d8667cbb MM |
405 | return -1; |
406 | } | |
54828d19 MK |
407 | if (err < 0) |
408 | printk(KERN_WARNING "lgdt330x: %s: error blasting " | |
409 | "bytes to lgdt3303 for modulation type(%d)\n", | |
ca7072dd | 410 | __func__, p->modulation); |
54828d19 | 411 | |
1963c907 MK |
412 | /* |
413 | * select serial or parallel MPEG harware interface | |
414 | * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303 | |
415 | * Parallel: 0x00 | |
416 | */ | |
417 | top_ctrl_cfg[1] |= state->config->serial_mpeg; | |
d8667cbb MM |
418 | |
419 | /* Select the requested mode */ | |
1963c907 | 420 | i2c_write_demod_bytes(state, top_ctrl_cfg, |
dc9ca2af MK |
421 | sizeof(top_ctrl_cfg)); |
422 | if (state->config->set_ts_params) | |
423 | state->config->set_ts_params(fe, 0); | |
ca7072dd | 424 | state->current_modulation = p->modulation; |
d8667cbb | 425 | } |
d8667cbb | 426 | |
dc9ca2af | 427 | /* Tune to the specified frequency */ |
dea74869 | 428 | if (fe->ops.tuner_ops.set_params) { |
14d24d14 | 429 | fe->ops.tuner_ops.set_params(fe); |
dea74869 | 430 | if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); |
02269f37 | 431 | } |
dc9ca2af MK |
432 | |
433 | /* Keep track of the new frequency */ | |
4302c15e MCC |
434 | /* FIXME this is the wrong way to do this... */ |
435 | /* The tuner is shared with the video4linux analog API */ | |
ca7072dd | 436 | state->current_frequency = p->frequency; |
dc9ca2af | 437 | |
6ddcc919 | 438 | lgdt330x_SwReset(state); |
d8667cbb MM |
439 | return 0; |
440 | } | |
441 | ||
7c61d80a | 442 | static int lgdt330x_get_frontend(struct dvb_frontend *fe) |
d8667cbb | 443 | { |
7c61d80a | 444 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
6ddcc919 | 445 | struct lgdt330x_state *state = fe->demodulator_priv; |
ca7072dd | 446 | p->frequency = state->current_frequency; |
d8667cbb MM |
447 | return 0; |
448 | } | |
449 | ||
1963c907 | 450 | static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status) |
d8667cbb | 451 | { |
1963c907 | 452 | struct lgdt330x_state* state = fe->demodulator_priv; |
d8667cbb MM |
453 | u8 buf[3]; |
454 | ||
455 | *status = 0; /* Reset status result */ | |
456 | ||
08d80525 | 457 | /* AGC status register */ |
1963c907 | 458 | i2c_read_demod_bytes(state, AGC_STATUS, buf, 1); |
271ddbf7 | 459 | dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]); |
08d80525 MK |
460 | if ((buf[0] & 0x0c) == 0x8){ |
461 | /* Test signal does not exist flag */ | |
462 | /* as well as the AGC lock flag. */ | |
463 | *status |= FE_HAS_SIGNAL; | |
08d80525 MK |
464 | } |
465 | ||
1963c907 MK |
466 | /* |
467 | * You must set the Mask bits to 1 in the IRQ_MASK in order | |
468 | * to see that status bit in the IRQ_STATUS register. | |
469 | * This is done in SwReset(); | |
470 | */ | |
d8667cbb | 471 | /* signal status */ |
1963c907 | 472 | i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf)); |
271ddbf7 | 473 | dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __func__, buf[0], buf[1], buf[2]); |
08d80525 | 474 | |
d8667cbb MM |
475 | |
476 | /* sync status */ | |
477 | if ((buf[2] & 0x03) == 0x01) { | |
478 | *status |= FE_HAS_SYNC; | |
479 | } | |
480 | ||
481 | /* FEC error status */ | |
482 | if ((buf[2] & 0x0c) == 0x08) { | |
483 | *status |= FE_HAS_LOCK; | |
484 | *status |= FE_HAS_VITERBI; | |
485 | } | |
486 | ||
d8667cbb | 487 | /* Carrier Recovery Lock Status Register */ |
1963c907 | 488 | i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); |
271ddbf7 | 489 | dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]); |
d8667cbb MM |
490 | switch (state->current_modulation) { |
491 | case QAM_256: | |
492 | case QAM_64: | |
af901ca1 | 493 | /* Need to understand why there are 3 lock levels here */ |
d8667cbb MM |
494 | if ((buf[0] & 0x07) == 0x07) |
495 | *status |= FE_HAS_CARRIER; | |
d8667cbb | 496 | break; |
d8667cbb MM |
497 | case VSB_8: |
498 | if ((buf[0] & 0x80) == 0x80) | |
499 | *status |= FE_HAS_CARRIER; | |
d8667cbb | 500 | break; |
d8667cbb | 501 | default: |
271ddbf7 | 502 | printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__); |
d8667cbb | 503 | } |
d8667cbb MM |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
1963c907 MK |
508 | static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status) |
509 | { | |
510 | struct lgdt330x_state* state = fe->demodulator_priv; | |
511 | int err; | |
512 | u8 buf[3]; | |
513 | ||
514 | *status = 0; /* Reset status result */ | |
515 | ||
516 | /* lgdt3303 AGC status register */ | |
517 | err = i2c_read_demod_bytes(state, 0x58, buf, 1); | |
518 | if (err < 0) | |
519 | return err; | |
520 | ||
271ddbf7 | 521 | dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]); |
1963c907 MK |
522 | if ((buf[0] & 0x21) == 0x01){ |
523 | /* Test input signal does not exist flag */ | |
524 | /* as well as the AGC lock flag. */ | |
525 | *status |= FE_HAS_SIGNAL; | |
1963c907 MK |
526 | } |
527 | ||
528 | /* Carrier Recovery Lock Status Register */ | |
529 | i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); | |
271ddbf7 | 530 | dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]); |
1963c907 MK |
531 | switch (state->current_modulation) { |
532 | case QAM_256: | |
533 | case QAM_64: | |
af901ca1 | 534 | /* Need to understand why there are 3 lock levels here */ |
1963c907 MK |
535 | if ((buf[0] & 0x07) == 0x07) |
536 | *status |= FE_HAS_CARRIER; | |
537 | else | |
538 | break; | |
539 | i2c_read_demod_bytes(state, 0x8a, buf, 1); | |
540 | if ((buf[0] & 0x04) == 0x04) | |
541 | *status |= FE_HAS_SYNC; | |
542 | if ((buf[0] & 0x01) == 0x01) | |
543 | *status |= FE_HAS_LOCK; | |
544 | if ((buf[0] & 0x08) == 0x08) | |
545 | *status |= FE_HAS_VITERBI; | |
546 | break; | |
547 | case VSB_8: | |
548 | if ((buf[0] & 0x80) == 0x80) | |
549 | *status |= FE_HAS_CARRIER; | |
550 | else | |
551 | break; | |
552 | i2c_read_demod_bytes(state, 0x38, buf, 1); | |
553 | if ((buf[0] & 0x02) == 0x00) | |
554 | *status |= FE_HAS_SYNC; | |
555 | if ((buf[0] & 0x01) == 0x01) { | |
556 | *status |= FE_HAS_LOCK; | |
557 | *status |= FE_HAS_VITERBI; | |
558 | } | |
559 | break; | |
560 | default: | |
271ddbf7 | 561 | printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__); |
1963c907 MK |
562 | } |
563 | return 0; | |
564 | } | |
565 | ||
19be685a TP |
566 | /* Calculate SNR estimation (scaled by 2^24) |
567 | ||
568 | 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM | |
569 | equations from LGDT3303 datasheet. VSB is the same between the '02 | |
570 | and '03, so maybe QAM is too? Perhaps someone with a newer datasheet | |
571 | that has QAM information could verify? | |
572 | ||
573 | For 8-VSB: (two ways, take your pick) | |
574 | LGDT3302: | |
575 | SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE) | |
576 | LGDT3303: | |
577 | SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE) | |
578 | LGDT3302 & LGDT3303: | |
579 | SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one) | |
580 | For 64-QAM: | |
581 | SNR = 10 * log10( 688128 / MSEQAM) | |
582 | For 256-QAM: | |
583 | SNR = 10 * log10( 696320 / MSEQAM) | |
584 | ||
585 | We re-write the snr equation as: | |
586 | SNR * 2^24 = 10*(c - intlog10(MSE)) | |
587 | Where for 256-QAM, c = log10(696320) * 2^24, and so on. */ | |
588 | ||
589 | static u32 calculate_snr(u32 mse, u32 c) | |
d8667cbb | 590 | { |
19be685a TP |
591 | if (mse == 0) /* No signal */ |
592 | return 0; | |
593 | ||
594 | mse = intlog10(mse); | |
595 | if (mse > c) { | |
596 | /* Negative SNR, which is possible, but realisticly the | |
597 | demod will lose lock before the signal gets this bad. The | |
598 | API only allows for unsigned values, so just return 0 */ | |
599 | return 0; | |
600 | } | |
601 | return 10*(c - mse); | |
d8667cbb MM |
602 | } |
603 | ||
1963c907 | 604 | static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr) |
d8667cbb | 605 | { |
6ddcc919 | 606 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
19be685a TP |
607 | u8 buf[5]; /* read data buffer */ |
608 | u32 noise; /* noise value */ | |
609 | u32 c; /* per-modulation SNR calculation constant */ | |
d8667cbb | 610 | |
19be685a TP |
611 | switch(state->current_modulation) { |
612 | case VSB_8: | |
613 | i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5); | |
614 | #ifdef USE_EQMSE | |
615 | /* Use Equalizer Mean-Square Error Register */ | |
616 | /* SNR for ranges from -15.61 to +41.58 */ | |
d8667cbb | 617 | noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2]; |
19be685a | 618 | c = 69765745; /* log10(25*24^2)*2^24 */ |
d8667cbb | 619 | #else |
19be685a TP |
620 | /* Use Phase Tracker Mean-Square Error Register */ |
621 | /* SNR for ranges from -13.11 to +44.08 */ | |
d8667cbb | 622 | noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4]; |
19be685a TP |
623 | c = 73957994; /* log10(25*32^2)*2^24 */ |
624 | #endif | |
625 | break; | |
626 | case QAM_64: | |
627 | case QAM_256: | |
628 | i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2); | |
1963c907 | 629 | noise = ((buf[0] & 3) << 8) | buf[1]; |
19be685a TP |
630 | c = state->current_modulation == QAM_64 ? 97939837 : 98026066; |
631 | /* log10(688128)*2^24 and log10(696320)*2^24 */ | |
632 | break; | |
633 | default: | |
634 | printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n", | |
271ddbf7 | 635 | __func__); |
19be685a | 636 | return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */ |
d8667cbb MM |
637 | } |
638 | ||
19be685a TP |
639 | state->snr = calculate_snr(noise, c); |
640 | *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */ | |
d8667cbb | 641 | |
271ddbf7 | 642 | dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise, |
19be685a | 643 | state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16); |
d8667cbb MM |
644 | |
645 | return 0; | |
646 | } | |
647 | ||
1963c907 MK |
648 | static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr) |
649 | { | |
1963c907 | 650 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
19be685a TP |
651 | u8 buf[5]; /* read data buffer */ |
652 | u32 noise; /* noise value */ | |
653 | u32 c; /* per-modulation SNR calculation constant */ | |
1963c907 | 654 | |
19be685a TP |
655 | switch(state->current_modulation) { |
656 | case VSB_8: | |
657 | i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5); | |
658 | #ifdef USE_EQMSE | |
659 | /* Use Equalizer Mean-Square Error Register */ | |
660 | /* SNR for ranges from -16.12 to +44.08 */ | |
661 | noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2]; | |
662 | c = 73957994; /* log10(25*32^2)*2^24 */ | |
663 | #else | |
664 | /* Use Phase Tracker Mean-Square Error Register */ | |
665 | /* SNR for ranges from -13.11 to +44.08 */ | |
1963c907 | 666 | noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4]; |
19be685a TP |
667 | c = 73957994; /* log10(25*32^2)*2^24 */ |
668 | #endif | |
669 | break; | |
670 | case QAM_64: | |
671 | case QAM_256: | |
672 | i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2); | |
1963c907 | 673 | noise = (buf[0] << 8) | buf[1]; |
19be685a TP |
674 | c = state->current_modulation == QAM_64 ? 97939837 : 98026066; |
675 | /* log10(688128)*2^24 and log10(696320)*2^24 */ | |
676 | break; | |
677 | default: | |
678 | printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n", | |
271ddbf7 | 679 | __func__); |
19be685a | 680 | return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */ |
1963c907 MK |
681 | } |
682 | ||
19be685a TP |
683 | state->snr = calculate_snr(noise, c); |
684 | *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */ | |
685 | ||
271ddbf7 | 686 | dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise, |
19be685a TP |
687 | state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength) | |
693 | { | |
694 | /* Calculate Strength from SNR up to 35dB */ | |
695 | /* Even though the SNR can go higher than 35dB, there is some comfort */ | |
696 | /* factor in having a range of strong signals that can show at 100% */ | |
697 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; | |
698 | u16 snr; | |
699 | int ret; | |
1963c907 | 700 | |
19be685a TP |
701 | ret = fe->ops.read_snr(fe, &snr); |
702 | if (ret != 0) | |
703 | return ret; | |
704 | /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ | |
705 | /* scale the range 0 - 35*2^24 into 0 - 65535 */ | |
706 | if (state->snr >= 8960 * 0x10000) | |
707 | *strength = 0xffff; | |
708 | else | |
709 | *strength = state->snr / 8960; | |
1963c907 MK |
710 | |
711 | return 0; | |
712 | } | |
713 | ||
6ddcc919 | 714 | static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings) |
d8667cbb MM |
715 | { |
716 | /* I have no idea about this - it may not be needed */ | |
717 | fe_tune_settings->min_delay_ms = 500; | |
718 | fe_tune_settings->step_size = 0; | |
719 | fe_tune_settings->max_drift = 0; | |
720 | return 0; | |
721 | } | |
722 | ||
6ddcc919 | 723 | static void lgdt330x_release(struct dvb_frontend* fe) |
d8667cbb | 724 | { |
6ddcc919 | 725 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
d8667cbb MM |
726 | kfree(state); |
727 | } | |
728 | ||
1963c907 MK |
729 | static struct dvb_frontend_ops lgdt3302_ops; |
730 | static struct dvb_frontend_ops lgdt3303_ops; | |
d8667cbb | 731 | |
6ddcc919 | 732 | struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, |
d8667cbb MM |
733 | struct i2c_adapter* i2c) |
734 | { | |
6ddcc919 | 735 | struct lgdt330x_state* state = NULL; |
d8667cbb MM |
736 | u8 buf[1]; |
737 | ||
738 | /* Allocate memory for the internal state */ | |
7408187d | 739 | state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL); |
d8667cbb MM |
740 | if (state == NULL) |
741 | goto error; | |
d8667cbb MM |
742 | |
743 | /* Setup the state */ | |
744 | state->config = config; | |
745 | state->i2c = i2c; | |
dea74869 PB |
746 | |
747 | /* Create dvb_frontend */ | |
1963c907 MK |
748 | switch (config->demod_chip) { |
749 | case LGDT3302: | |
dea74869 | 750 | memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops)); |
1963c907 MK |
751 | break; |
752 | case LGDT3303: | |
dea74869 | 753 | memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops)); |
1963c907 MK |
754 | break; |
755 | default: | |
756 | goto error; | |
757 | } | |
dea74869 | 758 | state->frontend.demodulator_priv = state; |
1963c907 | 759 | |
d8667cbb | 760 | /* Verify communication with demod chip */ |
1963c907 | 761 | if (i2c_read_demod_bytes(state, 2, buf, 1)) |
d8667cbb MM |
762 | goto error; |
763 | ||
764 | state->current_frequency = -1; | |
765 | state->current_modulation = -1; | |
766 | ||
d8667cbb MM |
767 | return &state->frontend; |
768 | ||
769 | error: | |
2ea75330 | 770 | kfree(state); |
271ddbf7 | 771 | dprintk("%s: ERROR\n",__func__); |
d8667cbb MM |
772 | return NULL; |
773 | } | |
774 | ||
1963c907 | 775 | static struct dvb_frontend_ops lgdt3302_ops = { |
ca7072dd | 776 | .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, |
1963c907 | 777 | .info = { |
e179d8b0 | 778 | .name= "LG Electronics LGDT3302 VSB/QAM Frontend", |
1963c907 MK |
779 | .frequency_min= 54000000, |
780 | .frequency_max= 858000000, | |
781 | .frequency_stepsize= 62500, | |
66944e99 MK |
782 | .symbol_rate_min = 5056941, /* QAM 64 */ |
783 | .symbol_rate_max = 10762000, /* VSB 8 */ | |
1963c907 MK |
784 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB |
785 | }, | |
786 | .init = lgdt330x_init, | |
ca7072dd MCC |
787 | .set_frontend = lgdt330x_set_parameters, |
788 | .get_frontend = lgdt330x_get_frontend, | |
1963c907 MK |
789 | .get_tune_settings = lgdt330x_get_tune_settings, |
790 | .read_status = lgdt3302_read_status, | |
791 | .read_ber = lgdt330x_read_ber, | |
792 | .read_signal_strength = lgdt330x_read_signal_strength, | |
793 | .read_snr = lgdt3302_read_snr, | |
794 | .read_ucblocks = lgdt330x_read_ucblocks, | |
795 | .release = lgdt330x_release, | |
796 | }; | |
797 | ||
798 | static struct dvb_frontend_ops lgdt3303_ops = { | |
ca7072dd | 799 | .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, |
d8667cbb | 800 | .info = { |
1963c907 | 801 | .name= "LG Electronics LGDT3303 VSB/QAM Frontend", |
d8667cbb MM |
802 | .frequency_min= 54000000, |
803 | .frequency_max= 858000000, | |
804 | .frequency_stepsize= 62500, | |
66944e99 MK |
805 | .symbol_rate_min = 5056941, /* QAM 64 */ |
806 | .symbol_rate_max = 10762000, /* VSB 8 */ | |
d8667cbb MM |
807 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB |
808 | }, | |
6ddcc919 | 809 | .init = lgdt330x_init, |
ca7072dd MCC |
810 | .set_frontend = lgdt330x_set_parameters, |
811 | .get_frontend = lgdt330x_get_frontend, | |
6ddcc919 | 812 | .get_tune_settings = lgdt330x_get_tune_settings, |
1963c907 | 813 | .read_status = lgdt3303_read_status, |
6ddcc919 MK |
814 | .read_ber = lgdt330x_read_ber, |
815 | .read_signal_strength = lgdt330x_read_signal_strength, | |
1963c907 | 816 | .read_snr = lgdt3303_read_snr, |
6ddcc919 MK |
817 | .read_ucblocks = lgdt330x_read_ucblocks, |
818 | .release = lgdt330x_release, | |
d8667cbb MM |
819 | }; |
820 | ||
1963c907 | 821 | MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); |
d8667cbb MM |
822 | MODULE_AUTHOR("Wilson Michaels"); |
823 | MODULE_LICENSE("GPL"); | |
824 | ||
6ddcc919 | 825 | EXPORT_SYMBOL(lgdt330x_attach); |
d8667cbb MM |
826 | |
827 | /* | |
828 | * Local variables: | |
829 | * c-basic-offset: 8 | |
d8667cbb MM |
830 | * End: |
831 | */ |