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[media] m88ts2022: fix coding style issues
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb-frontends / m88ds3103.c
CommitLineData
395d00d1
AP		 1/*
2 * Montage M88DS3103 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
395d00d1
AP		 15 */
16
17#include "m88ds3103_priv.h"
18
19static struct dvb_frontend_ops m88ds3103_ops;
20
21/* write multiple registers */
22static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
24{
63c80f70
AP		 25#define MAX_WR_LEN 32
26#define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
395d00d1 27 int ret;
63c80f70 28 u8 buf[MAX_WR_XFER_LEN];
395d00d1
AP		 29 struct i2c_msg msg[1] = {
30 {
31 .addr = priv->cfg->i2c_addr,
32 .flags = 0,
63c80f70 33 .len = 1 + len,
395d00d1
AP		 34 .buf = buf,
35 }
36 };
37
63c80f70
AP		 38 if (WARN_ON(len > MAX_WR_LEN))
39 return -EINVAL;
40
395d00d1
AP		 41 buf[0] = reg;
42 memcpy(&buf[1], val, len);
43
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
47 if (ret == 1) {
48 ret = 0;
49 } else {
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
53 ret = -EREMOTEIO;
54 }
55
56 return ret;
57}
58
59/* read multiple registers */
60static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
62{
63c80f70
AP		 63#define MAX_RD_LEN 3
64#define MAX_RD_XFER_LEN (MAX_RD_LEN)
395d00d1 65 int ret;
63c80f70 66 u8 buf[MAX_RD_XFER_LEN];
395d00d1
AP		 67 struct i2c_msg msg[2] = {
68 {
69 .addr = priv->cfg->i2c_addr,
70 .flags = 0,
71 .len = 1,
72 .buf = &reg,
73 }, {
74 .addr = priv->cfg->i2c_addr,
75 .flags = I2C_M_RD,
63c80f70 76 .len = len,
395d00d1
AP		 77 .buf = buf,
78 }
79 };
80
63c80f70
AP		 81 if (WARN_ON(len > MAX_RD_LEN))
82 return -EINVAL;
83
395d00d1
AP		 84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
87 if (ret == 2) {
88 memcpy(val, buf, len);
89 ret = 0;
90 } else {
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
94 ret = -EREMOTEIO;
95 }
96
97 return ret;
98}
99
100/* write single register */
101static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
102{
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
104}
105
106/* read single register */
107static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
108{
109 return m88ds3103_rd_regs(priv, reg, val, 1);
110}
111
112/* write single register with mask */
113static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
115{
116 int ret;
117 u8 u8tmp;
118
119 /* no need for read if whole reg is written */
120 if (mask != 0xff) {
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
122 if (ret)
123 return ret;
124
125 val &= mask;
126 u8tmp &= ~mask;
127 val |= u8tmp;
128 }
129
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
131}
132
133/* read single register with mask */
134static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
136{
137 int ret, i;
138 u8 u8tmp;
139
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
141 if (ret)
142 return ret;
143
144 u8tmp &= mask;
145
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
149 break;
150 }
151 *val = u8tmp >> i;
152
153 return 0;
154}
155
06487dee
AP		 156/* write reg val table using reg addr auto increment */
157static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
159{
160 int ret, i, j;
161 u8 buf[83];
162 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
163
164 if (tab_len > 83) {
165 ret = -EINVAL;
166 goto err;
167 }
168
169 for (i = 0, j = 0; i < tab_len; i++, j++) {
170 buf[j] = tab[i].val;
171
172 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
173 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
174 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
175 if (ret)
176 goto err;
177
178 j = -1;
179 }
180 }
181
182 return 0;
183err:
184 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
185 return ret;
186}
187
395d00d1
AP		 188static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
189{
190 struct m88ds3103_priv *priv = fe->demodulator_priv;
191 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
192 int ret;
193 u8 u8tmp;
194
195 *status = 0;
196
197 if (!priv->warm) {
198 ret = -EAGAIN;
199 goto err;
200 }
201
202 switch (c->delivery_system) {
203 case SYS_DVBS:
204 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
205 if (ret)
206 goto err;
207
208 if (u8tmp == 0x07)
209 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
210 FE_HAS_VITERBI | FE_HAS_SYNC |
211 FE_HAS_LOCK;
212 break;
213 case SYS_DVBS2:
214 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
215 if (ret)
216 goto err;
217
218 if (u8tmp == 0x8f)
219 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
220 FE_HAS_VITERBI | FE_HAS_SYNC |
221 FE_HAS_LOCK;
222 break;
223 default:
224 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
225 __func__);
226 ret = -EINVAL;
227 goto err;
228 }
229
230 priv->fe_status = *status;
231
232 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
233 __func__, u8tmp, *status);
234
235 return 0;
236err:
237 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
238 return ret;
239}
240
241static int m88ds3103_set_frontend(struct dvb_frontend *fe)
242{
243 struct m88ds3103_priv *priv = fe->demodulator_priv;
244 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
06487dee 245 int ret, len;
395d00d1
AP		 246 const struct m88ds3103_reg_val *init;
247 u8 u8tmp, u8tmp1, u8tmp2;
248 u8 buf[2];
249 u16 u16tmp, divide_ratio;
79d09330 250 u32 tuner_frequency, target_mclk;
395d00d1
AP		 251 s32 s32tmp;
252 dev_dbg(&priv->i2c->dev,
253 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
254 __func__, c->delivery_system,
255 c->modulation, c->frequency, c->symbol_rate,
256 c->inversion, c->pilot, c->rolloff);
257
258 if (!priv->warm) {
259 ret = -EAGAIN;
260 goto err;
261 }
262
263 /* program tuner */
264 if (fe->ops.tuner_ops.set_params) {
265 ret = fe->ops.tuner_ops.set_params(fe);
266 if (ret)
267 goto err;
268 }
269
270 if (fe->ops.tuner_ops.get_frequency) {
271 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
272 if (ret)
273 goto err;
2f9dff3f
AP		 274 } else {
275 /*
276 * Use nominal target frequency as tuner driver does not provide
277 * actual frequency used. Carrier offset calculation is not
278 * valid.
279 */
280 tuner_frequency = c->frequency;
395d00d1
AP		 281 }
282
283 /* reset */
284 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
285 if (ret)
286 goto err;
287
288 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
289 if (ret)
290 goto err;
291
292 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
293 if (ret)
294 goto err;
295
296 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
297 if (ret)
298 goto err;
299
300 switch (c->delivery_system) {
301 case SYS_DVBS:
302 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
303 init = m88ds3103_dvbs_init_reg_vals;
304 target_mclk = 96000;
305 break;
306 case SYS_DVBS2:
307 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
308 init = m88ds3103_dvbs2_init_reg_vals;
309
310 switch (priv->cfg->ts_mode) {
311 case M88DS3103_TS_SERIAL:
312 case M88DS3103_TS_SERIAL_D7:
313 if (c->symbol_rate < 18000000)
314 target_mclk = 96000;
315 else
316 target_mclk = 144000;
317 break;
318 case M88DS3103_TS_PARALLEL:
395d00d1
AP		 319 case M88DS3103_TS_CI:
320 if (c->symbol_rate < 18000000)
321 target_mclk = 96000;
322 else if (c->symbol_rate < 28000000)
323 target_mclk = 144000;
324 else
325 target_mclk = 192000;
326 break;
327 default:
328 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
329 __func__);
330 ret = -EINVAL;
331 goto err;
332 }
333 break;
334 default:
335 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
336 __func__);
337 ret = -EINVAL;
338 goto err;
339 }
340
341 /* program init table */
342 if (c->delivery_system != priv->delivery_system) {
06487dee
AP		 343 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
344 if (ret)
345 goto err;
395d00d1
AP		 346 }
347
348 u8tmp1 = 0; /* silence compiler warning */
349 switch (priv->cfg->ts_mode) {
350 case M88DS3103_TS_SERIAL:
351 u8tmp1 = 0x00;
79d09330 352 u8tmp = 0x06;
395d00d1
AP		 353 break;
354 case M88DS3103_TS_SERIAL_D7:
355 u8tmp1 = 0x20;
79d09330 356 u8tmp = 0x06;
395d00d1
AP		 357 break;
358 case M88DS3103_TS_PARALLEL:
79d09330 359 u8tmp = 0x02;
395d00d1
AP		 360 break;
361 case M88DS3103_TS_CI:
79d09330 362 u8tmp = 0x03;
395d00d1
AP		 363 break;
364 default:
365 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
366 ret = -EINVAL;
367 goto err;
368 }
369
79d09330 370 if (priv->cfg->ts_clk_pol)
371 u8tmp |= 0x40;
372
395d00d1 373 /* TS mode */
92676ac9 374 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
395d00d1
AP		 375 if (ret)
376 goto err;
377
378 switch (priv->cfg->ts_mode) {
379 case M88DS3103_TS_SERIAL:
380 case M88DS3103_TS_SERIAL_D7:
381 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
382 if (ret)
383 goto err;
384 }
385
79d09330 386 if (priv->cfg->ts_clk) {
387 divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk);
395d00d1
AP		 388 u8tmp1 = divide_ratio / 2;
389 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
390 } else {
391 divide_ratio = 0;
392 u8tmp1 = 0;
393 u8tmp2 = 0;
394 }
395
396 dev_dbg(&priv->i2c->dev,
397 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
79d09330 398 __func__, target_mclk, priv->cfg->ts_clk, divide_ratio);
395d00d1
AP		 399
400 u8tmp1--;
401 u8tmp2--;
402 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
403 u8tmp1 &= 0x3f;
404 /* u8tmp2[5:0] => ea[5:0] */
405 u8tmp2 &= 0x3f;
406
407 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
408 if (ret)
409 goto err;
410
411 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
412 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
413 if (ret)
414 goto err;
415
416 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
417 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
418 if (ret)
419 goto err;
420
421 switch (target_mclk) {
395d00d1
AP		 422 case 96000:
423 u8tmp1 = 0x02; /* 0b10 */
424 u8tmp2 = 0x01; /* 0b01 */
425 break;
395d00d1
AP		 426 case 144000:
427 u8tmp1 = 0x00; /* 0b00 */
428 u8tmp2 = 0x01; /* 0b01 */
429 break;
430 case 192000:
431 u8tmp1 = 0x03; /* 0b11 */
432 u8tmp2 = 0x00; /* 0b00 */
433 break;
395d00d1
AP		 434 }
435
436 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
437 if (ret)
438 goto err;
439
440 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
441 if (ret)
442 goto err;
443
444 if (c->symbol_rate <= 3000000)
445 u8tmp = 0x20;
446 else if (c->symbol_rate <= 10000000)
447 u8tmp = 0x10;
448 else
449 u8tmp = 0x06;
450
451 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
452 if (ret)
453 goto err;
454
455 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
456 if (ret)
457 goto err;
458
459 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
460 if (ret)
461 goto err;
462
463 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
464 if (ret)
465 goto err;
466
39c0029e 467 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2);
395d00d1
AP		 468 buf[0] = (u16tmp >> 0) & 0xff;
469 buf[1] = (u16tmp >> 8) & 0xff;
470 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
471 if (ret)
472 goto err;
473
474 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
475 if (ret)
476 goto err;
477
478 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
479 if (ret)
480 goto err;
481
482 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
483 if (ret)
484 goto err;
485
486 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
487 (tuner_frequency - c->frequency));
488
489 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
39c0029e 490 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ);
395d00d1
AP		 491 if (s32tmp < 0)
492 s32tmp += 0x10000;
493
494 buf[0] = (s32tmp >> 0) & 0xff;
495 buf[1] = (s32tmp >> 8) & 0xff;
496 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
497 if (ret)
498 goto err;
499
500 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
501 if (ret)
502 goto err;
503
504 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
505 if (ret)
506 goto err;
507
508 priv->delivery_system = c->delivery_system;
509
510 return 0;
511err:
512 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
513 return ret;
514}
515
516static int m88ds3103_init(struct dvb_frontend *fe)
517{
518 struct m88ds3103_priv *priv = fe->demodulator_priv;
519 int ret, len, remaining;
520 const struct firmware *fw = NULL;
521 u8 *fw_file = M88DS3103_FIRMWARE;
522 u8 u8tmp;
523 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
524
525 /* set cold state by default */
526 priv->warm = false;
527
528 /* wake up device from sleep */
529 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
530 if (ret)
531 goto err;
532
533 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
534 if (ret)
535 goto err;
536
537 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
538 if (ret)
539 goto err;
540
541 /* reset */
542 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
543 if (ret)
544 goto err;
545
546 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
547 if (ret)
548 goto err;
549
550 /* firmware status */
551 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
552 if (ret)
553 goto err;
554
555 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
556
557 if (u8tmp)
558 goto skip_fw_download;
559
560 /* cold state - try to download firmware */
561 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
562 KBUILD_MODNAME, m88ds3103_ops.info.name);
563
564 /* request the firmware, this will block and timeout */
565 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
566 if (ret) {
567 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
568 KBUILD_MODNAME, fw_file);
569 goto err;
570 }
571
572 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
573 KBUILD_MODNAME, fw_file);
574
575 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
576 if (ret)
577 goto err;
578
579 for (remaining = fw->size; remaining > 0;
580 remaining -= (priv->cfg->i2c_wr_max - 1)) {
581 len = remaining;
582 if (len > (priv->cfg->i2c_wr_max - 1))
583 len = (priv->cfg->i2c_wr_max - 1);
584
585 ret = m88ds3103_wr_regs(priv, 0xb0,
586 &fw->data[fw->size - remaining], len);
587 if (ret) {
588 dev_err(&priv->i2c->dev,
589 "%s: firmware download failed=%d\n",
590 KBUILD_MODNAME, ret);
591 goto err;
592 }
593 }
594
595 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
596 if (ret)
597 goto err;
598
599 release_firmware(fw);
600 fw = NULL;
601
602 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
603 if (ret)
604 goto err;
605
606 if (!u8tmp) {
607 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
608 KBUILD_MODNAME);
609 ret = -EFAULT;
610 goto err;
611 }
612
613 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
614 KBUILD_MODNAME, m88ds3103_ops.info.name);
615 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
616 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
617
618skip_fw_download:
619 /* warm state */
620 priv->warm = true;
621
622 return 0;
623err:
624 if (fw)
625 release_firmware(fw);
626
627 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
628 return ret;
629}
630
631static int m88ds3103_sleep(struct dvb_frontend *fe)
632{
633 struct m88ds3103_priv *priv = fe->demodulator_priv;
634 int ret;
635 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
636
637 priv->delivery_system = SYS_UNDEFINED;
638
639 /* TS Hi-Z */
640 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
641 if (ret)
642 goto err;
643
644 /* sleep */
645 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
646 if (ret)
647 goto err;
648
649 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
650 if (ret)
651 goto err;
652
653 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
654 if (ret)
655 goto err;
656
657 return 0;
658err:
659 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
660 return ret;
661}
662
663static int m88ds3103_get_frontend(struct dvb_frontend *fe)
664{
665 struct m88ds3103_priv *priv = fe->demodulator_priv;
666 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
667 int ret;
668 u8 buf[3];
669 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
670
671 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
672 ret = -EAGAIN;
673 goto err;
674 }
675
676 switch (c->delivery_system) {
677 case SYS_DVBS:
678 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
679 if (ret)
680 goto err;
681
682 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
683 if (ret)
684 goto err;
685
686 switch ((buf[0] >> 2) & 0x01) {
687 case 0:
688 c->inversion = INVERSION_OFF;
689 break;
690 case 1:
691 c->inversion = INVERSION_ON;
692 break;
395d00d1
AP		 693 }
694
695 switch ((buf[1] >> 5) & 0x07) {
696 case 0:
697 c->fec_inner = FEC_7_8;
698 break;
699 case 1:
700 c->fec_inner = FEC_5_6;
701 break;
702 case 2:
703 c->fec_inner = FEC_3_4;
704 break;
705 case 3:
706 c->fec_inner = FEC_2_3;
707 break;
708 case 4:
709 c->fec_inner = FEC_1_2;
710 break;
711 default:
712 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
713 __func__);
714 }
715
716 c->modulation = QPSK;
717
718 break;
719 case SYS_DVBS2:
720 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
721 if (ret)
722 goto err;
723
724 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
725 if (ret)
726 goto err;
727
728 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
729 if (ret)
730 goto err;
731
732 switch ((buf[0] >> 0) & 0x0f) {
733 case 2:
734 c->fec_inner = FEC_2_5;
735 break;
736 case 3:
737 c->fec_inner = FEC_1_2;
738 break;
739 case 4:
740 c->fec_inner = FEC_3_5;
741 break;
742 case 5:
743 c->fec_inner = FEC_2_3;
744 break;
745 case 6:
746 c->fec_inner = FEC_3_4;
747 break;
748 case 7:
749 c->fec_inner = FEC_4_5;
750 break;
751 case 8:
752 c->fec_inner = FEC_5_6;
753 break;
754 case 9:
755 c->fec_inner = FEC_8_9;
756 break;
757 case 10:
758 c->fec_inner = FEC_9_10;
759 break;
760 default:
761 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
762 __func__);
763 }
764
765 switch ((buf[0] >> 5) & 0x01) {
766 case 0:
767 c->pilot = PILOT_OFF;
768 break;
769 case 1:
770 c->pilot = PILOT_ON;
771 break;
395d00d1
AP		 772 }
773
774 switch ((buf[0] >> 6) & 0x07) {
775 case 0:
776 c->modulation = QPSK;
777 break;
778 case 1:
779 c->modulation = PSK_8;
780 break;
781 case 2:
782 c->modulation = APSK_16;
783 break;
784 case 3:
785 c->modulation = APSK_32;
786 break;
787 default:
788 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
789 __func__);
790 }
791
792 switch ((buf[1] >> 7) & 0x01) {
793 case 0:
794 c->inversion = INVERSION_OFF;
795 break;
796 case 1:
797 c->inversion = INVERSION_ON;
798 break;
395d00d1
AP		 799 }
800
801 switch ((buf[2] >> 0) & 0x03) {
802 case 0:
803 c->rolloff = ROLLOFF_35;
804 break;
805 case 1:
806 c->rolloff = ROLLOFF_25;
807 break;
808 case 2:
809 c->rolloff = ROLLOFF_20;
810 break;
811 default:
812 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
813 __func__);
814 }
815 break;
816 default:
817 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
818 __func__);
819 ret = -EINVAL;
820 goto err;
821 }
822
823 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
824 if (ret)
825 goto err;
826
827 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
828 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
829
830 return 0;
831err:
832 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
833 return ret;
834}
835
836static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
837{
838 struct m88ds3103_priv *priv = fe->demodulator_priv;
839 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
840 int ret, i, tmp;
841 u8 buf[3];
842 u16 noise, signal;
843 u32 noise_tot, signal_tot;
844 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
845 /* reports SNR in resolution of 0.1 dB */
846
847 /* more iterations for more accurate estimation */
848 #define M88DS3103_SNR_ITERATIONS 3
849
850 switch (c->delivery_system) {
851 case SYS_DVBS:
852 tmp = 0;
853
854 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
855 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
856 if (ret)
857 goto err;
858
859 tmp += buf[0];
860 }
861
862 /* use of one register limits max value to 15 dB */
863 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
864 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
865 if (tmp)
3ae266f8 866 *snr = div_u64((u64) 100 * intlog2(tmp), intlog2(10));
395d00d1
AP		 867 else
868 *snr = 0;
869 break;
870 case SYS_DVBS2:
871 noise_tot = 0;
872 signal_tot = 0;
873
874 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
875 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
876 if (ret)
877 goto err;
878
879 noise = buf[1] << 6; /* [13:6] */
880 noise |= buf[0] & 0x3f; /* [5:0] */
881 noise >>= 2;
882 signal = buf[2] * buf[2];
883 signal >>= 1;
884
885 noise_tot += noise;
886 signal_tot += signal;
887 }
888
889 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
890 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
891
892 /* SNR(X) dB = 10 * log10(X) dB */
893 if (signal > noise) {
894 tmp = signal / noise;
3ae266f8 895 *snr = div_u64((u64) 100 * intlog10(tmp), (1 << 24));
8a878dc4 896 } else {
395d00d1 897 *snr = 0;
8a878dc4 898 }
395d00d1
AP		 899 break;
900 default:
901 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
902 __func__);
903 ret = -EINVAL;
904 goto err;
905 }
906
907 return 0;
908err:
909 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
910 return ret;
911}
912
4423a2ba
AP		 913static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
914{
915 struct m88ds3103_priv *priv = fe->demodulator_priv;
916 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
917 int ret;
918 unsigned int utmp;
919 u8 buf[3], u8tmp;
920 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
921
922 switch (c->delivery_system) {
923 case SYS_DVBS:
924 ret = m88ds3103_wr_reg(priv, 0xf9, 0x04);
925 if (ret)
926 goto err;
927
928 ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp);
929 if (ret)
930 goto err;
931
932 if (!(u8tmp & 0x10)) {
933 u8tmp |= 0x10;
934
935 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2);
936 if (ret)
937 goto err;
938
939 priv->ber = (buf[1] << 8) | (buf[0] << 0);
940
941 /* restart counters */
942 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp);
943 if (ret)
944 goto err;
945 }
946 break;
947 case SYS_DVBS2:
948 ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3);
949 if (ret)
950 goto err;
951
952 utmp = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
953
954 if (utmp > 3000) {
955 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2);
956 if (ret)
957 goto err;
958
959 priv->ber = (buf[1] << 8) | (buf[0] << 0);
960
961 /* restart counters */
962 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01);
963 if (ret)
964 goto err;
965
966 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01);
967 if (ret)
968 goto err;
969
970 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00);
971 if (ret)
972 goto err;
973
974 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00);
975 if (ret)
976 goto err;
977 }
978 break;
979 default:
980 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
981 __func__);
982 ret = -EINVAL;
983 goto err;
984 }
985
986 *ber = priv->ber;
987
988 return 0;
989err:
990 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
991 return ret;
992}
395d00d1
AP		 993
994static int m88ds3103_set_tone(struct dvb_frontend *fe,
995 fe_sec_tone_mode_t fe_sec_tone_mode)
996{
997 struct m88ds3103_priv *priv = fe->demodulator_priv;
998 int ret;
999 u8 u8tmp, tone, reg_a1_mask;
1000 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
1001 fe_sec_tone_mode);
1002
1003 if (!priv->warm) {
1004 ret = -EAGAIN;
1005 goto err;
1006 }
1007
1008 switch (fe_sec_tone_mode) {
1009 case SEC_TONE_ON:
1010 tone = 0;
418a97cb 1011 reg_a1_mask = 0x47;
395d00d1
AP		 1012 break;
1013 case SEC_TONE_OFF:
1014 tone = 1;
1015 reg_a1_mask = 0x00;
1016 break;
1017 default:
1018 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
1019 __func__);
1020 ret = -EINVAL;
1021 goto err;
1022 }
1023
1024 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
1025 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1026 if (ret)
1027 goto err;
1028
1029 u8tmp = 1 << 2;
1030 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
1031 if (ret)
1032 goto err;
1033
1034 return 0;
1035err:
1036 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1037 return ret;
1038}
1039
79d09330 1040static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1041 fe_sec_voltage_t voltage)
1042{
1043 struct m88ds3103_priv *priv = fe->demodulator_priv;
1044 u8 data;
1045
1046 m88ds3103_rd_reg(priv, 0xa2, &data);
1047
1048 data &= ~0x03; /* bit0 V/H, bit1 off/on */
1049 if (priv->cfg->lnb_en_pol)
1050 data |= 0x02;
1051
1052 switch (voltage) {
1053 case SEC_VOLTAGE_18:
1054 if (priv->cfg->lnb_hv_pol == 0)
1055 data |= 0x01;
1056 break;
1057 case SEC_VOLTAGE_13:
1058 if (priv->cfg->lnb_hv_pol)
1059 data |= 0x01;
1060 break;
1061 case SEC_VOLTAGE_OFF:
1062 if (priv->cfg->lnb_en_pol)
1063 data &= ~0x02;
1064 else
1065 data |= 0x02;
1066 break;
1067 }
1068 m88ds3103_wr_reg(priv, 0xa2, data);
1069
1070 return 0;
1071}
1072
395d00d1
AP		 1073static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1074 struct dvb_diseqc_master_cmd *diseqc_cmd)
1075{
1076 struct m88ds3103_priv *priv = fe->demodulator_priv;
1077 int ret, i;
1078 u8 u8tmp;
1079 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1080 diseqc_cmd->msg_len, diseqc_cmd->msg);
1081
1082 if (!priv->warm) {
1083 ret = -EAGAIN;
1084 goto err;
1085 }
1086
1087 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1088 ret = -EINVAL;
1089 goto err;
1090 }
1091
1092 u8tmp = priv->cfg->envelope_mode << 5;
1093 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1094 if (ret)
1095 goto err;
1096
1097 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1098 diseqc_cmd->msg_len);
1099 if (ret)
1100 goto err;
1101
1102 ret = m88ds3103_wr_reg(priv, 0xa1,
1103 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1104 if (ret)
1105 goto err;
1106
1107 /* DiSEqC message typical period is 54 ms */
1108 usleep_range(40000, 60000);
1109
1110 /* wait DiSEqC TX ready */
1111 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1112 usleep_range(5000, 10000);
1113
1114 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1115 if (ret)
1116 goto err;
1117 }
1118
1119 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1120
1121 if (i == 0) {
1122 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1123
1124 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1125 if (ret)
1126 goto err;
1127 }
1128
1129 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1130 if (ret)
1131 goto err;
1132
1133 if (i == 0) {
1134 ret = -ETIMEDOUT;
1135 goto err;
1136 }
1137
1138 return 0;
1139err:
1140 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1141 return ret;
1142}
1143
1144static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1145 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1146{
1147 struct m88ds3103_priv *priv = fe->demodulator_priv;
1148 int ret, i;
1149 u8 u8tmp, burst;
1150 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1151 fe_sec_mini_cmd);
1152
1153 if (!priv->warm) {
1154 ret = -EAGAIN;
1155 goto err;
1156 }
1157
1158 u8tmp = priv->cfg->envelope_mode << 5;
1159 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1160 if (ret)
1161 goto err;
1162
1163 switch (fe_sec_mini_cmd) {
1164 case SEC_MINI_A:
1165 burst = 0x02;
1166 break;
1167 case SEC_MINI_B:
1168 burst = 0x01;
1169 break;
1170 default:
1171 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1172 __func__);
1173 ret = -EINVAL;
1174 goto err;
1175 }
1176
1177 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1178 if (ret)
1179 goto err;
1180
1181 /* DiSEqC ToneBurst period is 12.5 ms */
1182 usleep_range(11000, 20000);
1183
1184 /* wait DiSEqC TX ready */
1185 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1186 usleep_range(800, 2000);
1187
1188 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1189 if (ret)
1190 goto err;
1191 }
1192
1193 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1194
1195 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1196 if (ret)
1197 goto err;
1198
1199 if (i == 0) {
1200 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1201 ret = -ETIMEDOUT;
1202 goto err;
1203 }
1204
1205 return 0;
1206err:
1207 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1208 return ret;
1209}
1210
1211static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1212 struct dvb_frontend_tune_settings *s)
1213{
1214 s->min_delay_ms = 3000;
1215
1216 return 0;
1217}
1218
44b9055b 1219static void m88ds3103_release(struct dvb_frontend *fe)
395d00d1 1220{
44b9055b
AP		 1221 struct m88ds3103_priv *priv = fe->demodulator_priv;
1222 i2c_del_mux_adapter(priv->i2c_adapter);
1223 kfree(priv);
395d00d1
AP		 1224}
1225
44b9055b 1226static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
395d00d1 1227{
44b9055b 1228 struct m88ds3103_priv *priv = mux_priv;
395d00d1
AP		 1229 int ret;
1230 struct i2c_msg gate_open_msg[1] = {
1231 {
1232 .addr = priv->cfg->i2c_addr,
1233 .flags = 0,
1234 .len = 2,
1235 .buf = "\x03\x11",
1236 }
1237 };
395d00d1
AP		 1238
1239 mutex_lock(&priv->i2c_mutex);
1240
44b9055b 1241 /* open tuner I2C repeater for 1 xfer, closes automatically */
4fc57876 1242 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
395d00d1 1243 if (ret != 1) {
44b9055b 1244 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
395d00d1 1245 KBUILD_MODNAME, ret);
44b9055b
AP		 1246 if (ret >= 0)
1247 ret = -EREMOTEIO;
395d00d1 1248
44b9055b
AP		 1249 return ret;
1250 }
395d00d1 1251
44b9055b 1252 return 0;
395d00d1
AP		 1253}
1254
44b9055b
AP		 1255static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1256 u32 chan)
395d00d1 1257{
44b9055b
AP		 1258 struct m88ds3103_priv *priv = mux_priv;
1259
1260 mutex_unlock(&priv->i2c_mutex);
1261
1262 return 0;
395d00d1
AP		 1263}
1264
1265struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1266 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1267{
1268 int ret;
1269 struct m88ds3103_priv *priv;
1270 u8 chip_id, u8tmp;
1271
1272 /* allocate memory for the internal priv */
8a878dc4 1273 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
395d00d1
AP		 1274 if (!priv) {
1275 ret = -ENOMEM;
1276 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1277 goto err;
1278 }
1279
1280 priv->cfg = cfg;
1281 priv->i2c = i2c;
1282 mutex_init(&priv->i2c_mutex);
1283
1284 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1285 if (ret)
1286 goto err;
1287
1288 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1289
1290 switch (chip_id) {
1291 case 0xd0:
1292 break;
1293 default:
1294 goto err;
1295 }
1296
1297 switch (priv->cfg->clock_out) {
1298 case M88DS3103_CLOCK_OUT_DISABLED:
1299 u8tmp = 0x80;
1300 break;
1301 case M88DS3103_CLOCK_OUT_ENABLED:
1302 u8tmp = 0x00;
1303 break;
1304 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1305 u8tmp = 0x10;
1306 break;
1307 default:
1308 goto err;
1309 }
1310
1311 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1312 if (ret)
1313 goto err;
1314
1315 /* sleep */
1316 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1317 if (ret)
1318 goto err;
1319
1320 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1321 if (ret)
1322 goto err;
1323
1324 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1325 if (ret)
1326 goto err;
1327
44b9055b
AP		 1328 /* create mux i2c adapter for tuner */
1329 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1330 m88ds3103_select, m88ds3103_deselect);
1331 if (priv->i2c_adapter == NULL)
1332 goto err;
1333
1334 *tuner_i2c_adapter = priv->i2c_adapter;
1335
395d00d1
AP		 1336 /* create dvb_frontend */
1337 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1338 priv->fe.demodulator_priv = priv;
1339
395d00d1
AP		 1340 return &priv->fe;
1341err:
1342 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1343 kfree(priv);
1344 return NULL;
1345}
1346EXPORT_SYMBOL(m88ds3103_attach);
1347
1348static struct dvb_frontend_ops m88ds3103_ops = {
1349 .delsys = { SYS_DVBS, SYS_DVBS2 },
1350 .info = {
1351 .name = "Montage M88DS3103",
1352 .frequency_min = 950000,
1353 .frequency_max = 2150000,
1354 .frequency_tolerance = 5000,
1355 .symbol_rate_min = 1000000,
1356 .symbol_rate_max = 45000000,
1357 .caps = FE_CAN_INVERSION_AUTO |
1358 FE_CAN_FEC_1_2 |
1359 FE_CAN_FEC_2_3 |
1360 FE_CAN_FEC_3_4 |
1361 FE_CAN_FEC_4_5 |
1362 FE_CAN_FEC_5_6 |
1363 FE_CAN_FEC_6_7 |
1364 FE_CAN_FEC_7_8 |
1365 FE_CAN_FEC_8_9 |
1366 FE_CAN_FEC_AUTO |
1367 FE_CAN_QPSK |
1368 FE_CAN_RECOVER |
1369 FE_CAN_2G_MODULATION
1370 },
1371
1372 .release = m88ds3103_release,
1373
1374 .get_tune_settings = m88ds3103_get_tune_settings,
1375
1376 .init = m88ds3103_init,
1377 .sleep = m88ds3103_sleep,
1378
1379 .set_frontend = m88ds3103_set_frontend,
1380 .get_frontend = m88ds3103_get_frontend,
1381
1382 .read_status = m88ds3103_read_status,
1383 .read_snr = m88ds3103_read_snr,
4423a2ba 1384 .read_ber = m88ds3103_read_ber,
395d00d1
AP		 1385
1386 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1387 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1388
1389 .set_tone = m88ds3103_set_tone,
79d09330 1390 .set_voltage = m88ds3103_set_voltage,
395d00d1
AP		 1391};
1392
1393MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1394MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1395MODULE_LICENSE("GPL");
1396MODULE_FIRMWARE(M88DS3103_FIRMWARE);
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