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[media] m88ds3103: do not use dynamic stack allocation
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb-frontends / m88ds3103.c
CommitLineData
395d00d1
AP		 1/*
2 * Montage M88DS3103 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include "m88ds3103_priv.h"
22
23static struct dvb_frontend_ops m88ds3103_ops;
24
25/* write multiple registers */
26static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
27 u8 reg, const u8 *val, int len)
28{
63c80f70
AP		 29#define MAX_WR_LEN 32
30#define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
395d00d1 31 int ret;
63c80f70 32 u8 buf[MAX_WR_XFER_LEN];
395d00d1
AP		 33 struct i2c_msg msg[1] = {
34 {
35 .addr = priv->cfg->i2c_addr,
36 .flags = 0,
63c80f70 37 .len = 1 + len,
395d00d1
AP		 38 .buf = buf,
39 }
40 };
41
63c80f70
AP		 42 if (WARN_ON(len > MAX_WR_LEN))
43 return -EINVAL;
44
395d00d1
AP		 45 buf[0] = reg;
46 memcpy(&buf[1], val, len);
47
48 mutex_lock(&priv->i2c_mutex);
49 ret = i2c_transfer(priv->i2c, msg, 1);
50 mutex_unlock(&priv->i2c_mutex);
51 if (ret == 1) {
52 ret = 0;
53 } else {
54 dev_warn(&priv->i2c->dev,
55 "%s: i2c wr failed=%d reg=%02x len=%d\n",
56 KBUILD_MODNAME, ret, reg, len);
57 ret = -EREMOTEIO;
58 }
59
60 return ret;
61}
62
63/* read multiple registers */
64static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
65 u8 reg, u8 *val, int len)
66{
63c80f70
AP		 67#define MAX_RD_LEN 3
68#define MAX_RD_XFER_LEN (MAX_RD_LEN)
395d00d1 69 int ret;
63c80f70 70 u8 buf[MAX_RD_XFER_LEN];
395d00d1
AP		 71 struct i2c_msg msg[2] = {
72 {
73 .addr = priv->cfg->i2c_addr,
74 .flags = 0,
75 .len = 1,
76 .buf = &reg,
77 }, {
78 .addr = priv->cfg->i2c_addr,
79 .flags = I2C_M_RD,
63c80f70 80 .len = len,
395d00d1
AP		 81 .buf = buf,
82 }
83 };
84
63c80f70
AP		 85 if (WARN_ON(len > MAX_RD_LEN))
86 return -EINVAL;
87
395d00d1
AP		 88 mutex_lock(&priv->i2c_mutex);
89 ret = i2c_transfer(priv->i2c, msg, 2);
90 mutex_unlock(&priv->i2c_mutex);
91 if (ret == 2) {
92 memcpy(val, buf, len);
93 ret = 0;
94 } else {
95 dev_warn(&priv->i2c->dev,
96 "%s: i2c rd failed=%d reg=%02x len=%d\n",
97 KBUILD_MODNAME, ret, reg, len);
98 ret = -EREMOTEIO;
99 }
100
101 return ret;
102}
103
104/* write single register */
105static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
106{
107 return m88ds3103_wr_regs(priv, reg, &val, 1);
108}
109
110/* read single register */
111static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
112{
113 return m88ds3103_rd_regs(priv, reg, val, 1);
114}
115
116/* write single register with mask */
117static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
118 u8 reg, u8 val, u8 mask)
119{
120 int ret;
121 u8 u8tmp;
122
123 /* no need for read if whole reg is written */
124 if (mask != 0xff) {
125 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
126 if (ret)
127 return ret;
128
129 val &= mask;
130 u8tmp &= ~mask;
131 val |= u8tmp;
132 }
133
134 return m88ds3103_wr_regs(priv, reg, &val, 1);
135}
136
137/* read single register with mask */
138static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
139 u8 reg, u8 *val, u8 mask)
140{
141 int ret, i;
142 u8 u8tmp;
143
144 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
145 if (ret)
146 return ret;
147
148 u8tmp &= mask;
149
150 /* find position of the first bit */
151 for (i = 0; i < 8; i++) {
152 if ((mask >> i) & 0x01)
153 break;
154 }
155 *val = u8tmp >> i;
156
157 return 0;
158}
159
160static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
161{
162 struct m88ds3103_priv *priv = fe->demodulator_priv;
163 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
164 int ret;
165 u8 u8tmp;
166
167 *status = 0;
168
169 if (!priv->warm) {
170 ret = -EAGAIN;
171 goto err;
172 }
173
174 switch (c->delivery_system) {
175 case SYS_DVBS:
176 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
177 if (ret)
178 goto err;
179
180 if (u8tmp == 0x07)
181 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
182 FE_HAS_VITERBI | FE_HAS_SYNC |
183 FE_HAS_LOCK;
184 break;
185 case SYS_DVBS2:
186 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
187 if (ret)
188 goto err;
189
190 if (u8tmp == 0x8f)
191 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
192 FE_HAS_VITERBI | FE_HAS_SYNC |
193 FE_HAS_LOCK;
194 break;
195 default:
196 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
197 __func__);
198 ret = -EINVAL;
199 goto err;
200 }
201
202 priv->fe_status = *status;
203
204 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
205 __func__, u8tmp, *status);
206
207 return 0;
208err:
209 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
210 return ret;
211}
212
213static int m88ds3103_set_frontend(struct dvb_frontend *fe)
214{
215 struct m88ds3103_priv *priv = fe->demodulator_priv;
216 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
217 int ret, i, len;
218 const struct m88ds3103_reg_val *init;
219 u8 u8tmp, u8tmp1, u8tmp2;
220 u8 buf[2];
221 u16 u16tmp, divide_ratio;
222 u32 tuner_frequency, target_mclk, ts_clk;
223 s32 s32tmp;
224 dev_dbg(&priv->i2c->dev,
225 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
226 __func__, c->delivery_system,
227 c->modulation, c->frequency, c->symbol_rate,
228 c->inversion, c->pilot, c->rolloff);
229
230 if (!priv->warm) {
231 ret = -EAGAIN;
232 goto err;
233 }
234
235 /* program tuner */
236 if (fe->ops.tuner_ops.set_params) {
237 ret = fe->ops.tuner_ops.set_params(fe);
238 if (ret)
239 goto err;
240 }
241
242 if (fe->ops.tuner_ops.get_frequency) {
243 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
244 if (ret)
245 goto err;
246 }
247
248 /* reset */
249 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
250 if (ret)
251 goto err;
252
253 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
254 if (ret)
255 goto err;
256
257 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
258 if (ret)
259 goto err;
260
261 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
262 if (ret)
263 goto err;
264
265 switch (c->delivery_system) {
266 case SYS_DVBS:
267 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
268 init = m88ds3103_dvbs_init_reg_vals;
269 target_mclk = 96000;
270 break;
271 case SYS_DVBS2:
272 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
273 init = m88ds3103_dvbs2_init_reg_vals;
274
275 switch (priv->cfg->ts_mode) {
276 case M88DS3103_TS_SERIAL:
277 case M88DS3103_TS_SERIAL_D7:
278 if (c->symbol_rate < 18000000)
279 target_mclk = 96000;
280 else
281 target_mclk = 144000;
282 break;
283 case M88DS3103_TS_PARALLEL:
284 case M88DS3103_TS_PARALLEL_12:
285 case M88DS3103_TS_PARALLEL_16:
286 case M88DS3103_TS_PARALLEL_19_2:
287 case M88DS3103_TS_CI:
288 if (c->symbol_rate < 18000000)
289 target_mclk = 96000;
290 else if (c->symbol_rate < 28000000)
291 target_mclk = 144000;
292 else
293 target_mclk = 192000;
294 break;
295 default:
296 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
297 __func__);
298 ret = -EINVAL;
299 goto err;
300 }
301 break;
302 default:
303 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
304 __func__);
305 ret = -EINVAL;
306 goto err;
307 }
308
309 /* program init table */
310 if (c->delivery_system != priv->delivery_system) {
311 dev_dbg(&priv->i2c->dev, "%s: program init\n", __func__);
312 for (i = 0; i < len; i++) {
313 ret = m88ds3103_wr_reg(priv, init[i].reg, init[i].val);
314 if (ret)
315 goto err;
316 }
317 }
318
319 u8tmp1 = 0; /* silence compiler warning */
320 switch (priv->cfg->ts_mode) {
321 case M88DS3103_TS_SERIAL:
322 u8tmp1 = 0x00;
323 ts_clk = 0;
324 u8tmp = 0x04;
325 break;
326 case M88DS3103_TS_SERIAL_D7:
327 u8tmp1 = 0x20;
328 ts_clk = 0;
329 u8tmp = 0x04;
330 break;
331 case M88DS3103_TS_PARALLEL:
332 ts_clk = 24000;
333 u8tmp = 0x00;
334 break;
335 case M88DS3103_TS_PARALLEL_12:
336 ts_clk = 12000;
337 u8tmp = 0x00;
338 break;
339 case M88DS3103_TS_PARALLEL_16:
340 ts_clk = 16000;
341 u8tmp = 0x00;
342 break;
343 case M88DS3103_TS_PARALLEL_19_2:
344 ts_clk = 19200;
345 u8tmp = 0x00;
346 break;
347 case M88DS3103_TS_CI:
348 ts_clk = 6000;
349 u8tmp = 0x01;
350 break;
351 default:
352 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
353 ret = -EINVAL;
354 goto err;
355 }
356
357 /* TS mode */
358 ret = m88ds3103_wr_reg_mask(priv, 0xfd, u8tmp, 0x05);
359 if (ret)
360 goto err;
361
362 switch (priv->cfg->ts_mode) {
363 case M88DS3103_TS_SERIAL:
364 case M88DS3103_TS_SERIAL_D7:
365 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
366 if (ret)
367 goto err;
368 }
369
370 if (ts_clk) {
371 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk);
372 u8tmp1 = divide_ratio / 2;
373 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
374 } else {
375 divide_ratio = 0;
376 u8tmp1 = 0;
377 u8tmp2 = 0;
378 }
379
380 dev_dbg(&priv->i2c->dev,
381 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
382 __func__, target_mclk, ts_clk, divide_ratio);
383
384 u8tmp1--;
385 u8tmp2--;
386 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
387 u8tmp1 &= 0x3f;
388 /* u8tmp2[5:0] => ea[5:0] */
389 u8tmp2 &= 0x3f;
390
391 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
392 if (ret)
393 goto err;
394
395 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
396 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
397 if (ret)
398 goto err;
399
400 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
401 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
402 if (ret)
403 goto err;
404
405 switch (target_mclk) {
406 case 72000:
407 u8tmp1 = 0x00; /* 0b00 */
408 u8tmp2 = 0x03; /* 0b11 */
409 break;
410 case 96000:
411 u8tmp1 = 0x02; /* 0b10 */
412 u8tmp2 = 0x01; /* 0b01 */
413 break;
414 case 115200:
415 u8tmp1 = 0x01; /* 0b01 */
416 u8tmp2 = 0x01; /* 0b01 */
417 break;
418 case 144000:
419 u8tmp1 = 0x00; /* 0b00 */
420 u8tmp2 = 0x01; /* 0b01 */
421 break;
422 case 192000:
423 u8tmp1 = 0x03; /* 0b11 */
424 u8tmp2 = 0x00; /* 0b00 */
425 break;
426 default:
427 dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__);
428 ret = -EINVAL;
429 goto err;
430 }
431
432 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
433 if (ret)
434 goto err;
435
436 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
437 if (ret)
438 goto err;
439
440 if (c->symbol_rate <= 3000000)
441 u8tmp = 0x20;
442 else if (c->symbol_rate <= 10000000)
443 u8tmp = 0x10;
444 else
445 u8tmp = 0x06;
446
447 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
448 if (ret)
449 goto err;
450
451 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
452 if (ret)
453 goto err;
454
455 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
456 if (ret)
457 goto err;
458
459 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
460 if (ret)
461 goto err;
462
463 u16tmp = (((c->symbol_rate / 1000) << 15) + (M88DS3103_MCLK_KHZ / 4)) /
464 (M88DS3103_MCLK_KHZ / 2);
465 buf[0] = (u16tmp >> 0) & 0xff;
466 buf[1] = (u16tmp >> 8) & 0xff;
467 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
468 if (ret)
469 goto err;
470
471 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
472 if (ret)
473 goto err;
474
475 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
476 if (ret)
477 goto err;
478
479 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
480 if (ret)
481 goto err;
482
483 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
484 (tuner_frequency - c->frequency));
485
486 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
487 s32tmp = (2 * s32tmp + M88DS3103_MCLK_KHZ) / (2 * M88DS3103_MCLK_KHZ);
488 if (s32tmp < 0)
489 s32tmp += 0x10000;
490
491 buf[0] = (s32tmp >> 0) & 0xff;
492 buf[1] = (s32tmp >> 8) & 0xff;
493 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
494 if (ret)
495 goto err;
496
497 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
498 if (ret)
499 goto err;
500
501 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
502 if (ret)
503 goto err;
504
505 priv->delivery_system = c->delivery_system;
506
507 return 0;
508err:
509 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
510 return ret;
511}
512
513static int m88ds3103_init(struct dvb_frontend *fe)
514{
515 struct m88ds3103_priv *priv = fe->demodulator_priv;
516 int ret, len, remaining;
517 const struct firmware *fw = NULL;
518 u8 *fw_file = M88DS3103_FIRMWARE;
519 u8 u8tmp;
520 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
521
522 /* set cold state by default */
523 priv->warm = false;
524
525 /* wake up device from sleep */
526 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
527 if (ret)
528 goto err;
529
530 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
531 if (ret)
532 goto err;
533
534 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
535 if (ret)
536 goto err;
537
538 /* reset */
539 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
540 if (ret)
541 goto err;
542
543 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
544 if (ret)
545 goto err;
546
547 /* firmware status */
548 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
549 if (ret)
550 goto err;
551
552 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
553
554 if (u8tmp)
555 goto skip_fw_download;
556
557 /* cold state - try to download firmware */
558 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
559 KBUILD_MODNAME, m88ds3103_ops.info.name);
560
561 /* request the firmware, this will block and timeout */
562 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
563 if (ret) {
564 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
565 KBUILD_MODNAME, fw_file);
566 goto err;
567 }
568
569 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
570 KBUILD_MODNAME, fw_file);
571
572 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
573 if (ret)
574 goto err;
575
576 for (remaining = fw->size; remaining > 0;
577 remaining -= (priv->cfg->i2c_wr_max - 1)) {
578 len = remaining;
579 if (len > (priv->cfg->i2c_wr_max - 1))
580 len = (priv->cfg->i2c_wr_max - 1);
581
582 ret = m88ds3103_wr_regs(priv, 0xb0,
583 &fw->data[fw->size - remaining], len);
584 if (ret) {
585 dev_err(&priv->i2c->dev,
586 "%s: firmware download failed=%d\n",
587 KBUILD_MODNAME, ret);
588 goto err;
589 }
590 }
591
592 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
593 if (ret)
594 goto err;
595
596 release_firmware(fw);
597 fw = NULL;
598
599 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
600 if (ret)
601 goto err;
602
603 if (!u8tmp) {
604 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
605 KBUILD_MODNAME);
606 ret = -EFAULT;
607 goto err;
608 }
609
610 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
611 KBUILD_MODNAME, m88ds3103_ops.info.name);
612 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
613 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
614
615skip_fw_download:
616 /* warm state */
617 priv->warm = true;
618
619 return 0;
620err:
621 if (fw)
622 release_firmware(fw);
623
624 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
625 return ret;
626}
627
628static int m88ds3103_sleep(struct dvb_frontend *fe)
629{
630 struct m88ds3103_priv *priv = fe->demodulator_priv;
631 int ret;
632 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
633
634 priv->delivery_system = SYS_UNDEFINED;
635
636 /* TS Hi-Z */
637 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
638 if (ret)
639 goto err;
640
641 /* sleep */
642 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
643 if (ret)
644 goto err;
645
646 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
647 if (ret)
648 goto err;
649
650 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
651 if (ret)
652 goto err;
653
654 return 0;
655err:
656 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
657 return ret;
658}
659
660static int m88ds3103_get_frontend(struct dvb_frontend *fe)
661{
662 struct m88ds3103_priv *priv = fe->demodulator_priv;
663 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
664 int ret;
665 u8 buf[3];
666 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
667
668 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
669 ret = -EAGAIN;
670 goto err;
671 }
672
673 switch (c->delivery_system) {
674 case SYS_DVBS:
675 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
676 if (ret)
677 goto err;
678
679 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
680 if (ret)
681 goto err;
682
683 switch ((buf[0] >> 2) & 0x01) {
684 case 0:
685 c->inversion = INVERSION_OFF;
686 break;
687 case 1:
688 c->inversion = INVERSION_ON;
689 break;
690 default:
691 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
692 __func__);
693 }
694
695 switch ((buf[1] >> 5) & 0x07) {
696 case 0:
697 c->fec_inner = FEC_7_8;
698 break;
699 case 1:
700 c->fec_inner = FEC_5_6;
701 break;
702 case 2:
703 c->fec_inner = FEC_3_4;
704 break;
705 case 3:
706 c->fec_inner = FEC_2_3;
707 break;
708 case 4:
709 c->fec_inner = FEC_1_2;
710 break;
711 default:
712 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
713 __func__);
714 }
715
716 c->modulation = QPSK;
717
718 break;
719 case SYS_DVBS2:
720 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
721 if (ret)
722 goto err;
723
724 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
725 if (ret)
726 goto err;
727
728 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
729 if (ret)
730 goto err;
731
732 switch ((buf[0] >> 0) & 0x0f) {
733 case 2:
734 c->fec_inner = FEC_2_5;
735 break;
736 case 3:
737 c->fec_inner = FEC_1_2;
738 break;
739 case 4:
740 c->fec_inner = FEC_3_5;
741 break;
742 case 5:
743 c->fec_inner = FEC_2_3;
744 break;
745 case 6:
746 c->fec_inner = FEC_3_4;
747 break;
748 case 7:
749 c->fec_inner = FEC_4_5;
750 break;
751 case 8:
752 c->fec_inner = FEC_5_6;
753 break;
754 case 9:
755 c->fec_inner = FEC_8_9;
756 break;
757 case 10:
758 c->fec_inner = FEC_9_10;
759 break;
760 default:
761 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
762 __func__);
763 }
764
765 switch ((buf[0] >> 5) & 0x01) {
766 case 0:
767 c->pilot = PILOT_OFF;
768 break;
769 case 1:
770 c->pilot = PILOT_ON;
771 break;
772 default:
773 dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n",
774 __func__);
775 }
776
777 switch ((buf[0] >> 6) & 0x07) {
778 case 0:
779 c->modulation = QPSK;
780 break;
781 case 1:
782 c->modulation = PSK_8;
783 break;
784 case 2:
785 c->modulation = APSK_16;
786 break;
787 case 3:
788 c->modulation = APSK_32;
789 break;
790 default:
791 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
792 __func__);
793 }
794
795 switch ((buf[1] >> 7) & 0x01) {
796 case 0:
797 c->inversion = INVERSION_OFF;
798 break;
799 case 1:
800 c->inversion = INVERSION_ON;
801 break;
802 default:
803 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
804 __func__);
805 }
806
807 switch ((buf[2] >> 0) & 0x03) {
808 case 0:
809 c->rolloff = ROLLOFF_35;
810 break;
811 case 1:
812 c->rolloff = ROLLOFF_25;
813 break;
814 case 2:
815 c->rolloff = ROLLOFF_20;
816 break;
817 default:
818 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
819 __func__);
820 }
821 break;
822 default:
823 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
824 __func__);
825 ret = -EINVAL;
826 goto err;
827 }
828
829 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
830 if (ret)
831 goto err;
832
833 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
834 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
835
836 return 0;
837err:
838 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
839 return ret;
840}
841
842static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
843{
844 struct m88ds3103_priv *priv = fe->demodulator_priv;
845 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
846 int ret, i, tmp;
847 u8 buf[3];
848 u16 noise, signal;
849 u32 noise_tot, signal_tot;
850 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
851 /* reports SNR in resolution of 0.1 dB */
852
853 /* more iterations for more accurate estimation */
854 #define M88DS3103_SNR_ITERATIONS 3
855
856 switch (c->delivery_system) {
857 case SYS_DVBS:
858 tmp = 0;
859
860 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
861 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
862 if (ret)
863 goto err;
864
865 tmp += buf[0];
866 }
867
868 /* use of one register limits max value to 15 dB */
869 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
870 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
871 if (tmp)
872 *snr = 100ul * intlog2(tmp) / intlog2(10);
873 else
874 *snr = 0;
875 break;
876 case SYS_DVBS2:
877 noise_tot = 0;
878 signal_tot = 0;
879
880 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
881 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
882 if (ret)
883 goto err;
884
885 noise = buf[1] << 6; /* [13:6] */
886 noise |= buf[0] & 0x3f; /* [5:0] */
887 noise >>= 2;
888 signal = buf[2] * buf[2];
889 signal >>= 1;
890
891 noise_tot += noise;
892 signal_tot += signal;
893 }
894
895 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
896 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
897
898 /* SNR(X) dB = 10 * log10(X) dB */
899 if (signal > noise) {
900 tmp = signal / noise;
901 *snr = 100ul * intlog10(tmp) / (1 << 24);
902 } else
903 *snr = 0;
904 break;
905 default:
906 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
907 __func__);
908 ret = -EINVAL;
909 goto err;
910 }
911
912 return 0;
913err:
914 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
915 return ret;
916}
917
918
919static int m88ds3103_set_tone(struct dvb_frontend *fe,
920 fe_sec_tone_mode_t fe_sec_tone_mode)
921{
922 struct m88ds3103_priv *priv = fe->demodulator_priv;
923 int ret;
924 u8 u8tmp, tone, reg_a1_mask;
925 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
926 fe_sec_tone_mode);
927
928 if (!priv->warm) {
929 ret = -EAGAIN;
930 goto err;
931 }
932
933 switch (fe_sec_tone_mode) {
934 case SEC_TONE_ON:
935 tone = 0;
936 reg_a1_mask = 0x87;
937 break;
938 case SEC_TONE_OFF:
939 tone = 1;
940 reg_a1_mask = 0x00;
941 break;
942 default:
943 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
944 __func__);
945 ret = -EINVAL;
946 goto err;
947 }
948
949 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
950 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
951 if (ret)
952 goto err;
953
954 u8tmp = 1 << 2;
955 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
956 if (ret)
957 goto err;
958
959 return 0;
960err:
961 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
962 return ret;
963}
964
965static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
966 struct dvb_diseqc_master_cmd *diseqc_cmd)
967{
968 struct m88ds3103_priv *priv = fe->demodulator_priv;
969 int ret, i;
970 u8 u8tmp;
971 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
972 diseqc_cmd->msg_len, diseqc_cmd->msg);
973
974 if (!priv->warm) {
975 ret = -EAGAIN;
976 goto err;
977 }
978
979 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
980 ret = -EINVAL;
981 goto err;
982 }
983
984 u8tmp = priv->cfg->envelope_mode << 5;
985 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
986 if (ret)
987 goto err;
988
989 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
990 diseqc_cmd->msg_len);
991 if (ret)
992 goto err;
993
994 ret = m88ds3103_wr_reg(priv, 0xa1,
995 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
996 if (ret)
997 goto err;
998
999 /* DiSEqC message typical period is 54 ms */
1000 usleep_range(40000, 60000);
1001
1002 /* wait DiSEqC TX ready */
1003 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1004 usleep_range(5000, 10000);
1005
1006 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1007 if (ret)
1008 goto err;
1009 }
1010
1011 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1012
1013 if (i == 0) {
1014 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1015
1016 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1017 if (ret)
1018 goto err;
1019 }
1020
1021 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1022 if (ret)
1023 goto err;
1024
1025 if (i == 0) {
1026 ret = -ETIMEDOUT;
1027 goto err;
1028 }
1029
1030 return 0;
1031err:
1032 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1033 return ret;
1034}
1035
1036static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1037 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1038{
1039 struct m88ds3103_priv *priv = fe->demodulator_priv;
1040 int ret, i;
1041 u8 u8tmp, burst;
1042 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1043 fe_sec_mini_cmd);
1044
1045 if (!priv->warm) {
1046 ret = -EAGAIN;
1047 goto err;
1048 }
1049
1050 u8tmp = priv->cfg->envelope_mode << 5;
1051 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1052 if (ret)
1053 goto err;
1054
1055 switch (fe_sec_mini_cmd) {
1056 case SEC_MINI_A:
1057 burst = 0x02;
1058 break;
1059 case SEC_MINI_B:
1060 burst = 0x01;
1061 break;
1062 default:
1063 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1064 __func__);
1065 ret = -EINVAL;
1066 goto err;
1067 }
1068
1069 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1070 if (ret)
1071 goto err;
1072
1073 /* DiSEqC ToneBurst period is 12.5 ms */
1074 usleep_range(11000, 20000);
1075
1076 /* wait DiSEqC TX ready */
1077 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1078 usleep_range(800, 2000);
1079
1080 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1081 if (ret)
1082 goto err;
1083 }
1084
1085 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1086
1087 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1088 if (ret)
1089 goto err;
1090
1091 if (i == 0) {
1092 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1093 ret = -ETIMEDOUT;
1094 goto err;
1095 }
1096
1097 return 0;
1098err:
1099 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1100 return ret;
1101}
1102
1103static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1104 struct dvb_frontend_tune_settings *s)
1105{
1106 s->min_delay_ms = 3000;
1107
1108 return 0;
1109}
1110
1111static u32 m88ds3103_tuner_i2c_func(struct i2c_adapter *adapter)
1112{
1113 return I2C_FUNC_I2C;
1114}
1115
1116static int m88ds3103_tuner_i2c_xfer(struct i2c_adapter *i2c_adap,
1117 struct i2c_msg msg[], int num)
1118{
1119 struct m88ds3103_priv *priv = i2c_get_adapdata(i2c_adap);
1120 int ret;
1121 struct i2c_msg gate_open_msg[1] = {
1122 {
1123 .addr = priv->cfg->i2c_addr,
1124 .flags = 0,
1125 .len = 2,
1126 .buf = "\x03\x11",
1127 }
1128 };
1129 dev_dbg(&priv->i2c->dev, "%s: num=%d\n", __func__, num);
1130
1131 mutex_lock(&priv->i2c_mutex);
1132
1133 /* open i2c-gate */
1134 ret = i2c_transfer(priv->i2c, gate_open_msg, 1);
1135 if (ret != 1) {
1136 mutex_unlock(&priv->i2c_mutex);
1137 dev_warn(&priv->i2c->dev,
1138 "%s: i2c wr failed=%d\n",
1139 KBUILD_MODNAME, ret);
1140 ret = -EREMOTEIO;
1141 goto err;
1142 }
1143
1144 ret = i2c_transfer(priv->i2c, msg, num);
1145 mutex_unlock(&priv->i2c_mutex);
1146 if (ret < 0)
1147 dev_warn(&priv->i2c->dev, "%s: i2c failed=%d\n",
1148 KBUILD_MODNAME, ret);
1149
1150 return ret;
1151err:
1152 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1153 return ret;
1154}
1155
1156static struct i2c_algorithm m88ds3103_tuner_i2c_algo = {
1157 .master_xfer = m88ds3103_tuner_i2c_xfer,
1158 .functionality = m88ds3103_tuner_i2c_func,
1159};
1160
1161static void m88ds3103_release(struct dvb_frontend *fe)
1162{
1163 struct m88ds3103_priv *priv = fe->demodulator_priv;
1164 i2c_del_adapter(&priv->i2c_adapter);
1165 kfree(priv);
1166}
1167
1168struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1169 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1170{
1171 int ret;
1172 struct m88ds3103_priv *priv;
1173 u8 chip_id, u8tmp;
1174
1175 /* allocate memory for the internal priv */
1176 priv = kzalloc(sizeof(struct m88ds3103_priv), GFP_KERNEL);
1177 if (!priv) {
1178 ret = -ENOMEM;
1179 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1180 goto err;
1181 }
1182
1183 priv->cfg = cfg;
1184 priv->i2c = i2c;
1185 mutex_init(&priv->i2c_mutex);
1186
1187 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1188 if (ret)
1189 goto err;
1190
1191 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1192
1193 switch (chip_id) {
1194 case 0xd0:
1195 break;
1196 default:
1197 goto err;
1198 }
1199
1200 switch (priv->cfg->clock_out) {
1201 case M88DS3103_CLOCK_OUT_DISABLED:
1202 u8tmp = 0x80;
1203 break;
1204 case M88DS3103_CLOCK_OUT_ENABLED:
1205 u8tmp = 0x00;
1206 break;
1207 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1208 u8tmp = 0x10;
1209 break;
1210 default:
1211 goto err;
1212 }
1213
1214 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1215 if (ret)
1216 goto err;
1217
1218 /* sleep */
1219 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1220 if (ret)
1221 goto err;
1222
1223 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1224 if (ret)
1225 goto err;
1226
1227 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1228 if (ret)
1229 goto err;
1230
1231 /* create dvb_frontend */
1232 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1233 priv->fe.demodulator_priv = priv;
1234
1235 /* create i2c adapter for tuner */
1236 strlcpy(priv->i2c_adapter.name, KBUILD_MODNAME,
1237 sizeof(priv->i2c_adapter.name));
1238 priv->i2c_adapter.algo = &m88ds3103_tuner_i2c_algo;
1239 priv->i2c_adapter.algo_data = NULL;
1240 i2c_set_adapdata(&priv->i2c_adapter, priv);
1241 ret = i2c_add_adapter(&priv->i2c_adapter);
1242 if (ret) {
1243 dev_err(&i2c->dev, "%s: i2c bus could not be initialized\n",
1244 KBUILD_MODNAME);
1245 goto err;
1246 }
1247 *tuner_i2c_adapter = &priv->i2c_adapter;
1248
1249 return &priv->fe;
1250err:
1251 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1252 kfree(priv);
1253 return NULL;
1254}
1255EXPORT_SYMBOL(m88ds3103_attach);
1256
1257static struct dvb_frontend_ops m88ds3103_ops = {
1258 .delsys = { SYS_DVBS, SYS_DVBS2 },
1259 .info = {
1260 .name = "Montage M88DS3103",
1261 .frequency_min = 950000,
1262 .frequency_max = 2150000,
1263 .frequency_tolerance = 5000,
1264 .symbol_rate_min = 1000000,
1265 .symbol_rate_max = 45000000,
1266 .caps = FE_CAN_INVERSION_AUTO |
1267 FE_CAN_FEC_1_2 |
1268 FE_CAN_FEC_2_3 |
1269 FE_CAN_FEC_3_4 |
1270 FE_CAN_FEC_4_5 |
1271 FE_CAN_FEC_5_6 |
1272 FE_CAN_FEC_6_7 |
1273 FE_CAN_FEC_7_8 |
1274 FE_CAN_FEC_8_9 |
1275 FE_CAN_FEC_AUTO |
1276 FE_CAN_QPSK |
1277 FE_CAN_RECOVER |
1278 FE_CAN_2G_MODULATION
1279 },
1280
1281 .release = m88ds3103_release,
1282
1283 .get_tune_settings = m88ds3103_get_tune_settings,
1284
1285 .init = m88ds3103_init,
1286 .sleep = m88ds3103_sleep,
1287
1288 .set_frontend = m88ds3103_set_frontend,
1289 .get_frontend = m88ds3103_get_frontend,
1290
1291 .read_status = m88ds3103_read_status,
1292 .read_snr = m88ds3103_read_snr,
1293
1294 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1295 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1296
1297 .set_tone = m88ds3103_set_tone,
1298};
1299
1300MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1301MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1302MODULE_LICENSE("GPL");
1303MODULE_FIRMWARE(M88DS3103_FIRMWARE);
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