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Commit | Line | Data |
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395d00d1 | 1 | /* |
7978b8a1 | 2 | * Montage Technology M88DS3103/M88RS6000 demodulator driver |
395d00d1 AP |
3 | * |
4 | * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
395d00d1 AP |
15 | */ |
16 | ||
17 | #include "m88ds3103_priv.h" | |
18 | ||
19 | static struct dvb_frontend_ops m88ds3103_ops; | |
20 | ||
21 | /* write multiple registers */ | |
7978b8a1 | 22 | static int m88ds3103_wr_regs(struct m88ds3103_dev *dev, |
395d00d1 AP |
23 | u8 reg, const u8 *val, int len) |
24 | { | |
63c80f70 AP |
25 | #define MAX_WR_LEN 32 |
26 | #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1) | |
7978b8a1 | 27 | struct i2c_client *client = dev->client; |
395d00d1 | 28 | int ret; |
63c80f70 | 29 | u8 buf[MAX_WR_XFER_LEN]; |
395d00d1 AP |
30 | struct i2c_msg msg[1] = { |
31 | { | |
7978b8a1 | 32 | .addr = client->addr, |
395d00d1 | 33 | .flags = 0, |
63c80f70 | 34 | .len = 1 + len, |
395d00d1 AP |
35 | .buf = buf, |
36 | } | |
37 | }; | |
38 | ||
63c80f70 AP |
39 | if (WARN_ON(len > MAX_WR_LEN)) |
40 | return -EINVAL; | |
41 | ||
395d00d1 AP |
42 | buf[0] = reg; |
43 | memcpy(&buf[1], val, len); | |
44 | ||
7978b8a1 AP |
45 | mutex_lock(&dev->i2c_mutex); |
46 | ret = i2c_transfer(client->adapter, msg, 1); | |
47 | mutex_unlock(&dev->i2c_mutex); | |
395d00d1 AP |
48 | if (ret == 1) { |
49 | ret = 0; | |
50 | } else { | |
7978b8a1 AP |
51 | dev_warn(&client->dev, "i2c wr failed=%d reg=%02x len=%d\n", |
52 | ret, reg, len); | |
395d00d1 AP |
53 | ret = -EREMOTEIO; |
54 | } | |
55 | ||
56 | return ret; | |
57 | } | |
58 | ||
59 | /* read multiple registers */ | |
7978b8a1 | 60 | static int m88ds3103_rd_regs(struct m88ds3103_dev *dev, |
395d00d1 AP |
61 | u8 reg, u8 *val, int len) |
62 | { | |
63c80f70 AP |
63 | #define MAX_RD_LEN 3 |
64 | #define MAX_RD_XFER_LEN (MAX_RD_LEN) | |
7978b8a1 | 65 | struct i2c_client *client = dev->client; |
395d00d1 | 66 | int ret; |
63c80f70 | 67 | u8 buf[MAX_RD_XFER_LEN]; |
395d00d1 AP |
68 | struct i2c_msg msg[2] = { |
69 | { | |
7978b8a1 | 70 | .addr = client->addr, |
395d00d1 AP |
71 | .flags = 0, |
72 | .len = 1, | |
73 | .buf = ®, | |
74 | }, { | |
7978b8a1 | 75 | .addr = client->addr, |
395d00d1 | 76 | .flags = I2C_M_RD, |
63c80f70 | 77 | .len = len, |
395d00d1 AP |
78 | .buf = buf, |
79 | } | |
80 | }; | |
81 | ||
63c80f70 AP |
82 | if (WARN_ON(len > MAX_RD_LEN)) |
83 | return -EINVAL; | |
84 | ||
7978b8a1 AP |
85 | mutex_lock(&dev->i2c_mutex); |
86 | ret = i2c_transfer(client->adapter, msg, 2); | |
87 | mutex_unlock(&dev->i2c_mutex); | |
395d00d1 AP |
88 | if (ret == 2) { |
89 | memcpy(val, buf, len); | |
90 | ret = 0; | |
91 | } else { | |
7978b8a1 AP |
92 | dev_warn(&client->dev, "i2c rd failed=%d reg=%02x len=%d\n", |
93 | ret, reg, len); | |
395d00d1 AP |
94 | ret = -EREMOTEIO; |
95 | } | |
96 | ||
97 | return ret; | |
98 | } | |
99 | ||
100 | /* write single register */ | |
7978b8a1 | 101 | static int m88ds3103_wr_reg(struct m88ds3103_dev *dev, u8 reg, u8 val) |
395d00d1 | 102 | { |
7978b8a1 | 103 | return m88ds3103_wr_regs(dev, reg, &val, 1); |
395d00d1 AP |
104 | } |
105 | ||
106 | /* read single register */ | |
7978b8a1 | 107 | static int m88ds3103_rd_reg(struct m88ds3103_dev *dev, u8 reg, u8 *val) |
395d00d1 | 108 | { |
7978b8a1 | 109 | return m88ds3103_rd_regs(dev, reg, val, 1); |
395d00d1 AP |
110 | } |
111 | ||
112 | /* write single register with mask */ | |
7978b8a1 | 113 | static int m88ds3103_wr_reg_mask(struct m88ds3103_dev *dev, |
395d00d1 AP |
114 | u8 reg, u8 val, u8 mask) |
115 | { | |
116 | int ret; | |
117 | u8 u8tmp; | |
118 | ||
119 | /* no need for read if whole reg is written */ | |
120 | if (mask != 0xff) { | |
7978b8a1 | 121 | ret = m88ds3103_rd_regs(dev, reg, &u8tmp, 1); |
395d00d1 AP |
122 | if (ret) |
123 | return ret; | |
124 | ||
125 | val &= mask; | |
126 | u8tmp &= ~mask; | |
127 | val |= u8tmp; | |
128 | } | |
129 | ||
7978b8a1 | 130 | return m88ds3103_wr_regs(dev, reg, &val, 1); |
395d00d1 AP |
131 | } |
132 | ||
133 | /* read single register with mask */ | |
7978b8a1 | 134 | static int m88ds3103_rd_reg_mask(struct m88ds3103_dev *dev, |
395d00d1 AP |
135 | u8 reg, u8 *val, u8 mask) |
136 | { | |
137 | int ret, i; | |
138 | u8 u8tmp; | |
139 | ||
7978b8a1 | 140 | ret = m88ds3103_rd_regs(dev, reg, &u8tmp, 1); |
395d00d1 AP |
141 | if (ret) |
142 | return ret; | |
143 | ||
144 | u8tmp &= mask; | |
145 | ||
146 | /* find position of the first bit */ | |
147 | for (i = 0; i < 8; i++) { | |
148 | if ((mask >> i) & 0x01) | |
149 | break; | |
150 | } | |
151 | *val = u8tmp >> i; | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
06487dee | 156 | /* write reg val table using reg addr auto increment */ |
7978b8a1 | 157 | static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev, |
06487dee AP |
158 | const struct m88ds3103_reg_val *tab, int tab_len) |
159 | { | |
7978b8a1 | 160 | struct i2c_client *client = dev->client; |
06487dee AP |
161 | int ret, i, j; |
162 | u8 buf[83]; | |
41b9aa00 | 163 | |
7978b8a1 | 164 | dev_dbg(&client->dev, "tab_len=%d\n", tab_len); |
06487dee | 165 | |
f4df95bc | 166 | if (tab_len > 86) { |
06487dee AP |
167 | ret = -EINVAL; |
168 | goto err; | |
169 | } | |
170 | ||
171 | for (i = 0, j = 0; i < tab_len; i++, j++) { | |
172 | buf[j] = tab[i].val; | |
173 | ||
174 | if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || | |
7978b8a1 AP |
175 | !((j + 1) % (dev->cfg->i2c_wr_max - 1))) { |
176 | ret = m88ds3103_wr_regs(dev, tab[i].reg - j, buf, j + 1); | |
06487dee AP |
177 | if (ret) |
178 | goto err; | |
179 | ||
180 | j = -1; | |
181 | } | |
182 | } | |
183 | ||
184 | return 0; | |
185 | err: | |
7978b8a1 | 186 | dev_dbg(&client->dev, "failed=%d\n", ret); |
06487dee AP |
187 | return ret; |
188 | } | |
189 | ||
0df289a2 MCC |
190 | static int m88ds3103_read_status(struct dvb_frontend *fe, |
191 | enum fe_status *status) | |
395d00d1 | 192 | { |
7978b8a1 AP |
193 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
194 | struct i2c_client *client = dev->client; | |
395d00d1 | 195 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
c1daf651 | 196 | int ret, i, itmp; |
395d00d1 | 197 | u8 u8tmp; |
c1daf651 | 198 | u8 buf[3]; |
395d00d1 AP |
199 | |
200 | *status = 0; | |
201 | ||
7978b8a1 | 202 | if (!dev->warm) { |
395d00d1 AP |
203 | ret = -EAGAIN; |
204 | goto err; | |
205 | } | |
206 | ||
207 | switch (c->delivery_system) { | |
208 | case SYS_DVBS: | |
7978b8a1 | 209 | ret = m88ds3103_rd_reg_mask(dev, 0xd1, &u8tmp, 0x07); |
395d00d1 AP |
210 | if (ret) |
211 | goto err; | |
212 | ||
213 | if (u8tmp == 0x07) | |
214 | *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | | |
215 | FE_HAS_VITERBI | FE_HAS_SYNC | | |
216 | FE_HAS_LOCK; | |
217 | break; | |
218 | case SYS_DVBS2: | |
7978b8a1 | 219 | ret = m88ds3103_rd_reg_mask(dev, 0x0d, &u8tmp, 0x8f); |
395d00d1 AP |
220 | if (ret) |
221 | goto err; | |
222 | ||
223 | if (u8tmp == 0x8f) | |
224 | *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | | |
225 | FE_HAS_VITERBI | FE_HAS_SYNC | | |
226 | FE_HAS_LOCK; | |
227 | break; | |
228 | default: | |
7978b8a1 | 229 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
395d00d1 AP |
230 | ret = -EINVAL; |
231 | goto err; | |
232 | } | |
233 | ||
7978b8a1 | 234 | dev->fe_status = *status; |
395d00d1 | 235 | |
7978b8a1 | 236 | dev_dbg(&client->dev, "lock=%02x status=%02x\n", u8tmp, *status); |
395d00d1 | 237 | |
c1daf651 | 238 | /* CNR */ |
7978b8a1 | 239 | if (dev->fe_status & FE_HAS_VITERBI) { |
c1daf651 AP |
240 | unsigned int cnr, noise, signal, noise_tot, signal_tot; |
241 | ||
242 | cnr = 0; | |
243 | /* more iterations for more accurate estimation */ | |
244 | #define M88DS3103_SNR_ITERATIONS 3 | |
245 | ||
246 | switch (c->delivery_system) { | |
247 | case SYS_DVBS: | |
248 | itmp = 0; | |
249 | ||
250 | for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { | |
7978b8a1 | 251 | ret = m88ds3103_rd_reg(dev, 0xff, &buf[0]); |
c1daf651 AP |
252 | if (ret) |
253 | goto err; | |
254 | ||
255 | itmp += buf[0]; | |
256 | } | |
257 | ||
258 | /* use of single register limits max value to 15 dB */ | |
259 | /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ | |
260 | itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS); | |
261 | if (itmp) | |
262 | cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10)); | |
263 | break; | |
264 | case SYS_DVBS2: | |
265 | noise_tot = 0; | |
266 | signal_tot = 0; | |
267 | ||
268 | for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { | |
7978b8a1 | 269 | ret = m88ds3103_rd_regs(dev, 0x8c, buf, 3); |
c1daf651 AP |
270 | if (ret) |
271 | goto err; | |
272 | ||
273 | noise = buf[1] << 6; /* [13:6] */ | |
274 | noise |= buf[0] & 0x3f; /* [5:0] */ | |
275 | noise >>= 2; | |
276 | signal = buf[2] * buf[2]; | |
277 | signal >>= 1; | |
278 | ||
279 | noise_tot += noise; | |
280 | signal_tot += signal; | |
281 | } | |
282 | ||
283 | noise = noise_tot / M88DS3103_SNR_ITERATIONS; | |
284 | signal = signal_tot / M88DS3103_SNR_ITERATIONS; | |
285 | ||
286 | /* SNR(X) dB = 10 * log10(X) dB */ | |
287 | if (signal > noise) { | |
288 | itmp = signal / noise; | |
289 | cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24)); | |
290 | } | |
291 | break; | |
292 | default: | |
7978b8a1 | 293 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
c1daf651 AP |
294 | ret = -EINVAL; |
295 | goto err; | |
296 | } | |
297 | ||
298 | if (cnr) { | |
299 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
300 | c->cnr.stat[0].svalue = cnr; | |
301 | } else { | |
302 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
303 | } | |
304 | } else { | |
305 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
306 | } | |
307 | ||
ce80d713 | 308 | /* BER */ |
7978b8a1 | 309 | if (dev->fe_status & FE_HAS_LOCK) { |
ce80d713 AP |
310 | unsigned int utmp, post_bit_error, post_bit_count; |
311 | ||
312 | switch (c->delivery_system) { | |
313 | case SYS_DVBS: | |
7978b8a1 | 314 | ret = m88ds3103_wr_reg(dev, 0xf9, 0x04); |
ce80d713 AP |
315 | if (ret) |
316 | goto err; | |
317 | ||
7978b8a1 | 318 | ret = m88ds3103_rd_reg(dev, 0xf8, &u8tmp); |
ce80d713 AP |
319 | if (ret) |
320 | goto err; | |
321 | ||
322 | /* measurement ready? */ | |
323 | if (!(u8tmp & 0x10)) { | |
7978b8a1 | 324 | ret = m88ds3103_rd_regs(dev, 0xf6, buf, 2); |
ce80d713 AP |
325 | if (ret) |
326 | goto err; | |
327 | ||
328 | post_bit_error = buf[1] << 8 | buf[0] << 0; | |
329 | post_bit_count = 0x800000; | |
7978b8a1 AP |
330 | dev->post_bit_error += post_bit_error; |
331 | dev->post_bit_count += post_bit_count; | |
332 | dev->dvbv3_ber = post_bit_error; | |
ce80d713 AP |
333 | |
334 | /* restart measurement */ | |
335 | u8tmp |= 0x10; | |
7978b8a1 | 336 | ret = m88ds3103_wr_reg(dev, 0xf8, u8tmp); |
ce80d713 AP |
337 | if (ret) |
338 | goto err; | |
339 | } | |
340 | break; | |
341 | case SYS_DVBS2: | |
7978b8a1 | 342 | ret = m88ds3103_rd_regs(dev, 0xd5, buf, 3); |
ce80d713 AP |
343 | if (ret) |
344 | goto err; | |
345 | ||
346 | utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0; | |
347 | ||
348 | /* enough data? */ | |
349 | if (utmp > 4000) { | |
7978b8a1 | 350 | ret = m88ds3103_rd_regs(dev, 0xf7, buf, 2); |
ce80d713 AP |
351 | if (ret) |
352 | goto err; | |
353 | ||
354 | post_bit_error = buf[1] << 8 | buf[0] << 0; | |
355 | post_bit_count = 32 * utmp; /* TODO: FEC */ | |
7978b8a1 AP |
356 | dev->post_bit_error += post_bit_error; |
357 | dev->post_bit_count += post_bit_count; | |
358 | dev->dvbv3_ber = post_bit_error; | |
ce80d713 AP |
359 | |
360 | /* restart measurement */ | |
7978b8a1 | 361 | ret = m88ds3103_wr_reg(dev, 0xd1, 0x01); |
ce80d713 AP |
362 | if (ret) |
363 | goto err; | |
364 | ||
7978b8a1 | 365 | ret = m88ds3103_wr_reg(dev, 0xf9, 0x01); |
ce80d713 AP |
366 | if (ret) |
367 | goto err; | |
368 | ||
7978b8a1 | 369 | ret = m88ds3103_wr_reg(dev, 0xf9, 0x00); |
ce80d713 AP |
370 | if (ret) |
371 | goto err; | |
372 | ||
7978b8a1 | 373 | ret = m88ds3103_wr_reg(dev, 0xd1, 0x00); |
ce80d713 AP |
374 | if (ret) |
375 | goto err; | |
376 | } | |
377 | break; | |
378 | default: | |
7978b8a1 | 379 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
ce80d713 AP |
380 | ret = -EINVAL; |
381 | goto err; | |
382 | } | |
383 | ||
384 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
7978b8a1 | 385 | c->post_bit_error.stat[0].uvalue = dev->post_bit_error; |
ce80d713 | 386 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; |
7978b8a1 | 387 | c->post_bit_count.stat[0].uvalue = dev->post_bit_count; |
ce80d713 AP |
388 | } else { |
389 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
390 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
391 | } | |
392 | ||
395d00d1 AP |
393 | return 0; |
394 | err: | |
7978b8a1 | 395 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
396 | return ret; |
397 | } | |
398 | ||
399 | static int m88ds3103_set_frontend(struct dvb_frontend *fe) | |
400 | { | |
7978b8a1 AP |
401 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
402 | struct i2c_client *client = dev->client; | |
395d00d1 | 403 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
06487dee | 404 | int ret, len; |
395d00d1 | 405 | const struct m88ds3103_reg_val *init; |
b6851419 | 406 | u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */ |
f4df95bc | 407 | u8 buf[3]; |
b6851419 | 408 | u16 u16tmp, divide_ratio = 0; |
79d09330 | 409 | u32 tuner_frequency, target_mclk; |
395d00d1 | 410 | s32 s32tmp; |
41b9aa00 | 411 | |
7978b8a1 AP |
412 | dev_dbg(&client->dev, |
413 | "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", | |
414 | c->delivery_system, c->modulation, c->frequency, c->symbol_rate, | |
415 | c->inversion, c->pilot, c->rolloff); | |
395d00d1 | 416 | |
7978b8a1 | 417 | if (!dev->warm) { |
395d00d1 AP |
418 | ret = -EAGAIN; |
419 | goto err; | |
420 | } | |
421 | ||
f4df95bc | 422 | /* reset */ |
7978b8a1 | 423 | ret = m88ds3103_wr_reg(dev, 0x07, 0x80); |
f4df95bc | 424 | if (ret) |
425 | goto err; | |
426 | ||
7978b8a1 | 427 | ret = m88ds3103_wr_reg(dev, 0x07, 0x00); |
f4df95bc | 428 | if (ret) |
429 | goto err; | |
430 | ||
431 | /* Disable demod clock path */ | |
7978b8a1 AP |
432 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
433 | ret = m88ds3103_wr_reg(dev, 0x06, 0xe0); | |
f4df95bc | 434 | if (ret) |
435 | goto err; | |
436 | } | |
437 | ||
395d00d1 AP |
438 | /* program tuner */ |
439 | if (fe->ops.tuner_ops.set_params) { | |
440 | ret = fe->ops.tuner_ops.set_params(fe); | |
441 | if (ret) | |
442 | goto err; | |
443 | } | |
444 | ||
445 | if (fe->ops.tuner_ops.get_frequency) { | |
446 | ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); | |
447 | if (ret) | |
448 | goto err; | |
2f9dff3f AP |
449 | } else { |
450 | /* | |
451 | * Use nominal target frequency as tuner driver does not provide | |
452 | * actual frequency used. Carrier offset calculation is not | |
453 | * valid. | |
454 | */ | |
455 | tuner_frequency = c->frequency; | |
395d00d1 AP |
456 | } |
457 | ||
f4df95bc | 458 | /* select M88RS6000 demod main mclk and ts mclk from tuner die. */ |
7978b8a1 | 459 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 460 | if (c->symbol_rate > 45010000) |
7978b8a1 | 461 | dev->mclk_khz = 110250; |
f4df95bc | 462 | else |
7978b8a1 | 463 | dev->mclk_khz = 96000; |
395d00d1 | 464 | |
f4df95bc | 465 | if (c->delivery_system == SYS_DVBS) |
466 | target_mclk = 96000; | |
467 | else | |
468 | target_mclk = 144000; | |
469 | ||
470 | /* Enable demod clock path */ | |
7978b8a1 | 471 | ret = m88ds3103_wr_reg(dev, 0x06, 0x00); |
f4df95bc | 472 | if (ret) |
473 | goto err; | |
474 | usleep_range(10000, 20000); | |
475 | } else { | |
476 | /* set M88DS3103 mclk and ts mclk. */ | |
7978b8a1 | 477 | dev->mclk_khz = 96000; |
f4df95bc | 478 | |
7978b8a1 | 479 | switch (dev->cfg->ts_mode) { |
b6851419 | 480 | case M88DS3103_TS_SERIAL: |
481 | case M88DS3103_TS_SERIAL_D7: | |
7978b8a1 | 482 | target_mclk = dev->cfg->ts_clk; |
b6851419 | 483 | break; |
484 | case M88DS3103_TS_PARALLEL: | |
485 | case M88DS3103_TS_CI: | |
486 | if (c->delivery_system == SYS_DVBS) | |
487 | target_mclk = 96000; | |
488 | else { | |
f4df95bc | 489 | if (c->symbol_rate < 18000000) |
490 | target_mclk = 96000; | |
491 | else if (c->symbol_rate < 28000000) | |
492 | target_mclk = 144000; | |
493 | else | |
494 | target_mclk = 192000; | |
f4df95bc | 495 | } |
b6851419 | 496 | break; |
497 | default: | |
7978b8a1 | 498 | dev_dbg(&client->dev, "invalid ts_mode\n"); |
b6851419 | 499 | ret = -EINVAL; |
500 | goto err; | |
f4df95bc | 501 | } |
502 | ||
503 | switch (target_mclk) { | |
504 | case 96000: | |
505 | u8tmp1 = 0x02; /* 0b10 */ | |
506 | u8tmp2 = 0x01; /* 0b01 */ | |
507 | break; | |
508 | case 144000: | |
509 | u8tmp1 = 0x00; /* 0b00 */ | |
510 | u8tmp2 = 0x01; /* 0b01 */ | |
511 | break; | |
512 | case 192000: | |
513 | u8tmp1 = 0x03; /* 0b11 */ | |
514 | u8tmp2 = 0x00; /* 0b00 */ | |
515 | break; | |
516 | } | |
7978b8a1 | 517 | ret = m88ds3103_wr_reg_mask(dev, 0x22, u8tmp1 << 6, 0xc0); |
f4df95bc | 518 | if (ret) |
519 | goto err; | |
7978b8a1 | 520 | ret = m88ds3103_wr_reg_mask(dev, 0x24, u8tmp2 << 6, 0xc0); |
f4df95bc | 521 | if (ret) |
522 | goto err; | |
523 | } | |
395d00d1 | 524 | |
7978b8a1 | 525 | ret = m88ds3103_wr_reg(dev, 0xb2, 0x01); |
395d00d1 AP |
526 | if (ret) |
527 | goto err; | |
528 | ||
7978b8a1 | 529 | ret = m88ds3103_wr_reg(dev, 0x00, 0x01); |
395d00d1 AP |
530 | if (ret) |
531 | goto err; | |
532 | ||
533 | switch (c->delivery_system) { | |
534 | case SYS_DVBS: | |
7978b8a1 | 535 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 536 | len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals); |
537 | init = m88rs6000_dvbs_init_reg_vals; | |
538 | } else { | |
539 | len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); | |
540 | init = m88ds3103_dvbs_init_reg_vals; | |
541 | } | |
395d00d1 AP |
542 | break; |
543 | case SYS_DVBS2: | |
7978b8a1 | 544 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 545 | len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals); |
546 | init = m88rs6000_dvbs2_init_reg_vals; | |
547 | } else { | |
548 | len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); | |
549 | init = m88ds3103_dvbs2_init_reg_vals; | |
395d00d1 AP |
550 | } |
551 | break; | |
552 | default: | |
7978b8a1 | 553 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
395d00d1 AP |
554 | ret = -EINVAL; |
555 | goto err; | |
556 | } | |
557 | ||
558 | /* program init table */ | |
7978b8a1 AP |
559 | if (c->delivery_system != dev->delivery_system) { |
560 | ret = m88ds3103_wr_reg_val_tab(dev, init, len); | |
06487dee AP |
561 | if (ret) |
562 | goto err; | |
395d00d1 AP |
563 | } |
564 | ||
7978b8a1 | 565 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 566 | if ((c->delivery_system == SYS_DVBS2) |
567 | && ((c->symbol_rate / 1000) <= 5000)) { | |
7978b8a1 | 568 | ret = m88ds3103_wr_reg(dev, 0xc0, 0x04); |
f4df95bc | 569 | if (ret) |
570 | goto err; | |
571 | buf[0] = 0x09; | |
572 | buf[1] = 0x22; | |
573 | buf[2] = 0x88; | |
7978b8a1 | 574 | ret = m88ds3103_wr_regs(dev, 0x8a, buf, 3); |
f4df95bc | 575 | if (ret) |
576 | goto err; | |
577 | } | |
7978b8a1 | 578 | ret = m88ds3103_wr_reg_mask(dev, 0x9d, 0x08, 0x08); |
f4df95bc | 579 | if (ret) |
580 | goto err; | |
7978b8a1 | 581 | ret = m88ds3103_wr_reg(dev, 0xf1, 0x01); |
f4df95bc | 582 | if (ret) |
583 | goto err; | |
7978b8a1 | 584 | ret = m88ds3103_wr_reg_mask(dev, 0x30, 0x80, 0x80); |
f4df95bc | 585 | if (ret) |
586 | goto err; | |
587 | } | |
588 | ||
7978b8a1 | 589 | switch (dev->cfg->ts_mode) { |
395d00d1 AP |
590 | case M88DS3103_TS_SERIAL: |
591 | u8tmp1 = 0x00; | |
79d09330 | 592 | u8tmp = 0x06; |
395d00d1 AP |
593 | break; |
594 | case M88DS3103_TS_SERIAL_D7: | |
595 | u8tmp1 = 0x20; | |
79d09330 | 596 | u8tmp = 0x06; |
395d00d1 AP |
597 | break; |
598 | case M88DS3103_TS_PARALLEL: | |
79d09330 | 599 | u8tmp = 0x02; |
395d00d1 AP |
600 | break; |
601 | case M88DS3103_TS_CI: | |
79d09330 | 602 | u8tmp = 0x03; |
395d00d1 AP |
603 | break; |
604 | default: | |
7978b8a1 | 605 | dev_dbg(&client->dev, "invalid ts_mode\n"); |
395d00d1 AP |
606 | ret = -EINVAL; |
607 | goto err; | |
608 | } | |
609 | ||
7978b8a1 | 610 | if (dev->cfg->ts_clk_pol) |
79d09330 | 611 | u8tmp |= 0x40; |
612 | ||
395d00d1 | 613 | /* TS mode */ |
7978b8a1 | 614 | ret = m88ds3103_wr_reg(dev, 0xfd, u8tmp); |
395d00d1 AP |
615 | if (ret) |
616 | goto err; | |
617 | ||
7978b8a1 | 618 | switch (dev->cfg->ts_mode) { |
395d00d1 AP |
619 | case M88DS3103_TS_SERIAL: |
620 | case M88DS3103_TS_SERIAL_D7: | |
7978b8a1 | 621 | ret = m88ds3103_wr_reg_mask(dev, 0x29, u8tmp1, 0x20); |
395d00d1 AP |
622 | if (ret) |
623 | goto err; | |
395d00d1 AP |
624 | u8tmp1 = 0; |
625 | u8tmp2 = 0; | |
b6851419 | 626 | break; |
627 | default: | |
7978b8a1 AP |
628 | if (dev->cfg->ts_clk) { |
629 | divide_ratio = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk); | |
b6851419 | 630 | u8tmp1 = divide_ratio / 2; |
631 | u8tmp2 = DIV_ROUND_UP(divide_ratio, 2); | |
632 | } | |
395d00d1 AP |
633 | } |
634 | ||
7978b8a1 AP |
635 | dev_dbg(&client->dev, |
636 | "target_mclk=%d ts_clk=%d divide_ratio=%d\n", | |
637 | target_mclk, dev->cfg->ts_clk, divide_ratio); | |
395d00d1 AP |
638 | |
639 | u8tmp1--; | |
640 | u8tmp2--; | |
641 | /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ | |
642 | u8tmp1 &= 0x3f; | |
643 | /* u8tmp2[5:0] => ea[5:0] */ | |
644 | u8tmp2 &= 0x3f; | |
645 | ||
7978b8a1 | 646 | ret = m88ds3103_rd_reg(dev, 0xfe, &u8tmp); |
395d00d1 AP |
647 | if (ret) |
648 | goto err; | |
649 | ||
650 | u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2; | |
7978b8a1 | 651 | ret = m88ds3103_wr_reg(dev, 0xfe, u8tmp); |
395d00d1 AP |
652 | if (ret) |
653 | goto err; | |
654 | ||
655 | u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; | |
7978b8a1 | 656 | ret = m88ds3103_wr_reg(dev, 0xea, u8tmp); |
395d00d1 AP |
657 | if (ret) |
658 | goto err; | |
659 | ||
395d00d1 AP |
660 | if (c->symbol_rate <= 3000000) |
661 | u8tmp = 0x20; | |
662 | else if (c->symbol_rate <= 10000000) | |
663 | u8tmp = 0x10; | |
664 | else | |
665 | u8tmp = 0x06; | |
666 | ||
7978b8a1 | 667 | ret = m88ds3103_wr_reg(dev, 0xc3, 0x08); |
395d00d1 AP |
668 | if (ret) |
669 | goto err; | |
670 | ||
7978b8a1 | 671 | ret = m88ds3103_wr_reg(dev, 0xc8, u8tmp); |
395d00d1 AP |
672 | if (ret) |
673 | goto err; | |
674 | ||
7978b8a1 | 675 | ret = m88ds3103_wr_reg(dev, 0xc4, 0x08); |
395d00d1 AP |
676 | if (ret) |
677 | goto err; | |
678 | ||
7978b8a1 | 679 | ret = m88ds3103_wr_reg(dev, 0xc7, 0x00); |
395d00d1 AP |
680 | if (ret) |
681 | goto err; | |
682 | ||
7978b8a1 | 683 | u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2); |
395d00d1 AP |
684 | buf[0] = (u16tmp >> 0) & 0xff; |
685 | buf[1] = (u16tmp >> 8) & 0xff; | |
7978b8a1 | 686 | ret = m88ds3103_wr_regs(dev, 0x61, buf, 2); |
395d00d1 AP |
687 | if (ret) |
688 | goto err; | |
689 | ||
7978b8a1 | 690 | ret = m88ds3103_wr_reg_mask(dev, 0x4d, dev->cfg->spec_inv << 1, 0x02); |
395d00d1 AP |
691 | if (ret) |
692 | goto err; | |
693 | ||
7978b8a1 | 694 | ret = m88ds3103_wr_reg_mask(dev, 0x30, dev->cfg->agc_inv << 4, 0x10); |
395d00d1 AP |
695 | if (ret) |
696 | goto err; | |
697 | ||
7978b8a1 | 698 | ret = m88ds3103_wr_reg(dev, 0x33, dev->cfg->agc); |
395d00d1 AP |
699 | if (ret) |
700 | goto err; | |
701 | ||
7978b8a1 AP |
702 | dev_dbg(&client->dev, "carrier offset=%d\n", |
703 | (tuner_frequency - c->frequency)); | |
395d00d1 AP |
704 | |
705 | s32tmp = 0x10000 * (tuner_frequency - c->frequency); | |
7978b8a1 | 706 | s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz); |
395d00d1 AP |
707 | if (s32tmp < 0) |
708 | s32tmp += 0x10000; | |
709 | ||
710 | buf[0] = (s32tmp >> 0) & 0xff; | |
711 | buf[1] = (s32tmp >> 8) & 0xff; | |
7978b8a1 | 712 | ret = m88ds3103_wr_regs(dev, 0x5e, buf, 2); |
395d00d1 AP |
713 | if (ret) |
714 | goto err; | |
715 | ||
7978b8a1 | 716 | ret = m88ds3103_wr_reg(dev, 0x00, 0x00); |
395d00d1 AP |
717 | if (ret) |
718 | goto err; | |
719 | ||
7978b8a1 | 720 | ret = m88ds3103_wr_reg(dev, 0xb2, 0x00); |
395d00d1 AP |
721 | if (ret) |
722 | goto err; | |
723 | ||
7978b8a1 | 724 | dev->delivery_system = c->delivery_system; |
395d00d1 AP |
725 | |
726 | return 0; | |
727 | err: | |
7978b8a1 | 728 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
729 | return ret; |
730 | } | |
731 | ||
732 | static int m88ds3103_init(struct dvb_frontend *fe) | |
733 | { | |
7978b8a1 AP |
734 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
735 | struct i2c_client *client = dev->client; | |
c1daf651 | 736 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
395d00d1 AP |
737 | int ret, len, remaining; |
738 | const struct firmware *fw = NULL; | |
f4df95bc | 739 | u8 *fw_file; |
395d00d1 | 740 | u8 u8tmp; |
41b9aa00 | 741 | |
7978b8a1 | 742 | dev_dbg(&client->dev, "\n"); |
395d00d1 AP |
743 | |
744 | /* set cold state by default */ | |
7978b8a1 | 745 | dev->warm = false; |
395d00d1 AP |
746 | |
747 | /* wake up device from sleep */ | |
7978b8a1 | 748 | ret = m88ds3103_wr_reg_mask(dev, 0x08, 0x01, 0x01); |
395d00d1 AP |
749 | if (ret) |
750 | goto err; | |
751 | ||
7978b8a1 | 752 | ret = m88ds3103_wr_reg_mask(dev, 0x04, 0x00, 0x01); |
395d00d1 AP |
753 | if (ret) |
754 | goto err; | |
755 | ||
7978b8a1 | 756 | ret = m88ds3103_wr_reg_mask(dev, 0x23, 0x00, 0x10); |
395d00d1 AP |
757 | if (ret) |
758 | goto err; | |
759 | ||
395d00d1 | 760 | /* firmware status */ |
7978b8a1 | 761 | ret = m88ds3103_rd_reg(dev, 0xb9, &u8tmp); |
395d00d1 AP |
762 | if (ret) |
763 | goto err; | |
764 | ||
7978b8a1 | 765 | dev_dbg(&client->dev, "firmware=%02x\n", u8tmp); |
395d00d1 AP |
766 | |
767 | if (u8tmp) | |
768 | goto skip_fw_download; | |
769 | ||
f4df95bc | 770 | /* global reset, global diseqc reset, golbal fec reset */ |
7978b8a1 | 771 | ret = m88ds3103_wr_reg(dev, 0x07, 0xe0); |
f4df95bc | 772 | if (ret) |
773 | goto err; | |
774 | ||
7978b8a1 | 775 | ret = m88ds3103_wr_reg(dev, 0x07, 0x00); |
f4df95bc | 776 | if (ret) |
777 | goto err; | |
778 | ||
395d00d1 | 779 | /* cold state - try to download firmware */ |
7978b8a1 AP |
780 | dev_info(&client->dev, "found a '%s' in cold state\n", |
781 | m88ds3103_ops.info.name); | |
395d00d1 | 782 | |
7978b8a1 | 783 | if (dev->chip_id == M88RS6000_CHIP_ID) |
f4df95bc | 784 | fw_file = M88RS6000_FIRMWARE; |
785 | else | |
786 | fw_file = M88DS3103_FIRMWARE; | |
395d00d1 | 787 | /* request the firmware, this will block and timeout */ |
7978b8a1 | 788 | ret = request_firmware(&fw, fw_file, &client->dev); |
395d00d1 | 789 | if (ret) { |
7978b8a1 | 790 | dev_err(&client->dev, "firmare file '%s' not found\n", fw_file); |
395d00d1 AP |
791 | goto err; |
792 | } | |
793 | ||
7978b8a1 AP |
794 | dev_info(&client->dev, "downloading firmware from file '%s'\n", |
795 | fw_file); | |
395d00d1 | 796 | |
7978b8a1 | 797 | ret = m88ds3103_wr_reg(dev, 0xb2, 0x01); |
395d00d1 | 798 | if (ret) |
5ed0cf88 | 799 | goto error_fw_release; |
395d00d1 AP |
800 | |
801 | for (remaining = fw->size; remaining > 0; | |
7978b8a1 | 802 | remaining -= (dev->cfg->i2c_wr_max - 1)) { |
395d00d1 | 803 | len = remaining; |
7978b8a1 AP |
804 | if (len > (dev->cfg->i2c_wr_max - 1)) |
805 | len = (dev->cfg->i2c_wr_max - 1); | |
395d00d1 | 806 | |
7978b8a1 | 807 | ret = m88ds3103_wr_regs(dev, 0xb0, |
395d00d1 AP |
808 | &fw->data[fw->size - remaining], len); |
809 | if (ret) { | |
7978b8a1 AP |
810 | dev_err(&client->dev, "firmware download failed=%d\n", |
811 | ret); | |
5ed0cf88 | 812 | goto error_fw_release; |
395d00d1 AP |
813 | } |
814 | } | |
815 | ||
7978b8a1 | 816 | ret = m88ds3103_wr_reg(dev, 0xb2, 0x00); |
395d00d1 | 817 | if (ret) |
5ed0cf88 | 818 | goto error_fw_release; |
395d00d1 AP |
819 | |
820 | release_firmware(fw); | |
821 | fw = NULL; | |
822 | ||
7978b8a1 | 823 | ret = m88ds3103_rd_reg(dev, 0xb9, &u8tmp); |
395d00d1 AP |
824 | if (ret) |
825 | goto err; | |
826 | ||
827 | if (!u8tmp) { | |
7978b8a1 | 828 | dev_info(&client->dev, "firmware did not run\n"); |
395d00d1 AP |
829 | ret = -EFAULT; |
830 | goto err; | |
831 | } | |
832 | ||
7978b8a1 AP |
833 | dev_info(&client->dev, "found a '%s' in warm state\n", |
834 | m88ds3103_ops.info.name); | |
835 | dev_info(&client->dev, "firmware version: %X.%X\n", | |
836 | (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf)); | |
395d00d1 AP |
837 | |
838 | skip_fw_download: | |
839 | /* warm state */ | |
7978b8a1 AP |
840 | dev->warm = true; |
841 | ||
c1daf651 AP |
842 | /* init stats here in order signal app which stats are supported */ |
843 | c->cnr.len = 1; | |
844 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
ce80d713 AP |
845 | c->post_bit_error.len = 1; |
846 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
847 | c->post_bit_count.len = 1; | |
848 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
395d00d1 | 849 | |
7978b8a1 | 850 | return 0; |
5ed0cf88 ME |
851 | error_fw_release: |
852 | release_firmware(fw); | |
853 | err: | |
7978b8a1 | 854 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
855 | return ret; |
856 | } | |
857 | ||
858 | static int m88ds3103_sleep(struct dvb_frontend *fe) | |
859 | { | |
7978b8a1 AP |
860 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
861 | struct i2c_client *client = dev->client; | |
395d00d1 | 862 | int ret; |
f4df95bc | 863 | u8 u8tmp; |
41b9aa00 | 864 | |
7978b8a1 | 865 | dev_dbg(&client->dev, "\n"); |
395d00d1 | 866 | |
7978b8a1 AP |
867 | dev->fe_status = 0; |
868 | dev->delivery_system = SYS_UNDEFINED; | |
395d00d1 AP |
869 | |
870 | /* TS Hi-Z */ | |
7978b8a1 | 871 | if (dev->chip_id == M88RS6000_CHIP_ID) |
f4df95bc | 872 | u8tmp = 0x29; |
873 | else | |
874 | u8tmp = 0x27; | |
7978b8a1 | 875 | ret = m88ds3103_wr_reg_mask(dev, u8tmp, 0x00, 0x01); |
395d00d1 AP |
876 | if (ret) |
877 | goto err; | |
878 | ||
879 | /* sleep */ | |
7978b8a1 | 880 | ret = m88ds3103_wr_reg_mask(dev, 0x08, 0x00, 0x01); |
395d00d1 AP |
881 | if (ret) |
882 | goto err; | |
883 | ||
7978b8a1 | 884 | ret = m88ds3103_wr_reg_mask(dev, 0x04, 0x01, 0x01); |
395d00d1 AP |
885 | if (ret) |
886 | goto err; | |
887 | ||
7978b8a1 | 888 | ret = m88ds3103_wr_reg_mask(dev, 0x23, 0x10, 0x10); |
395d00d1 AP |
889 | if (ret) |
890 | goto err; | |
891 | ||
892 | return 0; | |
893 | err: | |
7978b8a1 | 894 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
895 | return ret; |
896 | } | |
897 | ||
898 | static int m88ds3103_get_frontend(struct dvb_frontend *fe) | |
899 | { | |
7978b8a1 AP |
900 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
901 | struct i2c_client *client = dev->client; | |
395d00d1 AP |
902 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
903 | int ret; | |
904 | u8 buf[3]; | |
41b9aa00 | 905 | |
7978b8a1 | 906 | dev_dbg(&client->dev, "\n"); |
395d00d1 | 907 | |
7978b8a1 | 908 | if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) { |
9240c384 | 909 | ret = 0; |
395d00d1 AP |
910 | goto err; |
911 | } | |
912 | ||
913 | switch (c->delivery_system) { | |
914 | case SYS_DVBS: | |
7978b8a1 | 915 | ret = m88ds3103_rd_reg(dev, 0xe0, &buf[0]); |
395d00d1 AP |
916 | if (ret) |
917 | goto err; | |
918 | ||
7978b8a1 | 919 | ret = m88ds3103_rd_reg(dev, 0xe6, &buf[1]); |
395d00d1 AP |
920 | if (ret) |
921 | goto err; | |
922 | ||
923 | switch ((buf[0] >> 2) & 0x01) { | |
924 | case 0: | |
925 | c->inversion = INVERSION_OFF; | |
926 | break; | |
927 | case 1: | |
928 | c->inversion = INVERSION_ON; | |
929 | break; | |
395d00d1 AP |
930 | } |
931 | ||
932 | switch ((buf[1] >> 5) & 0x07) { | |
933 | case 0: | |
934 | c->fec_inner = FEC_7_8; | |
935 | break; | |
936 | case 1: | |
937 | c->fec_inner = FEC_5_6; | |
938 | break; | |
939 | case 2: | |
940 | c->fec_inner = FEC_3_4; | |
941 | break; | |
942 | case 3: | |
943 | c->fec_inner = FEC_2_3; | |
944 | break; | |
945 | case 4: | |
946 | c->fec_inner = FEC_1_2; | |
947 | break; | |
948 | default: | |
7978b8a1 | 949 | dev_dbg(&client->dev, "invalid fec_inner\n"); |
395d00d1 AP |
950 | } |
951 | ||
952 | c->modulation = QPSK; | |
953 | ||
954 | break; | |
955 | case SYS_DVBS2: | |
7978b8a1 | 956 | ret = m88ds3103_rd_reg(dev, 0x7e, &buf[0]); |
395d00d1 AP |
957 | if (ret) |
958 | goto err; | |
959 | ||
7978b8a1 | 960 | ret = m88ds3103_rd_reg(dev, 0x89, &buf[1]); |
395d00d1 AP |
961 | if (ret) |
962 | goto err; | |
963 | ||
7978b8a1 | 964 | ret = m88ds3103_rd_reg(dev, 0xf2, &buf[2]); |
395d00d1 AP |
965 | if (ret) |
966 | goto err; | |
967 | ||
968 | switch ((buf[0] >> 0) & 0x0f) { | |
969 | case 2: | |
970 | c->fec_inner = FEC_2_5; | |
971 | break; | |
972 | case 3: | |
973 | c->fec_inner = FEC_1_2; | |
974 | break; | |
975 | case 4: | |
976 | c->fec_inner = FEC_3_5; | |
977 | break; | |
978 | case 5: | |
979 | c->fec_inner = FEC_2_3; | |
980 | break; | |
981 | case 6: | |
982 | c->fec_inner = FEC_3_4; | |
983 | break; | |
984 | case 7: | |
985 | c->fec_inner = FEC_4_5; | |
986 | break; | |
987 | case 8: | |
988 | c->fec_inner = FEC_5_6; | |
989 | break; | |
990 | case 9: | |
991 | c->fec_inner = FEC_8_9; | |
992 | break; | |
993 | case 10: | |
994 | c->fec_inner = FEC_9_10; | |
995 | break; | |
996 | default: | |
7978b8a1 | 997 | dev_dbg(&client->dev, "invalid fec_inner\n"); |
395d00d1 AP |
998 | } |
999 | ||
1000 | switch ((buf[0] >> 5) & 0x01) { | |
1001 | case 0: | |
1002 | c->pilot = PILOT_OFF; | |
1003 | break; | |
1004 | case 1: | |
1005 | c->pilot = PILOT_ON; | |
1006 | break; | |
395d00d1 AP |
1007 | } |
1008 | ||
1009 | switch ((buf[0] >> 6) & 0x07) { | |
1010 | case 0: | |
1011 | c->modulation = QPSK; | |
1012 | break; | |
1013 | case 1: | |
1014 | c->modulation = PSK_8; | |
1015 | break; | |
1016 | case 2: | |
1017 | c->modulation = APSK_16; | |
1018 | break; | |
1019 | case 3: | |
1020 | c->modulation = APSK_32; | |
1021 | break; | |
1022 | default: | |
7978b8a1 | 1023 | dev_dbg(&client->dev, "invalid modulation\n"); |
395d00d1 AP |
1024 | } |
1025 | ||
1026 | switch ((buf[1] >> 7) & 0x01) { | |
1027 | case 0: | |
1028 | c->inversion = INVERSION_OFF; | |
1029 | break; | |
1030 | case 1: | |
1031 | c->inversion = INVERSION_ON; | |
1032 | break; | |
395d00d1 AP |
1033 | } |
1034 | ||
1035 | switch ((buf[2] >> 0) & 0x03) { | |
1036 | case 0: | |
1037 | c->rolloff = ROLLOFF_35; | |
1038 | break; | |
1039 | case 1: | |
1040 | c->rolloff = ROLLOFF_25; | |
1041 | break; | |
1042 | case 2: | |
1043 | c->rolloff = ROLLOFF_20; | |
1044 | break; | |
1045 | default: | |
7978b8a1 | 1046 | dev_dbg(&client->dev, "invalid rolloff\n"); |
395d00d1 AP |
1047 | } |
1048 | break; | |
1049 | default: | |
7978b8a1 | 1050 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
395d00d1 AP |
1051 | ret = -EINVAL; |
1052 | goto err; | |
1053 | } | |
1054 | ||
7978b8a1 | 1055 | ret = m88ds3103_rd_regs(dev, 0x6d, buf, 2); |
395d00d1 AP |
1056 | if (ret) |
1057 | goto err; | |
1058 | ||
1059 | c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) * | |
7978b8a1 | 1060 | dev->mclk_khz * 1000 / 0x10000; |
395d00d1 AP |
1061 | |
1062 | return 0; | |
1063 | err: | |
7978b8a1 | 1064 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1065 | return ret; |
1066 | } | |
1067 | ||
1068 | static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) | |
1069 | { | |
395d00d1 | 1070 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
41b9aa00 | 1071 | |
c1daf651 AP |
1072 | if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) |
1073 | *snr = div_s64(c->cnr.stat[0].svalue, 100); | |
1074 | else | |
1075 | *snr = 0; | |
395d00d1 AP |
1076 | |
1077 | return 0; | |
395d00d1 AP |
1078 | } |
1079 | ||
4423a2ba AP |
1080 | static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber) |
1081 | { | |
7978b8a1 | 1082 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
41b9aa00 | 1083 | |
7978b8a1 | 1084 | *ber = dev->dvbv3_ber; |
4423a2ba AP |
1085 | |
1086 | return 0; | |
4423a2ba | 1087 | } |
395d00d1 AP |
1088 | |
1089 | static int m88ds3103_set_tone(struct dvb_frontend *fe, | |
0df289a2 | 1090 | enum fe_sec_tone_mode fe_sec_tone_mode) |
395d00d1 | 1091 | { |
7978b8a1 AP |
1092 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1093 | struct i2c_client *client = dev->client; | |
395d00d1 AP |
1094 | int ret; |
1095 | u8 u8tmp, tone, reg_a1_mask; | |
41b9aa00 | 1096 | |
7978b8a1 | 1097 | dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode); |
395d00d1 | 1098 | |
7978b8a1 | 1099 | if (!dev->warm) { |
395d00d1 AP |
1100 | ret = -EAGAIN; |
1101 | goto err; | |
1102 | } | |
1103 | ||
1104 | switch (fe_sec_tone_mode) { | |
1105 | case SEC_TONE_ON: | |
1106 | tone = 0; | |
418a97cb | 1107 | reg_a1_mask = 0x47; |
395d00d1 AP |
1108 | break; |
1109 | case SEC_TONE_OFF: | |
1110 | tone = 1; | |
1111 | reg_a1_mask = 0x00; | |
1112 | break; | |
1113 | default: | |
7978b8a1 | 1114 | dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n"); |
395d00d1 AP |
1115 | ret = -EINVAL; |
1116 | goto err; | |
1117 | } | |
1118 | ||
7978b8a1 AP |
1119 | u8tmp = tone << 7 | dev->cfg->envelope_mode << 5; |
1120 | ret = m88ds3103_wr_reg_mask(dev, 0xa2, u8tmp, 0xe0); | |
395d00d1 AP |
1121 | if (ret) |
1122 | goto err; | |
1123 | ||
1124 | u8tmp = 1 << 2; | |
7978b8a1 | 1125 | ret = m88ds3103_wr_reg_mask(dev, 0xa1, u8tmp, reg_a1_mask); |
395d00d1 AP |
1126 | if (ret) |
1127 | goto err; | |
1128 | ||
1129 | return 0; | |
1130 | err: | |
7978b8a1 | 1131 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1132 | return ret; |
1133 | } | |
1134 | ||
79d09330 | 1135 | static int m88ds3103_set_voltage(struct dvb_frontend *fe, |
0df289a2 | 1136 | enum fe_sec_voltage fe_sec_voltage) |
79d09330 | 1137 | { |
7978b8a1 AP |
1138 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1139 | struct i2c_client *client = dev->client; | |
d28677ff AP |
1140 | int ret; |
1141 | u8 u8tmp; | |
1142 | bool voltage_sel, voltage_dis; | |
79d09330 | 1143 | |
7978b8a1 | 1144 | dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage); |
79d09330 | 1145 | |
7978b8a1 | 1146 | if (!dev->warm) { |
d28677ff AP |
1147 | ret = -EAGAIN; |
1148 | goto err; | |
1149 | } | |
79d09330 | 1150 | |
d28677ff | 1151 | switch (fe_sec_voltage) { |
79d09330 | 1152 | case SEC_VOLTAGE_18: |
afbd6eb4 MCC |
1153 | voltage_sel = true; |
1154 | voltage_dis = false; | |
79d09330 | 1155 | break; |
1156 | case SEC_VOLTAGE_13: | |
afbd6eb4 MCC |
1157 | voltage_sel = false; |
1158 | voltage_dis = false; | |
79d09330 | 1159 | break; |
1160 | case SEC_VOLTAGE_OFF: | |
afbd6eb4 MCC |
1161 | voltage_sel = false; |
1162 | voltage_dis = true; | |
79d09330 | 1163 | break; |
d28677ff | 1164 | default: |
7978b8a1 | 1165 | dev_dbg(&client->dev, "invalid fe_sec_voltage\n"); |
d28677ff AP |
1166 | ret = -EINVAL; |
1167 | goto err; | |
79d09330 | 1168 | } |
d28677ff AP |
1169 | |
1170 | /* output pin polarity */ | |
7978b8a1 AP |
1171 | voltage_sel ^= dev->cfg->lnb_hv_pol; |
1172 | voltage_dis ^= dev->cfg->lnb_en_pol; | |
d28677ff AP |
1173 | |
1174 | u8tmp = voltage_dis << 1 | voltage_sel << 0; | |
7978b8a1 | 1175 | ret = m88ds3103_wr_reg_mask(dev, 0xa2, u8tmp, 0x03); |
d28677ff AP |
1176 | if (ret) |
1177 | goto err; | |
79d09330 | 1178 | |
1179 | return 0; | |
d28677ff | 1180 | err: |
7978b8a1 | 1181 | dev_dbg(&client->dev, "failed=%d\n", ret); |
d28677ff | 1182 | return ret; |
79d09330 | 1183 | } |
1184 | ||
395d00d1 AP |
1185 | static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, |
1186 | struct dvb_diseqc_master_cmd *diseqc_cmd) | |
1187 | { | |
7978b8a1 AP |
1188 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1189 | struct i2c_client *client = dev->client; | |
befa0cc1 AP |
1190 | int ret; |
1191 | unsigned long timeout; | |
395d00d1 | 1192 | u8 u8tmp; |
41b9aa00 | 1193 | |
7978b8a1 AP |
1194 | dev_dbg(&client->dev, "msg=%*ph\n", |
1195 | diseqc_cmd->msg_len, diseqc_cmd->msg); | |
395d00d1 | 1196 | |
7978b8a1 | 1197 | if (!dev->warm) { |
395d00d1 AP |
1198 | ret = -EAGAIN; |
1199 | goto err; | |
1200 | } | |
1201 | ||
1202 | if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { | |
1203 | ret = -EINVAL; | |
1204 | goto err; | |
1205 | } | |
1206 | ||
7978b8a1 AP |
1207 | u8tmp = dev->cfg->envelope_mode << 5; |
1208 | ret = m88ds3103_wr_reg_mask(dev, 0xa2, u8tmp, 0xe0); | |
395d00d1 AP |
1209 | if (ret) |
1210 | goto err; | |
1211 | ||
7978b8a1 | 1212 | ret = m88ds3103_wr_regs(dev, 0xa3, diseqc_cmd->msg, |
395d00d1 AP |
1213 | diseqc_cmd->msg_len); |
1214 | if (ret) | |
1215 | goto err; | |
1216 | ||
7978b8a1 | 1217 | ret = m88ds3103_wr_reg(dev, 0xa1, |
395d00d1 AP |
1218 | (diseqc_cmd->msg_len - 1) << 3 | 0x07); |
1219 | if (ret) | |
1220 | goto err; | |
1221 | ||
395d00d1 | 1222 | /* wait DiSEqC TX ready */ |
befa0cc1 AP |
1223 | #define SEND_MASTER_CMD_TIMEOUT 120 |
1224 | timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT); | |
1225 | ||
1226 | /* DiSEqC message typical period is 54 ms */ | |
1227 | usleep_range(50000, 54000); | |
395d00d1 | 1228 | |
befa0cc1 | 1229 | for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) { |
7978b8a1 | 1230 | ret = m88ds3103_rd_reg_mask(dev, 0xa1, &u8tmp, 0x40); |
395d00d1 AP |
1231 | if (ret) |
1232 | goto err; | |
1233 | } | |
1234 | ||
befa0cc1 | 1235 | if (u8tmp == 0) { |
7978b8a1 | 1236 | dev_dbg(&client->dev, "diseqc tx took %u ms\n", |
befa0cc1 AP |
1237 | jiffies_to_msecs(jiffies) - |
1238 | (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT)); | |
1239 | } else { | |
7978b8a1 | 1240 | dev_dbg(&client->dev, "diseqc tx timeout\n"); |
395d00d1 | 1241 | |
7978b8a1 | 1242 | ret = m88ds3103_wr_reg_mask(dev, 0xa1, 0x40, 0xc0); |
395d00d1 AP |
1243 | if (ret) |
1244 | goto err; | |
1245 | } | |
1246 | ||
7978b8a1 | 1247 | ret = m88ds3103_wr_reg_mask(dev, 0xa2, 0x80, 0xc0); |
395d00d1 AP |
1248 | if (ret) |
1249 | goto err; | |
1250 | ||
befa0cc1 | 1251 | if (u8tmp == 1) { |
395d00d1 AP |
1252 | ret = -ETIMEDOUT; |
1253 | goto err; | |
1254 | } | |
1255 | ||
1256 | return 0; | |
1257 | err: | |
7978b8a1 | 1258 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1259 | return ret; |
1260 | } | |
1261 | ||
1262 | static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, | |
0df289a2 | 1263 | enum fe_sec_mini_cmd fe_sec_mini_cmd) |
395d00d1 | 1264 | { |
7978b8a1 AP |
1265 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1266 | struct i2c_client *client = dev->client; | |
befa0cc1 AP |
1267 | int ret; |
1268 | unsigned long timeout; | |
395d00d1 | 1269 | u8 u8tmp, burst; |
41b9aa00 | 1270 | |
7978b8a1 | 1271 | dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd); |
395d00d1 | 1272 | |
7978b8a1 | 1273 | if (!dev->warm) { |
395d00d1 AP |
1274 | ret = -EAGAIN; |
1275 | goto err; | |
1276 | } | |
1277 | ||
7978b8a1 AP |
1278 | u8tmp = dev->cfg->envelope_mode << 5; |
1279 | ret = m88ds3103_wr_reg_mask(dev, 0xa2, u8tmp, 0xe0); | |
395d00d1 AP |
1280 | if (ret) |
1281 | goto err; | |
1282 | ||
1283 | switch (fe_sec_mini_cmd) { | |
1284 | case SEC_MINI_A: | |
1285 | burst = 0x02; | |
1286 | break; | |
1287 | case SEC_MINI_B: | |
1288 | burst = 0x01; | |
1289 | break; | |
1290 | default: | |
7978b8a1 | 1291 | dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n"); |
395d00d1 AP |
1292 | ret = -EINVAL; |
1293 | goto err; | |
1294 | } | |
1295 | ||
7978b8a1 | 1296 | ret = m88ds3103_wr_reg(dev, 0xa1, burst); |
395d00d1 AP |
1297 | if (ret) |
1298 | goto err; | |
1299 | ||
395d00d1 | 1300 | /* wait DiSEqC TX ready */ |
befa0cc1 AP |
1301 | #define SEND_BURST_TIMEOUT 40 |
1302 | timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT); | |
1303 | ||
1304 | /* DiSEqC ToneBurst period is 12.5 ms */ | |
1305 | usleep_range(8500, 12500); | |
395d00d1 | 1306 | |
befa0cc1 | 1307 | for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) { |
7978b8a1 | 1308 | ret = m88ds3103_rd_reg_mask(dev, 0xa1, &u8tmp, 0x40); |
395d00d1 AP |
1309 | if (ret) |
1310 | goto err; | |
1311 | } | |
1312 | ||
befa0cc1 | 1313 | if (u8tmp == 0) { |
7978b8a1 | 1314 | dev_dbg(&client->dev, "diseqc tx took %u ms\n", |
befa0cc1 AP |
1315 | jiffies_to_msecs(jiffies) - |
1316 | (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT)); | |
1317 | } else { | |
7978b8a1 | 1318 | dev_dbg(&client->dev, "diseqc tx timeout\n"); |
befa0cc1 | 1319 | |
7978b8a1 | 1320 | ret = m88ds3103_wr_reg_mask(dev, 0xa1, 0x40, 0xc0); |
befa0cc1 AP |
1321 | if (ret) |
1322 | goto err; | |
1323 | } | |
395d00d1 | 1324 | |
7978b8a1 | 1325 | ret = m88ds3103_wr_reg_mask(dev, 0xa2, 0x80, 0xc0); |
395d00d1 AP |
1326 | if (ret) |
1327 | goto err; | |
1328 | ||
befa0cc1 | 1329 | if (u8tmp == 1) { |
395d00d1 AP |
1330 | ret = -ETIMEDOUT; |
1331 | goto err; | |
1332 | } | |
1333 | ||
1334 | return 0; | |
1335 | err: | |
7978b8a1 | 1336 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1337 | return ret; |
1338 | } | |
1339 | ||
1340 | static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, | |
1341 | struct dvb_frontend_tune_settings *s) | |
1342 | { | |
1343 | s->min_delay_ms = 3000; | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
44b9055b | 1348 | static void m88ds3103_release(struct dvb_frontend *fe) |
395d00d1 | 1349 | { |
7978b8a1 AP |
1350 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1351 | struct i2c_client *client = dev->client; | |
41b9aa00 | 1352 | |
f01919e8 | 1353 | i2c_unregister_device(client); |
395d00d1 AP |
1354 | } |
1355 | ||
44b9055b | 1356 | static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) |
395d00d1 | 1357 | { |
7978b8a1 AP |
1358 | struct m88ds3103_dev *dev = mux_priv; |
1359 | struct i2c_client *client = dev->client; | |
395d00d1 AP |
1360 | int ret; |
1361 | struct i2c_msg gate_open_msg[1] = { | |
1362 | { | |
7978b8a1 | 1363 | .addr = client->addr, |
395d00d1 AP |
1364 | .flags = 0, |
1365 | .len = 2, | |
1366 | .buf = "\x03\x11", | |
1367 | } | |
1368 | }; | |
395d00d1 | 1369 | |
7978b8a1 | 1370 | mutex_lock(&dev->i2c_mutex); |
395d00d1 | 1371 | |
44b9055b | 1372 | /* open tuner I2C repeater for 1 xfer, closes automatically */ |
7978b8a1 | 1373 | ret = __i2c_transfer(client->adapter, gate_open_msg, 1); |
395d00d1 | 1374 | if (ret != 1) { |
7978b8a1 | 1375 | dev_warn(&client->dev, "i2c wr failed=%d\n", ret); |
44b9055b AP |
1376 | if (ret >= 0) |
1377 | ret = -EREMOTEIO; | |
395d00d1 | 1378 | |
44b9055b AP |
1379 | return ret; |
1380 | } | |
395d00d1 | 1381 | |
44b9055b | 1382 | return 0; |
395d00d1 AP |
1383 | } |
1384 | ||
44b9055b AP |
1385 | static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv, |
1386 | u32 chan) | |
395d00d1 | 1387 | { |
7978b8a1 | 1388 | struct m88ds3103_dev *dev = mux_priv; |
44b9055b | 1389 | |
7978b8a1 | 1390 | mutex_unlock(&dev->i2c_mutex); |
44b9055b AP |
1391 | |
1392 | return 0; | |
395d00d1 AP |
1393 | } |
1394 | ||
f01919e8 AP |
1395 | /* |
1396 | * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide | |
1397 | * proper I2C client for legacy media attach binding. | |
1398 | * New users must use I2C client binding directly! | |
1399 | */ | |
395d00d1 AP |
1400 | struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, |
1401 | struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) | |
1402 | { | |
f01919e8 AP |
1403 | struct i2c_client *client; |
1404 | struct i2c_board_info board_info; | |
1405 | struct m88ds3103_platform_data pdata; | |
1406 | ||
1407 | pdata.clk = cfg->clock; | |
1408 | pdata.i2c_wr_max = cfg->i2c_wr_max; | |
1409 | pdata.ts_mode = cfg->ts_mode; | |
1410 | pdata.ts_clk = cfg->ts_clk; | |
1411 | pdata.ts_clk_pol = cfg->ts_clk_pol; | |
1412 | pdata.spec_inv = cfg->spec_inv; | |
1413 | pdata.agc = cfg->agc; | |
1414 | pdata.agc_inv = cfg->agc_inv; | |
1415 | pdata.clk_out = cfg->clock_out; | |
1416 | pdata.envelope_mode = cfg->envelope_mode; | |
1417 | pdata.lnb_hv_pol = cfg->lnb_hv_pol; | |
1418 | pdata.lnb_en_pol = cfg->lnb_en_pol; | |
1419 | pdata.attach_in_use = true; | |
1420 | ||
1421 | memset(&board_info, 0, sizeof(board_info)); | |
1422 | strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE); | |
1423 | board_info.addr = cfg->i2c_addr; | |
1424 | board_info.platform_data = &pdata; | |
1425 | client = i2c_new_device(i2c, &board_info); | |
1426 | if (!client || !client->dev.driver) | |
1427 | return NULL; | |
1428 | ||
1429 | *tuner_i2c_adapter = pdata.get_i2c_adapter(client); | |
1430 | return pdata.get_dvb_frontend(client); | |
1431 | } | |
1432 | EXPORT_SYMBOL(m88ds3103_attach); | |
1433 | ||
1434 | static struct dvb_frontend_ops m88ds3103_ops = { | |
7978b8a1 | 1435 | .delsys = {SYS_DVBS, SYS_DVBS2}, |
f01919e8 | 1436 | .info = { |
7978b8a1 | 1437 | .name = "Montage Technology M88DS3103", |
f01919e8 AP |
1438 | .frequency_min = 950000, |
1439 | .frequency_max = 2150000, | |
1440 | .frequency_tolerance = 5000, | |
1441 | .symbol_rate_min = 1000000, | |
1442 | .symbol_rate_max = 45000000, | |
1443 | .caps = FE_CAN_INVERSION_AUTO | | |
1444 | FE_CAN_FEC_1_2 | | |
1445 | FE_CAN_FEC_2_3 | | |
1446 | FE_CAN_FEC_3_4 | | |
1447 | FE_CAN_FEC_4_5 | | |
1448 | FE_CAN_FEC_5_6 | | |
1449 | FE_CAN_FEC_6_7 | | |
1450 | FE_CAN_FEC_7_8 | | |
1451 | FE_CAN_FEC_8_9 | | |
1452 | FE_CAN_FEC_AUTO | | |
1453 | FE_CAN_QPSK | | |
1454 | FE_CAN_RECOVER | | |
1455 | FE_CAN_2G_MODULATION | |
1456 | }, | |
1457 | ||
1458 | .release = m88ds3103_release, | |
1459 | ||
1460 | .get_tune_settings = m88ds3103_get_tune_settings, | |
1461 | ||
1462 | .init = m88ds3103_init, | |
1463 | .sleep = m88ds3103_sleep, | |
1464 | ||
1465 | .set_frontend = m88ds3103_set_frontend, | |
1466 | .get_frontend = m88ds3103_get_frontend, | |
1467 | ||
1468 | .read_status = m88ds3103_read_status, | |
1469 | .read_snr = m88ds3103_read_snr, | |
1470 | .read_ber = m88ds3103_read_ber, | |
1471 | ||
1472 | .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, | |
1473 | .diseqc_send_burst = m88ds3103_diseqc_send_burst, | |
1474 | ||
1475 | .set_tone = m88ds3103_set_tone, | |
1476 | .set_voltage = m88ds3103_set_voltage, | |
1477 | }; | |
1478 | ||
1479 | static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client) | |
1480 | { | |
7978b8a1 | 1481 | struct m88ds3103_dev *dev = i2c_get_clientdata(client); |
f01919e8 AP |
1482 | |
1483 | dev_dbg(&client->dev, "\n"); | |
1484 | ||
1485 | return &dev->fe; | |
1486 | } | |
1487 | ||
1488 | static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client) | |
1489 | { | |
7978b8a1 | 1490 | struct m88ds3103_dev *dev = i2c_get_clientdata(client); |
f01919e8 AP |
1491 | |
1492 | dev_dbg(&client->dev, "\n"); | |
1493 | ||
1494 | return dev->i2c_adapter; | |
1495 | } | |
1496 | ||
1497 | static int m88ds3103_probe(struct i2c_client *client, | |
1498 | const struct i2c_device_id *id) | |
1499 | { | |
7978b8a1 | 1500 | struct m88ds3103_dev *dev; |
f01919e8 | 1501 | struct m88ds3103_platform_data *pdata = client->dev.platform_data; |
395d00d1 | 1502 | int ret; |
395d00d1 AP |
1503 | u8 chip_id, u8tmp; |
1504 | ||
f01919e8 AP |
1505 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1506 | if (!dev) { | |
395d00d1 | 1507 | ret = -ENOMEM; |
395d00d1 AP |
1508 | goto err; |
1509 | } | |
1510 | ||
f01919e8 | 1511 | dev->client = client; |
f01919e8 AP |
1512 | dev->config.clock = pdata->clk; |
1513 | dev->config.i2c_wr_max = pdata->i2c_wr_max; | |
1514 | dev->config.ts_mode = pdata->ts_mode; | |
1515 | dev->config.ts_clk = pdata->ts_clk; | |
1516 | dev->config.ts_clk_pol = pdata->ts_clk_pol; | |
1517 | dev->config.spec_inv = pdata->spec_inv; | |
1518 | dev->config.agc_inv = pdata->agc_inv; | |
1519 | dev->config.clock_out = pdata->clk_out; | |
1520 | dev->config.envelope_mode = pdata->envelope_mode; | |
1521 | dev->config.agc = pdata->agc; | |
1522 | dev->config.lnb_hv_pol = pdata->lnb_hv_pol; | |
1523 | dev->config.lnb_en_pol = pdata->lnb_en_pol; | |
1524 | dev->cfg = &dev->config; | |
1525 | mutex_init(&dev->i2c_mutex); | |
395d00d1 | 1526 | |
f4df95bc | 1527 | /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */ |
f01919e8 | 1528 | ret = m88ds3103_rd_reg(dev, 0x00, &chip_id); |
395d00d1 | 1529 | if (ret) |
f01919e8 | 1530 | goto err_kfree; |
395d00d1 | 1531 | |
f4df95bc | 1532 | chip_id >>= 1; |
f01919e8 | 1533 | dev_dbg(&client->dev, "chip_id=%02x\n", chip_id); |
395d00d1 AP |
1534 | |
1535 | switch (chip_id) { | |
f4df95bc | 1536 | case M88RS6000_CHIP_ID: |
1537 | case M88DS3103_CHIP_ID: | |
395d00d1 AP |
1538 | break; |
1539 | default: | |
f01919e8 | 1540 | goto err_kfree; |
395d00d1 | 1541 | } |
f01919e8 | 1542 | dev->chip_id = chip_id; |
395d00d1 | 1543 | |
f01919e8 | 1544 | switch (dev->cfg->clock_out) { |
395d00d1 AP |
1545 | case M88DS3103_CLOCK_OUT_DISABLED: |
1546 | u8tmp = 0x80; | |
1547 | break; | |
1548 | case M88DS3103_CLOCK_OUT_ENABLED: | |
1549 | u8tmp = 0x00; | |
1550 | break; | |
1551 | case M88DS3103_CLOCK_OUT_ENABLED_DIV2: | |
1552 | u8tmp = 0x10; | |
1553 | break; | |
1554 | default: | |
4347df6a | 1555 | ret = -EINVAL; |
f01919e8 | 1556 | goto err_kfree; |
395d00d1 AP |
1557 | } |
1558 | ||
f4df95bc | 1559 | /* 0x29 register is defined differently for m88rs6000. */ |
1560 | /* set internal tuner address to 0x21 */ | |
1561 | if (chip_id == M88RS6000_CHIP_ID) | |
1562 | u8tmp = 0x00; | |
1563 | ||
f01919e8 | 1564 | ret = m88ds3103_wr_reg(dev, 0x29, u8tmp); |
395d00d1 | 1565 | if (ret) |
f01919e8 | 1566 | goto err_kfree; |
395d00d1 AP |
1567 | |
1568 | /* sleep */ | |
f01919e8 | 1569 | ret = m88ds3103_wr_reg_mask(dev, 0x08, 0x00, 0x01); |
395d00d1 | 1570 | if (ret) |
f01919e8 AP |
1571 | goto err_kfree; |
1572 | ret = m88ds3103_wr_reg_mask(dev, 0x04, 0x01, 0x01); | |
395d00d1 | 1573 | if (ret) |
f01919e8 AP |
1574 | goto err_kfree; |
1575 | ret = m88ds3103_wr_reg_mask(dev, 0x23, 0x10, 0x10); | |
395d00d1 | 1576 | if (ret) |
f01919e8 | 1577 | goto err_kfree; |
395d00d1 | 1578 | |
44b9055b | 1579 | /* create mux i2c adapter for tuner */ |
f01919e8 AP |
1580 | dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev, |
1581 | dev, 0, 0, 0, m88ds3103_select, | |
1582 | m88ds3103_deselect); | |
4347df6a DC |
1583 | if (dev->i2c_adapter == NULL) { |
1584 | ret = -ENOMEM; | |
f01919e8 | 1585 | goto err_kfree; |
4347df6a | 1586 | } |
44b9055b | 1587 | |
395d00d1 | 1588 | /* create dvb_frontend */ |
f01919e8 AP |
1589 | memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); |
1590 | if (dev->chip_id == M88RS6000_CHIP_ID) | |
7978b8a1 AP |
1591 | strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000", |
1592 | sizeof(dev->fe.ops.info.name)); | |
f01919e8 AP |
1593 | if (!pdata->attach_in_use) |
1594 | dev->fe.ops.release = NULL; | |
1595 | dev->fe.demodulator_priv = dev; | |
1596 | i2c_set_clientdata(client, dev); | |
1597 | ||
1598 | /* setup callbacks */ | |
1599 | pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend; | |
1600 | pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter; | |
1601 | return 0; | |
1602 | err_kfree: | |
1603 | kfree(dev); | |
395d00d1 | 1604 | err: |
f01919e8 AP |
1605 | dev_dbg(&client->dev, "failed=%d\n", ret); |
1606 | return ret; | |
395d00d1 | 1607 | } |
395d00d1 | 1608 | |
f01919e8 AP |
1609 | static int m88ds3103_remove(struct i2c_client *client) |
1610 | { | |
7978b8a1 | 1611 | struct m88ds3103_dev *dev = i2c_get_clientdata(client); |
395d00d1 | 1612 | |
f01919e8 | 1613 | dev_dbg(&client->dev, "\n"); |
395d00d1 | 1614 | |
f01919e8 | 1615 | i2c_del_mux_adapter(dev->i2c_adapter); |
395d00d1 | 1616 | |
f01919e8 AP |
1617 | kfree(dev); |
1618 | return 0; | |
1619 | } | |
395d00d1 | 1620 | |
f01919e8 AP |
1621 | static const struct i2c_device_id m88ds3103_id_table[] = { |
1622 | {"m88ds3103", 0}, | |
1623 | {} | |
1624 | }; | |
1625 | MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table); | |
395d00d1 | 1626 | |
f01919e8 AP |
1627 | static struct i2c_driver m88ds3103_driver = { |
1628 | .driver = { | |
1629 | .owner = THIS_MODULE, | |
1630 | .name = "m88ds3103", | |
1631 | .suppress_bind_attrs = true, | |
1632 | }, | |
1633 | .probe = m88ds3103_probe, | |
1634 | .remove = m88ds3103_remove, | |
1635 | .id_table = m88ds3103_id_table, | |
395d00d1 AP |
1636 | }; |
1637 | ||
f01919e8 AP |
1638 | module_i2c_driver(m88ds3103_driver); |
1639 | ||
395d00d1 | 1640 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); |
7978b8a1 | 1641 | MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver"); |
395d00d1 AP |
1642 | MODULE_LICENSE("GPL"); |
1643 | MODULE_FIRMWARE(M88DS3103_FIRMWARE); | |
f4df95bc | 1644 | MODULE_FIRMWARE(M88RS6000_FIRMWARE); |