[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / m88rs2000.c

/*
	Driver for M88RS2000 demodulator and tuner

	Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
	Beta Driver

	Include various calculation code from DS3000 driver.
	Copyright (C) 2009 Konstantin Dimitrov.

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the Free Software
	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/types.h>


#include "dvb_frontend.h"
#include "m88rs2000.h"

struct m88rs2000_state {
	struct i2c_adapter *i2c;
	const struct m88rs2000_config *config;
	struct dvb_frontend frontend;
	u8 no_lock_count;
	u32 tuner_frequency;
	u32 symbol_rate;
	fe_code_rate_t fec_inner;
	u8 tuner_level;
	int errmode;
};

static int m88rs2000_debug;

module_param_named(debug, m88rs2000_debug, int, 0644);
MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");

#define dprintk(level, args...) do { \
	if (level & m88rs2000_debug) \
		printk(KERN_DEBUG "m88rs2000-fe: " args); \
} while (0)

#define deb_info(args...)  dprintk(0x01, args)
#define info(format, arg...) \
	printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)

static int m88rs2000_writereg(struct m88rs2000_state *state,
	u8 reg, u8 data)
{
	int ret;
	u8 buf[] = { reg, data };
	struct i2c_msg msg = {
		.addr = state->config->demod_addr,
		.flags = 0,
		.buf = buf,
		.len = 2
	};

	ret = i2c_transfer(state->i2c, &msg, 1);

	if (ret != 1)
		deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
			"ret == %i)\n", __func__, reg, data, ret);

	return (ret != 1) ? -EREMOTEIO : 0;
}

static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };

	struct i2c_msg msg[] = {
		{
			.addr = state->config->demod_addr,
			.flags = 0,
			.buf = b0,
			.len = 1
		}, {
			.addr = state->config->demod_addr,
			.flags = I2C_M_RD,
			.buf = b1,
			.len = 1
		}
	};

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2)
		deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
				__func__, reg, ret);

	return b1[0];
}

static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	int ret;
	u32 temp;
	u8 b[3];

	if ((srate < 1000000) || (srate > 45000000))
		return -EINVAL;

	temp = srate / 1000;
	temp *= 11831;
	temp /= 68;
	temp -= 3;

	b[0] = (u8) (temp >> 16) & 0xff;
	b[1] = (u8) (temp >> 8) & 0xff;
	b[2] = (u8) temp & 0xff;
	ret = m88rs2000_writereg(state, 0x93, b[2]);
	ret |= m88rs2000_writereg(state, 0x94, b[1]);
	ret |= m88rs2000_writereg(state, 0x95, b[0]);

	deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
	return ret;
}

static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
				    struct dvb_diseqc_master_cmd *m)
{
	struct m88rs2000_state *state = fe->demodulator_priv;

	int i;
	u8 reg;
	deb_info("%s\n", __func__);
	m88rs2000_writereg(state, 0x9a, 0x30);
	reg = m88rs2000_readreg(state, 0xb2);
	reg &= 0x3f;
	m88rs2000_writereg(state, 0xb2, reg);
	for (i = 0; i <  m->msg_len; i++)
		m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);

	reg = m88rs2000_readreg(state, 0xb1);
	reg &= 0x87;
	reg |= ((m->msg_len - 1) << 3) | 0x07;
	reg &= 0x7f;
	m88rs2000_writereg(state, 0xb1, reg);

	for (i = 0; i < 15; i++) {
		if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
			break;
		msleep(20);
	}

	reg = m88rs2000_readreg(state, 0xb1);
	if ((reg & 0x40) > 0x0) {
		reg &= 0x7f;
		reg |= 0x40;
		m88rs2000_writereg(state, 0xb1, reg);
	}

	reg = m88rs2000_readreg(state, 0xb2);
	reg &= 0x3f;
	reg |= 0x80;
	m88rs2000_writereg(state, 0xb2, reg);
	m88rs2000_writereg(state, 0x9a, 0xb0);


	return 0;
}

static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
						fe_sec_mini_cmd_t burst)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	u8 reg0, reg1;
	deb_info("%s\n", __func__);
	m88rs2000_writereg(state, 0x9a, 0x30);
	msleep(50);
	reg0 = m88rs2000_readreg(state, 0xb1);
	reg1 = m88rs2000_readreg(state, 0xb2);
	/* TODO complete this section */
	m88rs2000_writereg(state, 0xb2, reg1);
	m88rs2000_writereg(state, 0xb1, reg0);
	m88rs2000_writereg(state, 0x9a, 0xb0);

	return 0;
}

static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	u8 reg0, reg1;
	m88rs2000_writereg(state, 0x9a, 0x30);
	reg0 = m88rs2000_readreg(state, 0xb1);
	reg1 = m88rs2000_readreg(state, 0xb2);

	reg1 &= 0x3f;

	switch (tone) {
	case SEC_TONE_ON:
		reg0 |= 0x4;
		reg0 &= 0xbc;
		break;
	case SEC_TONE_OFF:
		reg1 |= 0x80;
		break;
	default:
		break;
	}
	m88rs2000_writereg(state, 0xb2, reg1);
	m88rs2000_writereg(state, 0xb1, reg0);
	m88rs2000_writereg(state, 0x9a, 0xb0);
	return 0;
}

struct inittab {
	u8 cmd;
	u8 reg;
	u8 val;
};

struct inittab m88rs2000_setup[] = {
	{DEMOD_WRITE, 0x9a, 0x30},
	{DEMOD_WRITE, 0x00, 0x01},
	{WRITE_DELAY, 0x19, 0x00},
	{DEMOD_WRITE, 0x00, 0x00},
	{DEMOD_WRITE, 0x9a, 0xb0},
	{DEMOD_WRITE, 0x81, 0xc1},
	{DEMOD_WRITE, 0x81, 0x81},
	{DEMOD_WRITE, 0x86, 0xc6},
	{DEMOD_WRITE, 0x9a, 0x30},
	{DEMOD_WRITE, 0xf0, 0x22},
	{DEMOD_WRITE, 0xf1, 0xbf},
	{DEMOD_WRITE, 0xb0, 0x45},
	{DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
	{DEMOD_WRITE, 0x9a, 0xb0},
	{0xff, 0xaa, 0xff}
};

struct inittab m88rs2000_shutdown[] = {
	{DEMOD_WRITE, 0x9a, 0x30},
	{DEMOD_WRITE, 0xb0, 0x00},
	{DEMOD_WRITE, 0xf1, 0x89},
	{DEMOD_WRITE, 0x00, 0x01},
	{DEMOD_WRITE, 0x9a, 0xb0},
	{DEMOD_WRITE, 0x81, 0x81},
	{0xff, 0xaa, 0xff}
};

struct inittab fe_reset[] = {
	{DEMOD_WRITE, 0x00, 0x01},
	{DEMOD_WRITE, 0xf1, 0xbf},
	{DEMOD_WRITE, 0x00, 0x01},
	{DEMOD_WRITE, 0x20, 0x81},
	{DEMOD_WRITE, 0x21, 0x80},
	{DEMOD_WRITE, 0x10, 0x33},
	{DEMOD_WRITE, 0x11, 0x44},
	{DEMOD_WRITE, 0x12, 0x07},
	{DEMOD_WRITE, 0x18, 0x20},
	{DEMOD_WRITE, 0x28, 0x04},
	{DEMOD_WRITE, 0x29, 0x8e},
	{DEMOD_WRITE, 0x3b, 0xff},
	{DEMOD_WRITE, 0x32, 0x10},
	{DEMOD_WRITE, 0x33, 0x02},
	{DEMOD_WRITE, 0x34, 0x30},
	{DEMOD_WRITE, 0x35, 0xff},
	{DEMOD_WRITE, 0x38, 0x50},
	{DEMOD_WRITE, 0x39, 0x68},
	{DEMOD_WRITE, 0x3c, 0x7f},
	{DEMOD_WRITE, 0x3d, 0x0f},
	{DEMOD_WRITE, 0x45, 0x20},
	{DEMOD_WRITE, 0x46, 0x24},
	{DEMOD_WRITE, 0x47, 0x7c},
	{DEMOD_WRITE, 0x48, 0x16},
	{DEMOD_WRITE, 0x49, 0x04},
	{DEMOD_WRITE, 0x4a, 0x01},
	{DEMOD_WRITE, 0x4b, 0x78},
	{DEMOD_WRITE, 0X4d, 0xd2},
	{DEMOD_WRITE, 0x4e, 0x6d},
	{DEMOD_WRITE, 0x50, 0x30},
	{DEMOD_WRITE, 0x51, 0x30},
	{DEMOD_WRITE, 0x54, 0x7b},
	{DEMOD_WRITE, 0x56, 0x09},
	{DEMOD_WRITE, 0x58, 0x59},
	{DEMOD_WRITE, 0x59, 0x37},
	{DEMOD_WRITE, 0x63, 0xfa},
	{0xff, 0xaa, 0xff}
};

struct inittab fe_trigger[] = {
	{DEMOD_WRITE, 0x97, 0x04},
	{DEMOD_WRITE, 0x99, 0x77},
	{DEMOD_WRITE, 0x9b, 0x64},
	{DEMOD_WRITE, 0x9e, 0x00},
	{DEMOD_WRITE, 0x9f, 0xf8},
	{DEMOD_WRITE, 0xa0, 0x20},
	{DEMOD_WRITE, 0xa1, 0xe0},
	{DEMOD_WRITE, 0xa3, 0x38},
	{DEMOD_WRITE, 0x98, 0xff},
	{DEMOD_WRITE, 0xc0, 0x0f},
	{DEMOD_WRITE, 0x89, 0x01},
	{DEMOD_WRITE, 0x00, 0x00},
	{WRITE_DELAY, 0x0a, 0x00},
	{DEMOD_WRITE, 0x00, 0x01},
	{DEMOD_WRITE, 0x00, 0x00},
	{DEMOD_WRITE, 0x9a, 0xb0},
	{0xff, 0xaa, 0xff}
};

static int m88rs2000_tab_set(struct m88rs2000_state *state,
		struct inittab *tab)
{
	int ret = 0;
	u8 i;
	if (tab == NULL)
		return -EINVAL;

	for (i = 0; i < 255; i++) {
		switch (tab[i].cmd) {
		case 0x01:
			ret = m88rs2000_writereg(state, tab[i].reg,
				tab[i].val);
			break;
		case 0x10:
			if (tab[i].reg > 0)
				mdelay(tab[i].reg);
			break;
		case 0xff:
			if (tab[i].reg == 0xaa && tab[i].val == 0xff)
				return 0;
		case 0x00:
			break;
		default:
			return -EINVAL;
		}
		if (ret < 0)
			return -ENODEV;
	}
	return 0;
}

static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	u8 data;

	data = m88rs2000_readreg(state, 0xb2);
	data |= 0x03; /* bit0 V/H, bit1 off/on */

	switch (volt) {
	case SEC_VOLTAGE_18:
		data &= ~0x03;
		break;
	case SEC_VOLTAGE_13:
		data &= ~0x03;
		data |= 0x01;
		break;
	case SEC_VOLTAGE_OFF:
		break;
	}

	m88rs2000_writereg(state, 0xb2, data);

	return 0;
}

static int m88rs2000_init(struct dvb_frontend *fe)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	int ret;

	deb_info("m88rs2000: init chip\n");
	/* Setup frontend from shutdown/cold */
	if (state->config->inittab)
		ret = m88rs2000_tab_set(state,
				(struct inittab *)state->config->inittab);
	else
		ret = m88rs2000_tab_set(state, m88rs2000_setup);

	return ret;
}

static int m88rs2000_sleep(struct dvb_frontend *fe)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	int ret;
	/* Shutdown the frondend */
	ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
	return ret;
}

static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	u8 reg = m88rs2000_readreg(state, 0x8c);

	*status = 0;

	if ((reg & 0x7) == 0x7) {
		*status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
			| FE_HAS_SYNC | FE_HAS_LOCK;
		if (state->config->set_ts_params)
			state->config->set_ts_params(fe, CALL_IS_READ);
	}
	return 0;
}

static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	u8 tmp0, tmp1;

	m88rs2000_writereg(state, 0x9a, 0x30);
	tmp0 = m88rs2000_readreg(state, 0xd8);
	if ((tmp0 & 0x10) != 0) {
		m88rs2000_writereg(state, 0x9a, 0xb0);
		*ber = 0xffffffff;
		return 0;
	}

	*ber = (m88rs2000_readreg(state, 0xd7) << 8) |
		m88rs2000_readreg(state, 0xd6);

	tmp1 = m88rs2000_readreg(state, 0xd9);
	m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
	/* needs twice */
	m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
	m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
	m88rs2000_writereg(state, 0x9a, 0xb0);

	return 0;
}

static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
	u16 *strength)
{
	if (fe->ops.tuner_ops.get_rf_strength)
		fe->ops.tuner_ops.get_rf_strength(fe, strength);

	return 0;
}

static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
{
	struct m88rs2000_state *state = fe->demodulator_priv;

	*snr = 512 * m88rs2000_readreg(state, 0x65);

	return 0;
}

static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	u8 tmp;

	*ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
			m88rs2000_readreg(state, 0xd4);
	tmp = m88rs2000_readreg(state, 0xd8);
	m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
	/* needs two times */
	m88rs2000_writereg(state, 0xd8, tmp | 0x20);
	m88rs2000_writereg(state, 0xd8, tmp | 0x20);

	return 0;
}

static int m88rs2000_set_fec(struct m88rs2000_state *state,
		fe_code_rate_t fec)
{
	u16 fec_set;
	switch (fec) {
	/* This is not confirmed kept for reference */
/*	case FEC_1_2:
		fec_set = 0x88;
		break;
	case FEC_2_3:
		fec_set = 0x68;
		break;
	case FEC_3_4:
		fec_set = 0x48;
		break;
	case FEC_5_6:
		fec_set = 0x28;
		break;
	case FEC_7_8:
		fec_set = 0x18;
		break; */
	case FEC_AUTO:
	default:
		fec_set = 0x08;
	}
	m88rs2000_writereg(state, 0x76, fec_set);

	return 0;
}


static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
{
	u8 reg;
	m88rs2000_writereg(state, 0x9a, 0x30);
	reg = m88rs2000_readreg(state, 0x76);
	m88rs2000_writereg(state, 0x9a, 0xb0);

	switch (reg) {
	case 0x88:
		return FEC_1_2;
	case 0x68:
		return FEC_2_3;
	case 0x48:
		return FEC_3_4;
	case 0x28:
		return FEC_5_6;
	case 0x18:
		return FEC_7_8;
	case 0x08:
	default:
		break;
	}

	return FEC_AUTO;
}

static int m88rs2000_set_frontend(struct dvb_frontend *fe)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	fe_status_t status;
	int i, ret = 0;
	s32 tmp;
	u32 tuner_freq;
	u16 offset = 0;
	u8 reg;

	state->no_lock_count = 0;

	if (c->delivery_system != SYS_DVBS) {
			deb_info("%s: unsupported delivery "
				"system selected (%d)\n",
				__func__, c->delivery_system);
			return -EOPNOTSUPP;
	}

	/* Set Tuner */
	if (fe->ops.tuner_ops.set_params)
		ret = fe->ops.tuner_ops.set_params(fe);

	if (ret < 0)
		return -ENODEV;

	if (fe->ops.tuner_ops.get_frequency)
		ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);

	if (ret < 0)
		return -ENODEV;

	offset = tuner_freq - c->frequency;

	/* calculate offset assuming 96000kHz*/
	tmp = offset;
	tmp *= 65536;

	tmp = (2 * tmp + 96000) / (2 * 96000);
	if (tmp < 0)
		tmp += 65536;

	offset = tmp & 0xffff;

	ret = m88rs2000_writereg(state, 0x9a, 0x30);
	/* Unknown usually 0xc6 sometimes 0xc1 */
	reg = m88rs2000_readreg(state, 0x86);
	ret |= m88rs2000_writereg(state, 0x86, reg);
	/* Offset lower nibble always 0 */
	ret |= m88rs2000_writereg(state, 0x9c, (offset >> 8));
	ret |= m88rs2000_writereg(state, 0x9d, offset & 0xf0);


	/* Reset Demod */
	ret = m88rs2000_tab_set(state, fe_reset);
	if (ret < 0)
		return -ENODEV;

	/* Unknown */
	reg = m88rs2000_readreg(state, 0x70);
	ret = m88rs2000_writereg(state, 0x70, reg);

	/* Set FEC */
	ret |= m88rs2000_set_fec(state, c->fec_inner);
	ret |= m88rs2000_writereg(state, 0x85, 0x1);
	ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
	ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
	ret |= m88rs2000_writereg(state, 0x90, 0xf1);
	ret |= m88rs2000_writereg(state, 0x91, 0x08);

	if (ret < 0)
		return -ENODEV;

	/* Set Symbol Rate */
	ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
	if (ret < 0)
		return -ENODEV;

	/* Set up Demod */
	ret = m88rs2000_tab_set(state, fe_trigger);
	if (ret < 0)
		return -ENODEV;

	for (i = 0; i < 25; i++) {
		reg = m88rs2000_readreg(state, 0x8c);
		if ((reg & 0x7) == 0x7) {
			status = FE_HAS_LOCK;
			break;
		}
		state->no_lock_count++;
		if (state->no_lock_count == 15) {
			reg = m88rs2000_readreg(state, 0x70);
			reg ^= 0x4;
			m88rs2000_writereg(state, 0x70, reg);
			state->no_lock_count = 0;
		}
		msleep(20);
	}

	if (status & FE_HAS_LOCK) {
		state->fec_inner = m88rs2000_get_fec(state);
		/* Uknown suspect SNR level */
		reg = m88rs2000_readreg(state, 0x65);
	}

	state->tuner_frequency = c->frequency;
	state->symbol_rate = c->symbol_rate;
	return 0;
}

static int m88rs2000_get_frontend(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct m88rs2000_state *state = fe->demodulator_priv;
	c->fec_inner = state->fec_inner;
	c->frequency = state->tuner_frequency;
	c->symbol_rate = state->symbol_rate;
	return 0;
}

static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
	struct m88rs2000_state *state = fe->demodulator_priv;

	if (enable)
		m88rs2000_writereg(state, 0x81, 0x84);
	else
		m88rs2000_writereg(state, 0x81, 0x81);
	udelay(10);
	return 0;
}

static void m88rs2000_release(struct dvb_frontend *fe)
{
	struct m88rs2000_state *state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops m88rs2000_ops = {
	.delsys = { SYS_DVBS },
	.info = {
		.name			= "M88RS2000 DVB-S",
		.frequency_min		= 950000,
		.frequency_max		= 2150000,
		.frequency_stepsize	= 1000,	 /* kHz for QPSK frontends */
		.frequency_tolerance	= 5000,
		.symbol_rate_min	= 1000000,
		.symbol_rate_max	= 45000000,
		.symbol_rate_tolerance	= 500,	/* ppm */
		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
		      FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
		      FE_CAN_QPSK |
		      FE_CAN_FEC_AUTO
	},

	.release = m88rs2000_release,
	.init = m88rs2000_init,
	.sleep = m88rs2000_sleep,
	.i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
	.read_status = m88rs2000_read_status,
	.read_ber = m88rs2000_read_ber,
	.read_signal_strength = m88rs2000_read_signal_strength,
	.read_snr = m88rs2000_read_snr,
	.read_ucblocks = m88rs2000_read_ucblocks,
	.diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
	.diseqc_send_burst = m88rs2000_send_diseqc_burst,
	.set_tone = m88rs2000_set_tone,
	.set_voltage = m88rs2000_set_voltage,

	.set_frontend = m88rs2000_set_frontend,
	.get_frontend = m88rs2000_get_frontend,
};

struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
				    struct i2c_adapter *i2c)
{
	struct m88rs2000_state *state = NULL;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	state->tuner_frequency = 0;
	state->symbol_rate = 0;
	state->fec_inner = 0;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &m88rs2000_ops,
			sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);

	return NULL;
}
EXPORT_SYMBOL(m88rs2000_attach);

MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.13");
Commit	Line	Data
ae8dc8ee MP	1	/*
	2	Driver for M88RS2000 demodulator and tuner
	3
	4	Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
	5	Beta Driver
	6
	7	Include various calculation code from DS3000 driver.
	8	Copyright (C) 2009 Konstantin Dimitrov.
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23
	24	*/
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/device.h>
	28	#include <linux/jiffies.h>
	29	#include <linux/string.h>
	30	#include <linux/slab.h>
	31	#include <linux/types.h>
	32
	33
	34	#include "dvb_frontend.h"
	35	#include "m88rs2000.h"
	36
	37	struct m88rs2000_state {
	38	struct i2c_adapter *i2c;
	39	const struct m88rs2000_config *config;
	40	struct dvb_frontend frontend;
	41	u8 no_lock_count;
	42	u32 tuner_frequency;
	43	u32 symbol_rate;
	44	fe_code_rate_t fec_inner;
	45	u8 tuner_level;
	46	int errmode;
	47	};
	48
	49	static int m88rs2000_debug;
	50
	51	module_param_named(debug, m88rs2000_debug, int, 0644);
	52	MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
	53
	54	#define dprintk(level, args...) do { \
	55	if (level & m88rs2000_debug) \
	56	printk(KERN_DEBUG "m88rs2000-fe: " args); \
	57	} while (0)
	58
	59	#define deb_info(args...) dprintk(0x01, args)
	60	#define info(format, arg...) \
	61	printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
	62
b858c331	63	static int m88rs2000_writereg(struct m88rs2000_state *state,
ae8dc8ee MP	64	u8 reg, u8 data)
	65	{
	66	int ret;
ae8dc8ee MP	67	u8 buf[] = { reg, data };
ae8dc8ee MP	68	struct i2c_msg msg = {
b858c331	69	.addr = state->config->demod_addr,
ae8dc8ee MP	70	.flags = 0,
	71	.buf = buf,
	72	.len = 2
	73	};
	74
	75	ret = i2c_transfer(state->i2c, &msg, 1);
	76
	77	if (ret != 1)
	78	deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
	79	"ret == %i)\n", __func__, reg, data, ret);
	80
	81	return (ret != 1) ? -EREMOTEIO : 0;
	82	}
	83
b858c331	84	static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
ae8dc8ee MP	85	{
	86	int ret;
	87	u8 b0[] = { reg };
	88	u8 b1[] = { 0 };
b858c331	89
ae8dc8ee MP	90	struct i2c_msg msg[] = {
ae8dc8ee MP	91	{
b858c331	92	.addr = state->config->demod_addr,
ae8dc8ee MP	93	.flags = 0,
	94	.buf = b0,
	95	.len = 1
	96	}, {
b858c331	97	.addr = state->config->demod_addr,
ae8dc8ee MP	98	.flags = I2C_M_RD,
	99	.buf = b1,
	100	.len = 1
	101	}
	102	};
	103
	104	ret = i2c_transfer(state->i2c, msg, 2);
	105
	106	if (ret != 2)
	107	deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
	108	__func__, reg, ret);
	109
	110	return b1[0];
	111	}
	112
ae8dc8ee MP	113	static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
	114	{
	115	struct m88rs2000_state *state = fe->demodulator_priv;
	116	int ret;
	117	u32 temp;
	118	u8 b[3];
	119
	120	if ((srate < 1000000) \|\| (srate > 45000000))
	121	return -EINVAL;
	122
	123	temp = srate / 1000;
	124	temp *= 11831;
	125	temp /= 68;
	126	temp -= 3;
	127
	128	b[0] = (u8) (temp >> 16) & 0xff;
	129	b[1] = (u8) (temp >> 8) & 0xff;
	130	b[2] = (u8) temp & 0xff;
b858c331 IL	131	ret = m88rs2000_writereg(state, 0x93, b[2]);
	132	ret \|= m88rs2000_writereg(state, 0x94, b[1]);
	133	ret \|= m88rs2000_writereg(state, 0x95, b[0]);
ae8dc8ee MP	134
	135	deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
	136	return ret;
	137	}
	138
	139	static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
	140	struct dvb_diseqc_master_cmd *m)
	141	{
	142	struct m88rs2000_state *state = fe->demodulator_priv;
	143
	144	int i;
	145	u8 reg;
	146	deb_info("%s\n", __func__);
b858c331 IL	147	m88rs2000_writereg(state, 0x9a, 0x30);
b858c331 IL	148	reg = m88rs2000_readreg(state, 0xb2);
ae8dc8ee	149	reg &= 0x3f;
b858c331	150	m88rs2000_writereg(state, 0xb2, reg);
ae8dc8ee	151	for (i = 0; i < m->msg_len; i++)
b858c331	152	m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
ae8dc8ee	153
b858c331	154	reg = m88rs2000_readreg(state, 0xb1);
ae8dc8ee MP	155	reg &= 0x87;
	156	reg \|= ((m->msg_len - 1) << 3) \| 0x07;
	157	reg &= 0x7f;
b858c331	158	m88rs2000_writereg(state, 0xb1, reg);
ae8dc8ee MP	159
ae8dc8ee MP	160	for (i = 0; i < 15; i++) {
b858c331	161	if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
ae8dc8ee MP	162	break;
	163	msleep(20);
	164	}
	165
b858c331	166	reg = m88rs2000_readreg(state, 0xb1);
ae8dc8ee MP	167	if ((reg & 0x40) > 0x0) {
	168	reg &= 0x7f;
	169	reg \|= 0x40;
b858c331	170	m88rs2000_writereg(state, 0xb1, reg);
ae8dc8ee MP	171	}
ae8dc8ee MP	172
b858c331	173	reg = m88rs2000_readreg(state, 0xb2);
ae8dc8ee MP	174	reg &= 0x3f;
ae8dc8ee MP	175	reg \|= 0x80;
b858c331 IL	176	m88rs2000_writereg(state, 0xb2, reg);
b858c331 IL	177	m88rs2000_writereg(state, 0x9a, 0xb0);
ae8dc8ee MP	178
	179
	180	return 0;
	181	}
	182
	183	static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
	184	fe_sec_mini_cmd_t burst)
	185	{
	186	struct m88rs2000_state *state = fe->demodulator_priv;
	187	u8 reg0, reg1;
	188	deb_info("%s\n", __func__);
b858c331	189	m88rs2000_writereg(state, 0x9a, 0x30);
ae8dc8ee	190	msleep(50);
b858c331 IL	191	reg0 = m88rs2000_readreg(state, 0xb1);
b858c331 IL	192	reg1 = m88rs2000_readreg(state, 0xb2);
593a2ce0	193	/* TODO complete this section */
b858c331 IL	194	m88rs2000_writereg(state, 0xb2, reg1);
	195	m88rs2000_writereg(state, 0xb1, reg0);
	196	m88rs2000_writereg(state, 0x9a, 0xb0);
ae8dc8ee MP	197
	198	return 0;
	199	}
	200
	201	static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
	202	{
	203	struct m88rs2000_state *state = fe->demodulator_priv;
	204	u8 reg0, reg1;
b858c331 IL	205	m88rs2000_writereg(state, 0x9a, 0x30);
	206	reg0 = m88rs2000_readreg(state, 0xb1);
	207	reg1 = m88rs2000_readreg(state, 0xb2);
ae8dc8ee MP	208
	209	reg1 &= 0x3f;
	210
	211	switch (tone) {
	212	case SEC_TONE_ON:
	213	reg0 \|= 0x4;
	214	reg0 &= 0xbc;
593a2ce0	215	break;
ae8dc8ee MP	216	case SEC_TONE_OFF:
ae8dc8ee MP	217	reg1 \|= 0x80;
593a2ce0	218	break;
ae8dc8ee	219	default:
593a2ce0	220	break;
ae8dc8ee	221	}
b858c331 IL	222	m88rs2000_writereg(state, 0xb2, reg1);
	223	m88rs2000_writereg(state, 0xb1, reg0);
	224	m88rs2000_writereg(state, 0x9a, 0xb0);
ae8dc8ee MP	225	return 0;
	226	}
	227
	228	struct inittab {
	229	u8 cmd;
	230	u8 reg;
	231	u8 val;
	232	};
	233
	234	struct inittab m88rs2000_setup[] = {
	235	{DEMOD_WRITE, 0x9a, 0x30},
	236	{DEMOD_WRITE, 0x00, 0x01},
	237	{WRITE_DELAY, 0x19, 0x00},
	238	{DEMOD_WRITE, 0x00, 0x00},
	239	{DEMOD_WRITE, 0x9a, 0xb0},
	240	{DEMOD_WRITE, 0x81, 0xc1},
ae8dc8ee MP	241	{DEMOD_WRITE, 0x81, 0x81},
	242	{DEMOD_WRITE, 0x86, 0xc6},
	243	{DEMOD_WRITE, 0x9a, 0x30},
	244	{DEMOD_WRITE, 0xf0, 0x22},
	245	{DEMOD_WRITE, 0xf1, 0xbf},
	246	{DEMOD_WRITE, 0xb0, 0x45},
593a2ce0	247	{DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
ae8dc8ee MP	248	{DEMOD_WRITE, 0x9a, 0xb0},
	249	{0xff, 0xaa, 0xff}
	250	};
	251
	252	struct inittab m88rs2000_shutdown[] = {
	253	{DEMOD_WRITE, 0x9a, 0x30},
	254	{DEMOD_WRITE, 0xb0, 0x00},
	255	{DEMOD_WRITE, 0xf1, 0x89},
	256	{DEMOD_WRITE, 0x00, 0x01},
	257	{DEMOD_WRITE, 0x9a, 0xb0},
ae8dc8ee MP	258	{DEMOD_WRITE, 0x81, 0x81},
	259	{0xff, 0xaa, 0xff}
	260	};
	261
ae8dc8ee MP	262	struct inittab fe_reset[] = {
	263	{DEMOD_WRITE, 0x00, 0x01},
	264	{DEMOD_WRITE, 0xf1, 0xbf},
	265	{DEMOD_WRITE, 0x00, 0x01},
	266	{DEMOD_WRITE, 0x20, 0x81},
	267	{DEMOD_WRITE, 0x21, 0x80},
	268	{DEMOD_WRITE, 0x10, 0x33},
	269	{DEMOD_WRITE, 0x11, 0x44},
	270	{DEMOD_WRITE, 0x12, 0x07},
	271	{DEMOD_WRITE, 0x18, 0x20},
	272	{DEMOD_WRITE, 0x28, 0x04},
	273	{DEMOD_WRITE, 0x29, 0x8e},
	274	{DEMOD_WRITE, 0x3b, 0xff},
	275	{DEMOD_WRITE, 0x32, 0x10},
	276	{DEMOD_WRITE, 0x33, 0x02},
	277	{DEMOD_WRITE, 0x34, 0x30},
	278	{DEMOD_WRITE, 0x35, 0xff},
	279	{DEMOD_WRITE, 0x38, 0x50},
	280	{DEMOD_WRITE, 0x39, 0x68},
	281	{DEMOD_WRITE, 0x3c, 0x7f},
	282	{DEMOD_WRITE, 0x3d, 0x0f},
	283	{DEMOD_WRITE, 0x45, 0x20},
	284	{DEMOD_WRITE, 0x46, 0x24},
	285	{DEMOD_WRITE, 0x47, 0x7c},
	286	{DEMOD_WRITE, 0x48, 0x16},
	287	{DEMOD_WRITE, 0x49, 0x04},
	288	{DEMOD_WRITE, 0x4a, 0x01},
	289	{DEMOD_WRITE, 0x4b, 0x78},
	290	{DEMOD_WRITE, 0X4d, 0xd2},
	291	{DEMOD_WRITE, 0x4e, 0x6d},
	292	{DEMOD_WRITE, 0x50, 0x30},
	293	{DEMOD_WRITE, 0x51, 0x30},
	294	{DEMOD_WRITE, 0x54, 0x7b},
	295	{DEMOD_WRITE, 0x56, 0x09},
	296	{DEMOD_WRITE, 0x58, 0x59},
	297	{DEMOD_WRITE, 0x59, 0x37},
	298	{DEMOD_WRITE, 0x63, 0xfa},
	299	{0xff, 0xaa, 0xff}
	300	};
	301
	302	struct inittab fe_trigger[] = {
	303	{DEMOD_WRITE, 0x97, 0x04},
	304	{DEMOD_WRITE, 0x99, 0x77},
	305	{DEMOD_WRITE, 0x9b, 0x64},
	306	{DEMOD_WRITE, 0x9e, 0x00},
	307	{DEMOD_WRITE, 0x9f, 0xf8},
	308	{DEMOD_WRITE, 0xa0, 0x20},
	309	{DEMOD_WRITE, 0xa1, 0xe0},
	310	{DEMOD_WRITE, 0xa3, 0x38},
	311	{DEMOD_WRITE, 0x98, 0xff},
	312	{DEMOD_WRITE, 0xc0, 0x0f},
	313	{DEMOD_WRITE, 0x89, 0x01},
	314	{DEMOD_WRITE, 0x00, 0x00},
	315	{WRITE_DELAY, 0x0a, 0x00},
	316	{DEMOD_WRITE, 0x00, 0x01},
	317	{DEMOD_WRITE, 0x00, 0x00},
	318	{DEMOD_WRITE, 0x9a, 0xb0},
	319	{0xff, 0xaa, 0xff}
	320	};
	321
	322	static int m88rs2000_tab_set(struct m88rs2000_state *state,
	323	struct inittab *tab)
	324	{
	325	int ret = 0;
326	u8 i;
327	if (tab == NULL)
328	return -EINVAL;
329
330	for (i = 0; i < 255; i++) {
331	switch (tab[i].cmd) {
332	case 0x01:
b858c331	333	ret = m88rs2000_writereg(state, tab[i].reg,
ae8dc8ee MP	334	tab[i].val);
	335	break;
	336	case 0x10:
	337	if (tab[i].reg > 0)
	338	mdelay(tab[i].reg);
	339	break;
	340	case 0xff:
	341	if (tab[i].reg == 0xaa && tab[i].val == 0xff)
	342	return 0;
	343	case 0x00:
	344	break;
	345	default:
	346	return -EINVAL;
	347	}
	348	if (ret < 0)
	349	return -ENODEV;
	350	}
	351	return 0;
	352	}
	353
	354	static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
	355	{
38431a98 IL	356	struct m88rs2000_state *state = fe->demodulator_priv;
	357	u8 data;
	358
b858c331	359	data = m88rs2000_readreg(state, 0xb2);
38431a98 IL	360	data \|= 0x03; /* bit0 V/H, bit1 off/on */
	361
	362	switch (volt) {
	363	case SEC_VOLTAGE_18:
	364	data &= ~0x03;
	365	break;
	366	case SEC_VOLTAGE_13:
	367	data &= ~0x03;
	368	data \|= 0x01;
	369	break;
	370	case SEC_VOLTAGE_OFF:
	371	break;
	372	}
	373
b858c331	374	m88rs2000_writereg(state, 0xb2, data);
ae8dc8ee MP	375
	376	return 0;
	377	}
	378
ae8dc8ee MP	379	static int m88rs2000_init(struct dvb_frontend *fe)
	380	{
	381	struct m88rs2000_state *state = fe->demodulator_priv;
	382	int ret;
	383
	384	deb_info("m88rs2000: init chip\n");
	385	/* Setup frontend from shutdown/cold */
081416e6 IL	386	if (state->config->inittab)
	387	ret = m88rs2000_tab_set(state,
	388	(struct inittab *)state->config->inittab);
	389	else
	390	ret = m88rs2000_tab_set(state, m88rs2000_setup);
ae8dc8ee MP	391
	392	return ret;
	393	}
	394
	395	static int m88rs2000_sleep(struct dvb_frontend *fe)
	396	{
	397	struct m88rs2000_state *state = fe->demodulator_priv;
	398	int ret;
	399	/* Shutdown the frondend */
	400	ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
	401	return ret;
	402	}
	403
	404	static int m88rs2000_read_status(struct dvb_frontend fe, fe_status_t status)
	405	{
	406	struct m88rs2000_state *state = fe->demodulator_priv;
b858c331	407	u8 reg = m88rs2000_readreg(state, 0x8c);
ae8dc8ee MP	408
	409	*status = 0;
	410
	411	if ((reg & 0x7) == 0x7) {
	412	*status = FE_HAS_CARRIER \| FE_HAS_SIGNAL \| FE_HAS_VITERBI
ff54298b	413	\| FE_HAS_SYNC \| FE_HAS_LOCK;
ae8dc8ee MP	414	if (state->config->set_ts_params)
	415	state->config->set_ts_params(fe, CALL_IS_READ);
	416	}
	417	return 0;
	418	}
	419
ae8dc8ee MP	420	static int m88rs2000_read_ber(struct dvb_frontend fe, u32 ber)
ae8dc8ee MP	421	{
38f7889c IL	422	struct m88rs2000_state *state = fe->demodulator_priv;
	423	u8 tmp0, tmp1;
	424
b858c331 IL	425	m88rs2000_writereg(state, 0x9a, 0x30);
b858c331 IL	426	tmp0 = m88rs2000_readreg(state, 0xd8);
38f7889c	427	if ((tmp0 & 0x10) != 0) {
b858c331	428	m88rs2000_writereg(state, 0x9a, 0xb0);
38f7889c IL	429	*ber = 0xffffffff;
	430	return 0;
	431	}
	432
b858c331 IL	433	*ber = (m88rs2000_readreg(state, 0xd7) << 8) \|
b858c331 IL	434	m88rs2000_readreg(state, 0xd6);
38f7889c	435
b858c331 IL	436	tmp1 = m88rs2000_readreg(state, 0xd9);
b858c331 IL	437	m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) \| 4);
38f7889c	438	/* needs twice */
b858c331 IL	439	m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) \| 0x30);
	440	m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) \| 0x30);
	441	m88rs2000_writereg(state, 0x9a, 0xb0);
38f7889c	442
ae8dc8ee MP	443	return 0;
	444	}
	445
	446	static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
	447	u16 *strength)
	448	{
a0a030bd MP	449	if (fe->ops.tuner_ops.get_rf_strength)
	450	fe->ops.tuner_ops.get_rf_strength(fe, strength);
	451
ae8dc8ee MP	452	return 0;
	453	}
	454
	455	static int m88rs2000_read_snr(struct dvb_frontend fe, u16 snr)
	456	{
38f7889c IL	457	struct m88rs2000_state *state = fe->demodulator_priv;
38f7889c IL	458
b858c331	459	snr = 512 m88rs2000_readreg(state, 0x65);
38f7889c	460
ae8dc8ee MP	461	return 0;
	462	}
	463
	464	static int m88rs2000_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	465	{
38f7889c IL	466	struct m88rs2000_state *state = fe->demodulator_priv;
	467	u8 tmp;
	468
b858c331 IL	469	*ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) \|
	470	m88rs2000_readreg(state, 0xd4);
	471	tmp = m88rs2000_readreg(state, 0xd8);
	472	m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
38f7889c	473	/* needs two times */
b858c331 IL	474	m88rs2000_writereg(state, 0xd8, tmp \| 0x20);
b858c331 IL	475	m88rs2000_writereg(state, 0xd8, tmp \| 0x20);
38f7889c	476
ae8dc8ee MP	477	return 0;
	478	}
	479
ae8dc8ee MP	480	static int m88rs2000_set_fec(struct m88rs2000_state *state,
	481	fe_code_rate_t fec)
	482	{
ae8dc8ee MP	483	u16 fec_set;
	484	switch (fec) {
	485	/* This is not confirmed kept for reference */
	486	/* case FEC_1_2:
	487	fec_set = 0x88;
	488	break;
	489	case FEC_2_3:
	490	fec_set = 0x68;
	491	break;
	492	case FEC_3_4:
	493	fec_set = 0x48;
	494	break;
	495	case FEC_5_6:
	496	fec_set = 0x28;
	497	break;
	498	case FEC_7_8:
	499	fec_set = 0x18;
	500	break; */
	501	case FEC_AUTO:
	502	default:
	503	fec_set = 0x08;
	504	}
b858c331	505	m88rs2000_writereg(state, 0x76, fec_set);
ae8dc8ee MP	506
	507	return 0;
	508	}
	509
	510
	511	static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
	512	{
	513	u8 reg;
b858c331 IL	514	m88rs2000_writereg(state, 0x9a, 0x30);
	515	reg = m88rs2000_readreg(state, 0x76);
	516	m88rs2000_writereg(state, 0x9a, 0xb0);
ae8dc8ee MP	517
	518	switch (reg) {
	519	case 0x88:
	520	return FEC_1_2;
	521	case 0x68:
	522	return FEC_2_3;
	523	case 0x48:
	524	return FEC_3_4;
	525	case 0x28:
	526	return FEC_5_6;
	527	case 0x18:
	528	return FEC_7_8;
	529	case 0x08:
	530	default:
	531	break;
	532	}
	533
	534	return FEC_AUTO;
	535	}
	536
	537	static int m88rs2000_set_frontend(struct dvb_frontend *fe)
	538	{
	539	struct m88rs2000_state *state = fe->demodulator_priv;
	540	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	541	fe_status_t status;
b858c331 IL	542	int i, ret = 0;
	543	s32 tmp;
	544	u32 tuner_freq;
ae8dc8ee MP	545	u16 offset = 0;
	546	u8 reg;
	547
	548	state->no_lock_count = 0;
	549
	550	if (c->delivery_system != SYS_DVBS) {
	551	deb_info("%s: unsupported delivery "
	552	"system selected (%d)\n",
	553	__func__, c->delivery_system);
	554	return -EOPNOTSUPP;
	555	}
	556
	557	/* Set Tuner */
b858c331 IL	558	if (fe->ops.tuner_ops.set_params)
	559	ret = fe->ops.tuner_ops.set_params(fe);
	560
	561	if (ret < 0)
	562	return -ENODEV;
	563
	564	if (fe->ops.tuner_ops.get_frequency)
	565	ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
	566
ae8dc8ee MP	567	if (ret < 0)
	568	return -ENODEV;
	569
b858c331 IL	570	offset = tuner_freq - c->frequency;
	571
	572	/* calculate offset assuming 96000kHz*/
	573	tmp = offset;
	574	tmp *= 65536;
	575
	576	tmp = (2 * tmp + 96000) / (2 * 96000);
	577	if (tmp < 0)
	578	tmp += 65536;
	579
	580	offset = tmp & 0xffff;
	581
	582	ret = m88rs2000_writereg(state, 0x9a, 0x30);
ae8dc8ee	583	/* Unknown usually 0xc6 sometimes 0xc1 */
b858c331 IL	584	reg = m88rs2000_readreg(state, 0x86);
b858c331 IL	585	ret \|= m88rs2000_writereg(state, 0x86, reg);
ae8dc8ee	586	/* Offset lower nibble always 0 */
b858c331 IL	587	ret \|= m88rs2000_writereg(state, 0x9c, (offset >> 8));
b858c331 IL	588	ret \|= m88rs2000_writereg(state, 0x9d, offset & 0xf0);
ae8dc8ee MP	589
	590
	591	/* Reset Demod */
	592	ret = m88rs2000_tab_set(state, fe_reset);
	593	if (ret < 0)
	594	return -ENODEV;
	595
	596	/* Unknown */
b858c331 IL	597	reg = m88rs2000_readreg(state, 0x70);
b858c331 IL	598	ret = m88rs2000_writereg(state, 0x70, reg);
ae8dc8ee MP	599
	600	/* Set FEC */
	601	ret \|= m88rs2000_set_fec(state, c->fec_inner);
b858c331 IL	602	ret \|= m88rs2000_writereg(state, 0x85, 0x1);
	603	ret \|= m88rs2000_writereg(state, 0x8a, 0xbf);
	604	ret \|= m88rs2000_writereg(state, 0x8d, 0x1e);
	605	ret \|= m88rs2000_writereg(state, 0x90, 0xf1);
	606	ret \|= m88rs2000_writereg(state, 0x91, 0x08);
ae8dc8ee MP	607
	608	if (ret < 0)
	609	return -ENODEV;
	610
	611	/* Set Symbol Rate */
	612	ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
	613	if (ret < 0)
	614	return -ENODEV;
	615
	616	/* Set up Demod */
	617	ret = m88rs2000_tab_set(state, fe_trigger);
	618	if (ret < 0)
	619	return -ENODEV;
	620
	621	for (i = 0; i < 25; i++) {
b858c331	622	reg = m88rs2000_readreg(state, 0x8c);
ae8dc8ee MP	623	if ((reg & 0x7) == 0x7) {
	624	status = FE_HAS_LOCK;
	625	break;
	626	}
	627	state->no_lock_count++;
e58c11f2	628	if (state->no_lock_count == 15) {
b858c331	629	reg = m88rs2000_readreg(state, 0x70);
ae8dc8ee	630	reg ^= 0x4;
b858c331	631	m88rs2000_writereg(state, 0x70, reg);
ae8dc8ee MP	632	state->no_lock_count = 0;
ae8dc8ee MP	633	}
ae8dc8ee MP	634	msleep(20);
	635	}
	636
	637	if (status & FE_HAS_LOCK) {
	638	state->fec_inner = m88rs2000_get_fec(state);
	639	/* Uknown suspect SNR level */
b858c331	640	reg = m88rs2000_readreg(state, 0x65);
ae8dc8ee MP	641	}
	642
	643	state->tuner_frequency = c->frequency;
	644	state->symbol_rate = c->symbol_rate;
	645	return 0;
	646	}
	647
	648	static int m88rs2000_get_frontend(struct dvb_frontend *fe)
	649	{
	650	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	651	struct m88rs2000_state *state = fe->demodulator_priv;
	652	c->fec_inner = state->fec_inner;
	653	c->frequency = state->tuner_frequency;
	654	c->symbol_rate = state->symbol_rate;
	655	return 0;
	656	}
	657
	658	static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
	659	{
	660	struct m88rs2000_state *state = fe->demodulator_priv;
	661
	662	if (enable)
b858c331	663	m88rs2000_writereg(state, 0x81, 0x84);
ae8dc8ee	664	else
b858c331	665	m88rs2000_writereg(state, 0x81, 0x81);
ae8dc8ee MP	666	udelay(10);
	667	return 0;
	668	}
	669
	670	static void m88rs2000_release(struct dvb_frontend *fe)
	671	{
	672	struct m88rs2000_state *state = fe->demodulator_priv;
	673	kfree(state);
	674	}
	675
	676	static struct dvb_frontend_ops m88rs2000_ops = {
	677	.delsys = { SYS_DVBS },
	678	.info = {
	679	.name = "M88RS2000 DVB-S",
ae8dc8ee MP	680	.frequency_min = 950000,
	681	.frequency_max = 2150000,
	682	.frequency_stepsize = 1000, /* kHz for QPSK frontends */
	683	.frequency_tolerance = 5000,
	684	.symbol_rate_min = 1000000,
	685	.symbol_rate_max = 45000000,
	686	.symbol_rate_tolerance = 500, /* ppm */
	687	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|
	688	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \|
	689	FE_CAN_QPSK \|
	690	FE_CAN_FEC_AUTO
	691	},
	692
	693	.release = m88rs2000_release,
	694	.init = m88rs2000_init,
	695	.sleep = m88rs2000_sleep,
ae8dc8ee MP	696	.i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
	697	.read_status = m88rs2000_read_status,
	698	.read_ber = m88rs2000_read_ber,
	699	.read_signal_strength = m88rs2000_read_signal_strength,
	700	.read_snr = m88rs2000_read_snr,
	701	.read_ucblocks = m88rs2000_read_ucblocks,
	702	.diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
	703	.diseqc_send_burst = m88rs2000_send_diseqc_burst,
	704	.set_tone = m88rs2000_set_tone,
	705	.set_voltage = m88rs2000_set_voltage,
	706
	707	.set_frontend = m88rs2000_set_frontend,
	708	.get_frontend = m88rs2000_get_frontend,
	709	};
	710
	711	struct dvb_frontend m88rs2000_attach(const struct m88rs2000_config config,
	712	struct i2c_adapter *i2c)
	713	{
	714	struct m88rs2000_state *state = NULL;
	715
	716	/* allocate memory for the internal state */
	717	state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
	718	if (state == NULL)
	719	goto error;
	720
	721	/* setup the state */
	722	state->config = config;
	723	state->i2c = i2c;
	724	state->tuner_frequency = 0;
	725	state->symbol_rate = 0;
	726	state->fec_inner = 0;
	727
ae8dc8ee MP	728	/* create dvb_frontend */
	729	memcpy(&state->frontend.ops, &m88rs2000_ops,
	730	sizeof(struct dvb_frontend_ops));
	731	state->frontend.demodulator_priv = state;
	732	return &state->frontend;
	733
	734	error:
	735	kfree(state);
	736
	737	return NULL;
	738	}
	739	EXPORT_SYMBOL(m88rs2000_attach);
	740
	741	MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
	742	MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
	743	MODULE_LICENSE("GPL");
593a2ce0	744	MODULE_VERSION("1.13");
ae8dc8ee	745