]>
Commit | Line | Data |
---|---|---|
b9ede79a MCC |
1 | /* |
2 | * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver | |
3 | * | |
a77cfcac | 4 | * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com> |
b9ede79a MCC |
5 | * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> |
6 | * | |
b9ede79a MCC |
7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <asm/div64.h> | |
19 | ||
20 | #include "dvb_frontend.h" | |
21 | #include "mb86a20s.h" | |
22 | ||
23 | static int debug = 1; | |
24 | module_param(debug, int, 0644); | |
25 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); | |
26 | ||
b9ede79a MCC |
27 | struct mb86a20s_state { |
28 | struct i2c_adapter *i2c; | |
29 | const struct mb86a20s_config *config; | |
09b6d21e | 30 | u32 last_frequency; |
b9ede79a MCC |
31 | |
32 | struct dvb_frontend frontend; | |
c736a5f2 | 33 | |
d01a8ee3 MCC |
34 | u32 estimated_rate[3]; |
35 | ||
c736a5f2 | 36 | bool need_init; |
b9ede79a MCC |
37 | }; |
38 | ||
39 | struct regdata { | |
40 | u8 reg; | |
41 | u8 data; | |
42 | }; | |
43 | ||
d01a8ee3 MCC |
44 | #define BER_SAMPLING_RATE 1 /* Seconds */ |
45 | ||
b9ede79a MCC |
46 | /* |
47 | * Initialization sequence: Use whatevere default values that PV SBTVD | |
48 | * does on its initialisation, obtained via USB snoop | |
49 | */ | |
50 | static struct regdata mb86a20s_init[] = { | |
51 | { 0x70, 0x0f }, | |
52 | { 0x70, 0xff }, | |
53 | { 0x08, 0x01 }, | |
54 | { 0x09, 0x3e }, | |
a7025edf | 55 | { 0x50, 0xd1 }, { 0x51, 0x22 }, |
b9ede79a MCC |
56 | { 0x39, 0x01 }, |
57 | { 0x71, 0x00 }, | |
a7025edf MCC |
58 | { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 }, |
59 | { 0x28, 0x20 }, { 0x29, 0x33 }, { 0x2a, 0xdf }, { 0x2b, 0xa9 }, | |
ebe96749 | 60 | { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 }, |
b9ede79a MCC |
61 | { 0x3b, 0x21 }, |
62 | { 0x3c, 0x3a }, | |
63 | { 0x01, 0x0d }, | |
a7025edf MCC |
64 | { 0x04, 0x08 }, { 0x05, 0x05 }, |
65 | { 0x04, 0x0e }, { 0x05, 0x00 }, | |
66 | { 0x04, 0x0f }, { 0x05, 0x14 }, | |
67 | { 0x04, 0x0b }, { 0x05, 0x8c }, | |
68 | { 0x04, 0x00 }, { 0x05, 0x00 }, | |
69 | { 0x04, 0x01 }, { 0x05, 0x07 }, | |
70 | { 0x04, 0x02 }, { 0x05, 0x0f }, | |
71 | { 0x04, 0x03 }, { 0x05, 0xa0 }, | |
72 | { 0x04, 0x09 }, { 0x05, 0x00 }, | |
73 | { 0x04, 0x0a }, { 0x05, 0xff }, | |
74 | { 0x04, 0x27 }, { 0x05, 0x64 }, | |
75 | { 0x04, 0x28 }, { 0x05, 0x00 }, | |
76 | { 0x04, 0x1e }, { 0x05, 0xff }, | |
77 | { 0x04, 0x29 }, { 0x05, 0x0a }, | |
78 | { 0x04, 0x32 }, { 0x05, 0x0a }, | |
79 | { 0x04, 0x14 }, { 0x05, 0x02 }, | |
80 | { 0x04, 0x04 }, { 0x05, 0x00 }, | |
81 | { 0x04, 0x05 }, { 0x05, 0x22 }, | |
82 | { 0x04, 0x06 }, { 0x05, 0x0e }, | |
83 | { 0x04, 0x07 }, { 0x05, 0xd8 }, | |
84 | { 0x04, 0x12 }, { 0x05, 0x00 }, | |
85 | { 0x04, 0x13 }, { 0x05, 0xff }, | |
ebe96749 MCC |
86 | { 0x04, 0x15 }, { 0x05, 0x4e }, |
87 | { 0x04, 0x16 }, { 0x05, 0x20 }, | |
09b6d21e MCC |
88 | |
89 | /* | |
90 | * On this demod, when the bit count reaches the count below, | |
91 | * it collects the bit error count. The bit counters are initialized | |
92 | * to 65535 here. This warrants that all of them will be quickly | |
93 | * calculated when device gets locked. As TMCC is parsed, the values | |
d01a8ee3 | 94 | * will be adjusted later in the driver's code. |
09b6d21e MCC |
95 | */ |
96 | { 0x52, 0x01 }, /* Turn on BER before Viterbi */ | |
97 | { 0x50, 0xa7 }, { 0x51, 0x00 }, | |
a7025edf MCC |
98 | { 0x50, 0xa8 }, { 0x51, 0xff }, |
99 | { 0x50, 0xa9 }, { 0x51, 0xff }, | |
09b6d21e | 100 | { 0x50, 0xaa }, { 0x51, 0x00 }, |
a7025edf MCC |
101 | { 0x50, 0xab }, { 0x51, 0xff }, |
102 | { 0x50, 0xac }, { 0x51, 0xff }, | |
09b6d21e | 103 | { 0x50, 0xad }, { 0x51, 0x00 }, |
a7025edf MCC |
104 | { 0x50, 0xae }, { 0x51, 0xff }, |
105 | { 0x50, 0xaf }, { 0x51, 0xff }, | |
09b6d21e MCC |
106 | |
107 | { 0x5e, 0x00 }, /* Turn off BER after Viterbi */ | |
a7025edf MCC |
108 | { 0x50, 0xdc }, { 0x51, 0x01 }, |
109 | { 0x50, 0xdd }, { 0x51, 0xf4 }, | |
110 | { 0x50, 0xde }, { 0x51, 0x01 }, | |
111 | { 0x50, 0xdf }, { 0x51, 0xf4 }, | |
112 | { 0x50, 0xe0 }, { 0x51, 0x01 }, | |
113 | { 0x50, 0xe1 }, { 0x51, 0xf4 }, | |
114 | { 0x50, 0xb0 }, { 0x51, 0x07 }, | |
115 | { 0x50, 0xb2 }, { 0x51, 0xff }, | |
116 | { 0x50, 0xb3 }, { 0x51, 0xff }, | |
117 | { 0x50, 0xb4 }, { 0x51, 0xff }, | |
118 | { 0x50, 0xb5 }, { 0x51, 0xff }, | |
119 | { 0x50, 0xb6 }, { 0x51, 0xff }, | |
120 | { 0x50, 0xb7 }, { 0x51, 0xff }, | |
121 | { 0x50, 0x50 }, { 0x51, 0x02 }, | |
09b6d21e MCC |
122 | { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ |
123 | { 0x45, 0x04 }, /* CN symbol 4 */ | |
b9ede79a | 124 | { 0x48, 0x04 }, |
a7025edf MCC |
125 | { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */ |
126 | { 0x50, 0xd6 }, { 0x51, 0x1f }, | |
127 | { 0x50, 0xd2 }, { 0x51, 0x03 }, | |
128 | { 0x50, 0xd7 }, { 0x51, 0x3f }, | |
ebe96749 MCC |
129 | { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x28, 0x74 }, { 0x29, 0x40 }, |
130 | { 0x28, 0x46 }, { 0x29, 0x2c }, { 0x28, 0x46 }, { 0x29, 0x0c }, | |
ce77d120 MCC |
131 | |
132 | { 0x04, 0x40 }, { 0x05, 0x00 }, | |
ebe96749 MCC |
133 | { 0x28, 0x00 }, { 0x29, 0x10 }, |
134 | { 0x28, 0x05 }, { 0x29, 0x02 }, | |
b9ede79a | 135 | { 0x1c, 0x01 }, |
a7025edf MCC |
136 | { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 }, |
137 | { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d }, | |
138 | { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, | |
139 | { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 }, | |
140 | { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 }, | |
141 | { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 }, | |
142 | { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, | |
143 | { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 }, | |
144 | { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e }, | |
145 | { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e }, | |
146 | { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 }, | |
147 | { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, | |
148 | { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 }, | |
149 | { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 }, | |
150 | { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe }, | |
151 | { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 }, | |
152 | { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee }, | |
153 | { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 }, | |
154 | { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f }, | |
155 | { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 }, | |
156 | { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 }, | |
157 | { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a }, | |
158 | { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc }, | |
159 | { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba }, | |
160 | { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 }, | |
161 | { 0x50, 0x1e }, { 0x51, 0x5d }, | |
162 | { 0x50, 0x22 }, { 0x51, 0x00 }, | |
163 | { 0x50, 0x23 }, { 0x51, 0xc8 }, | |
164 | { 0x50, 0x24 }, { 0x51, 0x00 }, | |
165 | { 0x50, 0x25 }, { 0x51, 0xf0 }, | |
166 | { 0x50, 0x26 }, { 0x51, 0x00 }, | |
167 | { 0x50, 0x27 }, { 0x51, 0xc3 }, | |
168 | { 0x50, 0x39 }, { 0x51, 0x02 }, | |
ebe96749 | 169 | { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 }, |
b9ede79a MCC |
170 | { 0xd0, 0x00 }, |
171 | }; | |
172 | ||
173 | static struct regdata mb86a20s_reset_reception[] = { | |
174 | { 0x70, 0xf0 }, | |
175 | { 0x70, 0xff }, | |
176 | { 0x08, 0x01 }, | |
177 | { 0x08, 0x00 }, | |
178 | }; | |
179 | ||
09b6d21e MCC |
180 | static struct regdata mb86a20s_vber_reset[] = { |
181 | { 0x53, 0x00 }, /* VBER Counter reset */ | |
182 | { 0x53, 0x07 }, | |
183 | }; | |
184 | ||
185 | static struct regdata mb86a20s_per_reset[] = { | |
186 | { 0x50, 0xb1 }, /* PER Counter reset */ | |
187 | { 0x51, 0x07 }, | |
188 | { 0x51, 0x00 }, | |
189 | }; | |
190 | ||
dd4493ef MCC |
191 | /* |
192 | * I2C read/write functions and macros | |
193 | */ | |
194 | ||
b9ede79a | 195 | static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, |
09b6d21e | 196 | u8 i2c_addr, u8 reg, u8 data) |
b9ede79a MCC |
197 | { |
198 | u8 buf[] = { reg, data }; | |
199 | struct i2c_msg msg = { | |
200 | .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 | |
201 | }; | |
202 | int rc; | |
203 | ||
204 | rc = i2c_transfer(state->i2c, &msg, 1); | |
205 | if (rc != 1) { | |
f66d81b5 MCC |
206 | dev_err(&state->i2c->dev, |
207 | "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", | |
208 | __func__, rc, reg, data); | |
b9ede79a MCC |
209 | return rc; |
210 | } | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, | |
216 | u8 i2c_addr, struct regdata *rd, int size) | |
217 | { | |
218 | int i, rc; | |
219 | ||
220 | for (i = 0; i < size; i++) { | |
221 | rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, | |
222 | rd[i].data); | |
223 | if (rc < 0) | |
224 | return rc; | |
225 | } | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, | |
230 | u8 i2c_addr, u8 reg) | |
231 | { | |
232 | u8 val; | |
233 | int rc; | |
234 | struct i2c_msg msg[] = { | |
235 | { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, | |
236 | { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } | |
237 | }; | |
238 | ||
239 | rc = i2c_transfer(state->i2c, msg, 2); | |
240 | ||
241 | if (rc != 2) { | |
f66d81b5 MCC |
242 | dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", |
243 | __func__, reg, rc); | |
244 | return (rc < 0) ? rc : -EIO; | |
b9ede79a MCC |
245 | } |
246 | ||
247 | return val; | |
248 | } | |
249 | ||
250 | #define mb86a20s_readreg(state, reg) \ | |
251 | mb86a20s_i2c_readreg(state, state->config->demod_address, reg) | |
252 | #define mb86a20s_writereg(state, reg, val) \ | |
253 | mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) | |
254 | #define mb86a20s_writeregdata(state, regdata) \ | |
255 | mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ | |
256 | regdata, ARRAY_SIZE(regdata)) | |
257 | ||
09b6d21e MCC |
258 | /* |
259 | * Ancillary internal routines (likely compiled inlined) | |
260 | * | |
261 | * The functions below assume that gateway lock has already obtained | |
262 | */ | |
263 | ||
dd4493ef | 264 | static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status) |
b9ede79a MCC |
265 | { |
266 | struct mb86a20s_state *state = fe->demodulator_priv; | |
dd4493ef | 267 | int val; |
b9ede79a | 268 | |
dd4493ef | 269 | *status = 0; |
b9ede79a | 270 | |
dd4493ef MCC |
271 | val = mb86a20s_readreg(state, 0x0a) & 0xf; |
272 | if (val < 0) | |
273 | return val; | |
68541cda | 274 | |
dd4493ef MCC |
275 | if (val >= 2) |
276 | *status |= FE_HAS_SIGNAL; | |
b9ede79a | 277 | |
dd4493ef MCC |
278 | if (val >= 4) |
279 | *status |= FE_HAS_CARRIER; | |
7572f9c5 | 280 | |
dd4493ef MCC |
281 | if (val >= 5) |
282 | *status |= FE_HAS_VITERBI; | |
7572f9c5 | 283 | |
dd4493ef MCC |
284 | if (val >= 7) |
285 | *status |= FE_HAS_SYNC; | |
68541cda | 286 | |
dd4493ef MCC |
287 | if (val >= 8) /* Maybe 9? */ |
288 | *status |= FE_HAS_LOCK; | |
289 | ||
f66d81b5 MCC |
290 | dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", |
291 | __func__, *status, val); | |
dd4493ef MCC |
292 | |
293 | return 0; | |
b9ede79a MCC |
294 | } |
295 | ||
09b6d21e | 296 | static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) |
b9ede79a MCC |
297 | { |
298 | struct mb86a20s_state *state = fe->demodulator_priv; | |
09b6d21e | 299 | int rc; |
b9ede79a | 300 | unsigned rf_max, rf_min, rf; |
68541cda | 301 | |
b9ede79a MCC |
302 | /* Does a binary search to get RF strength */ |
303 | rf_max = 0xfff; | |
304 | rf_min = 0; | |
305 | do { | |
306 | rf = (rf_max + rf_min) / 2; | |
09b6d21e MCC |
307 | rc = mb86a20s_writereg(state, 0x04, 0x1f); |
308 | if (rc < 0) | |
309 | return rc; | |
310 | rc = mb86a20s_writereg(state, 0x05, rf >> 8); | |
311 | if (rc < 0) | |
312 | return rc; | |
313 | rc = mb86a20s_writereg(state, 0x04, 0x20); | |
314 | if (rc < 0) | |
315 | return rc; | |
316 | rc = mb86a20s_writereg(state, 0x04, rf); | |
317 | if (rc < 0) | |
318 | return rc; | |
b9ede79a | 319 | |
09b6d21e MCC |
320 | rc = mb86a20s_readreg(state, 0x02); |
321 | if (rc < 0) | |
322 | return rc; | |
323 | if (rc & 0x08) | |
b9ede79a MCC |
324 | rf_min = (rf_max + rf_min) / 2; |
325 | else | |
326 | rf_max = (rf_max + rf_min) / 2; | |
327 | if (rf_max - rf_min < 4) { | |
09b6d21e MCC |
328 | rf = (rf_max + rf_min) / 2; |
329 | ||
330 | /* Rescale it from 2^12 (4096) to 2^16 */ | |
331 | rf <<= (16 - 12); | |
f66d81b5 MCC |
332 | dev_dbg(&state->i2c->dev, |
333 | "%s: signal strength = %d (%d < RF=%d < %d)\n", | |
334 | __func__, rf, rf_min, rf >> 4, rf_max); | |
09b6d21e | 335 | return rf; |
b9ede79a MCC |
336 | } |
337 | } while (1); | |
338 | ||
b9ede79a MCC |
339 | return 0; |
340 | } | |
341 | ||
959a119f MCC |
342 | static int mb86a20s_get_modulation(struct mb86a20s_state *state, |
343 | unsigned layer) | |
344 | { | |
345 | int rc; | |
346 | static unsigned char reg[] = { | |
347 | [0] = 0x86, /* Layer A */ | |
348 | [1] = 0x8a, /* Layer B */ | |
349 | [2] = 0x8e, /* Layer C */ | |
350 | }; | |
351 | ||
82033bc5 | 352 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
353 | return -EINVAL; |
354 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
355 | if (rc < 0) | |
356 | return rc; | |
357 | rc = mb86a20s_readreg(state, 0x6e); | |
358 | if (rc < 0) | |
359 | return rc; | |
04585921 | 360 | switch ((rc >> 4) & 0x07) { |
959a119f MCC |
361 | case 0: |
362 | return DQPSK; | |
363 | case 1: | |
364 | return QPSK; | |
365 | case 2: | |
366 | return QAM_16; | |
367 | case 3: | |
368 | return QAM_64; | |
369 | default: | |
370 | return QAM_AUTO; | |
371 | } | |
372 | } | |
373 | ||
374 | static int mb86a20s_get_fec(struct mb86a20s_state *state, | |
375 | unsigned layer) | |
376 | { | |
377 | int rc; | |
378 | ||
379 | static unsigned char reg[] = { | |
380 | [0] = 0x87, /* Layer A */ | |
381 | [1] = 0x8b, /* Layer B */ | |
382 | [2] = 0x8f, /* Layer C */ | |
383 | }; | |
384 | ||
82033bc5 | 385 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
386 | return -EINVAL; |
387 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
388 | if (rc < 0) | |
389 | return rc; | |
390 | rc = mb86a20s_readreg(state, 0x6e); | |
391 | if (rc < 0) | |
392 | return rc; | |
04585921 | 393 | switch ((rc >> 4) & 0x07) { |
959a119f MCC |
394 | case 0: |
395 | return FEC_1_2; | |
396 | case 1: | |
397 | return FEC_2_3; | |
398 | case 2: | |
399 | return FEC_3_4; | |
400 | case 3: | |
401 | return FEC_5_6; | |
402 | case 4: | |
403 | return FEC_7_8; | |
404 | default: | |
405 | return FEC_AUTO; | |
406 | } | |
407 | } | |
408 | ||
409 | static int mb86a20s_get_interleaving(struct mb86a20s_state *state, | |
410 | unsigned layer) | |
411 | { | |
412 | int rc; | |
413 | ||
414 | static unsigned char reg[] = { | |
415 | [0] = 0x88, /* Layer A */ | |
416 | [1] = 0x8c, /* Layer B */ | |
417 | [2] = 0x90, /* Layer C */ | |
418 | }; | |
419 | ||
82033bc5 | 420 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
421 | return -EINVAL; |
422 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
423 | if (rc < 0) | |
424 | return rc; | |
425 | rc = mb86a20s_readreg(state, 0x6e); | |
426 | if (rc < 0) | |
427 | return rc; | |
04585921 MCC |
428 | |
429 | switch ((rc >> 4) & 0x07) { | |
430 | case 1: | |
431 | return GUARD_INTERVAL_1_4; | |
432 | case 2: | |
433 | return GUARD_INTERVAL_1_8; | |
434 | case 3: | |
435 | return GUARD_INTERVAL_1_16; | |
436 | case 4: | |
437 | return GUARD_INTERVAL_1_32; | |
438 | ||
439 | default: | |
440 | case 0: | |
441 | return GUARD_INTERVAL_AUTO; | |
442 | } | |
959a119f MCC |
443 | } |
444 | ||
445 | static int mb86a20s_get_segment_count(struct mb86a20s_state *state, | |
446 | unsigned layer) | |
447 | { | |
448 | int rc, count; | |
959a119f MCC |
449 | static unsigned char reg[] = { |
450 | [0] = 0x89, /* Layer A */ | |
451 | [1] = 0x8d, /* Layer B */ | |
452 | [2] = 0x91, /* Layer C */ | |
453 | }; | |
454 | ||
f66d81b5 MCC |
455 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
456 | ||
82033bc5 | 457 | if (layer >= ARRAY_SIZE(reg)) |
959a119f | 458 | return -EINVAL; |
f66d81b5 | 459 | |
959a119f MCC |
460 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); |
461 | if (rc < 0) | |
462 | return rc; | |
463 | rc = mb86a20s_readreg(state, 0x6e); | |
464 | if (rc < 0) | |
465 | return rc; | |
466 | count = (rc >> 4) & 0x0f; | |
467 | ||
f66d81b5 MCC |
468 | dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); |
469 | ||
959a119f MCC |
470 | return count; |
471 | } | |
472 | ||
a77cfcac MCC |
473 | static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) |
474 | { | |
f66d81b5 | 475 | struct mb86a20s_state *state = fe->demodulator_priv; |
a77cfcac MCC |
476 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
477 | ||
f66d81b5 MCC |
478 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
479 | ||
a77cfcac MCC |
480 | /* Fixed parameters */ |
481 | c->delivery_system = SYS_ISDBT; | |
482 | c->bandwidth_hz = 6000000; | |
483 | ||
484 | /* Initialize values that will be later autodetected */ | |
485 | c->isdbt_layer_enabled = 0; | |
486 | c->transmission_mode = TRANSMISSION_MODE_AUTO; | |
487 | c->guard_interval = GUARD_INTERVAL_AUTO; | |
488 | c->isdbt_sb_mode = 0; | |
489 | c->isdbt_sb_segment_count = 0; | |
490 | } | |
491 | ||
d01a8ee3 MCC |
492 | /* |
493 | * Estimates the bit rate using the per-segment bit rate given by | |
494 | * ABNT/NBR 15601 spec (table 4). | |
495 | */ | |
496 | static u32 isdbt_rate[3][5][4] = { | |
497 | { /* DQPSK/QPSK */ | |
498 | { 280850, 312060, 330420, 340430 }, /* 1/2 */ | |
499 | { 374470, 416080, 440560, 453910 }, /* 2/3 */ | |
500 | { 421280, 468090, 495630, 510650 }, /* 3/4 */ | |
501 | { 468090, 520100, 550700, 567390 }, /* 5/6 */ | |
502 | { 491500, 546110, 578230, 595760 }, /* 7/8 */ | |
503 | }, { /* QAM16 */ | |
504 | { 561710, 624130, 660840, 680870 }, /* 1/2 */ | |
505 | { 748950, 832170, 881120, 907820 }, /* 2/3 */ | |
506 | { 842570, 936190, 991260, 1021300 }, /* 3/4 */ | |
507 | { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ | |
508 | { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ | |
509 | }, { /* QAM64 */ | |
510 | { 842570, 936190, 991260, 1021300 }, /* 1/2 */ | |
511 | { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ | |
512 | { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ | |
513 | { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ | |
514 | { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ | |
515 | } | |
516 | }; | |
517 | ||
518 | static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, | |
519 | u32 modulation, u32 fec, u32 interleaving, | |
520 | u32 segment) | |
521 | { | |
522 | struct mb86a20s_state *state = fe->demodulator_priv; | |
523 | u32 rate; | |
524 | int m, f, i; | |
525 | ||
526 | /* | |
527 | * If modulation/fec/interleaving is not detected, the default is | |
528 | * to consider the lowest bit rate, to avoid taking too long time | |
529 | * to get BER. | |
530 | */ | |
531 | switch (modulation) { | |
532 | case DQPSK: | |
533 | case QPSK: | |
534 | default: | |
535 | m = 0; | |
536 | break; | |
537 | case QAM_16: | |
538 | m = 1; | |
539 | break; | |
540 | case QAM_64: | |
541 | m = 2; | |
542 | break; | |
543 | } | |
544 | ||
545 | switch (fec) { | |
546 | default: | |
547 | case FEC_1_2: | |
548 | case FEC_AUTO: | |
549 | f = 0; | |
550 | break; | |
551 | case FEC_2_3: | |
552 | f = 1; | |
553 | break; | |
554 | case FEC_3_4: | |
555 | f = 2; | |
556 | break; | |
557 | case FEC_5_6: | |
558 | f = 3; | |
559 | break; | |
560 | case FEC_7_8: | |
561 | f = 4; | |
562 | break; | |
563 | } | |
564 | ||
565 | switch (interleaving) { | |
566 | default: | |
567 | case GUARD_INTERVAL_1_4: | |
568 | i = 0; | |
569 | break; | |
570 | case GUARD_INTERVAL_1_8: | |
571 | i = 1; | |
572 | break; | |
573 | case GUARD_INTERVAL_1_16: | |
574 | i = 2; | |
575 | break; | |
576 | case GUARD_INTERVAL_1_32: | |
577 | i = 3; | |
578 | break; | |
579 | } | |
580 | ||
581 | /* Samples BER at BER_SAMPLING_RATE seconds */ | |
582 | rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE; | |
583 | ||
584 | /* Avoids sampling too quickly or to overflow the register */ | |
585 | if (rate < 256) | |
586 | rate = 256; | |
587 | else if (rate > (1 << 24) - 1) | |
588 | rate = (1 << 24) - 1; | |
589 | ||
590 | dev_dbg(&state->i2c->dev, | |
591 | "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", | |
592 | __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000, | |
593 | rate, rate); | |
594 | ||
595 | state->estimated_rate[i] = rate; | |
596 | } | |
597 | ||
598 | ||
7c61d80a | 599 | static int mb86a20s_get_frontend(struct dvb_frontend *fe) |
b9ede79a | 600 | { |
959a119f | 601 | struct mb86a20s_state *state = fe->demodulator_priv; |
a77cfcac | 602 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
959a119f | 603 | int i, rc; |
b9ede79a | 604 | |
f66d81b5 MCC |
605 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
606 | ||
a77cfcac MCC |
607 | /* Reset frontend cache to default values */ |
608 | mb86a20s_reset_frontend_cache(fe); | |
959a119f | 609 | |
959a119f MCC |
610 | /* Check for partial reception */ |
611 | rc = mb86a20s_writereg(state, 0x6d, 0x85); | |
a77cfcac MCC |
612 | if (rc < 0) |
613 | return rc; | |
614 | rc = mb86a20s_readreg(state, 0x6e); | |
615 | if (rc < 0) | |
616 | return rc; | |
617 | c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; | |
959a119f MCC |
618 | |
619 | /* Get per-layer data */ | |
a77cfcac | 620 | |
959a119f | 621 | for (i = 0; i < 3; i++) { |
f66d81b5 MCC |
622 | dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", |
623 | __func__, 'A' + i); | |
624 | ||
959a119f | 625 | rc = mb86a20s_get_segment_count(state, i); |
a77cfcac | 626 | if (rc < 0) |
f66d81b5 | 627 | goto noperlayer_error; |
d01a8ee3 | 628 | if (rc >= 0 && rc < 14) { |
a77cfcac | 629 | c->layer[i].segment_count = rc; |
d01a8ee3 | 630 | } else { |
a77cfcac | 631 | c->layer[i].segment_count = 0; |
d01a8ee3 | 632 | state->estimated_rate[i] = 0; |
959a119f | 633 | continue; |
a77cfcac MCC |
634 | } |
635 | c->isdbt_layer_enabled |= 1 << i; | |
959a119f | 636 | rc = mb86a20s_get_modulation(state, i); |
a77cfcac | 637 | if (rc < 0) |
f66d81b5 MCC |
638 | goto noperlayer_error; |
639 | dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", | |
640 | __func__, rc); | |
a77cfcac | 641 | c->layer[i].modulation = rc; |
959a119f | 642 | rc = mb86a20s_get_fec(state, i); |
a77cfcac | 643 | if (rc < 0) |
f66d81b5 MCC |
644 | goto noperlayer_error; |
645 | dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", | |
646 | __func__, rc); | |
a77cfcac | 647 | c->layer[i].fec = rc; |
959a119f | 648 | rc = mb86a20s_get_interleaving(state, i); |
a77cfcac | 649 | if (rc < 0) |
f66d81b5 MCC |
650 | goto noperlayer_error; |
651 | dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", | |
652 | __func__, rc); | |
a77cfcac | 653 | c->layer[i].interleaving = rc; |
d01a8ee3 MCC |
654 | mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation, |
655 | c->layer[i].fec, | |
656 | c->layer[i].interleaving, | |
657 | c->layer[i].segment_count); | |
959a119f MCC |
658 | } |
659 | ||
959a119f | 660 | rc = mb86a20s_writereg(state, 0x6d, 0x84); |
a77cfcac MCC |
661 | if (rc < 0) |
662 | return rc; | |
663 | if ((rc & 0x60) == 0x20) { | |
664 | c->isdbt_sb_mode = 1; | |
959a119f | 665 | /* At least, one segment should exist */ |
a77cfcac MCC |
666 | if (!c->isdbt_sb_segment_count) |
667 | c->isdbt_sb_segment_count = 1; | |
668 | } | |
959a119f MCC |
669 | |
670 | /* Get transmission mode and guard interval */ | |
959a119f | 671 | rc = mb86a20s_readreg(state, 0x07); |
a77cfcac MCC |
672 | if (rc < 0) |
673 | return rc; | |
674 | if ((rc & 0x60) == 0x20) { | |
675 | switch (rc & 0x0c >> 2) { | |
676 | case 0: | |
677 | c->transmission_mode = TRANSMISSION_MODE_2K; | |
678 | break; | |
679 | case 1: | |
680 | c->transmission_mode = TRANSMISSION_MODE_4K; | |
681 | break; | |
682 | case 2: | |
683 | c->transmission_mode = TRANSMISSION_MODE_8K; | |
684 | break; | |
959a119f | 685 | } |
a77cfcac MCC |
686 | } |
687 | if (!(rc & 0x10)) { | |
688 | switch (rc & 0x3) { | |
689 | case 0: | |
690 | c->guard_interval = GUARD_INTERVAL_1_4; | |
691 | break; | |
692 | case 1: | |
693 | c->guard_interval = GUARD_INTERVAL_1_8; | |
694 | break; | |
695 | case 2: | |
696 | c->guard_interval = GUARD_INTERVAL_1_16; | |
697 | break; | |
959a119f MCC |
698 | } |
699 | } | |
09b6d21e | 700 | return 0; |
959a119f | 701 | |
f66d81b5 | 702 | noperlayer_error: |
b9ede79a | 703 | |
09b6d21e MCC |
704 | /* per-layer info is incomplete; discard all per-layer */ |
705 | c->isdbt_layer_enabled = 0; | |
706 | ||
707 | return rc; | |
708 | } | |
709 | ||
710 | static int mb86a20s_reset_counters(struct dvb_frontend *fe) | |
711 | { | |
712 | struct mb86a20s_state *state = fe->demodulator_priv; | |
713 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
714 | int rc, val; | |
715 | ||
716 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
717 | ||
718 | /* Reset the counters, if the channel changed */ | |
719 | if (state->last_frequency != c->frequency) { | |
720 | memset(&c->strength, 0, sizeof(c->strength)); | |
721 | memset(&c->cnr, 0, sizeof(c->cnr)); | |
722 | memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); | |
723 | memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); | |
724 | memset(&c->block_error, 0, sizeof(c->block_error)); | |
725 | memset(&c->block_count, 0, sizeof(c->block_count)); | |
726 | ||
727 | state->last_frequency = c->frequency; | |
728 | } | |
729 | ||
730 | /* Clear status for most stats */ | |
731 | ||
732 | /* BER counter reset */ | |
733 | rc = mb86a20s_writeregdata(state, mb86a20s_vber_reset); | |
734 | if (rc < 0) | |
735 | goto err; | |
736 | ||
737 | /* MER, PER counter reset */ | |
738 | rc = mb86a20s_writeregdata(state, mb86a20s_per_reset); | |
739 | if (rc < 0) | |
740 | goto err; | |
741 | ||
742 | /* CNR counter reset */ | |
743 | rc = mb86a20s_readreg(state, 0x45); | |
744 | if (rc < 0) | |
745 | goto err; | |
746 | val = rc; | |
747 | rc = mb86a20s_writereg(state, 0x45, val | 0x10); | |
748 | if (rc < 0) | |
749 | goto err; | |
750 | rc = mb86a20s_writereg(state, 0x45, val & 0x6f); | |
751 | if (rc < 0) | |
752 | goto err; | |
753 | ||
754 | /* MER counter reset */ | |
755 | rc = mb86a20s_writereg(state, 0x50, 0x50); | |
756 | if (rc < 0) | |
757 | goto err; | |
758 | rc = mb86a20s_readreg(state, 0x51); | |
759 | if (rc < 0) | |
760 | goto err; | |
761 | val = rc; | |
762 | rc = mb86a20s_writereg(state, 0x51, val | 0x01); | |
763 | if (rc < 0) | |
764 | goto err; | |
765 | rc = mb86a20s_writereg(state, 0x51, val & 0x06); | |
766 | if (rc < 0) | |
767 | goto err; | |
768 | ||
149d518a | 769 | goto ok; |
09b6d21e | 770 | err: |
149d518a MCC |
771 | dev_err(&state->i2c->dev, |
772 | "%s: Can't reset FE statistics (error %d).\n", | |
773 | __func__, rc); | |
774 | ok: | |
a77cfcac | 775 | return rc; |
09b6d21e MCC |
776 | } |
777 | ||
149d518a MCC |
778 | static int mb86a20s_get_ber_before_vterbi(struct dvb_frontend *fe, |
779 | unsigned layer, | |
780 | u32 *error, u32 *count) | |
781 | { | |
782 | struct mb86a20s_state *state = fe->demodulator_priv; | |
783 | int rc; | |
784 | ||
785 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
786 | ||
787 | if (layer >= 3) | |
788 | return -EINVAL; | |
789 | ||
790 | /* Check if the BER measures are already available */ | |
791 | rc = mb86a20s_readreg(state, 0x54); | |
792 | if (rc < 0) | |
793 | return rc; | |
794 | ||
795 | /* Check if data is available for that layer */ | |
796 | if (!(rc & (1 << layer))) { | |
797 | dev_dbg(&state->i2c->dev, | |
798 | "%s: BER for layer %c is not available yet.\n", | |
799 | __func__, 'A' + layer); | |
800 | return -EBUSY; | |
801 | } | |
802 | ||
803 | /* Read Bit Error Count */ | |
804 | rc = mb86a20s_readreg(state, 0x55 + layer * 3); | |
805 | if (rc < 0) | |
806 | return rc; | |
807 | *error = rc << 16; | |
808 | rc = mb86a20s_readreg(state, 0x56 + layer * 3); | |
809 | if (rc < 0) | |
810 | return rc; | |
811 | *error |= rc << 8; | |
812 | rc = mb86a20s_readreg(state, 0x57 + layer * 3); | |
813 | if (rc < 0) | |
814 | return rc; | |
815 | *error |= rc; | |
816 | ||
817 | dev_dbg(&state->i2c->dev, | |
818 | "%s: bit error before Viterbi for layer %c: %d.\n", | |
819 | __func__, 'A' + layer, *error); | |
820 | ||
821 | /* Read Bit Count */ | |
822 | rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); | |
823 | if (rc < 0) | |
824 | return rc; | |
825 | rc = mb86a20s_readreg(state, 0x51); | |
826 | if (rc < 0) | |
827 | return rc; | |
828 | *count = rc << 16; | |
829 | rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); | |
830 | if (rc < 0) | |
831 | return rc; | |
832 | rc = mb86a20s_readreg(state, 0x51); | |
833 | if (rc < 0) | |
834 | return rc; | |
835 | *count |= rc << 8; | |
836 | rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); | |
837 | if (rc < 0) | |
838 | return rc; | |
839 | rc = mb86a20s_readreg(state, 0x51); | |
840 | if (rc < 0) | |
841 | return rc; | |
842 | *count |= rc; | |
843 | ||
844 | dev_dbg(&state->i2c->dev, | |
845 | "%s: bit count before Viterbi for layer %c: %d.\n", | |
846 | __func__, 'A' + layer, *count); | |
847 | ||
848 | ||
d01a8ee3 MCC |
849 | /* |
850 | * As we get TMCC data from the frontend, we can better estimate the | |
851 | * BER bit counters, in order to do the BER measure during a longer | |
852 | * time. Use those data, if available, to update the bit count | |
853 | * measure. | |
854 | */ | |
855 | ||
856 | if (state->estimated_rate[layer] | |
857 | && state->estimated_rate[layer] != *count) { | |
858 | dev_dbg(&state->i2c->dev, | |
859 | "%s: updating layer %c counter to %d.\n", | |
860 | __func__, 'A' + layer, state->estimated_rate[layer]); | |
861 | rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); | |
862 | if (rc < 0) | |
863 | return rc; | |
864 | rc = mb86a20s_writereg(state, 0x51, | |
865 | state->estimated_rate[layer] >> 16); | |
866 | if (rc < 0) | |
867 | return rc; | |
868 | rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); | |
869 | if (rc < 0) | |
870 | return rc; | |
871 | rc = mb86a20s_writereg(state, 0x51, | |
872 | state->estimated_rate[layer] >> 8); | |
873 | if (rc < 0) | |
874 | return rc; | |
875 | rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); | |
876 | if (rc < 0) | |
877 | return rc; | |
878 | rc = mb86a20s_writereg(state, 0x51, | |
879 | state->estimated_rate[layer]); | |
880 | if (rc < 0) | |
881 | return rc; | |
882 | } | |
883 | ||
884 | ||
149d518a MCC |
885 | /* Reset counter to collect new data */ |
886 | rc = mb86a20s_writereg(state, 0x53, 0x07 & ~(1 << layer)); | |
887 | if (rc < 0) | |
888 | return rc; | |
889 | rc = mb86a20s_writereg(state, 0x53, 0x07); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
09b6d21e MCC |
894 | static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) |
895 | { | |
896 | struct mb86a20s_state *state = fe->demodulator_priv; | |
897 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
898 | int i; | |
899 | ||
900 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
a77cfcac | 901 | |
09b6d21e MCC |
902 | /* Fill the length of each status counter */ |
903 | ||
904 | /* Only global stats */ | |
905 | c->strength.len = 1; | |
906 | ||
907 | /* Per-layer stats - 3 layers + global */ | |
908 | c->cnr.len = 4; | |
909 | c->pre_bit_error.len = 4; | |
910 | c->pre_bit_count.len = 4; | |
911 | c->block_error.len = 4; | |
912 | c->block_count.len = 4; | |
913 | ||
914 | /* Signal is always available */ | |
915 | c->strength.stat[0].scale = FE_SCALE_RELATIVE; | |
916 | c->strength.stat[0].uvalue = 0; | |
917 | ||
918 | /* Put all of them at FE_SCALE_NOT_AVAILABLE */ | |
919 | for (i = 0; i < 4; i++) { | |
920 | c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
921 | c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
922 | c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
923 | c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
924 | c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE; | |
925 | } | |
b9ede79a MCC |
926 | } |
927 | ||
149d518a MCC |
928 | static int mb86a20s_get_stats(struct dvb_frontend *fe) |
929 | { | |
930 | struct mb86a20s_state *state = fe->demodulator_priv; | |
931 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
932 | int rc = 0, i; | |
933 | u32 bit_error = 0, bit_count = 0; | |
934 | u32 t_pre_bit_error = 0, t_pre_bit_count = 0; | |
935 | int active_layers = 0, ber_layers = 0; | |
936 | ||
937 | /* Get per-layer stats */ | |
938 | for (i = 0; i < 3; i++) { | |
939 | if (c->isdbt_layer_enabled & (1 << i)) { | |
940 | /* Layer is active and has rc segments */ | |
941 | active_layers++; | |
942 | ||
943 | /* Read per-layer BER */ | |
944 | /* Handle BER before vterbi */ | |
945 | rc = mb86a20s_get_ber_before_vterbi(fe, i, | |
946 | &bit_error, | |
947 | &bit_count); | |
948 | if (rc >= 0) { | |
949 | c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; | |
950 | c->pre_bit_error.stat[1 + i].uvalue += bit_error; | |
951 | c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; | |
952 | c->pre_bit_count.stat[1 + i].uvalue += bit_count; | |
953 | } else if (rc != -EBUSY) { | |
954 | /* | |
955 | * If an I/O error happened, | |
956 | * measures are now unavailable | |
957 | */ | |
958 | c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; | |
959 | c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE; | |
960 | dev_err(&state->i2c->dev, | |
961 | "%s: Can't get BER for layer %c (error %d).\n", | |
962 | __func__, 'A' + i, rc); | |
963 | } | |
964 | ||
965 | if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE) | |
966 | ber_layers++; | |
967 | ||
968 | /* Update total BER */ | |
969 | t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue; | |
970 | t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue; | |
971 | } | |
972 | } | |
973 | ||
974 | /* | |
975 | * Start showing global count if at least one error count is | |
976 | * available. | |
977 | */ | |
978 | if (ber_layers) { | |
979 | /* | |
980 | * At least one per-layer BER measure was read. We can now | |
981 | * calculate the total BER | |
982 | * | |
983 | * Total Bit Error/Count is calculated as the sum of the | |
984 | * bit errors on all active layers. | |
985 | */ | |
986 | c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
987 | c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; | |
988 | c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
989 | c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; | |
990 | } | |
991 | ||
992 | return rc; | |
993 | } | |
09b6d21e MCC |
994 | |
995 | /* | |
996 | * The functions below are called via DVB callbacks, so they need to | |
997 | * properly use the I2C gate control | |
998 | */ | |
999 | ||
dd4493ef MCC |
1000 | static int mb86a20s_initfe(struct dvb_frontend *fe) |
1001 | { | |
1002 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1003 | int rc; | |
1004 | u8 regD5 = 1; | |
1005 | ||
f66d81b5 | 1006 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
dd4493ef MCC |
1007 | |
1008 | if (fe->ops.i2c_gate_ctrl) | |
1009 | fe->ops.i2c_gate_ctrl(fe, 0); | |
1010 | ||
1011 | /* Initialize the frontend */ | |
1012 | rc = mb86a20s_writeregdata(state, mb86a20s_init); | |
1013 | if (rc < 0) | |
1014 | goto err; | |
1015 | ||
1016 | if (!state->config->is_serial) { | |
1017 | regD5 &= ~1; | |
1018 | ||
1019 | rc = mb86a20s_writereg(state, 0x50, 0xd5); | |
1020 | if (rc < 0) | |
1021 | goto err; | |
1022 | rc = mb86a20s_writereg(state, 0x51, regD5); | |
1023 | if (rc < 0) | |
1024 | goto err; | |
1025 | } | |
1026 | ||
1027 | err: | |
1028 | if (fe->ops.i2c_gate_ctrl) | |
1029 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1030 | ||
1031 | if (rc < 0) { | |
1032 | state->need_init = true; | |
f66d81b5 MCC |
1033 | dev_info(&state->i2c->dev, |
1034 | "mb86a20s: Init failed. Will try again later\n"); | |
dd4493ef MCC |
1035 | } else { |
1036 | state->need_init = false; | |
f66d81b5 | 1037 | dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); |
dd4493ef MCC |
1038 | } |
1039 | return rc; | |
1040 | } | |
1041 | ||
1042 | static int mb86a20s_set_frontend(struct dvb_frontend *fe) | |
1043 | { | |
1044 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1045 | int rc; | |
1046 | #if 0 | |
1047 | /* | |
1048 | * FIXME: Properly implement the set frontend properties | |
1049 | */ | |
1050 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
1051 | #endif | |
f66d81b5 | 1052 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
dd4493ef MCC |
1053 | |
1054 | /* | |
1055 | * Gate should already be opened, but it doesn't hurt to | |
1056 | * double-check | |
1057 | */ | |
1058 | if (fe->ops.i2c_gate_ctrl) | |
1059 | fe->ops.i2c_gate_ctrl(fe, 1); | |
dd4493ef MCC |
1060 | fe->ops.tuner_ops.set_params(fe); |
1061 | ||
1062 | /* | |
1063 | * Make it more reliable: if, for some reason, the initial | |
1064 | * device initialization doesn't happen, initialize it when | |
1065 | * a SBTVD parameters are adjusted. | |
1066 | * | |
1067 | * Unfortunately, due to a hard to track bug at tda829x/tda18271, | |
1068 | * the agc callback logic is not called during DVB attach time, | |
1069 | * causing mb86a20s to not be initialized with Kworld SBTVD. | |
1070 | * So, this hack is needed, in order to make Kworld SBTVD to work. | |
1071 | */ | |
1072 | if (state->need_init) | |
1073 | mb86a20s_initfe(fe); | |
1074 | ||
1075 | if (fe->ops.i2c_gate_ctrl) | |
1076 | fe->ops.i2c_gate_ctrl(fe, 0); | |
d01a8ee3 | 1077 | |
dd4493ef | 1078 | rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); |
09b6d21e | 1079 | mb86a20s_reset_counters(fe); |
d01a8ee3 | 1080 | |
dd4493ef MCC |
1081 | if (fe->ops.i2c_gate_ctrl) |
1082 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1083 | ||
1084 | return rc; | |
1085 | } | |
1086 | ||
09b6d21e MCC |
1087 | static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, |
1088 | fe_status_t *status) | |
d36e418a | 1089 | { |
09b6d21e MCC |
1090 | struct mb86a20s_state *state = fe->demodulator_priv; |
1091 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
1092 | int rc; | |
d36e418a | 1093 | |
09b6d21e | 1094 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
d36e418a MCC |
1095 | |
1096 | if (fe->ops.i2c_gate_ctrl) | |
1097 | fe->ops.i2c_gate_ctrl(fe, 0); | |
1098 | ||
09b6d21e MCC |
1099 | /* Get lock */ |
1100 | rc = mb86a20s_read_status(fe, status); | |
1101 | if (!(*status & FE_HAS_LOCK)) { | |
1102 | mb86a20s_stats_not_ready(fe); | |
1103 | mb86a20s_reset_frontend_cache(fe); | |
1104 | } | |
149d518a MCC |
1105 | if (rc < 0) { |
1106 | dev_err(&state->i2c->dev, | |
1107 | "%s: Can't read frontend lock status\n", __func__); | |
09b6d21e | 1108 | goto error; |
149d518a | 1109 | } |
09b6d21e MCC |
1110 | |
1111 | /* Get signal strength */ | |
1112 | rc = mb86a20s_read_signal_strength(fe); | |
1113 | if (rc < 0) { | |
149d518a MCC |
1114 | dev_err(&state->i2c->dev, |
1115 | "%s: Can't reset VBER registers.\n", __func__); | |
09b6d21e MCC |
1116 | mb86a20s_stats_not_ready(fe); |
1117 | mb86a20s_reset_frontend_cache(fe); | |
149d518a MCC |
1118 | |
1119 | rc = 0; /* Status is OK */ | |
09b6d21e MCC |
1120 | goto error; |
1121 | } | |
1122 | /* Fill signal strength */ | |
1123 | c->strength.stat[0].uvalue = rc; | |
1124 | ||
1125 | if (*status & FE_HAS_LOCK) { | |
1126 | /* Get TMCC info*/ | |
1127 | rc = mb86a20s_get_frontend(fe); | |
149d518a MCC |
1128 | if (rc < 0) { |
1129 | dev_err(&state->i2c->dev, | |
1130 | "%s: Can't get FE TMCC data.\n", __func__); | |
1131 | rc = 0; /* Status is OK */ | |
1132 | goto error; | |
1133 | } | |
1134 | ||
1135 | /* Get statistics */ | |
1136 | rc = mb86a20s_get_stats(fe); | |
1137 | if (rc < 0 && rc != -EBUSY) { | |
1138 | dev_err(&state->i2c->dev, | |
1139 | "%s: Can't get FE statistics.\n", __func__); | |
1140 | rc = 0; | |
09b6d21e | 1141 | goto error; |
149d518a MCC |
1142 | } |
1143 | rc = 0; /* Don't return EBUSY to userspace */ | |
09b6d21e | 1144 | } |
149d518a | 1145 | goto ok; |
09b6d21e | 1146 | |
149d518a | 1147 | error: |
09b6d21e | 1148 | mb86a20s_stats_not_ready(fe); |
d36e418a | 1149 | |
149d518a | 1150 | ok: |
d36e418a MCC |
1151 | if (fe->ops.i2c_gate_ctrl) |
1152 | fe->ops.i2c_gate_ctrl(fe, 1); | |
149d518a | 1153 | |
09b6d21e MCC |
1154 | return rc; |
1155 | } | |
1156 | ||
1157 | static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, | |
1158 | u16 *strength) | |
1159 | { | |
1160 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
1161 | ||
1162 | ||
1163 | *strength = c->strength.stat[0].uvalue; | |
d36e418a | 1164 | |
09b6d21e | 1165 | return 0; |
d36e418a MCC |
1166 | } |
1167 | ||
09b6d21e MCC |
1168 | static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe) |
1169 | { | |
1170 | /* | |
1171 | * get_frontend is now handled together with other stats | |
1172 | * retrival, when read_status() is called, as some statistics | |
1173 | * will depend on the layers detection. | |
1174 | */ | |
1175 | return 0; | |
1176 | }; | |
1177 | ||
b9ede79a | 1178 | static int mb86a20s_tune(struct dvb_frontend *fe, |
7e072221 | 1179 | bool re_tune, |
b9ede79a MCC |
1180 | unsigned int mode_flags, |
1181 | unsigned int *delay, | |
1182 | fe_status_t *status) | |
1183 | { | |
f66d81b5 | 1184 | struct mb86a20s_state *state = fe->demodulator_priv; |
b9ede79a MCC |
1185 | int rc = 0; |
1186 | ||
f66d81b5 | 1187 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
b9ede79a | 1188 | |
7e072221 | 1189 | if (re_tune) |
2d76e22b | 1190 | rc = mb86a20s_set_frontend(fe); |
b9ede79a MCC |
1191 | |
1192 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
09b6d21e | 1193 | mb86a20s_read_status_and_stats(fe, status); |
b9ede79a MCC |
1194 | |
1195 | return rc; | |
1196 | } | |
1197 | ||
1198 | static void mb86a20s_release(struct dvb_frontend *fe) | |
1199 | { | |
1200 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1201 | ||
f66d81b5 | 1202 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
b9ede79a MCC |
1203 | |
1204 | kfree(state); | |
1205 | } | |
1206 | ||
1207 | static struct dvb_frontend_ops mb86a20s_ops; | |
1208 | ||
1209 | struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, | |
1210 | struct i2c_adapter *i2c) | |
1211 | { | |
f66d81b5 | 1212 | struct mb86a20s_state *state; |
b9ede79a MCC |
1213 | u8 rev; |
1214 | ||
f167e302 MCC |
1215 | dev_dbg(&i2c->dev, "%s called.\n", __func__); |
1216 | ||
b9ede79a | 1217 | /* allocate memory for the internal state */ |
f66d81b5 | 1218 | state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL); |
b9ede79a | 1219 | if (state == NULL) { |
f167e302 | 1220 | dev_err(&i2c->dev, |
f66d81b5 | 1221 | "%s: unable to allocate memory for state\n", __func__); |
b9ede79a MCC |
1222 | goto error; |
1223 | } | |
1224 | ||
1225 | /* setup the state */ | |
1226 | state->config = config; | |
1227 | state->i2c = i2c; | |
1228 | ||
1229 | /* create dvb_frontend */ | |
1230 | memcpy(&state->frontend.ops, &mb86a20s_ops, | |
1231 | sizeof(struct dvb_frontend_ops)); | |
1232 | state->frontend.demodulator_priv = state; | |
1233 | ||
1234 | /* Check if it is a mb86a20s frontend */ | |
1235 | rev = mb86a20s_readreg(state, 0); | |
1236 | ||
1237 | if (rev == 0x13) { | |
f167e302 | 1238 | dev_info(&i2c->dev, |
f66d81b5 | 1239 | "Detected a Fujitsu mb86a20s frontend\n"); |
b9ede79a | 1240 | } else { |
f167e302 | 1241 | dev_dbg(&i2c->dev, |
f66d81b5 | 1242 | "Frontend revision %d is unknown - aborting.\n", |
b9ede79a MCC |
1243 | rev); |
1244 | goto error; | |
1245 | } | |
1246 | ||
1247 | return &state->frontend; | |
1248 | ||
1249 | error: | |
1250 | kfree(state); | |
1251 | return NULL; | |
1252 | } | |
1253 | EXPORT_SYMBOL(mb86a20s_attach); | |
1254 | ||
1255 | static struct dvb_frontend_ops mb86a20s_ops = { | |
2d76e22b | 1256 | .delsys = { SYS_ISDBT }, |
b9ede79a MCC |
1257 | /* Use dib8000 values per default */ |
1258 | .info = { | |
1259 | .name = "Fujitsu mb86A20s", | |
b9ede79a MCC |
1260 | .caps = FE_CAN_INVERSION_AUTO | FE_CAN_RECOVER | |
1261 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
1262 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
1263 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | | |
1264 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | | |
1265 | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, | |
1266 | /* Actually, those values depend on the used tuner */ | |
1267 | .frequency_min = 45000000, | |
1268 | .frequency_max = 864000000, | |
1269 | .frequency_stepsize = 62500, | |
1270 | }, | |
1271 | ||
1272 | .release = mb86a20s_release, | |
1273 | ||
1274 | .init = mb86a20s_initfe, | |
2d76e22b | 1275 | .set_frontend = mb86a20s_set_frontend, |
09b6d21e MCC |
1276 | .get_frontend = mb86a20s_get_frontend_dummy, |
1277 | .read_status = mb86a20s_read_status_and_stats, | |
1278 | .read_signal_strength = mb86a20s_read_signal_strength_from_cache, | |
b9ede79a MCC |
1279 | .tune = mb86a20s_tune, |
1280 | }; | |
1281 | ||
1282 | MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); | |
1283 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); | |
1284 | MODULE_LICENSE("GPL"); |