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[media] rc-main: clear rc_map.name in ir_free_table()
[mirror_ubuntu-hirsute-kernel.git] / drivers / media / dvb-frontends / rtl2832.c
CommitLineData
82041c0a
TM		 1/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
75c24005 5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
82041c0a
TM		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include "rtl2832_priv.h"
82041c0a 23
298f18a3 24#define REG_MASK(b) (BIT(b + 1) - 1)
82041c0a
TM		 25
26static const struct rtl2832_reg_entry registers[] = {
eec21beb
AP		 27 [DVBT_SOFT_RST] = {0x101, 2, 2},
28 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
29 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
30 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
31 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
32 [DVBT_AD_EN_REG] = {0x008, 7, 7},
33 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
34 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
35 [DVBT_MGD_THD0] = {0x195, 7, 0},
36 [DVBT_MGD_THD1] = {0x196, 7, 0},
37 [DVBT_MGD_THD2] = {0x197, 7, 0},
38 [DVBT_MGD_THD3] = {0x198, 7, 0},
39 [DVBT_MGD_THD4] = {0x199, 7, 0},
40 [DVBT_MGD_THD5] = {0x19a, 7, 0},
41 [DVBT_MGD_THD6] = {0x19b, 7, 0},
42 [DVBT_MGD_THD7] = {0x19c, 7, 0},
43 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
44 [DVBT_AD_AV_REF] = {0x009, 6, 0},
45 [DVBT_REG_PI] = {0x00a, 2, 0},
46 [DVBT_PIP_ON] = {0x021, 3, 3},
47 [DVBT_SCALE1_B92] = {0x292, 7, 0},
48 [DVBT_SCALE1_B93] = {0x293, 7, 0},
49 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
50 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
51 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
52 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
53 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
54 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
55 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
56 [DVBT_KB_P1] = {0x164, 3, 1},
57 [DVBT_KB_P2] = {0x164, 6, 4},
58 [DVBT_KB_P3] = {0x165, 2, 0},
59 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
60 [DVBT_AD_AVI] = {0x009, 1, 0},
61 [DVBT_AD_AVQ] = {0x009, 3, 2},
62 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
63 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
64 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
65 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
66 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
67 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
68 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
69 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
70 [DVBT_SPEC_INV] = {0x115, 0, 0},
71 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
72 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
73 [DVBT_FSM_STAGE] = {0x351, 6, 3},
74 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
75 [DVBT_RX_HIER] = {0x33c, 6, 4},
76 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
77 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
78 [DVBT_GI_IDX] = {0x351, 1, 0},
79 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
80 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
81 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
82 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
83 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
84 [DVBT_DAGC_VAL] = {0x305, 7, 0},
85 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
86 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
87 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
88 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
89 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
90 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
91 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
92 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
93 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
94 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
95 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
96 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
97 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
98 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
99 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
100 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
101 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
102 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
103 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
104 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
105 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
106 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
107 [DVBT_VTOP1] = {0x106, 5, 0},
108 [DVBT_VTOP2] = {0x1c9, 5, 0},
109 [DVBT_VTOP3] = {0x1ca, 5, 0},
110 [DVBT_KRF1] = {0x1cb, 7, 0},
111 [DVBT_KRF2] = {0x107, 7, 0},
112 [DVBT_KRF3] = {0x1cd, 7, 0},
113 [DVBT_KRF4] = {0x1ce, 7, 0},
114 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
115 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
116 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
117 [DVBT_THD_UP1] = {0x1dd, 7, 0},
118 [DVBT_THD_DW1] = {0x1de, 7, 0},
119 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
120 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
121 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
122 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
123 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
124 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
125 [DVBT_ERR_DUR] = {0x17c, 0, 0},
126 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
127 [DVBT_ERR_LVL] = {0x17c, 2, 2},
128 [DVBT_VAL_LVL] = {0x17c, 3, 3},
129 [DVBT_SERIAL] = {0x17c, 4, 4},
130 [DVBT_SER_LSB] = {0x17c, 5, 5},
131 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
132 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
133 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
134 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
135 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
136 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
137 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
138 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
139 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
140 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
141 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
142 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
143 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
144 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
145 [DVBT_SM_PASS] = {0x193, 11, 0},
146 [DVBT_AD7_SETTING] = {0x011, 15, 0},
147 [DVBT_RSSI_R] = {0x301, 6, 0},
148 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
149 [DVBT_REG_MON] = {0x00d, 1, 0},
150 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
151 [DVBT_REG_GPE] = {0x00d, 7, 7},
152 [DVBT_REG_GPO] = {0x010, 0, 0},
153 [DVBT_REG_4MSEL] = {0x013, 0, 0},
82041c0a
TM		 154};
155
038c6f24 156static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
82041c0a 157{
6e6aac65 158 struct i2c_client *client = dev->client;
cd559e0b 159 int ret, i;
eec21beb 160 u16 reg_start_addr;
cd559e0b
AP		 161 u8 msb, lsb, reading[4], len;
162 u32 reading_tmp, mask;
82041c0a
TM		 163
164 reg_start_addr = registers[reg].start_address;
165 msb = registers[reg].msb;
166 lsb = registers[reg].lsb;
82041c0a 167 len = (msb >> 3) + 1;
298f18a3 168 mask = REG_MASK(msb - lsb);
82041c0a 169
1cf79db2 170 ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
82041c0a
TM		 171 if (ret)
172 goto err;
173
174 reading_tmp = 0;
175 for (i = 0; i < len; i++)
176 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
177
178 *val = (reading_tmp >> lsb) & mask;
179
cd559e0b 180 return 0;
82041c0a 181err:
6e6aac65 182 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a 183 return ret;
82041c0a
TM		 184}
185
038c6f24 186static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
82041c0a 187{
6e6aac65 188 struct i2c_client *client = dev->client;
82041c0a 189 int ret, i;
eec21beb 190 u16 reg_start_addr;
cd559e0b
AP		 191 u8 msb, lsb, reading[4], writing[4], len;
192 u32 reading_tmp, writing_tmp, mask;
82041c0a
TM		 193
194 reg_start_addr = registers[reg].start_address;
195 msb = registers[reg].msb;
196 lsb = registers[reg].lsb;
82041c0a 197 len = (msb >> 3) + 1;
298f18a3 198 mask = REG_MASK(msb - lsb);
82041c0a 199
1cf79db2 200 ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
82041c0a
TM		 201 if (ret)
202 goto err;
203
204 reading_tmp = 0;
205 for (i = 0; i < len; i++)
206 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
207
208 writing_tmp = reading_tmp & ~(mask << lsb);
209 writing_tmp |= ((val & mask) << lsb);
210
82041c0a
TM		 211 for (i = 0; i < len; i++)
212 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
213
1cf79db2 214 ret = regmap_bulk_write(dev->regmap, reg_start_addr, writing, len);
82041c0a
TM		 215 if (ret)
216 goto err;
217
cd559e0b 218 return 0;
82041c0a 219err:
6e6aac65 220 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a 221 return ret;
82041c0a
TM		 222}
223
884655ad 224static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
82041c0a 225{
038c6f24 226 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 227 struct i2c_client *client = dev->client;
884655ad 228 int ret;
82041c0a 229 u64 pset_iffreq;
884655ad
MCC		 230 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
231
232 /*
233 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
234 * / CrystalFreqHz)
235 */
e1174d78 236 pset_iffreq = if_freq % dev->pdata->clk;
884655ad 237 pset_iffreq *= 0x400000;
e1174d78 238 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
c8832e8f 239 pset_iffreq = -pset_iffreq;
884655ad 240 pset_iffreq = pset_iffreq & 0x3fffff;
6e6aac65
AP		 241 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
242 if_freq, (unsigned)pset_iffreq);
c8832e8f 243
038c6f24 244 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
884655ad 245 if (ret)
cd559e0b 246 goto err;
884655ad 247
038c6f24 248 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
cd559e0b
AP		 249 if (ret)
250 goto err;
884655ad 251
cd559e0b
AP		 252 return 0;
253err:
254 dev_dbg(&client->dev, "failed=%d\n", ret);
3ca2418d 255 return ret;
884655ad
MCC		 256}
257
258static int rtl2832_init(struct dvb_frontend *fe)
259{
038c6f24 260 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 261 struct i2c_client *client = dev->client;
19d273d6 262 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
832cc7cd 263 const struct rtl2832_reg_value *init;
884655ad 264 int i, ret, len;
82041c0a
TM		 265 /* initialization values for the demodulator registers */
266 struct rtl2832_reg_value rtl2832_initial_regs[] = {
267 {DVBT_AD_EN_REG, 0x1},
268 {DVBT_AD_EN_REG1, 0x1},
269 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
270 {DVBT_MGD_THD0, 0x10},
271 {DVBT_MGD_THD1, 0x20},
272 {DVBT_MGD_THD2, 0x20},
273 {DVBT_MGD_THD3, 0x40},
274 {DVBT_MGD_THD4, 0x22},
275 {DVBT_MGD_THD5, 0x32},
276 {DVBT_MGD_THD6, 0x37},
277 {DVBT_MGD_THD7, 0x39},
278 {DVBT_EN_BK_TRK, 0x0},
279 {DVBT_EN_CACQ_NOTCH, 0x0},
280 {DVBT_AD_AV_REF, 0x2a},
281 {DVBT_REG_PI, 0x6},
282 {DVBT_PIP_ON, 0x0},
283 {DVBT_CDIV_PH0, 0x8},
284 {DVBT_CDIV_PH1, 0x8},
285 {DVBT_SCALE1_B92, 0x4},
286 {DVBT_SCALE1_B93, 0xb0},
287 {DVBT_SCALE1_BA7, 0x78},
288 {DVBT_SCALE1_BA9, 0x28},
289 {DVBT_SCALE1_BAA, 0x59},
290 {DVBT_SCALE1_BAB, 0x83},
291 {DVBT_SCALE1_BAC, 0xd4},
292 {DVBT_SCALE1_BB0, 0x65},
293 {DVBT_SCALE1_BB1, 0x43},
294 {DVBT_KB_P1, 0x1},
295 {DVBT_KB_P2, 0x4},
296 {DVBT_KB_P3, 0x7},
297 {DVBT_K1_CR_STEP12, 0xa},
298 {DVBT_REG_GPE, 0x1},
299 {DVBT_SERIAL, 0x0},
300 {DVBT_CDIV_PH0, 0x9},
301 {DVBT_CDIV_PH1, 0x9},
302 {DVBT_MPEG_IO_OPT_2_2, 0x0},
303 {DVBT_MPEG_IO_OPT_1_0, 0x0},
304 {DVBT_TRK_KS_P2, 0x4},
305 {DVBT_TRK_KS_I2, 0x7},
306 {DVBT_TR_THD_SET2, 0x6},
307 {DVBT_TRK_KC_I2, 0x5},
308 {DVBT_CR_THD_SET2, 0x1},
82041c0a
TM		 309 };
310
6e6aac65 311 dev_dbg(&client->dev, "\n");
82041c0a 312
d884acad
AP		 313 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
314 if (ret)
315 goto err;
316
82041c0a 317 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
038c6f24 318 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
82041c0a
TM		 319 rtl2832_initial_regs[i].value);
320 if (ret)
321 goto err;
322 }
323
832cc7cd 324 /* load tuner specific settings */
e1174d78
AP		 325 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
326 dev->pdata->tuner);
327 switch (dev->pdata->tuner) {
f88aae9d
AP		 328 case RTL2832_TUNER_FC2580:
329 len = ARRAY_SIZE(rtl2832_tuner_init_fc2580);
330 init = rtl2832_tuner_init_fc2580;
331 break;
832cc7cd
AP		 332 case RTL2832_TUNER_FC0012:
333 case RTL2832_TUNER_FC0013:
334 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
335 init = rtl2832_tuner_init_fc0012;
336 break;
5db4187a
AP		 337 case RTL2832_TUNER_TUA9001:
338 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
339 init = rtl2832_tuner_init_tua9001;
340 break;
7e688de0
AP		 341 case RTL2832_TUNER_E4000:
342 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
343 init = rtl2832_tuner_init_e4000;
344 break;
fa4bfd2b 345 case RTL2832_TUNER_R820T:
a26758ed 346 case RTL2832_TUNER_R828D:
fa4bfd2b
MCC		 347 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
348 init = rtl2832_tuner_init_r820t;
349 break;
699dcffc
OS		 350 case RTL2832_TUNER_SI2157:
351 len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
352 init = rtl2832_tuner_init_si2157;
353 break;
832cc7cd
AP		 354 default:
355 ret = -EINVAL;
356 goto err;
357 }
358
359 for (i = 0; i < len; i++) {
038c6f24 360 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
832cc7cd
AP		 361 if (ret)
362 goto err;
363 }
364
19d273d6 365 /* init stats here in order signal app which stats are supported */
25ef9f55
AP		 366 c->strength.len = 1;
367 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19d273d6
AP		 368 c->cnr.len = 1;
369 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6b4fd018
AP		 370 c->post_bit_error.len = 1;
371 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
372 c->post_bit_count.len = 1;
373 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
038c6f24 374 dev->sleeping = false;
82041c0a 375
cd559e0b 376 return 0;
82041c0a 377err:
6e6aac65 378 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 379 return ret;
380}
381
382static int rtl2832_sleep(struct dvb_frontend *fe)
383{
038c6f24 384 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 385 struct i2c_client *client = dev->client;
a08c3781 386 int ret;
82041c0a 387
6e6aac65 388 dev_dbg(&client->dev, "\n");
a08c3781 389
038c6f24 390 dev->sleeping = true;
19d273d6 391 dev->fe_status = 0;
a08c3781
AP		 392
393 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
394 if (ret)
395 goto err;
396
82041c0a 397 return 0;
a08c3781
AP		 398err:
399 dev_dbg(&client->dev, "failed=%d\n", ret);
400 return ret;
82041c0a
TM		 401}
402
b0944ea2 403static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
82041c0a
TM		 404 struct dvb_frontend_tune_settings *s)
405{
038c6f24 406 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 407 struct i2c_client *client = dev->client;
298efdd3 408
6e6aac65 409 dev_dbg(&client->dev, "\n");
82041c0a
TM		 410 s->min_delay_ms = 1000;
411 s->step_size = fe->ops.info.frequency_stepsize * 2;
412 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
413 return 0;
414}
415
416static int rtl2832_set_frontend(struct dvb_frontend *fe)
417{
038c6f24 418 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 419 struct i2c_client *client = dev->client;
82041c0a
TM		 420 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
421 int ret, i, j;
422 u64 bw_mode, num, num2;
423 u32 resamp_ratio, cfreq_off_ratio;
82041c0a
TM		 424 static u8 bw_params[3][32] = {
425 /* 6 MHz bandwidth */
426 {
427 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
428 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
429 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
430 0x19, 0xe0,
431 },
432
433 /* 7 MHz bandwidth */
434 {
435 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
436 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
437 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
438 0x19, 0x10,
439 },
440
441 /* 8 MHz bandwidth */
442 {
443 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
444 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
445 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
446 0x19, 0xe0,
447 },
448 };
449
6e6aac65
AP		 450 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
451 c->frequency, c->bandwidth_hz, c->inversion);
82041c0a
TM		 452
453 /* program tuner */
454 if (fe->ops.tuner_ops.set_params)
455 fe->ops.tuner_ops.set_params(fe);
456
fa4bfd2b
MCC		 457 /* If the frontend has get_if_frequency(), use it */
458 if (fe->ops.tuner_ops.get_if_frequency) {
459 u32 if_freq;
fa4bfd2b
MCC		 460
461 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
462 if (ret)
463 goto err;
464
884655ad 465 ret = rtl2832_set_if(fe, if_freq);
fa4bfd2b
MCC		 466 if (ret)
467 goto err;
468 }
469
82041c0a
TM		 470 switch (c->bandwidth_hz) {
471 case 6000000:
472 i = 0;
473 bw_mode = 48000000;
474 break;
475 case 7000000:
476 i = 1;
477 bw_mode = 56000000;
478 break;
479 case 8000000:
480 i = 2;
481 bw_mode = 64000000;
482 break;
483 default:
6e6aac65
AP		 484 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
485 c->bandwidth_hz);
486 ret = -EINVAL;
487 goto err;
82041c0a
TM		 488 }
489
fc4b3fa7 490 for (j = 0; j < sizeof(bw_params[0]); j++) {
1cf79db2
PR		 491 ret = regmap_bulk_write(dev->regmap,
492 0x11c + j, &bw_params[i][j], 1);
82041c0a
TM		 493 if (ret)
494 goto err;
495 }
496
497 /* calculate and set resample ratio
498 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
499 * / ConstWithBandwidthMode)
500 */
e1174d78 501 num = dev->pdata->clk * 7;
82041c0a
TM		 502 num *= 0x400000;
503 num = div_u64(num, bw_mode);
504 resamp_ratio = num & 0x3ffffff;
038c6f24 505 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
82041c0a
TM		 506 if (ret)
507 goto err;
508
509 /* calculate and set cfreq off ratio
510 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
511 * / (CrystalFreqHz * 7))
512 */
513 num = bw_mode << 20;
e1174d78 514 num2 = dev->pdata->clk * 7;
82041c0a
TM		 515 num = div_u64(num, num2);
516 num = -num;
517 cfreq_off_ratio = num & 0xfffff;
038c6f24 518 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
82041c0a
TM		 519 if (ret)
520 goto err;
521
82041c0a 522 /* soft reset */
038c6f24 523 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
82041c0a
TM		 524 if (ret)
525 goto err;
526
038c6f24 527 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
82041c0a
TM		 528 if (ret)
529 goto err;
530
cd559e0b 531 return 0;
82041c0a 532err:
6e6aac65 533 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 534 return ret;
535}
536
7e3e68bc
MCC		 537static int rtl2832_get_frontend(struct dvb_frontend *fe,
538 struct dtv_frontend_properties *c)
0ce67a2a 539{
038c6f24 540 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 541 struct i2c_client *client = dev->client;
0ce67a2a
AP		 542 int ret;
543 u8 buf[3];
544
038c6f24 545 if (dev->sleeping)
0ce67a2a
AP		 546 return 0;
547
1cf79db2 548 ret = regmap_bulk_read(dev->regmap, 0x33c, buf, 2);
0ce67a2a
AP		 549 if (ret)
550 goto err;
551
1cf79db2 552 ret = regmap_bulk_read(dev->regmap, 0x351, &buf[2], 1);
0ce67a2a
AP		 553 if (ret)
554 goto err;
555
6e6aac65 556 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
0ce67a2a
AP		 557
558 switch ((buf[0] >> 2) & 3) {
559 case 0:
560 c->modulation = QPSK;
561 break;
562 case 1:
563 c->modulation = QAM_16;
564 break;
565 case 2:
566 c->modulation = QAM_64;
567 break;
568 }
569
570 switch ((buf[2] >> 2) & 1) {
571 case 0:
572 c->transmission_mode = TRANSMISSION_MODE_2K;
573 break;
574 case 1:
575 c->transmission_mode = TRANSMISSION_MODE_8K;
576 }
577
578 switch ((buf[2] >> 0) & 3) {
579 case 0:
580 c->guard_interval = GUARD_INTERVAL_1_32;
581 break;
582 case 1:
583 c->guard_interval = GUARD_INTERVAL_1_16;
584 break;
585 case 2:
586 c->guard_interval = GUARD_INTERVAL_1_8;
587 break;
588 case 3:
589 c->guard_interval = GUARD_INTERVAL_1_4;
590 break;
591 }
592
593 switch ((buf[0] >> 4) & 7) {
594 case 0:
595 c->hierarchy = HIERARCHY_NONE;
596 break;
597 case 1:
598 c->hierarchy = HIERARCHY_1;
599 break;
600 case 2:
601 c->hierarchy = HIERARCHY_2;
602 break;
603 case 3:
604 c->hierarchy = HIERARCHY_4;
605 break;
606 }
607
608 switch ((buf[1] >> 3) & 7) {
609 case 0:
610 c->code_rate_HP = FEC_1_2;
611 break;
612 case 1:
613 c->code_rate_HP = FEC_2_3;
614 break;
615 case 2:
616 c->code_rate_HP = FEC_3_4;
617 break;
618 case 3:
619 c->code_rate_HP = FEC_5_6;
620 break;
621 case 4:
622 c->code_rate_HP = FEC_7_8;
623 break;
624 }
625
626 switch ((buf[1] >> 0) & 7) {
627 case 0:
628 c->code_rate_LP = FEC_1_2;
629 break;
630 case 1:
631 c->code_rate_LP = FEC_2_3;
632 break;
633 case 2:
634 c->code_rate_LP = FEC_3_4;
635 break;
636 case 3:
637 c->code_rate_LP = FEC_5_6;
638 break;
639 case 4:
640 c->code_rate_LP = FEC_7_8;
641 break;
642 }
643
644 return 0;
645err:
6e6aac65 646 dev_dbg(&client->dev, "failed=%d\n", ret);
0ce67a2a
AP		 647 return ret;
648}
649
0df289a2 650static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status)
82041c0a 651{
038c6f24 652 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 653 struct i2c_client *client = dev->client;
426508e6 654 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
82041c0a 655 int ret;
20357756 656 u32 uninitialized_var(tmp);
426508e6
AP		 657 u8 u8tmp, buf[2];
658 u16 u16tmp;
82041c0a 659
6e6aac65
AP		 660 dev_dbg(&client->dev, "\n");
661
662 *status = 0;
038c6f24 663 if (dev->sleeping)
82041c0a
TM		 664 return 0;
665
038c6f24 666 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
82041c0a
TM		 667 if (ret)
668 goto err;
669
670 if (tmp == 11) {
671 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
672 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1c7da405 673 } else if (tmp == 10) {
82041c0a
TM		 674 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
675 FE_HAS_VITERBI;
1c7da405 676 }
82041c0a 677
19d273d6 678 dev->fe_status = *status;
19d273d6 679
25ef9f55
AP		 680 /* signal strength */
681 if (dev->fe_status & FE_HAS_SIGNAL) {
682 /* read digital AGC */
1cf79db2 683 ret = regmap_bulk_read(dev->regmap, 0x305, &u8tmp, 1);
25ef9f55
AP		 684 if (ret)
685 goto err;
686
687 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
688
689 u8tmp = ~u8tmp;
690 u16tmp = u8tmp << 8 | u8tmp << 0;
691
692 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
693 c->strength.stat[0].uvalue = u16tmp;
694 } else {
695 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
696 }
697
19d273d6
AP		 698 /* CNR */
699 if (dev->fe_status & FE_HAS_VITERBI) {
700 unsigned hierarchy, constellation;
701 #define CONSTELLATION_NUM 3
702 #define HIERARCHY_NUM 4
703 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
704 {85387325, 85387325, 85387325, 85387325},
705 {86676178, 86676178, 87167949, 87795660},
706 {87659938, 87659938, 87885178, 88241743},
707 };
708
1cf79db2 709 ret = regmap_bulk_read(dev->regmap, 0x33c, &u8tmp, 1);
19d273d6
AP		 710 if (ret)
711 goto err;
712
713 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
714 if (constellation > CONSTELLATION_NUM - 1)
426508e6 715 goto err;
19d273d6
AP		 716
717 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
718 if (hierarchy > HIERARCHY_NUM - 1)
426508e6 719 goto err;
19d273d6 720
1cf79db2 721 ret = regmap_bulk_read(dev->regmap, 0x40c, buf, 2);
19d273d6
AP		 722 if (ret)
723 goto err;
724
725 u16tmp = buf[0] << 8 | buf[1] << 0;
726 if (u16tmp)
727 tmp = (constant[constellation][hierarchy] -
728 intlog10(u16tmp)) / ((1 << 24) / 10000);
729 else
730 tmp = 0;
731
732 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
733
734 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
735 c->cnr.stat[0].svalue = tmp;
736 } else {
737 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
738 }
739
6b4fd018
AP		 740 /* BER */
741 if (dev->fe_status & FE_HAS_LOCK) {
1cf79db2 742 ret = regmap_bulk_read(dev->regmap, 0x34e, buf, 2);
6b4fd018
AP		 743 if (ret)
744 goto err;
745
746 u16tmp = buf[0] << 8 | buf[1] << 0;
747 dev->post_bit_error += u16tmp;
748 dev->post_bit_count += 1000000;
749
750 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
751
752 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
753 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
754 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
755 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
756 } else {
757 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
758 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
759 }
760
426508e6 761 return 0;
19d273d6
AP		 762err:
763 dev_dbg(&client->dev, "failed=%d\n", ret);
426508e6
AP		 764 return ret;
765}
766
767static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
768{
769 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
770
771 /* report SNR in resolution of 0.1 dB */
772 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
773 *snr = div_s64(c->cnr.stat[0].svalue, 100);
774 else
775 *snr = 0;
776
777 return 0;
778}
779
780static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
781{
782 struct rtl2832_dev *dev = fe->demodulator_priv;
783
784 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
785 dev->post_bit_error_prev = dev->post_bit_error;
786
787 return 0;
19d273d6
AP		 788}
789
92d20d9f 790/*
d1016581 791 * I2C gate/mux/repeater logic
d1016581
AP		 792 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
793 * is delayed here a little bit in order to see if there is sequence of I2C
92d20d9f 794 * messages sent to same I2C bus.
92d20d9f
AP		 795 */
796static void rtl2832_i2c_gate_work(struct work_struct *work)
797{
d1016581 798 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
6e6aac65 799 struct i2c_client *client = dev->client;
92d20d9f 800 int ret;
6e6aac65 801
d1016581 802 /* close gate */
1cf79db2 803 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x00);
d1016581 804 if (ret)
92d20d9f
AP		 805 goto err;
806
92d20d9f
AP		 807 return;
808err:
6e6aac65 809 dev_dbg(&client->dev, "failed=%d\n", ret);
92d20d9f
AP		 810}
811
cddcc40b 812static int rtl2832_select(struct i2c_mux_core *muxc, u32 chan_id)
8823f028 813{
cddcc40b 814 struct rtl2832_dev *dev = i2c_mux_priv(muxc);
6e6aac65 815 struct i2c_client *client = dev->client;
0ea872d4 816 int ret;
92d20d9f
AP		 817
818 /* terminate possible gate closing */
d1016581 819 cancel_delayed_work(&dev->i2c_gate_work);
8823f028 820
1cf79db2 821 /* open gate */
0d117901 822 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
d1016581 823 if (ret)
0ea872d4
AP		 824 goto err;
825
0ea872d4
AP		 826 return 0;
827err:
6e6aac65 828 dev_dbg(&client->dev, "failed=%d\n", ret);
d1016581 829 return ret;
8823f028
AP		 830}
831
cddcc40b 832static int rtl2832_deselect(struct i2c_mux_core *muxc, u32 chan_id)
92d20d9f 833{
cddcc40b 834 struct rtl2832_dev *dev = i2c_mux_priv(muxc);
6e6aac65 835
038c6f24 836 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
92d20d9f
AP		 837 return 0;
838}
839
82041c0a
TM		 840static struct dvb_frontend_ops rtl2832_ops = {
841 .delsys = { SYS_DVBT },
842 .info = {
843 .name = "Realtek RTL2832 (DVB-T)",
844 .frequency_min = 174000000,
845 .frequency_max = 862000000,
846 .frequency_stepsize = 166667,
847 .caps = FE_CAN_FEC_1_2 |
848 FE_CAN_FEC_2_3 |
849 FE_CAN_FEC_3_4 |
850 FE_CAN_FEC_5_6 |
851 FE_CAN_FEC_7_8 |
852 FE_CAN_FEC_AUTO |
853 FE_CAN_QPSK |
854 FE_CAN_QAM_16 |
855 FE_CAN_QAM_64 |
856 FE_CAN_QAM_AUTO |
857 FE_CAN_TRANSMISSION_MODE_AUTO |
858 FE_CAN_GUARD_INTERVAL_AUTO |
859 FE_CAN_HIERARCHY_AUTO |
860 FE_CAN_RECOVER |
861 FE_CAN_MUTE_TS
862 },
863
82041c0a
TM		 864 .init = rtl2832_init,
865 .sleep = rtl2832_sleep,
866
867 .get_tune_settings = rtl2832_get_tune_settings,
868
869 .set_frontend = rtl2832_set_frontend,
0ce67a2a 870 .get_frontend = rtl2832_get_frontend,
82041c0a
TM		 871
872 .read_status = rtl2832_read_status,
73983497 873 .read_snr = rtl2832_read_snr,
db32d74a 874 .read_ber = rtl2832_read_ber,
82041c0a
TM		 875};
876
dcadb82a
AP		 877static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
878{
879 switch (reg) {
880 case 0x305:
881 case 0x33c:
882 case 0x34e:
883 case 0x351:
884 case 0x40c ... 0x40d:
885 return true;
886 default:
887 break;
888 }
889
890 return false;
891}
892
6f5f6ee2
AP		 893static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
894{
038c6f24 895 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 896
897 dev_dbg(&client->dev, "\n");
898 return &dev->fe;
899}
900
cd559e0b 901static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
6f5f6ee2 902{
038c6f24 903 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 904
905 dev_dbg(&client->dev, "\n");
cddcc40b 906 return dev->muxc->adapter[0];
6f5f6ee2
AP		 907}
908
d884acad 909static int rtl2832_slave_ts_ctrl(struct i2c_client *client, bool enable)
6f5f6ee2 910{
038c6f24 911 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 912 int ret;
913
d884acad 914 dev_dbg(&client->dev, "enable=%d\n", enable);
6f5f6ee2 915
d884acad
AP		 916 if (enable) {
917 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
918 if (ret)
919 goto err;
1cf79db2 920 ret = regmap_bulk_write(dev->regmap, 0x10c, "\x5f\xff", 2);
d884acad
AP		 921 if (ret)
922 goto err;
923 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
924 if (ret)
925 goto err;
1cf79db2 926 ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x18", 1);
d884acad
AP		 927 if (ret)
928 goto err;
1cf79db2 929 ret = regmap_bulk_write(dev->regmap, 0x192, "\x7f\xf7\xff", 3);
d884acad
AP		 930 if (ret)
931 goto err;
932 } else {
1cf79db2 933 ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\x0f\xff", 3);
d884acad
AP		 934 if (ret)
935 goto err;
1cf79db2 936 ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x08", 1);
d884acad
AP		 937 if (ret)
938 goto err;
939 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x0);
940 if (ret)
941 goto err;
1cf79db2 942 ret = regmap_bulk_write(dev->regmap, 0x10c, "\x00\x00", 2);
d884acad
AP		 943 if (ret)
944 goto err;
945 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
946 if (ret)
947 goto err;
948 }
6f5f6ee2 949
d10f89cc
MB		 950 dev->slave_ts = enable;
951
6f5f6ee2
AP		 952 return 0;
953err:
954 dev_dbg(&client->dev, "failed=%d\n", ret);
955 return ret;
956}
957
4b01e01a
AP		 958static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
959{
960 struct rtl2832_dev *dev = fe->demodulator_priv;
961 struct i2c_client *client = dev->client;
962 int ret;
963 u8 u8tmp;
964
d10f89cc 965 dev_dbg(&client->dev, "onoff=%d, slave_ts=%d\n", onoff, dev->slave_ts);
4b01e01a
AP		 966
967 /* enable / disable PID filter */
968 if (onoff)
969 u8tmp = 0x80;
970 else
971 u8tmp = 0x00;
972
d10f89cc
MB		 973 if (dev->slave_ts)
974 ret = regmap_update_bits(dev->regmap, 0x021, 0xc0, u8tmp);
975 else
976 ret = regmap_update_bits(dev->regmap, 0x061, 0xc0, u8tmp);
4b01e01a
AP		 977 if (ret)
978 goto err;
979
980 return 0;
981err:
982 dev_dbg(&client->dev, "failed=%d\n", ret);
983 return ret;
984}
985
986static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
987 int onoff)
988{
989 struct rtl2832_dev *dev = fe->demodulator_priv;
990 struct i2c_client *client = dev->client;
991 int ret;
992 u8 buf[4];
993
d10f89cc
MB		 994 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d slave_ts=%d\n",
995 index, pid, onoff, dev->slave_ts);
4b01e01a
AP		 996
997 /* skip invalid PIDs (0x2000) */
998 if (pid > 0x1fff || index > 32)
999 return 0;
1000
1001 if (onoff)
1002 set_bit(index, &dev->filters);
1003 else
1004 clear_bit(index, &dev->filters);
1005
1006 /* enable / disable PIDs */
1007 buf[0] = (dev->filters >> 0) & 0xff;
1008 buf[1] = (dev->filters >> 8) & 0xff;
1009 buf[2] = (dev->filters >> 16) & 0xff;
1010 buf[3] = (dev->filters >> 24) & 0xff;
d10f89cc
MB		 1011
1012 if (dev->slave_ts)
1013 ret = regmap_bulk_write(dev->regmap, 0x022, buf, 4);
1014 else
1015 ret = regmap_bulk_write(dev->regmap, 0x062, buf, 4);
4b01e01a
AP		 1016 if (ret)
1017 goto err;
1018
1019 /* add PID */
1020 buf[0] = (pid >> 8) & 0xff;
1021 buf[1] = (pid >> 0) & 0xff;
d10f89cc
MB		 1022
1023 if (dev->slave_ts)
1024 ret = regmap_bulk_write(dev->regmap, 0x026 + 2 * index, buf, 2);
1025 else
1026 ret = regmap_bulk_write(dev->regmap, 0x066 + 2 * index, buf, 2);
4b01e01a
AP		 1027 if (ret)
1028 goto err;
1029
1030 return 0;
1031err:
1032 dev_dbg(&client->dev, "failed=%d\n", ret);
1033 return ret;
1034}
1035
c2c8386f
AP		 1036static int rtl2832_probe(struct i2c_client *client,
1037 const struct i2c_device_id *id)
1038{
1039 struct rtl2832_platform_data *pdata = client->dev.platform_data;
c2c8386f 1040 struct i2c_adapter *i2c = client->adapter;
038c6f24 1041 struct rtl2832_dev *dev;
c2c8386f
AP		 1042 int ret;
1043 u8 tmp;
d1016581
AP		 1044 static const struct regmap_range_cfg regmap_range_cfg[] = {
1045 {
1046 .selector_reg = 0x00,
1047 .selector_mask = 0xff,
1048 .selector_shift = 0,
1049 .window_start = 0,
1050 .window_len = 0x100,
1051 .range_min = 0 * 0x100,
1052 .range_max = 5 * 0x100,
1053 },
1054 };
c2c8386f
AP		 1055
1056 dev_dbg(&client->dev, "\n");
1057
c2c8386f 1058 /* allocate memory for the internal state */
038c6f24
AP		 1059 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1060 if (dev == NULL) {
c2c8386f
AP		 1061 ret = -ENOMEM;
1062 goto err;
1063 }
1064
038c6f24 1065 /* setup the state */
d1016581 1066 i2c_set_clientdata(client, dev);
038c6f24 1067 dev->client = client;
e1174d78 1068 dev->pdata = client->dev.platform_data;
038c6f24 1069 dev->sleeping = true;
038c6f24 1070 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
d1016581 1071 /* create regmap */
b410dae4
AP		 1072 dev->regmap_config.reg_bits = 8,
1073 dev->regmap_config.val_bits = 8,
b410dae4
AP		 1074 dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
1075 dev->regmap_config.max_register = 5 * 0x100,
1076 dev->regmap_config.ranges = regmap_range_cfg,
1077 dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
b3b2bf82 1078 dev->regmap_config.cache_type = REGCACHE_NONE,
1cf79db2 1079 dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
d1016581
AP		 1080 if (IS_ERR(dev->regmap)) {
1081 ret = PTR_ERR(dev->regmap);
1082 goto err_kfree;
1083 }
c2c8386f
AP		 1084
1085 /* check if the demod is there */
1cf79db2 1086 ret = regmap_bulk_read(dev->regmap, 0x000, &tmp, 1);
c2c8386f 1087 if (ret)
0d117901 1088 goto err_regmap_exit;
c2c8386f
AP		 1089
1090 /* create muxed i2c adapter for demod tuner bus */
1cf79db2 1091 dev->muxc = i2c_mux_alloc(i2c, &i2c->dev, 1, 0, I2C_MUX_LOCKED,
cddcc40b
PR		 1092 rtl2832_select, rtl2832_deselect);
1093 if (!dev->muxc) {
1094 ret = -ENOMEM;
0d117901 1095 goto err_regmap_exit;
c2c8386f 1096 }
cddcc40b
PR		 1097 dev->muxc->priv = dev;
1098 ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1099 if (ret)
1100 goto err_regmap_exit;
c2c8386f
AP		 1101
1102 /* create dvb_frontend */
038c6f24
AP		 1103 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1104 dev->fe.demodulator_priv = dev;
6f5f6ee2
AP		 1105
1106 /* setup callbacks */
1107 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
cd559e0b 1108 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
d884acad 1109 pdata->slave_ts_ctrl = rtl2832_slave_ts_ctrl;
4b01e01a
AP		 1110 pdata->pid_filter = rtl2832_pid_filter;
1111 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1cf79db2 1112 pdata->regmap = dev->regmap;
c2c8386f
AP		 1113
1114 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1115 return 0;
d1016581
AP		 1116err_regmap_exit:
1117 regmap_exit(dev->regmap);
c2c8386f 1118err_kfree:
038c6f24 1119 kfree(dev);
c2c8386f
AP		 1120err:
1121 dev_dbg(&client->dev, "failed=%d\n", ret);
1122 return ret;
1123}
1124
1125static int rtl2832_remove(struct i2c_client *client)
1126{
038c6f24 1127 struct rtl2832_dev *dev = i2c_get_clientdata(client);
c2c8386f
AP		 1128
1129 dev_dbg(&client->dev, "\n");
1130
038c6f24 1131 cancel_delayed_work_sync(&dev->i2c_gate_work);
c2c8386f 1132
cddcc40b 1133 i2c_mux_del_adapters(dev->muxc);
c2c8386f 1134
d1016581
AP		 1135 regmap_exit(dev->regmap);
1136
038c6f24 1137 kfree(dev);
c2c8386f
AP		 1138
1139 return 0;
1140}
1141
1142static const struct i2c_device_id rtl2832_id_table[] = {
1143 {"rtl2832", 0},
1144 {}
1145};
1146MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1147
1148static struct i2c_driver rtl2832_driver = {
1149 .driver = {
c2c8386f 1150 .name = "rtl2832",
678fdb68 1151 .suppress_bind_attrs = true,
c2c8386f
AP		 1152 },
1153 .probe = rtl2832_probe,
1154 .remove = rtl2832_remove,
1155 .id_table = rtl2832_id_table,
1156};
1157
1158module_i2c_driver(rtl2832_driver);
1159
82041c0a 1160MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
75c24005 1161MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
82041c0a
TM		 1162MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1163MODULE_LICENSE("GPL");
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