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c942fddf | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
3e54a169 | 2 | /* |
7dbbb4bf MS |
3 | * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator |
4 | * | |
5 | * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> | |
7dbbb4bf | 6 | */ |
3e54a169 MS |
7 | |
8 | #ifndef _DVB_SI2165_PRIV | |
9 | #define _DVB_SI2165_PRIV | |
10 | ||
55bea400 | 11 | #define SI2165_FIRMWARE_REV_D "dvb-demod-si2165.fw" |
3e54a169 | 12 | |
81fd533a MS |
13 | struct si2165_config { |
14 | /* i2c addr | |
7dbbb4bf MS |
15 | * possible values: 0x64,0x65,0x66,0x67 |
16 | */ | |
81fd533a MS |
17 | u8 i2c_addr; |
18 | ||
19 | /* external clock or XTAL */ | |
20 | u8 chip_mode; | |
21 | ||
22 | /* frequency of external clock or xtal in Hz | |
23 | * possible values: 4000000, 16000000, 20000000, 240000000, 27000000 | |
24 | */ | |
7dbbb4bf | 25 | u32 ref_freq_hz; |
81fd533a MS |
26 | |
27 | /* invert the spectrum */ | |
28 | bool inversion; | |
29 | }; | |
30 | ||
964b3727 MS |
31 | #define STATISTICS_PERIOD_PKT_COUNT 30000u |
32 | #define STATISTICS_PERIOD_BIT_COUNT (STATISTICS_PERIOD_PKT_COUNT * 204 * 8) | |
33 | ||
814f86c9 MS |
34 | #define REG_CHIP_MODE 0x0000 |
35 | #define REG_CHIP_REVCODE 0x0023 | |
36 | #define REV_CHIP_TYPE 0x0118 | |
37 | #define REG_CHIP_INIT 0x0050 | |
38 | #define REG_INIT_DONE 0x0054 | |
39 | #define REG_START_INIT 0x0096 | |
40 | #define REG_PLL_DIVL 0x00a0 | |
41 | #define REG_RST_ALL 0x00c0 | |
42 | #define REG_LOCK_TIMEOUT 0x00c4 | |
43 | #define REG_AUTO_RESET 0x00cb | |
44 | #define REG_OVERSAMP 0x00e4 | |
45 | #define REG_IF_FREQ_SHIFT 0x00e8 | |
46 | #define REG_DVB_STANDARD 0x00ec | |
47 | #define REG_DSP_CLOCK 0x0104 | |
48 | #define REG_ADC_RI8 0x0123 | |
49 | #define REG_ADC_RI1 0x012a | |
50 | #define REG_ADC_RI2 0x012b | |
51 | #define REG_ADC_RI3 0x012c | |
52 | #define REG_ADC_RI4 0x012d | |
53 | #define REG_ADC_RI5 0x012e | |
54 | #define REG_ADC_RI6 0x012f | |
55 | #define REG_AGC_CRESTF_DBX8 0x0150 | |
56 | #define REG_AGC_UNFREEZE_THR 0x015b | |
57 | #define REG_AGC2_MIN 0x016e | |
58 | #define REG_AGC2_KACQ 0x016c | |
59 | #define REG_AGC2_KLOC 0x016d | |
60 | #define REG_AGC2_OUTPUT 0x0170 | |
61 | #define REG_AGC2_CLKDIV 0x0171 | |
62 | #define REG_AGC_IF_TRI 0x018b | |
63 | #define REG_AGC_IF_SLR 0x0190 | |
64 | #define REG_AAF_CRESTF_DBX8 0x01a0 | |
65 | #define REG_ACI_CRESTF_DBX8 0x01c8 | |
66 | #define REG_SWEEP_STEP 0x0232 | |
67 | #define REG_KP_LOCK 0x023a | |
68 | #define REG_UNKNOWN_24C 0x024c | |
69 | #define REG_CENTRAL_TAP 0x0261 | |
c0675d0b | 70 | #define REG_C_N 0x026c |
814f86c9 MS |
71 | #define REG_EQ_AUTO_CONTROL 0x0278 |
72 | #define REG_UNKNOWN_27C 0x027c | |
73 | #define REG_START_SYNCHRO 0x02e0 | |
74 | #define REG_REQ_CONSTELLATION 0x02f4 | |
75 | #define REG_T_BANDWIDTH 0x0308 | |
76 | #define REG_FREQ_SYNC_RANGE 0x030c | |
77 | #define REG_IMPULSIVE_NOISE_REM 0x031c | |
78 | #define REG_WDOG_AND_BOOT 0x0341 | |
79 | #define REG_PATCH_VERSION 0x0344 | |
80 | #define REG_ADDR_JUMP 0x0348 | |
81 | #define REG_UNKNOWN_350 0x0350 | |
82 | #define REG_EN_RST_ERROR 0x035c | |
83 | #define REG_DCOM_CONTROL_BYTE 0x0364 | |
84 | #define REG_DCOM_ADDR 0x0368 | |
85 | #define REG_DCOM_DATA 0x036c | |
86 | #define REG_RST_CRC 0x0379 | |
87 | #define REG_GP_REG0_LSB 0x0384 | |
88 | #define REG_GP_REG0_MSB 0x0387 | |
89 | #define REG_CRC 0x037a | |
1e5fde1b | 90 | #define REG_CHECK_SIGNAL 0x03a8 |
964b3727 MS |
91 | #define REG_CBER_RST 0x0424 |
92 | #define REG_CBER_BIT 0x0428 | |
93 | #define REG_CBER_ERR 0x0430 | |
94 | #define REG_CBER_AVAIL 0x0434 | |
1e5fde1b | 95 | #define REG_PS_LOCK 0x0440 |
964b3727 MS |
96 | #define REG_UNCOR_CNT 0x0468 |
97 | #define REG_BER_RST 0x046c | |
814f86c9 | 98 | #define REG_BER_PKT 0x0470 |
964b3727 MS |
99 | #define REG_BER_BIT 0x0478 |
100 | #define REG_BER_AVAIL 0x047c | |
814f86c9 MS |
101 | #define REG_FEC_LOCK 0x04e0 |
102 | #define REG_TS_DATA_MODE 0x04e4 | |
103 | #define REG_TS_CLK_MODE 0x04e5 | |
104 | #define REG_TS_TRI 0x04ef | |
105 | #define REG_TS_SLR 0x04f4 | |
106 | #define REG_RSSI_ENABLE 0x0641 | |
107 | #define REG_RSSI_PAD_CTRL 0x0646 | |
108 | #define REG_TS_PARALLEL_MODE 0x08f8 | |
109 | ||
3e54a169 | 110 | #endif /* _DVB_SI2165_PRIV */ |