[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb-frontends / ts2020.c

/*
    Montage Technology TS2020 - Silicon Tuner driver
    Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>

    Copyright (C) 2009-2012 TurboSight.com

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include "dvb_frontend.h"
#include "ts2020.h"

#define TS2020_XTAL_FREQ   27000 /* in kHz */
#define FREQ_OFFSET_LOW_SYM_RATE 3000

struct ts2020_priv {
	/* i2c details */
	int i2c_address;
	struct i2c_adapter *i2c;
	u8 clk_out_div;
	u32 frequency;
};

static int ts2020_release(struct dvb_frontend *fe)
{
	kfree(fe->tuner_priv);
	fe->tuner_priv = NULL;
	return 0;
}

static int ts2020_writereg(struct dvb_frontend *fe, int reg, int data)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	u8 buf[] = { reg, data };
	struct i2c_msg msg[] = {
		{
			.addr = priv->i2c_address,
			.flags = 0,
			.buf = buf,
			.len = 2
		}
	};
	int err;

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	err = i2c_transfer(priv->i2c, msg, 1);
	if (err != 1) {
		printk(KERN_ERR
		       "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
		       __func__, err, reg, data);
		return -EREMOTEIO;
	}

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	return 0;
}

static int ts2020_readreg(struct dvb_frontend *fe, u8 reg)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = {
		{
			.addr = priv->i2c_address,
			.flags = 0,
			.buf = b0,
			.len = 1
		}, {
			.addr = priv->i2c_address,
			.flags = I2C_M_RD,
			.buf = b1,
			.len = 1
		}
	};

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	ret = i2c_transfer(priv->i2c, msg, 2);

	if (ret != 2) {
		printk(KERN_ERR "%s: reg=0x%x(error=%d)\n",
		       __func__, reg, ret);
		return ret;
	}

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	return b1[0];
}

static int ts2020_sleep(struct dvb_frontend *fe)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u8 buf[] = { 10, 0 };
	struct i2c_msg msg = {
		.addr = priv->i2c_address,
		.flags = 0,
		.buf = buf,
		.len = 2
	};

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 1);

	ret = i2c_transfer(priv->i2c, &msg, 1);
	if (ret != 1)
		printk(KERN_ERR "%s: i2c error\n", __func__);

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	return (ret == 1) ? 0 : ret;
}

static int ts2020_init(struct dvb_frontend *fe)
{
	struct ts2020_priv *priv = fe->tuner_priv;

	ts2020_writereg(fe, 0x42, 0x73);
	ts2020_writereg(fe, 0x05, priv->clk_out_div);
	ts2020_writereg(fe, 0x20, 0x27);
	ts2020_writereg(fe, 0x07, 0x02);
	ts2020_writereg(fe, 0x11, 0xff);
	ts2020_writereg(fe, 0x60, 0xf9);
	ts2020_writereg(fe, 0x08, 0x01);
	ts2020_writereg(fe, 0x00, 0x41);

	return 0;
}

static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
{
	int ret;
	ret = ts2020_writereg(fe, 0x51, 0x1f - offset);
	ret |= ts2020_writereg(fe, 0x51, 0x1f);
	ret |= ts2020_writereg(fe, 0x50, offset);
	ret |= ts2020_writereg(fe, 0x50, 0x00);
	msleep(20);
	return ret;
}

static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
{
	int reg;

	reg = ts2020_readreg(fe, 0x3d);
	reg &= 0x7f;
	if (reg < 0x16)
		reg = 0xa1;
	else if (reg == 0x16)
		reg = 0x99;
	else
		reg = 0xf9;

	ts2020_writereg(fe, 0x60, reg);
	reg = ts2020_tuner_gate_ctrl(fe, 0x08);

	return reg;
}

static int ts2020_set_params(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u32 frequency = c->frequency;
	s32 offset_khz;
	u32 symbol_rate = (c->symbol_rate / 1000);
	u32 f3db, gdiv28;
	u16 value, ndiv, lpf_coeff;
	u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
	u8 lo = 0x01, div4 = 0x0;

	/* Calculate frequency divider */
	if (frequency < 1060000) {
		lo |= 0x10;
		div4 = 0x1;
		ndiv = (frequency * 14 * 4) / TS2020_XTAL_FREQ;
	} else
		ndiv = (frequency * 14 * 2) / TS2020_XTAL_FREQ;
	ndiv = ndiv + ndiv % 2;
	ndiv = ndiv - 1024;

	ret = ts2020_writereg(fe, 0x10, 0x80 | lo);

	/* Set frequency divider */
	ret |= ts2020_writereg(fe, 0x01, (ndiv >> 8) & 0xf);
	ret |= ts2020_writereg(fe, 0x02, ndiv & 0xff);

	ret |= ts2020_writereg(fe, 0x03, 0x06);
	ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
	if (ret < 0)
		return -ENODEV;

	/* Tuner Frequency Range */
	ret = ts2020_writereg(fe, 0x10, lo);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x08);

	/* Tuner RF */
	ret |= ts2020_set_tuner_rf(fe);

	gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
	ret |= ts2020_writereg(fe, 0x04, gdiv28 & 0xff);
	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
	if (ret < 0)
		return -ENODEV;

	value = ts2020_readreg(fe, 0x26);

	f3db = (symbol_rate * 135) / 200 + 2000;
	f3db += FREQ_OFFSET_LOW_SYM_RATE;
	if (f3db < 7000)
		f3db = 7000;
	if (f3db > 40000)
		f3db = 40000;

	gdiv28 = gdiv28 * 207 / (value * 2 + 151);
	mlpf_max = gdiv28 * 135 / 100;
	mlpf_min = gdiv28 * 78 / 100;
	if (mlpf_max > 63)
		mlpf_max = 63;

	lpf_coeff = 2766;

	nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
		(TS2020_XTAL_FREQ / 1000)  + 1) / 2;
	if (nlpf > 23)
		nlpf = 23;
	if (nlpf < 1)
		nlpf = 1;

	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
		* lpf_coeff * 2  / f3db + 1) / 2;

	if (lpf_mxdiv < mlpf_min) {
		nlpf++;
		lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
			* lpf_coeff * 2  / f3db + 1) / 2;
	}

	if (lpf_mxdiv > mlpf_max)
		lpf_mxdiv = mlpf_max;

	ret = ts2020_writereg(fe, 0x04, lpf_mxdiv);
	ret |= ts2020_writereg(fe, 0x06, nlpf);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x01);

	msleep(80);
	/* calculate offset assuming 96000kHz*/
	offset_khz = (ndiv - ndiv % 2 + 1024) * TS2020_XTAL_FREQ
		/ (6 + 8) / (div4 + 1) / 2;

	priv->frequency = offset_khz;

	return (ret < 0) ? -EINVAL : 0;
}

static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	*frequency = priv->frequency;
	return 0;
}

/* read TS2020 signal strength */
static int ts2020_read_signal_strength(struct dvb_frontend *fe,
						u16 *signal_strength)
{
	u16 sig_reading, sig_strength;
	u8 rfgain, bbgain;

	rfgain = ts2020_readreg(fe, 0x3d) & 0x1f;
	bbgain = ts2020_readreg(fe, 0x21) & 0x1f;

	if (rfgain > 15)
		rfgain = 15;
	if (bbgain > 13)
		bbgain = 13;

	sig_reading = rfgain * 2 + bbgain * 3;

	sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;

	/* cook the value to be suitable for szap-s2 human readable output */
	*signal_strength = sig_strength * 1000;

	return 0;
}

static struct dvb_tuner_ops ts2020_tuner_ops = {
	.info = {
		.name = "TS2020",
		.frequency_min = 950000,
		.frequency_max = 2150000
	},
	.init = ts2020_init,
	.release = ts2020_release,
	.sleep = ts2020_sleep,
	.set_params = ts2020_set_params,
	.get_frequency = ts2020_get_frequency,
	.get_rf_strength = ts2020_read_signal_strength,
};

struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
					const struct ts2020_config *config,
					struct i2c_adapter *i2c)
{
	struct ts2020_priv *priv = NULL;
	u8 buf;

	priv = kzalloc(sizeof(struct ts2020_priv), GFP_KERNEL);
	if (priv == NULL)
		return NULL;

	priv->i2c_address = config->tuner_address;
	priv->i2c = i2c;
	priv->clk_out_div = config->clk_out_div;
	fe->tuner_priv = priv;

	/* Wake Up the tuner */
	if ((0x03 & ts2020_readreg(fe, 0x00)) == 0x00) {
		ts2020_writereg(fe, 0x00, 0x01);
		msleep(2);
	}

	ts2020_writereg(fe, 0x00, 0x03);
	msleep(2);

	/* Check the tuner version */
	buf = ts2020_readreg(fe, 0x00);
	if ((buf == 0x01) || (buf == 0x41) || (buf == 0x81))
		printk(KERN_INFO "%s: Find tuner TS2020!\n", __func__);
	else {
		printk(KERN_ERR "%s: Read tuner reg[0] = %d\n", __func__, buf);
		kfree(priv);
		return NULL;
	}

	memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
				sizeof(struct dvb_tuner_ops));

	return fe;
}
EXPORT_SYMBOL(ts2020_attach);

MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
MODULE_LICENSE("GPL");
Commit	Line	Data
6fef4fc7 KD	1	/*
	2	Montage Technology TS2020 - Silicon Tuner driver
	3	Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
	4
	5	Copyright (C) 2009-2012 TurboSight.com
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#include "dvb_frontend.h"
	23	#include "ts2020.h"
	24
	25	#define TS2020_XTAL_FREQ 27000 /* in kHz */
b858c331	26	#define FREQ_OFFSET_LOW_SYM_RATE 3000
6fef4fc7	27
b858c331 IL	28	struct ts2020_priv {
	29	/* i2c details */
	30	int i2c_address;
6fef4fc7	31	struct i2c_adapter *i2c;
b858c331 IL	32	u8 clk_out_div;
b858c331 IL	33	u32 frequency;
6fef4fc7 KD	34	};
6fef4fc7 KD	35
b858c331	36	static int ts2020_release(struct dvb_frontend *fe)
6fef4fc7	37	{
b858c331 IL	38	kfree(fe->tuner_priv);
	39	fe->tuner_priv = NULL;
	40	return 0;
	41	}
	42
	43	static int ts2020_writereg(struct dvb_frontend *fe, int reg, int data)
	44	{
	45	struct ts2020_priv *priv = fe->tuner_priv;
	46	u8 buf[] = { reg, data };
	47	struct i2c_msg msg[] = {
	48	{
	49	.addr = priv->i2c_address,
	50	.flags = 0,
	51	.buf = buf,
	52	.len = 2
	53	}
	54	};
	55	int err;
	56
	57	if (fe->ops.i2c_gate_ctrl)
	58	fe->ops.i2c_gate_ctrl(fe, 1);
	59
	60	err = i2c_transfer(priv->i2c, msg, 1);
	61	if (err != 1) {
	62	printk(KERN_ERR
	63	"%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
	64	__func__, err, reg, data);
	65	return -EREMOTEIO;
	66	}
6fef4fc7	67
b858c331 IL	68	if (fe->ops.i2c_gate_ctrl)
	69	fe->ops.i2c_gate_ctrl(fe, 0);
	70
	71	return 0;
	72	}
	73
	74	static int ts2020_readreg(struct dvb_frontend *fe, u8 reg)
	75	{
	76	struct ts2020_priv *priv = fe->tuner_priv;
6fef4fc7 KD	77	int ret;
	78	u8 b0[] = { reg };
	79	u8 b1[] = { 0 };
	80	struct i2c_msg msg[] = {
	81	{
b858c331	82	.addr = priv->i2c_address,
6fef4fc7 KD	83	.flags = 0,
	84	.buf = b0,
	85	.len = 1
	86	}, {
b858c331	87	.addr = priv->i2c_address,
6fef4fc7 KD	88	.flags = I2C_M_RD,
	89	.buf = b1,
	90	.len = 1
	91	}
	92	};
	93
	94	if (fe->ops.i2c_gate_ctrl)
	95	fe->ops.i2c_gate_ctrl(fe, 1);
	96
b858c331	97	ret = i2c_transfer(priv->i2c, msg, 2);
6fef4fc7 KD	98
6fef4fc7 KD	99	if (ret != 2) {
b858c331 IL	100	printk(KERN_ERR "%s: reg=0x%x(error=%d)\n",
b858c331 IL	101	__func__, reg, ret);
6fef4fc7 KD	102	return ret;
	103	}
	104
b858c331 IL	105	if (fe->ops.i2c_gate_ctrl)
	106	fe->ops.i2c_gate_ctrl(fe, 0);
	107
6fef4fc7 KD	108	return b1[0];
	109	}
	110
b858c331	111	static int ts2020_sleep(struct dvb_frontend *fe)
6fef4fc7	112	{
b858c331 IL	113	struct ts2020_priv *priv = fe->tuner_priv;
	114	int ret;
	115	u8 buf[] = { 10, 0 };
	116	struct i2c_msg msg = {
	117	.addr = priv->i2c_address,
	118	.flags = 0,
	119	.buf = buf,
	120	.len = 2
	121	};
6fef4fc7 KD	122
	123	if (fe->ops.i2c_gate_ctrl)
	124	fe->ops.i2c_gate_ctrl(fe, 1);
	125
b858c331 IL	126	ret = i2c_transfer(priv->i2c, &msg, 1);
	127	if (ret != 1)
	128	printk(KERN_ERR "%s: i2c error\n", __func__);
6fef4fc7 KD	129
	130	if (fe->ops.i2c_gate_ctrl)
	131	fe->ops.i2c_gate_ctrl(fe, 0);
	132
b858c331	133	return (ret == 1) ? 0 : ret;
6fef4fc7 KD	134	}
	135
	136	static int ts2020_init(struct dvb_frontend *fe)
	137	{
b858c331 IL	138	struct ts2020_priv *priv = fe->tuner_priv;
b858c331 IL	139
6fef4fc7	140	ts2020_writereg(fe, 0x42, 0x73);
b858c331 IL	141	ts2020_writereg(fe, 0x05, priv->clk_out_div);
	142	ts2020_writereg(fe, 0x20, 0x27);
	143	ts2020_writereg(fe, 0x07, 0x02);
	144	ts2020_writereg(fe, 0x11, 0xff);
	145	ts2020_writereg(fe, 0x60, 0xf9);
	146	ts2020_writereg(fe, 0x08, 0x01);
	147	ts2020_writereg(fe, 0x00, 0x41);
	148
6fef4fc7 KD	149	return 0;
	150	}
	151
b858c331	152	static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
6fef4fc7	153	{
b858c331 IL	154	int ret;
	155	ret = ts2020_writereg(fe, 0x51, 0x1f - offset);
	156	ret \|= ts2020_writereg(fe, 0x51, 0x1f);
	157	ret \|= ts2020_writereg(fe, 0x50, offset);
	158	ret \|= ts2020_writereg(fe, 0x50, 0x00);
	159	msleep(20);
	160	return ret;
	161	}
6fef4fc7	162
b858c331 IL	163	static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
	164	{
	165	int reg;
6fef4fc7	166
b858c331 IL	167	reg = ts2020_readreg(fe, 0x3d);
	168	reg &= 0x7f;
	169	if (reg < 0x16)
	170	reg = 0xa1;
	171	else if (reg == 0x16)
	172	reg = 0x99;
	173	else
	174	reg = 0xf9;
6fef4fc7	175
b858c331 IL	176	ts2020_writereg(fe, 0x60, reg);
b858c331 IL	177	reg = ts2020_tuner_gate_ctrl(fe, 0x08);
6fef4fc7	178
b858c331	179	return reg;
6fef4fc7 KD	180	}
	181
	182	static int ts2020_set_params(struct dvb_frontend *fe)
	183	{
	184	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
9898df64	185	struct ts2020_priv *priv = fe->tuner_priv;
b858c331 IL	186	int ret;
	187	u32 frequency = c->frequency;
	188	s32 offset_khz;
	189	u32 symbol_rate = (c->symbol_rate / 1000);
	190	u32 f3db, gdiv28;
	191	u16 value, ndiv, lpf_coeff;
	192	u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
	193	u8 lo = 0x01, div4 = 0x0;
	194
	195	/* Calculate frequency divider */
	196	if (frequency < 1060000) {
	197	lo \|= 0x10;
	198	div4 = 0x1;
	199	ndiv = (frequency * 14 * 4) / TS2020_XTAL_FREQ;
	200	} else
	201	ndiv = (frequency * 14 * 2) / TS2020_XTAL_FREQ;
	202	ndiv = ndiv + ndiv % 2;
	203	ndiv = ndiv - 1024;
	204
	205	ret = ts2020_writereg(fe, 0x10, 0x80 \| lo);
	206
	207	/* Set frequency divider */
	208	ret \|= ts2020_writereg(fe, 0x01, (ndiv >> 8) & 0xf);
	209	ret \|= ts2020_writereg(fe, 0x02, ndiv & 0xff);
	210
	211	ret \|= ts2020_writereg(fe, 0x03, 0x06);
	212	ret \|= ts2020_tuner_gate_ctrl(fe, 0x10);
	213	if (ret < 0)
	214	return -ENODEV;
	215
	216	/* Tuner Frequency Range */
	217	ret = ts2020_writereg(fe, 0x10, lo);
	218
	219	ret \|= ts2020_tuner_gate_ctrl(fe, 0x08);
	220
	221	/* Tuner RF */
	222	ret \|= ts2020_set_tuner_rf(fe);
	223
	224	gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
	225	ret \|= ts2020_writereg(fe, 0x04, gdiv28 & 0xff);
	226	ret \|= ts2020_tuner_gate_ctrl(fe, 0x04);
	227	if (ret < 0)
	228	return -ENODEV;
6fef4fc7	229
b858c331	230	value = ts2020_readreg(fe, 0x26);
6fef4fc7	231
b858c331 IL	232	f3db = (symbol_rate * 135) / 200 + 2000;
b858c331 IL	233	f3db += FREQ_OFFSET_LOW_SYM_RATE;
6fef4fc7 KD	234	if (f3db < 7000)
	235	f3db = 7000;
	236	if (f3db > 40000)
	237	f3db = 40000;
	238
b858c331 IL	239	gdiv28 = gdiv28 * 207 / (value * 2 + 151);
	240	mlpf_max = gdiv28 * 135 / 100;
	241	mlpf_min = gdiv28 * 78 / 100;
6fef4fc7 KD	242	if (mlpf_max > 63)
	243	mlpf_max = 63;
	244
b858c331 IL	245	lpf_coeff = 2766;
	246
	247	nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
	248	(TS2020_XTAL_FREQ / 1000) + 1) / 2;
6fef4fc7 KD	249	if (nlpf > 23)
	250	nlpf = 23;
	251	if (nlpf < 1)
	252	nlpf = 1;
	253
b858c331 IL	254	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
b858c331 IL	255	* lpf_coeff * 2 / f3db + 1) / 2;
6fef4fc7	256
b858c331	257	if (lpf_mxdiv < mlpf_min) {
6fef4fc7	258	nlpf++;
b858c331 IL	259	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
b858c331 IL	260	* lpf_coeff * 2 / f3db + 1) / 2;
6fef4fc7 KD	261	}
6fef4fc7 KD	262
b858c331 IL	263	if (lpf_mxdiv > mlpf_max)
b858c331 IL	264	lpf_mxdiv = mlpf_max;
6fef4fc7	265
b858c331 IL	266	ret = ts2020_writereg(fe, 0x04, lpf_mxdiv);
b858c331 IL	267	ret \|= ts2020_writereg(fe, 0x06, nlpf);
6fef4fc7	268
b858c331	269	ret \|= ts2020_tuner_gate_ctrl(fe, 0x04);
6fef4fc7	270
b858c331	271	ret \|= ts2020_tuner_gate_ctrl(fe, 0x01);
6fef4fc7	272
b858c331 IL	273	msleep(80);
	274	/* calculate offset assuming 96000kHz*/
	275	offset_khz = (ndiv - ndiv % 2 + 1024) * TS2020_XTAL_FREQ
	276	/ (6 + 8) / (div4 + 1) / 2;
6fef4fc7	277
b858c331 IL	278	priv->frequency = offset_khz;
	279
	280	return (ret < 0) ? -EINVAL : 0;
	281	}
6fef4fc7	282
b858c331 IL	283	static int ts2020_get_frequency(struct dvb_frontend fe, u32 frequency)
	284	{
	285	struct ts2020_priv *priv = fe->tuner_priv;
	286	*frequency = priv->frequency;
6fef4fc7 KD	287	return 0;
	288	}
	289
b858c331 IL	290	/* read TS2020 signal strength */
	291	static int ts2020_read_signal_strength(struct dvb_frontend *fe,
	292	u16 *signal_strength)
6fef4fc7 KD	293	{
	294	u16 sig_reading, sig_strength;
	295	u8 rfgain, bbgain;
	296
	297	rfgain = ts2020_readreg(fe, 0x3d) & 0x1f;
	298	bbgain = ts2020_readreg(fe, 0x21) & 0x1f;
	299
	300	if (rfgain > 15)
	301	rfgain = 15;
	302	if (bbgain > 13)
	303	bbgain = 13;
	304
	305	sig_reading = rfgain * 2 + bbgain * 3;
	306
	307	sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
	308
	309	/* cook the value to be suitable for szap-s2 human readable output */
	310	signal_strength = sig_strength 1000;
	311
	312	return 0;
	313	}
	314
b858c331	315	static struct dvb_tuner_ops ts2020_tuner_ops = {
6fef4fc7	316	.info = {
b858c331	317	.name = "TS2020",
6fef4fc7	318	.frequency_min = 950000,
b858c331	319	.frequency_max = 2150000
6fef4fc7	320	},
6fef4fc7 KD	321	.init = ts2020_init,
6fef4fc7 KD	322	.release = ts2020_release,
b858c331	323	.sleep = ts2020_sleep,
6fef4fc7 KD	324	.set_params = ts2020_set_params,
6fef4fc7 KD	325	.get_frequency = ts2020_get_frequency,
b858c331	326	.get_rf_strength = ts2020_read_signal_strength,
6fef4fc7 KD	327	};
	328
	329	struct dvb_frontend ts2020_attach(struct dvb_frontend fe,
b858c331 IL	330	const struct ts2020_config *config,
b858c331 IL	331	struct i2c_adapter *i2c)
6fef4fc7	332	{
b858c331 IL	333	struct ts2020_priv *priv = NULL;
	334	u8 buf;
	335
	336	priv = kzalloc(sizeof(struct ts2020_priv), GFP_KERNEL);
	337	if (priv == NULL)
	338	return NULL;
6fef4fc7	339
b858c331 IL	340	priv->i2c_address = config->tuner_address;
	341	priv->i2c = i2c;
	342	priv->clk_out_div = config->clk_out_div;
	343	fe->tuner_priv = priv;
	344
	345	/* Wake Up the tuner */
	346	if ((0x03 & ts2020_readreg(fe, 0x00)) == 0x00) {
	347	ts2020_writereg(fe, 0x00, 0x01);
	348	msleep(2);
	349	}
	350
	351	ts2020_writereg(fe, 0x00, 0x03);
	352	msleep(2);
	353
	354	/* Check the tuner version */
	355	buf = ts2020_readreg(fe, 0x00);
	356	if ((buf == 0x01) \|\| (buf == 0x41) \|\| (buf == 0x81))
	357	printk(KERN_INFO "%s: Find tuner TS2020!\n", __func__);
	358	else {
	359	printk(KERN_ERR "%s: Read tuner reg[0] = %d\n", __func__, buf);
	360	kfree(priv);
6fef4fc7	361	return NULL;
b858c331	362	}
6fef4fc7	363
b858c331 IL	364	memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
b858c331 IL	365	sizeof(struct dvb_tuner_ops));
6fef4fc7 KD	366
	367	return fe;
	368	}
	369	EXPORT_SYMBOL(ts2020_attach);
	370
	371	MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
	372	MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
	373	MODULE_LICENSE("GPL");