]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/media/i2c/ad9389b.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] v4l2-dv-timings: add v4l2_print_dv_timings helper
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / ad9389b.c
CommitLineData
117a55b6
HV		 1/*
2 * Analog Devices AD9389B/AD9889B video encoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20/*
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/slab.h>
29#include <linux/i2c.h>
30#include <linux/delay.h>
31#include <linux/videodev2.h>
32#include <linux/workqueue.h>
33#include <linux/v4l2-dv-timings.h>
34#include <media/v4l2-device.h>
117a55b6 35#include <media/v4l2-common.h>
25764158 36#include <media/v4l2-dv-timings.h>
117a55b6
HV		 37#include <media/v4l2-ctrls.h>
38#include <media/ad9389b.h>
39
40static int debug;
41module_param(debug, int, 0644);
42MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47MODULE_LICENSE("GPL");
48
49#define MASK_AD9389B_EDID_RDY_INT 0x04
50#define MASK_AD9389B_MSEN_INT 0x40
51#define MASK_AD9389B_HPD_INT 0x80
52
53#define MASK_AD9389B_HPD_DETECT 0x40
54#define MASK_AD9389B_MSEN_DETECT 0x20
55#define MASK_AD9389B_EDID_RDY 0x10
56
57#define EDID_MAX_RETRIES (8)
58#define EDID_DELAY 250
59#define EDID_MAX_SEGM 8
60
61/*
62**********************************************************************
63*
64* Arrays with configuration parameters for the AD9389B
65*
66**********************************************************************
67*/
68
69struct i2c_reg_value {
70 u8 reg;
71 u8 value;
72};
73
74struct ad9389b_state_edid {
75 /* total number of blocks */
76 u32 blocks;
77 /* Number of segments read */
78 u32 segments;
79 u8 data[EDID_MAX_SEGM * 256];
80 /* Number of EDID read retries left */
81 unsigned read_retries;
82};
83
84struct ad9389b_state {
85 struct ad9389b_platform_data pdata;
86 struct v4l2_subdev sd;
87 struct media_pad pad;
88 struct v4l2_ctrl_handler hdl;
89 int chip_revision;
90 /* Is the ad9389b powered on? */
91 bool power_on;
92 /* Did we receive hotplug and rx-sense signals? */
93 bool have_monitor;
94 /* timings from s_dv_timings */
95 struct v4l2_dv_timings dv_timings;
96 /* controls */
97 struct v4l2_ctrl *hdmi_mode_ctrl;
98 struct v4l2_ctrl *hotplug_ctrl;
99 struct v4l2_ctrl *rx_sense_ctrl;
100 struct v4l2_ctrl *have_edid0_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102 struct i2c_client *edid_i2c_client;
103 struct ad9389b_state_edid edid;
104 /* Running counter of the number of detected EDIDs (for debugging) */
105 unsigned edid_detect_counter;
106 struct workqueue_struct *work_queue;
107 struct delayed_work edid_handler; /* work entry */
108};
109
110static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
111static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
112static void ad9389b_setup(struct v4l2_subdev *sd);
113static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
114static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
115
116static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
117{
118 return container_of(sd, struct ad9389b_state, sd);
119}
120
121static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
122{
123 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
124}
125
126/* ------------------------ I2C ----------------------------------------------- */
127
128static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
129{
130 struct i2c_client *client = v4l2_get_subdevdata(sd);
131
132 return i2c_smbus_read_byte_data(client, reg);
133}
134
135static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
136{
137 struct i2c_client *client = v4l2_get_subdevdata(sd);
138 int ret;
139 int i;
140
141 for (i = 0; i < 3; i++) {
142 ret = i2c_smbus_write_byte_data(client, reg, val);
143 if (ret == 0)
144 return 0;
145 }
146 v4l2_err(sd, "I2C Write Problem\n");
147 return ret;
148}
149
150/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
151 and then the value-mask (to be OR-ed). */
152static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
153 u8 clr_mask, u8 val_mask)
154{
155 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
156}
157
158static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
159{
160 struct ad9389b_state *state = get_ad9389b_state(sd);
161 int i;
162
163 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
164
165 for (i = 0; i < len; i++)
166 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
167}
168
169static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
170{
171 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
172}
173
174static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
175{
176 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
177}
178
179static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
180{
181 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
182 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
183}
184
185static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
186 u16 A1, u16 A2, u16 A3, u16 A4,
187 u16 B1, u16 B2, u16 B3, u16 B4,
188 u16 C1, u16 C2, u16 C3, u16 C4)
189{
190 /* A */
191 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
192 ad9389b_wr(sd, 0x19, A1);
193 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
194 ad9389b_wr(sd, 0x1B, A2);
195 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
196 ad9389b_wr(sd, 0x1d, A3);
197 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
198 ad9389b_wr(sd, 0x1f, A4);
199
200 /* B */
201 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
202 ad9389b_wr(sd, 0x21, B1);
203 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
204 ad9389b_wr(sd, 0x23, B2);
205 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
206 ad9389b_wr(sd, 0x25, B3);
207 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
208 ad9389b_wr(sd, 0x27, B4);
209
210 /* C */
211 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
212 ad9389b_wr(sd, 0x29, C1);
213 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
214 ad9389b_wr(sd, 0x2B, C2);
215 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
216 ad9389b_wr(sd, 0x2D, C3);
217 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
218 ad9389b_wr(sd, 0x2F, C4);
219}
220
221static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
222{
223 if (enable) {
224 u8 csc_mode = 0;
225
226 ad9389b_csc_conversion_mode(sd, csc_mode);
227 ad9389b_csc_coeff(sd,
228 4096-564, 0, 0, 256,
229 0, 4096-564, 0, 256,
230 0, 0, 4096-564, 256);
231 /* enable CSC */
232 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
233 /* AVI infoframe: Limited range RGB (16-235) */
234 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
235 } else {
236 /* disable CSC */
237 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
238 /* AVI infoframe: Full range RGB (0-255) */
239 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
240 }
241}
242
243static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
244{
245 struct ad9389b_state *state = get_ad9389b_state(sd);
246
247 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
248 /* CEA format, not IT */
249 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
250 } else {
251 /* IT format */
252 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
253 }
254}
255
256static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
257{
258 struct ad9389b_state *state = get_ad9389b_state(sd);
259
260 switch (ctrl->val) {
261 case V4L2_DV_RGB_RANGE_AUTO:
262 /* automatic */
263 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
264 /* cea format, RGB limited range (16-235) */
265 ad9389b_csc_rgb_full2limit(sd, true);
266 } else {
267 /* not cea format, RGB full range (0-255) */
268 ad9389b_csc_rgb_full2limit(sd, false);
269 }
270 break;
271 case V4L2_DV_RGB_RANGE_LIMITED:
272 /* RGB limited range (16-235) */
273 ad9389b_csc_rgb_full2limit(sd, true);
274 break;
275 case V4L2_DV_RGB_RANGE_FULL:
276 /* RGB full range (0-255) */
277 ad9389b_csc_rgb_full2limit(sd, false);
278 break;
279 default:
280 return -EINVAL;
281 }
282 return 0;
283}
284
285static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
286{
287 u8 gear;
288
289 /* Workaround for TMDS PLL problem
290 * The TMDS PLL in AD9389b change gear when the chip is heated above a
291 * certain temperature. The output is disabled when the PLL change gear
292 * so the monitor has to lock on the signal again. A workaround for
293 * this is to use the manual PLL gears. This is a solution from Analog
294 * Devices that is not documented in the datasheets.
295 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
296 *
297 * The pixel frequency ranges are based on readout of the gear the
298 * automatic gearing selects for different pixel clocks
299 * (read from 0x9e [3:1]).
300 */
301
302 if (pixelclock > 140000000)
303 gear = 0xc0; /* 4th gear */
304 else if (pixelclock > 117000000)
305 gear = 0xb0; /* 3rd gear */
306 else if (pixelclock > 87000000)
307 gear = 0xa0; /* 2nd gear */
308 else if (pixelclock > 60000000)
309 gear = 0x90; /* 1st gear */
310 else
311 gear = 0x80; /* 0th gear */
312
313 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
314}
315
316/* ------------------------------ CTRL OPS ------------------------------ */
317
318static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
319{
320 struct v4l2_subdev *sd = to_sd(ctrl);
321 struct ad9389b_state *state = get_ad9389b_state(sd);
322
323 v4l2_dbg(1, debug, sd,
324 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
325
326 if (state->hdmi_mode_ctrl == ctrl) {
327 /* Set HDMI or DVI-D */
328 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
329 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
330 return 0;
331 }
332 if (state->rgb_quantization_range_ctrl == ctrl)
333 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
334 return -EINVAL;
335}
336
337static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
338 .s_ctrl = ad9389b_s_ctrl,
339};
340
341/* ---------------------------- CORE OPS ------------------------------------------- */
342
343#ifdef CONFIG_VIDEO_ADV_DEBUG
344static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
345{
117a55b6
HV		 346 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
347 reg->size = 1;
348 return 0;
349}
350
977ba3b1 351static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
117a55b6 352{
117a55b6
HV		 353 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
354 return 0;
355}
356#endif
357
117a55b6
HV		 358static int ad9389b_log_status(struct v4l2_subdev *sd)
359{
360 struct ad9389b_state *state = get_ad9389b_state(sd);
361 struct ad9389b_state_edid *edid = &state->edid;
362
363 static const char * const states[] = {
364 "in reset",
365 "reading EDID",
366 "idle",
367 "initializing HDCP",
368 "HDCP enabled",
369 "initializing HDCP repeater",
370 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
371 };
372 static const char * const errors[] = {
373 "no error",
374 "bad receiver BKSV",
375 "Ri mismatch",
376 "Pj mismatch",
377 "i2c error",
378 "timed out",
379 "max repeater cascade exceeded",
380 "hash check failed",
381 "too many devices",
382 "9", "A", "B", "C", "D", "E", "F"
383 };
384
385 u8 manual_gear;
386
387 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
388 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
389 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
390 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
391 "detected" : "no",
392 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
393 "detected" : "no",
394 edid->segments ? "found" : "no", edid->blocks);
395 if (state->have_monitor) {
396 v4l2_info(sd, "%s output %s\n",
397 (ad9389b_rd(sd, 0xaf) & 0x02) ?
398 "HDMI" : "DVI-D",
399 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
400 "disabled" : "enabled");
401 }
402 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
403 "encrypted" : "no encryption");
404 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
405 states[ad9389b_rd(sd, 0xc8) & 0xf],
406 errors[ad9389b_rd(sd, 0xc8) >> 4],
407 state->edid_detect_counter,
408 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
409 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
410 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
411 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
412 v4l2_info(sd, "ad9389b: %s gear %d\n",
413 manual_gear ? "manual" : "automatic",
414 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
415 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
416 if (state->have_monitor) {
417 if (ad9389b_rd(sd, 0xaf) & 0x02) {
418 /* HDMI only */
419 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
420 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
421 ad9389b_rd(sd, 0x02) << 8 |
422 ad9389b_rd(sd, 0x03);
423 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
424 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
425 u32 CTS;
426
427 if (manual_cts)
428 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
429 ad9389b_rd(sd, 0x08) << 8 |
430 ad9389b_rd(sd, 0x09);
431 else
432 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
433 ad9389b_rd(sd, 0x05) << 8 |
434 ad9389b_rd(sd, 0x06);
435 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
436 ad9389b_rd(sd, 0x02) << 8 |
437 ad9389b_rd(sd, 0x03);
438
439 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
440 manual_cts ? "manual" : "automatic", N, CTS);
441
442 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
443 vic_detect, vic_sent);
444 }
445 }
446 if (state->dv_timings.type == V4L2_DV_BT_656_1120) {
447 struct v4l2_bt_timings *bt = bt = &state->dv_timings.bt;
eacf8f9a
HV		 448 u32 frame_width = V4L2_DV_BT_FRAME_WIDTH(bt);
449 u32 frame_height = V4L2_DV_BT_FRAME_HEIGHT(bt);
117a55b6
HV		 450 u32 frame_size = frame_width * frame_height;
451
452 v4l2_info(sd, "timings: %ux%u%s%u (%ux%u). Pix freq. = %u Hz. Polarities = 0x%x\n",
453 bt->width, bt->height, bt->interlaced ? "i" : "p",
454 frame_size > 0 ? (unsigned)bt->pixelclock / frame_size : 0,
455 frame_width, frame_height,
456 (unsigned)bt->pixelclock, bt->polarities);
457 } else {
458 v4l2_info(sd, "no timings set\n");
459 }
460 return 0;
461}
462
463/* Power up/down ad9389b */
464static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
465{
466 struct ad9389b_state *state = get_ad9389b_state(sd);
467 struct ad9389b_platform_data *pdata = &state->pdata;
468 const int retries = 20;
469 int i;
470
471 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
472
473 state->power_on = on;
474
475 if (!on) {
476 /* Power down */
477 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
478 return true;
479 }
480
481 /* Power up */
482 /* The ad9389b does not always come up immediately.
483 Retry multiple times. */
484 for (i = 0; i < retries; i++) {
485 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
486 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
487 break;
488 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
489 msleep(10);
490 }
491 if (i == retries) {
492 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
493 ad9389b_s_power(sd, 0);
494 return false;
495 }
496 if (i > 1)
497 v4l2_dbg(1, debug, sd,
498 "needed %d retries to powerup the ad9389b\n", i);
499
500 /* Select chip: AD9389B */
501 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
502
503 /* Reserved registers that must be set according to REF_01 p. 11*/
504 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
505 ad9389b_wr(sd, 0x9c, 0x38);
506 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
507
508 /* Differential output drive strength */
509 if (pdata->diff_data_drive_strength > 0)
510 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
511 else
512 ad9389b_wr(sd, 0xa2, 0x87);
513
514 if (pdata->diff_clk_drive_strength > 0)
515 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
516 else
517 ad9389b_wr(sd, 0xa3, 0x87);
518
519 ad9389b_wr(sd, 0x0a, 0x01);
520 ad9389b_wr(sd, 0xbb, 0xff);
521
522 /* Set number of attempts to read the EDID */
523 ad9389b_wr(sd, 0xc9, 0xf);
524 return true;
525}
526
527/* Enable interrupts */
528static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
529{
530 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
531 u8 irqs_rd;
532 int retries = 100;
533
534 /* The datasheet says that the EDID ready interrupt should be
535 disabled if there is no hotplug. */
536 if (!enable)
537 irqs = 0;
538 else if (ad9389b_have_hotplug(sd))
539 irqs |= MASK_AD9389B_EDID_RDY_INT;
540
541 /*
542 * This i2c write can fail (approx. 1 in 1000 writes). But it
543 * is essential that this register is correct, so retry it
544 * multiple times.
545 *
546 * Note that the i2c write does not report an error, but the readback
547 * clearly shows the wrong value.
548 */
549 do {
550 ad9389b_wr(sd, 0x94, irqs);
551 irqs_rd = ad9389b_rd(sd, 0x94);
552 } while (retries-- && irqs_rd != irqs);
553
554 if (irqs_rd != irqs)
555 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
556}
557
558/* Interrupt handler */
559static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
560{
561 u8 irq_status;
562
563 /* disable interrupts to prevent a race condition */
564 ad9389b_set_isr(sd, false);
565 irq_status = ad9389b_rd(sd, 0x96);
566 /* clear detected interrupts */
567 ad9389b_wr(sd, 0x96, irq_status);
568
569 if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
570 ad9389b_check_monitor_present_status(sd);
571 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
572 ad9389b_check_edid_status(sd);
573
574 /* enable interrupts */
575 ad9389b_set_isr(sd, true);
576 *handled = true;
577 return 0;
578}
579
580static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
581 .log_status = ad9389b_log_status,
117a55b6
HV		 582#ifdef CONFIG_VIDEO_ADV_DEBUG
583 .g_register = ad9389b_g_register,
584 .s_register = ad9389b_s_register,
585#endif
586 .s_power = ad9389b_s_power,
587 .interrupt_service_routine = ad9389b_isr,
588};
589
590/* ------------------------------ PAD OPS ------------------------------ */
591
592static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
593{
594 struct ad9389b_state *state = get_ad9389b_state(sd);
595
596 if (edid->pad != 0)
597 return -EINVAL;
598 if (edid->blocks == 0 || edid->blocks > 256)
599 return -EINVAL;
600 if (!edid->edid)
601 return -EINVAL;
602 if (!state->edid.segments) {
603 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
604 return -ENODATA;
605 }
606 if (edid->start_block >= state->edid.segments * 2)
607 return -E2BIG;
608 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
609 edid->blocks = state->edid.segments * 2 - edid->start_block;
610 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
611 128 * edid->blocks);
612 return 0;
613}
614
615static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
616 .get_edid = ad9389b_get_edid,
617};
618
619/* ------------------------------ VIDEO OPS ------------------------------ */
620
621/* Enable/disable ad9389b output */
622static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
623{
624 struct ad9389b_state *state = get_ad9389b_state(sd);
625
626 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
627
628 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
629 if (enable) {
630 ad9389b_check_monitor_present_status(sd);
631 } else {
632 ad9389b_s_power(sd, 0);
633 state->have_monitor = false;
634 }
635 return 0;
636}
637
04164904
HV		 638static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
639 .type = V4L2_DV_BT_656_1120,
640 .bt = {
641 .max_width = 1920,
642 .max_height = 1200,
643 .min_pixelclock = 27000000,
644 .max_pixelclock = 170000000,
645 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
646 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
647 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
648 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
649 },
117a55b6
HV		 650};
651
652static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
653 struct v4l2_dv_timings *timings)
654{
655 struct ad9389b_state *state = get_ad9389b_state(sd);
117a55b6
HV		 656
657 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
658
659 /* quick sanity check */
04164904 660 if (!v4l2_dv_valid_timings(timings, &ad9389b_timings_cap))
117a55b6
HV		 661 return -EINVAL;
662
663 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
04164904
HV		 664 if the format is one of the CEA or DMT timings. */
665 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0);
117a55b6
HV		 666
667 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
668
669 /* save timings */
670 state->dv_timings = *timings;
671
672 /* update quantization range based on new dv_timings */
673 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
674
675 /* update PLL gear based on new dv_timings */
676 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
677 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
678
679 /* update AVI infoframe */
680 ad9389b_set_IT_content_AVI_InfoFrame(sd);
681
682 return 0;
683}
684
685static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
686 struct v4l2_dv_timings *timings)
687{
688 struct ad9389b_state *state = get_ad9389b_state(sd);
689
690 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
691
692 if (!timings)
693 return -EINVAL;
694
695 *timings = state->dv_timings;
696
697 return 0;
698}
699
700static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
701 struct v4l2_enum_dv_timings *timings)
702{
04164904 703 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap);
117a55b6
HV		 704}
705
706static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
707 struct v4l2_dv_timings_cap *cap)
708{
04164904 709 *cap = ad9389b_timings_cap;
117a55b6
HV		 710 return 0;
711}
712
713static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
714 .s_stream = ad9389b_s_stream,
715 .s_dv_timings = ad9389b_s_dv_timings,
716 .g_dv_timings = ad9389b_g_dv_timings,
717 .enum_dv_timings = ad9389b_enum_dv_timings,
718 .dv_timings_cap = ad9389b_dv_timings_cap,
719};
720
721static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
722{
723 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
724
725 if (enable)
726 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
727 else
728 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
729
730 return 0;
731}
732
733static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
734{
735 u32 N;
736
737 switch (freq) {
738 case 32000: N = 4096; break;
739 case 44100: N = 6272; break;
740 case 48000: N = 6144; break;
741 case 88200: N = 12544; break;
742 case 96000: N = 12288; break;
743 case 176400: N = 25088; break;
744 case 192000: N = 24576; break;
745 default:
746 return -EINVAL;
747 }
748
749 /* Set N (used with CTS to regenerate the audio clock) */
750 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
751 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
752 ad9389b_wr(sd, 0x03, N & 0xff);
753
754 return 0;
755}
756
757static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
758{
759 u32 i2s_sf;
760
761 switch (freq) {
762 case 32000: i2s_sf = 0x30; break;
763 case 44100: i2s_sf = 0x00; break;
764 case 48000: i2s_sf = 0x20; break;
765 case 88200: i2s_sf = 0x80; break;
766 case 96000: i2s_sf = 0xa0; break;
767 case 176400: i2s_sf = 0xc0; break;
768 case 192000: i2s_sf = 0xe0; break;
769 default:
770 return -EINVAL;
771 }
772
773 /* Set sampling frequency for I2S audio to 48 kHz */
774 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
775
776 return 0;
777}
778
779static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
780{
781 /* TODO based on input/output/config */
782 /* TODO See datasheet "Programmers guide" p. 39-40 */
783
784 /* Only 2 channels in use for application */
785 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
786 /* Speaker mapping */
787 ad9389b_wr(sd, 0x51, 0x00);
788
789 /* TODO Where should this be placed? */
790 /* 16 bit audio word length */
791 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
792
793 return 0;
794}
795
796static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
797 .s_stream = ad9389b_s_audio_stream,
798 .s_clock_freq = ad9389b_s_clock_freq,
799 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
800 .s_routing = ad9389b_s_routing,
801};
802
803/* --------------------- SUBDEV OPS --------------------------------------- */
804
805static const struct v4l2_subdev_ops ad9389b_ops = {
806 .core = &ad9389b_core_ops,
807 .video = &ad9389b_video_ops,
808 .audio = &ad9389b_audio_ops,
809 .pad = &ad9389b_pad_ops,
810};
811
812/* ----------------------------------------------------------------------- */
813static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
814 int segment, u8 *buf)
815{
816 int i, j;
817
818 if (debug < lvl)
819 return;
820
821 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
822 for (i = 0; i < 256; i += 16) {
823 u8 b[128];
824 u8 *bp = b;
825
826 if (i == 128)
827 v4l2_dbg(lvl, debug, sd, "\n");
828 for (j = i; j < i + 16; j++) {
829 sprintf(bp, "0x%02x, ", buf[j]);
830 bp += 6;
831 }
832 bp[0] = '\0';
833 v4l2_dbg(lvl, debug, sd, "%s\n", b);
834 }
835}
836
837static void ad9389b_edid_handler(struct work_struct *work)
838{
839 struct delayed_work *dwork = to_delayed_work(work);
840 struct ad9389b_state *state = container_of(dwork,
841 struct ad9389b_state, edid_handler);
842 struct v4l2_subdev *sd = &state->sd;
843 struct ad9389b_edid_detect ed;
844
845 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
846
847 if (ad9389b_check_edid_status(sd)) {
848 /* Return if we received the EDID. */
849 return;
850 }
851
852 if (ad9389b_have_hotplug(sd)) {
853 /* We must retry reading the EDID several times, it is possible
854 * that initially the EDID couldn't be read due to i2c errors
855 * (DVI connectors are particularly prone to this problem). */
856 if (state->edid.read_retries) {
857 state->edid.read_retries--;
15edc1cc
MB		 858 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
859 state->have_monitor = false;
860 ad9389b_s_power(sd, false);
861 ad9389b_s_power(sd, true);
117a55b6
HV		 862 queue_delayed_work(state->work_queue,
863 &state->edid_handler, EDID_DELAY);
864 return;
865 }
866 }
867
868 /* We failed to read the EDID, so send an event for this. */
869 ed.present = false;
870 ed.segment = ad9389b_rd(sd, 0xc4);
871 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
872 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
873}
874
875static void ad9389b_audio_setup(struct v4l2_subdev *sd)
876{
877 v4l2_dbg(1, debug, sd, "%s\n", __func__);
878
879 ad9389b_s_i2s_clock_freq(sd, 48000);
880 ad9389b_s_clock_freq(sd, 48000);
881 ad9389b_s_routing(sd, 0, 0, 0);
882}
883
884/* Initial setup of AD9389b */
885
886/* Configure hdmi transmitter. */
887static void ad9389b_setup(struct v4l2_subdev *sd)
888{
889 struct ad9389b_state *state = get_ad9389b_state(sd);
890
891 v4l2_dbg(1, debug, sd, "%s\n", __func__);
892
893 /* Input format: RGB 4:4:4 */
894 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
895 /* Output format: RGB 4:4:4 */
896 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
f3b33ede
MR		 897 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
898 Aspect ratio: 16:9 */
899 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
117a55b6
HV		 900 /* Output format: RGB 4:4:4, Active Format Information is valid. */
901 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
902 /* Underscanned */
903 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
904 /* Setup video format */
905 ad9389b_wr(sd, 0x3c, 0x0);
906 /* Active format aspect ratio: same as picure. */
907 ad9389b_wr(sd, 0x47, 0x80);
908 /* No encryption */
909 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
910 /* Positive clk edge capture for input video clock */
911 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
912
913 ad9389b_audio_setup(sd);
914
915 v4l2_ctrl_handler_setup(&state->hdl);
916
917 ad9389b_set_IT_content_AVI_InfoFrame(sd);
918}
919
920static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
921{
922 struct ad9389b_monitor_detect mdt;
923 struct ad9389b_state *state = get_ad9389b_state(sd);
924
925 mdt.present = state->have_monitor;
926 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
927}
928
929static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
930{
931 struct ad9389b_state *state = get_ad9389b_state(sd);
932 /* read hotplug and rx-sense state */
933 u8 status = ad9389b_rd(sd, 0x42);
934
935 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
936 __func__,
937 status,
938 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
939 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
940
941 if ((status & MASK_AD9389B_HPD_DETECT) &&
942 ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
943 v4l2_dbg(1, debug, sd,
944 "%s: hotplug and (rx-sense or edid)\n", __func__);
945 if (!state->have_monitor) {
946 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
947 state->have_monitor = true;
948 ad9389b_set_isr(sd, true);
949 if (!ad9389b_s_power(sd, true)) {
950 v4l2_dbg(1, debug, sd,
951 "%s: monitor detected, powerup failed\n", __func__);
952 return;
953 }
954 ad9389b_setup(sd);
955 ad9389b_notify_monitor_detect(sd);
956 state->edid.read_retries = EDID_MAX_RETRIES;
957 queue_delayed_work(state->work_queue,
958 &state->edid_handler, EDID_DELAY);
959 }
960 } else if (status & MASK_AD9389B_HPD_DETECT) {
961 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
962 state->edid.read_retries = EDID_MAX_RETRIES;
963 queue_delayed_work(state->work_queue,
964 &state->edid_handler, EDID_DELAY);
965 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
966 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
967 if (state->have_monitor) {
968 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
969 state->have_monitor = false;
970 ad9389b_notify_monitor_detect(sd);
971 }
972 ad9389b_s_power(sd, false);
973 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
974 }
975
976 /* update read only ctrls */
977 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
978 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
979 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
980}
981
982static bool edid_block_verify_crc(u8 *edid_block)
983{
117a55b6 984 u8 sum = 0;
350a1815 985 int i;
117a55b6 986
350a1815
MB		 987 for (i = 0; i < 128; i++)
988 sum += edid_block[i];
989 return sum == 0;
117a55b6
HV		 990}
991
992static bool edid_segment_verify_crc(struct v4l2_subdev *sd, u32 segment)
993{
994 struct ad9389b_state *state = get_ad9389b_state(sd);
995 u32 blocks = state->edid.blocks;
996 u8 *data = state->edid.data;
997
998 if (edid_block_verify_crc(&data[segment * 256])) {
999 if ((segment + 1) * 2 <= blocks)
1000 return edid_block_verify_crc(&data[segment * 256 + 128]);
1001 return true;
1002 }
1003 return false;
1004}
1005
1006static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1007{
1008 struct ad9389b_state *state = get_ad9389b_state(sd);
1009 struct ad9389b_edid_detect ed;
1010 int segment;
1011 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1012
1013 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1014 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1015
1016 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1017 return false;
1018
1019 segment = ad9389b_rd(sd, 0xc4);
1020 if (segment >= EDID_MAX_SEGM) {
1021 v4l2_err(sd, "edid segment number too big\n");
1022 return false;
1023 }
1024 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1025 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1026 ad9389b_dbg_dump_edid(2, debug, sd, segment,
1027 &state->edid.data[segment * 256]);
1028 if (segment == 0) {
1029 state->edid.blocks = state->edid.data[0x7e] + 1;
1030 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1031 __func__, state->edid.blocks);
1032 }
1033 if (!edid_segment_verify_crc(sd, segment)) {
1034 /* edid crc error, force reread of edid segment */
7be4f888
MR		 1035 v4l2_err(sd, "%s: edid crc error\n", __func__);
1036 state->have_monitor = false;
117a55b6
HV		 1037 ad9389b_s_power(sd, false);
1038 ad9389b_s_power(sd, true);
1039 return false;
1040 }
1041 /* one more segment read ok */
1042 state->edid.segments = segment + 1;
1043 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1044 /* Request next EDID segment */
1045 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1046 __func__, state->edid.segments);
1047 ad9389b_wr(sd, 0xc9, 0xf);
1048 ad9389b_wr(sd, 0xc4, state->edid.segments);
1049 state->edid.read_retries = EDID_MAX_RETRIES;
1050 queue_delayed_work(state->work_queue,
1051 &state->edid_handler, EDID_DELAY);
1052 return false;
1053 }
1054
1055 /* report when we have all segments but report only for segment 0 */
1056 ed.present = true;
1057 ed.segment = 0;
1058 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1059 state->edid_detect_counter++;
1060 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1061 return ed.present;
1062}
1063
1064/* ----------------------------------------------------------------------- */
1065
1066static void ad9389b_init_setup(struct v4l2_subdev *sd)
1067{
1068 struct ad9389b_state *state = get_ad9389b_state(sd);
1069 struct ad9389b_state_edid *edid = &state->edid;
1070
1071 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1072
1073 /* clear all interrupts */
1074 ad9389b_wr(sd, 0x96, 0xff);
1075
1076 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1077 state->have_monitor = false;
1078 ad9389b_set_isr(sd, false);
1079}
1080
1081static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1082{
1083 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1084 struct ad9389b_state *state;
1085 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1086 struct v4l2_ctrl_handler *hdl;
1087 struct v4l2_subdev *sd;
1088 int err = -EIO;
1089
1090 /* Check if the adapter supports the needed features */
1091 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1092 return -EIO;
1093
1094 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1095 client->addr << 1);
1096
c02b211d 1097 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
117a55b6
HV		 1098 if (!state)
1099 return -ENOMEM;
1100
1101 /* Platform data */
1102 if (pdata == NULL) {
1103 v4l_err(client, "No platform data!\n");
c02b211d 1104 return -ENODEV;
117a55b6
HV		 1105 }
1106 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1107
1108 sd = &state->sd;
1109 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1110 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1111
1112 hdl = &state->hdl;
1113 v4l2_ctrl_handler_init(hdl, 5);
1114
1115 /* private controls */
1116
1117 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1118 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1119 0, V4L2_DV_TX_MODE_DVI_D);
1120 state->hdmi_mode_ctrl->is_private = true;
1121 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1122 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1123 state->hotplug_ctrl->is_private = true;
1124 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1125 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1126 state->rx_sense_ctrl->is_private = true;
1127 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1128 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1129 state->have_edid0_ctrl->is_private = true;
1130 state->rgb_quantization_range_ctrl =
1131 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1132 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1133 0, V4L2_DV_RGB_RANGE_AUTO);
1134 state->rgb_quantization_range_ctrl->is_private = true;
1135 sd->ctrl_handler = hdl;
1136 if (hdl->error) {
1137 err = hdl->error;
1138
1139 goto err_hdl;
1140 }
1141
1142 state->pad.flags = MEDIA_PAD_FL_SINK;
1143 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1144 if (err)
1145 goto err_hdl;
1146
1147 state->chip_revision = ad9389b_rd(sd, 0x0);
1148 if (state->chip_revision != 2) {
1149 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1150 err = -EIO;
1151 goto err_entity;
1152 }
1153 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1154 ad9389b_rd(sd, 0x41), state->chip_revision);
1155
1156 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1157 if (state->edid_i2c_client == NULL) {
1158 v4l2_err(sd, "failed to register edid i2c client\n");
6ec735df 1159 err = -ENOMEM;
117a55b6
HV		 1160 goto err_entity;
1161 }
1162
1163 state->work_queue = create_singlethread_workqueue(sd->name);
1164 if (state->work_queue == NULL) {
1165 v4l2_err(sd, "could not create workqueue\n");
6ec735df 1166 err = -ENOMEM;
117a55b6
HV		 1167 goto err_unreg;
1168 }
1169
1170 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1171 state->dv_timings = dv1080p60;
1172
1173 ad9389b_init_setup(sd);
1174 ad9389b_set_isr(sd, true);
1175
1176 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1177 client->addr << 1, client->adapter->name);
1178 return 0;
1179
1180err_unreg:
1181 i2c_unregister_device(state->edid_i2c_client);
1182err_entity:
1183 media_entity_cleanup(&sd->entity);
1184err_hdl:
1185 v4l2_ctrl_handler_free(&state->hdl);
117a55b6
HV		 1186 return err;
1187}
1188
1189/* ----------------------------------------------------------------------- */
1190
1191static int ad9389b_remove(struct i2c_client *client)
1192{
1193 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1194 struct ad9389b_state *state = get_ad9389b_state(sd);
1195
1196 state->chip_revision = -1;
1197
1198 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1199 client->addr << 1, client->adapter->name);
1200
1201 ad9389b_s_stream(sd, false);
1202 ad9389b_s_audio_stream(sd, false);
1203 ad9389b_init_setup(sd);
1204 cancel_delayed_work(&state->edid_handler);
1205 i2c_unregister_device(state->edid_i2c_client);
1206 destroy_workqueue(state->work_queue);
1207 v4l2_device_unregister_subdev(sd);
1208 media_entity_cleanup(&sd->entity);
1209 v4l2_ctrl_handler_free(sd->ctrl_handler);
117a55b6
HV		 1210 return 0;
1211}
1212
1213/* ----------------------------------------------------------------------- */
1214
1215static struct i2c_device_id ad9389b_id[] = {
e1277110
HV		 1216 { "ad9389b", 0 },
1217 { "ad9889b", 0 },
117a55b6
HV		 1218 { }
1219};
1220MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1221
1222static struct i2c_driver ad9389b_driver = {
1223 .driver = {
1224 .owner = THIS_MODULE,
1225 .name = "ad9389b",
1226 },
1227 .probe = ad9389b_probe,
1228 .remove = ad9389b_remove,
1229 .id_table = ad9389b_id,
1230};
1231
1232module_i2c_driver(ad9389b_driver);
Ubuntu Artful kernel mirror