[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / adv7183.c

/*
 * adv7183.c Analog Devices ADV7183 video decoder driver
 *
 * Copyright (c) 2011 Analog Devices Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/videodev2.h>

#include <media/i2c/adv7183.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>

#include "adv7183_regs.h"

struct adv7183 {
	struct v4l2_subdev sd;
	struct v4l2_ctrl_handler hdl;

	v4l2_std_id std; /* Current set standard */
	u32 input;
	u32 output;
	unsigned reset_pin;
	unsigned oe_pin;
	struct v4l2_mbus_framefmt fmt;
};

/* EXAMPLES USING 27 MHz CLOCK
 * Mode 1 CVBS Input (Composite Video on AIN5)
 * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
 */
static const unsigned char adv7183_init_regs[] = {
	ADV7183_IN_CTRL, 0x04,           /* CVBS input on AIN5 */
	ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
	ADV7183_SHAP_FILT_CTRL, 0x41,    /* Set CSFM to SH1 */
	ADV7183_ADC_CTRL, 0x16,          /* Power down ADC 1 and ADC 2 */
	ADV7183_CTI_DNR_CTRL_4, 0x04,    /* Set DNR threshold to 4 for flat response */
	/* ADI recommended programming sequence */
	ADV7183_ADI_CTRL, 0x80,
	ADV7183_CTI_DNR_CTRL_4, 0x20,
	0x52, 0x18,
	0x58, 0xED,
	0x77, 0xC5,
	0x7C, 0x93,
	0x7D, 0x00,
	0xD0, 0x48,
	0xD5, 0xA0,
	0xD7, 0xEA,
	ADV7183_SD_SATURATION_CR, 0x3E,
	ADV7183_PAL_V_END, 0x3E,
	ADV7183_PAL_F_TOGGLE, 0x0F,
	ADV7183_ADI_CTRL, 0x00,
};

static inline struct adv7183 *to_adv7183(struct v4l2_subdev *sd)
{
	return container_of(sd, struct adv7183, sd);
}
static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
}

static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return i2c_smbus_read_byte_data(client, reg);
}

static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
				unsigned char value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return i2c_smbus_write_byte_data(client, reg, value);
}

static int adv7183_writeregs(struct v4l2_subdev *sd,
		const unsigned char *regs, unsigned int num)
{
	unsigned char reg, data;
	unsigned int cnt = 0;

	if (num & 0x1) {
		v4l2_err(sd, "invalid regs array\n");
		return -1;
	}

	while (cnt < num) {
		reg = *regs++;
		data = *regs++;
		cnt += 2;

		adv7183_write(sd, reg, data);
	}
	return 0;
}

static int adv7183_log_status(struct v4l2_subdev *sd)
{
	struct adv7183 *decoder = to_adv7183(sd);

	v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
			adv7183_read(sd, ADV7183_IN_CTRL));
	v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
			adv7183_read(sd, ADV7183_VD_SEL));
	v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
			adv7183_read(sd, ADV7183_OUT_CTRL));
	v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
			adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
	v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
			adv7183_read(sd, ADV7183_AUTO_DET_EN));
	v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
			adv7183_read(sd, ADV7183_CONTRAST));
	v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
			adv7183_read(sd, ADV7183_BRIGHTNESS));
	v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
			adv7183_read(sd, ADV7183_HUE));
	v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
			adv7183_read(sd, ADV7183_DEF_Y));
	v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
			adv7183_read(sd, ADV7183_DEF_C));
	v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
			adv7183_read(sd, ADV7183_ADI_CTRL));
	v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
			adv7183_read(sd, ADV7183_POW_MANAGE));
	v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_STATUS_1),
			adv7183_read(sd, ADV7183_STATUS_2),
			adv7183_read(sd, ADV7183_STATUS_3));
	v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
			adv7183_read(sd, ADV7183_IDENT));
	v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
			adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
	v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
			adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
	v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
			adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
	v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
			adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
	v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
			adv7183_read(sd, ADV7183_ADI_CTRL_2));
	v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
			adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
	v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
			adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
	v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
			adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
	v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
			adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
	v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
			adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
	v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
			adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
			adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
	v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
			adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
			adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
	v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
			adv7183_read(sd, ADV7183_POLARITY));
	v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
			adv7183_read(sd, ADV7183_ADC_CTRL));
	v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_SD_OFFSET_CB),
			adv7183_read(sd, ADV7183_SD_OFFSET_CR));
	v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
			adv7183_read(sd, ADV7183_SD_SATURATION_CB),
			adv7183_read(sd, ADV7183_SD_SATURATION_CR));
	v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
			adv7183_read(sd, ADV7183_DRIVE_STR));
	v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
	return 0;
}

static int adv7183_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	struct adv7183 *decoder = to_adv7183(sd);

	*std = decoder->std;
	return 0;
}

static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct adv7183 *decoder = to_adv7183(sd);
	int reg;

	reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
	if (std == V4L2_STD_PAL_60)
		reg |= 0x60;
	else if (std == V4L2_STD_NTSC_443)
		reg |= 0x70;
	else if (std == V4L2_STD_PAL_N)
		reg |= 0x90;
	else if (std == V4L2_STD_PAL_M)
		reg |= 0xA0;
	else if (std == V4L2_STD_PAL_Nc)
		reg |= 0xC0;
	else if (std & V4L2_STD_PAL)
		reg |= 0x80;
	else if (std & V4L2_STD_NTSC)
		reg |= 0x50;
	else if (std & V4L2_STD_SECAM)
		reg |= 0xE0;
	else
		return -EINVAL;
	adv7183_write(sd, ADV7183_IN_CTRL, reg);

	decoder->std = std;

	return 0;
}

static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
{
	int reg;

	reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80;
	adv7183_write(sd, ADV7183_POW_MANAGE, reg);
	/* wait 5ms before any further i2c writes are performed */
	usleep_range(5000, 10000);
	return 0;
}

static int adv7183_s_routing(struct v4l2_subdev *sd,
				u32 input, u32 output, u32 config)
{
	struct adv7183 *decoder = to_adv7183(sd);
	int reg;

	if ((input > ADV7183_COMPONENT1) || (output > ADV7183_16BIT_OUT))
		return -EINVAL;

	if (input != decoder->input) {
		decoder->input = input;
		reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
		switch (input) {
		case ADV7183_COMPOSITE1:
			reg |= 0x1;
			break;
		case ADV7183_COMPOSITE2:
			reg |= 0x2;
			break;
		case ADV7183_COMPOSITE3:
			reg |= 0x3;
			break;
		case ADV7183_COMPOSITE4:
			reg |= 0x4;
			break;
		case ADV7183_COMPOSITE5:
			reg |= 0x5;
			break;
		case ADV7183_COMPOSITE6:
			reg |= 0xB;
			break;
		case ADV7183_COMPOSITE7:
			reg |= 0xC;
			break;
		case ADV7183_COMPOSITE8:
			reg |= 0xD;
			break;
		case ADV7183_COMPOSITE9:
			reg |= 0xE;
			break;
		case ADV7183_COMPOSITE10:
			reg |= 0xF;
			break;
		case ADV7183_SVIDEO0:
			reg |= 0x6;
			break;
		case ADV7183_SVIDEO1:
			reg |= 0x7;
			break;
		case ADV7183_SVIDEO2:
			reg |= 0x8;
			break;
		case ADV7183_COMPONENT0:
			reg |= 0x9;
			break;
		case ADV7183_COMPONENT1:
			reg |= 0xA;
			break;
		default:
			break;
		}
		adv7183_write(sd, ADV7183_IN_CTRL, reg);
	}

	if (output != decoder->output) {
		decoder->output = output;
		reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
		switch (output) {
		case ADV7183_16BIT_OUT:
			reg |= 0x9;
			break;
		default:
			reg |= 0xC;
			break;
		}
		adv7183_write(sd, ADV7183_OUT_CTRL, reg);
	}

	return 0;
}

static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct v4l2_subdev *sd = to_sd(ctrl);
	int val = ctrl->val;

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		if (val < 0)
			val = 127 - val;
		adv7183_write(sd, ADV7183_BRIGHTNESS, val);
		break;
	case V4L2_CID_CONTRAST:
		adv7183_write(sd, ADV7183_CONTRAST, val);
		break;
	case V4L2_CID_SATURATION:
		adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
		adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
		break;
	case V4L2_CID_HUE:
		adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
		adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int adv7183_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	struct adv7183 *decoder = to_adv7183(sd);
	int reg;

	/* enable autodetection block */
	reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
	adv7183_write(sd, ADV7183_IN_CTRL, reg);

	/* wait autodetection switch */
	mdelay(10);

	/* get autodetection result */
	reg = adv7183_read(sd, ADV7183_STATUS_1);
	switch ((reg >> 0x4) & 0x7) {
	case 0:
		*std &= V4L2_STD_NTSC;
		break;
	case 1:
		*std &= V4L2_STD_NTSC_443;
		break;
	case 2:
		*std &= V4L2_STD_PAL_M;
		break;
	case 3:
		*std &= V4L2_STD_PAL_60;
		break;
	case 4:
		*std &= V4L2_STD_PAL;
		break;
	case 5:
		*std &= V4L2_STD_SECAM;
		break;
	case 6:
		*std &= V4L2_STD_PAL_Nc;
		break;
	case 7:
		*std &= V4L2_STD_SECAM;
		break;
	default:
		*std = V4L2_STD_UNKNOWN;
		break;
	}

	/* after std detection, write back user set std */
	adv7183_s_std(sd, decoder->std);
	return 0;
}

static int adv7183_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	int reg;

	*status = V4L2_IN_ST_NO_SIGNAL;
	reg = adv7183_read(sd, ADV7183_STATUS_1);
	if (reg < 0)
		return reg;
	if (reg & 0x1)
		*status = 0;
	return 0;
}

static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
		struct v4l2_subdev_pad_config *cfg,
		struct v4l2_subdev_mbus_code_enum *code)
{
	if (code->pad || code->index > 0)
		return -EINVAL;

	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
	return 0;
}

static int adv7183_set_fmt(struct v4l2_subdev *sd,
		struct v4l2_subdev_pad_config *cfg,
		struct v4l2_subdev_format *format)
{
	struct adv7183 *decoder = to_adv7183(sd);
	struct v4l2_mbus_framefmt *fmt = &format->format;

	if (format->pad)
		return -EINVAL;

	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
	if (decoder->std & V4L2_STD_525_60) {
		fmt->field = V4L2_FIELD_SEQ_TB;
		fmt->width = 720;
		fmt->height = 480;
	} else {
		fmt->field = V4L2_FIELD_SEQ_BT;
		fmt->width = 720;
		fmt->height = 576;
	}
	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
		decoder->fmt = *fmt;
	else
		cfg->try_fmt = *fmt;
	return 0;
}

static int adv7183_get_fmt(struct v4l2_subdev *sd,
		struct v4l2_subdev_pad_config *cfg,
		struct v4l2_subdev_format *format)
{
	struct adv7183 *decoder = to_adv7183(sd);

	if (format->pad)
		return -EINVAL;

	format->format = decoder->fmt;
	return 0;
}

static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
{
	struct adv7183 *decoder = to_adv7183(sd);

	if (enable)
		gpio_set_value(decoder->oe_pin, 0);
	else
		gpio_set_value(decoder->oe_pin, 1);
	udelay(1);
	return 0;
}

#ifdef CONFIG_VIDEO_ADV_DEBUG
static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
{
	reg->val = adv7183_read(sd, reg->reg & 0xff);
	reg->size = 1;
	return 0;
}

static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
{
	adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
	return 0;
}
#endif

static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
	.s_ctrl = adv7183_s_ctrl,
};

static const struct v4l2_subdev_core_ops adv7183_core_ops = {
	.log_status = adv7183_log_status,
	.reset = adv7183_reset,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = adv7183_g_register,
	.s_register = adv7183_s_register,
#endif
};

static const struct v4l2_subdev_video_ops adv7183_video_ops = {
	.g_std = adv7183_g_std,
	.s_std = adv7183_s_std,
	.s_routing = adv7183_s_routing,
	.querystd = adv7183_querystd,
	.g_input_status = adv7183_g_input_status,
	.s_stream = adv7183_s_stream,
};

static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
	.enum_mbus_code = adv7183_enum_mbus_code,
	.get_fmt = adv7183_get_fmt,
	.set_fmt = adv7183_set_fmt,
};

static const struct v4l2_subdev_ops adv7183_ops = {
	.core = &adv7183_core_ops,
	.video = &adv7183_video_ops,
	.pad = &adv7183_pad_ops,
};

static int adv7183_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	struct adv7183 *decoder;
	struct v4l2_subdev *sd;
	struct v4l2_ctrl_handler *hdl;
	int ret;
	struct v4l2_subdev_format fmt = {
		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	};
	const unsigned *pin_array;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
		return -EIO;

	v4l_info(client, "chip found @ 0x%02x (%s)\n",
			client->addr << 1, client->adapter->name);

	pin_array = client->dev.platform_data;
	if (pin_array == NULL)
		return -EINVAL;

	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
	if (decoder == NULL)
		return -ENOMEM;

	decoder->reset_pin = pin_array[0];
	decoder->oe_pin = pin_array[1];

	if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
				  GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
		v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
		return -EBUSY;
	}

	if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
				  GPIOF_OUT_INIT_HIGH,
				  "ADV7183 Output Enable")) {
		v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
		return -EBUSY;
	}

	sd = &decoder->sd;
	v4l2_i2c_subdev_init(sd, client, &adv7183_ops);

	hdl = &decoder->hdl;
	v4l2_ctrl_handler_init(hdl, 4);
	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
			V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
			V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
			V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
			V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
	/* hook the control handler into the driver */
	sd->ctrl_handler = hdl;
	if (hdl->error) {
		ret = hdl->error;

		v4l2_ctrl_handler_free(hdl);
		return ret;
	}

	/* v4l2 doesn't support an autodetect standard, pick PAL as default */
	decoder->std = V4L2_STD_PAL;
	decoder->input = ADV7183_COMPOSITE4;
	decoder->output = ADV7183_8BIT_OUT;

	/* reset chip */
	/* reset pulse width at least 5ms */
	mdelay(10);
	gpio_set_value(decoder->reset_pin, 1);
	/* wait 5ms before any further i2c writes are performed */
	mdelay(5);

	adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
	adv7183_s_std(sd, decoder->std);
	fmt.format.width = 720;
	fmt.format.height = 576;
	adv7183_set_fmt(sd, NULL, &fmt);

	/* initialize the hardware to the default control values */
	ret = v4l2_ctrl_handler_setup(hdl);
	if (ret) {
		v4l2_ctrl_handler_free(hdl);
		return ret;
	}

	return 0;
}

static int adv7183_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);

	v4l2_device_unregister_subdev(sd);
	v4l2_ctrl_handler_free(sd->ctrl_handler);
	return 0;
}

static const struct i2c_device_id adv7183_id[] = {
	{"adv7183", 0},
	{},
};

MODULE_DEVICE_TABLE(i2c, adv7183_id);

static struct i2c_driver adv7183_driver = {
	.driver = {
		.name   = "adv7183",
	},
	.probe          = adv7183_probe,
	.remove         = adv7183_remove,
	.id_table       = adv7183_id,
};

module_i2c_driver(adv7183_driver);

MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
202ea1f0 SJ	1	/*
	2	* adv7183.c Analog Devices ADV7183 video decoder driver
	3	*
	4	* Copyright (c) 2011 Analog Devices Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
202ea1f0 SJ	14	*/
	15
	16	#include <linux/delay.h>
	17	#include <linux/errno.h>
	18	#include <linux/gpio.h>
	19	#include <linux/i2c.h>
	20	#include <linux/init.h>
	21	#include <linux/module.h>
	22	#include <linux/slab.h>
	23	#include <linux/types.h>
	24	#include <linux/videodev2.h>
	25
b5dcee22	26	#include <media/i2c/adv7183.h>
202ea1f0 SJ	27	#include <media/v4l2-ctrls.h>
	28	#include <media/v4l2-device.h>
	29
	30	#include "adv7183_regs.h"
	31
	32	struct adv7183 {
	33	struct v4l2_subdev sd;
	34	struct v4l2_ctrl_handler hdl;
	35
	36	v4l2_std_id std; /* Current set standard */
	37	u32 input;
	38	u32 output;
	39	unsigned reset_pin;
	40	unsigned oe_pin;
	41	struct v4l2_mbus_framefmt fmt;
	42	};
	43
	44	/* EXAMPLES USING 27 MHz CLOCK
	45	* Mode 1 CVBS Input (Composite Video on AIN5)
	46	* All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
	47	*/
	48	static const unsigned char adv7183_init_regs[] = {
	49	ADV7183_IN_CTRL, 0x04, /* CVBS input on AIN5 */
	50	ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
	51	ADV7183_SHAP_FILT_CTRL, 0x41, /* Set CSFM to SH1 */
	52	ADV7183_ADC_CTRL, 0x16, /* Power down ADC 1 and ADC 2 */
	53	ADV7183_CTI_DNR_CTRL_4, 0x04, /* Set DNR threshold to 4 for flat response */
	54	/* ADI recommended programming sequence */
	55	ADV7183_ADI_CTRL, 0x80,
	56	ADV7183_CTI_DNR_CTRL_4, 0x20,
	57	0x52, 0x18,
	58	0x58, 0xED,
	59	0x77, 0xC5,
	60	0x7C, 0x93,
	61	0x7D, 0x00,
	62	0xD0, 0x48,
	63	0xD5, 0xA0,
	64	0xD7, 0xEA,
	65	ADV7183_SD_SATURATION_CR, 0x3E,
	66	ADV7183_PAL_V_END, 0x3E,
	67	ADV7183_PAL_F_TOGGLE, 0x0F,
	68	ADV7183_ADI_CTRL, 0x00,
	69	};
	70
	71	static inline struct adv7183 to_adv7183(struct v4l2_subdev sd)
	72	{
	73	return container_of(sd, struct adv7183, sd);
	74	}
	75	static inline struct v4l2_subdev to_sd(struct v4l2_ctrl ctrl)
	76	{
	77	return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
	78	}
	79
	80	static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
	81	{
	82	struct i2c_client *client = v4l2_get_subdevdata(sd);
	83
	84	return i2c_smbus_read_byte_data(client, reg);
	85	}
	86
	87	static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
	88	unsigned char value)
	89	{
	90	struct i2c_client *client = v4l2_get_subdevdata(sd);
91
92	return i2c_smbus_write_byte_data(client, reg, value);
93	}
94
95	static int adv7183_writeregs(struct v4l2_subdev *sd,
96	const unsigned char *regs, unsigned int num)
97	{
98	unsigned char reg, data;
99	unsigned int cnt = 0;
100
101	if (num & 0x1) {
102	v4l2_err(sd, "invalid regs array\n");
103	return -1;
104	}
105
106	while (cnt < num) {
107	reg = *regs++;
108	data = *regs++;
109	cnt += 2;
110
111	adv7183_write(sd, reg, data);
112	}
113	return 0;
114	}
115
116	static int adv7183_log_status(struct v4l2_subdev *sd)
117	{
118	struct adv7183 *decoder = to_adv7183(sd);
119
120	v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
121	adv7183_read(sd, ADV7183_IN_CTRL));
122	v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
123	adv7183_read(sd, ADV7183_VD_SEL));
124	v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
125	adv7183_read(sd, ADV7183_OUT_CTRL));
126	v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
127	adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
128	v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
129	adv7183_read(sd, ADV7183_AUTO_DET_EN));
130	v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
131	adv7183_read(sd, ADV7183_CONTRAST));
132	v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
133	adv7183_read(sd, ADV7183_BRIGHTNESS));
134	v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
135	adv7183_read(sd, ADV7183_HUE));
136	v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
137	adv7183_read(sd, ADV7183_DEF_Y));
138	v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
139	adv7183_read(sd, ADV7183_DEF_C));
140	v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
141	adv7183_read(sd, ADV7183_ADI_CTRL));
142	v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
143	adv7183_read(sd, ADV7183_POW_MANAGE));
144	v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
145	adv7183_read(sd, ADV7183_STATUS_1),
146	adv7183_read(sd, ADV7183_STATUS_2),
147	adv7183_read(sd, ADV7183_STATUS_3));
148	v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
149	adv7183_read(sd, ADV7183_IDENT));
150	v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
151	adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
152	v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
153	adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
154	v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
155	adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
156	adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
157	v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
158	adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
159	v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
160	adv7183_read(sd, ADV7183_ADI_CTRL_2));
161	v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
162	adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
163	v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
164	adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
165	v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
166	adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
167	v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
168	adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
169	adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
170	v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
171	adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
172	adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
173	v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
174	adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
175	adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
176	adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
6d3be300	177	v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
202ea1f0 SJ	178	adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
	179	adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
	180	adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
	181	v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
	182	adv7183_read(sd, ADV7183_POLARITY));
	183	v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
	184	adv7183_read(sd, ADV7183_ADC_CTRL));
	185	v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
	186	adv7183_read(sd, ADV7183_SD_OFFSET_CB),
	187	adv7183_read(sd, ADV7183_SD_OFFSET_CR));
	188	v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
	189	adv7183_read(sd, ADV7183_SD_SATURATION_CB),
	190	adv7183_read(sd, ADV7183_SD_SATURATION_CR));
	191	v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
	192	adv7183_read(sd, ADV7183_DRIVE_STR));
	193	v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
	194	return 0;
	195	}
	196
	197	static int adv7183_g_std(struct v4l2_subdev sd, v4l2_std_id std)
	198	{
	199	struct adv7183 *decoder = to_adv7183(sd);
	200
	201	*std = decoder->std;
	202	return 0;
	203	}
	204
	205	static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
	206	{
	207	struct adv7183 *decoder = to_adv7183(sd);
	208	int reg;
	209
	210	reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
	211	if (std == V4L2_STD_PAL_60)
	212	reg \|= 0x60;
	213	else if (std == V4L2_STD_NTSC_443)
	214	reg \|= 0x70;
	215	else if (std == V4L2_STD_PAL_N)
	216	reg \|= 0x90;
	217	else if (std == V4L2_STD_PAL_M)
	218	reg \|= 0xA0;
	219	else if (std == V4L2_STD_PAL_Nc)
	220	reg \|= 0xC0;
	221	else if (std & V4L2_STD_PAL)
	222	reg \|= 0x80;
	223	else if (std & V4L2_STD_NTSC)
	224	reg \|= 0x50;
	225	else if (std & V4L2_STD_SECAM)
	226	reg \|= 0xE0;
	227	else
	228	return -EINVAL;
	229	adv7183_write(sd, ADV7183_IN_CTRL, reg);
	230
	231	decoder->std = std;
	232
	233	return 0;
	234	}
	235
	236	static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
	237	{
	238	int reg;
	239
	240	reg = adv7183_read(sd, ADV7183_POW_MANAGE) \| 0x80;
	241	adv7183_write(sd, ADV7183_POW_MANAGE, reg);
242	/* wait 5ms before any further i2c writes are performed */
243	usleep_range(5000, 10000);
244	return 0;
245	}
246
247	static int adv7183_s_routing(struct v4l2_subdev *sd,
248	u32 input, u32 output, u32 config)
249	{
250	struct adv7183 *decoder = to_adv7183(sd);
251	int reg;
252
253	if ((input > ADV7183_COMPONENT1) \|\| (output > ADV7183_16BIT_OUT))
254	return -EINVAL;
255
256	if (input != decoder->input) {
257	decoder->input = input;
258	reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
259	switch (input) {
260	case ADV7183_COMPOSITE1:
261	reg \|= 0x1;
262	break;
263	case ADV7183_COMPOSITE2:
264	reg \|= 0x2;
265	break;
266	case ADV7183_COMPOSITE3:
267	reg \|= 0x3;
268	break;
269	case ADV7183_COMPOSITE4:
270	reg \|= 0x4;
271	break;
272	case ADV7183_COMPOSITE5:
273	reg \|= 0x5;
274	break;
275	case ADV7183_COMPOSITE6:
276	reg \|= 0xB;
277	break;
278	case ADV7183_COMPOSITE7:
279	reg \|= 0xC;
280	break;
281	case ADV7183_COMPOSITE8:
282	reg \|= 0xD;
283	break;
284	case ADV7183_COMPOSITE9:
285	reg \|= 0xE;
286	break;
287	case ADV7183_COMPOSITE10:
288	reg \|= 0xF;
289	break;
290	case ADV7183_SVIDEO0:
291	reg \|= 0x6;
292	break;
293	case ADV7183_SVIDEO1:
294	reg \|= 0x7;
295	break;
296	case ADV7183_SVIDEO2:
297	reg \|= 0x8;
298	break;
299	case ADV7183_COMPONENT0:
300	reg \|= 0x9;
301	break;
302	case ADV7183_COMPONENT1:
303	reg \|= 0xA;
304	break;
305	default:
306	break;
307	}
308	adv7183_write(sd, ADV7183_IN_CTRL, reg);
309	}
310
311	if (output != decoder->output) {
312	decoder->output = output;
313	reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
314	switch (output) {
315	case ADV7183_16BIT_OUT:
316	reg \|= 0x9;
317	break;
318	default:
319	reg \|= 0xC;
320	break;
321	}
322	adv7183_write(sd, ADV7183_OUT_CTRL, reg);
323	}
324
325	return 0;
326	}
327
328	static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
329	{
330	struct v4l2_subdev *sd = to_sd(ctrl);
331	int val = ctrl->val;
332
333	switch (ctrl->id) {
334	case V4L2_CID_BRIGHTNESS:
335	if (val < 0)
336	val = 127 - val;
337	adv7183_write(sd, ADV7183_BRIGHTNESS, val);
338	break;
339	case V4L2_CID_CONTRAST:
340	adv7183_write(sd, ADV7183_CONTRAST, val);
341	break;
342	case V4L2_CID_SATURATION:
343	adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
344	adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
345	break;
346	case V4L2_CID_HUE:
347	adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
348	adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
349	break;
350	default:
351	return -EINVAL;
352	}
353
354	return 0;
355	}
356
357	static int adv7183_querystd(struct v4l2_subdev sd, v4l2_std_id std)
358	{
359	struct adv7183 *decoder = to_adv7183(sd);
360	int reg;
361
362	/* enable autodetection block */
363	reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
364	adv7183_write(sd, ADV7183_IN_CTRL, reg);
365
366	/* wait autodetection switch */
367	mdelay(10);
368
369	/* get autodetection result */
370	reg = adv7183_read(sd, ADV7183_STATUS_1);
371	switch ((reg >> 0x4) & 0x7) {
372	case 0:
7dd8fbbe	373	*std &= V4L2_STD_NTSC;
202ea1f0 SJ	374	break;
202ea1f0 SJ	375	case 1:
7dd8fbbe	376	*std &= V4L2_STD_NTSC_443;
202ea1f0 SJ	377	break;
202ea1f0 SJ	378	case 2:
7dd8fbbe	379	*std &= V4L2_STD_PAL_M;
202ea1f0 SJ	380	break;
202ea1f0 SJ	381	case 3:
7dd8fbbe	382	*std &= V4L2_STD_PAL_60;
202ea1f0 SJ	383	break;
202ea1f0 SJ	384	case 4:
7dd8fbbe	385	*std &= V4L2_STD_PAL;
202ea1f0 SJ	386	break;
202ea1f0 SJ	387	case 5:
7dd8fbbe	388	*std &= V4L2_STD_SECAM;
202ea1f0 SJ	389	break;
202ea1f0 SJ	390	case 6:
7dd8fbbe	391	*std &= V4L2_STD_PAL_Nc;
202ea1f0 SJ	392	break;
202ea1f0 SJ	393	case 7:
7dd8fbbe	394	*std &= V4L2_STD_SECAM;
202ea1f0 SJ	395	break;
	396	default:
	397	*std = V4L2_STD_UNKNOWN;
	398	break;
	399	}
	400
	401	/* after std detection, write back user set std */
	402	adv7183_s_std(sd, decoder->std);
	403	return 0;
	404	}
	405
	406	static int adv7183_g_input_status(struct v4l2_subdev sd, u32 status)
	407	{
	408	int reg;
	409
	410	*status = V4L2_IN_ST_NO_SIGNAL;
	411	reg = adv7183_read(sd, ADV7183_STATUS_1);
	412	if (reg < 0)
	413	return reg;
	414	if (reg & 0x1)
	415	*status = 0;
	416	return 0;
	417	}
	418
ebcff5fc HV	419	static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
	420	struct v4l2_subdev_pad_config *cfg,
	421	struct v4l2_subdev_mbus_code_enum *code)
202ea1f0	422	{
ebcff5fc	423	if (code->pad \|\| code->index > 0)
202ea1f0 SJ	424	return -EINVAL;
202ea1f0 SJ	425
ebcff5fc	426	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
202ea1f0 SJ	427	return 0;
	428	}
	429
717fd5b4 HV	430	static int adv7183_set_fmt(struct v4l2_subdev *sd,
	431	struct v4l2_subdev_pad_config *cfg,
	432	struct v4l2_subdev_format *format)
202ea1f0 SJ	433	{
202ea1f0 SJ	434	struct adv7183 *decoder = to_adv7183(sd);
717fd5b4 HV	435	struct v4l2_mbus_framefmt *fmt = &format->format;
	436
	437	if (format->pad)
	438	return -EINVAL;
202ea1f0	439
f5fe58fd	440	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
202ea1f0 SJ	441	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
	442	if (decoder->std & V4L2_STD_525_60) {
	443	fmt->field = V4L2_FIELD_SEQ_TB;
	444	fmt->width = 720;
	445	fmt->height = 480;
	446	} else {
	447	fmt->field = V4L2_FIELD_SEQ_BT;
	448	fmt->width = 720;
	449	fmt->height = 576;
	450	}
717fd5b4 HV	451	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
	452	decoder->fmt = *fmt;
	453	else
	454	cfg->try_fmt = *fmt;
202ea1f0 SJ	455	return 0;
	456	}
	457
da298c6d HV	458	static int adv7183_get_fmt(struct v4l2_subdev *sd,
	459	struct v4l2_subdev_pad_config *cfg,
	460	struct v4l2_subdev_format *format)
202ea1f0 SJ	461	{
	462	struct adv7183 *decoder = to_adv7183(sd);
	463
da298c6d HV	464	if (format->pad)
	465	return -EINVAL;
	466
	467	format->format = decoder->fmt;
202ea1f0 SJ	468	return 0;
	469	}
	470
	471	static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
	472	{
	473	struct adv7183 *decoder = to_adv7183(sd);
	474
	475	if (enable)
95323361	476	gpio_set_value(decoder->oe_pin, 0);
202ea1f0	477	else
95323361	478	gpio_set_value(decoder->oe_pin, 1);
202ea1f0 SJ	479	udelay(1);
	480	return 0;
	481	}
	482
202ea1f0 SJ	483	#ifdef CONFIG_VIDEO_ADV_DEBUG
	484	static int adv7183_g_register(struct v4l2_subdev sd, struct v4l2_dbg_register reg)
	485	{
202ea1f0 SJ	486	reg->val = adv7183_read(sd, reg->reg & 0xff);
	487	reg->size = 1;
	488	return 0;
	489	}
	490
977ba3b1	491	static int adv7183_s_register(struct v4l2_subdev sd, const struct v4l2_dbg_register reg)
202ea1f0	492	{
202ea1f0 SJ	493	adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
	494	return 0;
	495	}
	496	#endif
	497
	498	static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
	499	.s_ctrl = adv7183_s_ctrl,
	500	};
	501
	502	static const struct v4l2_subdev_core_ops adv7183_core_ops = {
	503	.log_status = adv7183_log_status,
202ea1f0	504	.reset = adv7183_reset,
202ea1f0 SJ	505	#ifdef CONFIG_VIDEO_ADV_DEBUG
	506	.g_register = adv7183_g_register,
	507	.s_register = adv7183_s_register,
	508	#endif
	509	};
	510
	511	static const struct v4l2_subdev_video_ops adv7183_video_ops = {
8774bed9 LP	512	.g_std = adv7183_g_std,
8774bed9 LP	513	.s_std = adv7183_s_std,
202ea1f0 SJ	514	.s_routing = adv7183_s_routing,
	515	.querystd = adv7183_querystd,
	516	.g_input_status = adv7183_g_input_status,
202ea1f0 SJ	517	.s_stream = adv7183_s_stream,
	518	};
	519
ebcff5fc HV	520	static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
ebcff5fc HV	521	.enum_mbus_code = adv7183_enum_mbus_code,
da298c6d	522	.get_fmt = adv7183_get_fmt,
717fd5b4	523	.set_fmt = adv7183_set_fmt,
ebcff5fc HV	524	};
ebcff5fc HV	525
202ea1f0 SJ	526	static const struct v4l2_subdev_ops adv7183_ops = {
	527	.core = &adv7183_core_ops,
	528	.video = &adv7183_video_ops,
ebcff5fc	529	.pad = &adv7183_pad_ops,
202ea1f0 SJ	530	};
	531
	532	static int adv7183_probe(struct i2c_client *client,
	533	const struct i2c_device_id *id)
	534	{
	535	struct adv7183 *decoder;
	536	struct v4l2_subdev *sd;
	537	struct v4l2_ctrl_handler *hdl;
	538	int ret;
717fd5b4 HV	539	struct v4l2_subdev_format fmt = {
	540	.which = V4L2_SUBDEV_FORMAT_ACTIVE,
	541	};
202ea1f0 SJ	542	const unsigned *pin_array;
	543
	544	/* Check if the adapter supports the needed features */
	545	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
	546	return -EIO;
	547
	548	v4l_info(client, "chip found @ 0x%02x (%s)\n",
	549	client->addr << 1, client->adapter->name);
	550
	551	pin_array = client->dev.platform_data;
	552	if (pin_array == NULL)
	553	return -EINVAL;
	554
c02b211d	555	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
202ea1f0 SJ	556	if (decoder == NULL)
	557	return -ENOMEM;
	558
	559	decoder->reset_pin = pin_array[0];
	560	decoder->oe_pin = pin_array[1];
	561
b015ba29 LP	562	if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
b015ba29 LP	563	GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
202ea1f0	564	v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
c02b211d	565	return -EBUSY;
202ea1f0 SJ	566	}
202ea1f0 SJ	567
b015ba29 LP	568	if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
	569	GPIOF_OUT_INIT_HIGH,
	570	"ADV7183 Output Enable")) {
202ea1f0	571	v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
b015ba29	572	return -EBUSY;
202ea1f0 SJ	573	}
	574
	575	sd = &decoder->sd;
	576	v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
	577
	578	hdl = &decoder->hdl;
	579	v4l2_ctrl_handler_init(hdl, 4);
	580	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
	581	V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	582	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
	583	V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
	584	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
	585	V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
	586	v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
	587	V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
	588	/* hook the control handler into the driver */
	589	sd->ctrl_handler = hdl;
	590	if (hdl->error) {
	591	ret = hdl->error;
	592
	593	v4l2_ctrl_handler_free(hdl);
b015ba29	594	return ret;
202ea1f0 SJ	595	}
	596
	597	/* v4l2 doesn't support an autodetect standard, pick PAL as default */
	598	decoder->std = V4L2_STD_PAL;
	599	decoder->input = ADV7183_COMPOSITE4;
	600	decoder->output = ADV7183_8BIT_OUT;
	601
202ea1f0	602	/* reset chip */
202ea1f0 SJ	603	/* reset pulse width at least 5ms */
202ea1f0 SJ	604	mdelay(10);
95323361	605	gpio_set_value(decoder->reset_pin, 1);
202ea1f0 SJ	606	/* wait 5ms before any further i2c writes are performed */
	607	mdelay(5);
	608
	609	adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
	610	adv7183_s_std(sd, decoder->std);
717fd5b4 HV	611	fmt.format.width = 720;
	612	fmt.format.height = 576;
	613	adv7183_set_fmt(sd, NULL, &fmt);
202ea1f0 SJ	614
	615	/* initialize the hardware to the default control values */
	616	ret = v4l2_ctrl_handler_setup(hdl);
	617	if (ret) {
	618	v4l2_ctrl_handler_free(hdl);
b015ba29	619	return ret;
202ea1f0 SJ	620	}
	621
	622	return 0;
202ea1f0 SJ	623	}
	624
	625	static int adv7183_remove(struct i2c_client *client)
	626	{
	627	struct v4l2_subdev *sd = i2c_get_clientdata(client);
202ea1f0 SJ	628
	629	v4l2_device_unregister_subdev(sd);
	630	v4l2_ctrl_handler_free(sd->ctrl_handler);
202ea1f0 SJ	631	return 0;
	632	}
	633
	634	static const struct i2c_device_id adv7183_id[] = {
	635	{"adv7183", 0},
	636	{},
	637	};
	638
	639	MODULE_DEVICE_TABLE(i2c, adv7183_id);
	640
	641	static struct i2c_driver adv7183_driver = {
	642	.driver = {
202ea1f0 SJ	643	.name = "adv7183",
	644	},
	645	.probe = adv7183_probe,
4c62e976	646	.remove = adv7183_remove,
202ea1f0 SJ	647	.id_table = adv7183_id,
	648	};
	649
01aea0bf	650	module_i2c_driver(adv7183_driver);
202ea1f0 SJ	651
	652	MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
	653	MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
	654	MODULE_LICENSE("GPL v2");