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[media] adv7511: drop adv7511_set_IT_content_AVI_InfoFrame
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / adv7511.c
CommitLineData
5a544cce
HV		 1/*
2 * Analog Devices ADV7511 HDMI Transmitter Device Driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/i2c.h>
25#include <linux/delay.h>
26#include <linux/videodev2.h>
27#include <linux/gpio.h>
28#include <linux/workqueue.h>
1fb69bfd 29#include <linux/hdmi.h>
5a544cce
HV		 30#include <linux/v4l2-dv-timings.h>
31#include <media/v4l2-device.h>
32#include <media/v4l2-common.h>
33#include <media/v4l2-ctrls.h>
34#include <media/v4l2-dv-timings.h>
b5dcee22 35#include <media/i2c/adv7511.h>
257d4eae 36#include <media/cec.h>
5a544cce
HV		 37
38static int debug;
39module_param(debug, int, 0644);
40MODULE_PARM_DESC(debug, "debug level (0-2)");
41
42MODULE_DESCRIPTION("Analog Devices ADV7511 HDMI Transmitter Device Driver");
43MODULE_AUTHOR("Hans Verkuil");
8f7a5f46 44MODULE_LICENSE("GPL v2");
5a544cce
HV		 45
46#define MASK_ADV7511_EDID_RDY_INT 0x04
47#define MASK_ADV7511_MSEN_INT 0x40
48#define MASK_ADV7511_HPD_INT 0x80
49
50#define MASK_ADV7511_HPD_DETECT 0x40
51#define MASK_ADV7511_MSEN_DETECT 0x20
52#define MASK_ADV7511_EDID_RDY 0x10
53
54#define EDID_MAX_RETRIES (8)
55#define EDID_DELAY 250
56#define EDID_MAX_SEGM 8
57
58#define ADV7511_MAX_WIDTH 1920
59#define ADV7511_MAX_HEIGHT 1200
60#define ADV7511_MIN_PIXELCLOCK 20000000
61#define ADV7511_MAX_PIXELCLOCK 225000000
62
257d4eae
HV		 63#define ADV7511_MAX_ADDRS (3)
64
5a544cce
HV		 65/*
66**********************************************************************
67*
68* Arrays with configuration parameters for the ADV7511
69*
70**********************************************************************
71*/
72
73struct i2c_reg_value {
74 unsigned char reg;
75 unsigned char value;
76};
77
78struct adv7511_state_edid {
79 /* total number of blocks */
80 u32 blocks;
81 /* Number of segments read */
82 u32 segments;
5be50ef1 83 u8 data[EDID_MAX_SEGM * 256];
5a544cce
HV		 84 /* Number of EDID read retries left */
85 unsigned read_retries;
86 bool complete;
87};
88
89struct adv7511_state {
90 struct adv7511_platform_data pdata;
91 struct v4l2_subdev sd;
92 struct media_pad pad;
93 struct v4l2_ctrl_handler hdl;
94 int chip_revision;
5be50ef1 95 u8 i2c_edid_addr;
b4dbad8f 96 u8 i2c_pktmem_addr;
257d4eae
HV		 97 u8 i2c_cec_addr;
98
99 struct i2c_client *i2c_cec;
100 struct cec_adapter *cec_adap;
101 u8 cec_addr[ADV7511_MAX_ADDRS];
102 u8 cec_valid_addrs;
103 bool cec_enabled_adap;
104
5a544cce
HV		 105 /* Is the adv7511 powered on? */
106 bool power_on;
107 /* Did we receive hotplug and rx-sense signals? */
108 bool have_monitor;
257d4eae 109 bool enabled_irq;
5a544cce
HV		 110 /* timings from s_dv_timings */
111 struct v4l2_dv_timings dv_timings;
1fb69bfd
HV		 112 u32 fmt_code;
113 u32 colorspace;
114 u32 ycbcr_enc;
115 u32 quantization;
e719a51a 116 u32 xfer_func;
df0e5775 117 u32 content_type;
5a544cce
HV		 118 /* controls */
119 struct v4l2_ctrl *hdmi_mode_ctrl;
120 struct v4l2_ctrl *hotplug_ctrl;
121 struct v4l2_ctrl *rx_sense_ctrl;
122 struct v4l2_ctrl *have_edid0_ctrl;
123 struct v4l2_ctrl *rgb_quantization_range_ctrl;
df0e5775 124 struct v4l2_ctrl *content_type_ctrl;
5a544cce 125 struct i2c_client *i2c_edid;
b4dbad8f 126 struct i2c_client *i2c_pktmem;
5a544cce
HV		 127 struct adv7511_state_edid edid;
128 /* Running counter of the number of detected EDIDs (for debugging) */
129 unsigned edid_detect_counter;
130 struct workqueue_struct *work_queue;
131 struct delayed_work edid_handler; /* work entry */
132};
133
134static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd);
135static bool adv7511_check_edid_status(struct v4l2_subdev *sd);
136static void adv7511_setup(struct v4l2_subdev *sd);
137static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
138static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
139
140
141static const struct v4l2_dv_timings_cap adv7511_timings_cap = {
142 .type = V4L2_DV_BT_656_1120,
aefd4a5a
GG		 143 /* keep this initialization for compatibility with GCC < 4.4.6 */
144 .reserved = { 0 },
145 V4L2_INIT_BT_TIMINGS(0, ADV7511_MAX_WIDTH, 0, ADV7511_MAX_HEIGHT,
146 ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK,
147 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
5a544cce 148 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
aefd4a5a
GG		 149 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
150 V4L2_DV_BT_CAP_CUSTOM)
5a544cce
HV		 151};
152
153static inline struct adv7511_state *get_adv7511_state(struct v4l2_subdev *sd)
154{
155 return container_of(sd, struct adv7511_state, sd);
156}
157
158static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
159{
160 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd;
161}
162
163/* ------------------------ I2C ----------------------------------------------- */
164
165static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
166 u8 command, bool check)
167{
168 union i2c_smbus_data data;
169
170 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
171 I2C_SMBUS_READ, command,
172 I2C_SMBUS_BYTE_DATA, &data))
173 return data.byte;
174 if (check)
175 v4l_err(client, "error reading %02x, %02x\n",
176 client->addr, command);
177 return -1;
178}
179
180static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
181{
182 int i;
183 for (i = 0; i < 3; i++) {
184 int ret = adv_smbus_read_byte_data_check(client, command, true);
185 if (ret >= 0) {
186 if (i)
187 v4l_err(client, "read ok after %d retries\n", i);
188 return ret;
189 }
190 }
191 v4l_err(client, "read failed\n");
192 return -1;
193}
194
195static int adv7511_rd(struct v4l2_subdev *sd, u8 reg)
196{
197 struct i2c_client *client = v4l2_get_subdevdata(sd);
198
199 return adv_smbus_read_byte_data(client, reg);
200}
201
202static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
203{
204 struct i2c_client *client = v4l2_get_subdevdata(sd);
205 int ret;
206 int i;
207
208 for (i = 0; i < 3; i++) {
209 ret = i2c_smbus_write_byte_data(client, reg, val);
210 if (ret == 0)
211 return 0;
212 }
213 v4l2_err(sd, "%s: i2c write error\n", __func__);
214 return ret;
215}
216
217/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
218 and then the value-mask (to be OR-ed). */
5be50ef1 219static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask)
5a544cce
HV		 220{
221 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask);
222}
223
224static int adv_smbus_read_i2c_block_data(struct i2c_client *client,
225 u8 command, unsigned length, u8 *values)
226{
227 union i2c_smbus_data data;
228 int ret;
229
230 if (length > I2C_SMBUS_BLOCK_MAX)
231 length = I2C_SMBUS_BLOCK_MAX;
232 data.block[0] = length;
233
234 ret = i2c_smbus_xfer(client->adapter, client->addr, client->flags,
235 I2C_SMBUS_READ, command,
236 I2C_SMBUS_I2C_BLOCK_DATA, &data);
237 memcpy(values, data.block + 1, length);
238 return ret;
239}
240
257d4eae 241static void adv7511_edid_rd(struct v4l2_subdev *sd, uint16_t len, uint8_t *buf)
5a544cce
HV		 242{
243 struct adv7511_state *state = get_adv7511_state(sd);
244 int i;
245 int err = 0;
246
247 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
248
249 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
250 err = adv_smbus_read_i2c_block_data(state->i2c_edid, i,
251 I2C_SMBUS_BLOCK_MAX, buf + i);
252 if (err)
253 v4l2_err(sd, "%s: i2c read error\n", __func__);
254}
255
257d4eae
HV		 256static inline int adv7511_cec_read(struct v4l2_subdev *sd, u8 reg)
257{
258 struct adv7511_state *state = get_adv7511_state(sd);
259
260 return i2c_smbus_read_byte_data(state->i2c_cec, reg);
261}
262
263static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
264{
265 struct adv7511_state *state = get_adv7511_state(sd);
266 int ret;
267 int i;
268
269 for (i = 0; i < 3; i++) {
270 ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val);
271 if (ret == 0)
272 return 0;
273 }
274 v4l2_err(sd, "%s: I2C Write Problem\n", __func__);
275 return ret;
276}
277
278static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask,
279 u8 val)
280{
281 return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val);
282}
283
b4dbad8f
HV		 284static int adv7511_pktmem_rd(struct v4l2_subdev *sd, u8 reg)
285{
286 struct adv7511_state *state = get_adv7511_state(sd);
287
288 return adv_smbus_read_byte_data(state->i2c_pktmem, reg);
289}
290
291static int adv7511_pktmem_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
292{
293 struct adv7511_state *state = get_adv7511_state(sd);
294 int ret;
295 int i;
296
297 for (i = 0; i < 3; i++) {
298 ret = i2c_smbus_write_byte_data(state->i2c_pktmem, reg, val);
299 if (ret == 0)
300 return 0;
301 }
302 v4l2_err(sd, "%s: i2c write error\n", __func__);
303 return ret;
304}
305
306/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
307 and then the value-mask (to be OR-ed). */
308static inline void adv7511_pktmem_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask)
309{
310 adv7511_pktmem_wr(sd, reg, (adv7511_pktmem_rd(sd, reg) & clr_mask) | val_mask);
311}
312
5a544cce
HV		 313static inline bool adv7511_have_hotplug(struct v4l2_subdev *sd)
314{
315 return adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT;
316}
317
318static inline bool adv7511_have_rx_sense(struct v4l2_subdev *sd)
319{
320 return adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT;
321}
322
5be50ef1 323static void adv7511_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
5a544cce
HV		 324{
325 adv7511_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
326}
327
328static void adv7511_csc_coeff(struct v4l2_subdev *sd,
329 u16 A1, u16 A2, u16 A3, u16 A4,
330 u16 B1, u16 B2, u16 B3, u16 B4,
331 u16 C1, u16 C2, u16 C3, u16 C4)
332{
333 /* A */
334 adv7511_wr_and_or(sd, 0x18, 0xe0, A1>>8);
335 adv7511_wr(sd, 0x19, A1);
336 adv7511_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
337 adv7511_wr(sd, 0x1B, A2);
338 adv7511_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
339 adv7511_wr(sd, 0x1d, A3);
340 adv7511_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
341 adv7511_wr(sd, 0x1f, A4);
342
343 /* B */
344 adv7511_wr_and_or(sd, 0x20, 0xe0, B1>>8);
345 adv7511_wr(sd, 0x21, B1);
346 adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8);
347 adv7511_wr(sd, 0x23, B2);
348 adv7511_wr_and_or(sd, 0x24, 0xe0, B3>>8);
349 adv7511_wr(sd, 0x25, B3);
350 adv7511_wr_and_or(sd, 0x26, 0xe0, B4>>8);
351 adv7511_wr(sd, 0x27, B4);
352
353 /* C */
354 adv7511_wr_and_or(sd, 0x28, 0xe0, C1>>8);
355 adv7511_wr(sd, 0x29, C1);
356 adv7511_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
357 adv7511_wr(sd, 0x2B, C2);
358 adv7511_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
359 adv7511_wr(sd, 0x2D, C3);
360 adv7511_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
361 adv7511_wr(sd, 0x2F, C4);
362}
363
364static void adv7511_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
365{
366 if (enable) {
5be50ef1 367 u8 csc_mode = 0;
5a544cce
HV		 368 adv7511_csc_conversion_mode(sd, csc_mode);
369 adv7511_csc_coeff(sd,
370 4096-564, 0, 0, 256,
371 0, 4096-564, 0, 256,
372 0, 0, 4096-564, 256);
373 /* enable CSC */
374 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x80);
375 /* AVI infoframe: Limited range RGB (16-235) */
376 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x04);
377 } else {
378 /* disable CSC */
379 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
380 /* AVI infoframe: Full range RGB (0-255) */
381 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x08);
382 }
383}
384
5a544cce
HV		 385static int adv7511_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
386{
387 switch (ctrl->val) {
388 default:
389 return -EINVAL;
390 break;
391 case V4L2_DV_RGB_RANGE_AUTO: {
392 /* automatic */
393 struct adv7511_state *state = get_adv7511_state(sd);
394
680fee04
HV		 395 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
396 /* CE format, RGB limited range (16-235) */
5a544cce
HV		 397 adv7511_csc_rgb_full2limit(sd, true);
398 } else {
680fee04 399 /* not CE format, RGB full range (0-255) */
5a544cce
HV		 400 adv7511_csc_rgb_full2limit(sd, false);
401 }
402 }
403 break;
404 case V4L2_DV_RGB_RANGE_LIMITED:
405 /* RGB limited range (16-235) */
406 adv7511_csc_rgb_full2limit(sd, true);
407 break;
408 case V4L2_DV_RGB_RANGE_FULL:
409 /* RGB full range (0-255) */
410 adv7511_csc_rgb_full2limit(sd, false);
411 break;
412 }
413 return 0;
414}
415
416/* ------------------------------ CTRL OPS ------------------------------ */
417
418static int adv7511_s_ctrl(struct v4l2_ctrl *ctrl)
419{
420 struct v4l2_subdev *sd = to_sd(ctrl);
421 struct adv7511_state *state = get_adv7511_state(sd);
422
423 v4l2_dbg(1, debug, sd, "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
424
425 if (state->hdmi_mode_ctrl == ctrl) {
426 /* Set HDMI or DVI-D */
427 adv7511_wr_and_or(sd, 0xaf, 0xfd, ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
428 return 0;
429 }
430 if (state->rgb_quantization_range_ctrl == ctrl)
431 return adv7511_set_rgb_quantization_mode(sd, ctrl);
df0e5775
HV		 432 if (state->content_type_ctrl == ctrl) {
433 u8 itc, cn;
434
435 state->content_type = ctrl->val;
436 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
437 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
438 adv7511_wr_and_or(sd, 0x57, 0x7f, itc << 7);
439 adv7511_wr_and_or(sd, 0x59, 0xcf, cn << 4);
440 return 0;
441 }
5a544cce
HV		 442
443 return -EINVAL;
444}
445
446static const struct v4l2_ctrl_ops adv7511_ctrl_ops = {
447 .s_ctrl = adv7511_s_ctrl,
448};
449
450/* ---------------------------- CORE OPS ------------------------------------------- */
451
452#ifdef CONFIG_VIDEO_ADV_DEBUG
453static void adv7511_inv_register(struct v4l2_subdev *sd)
454{
257d4eae
HV		 455 struct adv7511_state *state = get_adv7511_state(sd);
456
5a544cce 457 v4l2_info(sd, "0x000-0x0ff: Main Map\n");
257d4eae
HV		 458 if (state->i2c_cec)
459 v4l2_info(sd, "0x100-0x1ff: CEC Map\n");
5a544cce
HV		 460}
461
462static int adv7511_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
463{
257d4eae
HV		 464 struct adv7511_state *state = get_adv7511_state(sd);
465
5a544cce
HV		 466 reg->size = 1;
467 switch (reg->reg >> 8) {
468 case 0:
469 reg->val = adv7511_rd(sd, reg->reg & 0xff);
470 break;
257d4eae
HV		 471 case 1:
472 if (state->i2c_cec) {
473 reg->val = adv7511_cec_read(sd, reg->reg & 0xff);
474 break;
475 }
476 /* fall through */
5a544cce
HV		 477 default:
478 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
479 adv7511_inv_register(sd);
480 break;
481 }
482 return 0;
483}
484
485static int adv7511_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
486{
257d4eae
HV		 487 struct adv7511_state *state = get_adv7511_state(sd);
488
5a544cce
HV		 489 switch (reg->reg >> 8) {
490 case 0:
491 adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff);
492 break;
257d4eae
HV		 493 case 1:
494 if (state->i2c_cec) {
495 adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
496 break;
497 }
498 /* fall through */
5a544cce
HV		 499 default:
500 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
501 adv7511_inv_register(sd);
502 break;
503 }
504 return 0;
505}
506#endif
507
b4dbad8f
HV		 508struct adv7511_cfg_read_infoframe {
509 const char *desc;
510 u8 present_reg;
511 u8 present_mask;
512 u8 header[3];
513 u16 payload_addr;
514};
515
516static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size)
517{
518 u8 csum = 0;
519 size_t i;
520
521 /* compute checksum */
522 for (i = 0; i < size; i++)
523 csum += ptr[i];
524
525 return 256 - csum;
526}
527
528static void log_infoframe(struct v4l2_subdev *sd, const struct adv7511_cfg_read_infoframe *cri)
529{
530 struct i2c_client *client = v4l2_get_subdevdata(sd);
531 struct device *dev = &client->dev;
532 union hdmi_infoframe frame;
533 u8 buffer[32];
534 u8 len;
535 int i;
536
537 if (!(adv7511_rd(sd, cri->present_reg) & cri->present_mask)) {
538 v4l2_info(sd, "%s infoframe not transmitted\n", cri->desc);
539 return;
540 }
541
542 memcpy(buffer, cri->header, sizeof(cri->header));
543
544 len = buffer[2];
545
546 if (len + 4 > sizeof(buffer)) {
547 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
548 return;
549 }
550
551 if (cri->payload_addr >= 0x100) {
552 for (i = 0; i < len; i++)
553 buffer[i + 4] = adv7511_pktmem_rd(sd, cri->payload_addr + i - 0x100);
554 } else {
555 for (i = 0; i < len; i++)
556 buffer[i + 4] = adv7511_rd(sd, cri->payload_addr + i);
557 }
558 buffer[3] = 0;
559 buffer[3] = hdmi_infoframe_checksum(buffer, len + 4);
560
561 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
562 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
563 return;
564 }
565
566 hdmi_infoframe_log(KERN_INFO, dev, &frame);
567}
568
569static void adv7511_log_infoframes(struct v4l2_subdev *sd)
570{
571 static const struct adv7511_cfg_read_infoframe cri[] = {
572 { "AVI", 0x44, 0x10, { 0x82, 2, 13 }, 0x55 },
573 { "Audio", 0x44, 0x08, { 0x84, 1, 10 }, 0x73 },
574 { "SDP", 0x40, 0x40, { 0x83, 1, 25 }, 0x103 },
575 };
576 int i;
577
578 for (i = 0; i < ARRAY_SIZE(cri); i++)
579 log_infoframe(sd, &cri[i]);
580}
581
5a544cce
HV		 582static int adv7511_log_status(struct v4l2_subdev *sd)
583{
584 struct adv7511_state *state = get_adv7511_state(sd);
585 struct adv7511_state_edid *edid = &state->edid;
257d4eae 586 int i;
5a544cce
HV		 587
588 static const char * const states[] = {
589 "in reset",
590 "reading EDID",
591 "idle",
592 "initializing HDCP",
593 "HDCP enabled",
594 "initializing HDCP repeater",
595 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
596 };
597 static const char * const errors[] = {
598 "no error",
599 "bad receiver BKSV",
600 "Ri mismatch",
601 "Pj mismatch",
602 "i2c error",
603 "timed out",
604 "max repeater cascade exceeded",
605 "hash check failed",
606 "too many devices",
607 "9", "A", "B", "C", "D", "E", "F"
608 };
609
610 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
611 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
612 (adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT) ? "detected" : "no",
613 (adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT) ? "detected" : "no",
614 edid->segments ? "found" : "no",
615 edid->blocks);
616 v4l2_info(sd, "%s output %s\n",
617 (adv7511_rd(sd, 0xaf) & 0x02) ?
618 "HDMI" : "DVI-D",
619 (adv7511_rd(sd, 0xa1) & 0x3c) ?
620 "disabled" : "enabled");
621 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
622 states[adv7511_rd(sd, 0xc8) & 0xf],
623 errors[adv7511_rd(sd, 0xc8) >> 4], state->edid_detect_counter,
624 adv7511_rd(sd, 0x94), adv7511_rd(sd, 0x96));
625 v4l2_info(sd, "RGB quantization: %s range\n", adv7511_rd(sd, 0x18) & 0x80 ? "limited" : "full");
3ecabed1
MB		 626 if (adv7511_rd(sd, 0xaf) & 0x02) {
627 /* HDMI only */
628 u8 manual_cts = adv7511_rd(sd, 0x0a) & 0x80;
629 u32 N = (adv7511_rd(sd, 0x01) & 0xf) << 16 |
630 adv7511_rd(sd, 0x02) << 8 |
631 adv7511_rd(sd, 0x03);
632 u8 vic_detect = adv7511_rd(sd, 0x3e) >> 2;
633 u8 vic_sent = adv7511_rd(sd, 0x3d) & 0x3f;
634 u32 CTS;
635
636 if (manual_cts)
637 CTS = (adv7511_rd(sd, 0x07) & 0xf) << 16 |
638 adv7511_rd(sd, 0x08) << 8 |
639 adv7511_rd(sd, 0x09);
640 else
641 CTS = (adv7511_rd(sd, 0x04) & 0xf) << 16 |
642 adv7511_rd(sd, 0x05) << 8 |
643 adv7511_rd(sd, 0x06);
644 v4l2_info(sd, "CTS %s mode: N %d, CTS %d\n",
645 manual_cts ? "manual" : "automatic", N, CTS);
646 v4l2_info(sd, "VIC: detected %d, sent %d\n",
647 vic_detect, vic_sent);
b4dbad8f 648 adv7511_log_infoframes(sd);
3ecabed1 649 }
5a544cce
HV		 650 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
651 v4l2_print_dv_timings(sd->name, "timings: ",
652 &state->dv_timings, false);
653 else
654 v4l2_info(sd, "no timings set\n");
655 v4l2_info(sd, "i2c edid addr: 0x%x\n", state->i2c_edid_addr);
257d4eae
HV		 656
657 if (state->i2c_cec == NULL)
658 return 0;
659
5a544cce 660 v4l2_info(sd, "i2c cec addr: 0x%x\n", state->i2c_cec_addr);
257d4eae
HV		 661
662 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
663 "enabled" : "disabled");
664 if (state->cec_enabled_adap) {
665 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
666 bool is_valid = state->cec_valid_addrs & (1 << i);
667
668 if (is_valid)
669 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
670 state->cec_addr[i]);
671 }
672 }
b4dbad8f 673 v4l2_info(sd, "i2c pktmem addr: 0x%x\n", state->i2c_pktmem_addr);
5a544cce
HV		 674 return 0;
675}
676
677/* Power up/down adv7511 */
678static int adv7511_s_power(struct v4l2_subdev *sd, int on)
679{
680 struct adv7511_state *state = get_adv7511_state(sd);
681 const int retries = 20;
682 int i;
683
684 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
685
686 state->power_on = on;
687
688 if (!on) {
689 /* Power down */
690 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
691 return true;
692 }
693
694 /* Power up */
695 /* The adv7511 does not always come up immediately.
696 Retry multiple times. */
697 for (i = 0; i < retries; i++) {
698 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x0);
699 if ((adv7511_rd(sd, 0x41) & 0x40) == 0)
700 break;
701 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
702 msleep(10);
703 }
704 if (i == retries) {
705 v4l2_dbg(1, debug, sd, "%s: failed to powerup the adv7511!\n", __func__);
706 adv7511_s_power(sd, 0);
707 return false;
708 }
709 if (i > 1)
710 v4l2_dbg(1, debug, sd, "%s: needed %d retries to powerup the adv7511\n", __func__, i);
711
712 /* Reserved registers that must be set */
713 adv7511_wr(sd, 0x98, 0x03);
714 adv7511_wr_and_or(sd, 0x9a, 0xfe, 0x70);
715 adv7511_wr(sd, 0x9c, 0x30);
716 adv7511_wr_and_or(sd, 0x9d, 0xfc, 0x01);
717 adv7511_wr(sd, 0xa2, 0xa4);
718 adv7511_wr(sd, 0xa3, 0xa4);
719 adv7511_wr(sd, 0xe0, 0xd0);
720 adv7511_wr(sd, 0xf9, 0x00);
721
722 adv7511_wr(sd, 0x43, state->i2c_edid_addr);
b4dbad8f 723 adv7511_wr(sd, 0x45, state->i2c_pktmem_addr);
5a544cce
HV		 724
725 /* Set number of attempts to read the EDID */
726 adv7511_wr(sd, 0xc9, 0xf);
727 return true;
728}
729
257d4eae
HV		 730#if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
731static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
732{
733 struct adv7511_state *state = adap->priv;
734 struct v4l2_subdev *sd = &state->sd;
735
736 if (state->i2c_cec == NULL)
737 return -EIO;
738
739 if (!state->cec_enabled_adap && enable) {
740 /* power up cec section */
741 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x01);
742 /* legacy mode and clear all rx buffers */
743 adv7511_cec_write(sd, 0x4a, 0x07);
744 adv7511_cec_write(sd, 0x4a, 0);
745 adv7511_cec_write_and_or(sd, 0x11, 0xfe, 0); /* initially disable tx */
746 /* enabled irqs: */
747 /* tx: ready */
748 /* tx: arbitration lost */
749 /* tx: retry timeout */
750 /* rx: ready 1 */
751 if (state->enabled_irq)
752 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x39);
753 } else if (state->cec_enabled_adap && !enable) {
754 if (state->enabled_irq)
755 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x00);
756 /* disable address mask 1-3 */
757 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0x00);
758 /* power down cec section */
759 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x00);
760 state->cec_valid_addrs = 0;
761 }
762 state->cec_enabled_adap = enable;
763 return 0;
764}
765
766static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
767{
768 struct adv7511_state *state = adap->priv;
769 struct v4l2_subdev *sd = &state->sd;
770 unsigned int i, free_idx = ADV7511_MAX_ADDRS;
771
772 if (!state->cec_enabled_adap)
773 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
774
775 if (addr == CEC_LOG_ADDR_INVALID) {
776 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0);
777 state->cec_valid_addrs = 0;
778 return 0;
779 }
780
781 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
782 bool is_valid = state->cec_valid_addrs & (1 << i);
783
784 if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
785 free_idx = i;
786 if (is_valid && state->cec_addr[i] == addr)
787 return 0;
788 }
789 if (i == ADV7511_MAX_ADDRS) {
790 i = free_idx;
791 if (i == ADV7511_MAX_ADDRS)
792 return -ENXIO;
793 }
794 state->cec_addr[i] = addr;
795 state->cec_valid_addrs |= 1 << i;
796
797 switch (i) {
798 case 0:
799 /* enable address mask 0 */
800 adv7511_cec_write_and_or(sd, 0x4b, 0xef, 0x10);
801 /* set address for mask 0 */
802 adv7511_cec_write_and_or(sd, 0x4c, 0xf0, addr);
803 break;
804 case 1:
805 /* enable address mask 1 */
806 adv7511_cec_write_and_or(sd, 0x4b, 0xdf, 0x20);
807 /* set address for mask 1 */
808 adv7511_cec_write_and_or(sd, 0x4c, 0x0f, addr << 4);
809 break;
810 case 2:
811 /* enable address mask 2 */
812 adv7511_cec_write_and_or(sd, 0x4b, 0xbf, 0x40);
813 /* set address for mask 1 */
814 adv7511_cec_write_and_or(sd, 0x4d, 0xf0, addr);
815 break;
816 }
817 return 0;
818}
819
820static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
821 u32 signal_free_time, struct cec_msg *msg)
822{
823 struct adv7511_state *state = adap->priv;
824 struct v4l2_subdev *sd = &state->sd;
825 u8 len = msg->len;
826 unsigned int i;
827
828 v4l2_dbg(1, debug, sd, "%s: len %d\n", __func__, len);
829
830 if (len > 16) {
831 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
832 return -EINVAL;
833 }
834
835 /*
836 * The number of retries is the number of attempts - 1, but retry
837 * at least once. It's not clear if a value of 0 is allowed, so
838 * let's do at least one retry.
839 */
840 adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4);
841
842 /* blocking, clear cec tx irq status */
843 adv7511_wr_and_or(sd, 0x97, 0xc7, 0x38);
844
845 /* write data */
846 for (i = 0; i < len; i++)
847 adv7511_cec_write(sd, i, msg->msg[i]);
848
849 /* set length (data + header) */
850 adv7511_cec_write(sd, 0x10, len);
851 /* start transmit, enable tx */
852 adv7511_cec_write(sd, 0x11, 0x01);
853 return 0;
854}
855
856static void adv_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
857{
858 struct adv7511_state *state = get_adv7511_state(sd);
859
860 if ((adv7511_cec_read(sd, 0x11) & 0x01) == 0) {
861 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
862 return;
863 }
864
865 if (tx_raw_status & 0x10) {
866 v4l2_dbg(1, debug, sd,
867 "%s: tx raw: arbitration lost\n", __func__);
868 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
869 1, 0, 0, 0);
870 return;
871 }
872 if (tx_raw_status & 0x08) {
873 u8 status;
874 u8 nack_cnt;
875 u8 low_drive_cnt;
876
877 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
878 /*
879 * We set this status bit since this hardware performs
880 * retransmissions.
881 */
882 status = CEC_TX_STATUS_MAX_RETRIES;
883 nack_cnt = adv7511_cec_read(sd, 0x14) & 0xf;
884 if (nack_cnt)
885 status |= CEC_TX_STATUS_NACK;
886 low_drive_cnt = adv7511_cec_read(sd, 0x14) >> 4;
887 if (low_drive_cnt)
888 status |= CEC_TX_STATUS_LOW_DRIVE;
889 cec_transmit_done(state->cec_adap, status,
890 0, nack_cnt, low_drive_cnt, 0);
891 return;
892 }
893 if (tx_raw_status & 0x20) {
894 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
895 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
896 return;
897 }
898}
899
900static const struct cec_adap_ops adv7511_cec_adap_ops = {
901 .adap_enable = adv7511_cec_adap_enable,
902 .adap_log_addr = adv7511_cec_adap_log_addr,
903 .adap_transmit = adv7511_cec_adap_transmit,
904};
905#endif
906
5a544cce
HV		 907/* Enable interrupts */
908static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable)
909{
257d4eae 910 struct adv7511_state *state = get_adv7511_state(sd);
5be50ef1
HV		 911 u8 irqs = MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT;
912 u8 irqs_rd;
5a544cce
HV		 913 int retries = 100;
914
915 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? "enable" : "disable");
916
257d4eae
HV		 917 if (state->enabled_irq == enable)
918 return;
919 state->enabled_irq = enable;
920
5a544cce
HV		 921 /* The datasheet says that the EDID ready interrupt should be
922 disabled if there is no hotplug. */
923 if (!enable)
924 irqs = 0;
925 else if (adv7511_have_hotplug(sd))
926 irqs |= MASK_ADV7511_EDID_RDY_INT;
927
257d4eae
HV		 928 adv7511_wr_and_or(sd, 0x95, 0xc0,
929 (state->cec_enabled_adap && enable) ? 0x39 : 0x00);
930
5a544cce
HV		 931 /*
932 * This i2c write can fail (approx. 1 in 1000 writes). But it
933 * is essential that this register is correct, so retry it
934 * multiple times.
935 *
936 * Note that the i2c write does not report an error, but the readback
937 * clearly shows the wrong value.
938 */
939 do {
940 adv7511_wr(sd, 0x94, irqs);
941 irqs_rd = adv7511_rd(sd, 0x94);
942 } while (retries-- && irqs_rd != irqs);
943
944 if (irqs_rd == irqs)
945 return;
946 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
947}
948
949/* Interrupt handler */
950static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
951{
5be50ef1 952 u8 irq_status;
257d4eae 953 u8 cec_irq;
5a544cce
HV		 954
955 /* disable interrupts to prevent a race condition */
956 adv7511_set_isr(sd, false);
957 irq_status = adv7511_rd(sd, 0x96);
257d4eae 958 cec_irq = adv7511_rd(sd, 0x97);
5a544cce
HV		 959 /* clear detected interrupts */
960 adv7511_wr(sd, 0x96, irq_status);
257d4eae 961 adv7511_wr(sd, 0x97, cec_irq);
5a544cce 962
257d4eae
HV		 963 v4l2_dbg(1, debug, sd, "%s: irq 0x%x, cec-irq 0x%x\n", __func__,
964 irq_status, cec_irq);
5a544cce
HV		 965
966 if (irq_status & (MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT))
967 adv7511_check_monitor_present_status(sd);
968 if (irq_status & MASK_ADV7511_EDID_RDY_INT)
969 adv7511_check_edid_status(sd);
970
257d4eae
HV		 971#if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
972 if (cec_irq & 0x38)
973 adv_cec_tx_raw_status(sd, cec_irq);
974
975 if (cec_irq & 1) {
976 struct adv7511_state *state = get_adv7511_state(sd);
977 struct cec_msg msg;
978
979 msg.len = adv7511_cec_read(sd, 0x25) & 0x1f;
980
981 v4l2_dbg(1, debug, sd, "%s: cec msg len %d\n", __func__,
982 msg.len);
983
984 if (msg.len > 16)
985 msg.len = 16;
986
987 if (msg.len) {
988 u8 i;
989
990 for (i = 0; i < msg.len; i++)
991 msg.msg[i] = adv7511_cec_read(sd, i + 0x15);
992
993 adv7511_cec_write(sd, 0x4a, 1); /* toggle to re-enable rx 1 */
994 adv7511_cec_write(sd, 0x4a, 0);
995 cec_received_msg(state->cec_adap, &msg);
996 }
997 }
998#endif
999
5a544cce
HV		 1000 /* enable interrupts */
1001 adv7511_set_isr(sd, true);
1002
1003 if (handled)
1004 *handled = true;
1005 return 0;
1006}
1007
5a544cce
HV		 1008static const struct v4l2_subdev_core_ops adv7511_core_ops = {
1009 .log_status = adv7511_log_status,
1010#ifdef CONFIG_VIDEO_ADV_DEBUG
1011 .g_register = adv7511_g_register,
1012 .s_register = adv7511_s_register,
1013#endif
1014 .s_power = adv7511_s_power,
1015 .interrupt_service_routine = adv7511_isr,
1016};
1017
1018/* ------------------------------ VIDEO OPS ------------------------------ */
1019
1020/* Enable/disable adv7511 output */
1021static int adv7511_s_stream(struct v4l2_subdev *sd, int enable)
1022{
1023 struct adv7511_state *state = get_adv7511_state(sd);
1024
1025 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1026 adv7511_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
1027 if (enable) {
1028 adv7511_check_monitor_present_status(sd);
1029 } else {
1030 adv7511_s_power(sd, 0);
1031 state->have_monitor = false;
1032 }
1033 return 0;
1034}
1035
1036static int adv7511_s_dv_timings(struct v4l2_subdev *sd,
1037 struct v4l2_dv_timings *timings)
1038{
1039 struct adv7511_state *state = get_adv7511_state(sd);
1040
1041 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1042
1043 /* quick sanity check */
1044 if (!v4l2_valid_dv_timings(timings, &adv7511_timings_cap, NULL, NULL))
1045 return -EINVAL;
1046
1047 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1048 if the format is one of the CEA or DMT timings. */
1049 v4l2_find_dv_timings_cap(timings, &adv7511_timings_cap, 0, NULL, NULL);
1050
1051 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
1052
1053 /* save timings */
1054 state->dv_timings = *timings;
1055
1056 /* update quantization range based on new dv_timings */
1057 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1058
5a544cce
HV		 1059 return 0;
1060}
1061
1062static int adv7511_g_dv_timings(struct v4l2_subdev *sd,
1063 struct v4l2_dv_timings *timings)
1064{
1065 struct adv7511_state *state = get_adv7511_state(sd);
1066
1067 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1068
1069 if (!timings)
1070 return -EINVAL;
1071
1072 *timings = state->dv_timings;
1073
1074 return 0;
1075}
1076
1077static int adv7511_enum_dv_timings(struct v4l2_subdev *sd,
1078 struct v4l2_enum_dv_timings *timings)
1079{
9646171f
LP		 1080 if (timings->pad != 0)
1081 return -EINVAL;
1082
5a544cce
HV		 1083 return v4l2_enum_dv_timings_cap(timings, &adv7511_timings_cap, NULL, NULL);
1084}
1085
1086static int adv7511_dv_timings_cap(struct v4l2_subdev *sd,
1087 struct v4l2_dv_timings_cap *cap)
1088{
9646171f
LP		 1089 if (cap->pad != 0)
1090 return -EINVAL;
1091
5a544cce
HV		 1092 *cap = adv7511_timings_cap;
1093 return 0;
1094}
1095
1096static const struct v4l2_subdev_video_ops adv7511_video_ops = {
1097 .s_stream = adv7511_s_stream,
1098 .s_dv_timings = adv7511_s_dv_timings,
1099 .g_dv_timings = adv7511_g_dv_timings,
5a544cce
HV		 1100};
1101
1102/* ------------------------------ AUDIO OPS ------------------------------ */
1103static int adv7511_s_audio_stream(struct v4l2_subdev *sd, int enable)
1104{
1105 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1106
1107 if (enable)
1108 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x80);
1109 else
1110 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x40);
1111
1112 return 0;
1113}
1114
1115static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1116{
1117 u32 N;
1118
1119 switch (freq) {
1120 case 32000: N = 4096; break;
1121 case 44100: N = 6272; break;
1122 case 48000: N = 6144; break;
1123 case 88200: N = 12544; break;
1124 case 96000: N = 12288; break;
1125 case 176400: N = 25088; break;
1126 case 192000: N = 24576; break;
1127 default:
1128 return -EINVAL;
1129 }
1130
1131 /* Set N (used with CTS to regenerate the audio clock) */
1132 adv7511_wr(sd, 0x01, (N >> 16) & 0xf);
1133 adv7511_wr(sd, 0x02, (N >> 8) & 0xff);
1134 adv7511_wr(sd, 0x03, N & 0xff);
1135
1136 return 0;
1137}
1138
1139static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1140{
1141 u32 i2s_sf;
1142
1143 switch (freq) {
1144 case 32000: i2s_sf = 0x30; break;
1145 case 44100: i2s_sf = 0x00; break;
1146 case 48000: i2s_sf = 0x20; break;
1147 case 88200: i2s_sf = 0x80; break;
1148 case 96000: i2s_sf = 0xa0; break;
1149 case 176400: i2s_sf = 0xc0; break;
1150 case 192000: i2s_sf = 0xe0; break;
1151 default:
1152 return -EINVAL;
1153 }
1154
1155 /* Set sampling frequency for I2S audio to 48 kHz */
1156 adv7511_wr_and_or(sd, 0x15, 0xf, i2s_sf);
1157
1158 return 0;
1159}
1160
1161static int adv7511_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
1162{
1163 /* Only 2 channels in use for application */
1164 adv7511_wr_and_or(sd, 0x73, 0xf8, 0x1);
1165 /* Speaker mapping */
1166 adv7511_wr(sd, 0x76, 0x00);
1167
1168 /* 16 bit audio word length */
1169 adv7511_wr_and_or(sd, 0x14, 0xf0, 0x02);
1170
1171 return 0;
1172}
1173
1174static const struct v4l2_subdev_audio_ops adv7511_audio_ops = {
1175 .s_stream = adv7511_s_audio_stream,
1176 .s_clock_freq = adv7511_s_clock_freq,
1177 .s_i2s_clock_freq = adv7511_s_i2s_clock_freq,
1178 .s_routing = adv7511_s_routing,
1179};
1180
9646171f
LP		 1181/* ---------------------------- PAD OPS ------------------------------------- */
1182
1183static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1184{
1185 struct adv7511_state *state = get_adv7511_state(sd);
1186
c81285ae
HV		 1187 memset(edid->reserved, 0, sizeof(edid->reserved));
1188
9646171f
LP		 1189 if (edid->pad != 0)
1190 return -EINVAL;
c81285ae
HV		 1191
1192 if (edid->start_block == 0 && edid->blocks == 0) {
1193 edid->blocks = state->edid.segments * 2;
1194 return 0;
9646171f 1195 }
c81285ae
HV		 1196
1197 if (state->edid.segments == 0)
1198 return -ENODATA;
1199
9646171f 1200 if (edid->start_block >= state->edid.segments * 2)
c81285ae
HV		 1201 return -EINVAL;
1202
1203 if (edid->start_block + edid->blocks > state->edid.segments * 2)
9646171f
LP		 1204 edid->blocks = state->edid.segments * 2 - edid->start_block;
1205
1206 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
1207 128 * edid->blocks);
c81285ae 1208
9646171f
LP		 1209 return 0;
1210}
1211
1fb69bfd 1212static int adv7511_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1213 struct v4l2_subdev_pad_config *cfg,
1fb69bfd
HV		 1214 struct v4l2_subdev_mbus_code_enum *code)
1215{
1216 if (code->pad != 0)
1217 return -EINVAL;
1218
1219 switch (code->index) {
1220 case 0:
1221 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1222 break;
1223 case 1:
1224 code->code = MEDIA_BUS_FMT_YUYV8_1X16;
1225 break;
1226 case 2:
1227 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232 return 0;
1233}
1234
1235static void adv7511_fill_format(struct adv7511_state *state,
1236 struct v4l2_mbus_framefmt *format)
1237{
1238 memset(format, 0, sizeof(*format));
1239
1240 format->width = state->dv_timings.bt.width;
1241 format->height = state->dv_timings.bt.height;
1242 format->field = V4L2_FIELD_NONE;
1243}
1244
f7234138
HV		 1245static int adv7511_get_fmt(struct v4l2_subdev *sd,
1246 struct v4l2_subdev_pad_config *cfg,
1247 struct v4l2_subdev_format *format)
1fb69bfd
HV		 1248{
1249 struct adv7511_state *state = get_adv7511_state(sd);
1250
1251 if (format->pad != 0)
1252 return -EINVAL;
1253
1254 adv7511_fill_format(state, &format->format);
1255
1256 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1257 struct v4l2_mbus_framefmt *fmt;
1258
f7234138 1259 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1fb69bfd
HV		 1260 format->format.code = fmt->code;
1261 format->format.colorspace = fmt->colorspace;
1262 format->format.ycbcr_enc = fmt->ycbcr_enc;
1263 format->format.quantization = fmt->quantization;
e719a51a 1264 format->format.xfer_func = fmt->xfer_func;
1fb69bfd
HV		 1265 } else {
1266 format->format.code = state->fmt_code;
1267 format->format.colorspace = state->colorspace;
1268 format->format.ycbcr_enc = state->ycbcr_enc;
1269 format->format.quantization = state->quantization;
e719a51a 1270 format->format.xfer_func = state->xfer_func;
1fb69bfd
HV		 1271 }
1272
1273 return 0;
1274}
1275
f7234138
HV		 1276static int adv7511_set_fmt(struct v4l2_subdev *sd,
1277 struct v4l2_subdev_pad_config *cfg,
1278 struct v4l2_subdev_format *format)
1fb69bfd
HV		 1279{
1280 struct adv7511_state *state = get_adv7511_state(sd);
1281 /*
1282 * Bitfield namings come the CEA-861-F standard, table 8 "Auxiliary
1283 * Video Information (AVI) InfoFrame Format"
1284 *
1285 * c = Colorimetry
1286 * ec = Extended Colorimetry
1287 * y = RGB or YCbCr
1288 * q = RGB Quantization Range
1289 * yq = YCC Quantization Range
1290 */
1291 u8 c = HDMI_COLORIMETRY_NONE;
1292 u8 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1293 u8 y = HDMI_COLORSPACE_RGB;
1294 u8 q = HDMI_QUANTIZATION_RANGE_DEFAULT;
1295 u8 yq = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
df0e5775
HV		 1296 u8 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1297 u8 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
1fb69bfd
HV		 1298
1299 if (format->pad != 0)
1300 return -EINVAL;
1301 switch (format->format.code) {
1302 case MEDIA_BUS_FMT_UYVY8_1X16:
1303 case MEDIA_BUS_FMT_YUYV8_1X16:
1304 case MEDIA_BUS_FMT_RGB888_1X24:
1305 break;
1306 default:
1307 return -EINVAL;
1308 }
1309
1310 adv7511_fill_format(state, &format->format);
1311 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1312 struct v4l2_mbus_framefmt *fmt;
1313
f7234138 1314 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1fb69bfd
HV		 1315 fmt->code = format->format.code;
1316 fmt->colorspace = format->format.colorspace;
1317 fmt->ycbcr_enc = format->format.ycbcr_enc;
1318 fmt->quantization = format->format.quantization;
e719a51a 1319 fmt->xfer_func = format->format.xfer_func;
1fb69bfd
HV		 1320 return 0;
1321 }
1322
1323 switch (format->format.code) {
1324 case MEDIA_BUS_FMT_UYVY8_1X16:
1325 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1326 adv7511_wr_and_or(sd, 0x16, 0x03, 0xb8);
1327 y = HDMI_COLORSPACE_YUV422;
1328 break;
1329 case MEDIA_BUS_FMT_YUYV8_1X16:
1330 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1331 adv7511_wr_and_or(sd, 0x16, 0x03, 0xbc);
1332 y = HDMI_COLORSPACE_YUV422;
1333 break;
1334 case MEDIA_BUS_FMT_RGB888_1X24:
1335 default:
1336 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x00);
1337 adv7511_wr_and_or(sd, 0x16, 0x03, 0x00);
1338 break;
1339 }
1340 state->fmt_code = format->format.code;
1341 state->colorspace = format->format.colorspace;
1342 state->ycbcr_enc = format->format.ycbcr_enc;
1343 state->quantization = format->format.quantization;
e719a51a 1344 state->xfer_func = format->format.xfer_func;
1fb69bfd
HV		 1345
1346 switch (format->format.colorspace) {
1347 case V4L2_COLORSPACE_ADOBERGB:
1348 c = HDMI_COLORIMETRY_EXTENDED;
1349 ec = y ? HDMI_EXTENDED_COLORIMETRY_ADOBE_YCC_601 :
1350 HDMI_EXTENDED_COLORIMETRY_ADOBE_RGB;
1351 break;
1352 case V4L2_COLORSPACE_SMPTE170M:
1353 c = y ? HDMI_COLORIMETRY_ITU_601 : HDMI_COLORIMETRY_NONE;
1354 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV601) {
1355 c = HDMI_COLORIMETRY_EXTENDED;
1356 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1357 }
1358 break;
1359 case V4L2_COLORSPACE_REC709:
1360 c = y ? HDMI_COLORIMETRY_ITU_709 : HDMI_COLORIMETRY_NONE;
1361 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV709) {
1362 c = HDMI_COLORIMETRY_EXTENDED;
1363 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1364 }
1365 break;
1366 case V4L2_COLORSPACE_SRGB:
1367 c = y ? HDMI_COLORIMETRY_EXTENDED : HDMI_COLORIMETRY_NONE;
1368 ec = y ? HDMI_EXTENDED_COLORIMETRY_S_YCC_601 :
1369 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1370 break;
1371 case V4L2_COLORSPACE_BT2020:
1372 c = HDMI_COLORIMETRY_EXTENDED;
1373 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_BT2020_CONST_LUM)
1374 ec = 5; /* Not yet available in hdmi.h */
1375 else
1376 ec = 6; /* Not yet available in hdmi.h */
1377 break;
1378 default:
1379 break;
1380 }
1381
1382 /*
1383 * CEA-861-F says that for RGB formats the YCC range must match the
1384 * RGB range, although sources should ignore the YCC range.
1385 *
1386 * The RGB quantization range shouldn't be non-zero if the EDID doesn't
1387 * have the Q bit set in the Video Capabilities Data Block, however this
1388 * isn't checked at the moment. The assumption is that the application
1389 * knows the EDID and can detect this.
1390 *
1391 * The same is true for the YCC quantization range: non-standard YCC
1392 * quantization ranges should only be sent if the EDID has the YQ bit
1393 * set in the Video Capabilities Data Block.
1394 */
1395 switch (format->format.quantization) {
1396 case V4L2_QUANTIZATION_FULL_RANGE:
1397 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1398 HDMI_QUANTIZATION_RANGE_FULL;
1399 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_FULL;
1400 break;
1401 case V4L2_QUANTIZATION_LIM_RANGE:
1402 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1403 HDMI_QUANTIZATION_RANGE_LIMITED;
1404 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1405 break;
1406 }
1407
1408 adv7511_wr_and_or(sd, 0x4a, 0xbf, 0);
1409 adv7511_wr_and_or(sd, 0x55, 0x9f, y << 5);
1410 adv7511_wr_and_or(sd, 0x56, 0x3f, c << 6);
df0e5775
HV		 1411 adv7511_wr_and_or(sd, 0x57, 0x83, (ec << 4) | (q << 2) | (itc << 7));
1412 adv7511_wr_and_or(sd, 0x59, 0x0f, (yq << 6) | (cn << 4));
1fb69bfd
HV		 1413 adv7511_wr_and_or(sd, 0x4a, 0xff, 1);
1414
1415 return 0;
1416}
1417
9646171f
LP		 1418static const struct v4l2_subdev_pad_ops adv7511_pad_ops = {
1419 .get_edid = adv7511_get_edid,
1fb69bfd
HV		 1420 .enum_mbus_code = adv7511_enum_mbus_code,
1421 .get_fmt = adv7511_get_fmt,
1422 .set_fmt = adv7511_set_fmt,
9646171f
LP		 1423 .enum_dv_timings = adv7511_enum_dv_timings,
1424 .dv_timings_cap = adv7511_dv_timings_cap,
1425};
1426
5a544cce
HV		 1427/* --------------------- SUBDEV OPS --------------------------------------- */
1428
1429static const struct v4l2_subdev_ops adv7511_ops = {
1430 .core = &adv7511_core_ops,
1431 .pad = &adv7511_pad_ops,
1432 .video = &adv7511_video_ops,
1433 .audio = &adv7511_audio_ops,
1434};
1435
1436/* ----------------------------------------------------------------------- */
5be50ef1 1437static void adv7511_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd, int segment, u8 *buf)
5a544cce
HV		 1438{
1439 if (debug >= lvl) {
1440 int i, j;
1441 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
1442 for (i = 0; i < 256; i += 16) {
1443 u8 b[128];
1444 u8 *bp = b;
1445 if (i == 128)
1446 v4l2_dbg(lvl, debug, sd, "\n");
1447 for (j = i; j < i + 16; j++) {
1448 sprintf(bp, "0x%02x, ", buf[j]);
1449 bp += 6;
1450 }
1451 bp[0] = '\0';
1452 v4l2_dbg(lvl, debug, sd, "%s\n", b);
1453 }
1454 }
1455}
1456
b339a72e
HV		 1457static void adv7511_notify_no_edid(struct v4l2_subdev *sd)
1458{
1459 struct adv7511_state *state = get_adv7511_state(sd);
1460 struct adv7511_edid_detect ed;
1461
1462 /* We failed to read the EDID, so send an event for this. */
1463 ed.present = false;
1464 ed.segment = adv7511_rd(sd, 0xc4);
257d4eae
HV		 1465 ed.phys_addr = CEC_PHYS_ADDR_INVALID;
1466 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
b339a72e
HV		 1467 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1468 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x0);
1469}
1470
5a544cce
HV		 1471static void adv7511_edid_handler(struct work_struct *work)
1472{
1473 struct delayed_work *dwork = to_delayed_work(work);
1474 struct adv7511_state *state = container_of(dwork, struct adv7511_state, edid_handler);
1475 struct v4l2_subdev *sd = &state->sd;
5a544cce
HV		 1476
1477 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1478
1479 if (adv7511_check_edid_status(sd)) {
1480 /* Return if we received the EDID. */
1481 return;
1482 }
1483
1484 if (adv7511_have_hotplug(sd)) {
1485 /* We must retry reading the EDID several times, it is possible
1486 * that initially the EDID couldn't be read due to i2c errors
1487 * (DVI connectors are particularly prone to this problem). */
1488 if (state->edid.read_retries) {
1489 state->edid.read_retries--;
1490 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
1491 state->have_monitor = false;
1492 adv7511_s_power(sd, false);
1493 adv7511_s_power(sd, true);
1494 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1495 return;
1496 }
1497 }
1498
1499 /* We failed to read the EDID, so send an event for this. */
b339a72e 1500 adv7511_notify_no_edid(sd);
5a544cce
HV		 1501 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
1502}
1503
1504static void adv7511_audio_setup(struct v4l2_subdev *sd)
1505{
1506 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1507
1508 adv7511_s_i2s_clock_freq(sd, 48000);
1509 adv7511_s_clock_freq(sd, 48000);
1510 adv7511_s_routing(sd, 0, 0, 0);
1511}
1512
1513/* Configure hdmi transmitter. */
1514static void adv7511_setup(struct v4l2_subdev *sd)
1515{
1516 struct adv7511_state *state = get_adv7511_state(sd);
1517 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1518
1519 /* Input format: RGB 4:4:4 */
1520 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x0);
1521 /* Output format: RGB 4:4:4 */
1522 adv7511_wr_and_or(sd, 0x16, 0x7f, 0x0);
1523 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion, Aspect ratio: 16:9 */
1524 adv7511_wr_and_or(sd, 0x17, 0xf9, 0x06);
1525 /* Disable pixel repetition */
1526 adv7511_wr_and_or(sd, 0x3b, 0x9f, 0x0);
1527 /* Disable CSC */
1528 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
1529 /* Output format: RGB 4:4:4, Active Format Information is valid,
1530 * underscanned */
1531 adv7511_wr_and_or(sd, 0x55, 0x9c, 0x12);
1532 /* AVI Info frame packet enable, Audio Info frame disable */
1533 adv7511_wr_and_or(sd, 0x44, 0xe7, 0x10);
1534 /* Colorimetry, Active format aspect ratio: same as picure. */
1535 adv7511_wr(sd, 0x56, 0xa8);
1536 /* No encryption */
1537 adv7511_wr_and_or(sd, 0xaf, 0xed, 0x0);
1538
1539 /* Positive clk edge capture for input video clock */
1540 adv7511_wr_and_or(sd, 0xba, 0x1f, 0x60);
1541
1542 adv7511_audio_setup(sd);
1543
1544 v4l2_ctrl_handler_setup(&state->hdl);
1545}
1546
1547static void adv7511_notify_monitor_detect(struct v4l2_subdev *sd)
1548{
1549 struct adv7511_monitor_detect mdt;
1550 struct adv7511_state *state = get_adv7511_state(sd);
1551
1552 mdt.present = state->have_monitor;
1553 v4l2_subdev_notify(sd, ADV7511_MONITOR_DETECT, (void *)&mdt);
1554}
1555
1556static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd)
1557{
1558 struct adv7511_state *state = get_adv7511_state(sd);
1559 /* read hotplug and rx-sense state */
5be50ef1 1560 u8 status = adv7511_rd(sd, 0x42);
5a544cce
HV		 1561
1562 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1563 __func__,
1564 status,
1565 status & MASK_ADV7511_HPD_DETECT ? ", hotplug" : "",
1566 status & MASK_ADV7511_MSEN_DETECT ? ", rx-sense" : "");
1567
1568 /* update read only ctrls */
1569 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, adv7511_have_hotplug(sd) ? 0x1 : 0x0);
1570 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, adv7511_have_rx_sense(sd) ? 0x1 : 0x0);
5a544cce
HV		 1571
1572 if ((status & MASK_ADV7511_HPD_DETECT) && ((status & MASK_ADV7511_MSEN_DETECT) || state->edid.segments)) {
1573 v4l2_dbg(1, debug, sd, "%s: hotplug and (rx-sense or edid)\n", __func__);
1574 if (!state->have_monitor) {
1575 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1576 state->have_monitor = true;
1577 adv7511_set_isr(sd, true);
1578 if (!adv7511_s_power(sd, true)) {
1579 v4l2_dbg(1, debug, sd, "%s: monitor detected, powerup failed\n", __func__);
1580 return;
1581 }
1582 adv7511_setup(sd);
1583 adv7511_notify_monitor_detect(sd);
1584 state->edid.read_retries = EDID_MAX_RETRIES;
1585 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1586 }
1587 } else if (status & MASK_ADV7511_HPD_DETECT) {
1588 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1589 state->edid.read_retries = EDID_MAX_RETRIES;
1590 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1591 } else if (!(status & MASK_ADV7511_HPD_DETECT)) {
1592 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1593 if (state->have_monitor) {
1594 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1595 state->have_monitor = false;
1596 adv7511_notify_monitor_detect(sd);
1597 }
1598 adv7511_s_power(sd, false);
1599 memset(&state->edid, 0, sizeof(struct adv7511_state_edid));
b339a72e 1600 adv7511_notify_no_edid(sd);
5a544cce
HV		 1601 }
1602}
1603
5be50ef1 1604static bool edid_block_verify_crc(u8 *edid_block)
5a544cce 1605{
5be50ef1 1606 u8 sum = 0;
928b0fe7 1607 int i;
5a544cce
HV		 1608
1609 for (i = 0; i < 128; i++)
928b0fe7
MB		 1610 sum += edid_block[i];
1611 return sum == 0;
5a544cce
HV		 1612}
1613
928b0fe7 1614static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
5a544cce
HV		 1615{
1616 struct adv7511_state *state = get_adv7511_state(sd);
1617 u32 blocks = state->edid.blocks;
5be50ef1 1618 u8 *data = state->edid.data;
5a544cce 1619
928b0fe7
MB		 1620 if (!edid_block_verify_crc(&data[segment * 256]))
1621 return false;
1622 if ((segment + 1) * 2 <= blocks)
1623 return edid_block_verify_crc(&data[segment * 256 + 128]);
1624 return true;
1625}
1626
1627static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1628{
1629 static const u8 hdmi_header[] = {
1630 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1631 };
1632 struct adv7511_state *state = get_adv7511_state(sd);
1633 u8 *data = state->edid.data;
1634
1635 if (segment != 0)
5a544cce 1636 return true;
928b0fe7 1637 return !memcmp(data, hdmi_header, sizeof(hdmi_header));
5a544cce
HV		 1638}
1639
1640static bool adv7511_check_edid_status(struct v4l2_subdev *sd)
1641{
1642 struct adv7511_state *state = get_adv7511_state(sd);
5be50ef1 1643 u8 edidRdy = adv7511_rd(sd, 0xc5);
5a544cce
HV		 1644
1645 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1646 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1647
1648 if (state->edid.complete)
1649 return true;
1650
1651 if (edidRdy & MASK_ADV7511_EDID_RDY) {
1652 int segment = adv7511_rd(sd, 0xc4);
1653 struct adv7511_edid_detect ed;
1654
1655 if (segment >= EDID_MAX_SEGM) {
1656 v4l2_err(sd, "edid segment number too big\n");
1657 return false;
1658 }
1659 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1660 adv7511_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1661 adv7511_dbg_dump_edid(2, debug, sd, segment, &state->edid.data[segment * 256]);
1662 if (segment == 0) {
1663 state->edid.blocks = state->edid.data[0x7e] + 1;
1664 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n", __func__, state->edid.blocks);
1665 }
928b0fe7
MB		 1666 if (!edid_verify_crc(sd, segment) ||
1667 !edid_verify_header(sd, segment)) {
5a544cce 1668 /* edid crc error, force reread of edid segment */
928b0fe7 1669 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
5a544cce
HV		 1670 state->have_monitor = false;
1671 adv7511_s_power(sd, false);
1672 adv7511_s_power(sd, true);
1673 return false;
1674 }
1675 /* one more segment read ok */
1676 state->edid.segments = segment + 1;
b339a72e 1677 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x1);
5a544cce
HV		 1678 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1679 /* Request next EDID segment */
1680 v4l2_dbg(1, debug, sd, "%s: request segment %d\n", __func__, state->edid.segments);
1681 adv7511_wr(sd, 0xc9, 0xf);
1682 adv7511_wr(sd, 0xc4, state->edid.segments);
1683 state->edid.read_retries = EDID_MAX_RETRIES;
1684 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1685 return false;
1686 }
1687
1688 v4l2_dbg(1, debug, sd, "%s: edid complete with %d segment(s)\n", __func__, state->edid.segments);
1689 state->edid.complete = true;
257d4eae
HV		 1690 ed.phys_addr = cec_get_edid_phys_addr(state->edid.data,
1691 state->edid.segments * 256,
1692 NULL);
5a544cce
HV		 1693 /* report when we have all segments
1694 but report only for segment 0
1695 */
1696 ed.present = true;
1697 ed.segment = 0;
1698 state->edid_detect_counter++;
257d4eae 1699 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
5a544cce
HV		 1700 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1701 return ed.present;
1702 }
1703
1704 return false;
1705}
1706
257d4eae
HV		 1707static int adv7511_registered(struct v4l2_subdev *sd)
1708{
1709 struct adv7511_state *state = get_adv7511_state(sd);
1710 int err;
1711
1712 err = cec_register_adapter(state->cec_adap);
1713 if (err)
1714 cec_delete_adapter(state->cec_adap);
1715 return err;
1716}
1717
1718static void adv7511_unregistered(struct v4l2_subdev *sd)
1719{
1720 struct adv7511_state *state = get_adv7511_state(sd);
1721
1722 cec_unregister_adapter(state->cec_adap);
1723}
1724
1725static const struct v4l2_subdev_internal_ops adv7511_int_ops = {
1726 .registered = adv7511_registered,
1727 .unregistered = adv7511_unregistered,
1728};
1729
5a544cce
HV		 1730/* ----------------------------------------------------------------------- */
1731/* Setup ADV7511 */
1732static void adv7511_init_setup(struct v4l2_subdev *sd)
1733{
1734 struct adv7511_state *state = get_adv7511_state(sd);
1735 struct adv7511_state_edid *edid = &state->edid;
257d4eae
HV		 1736 u32 cec_clk = state->pdata.cec_clk;
1737 u8 ratio;
5a544cce
HV		 1738
1739 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1740
1741 /* clear all interrupts */
1742 adv7511_wr(sd, 0x96, 0xff);
257d4eae 1743 adv7511_wr(sd, 0x97, 0xff);
a62c6216
MB		 1744 /*
1745 * Stop HPD from resetting a lot of registers.
1746 * It might leave the chip in a partly un-initialized state,
1747 * in particular with regards to hotplug bounces.
1748 */
1749 adv7511_wr_and_or(sd, 0xd6, 0x3f, 0xc0);
5a544cce
HV		 1750 memset(edid, 0, sizeof(struct adv7511_state_edid));
1751 state->have_monitor = false;
1752 adv7511_set_isr(sd, false);
1753 adv7511_s_stream(sd, false);
1754 adv7511_s_audio_stream(sd, false);
257d4eae
HV		 1755
1756 if (state->i2c_cec == NULL)
1757 return;
1758
1759 v4l2_dbg(1, debug, sd, "%s: cec_clk %d\n", __func__, cec_clk);
1760
1761 /* cec soft reset */
1762 adv7511_cec_write(sd, 0x50, 0x01);
1763 adv7511_cec_write(sd, 0x50, 0x00);
1764
1765 /* legacy mode */
1766 adv7511_cec_write(sd, 0x4a, 0x00);
1767
1768 if (cec_clk % 750000 != 0)
1769 v4l2_err(sd, "%s: cec_clk %d, not multiple of 750 Khz\n",
1770 __func__, cec_clk);
1771
1772 ratio = (cec_clk / 750000) - 1;
1773 adv7511_cec_write(sd, 0x4e, ratio << 2);
5a544cce
HV		 1774}
1775
1776static int adv7511_probe(struct i2c_client *client, const struct i2c_device_id *id)
1777{
1778 struct adv7511_state *state;
1779 struct adv7511_platform_data *pdata = client->dev.platform_data;
1780 struct v4l2_ctrl_handler *hdl;
1781 struct v4l2_subdev *sd;
1782 u8 chip_id[2];
1783 int err = -EIO;
1784
1785 /* Check if the adapter supports the needed features */
1786 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1787 return -EIO;
1788
1789 state = devm_kzalloc(&client->dev, sizeof(struct adv7511_state), GFP_KERNEL);
1790 if (!state)
1791 return -ENOMEM;
1792
1793 /* Platform data */
1794 if (!pdata) {
1795 v4l_err(client, "No platform data!\n");
1796 return -ENODEV;
1797 }
1798 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1fb69bfd
HV		 1799 state->fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1800 state->colorspace = V4L2_COLORSPACE_SRGB;
5a544cce
HV		 1801
1802 sd = &state->sd;
1803
1804 v4l2_dbg(1, debug, sd, "detecting adv7511 client on address 0x%x\n",
1805 client->addr << 1);
1806
1807 v4l2_i2c_subdev_init(sd, client, &adv7511_ops);
257d4eae 1808 sd->internal_ops = &adv7511_int_ops;
5a544cce
HV		 1809
1810 hdl = &state->hdl;
1811 v4l2_ctrl_handler_init(hdl, 10);
1812 /* add in ascending ID order */
1813 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1814 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1815 0, V4L2_DV_TX_MODE_DVI_D);
1816 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1817 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1818 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1819 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1820 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1821 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1822 state->rgb_quantization_range_ctrl =
1823 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1824 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1825 0, V4L2_DV_RGB_RANGE_AUTO);
df0e5775
HV		 1826 state->content_type_ctrl =
1827 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1828 V4L2_CID_DV_TX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
1829 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
5a544cce
HV		 1830 sd->ctrl_handler = hdl;
1831 if (hdl->error) {
1832 err = hdl->error;
1833 goto err_hdl;
1834 }
5a544cce 1835 state->pad.flags = MEDIA_PAD_FL_SINK;
ab22e77c 1836 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
5a544cce
HV		 1837 if (err)
1838 goto err_hdl;
1839
1840 /* EDID and CEC i2c addr */
1841 state->i2c_edid_addr = state->pdata.i2c_edid << 1;
1842 state->i2c_cec_addr = state->pdata.i2c_cec << 1;
b4dbad8f 1843 state->i2c_pktmem_addr = state->pdata.i2c_pktmem << 1;
5a544cce
HV		 1844
1845 state->chip_revision = adv7511_rd(sd, 0x0);
1846 chip_id[0] = adv7511_rd(sd, 0xf5);
1847 chip_id[1] = adv7511_rd(sd, 0xf6);
1848 if (chip_id[0] != 0x75 || chip_id[1] != 0x11) {
257d4eae
HV		 1849 v4l2_err(sd, "chip_id != 0x7511, read 0x%02x%02x\n", chip_id[0],
1850 chip_id[1]);
5a544cce
HV		 1851 err = -EIO;
1852 goto err_entity;
1853 }
1854
257d4eae
HV		 1855 state->i2c_edid = i2c_new_dummy(client->adapter,
1856 state->i2c_edid_addr >> 1);
5a544cce
HV		 1857 if (state->i2c_edid == NULL) {
1858 v4l2_err(sd, "failed to register edid i2c client\n");
f527b17a 1859 err = -ENOMEM;
5a544cce
HV		 1860 goto err_entity;
1861 }
1862
257d4eae
HV		 1863 adv7511_wr(sd, 0xe1, state->i2c_cec_addr);
1864 if (state->pdata.cec_clk < 3000000 ||
1865 state->pdata.cec_clk > 100000000) {
1866 v4l2_err(sd, "%s: cec_clk %u outside range, disabling cec\n",
1867 __func__, state->pdata.cec_clk);
1868 state->pdata.cec_clk = 0;
1869 }
1870
1871 if (state->pdata.cec_clk) {
1872 state->i2c_cec = i2c_new_dummy(client->adapter,
1873 state->i2c_cec_addr >> 1);
1874 if (state->i2c_cec == NULL) {
1875 v4l2_err(sd, "failed to register cec i2c client\n");
1876 goto err_unreg_edid;
1877 }
1878 adv7511_wr(sd, 0xe2, 0x00); /* power up cec section */
1879 } else {
1880 adv7511_wr(sd, 0xe2, 0x01); /* power down cec section */
1881 }
1882
b4dbad8f
HV		 1883 state->i2c_pktmem = i2c_new_dummy(client->adapter, state->i2c_pktmem_addr >> 1);
1884 if (state->i2c_pktmem == NULL) {
1885 v4l2_err(sd, "failed to register pktmem i2c client\n");
1886 err = -ENOMEM;
257d4eae 1887 goto err_unreg_cec;
b4dbad8f
HV		 1888 }
1889
5a544cce
HV		 1890 state->work_queue = create_singlethread_workqueue(sd->name);
1891 if (state->work_queue == NULL) {
1892 v4l2_err(sd, "could not create workqueue\n");
f527b17a 1893 err = -ENOMEM;
b4dbad8f 1894 goto err_unreg_pktmem;
5a544cce
HV		 1895 }
1896
1897 INIT_DELAYED_WORK(&state->edid_handler, adv7511_edid_handler);
1898
1899 adv7511_init_setup(sd);
257d4eae
HV		 1900
1901#if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
1902 state->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
1903 state, dev_name(&client->dev), CEC_CAP_TRANSMIT |
1904 CEC_CAP_LOG_ADDRS | CEC_CAP_PASSTHROUGH | CEC_CAP_RC,
1905 ADV7511_MAX_ADDRS, &client->dev);
1906 err = PTR_ERR_OR_ZERO(state->cec_adap);
1907 if (err) {
1908 destroy_workqueue(state->work_queue);
1909 goto err_unreg_pktmem;
1910 }
1911#endif
1912
5a544cce
HV		 1913 adv7511_set_isr(sd, true);
1914 adv7511_check_monitor_present_status(sd);
1915
1916 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1917 client->addr << 1, client->adapter->name);
1918 return 0;
1919
b4dbad8f
HV		 1920err_unreg_pktmem:
1921 i2c_unregister_device(state->i2c_pktmem);
257d4eae
HV		 1922err_unreg_cec:
1923 if (state->i2c_cec)
1924 i2c_unregister_device(state->i2c_cec);
b4dbad8f 1925err_unreg_edid:
5a544cce
HV		 1926 i2c_unregister_device(state->i2c_edid);
1927err_entity:
1928 media_entity_cleanup(&sd->entity);
1929err_hdl:
1930 v4l2_ctrl_handler_free(&state->hdl);
1931 return err;
1932}
1933
1934/* ----------------------------------------------------------------------- */
1935
1936static int adv7511_remove(struct i2c_client *client)
1937{
1938 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1939 struct adv7511_state *state = get_adv7511_state(sd);
1940
1941 state->chip_revision = -1;
1942
1943 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1944 client->addr << 1, client->adapter->name);
1945
257d4eae 1946 adv7511_set_isr(sd, false);
5a544cce
HV		 1947 adv7511_init_setup(sd);
1948 cancel_delayed_work(&state->edid_handler);
1949 i2c_unregister_device(state->i2c_edid);
257d4eae
HV		 1950 if (state->i2c_cec)
1951 i2c_unregister_device(state->i2c_cec);
b4dbad8f 1952 i2c_unregister_device(state->i2c_pktmem);
5a544cce
HV		 1953 destroy_workqueue(state->work_queue);
1954 v4l2_device_unregister_subdev(sd);
1955 media_entity_cleanup(&sd->entity);
1956 v4l2_ctrl_handler_free(sd->ctrl_handler);
1957 return 0;
1958}
1959
1960/* ----------------------------------------------------------------------- */
1961
1962static struct i2c_device_id adv7511_id[] = {
1963 { "adv7511", 0 },
1964 { }
1965};
1966MODULE_DEVICE_TABLE(i2c, adv7511_id);
1967
1968static struct i2c_driver adv7511_driver = {
1969 .driver = {
5a544cce
HV		 1970 .name = "adv7511",
1971 },
1972 .probe = adv7511_probe,
1973 .remove = adv7511_remove,
1974 .id_table = adv7511_id,
1975};
1976
1977module_i2c_driver(adv7511_driver);
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