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[media] v4l2-subdev: allow subdev to send an event to the v4l2_device notify function
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
c72a53ce 32#include <linux/i2c.h>
54450f59
HV		 33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
c72a53ce 36#include <linux/v4l2-dv-timings.h>
54450f59
HV		 37#include <linux/videodev2.h>
38#include <linux/workqueue.h>
c72a53ce
LP		 39
40#include <media/adv7604.h>
54450f59 41#include <media/v4l2-ctrls.h>
c72a53ce 42#include <media/v4l2-device.h>
25764158 43#include <media/v4l2-dv-timings.h>
6fa88045 44#include <media/v4l2-of.h>
54450f59
HV		 45
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7604 system clock frequency */
b44b2e06 56#define ADV76XX_FSC (28636360)
54450f59 57
b44b2e06 58#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 59
b44b2e06 60#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 62#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 63
b44b2e06 64#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 66#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 68#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70
b44b2e06
PA		 71#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
72#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
73#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
74#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
75#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
76#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 77
b44b2e06 78#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 79
b44b2e06 80enum adv76xx_type {
d42010a1
LPC		 81 ADV7604,
82 ADV7611,
83};
84
b44b2e06 85struct adv76xx_reg_seq {
d42010a1
LPC		 86 unsigned int reg;
87 u8 val;
88};
89
b44b2e06 90struct adv76xx_format_info {
f5fe58fd 91 u32 code;
539b33b0
LP		 92 u8 op_ch_sel;
93 bool rgb_out;
94 bool swap_cb_cr;
95 u8 op_format_sel;
96};
97
b44b2e06
PA		 98struct adv76xx_chip_info {
99 enum adv76xx_type type;
d42010a1
LPC		 100
101 bool has_afe;
102 unsigned int max_port;
103 unsigned int num_dv_ports;
104
105 unsigned int edid_enable_reg;
106 unsigned int edid_status_reg;
107 unsigned int lcf_reg;
108
109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask;
80f4944e 112 unsigned int cp_csc;
d42010a1 113
b44b2e06 114 const struct adv76xx_format_info *formats;
539b33b0
LP		 115 unsigned int nformats;
116
d42010a1
LPC		 117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
118 void (*setup_irqs)(struct v4l2_subdev *sd);
119 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
121
122 /* 0 = AFE, 1 = HDMI */
b44b2e06 123 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 124 unsigned int num_recommended_settings[2];
125
126 unsigned long page_mask;
5380baaf 127
128 /* Masks for timings */
129 unsigned int linewidth_mask;
130 unsigned int field0_height_mask;
131 unsigned int field1_height_mask;
132 unsigned int hfrontporch_mask;
133 unsigned int hsync_mask;
134 unsigned int hbackporch_mask;
135 unsigned int field0_vfrontporch_mask;
136 unsigned int field1_vfrontporch_mask;
137 unsigned int field0_vsync_mask;
138 unsigned int field1_vsync_mask;
139 unsigned int field0_vbackporch_mask;
140 unsigned int field1_vbackporch_mask;
d42010a1
LPC		 141};
142
54450f59
HV		 143/*
144 **********************************************************************
145 *
146 * Arrays with configuration parameters for the ADV7604
147 *
148 **********************************************************************
149 */
c784b1e2 150
b44b2e06
PA		 151struct adv76xx_state {
152 const struct adv76xx_chip_info *info;
153 struct adv76xx_platform_data pdata;
539b33b0 154
e9d50e9e
LP		 155 struct gpio_desc *hpd_gpio[4];
156
54450f59 157 struct v4l2_subdev sd;
b44b2e06 158 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 159 unsigned int source_pad;
539b33b0 160
54450f59 161 struct v4l2_ctrl_handler hdl;
539b33b0 162
b44b2e06 163 enum adv76xx_pad selected_input;
539b33b0 164
54450f59 165 struct v4l2_dv_timings timings;
b44b2e06 166 const struct adv76xx_format_info *format;
539b33b0 167
4a31a93a
MR		 168 struct {
169 u8 edid[256];
170 u32 present;
171 unsigned blocks;
172 } edid;
dd08beb9 173 u16 spa_port_a[2];
54450f59
HV		 174 struct v4l2_fract aspect_ratio;
175 u32 rgb_quantization_range;
176 struct workqueue_struct *work_queues;
177 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 178 bool restart_stdi_once;
54450f59
HV		 179
180 /* i2c clients */
b44b2e06 181 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59
HV		 182
183 /* controls */
184 struct v4l2_ctrl *detect_tx_5v_ctrl;
185 struct v4l2_ctrl *analog_sampling_phase_ctrl;
186 struct v4l2_ctrl *free_run_color_manual_ctrl;
187 struct v4l2_ctrl *free_run_color_ctrl;
188 struct v4l2_ctrl *rgb_quantization_range_ctrl;
189};
190
b44b2e06 191static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 192{
193 return state->info->has_afe;
194}
195
54450f59 196/* Supported CEA and DMT timings */
b44b2e06 197static const struct v4l2_dv_timings adv76xx_timings[] = {
54450f59
HV		 198 V4L2_DV_BT_CEA_720X480P59_94,
199 V4L2_DV_BT_CEA_720X576P50,
200 V4L2_DV_BT_CEA_1280X720P24,
201 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 202 V4L2_DV_BT_CEA_1280X720P50,
203 V4L2_DV_BT_CEA_1280X720P60,
204 V4L2_DV_BT_CEA_1920X1080P24,
205 V4L2_DV_BT_CEA_1920X1080P25,
206 V4L2_DV_BT_CEA_1920X1080P30,
207 V4L2_DV_BT_CEA_1920X1080P50,
208 V4L2_DV_BT_CEA_1920X1080P60,
209
ccbd5bc4 210 /* sorted by DMT ID */
54450f59
HV		 211 V4L2_DV_BT_DMT_640X350P85,
212 V4L2_DV_BT_DMT_640X400P85,
213 V4L2_DV_BT_DMT_720X400P85,
214 V4L2_DV_BT_DMT_640X480P60,
215 V4L2_DV_BT_DMT_640X480P72,
216 V4L2_DV_BT_DMT_640X480P75,
217 V4L2_DV_BT_DMT_640X480P85,
218 V4L2_DV_BT_DMT_800X600P56,
219 V4L2_DV_BT_DMT_800X600P60,
220 V4L2_DV_BT_DMT_800X600P72,
221 V4L2_DV_BT_DMT_800X600P75,
222 V4L2_DV_BT_DMT_800X600P85,
223 V4L2_DV_BT_DMT_848X480P60,
224 V4L2_DV_BT_DMT_1024X768P60,
225 V4L2_DV_BT_DMT_1024X768P70,
226 V4L2_DV_BT_DMT_1024X768P75,
227 V4L2_DV_BT_DMT_1024X768P85,
228 V4L2_DV_BT_DMT_1152X864P75,
229 V4L2_DV_BT_DMT_1280X768P60_RB,
230 V4L2_DV_BT_DMT_1280X768P60,
231 V4L2_DV_BT_DMT_1280X768P75,
232 V4L2_DV_BT_DMT_1280X768P85,
233 V4L2_DV_BT_DMT_1280X800P60_RB,
234 V4L2_DV_BT_DMT_1280X800P60,
235 V4L2_DV_BT_DMT_1280X800P75,
236 V4L2_DV_BT_DMT_1280X800P85,
237 V4L2_DV_BT_DMT_1280X960P60,
238 V4L2_DV_BT_DMT_1280X960P85,
239 V4L2_DV_BT_DMT_1280X1024P60,
240 V4L2_DV_BT_DMT_1280X1024P75,
241 V4L2_DV_BT_DMT_1280X1024P85,
242 V4L2_DV_BT_DMT_1360X768P60,
243 V4L2_DV_BT_DMT_1400X1050P60_RB,
244 V4L2_DV_BT_DMT_1400X1050P60,
245 V4L2_DV_BT_DMT_1400X1050P75,
246 V4L2_DV_BT_DMT_1400X1050P85,
247 V4L2_DV_BT_DMT_1440X900P60_RB,
248 V4L2_DV_BT_DMT_1440X900P60,
249 V4L2_DV_BT_DMT_1600X1200P60,
250 V4L2_DV_BT_DMT_1680X1050P60_RB,
251 V4L2_DV_BT_DMT_1680X1050P60,
252 V4L2_DV_BT_DMT_1792X1344P60,
253 V4L2_DV_BT_DMT_1856X1392P60,
254 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 255 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 256 V4L2_DV_BT_DMT_1366X768P60,
257 V4L2_DV_BT_DMT_1920X1080P60,
258 { },
259};
260
b44b2e06 261struct adv76xx_video_standards {
ccbd5bc4
HV		 262 struct v4l2_dv_timings timings;
263 u8 vid_std;
264 u8 v_freq;
265};
266
267/* sorted by number of lines */
b44b2e06 268static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 269 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
270 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
271 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
272 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
273 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
274 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
275 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
276 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
277 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
278 /* TODO add 1920x1080P60_RB (CVT timing) */
279 { },
280};
281
282/* sorted by number of lines */
b44b2e06 283static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 284 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
285 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
286 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
287 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
288 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
289 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
290 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
291 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
292 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
293 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
294 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
295 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
296 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
297 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
298 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
299 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
300 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
301 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
302 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
303 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
304 /* TODO add 1600X1200P60_RB (not a DMT timing) */
305 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
306 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
307 { },
308};
309
310/* sorted by number of lines */
b44b2e06 311static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 312 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
313 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
314 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
315 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
316 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
317 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
318 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
319 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
320 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
321 { },
322};
323
324/* sorted by number of lines */
b44b2e06 325static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 326 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
327 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
328 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
329 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
330 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
331 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
332 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
333 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
334 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
335 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
336 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
337 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
338 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
339 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
340 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
341 { },
342};
343
54450f59
HV		 344/* ----------------------------------------------------------------------- */
345
b44b2e06 346static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 347{
b44b2e06 348 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 349}
350
54450f59
HV		 351static inline unsigned htotal(const struct v4l2_bt_timings *t)
352{
eacf8f9a 353 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 354}
355
54450f59
HV		 356static inline unsigned vtotal(const struct v4l2_bt_timings *t)
357{
eacf8f9a 358 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 359}
360
361/* ----------------------------------------------------------------------- */
362
363static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
364 u8 command, bool check)
365{
366 union i2c_smbus_data data;
367
368 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
369 I2C_SMBUS_READ, command,
370 I2C_SMBUS_BYTE_DATA, &data))
371 return data.byte;
372 if (check)
373 v4l_err(client, "error reading %02x, %02x\n",
374 client->addr, command);
375 return -EIO;
376}
377
b44b2e06
PA		 378static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
379 enum adv76xx_page page, u8 command)
54450f59 380{
05cacb17
LP		 381 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
382 command, true);
54450f59
HV		 383}
384
b44b2e06
PA		 385static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
386 enum adv76xx_page page, u8 command,
05cacb17 387 u8 value)
54450f59 388{
05cacb17 389 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 390 union i2c_smbus_data data;
391 int err;
392 int i;
393
394 data.byte = value;
395 for (i = 0; i < 3; i++) {
396 err = i2c_smbus_xfer(client->adapter, client->addr,
397 client->flags,
398 I2C_SMBUS_WRITE, command,
399 I2C_SMBUS_BYTE_DATA, &data);
400 if (!err)
401 break;
402 }
403 if (err < 0)
404 v4l_err(client, "error writing %02x, %02x, %02x\n",
405 client->addr, command, value);
406 return err;
407}
408
b44b2e06
PA		 409static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
410 enum adv76xx_page page, u8 command,
05cacb17 411 unsigned length, const u8 *values)
54450f59 412{
05cacb17 413 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 414 union i2c_smbus_data data;
415
416 if (length > I2C_SMBUS_BLOCK_MAX)
417 length = I2C_SMBUS_BLOCK_MAX;
418 data.block[0] = length;
419 memcpy(data.block + 1, values, length);
420 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
421 I2C_SMBUS_WRITE, command,
422 I2C_SMBUS_I2C_BLOCK_DATA, &data);
423}
424
425/* ----------------------------------------------------------------------- */
426
427static inline int io_read(struct v4l2_subdev *sd, u8 reg)
428{
b44b2e06 429 struct adv76xx_state *state = to_state(sd);
54450f59 430
b44b2e06 431 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 432}
433
434static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
435{
b44b2e06 436 struct adv76xx_state *state = to_state(sd);
54450f59 437
b44b2e06 438 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
54450f59
HV		 439}
440
22d97e56 441static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 442{
22d97e56 443 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 444}
445
446static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
447{
b44b2e06 448 struct adv76xx_state *state = to_state(sd);
54450f59 449
05cacb17 450 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 451}
452
453static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
454{
b44b2e06 455 struct adv76xx_state *state = to_state(sd);
54450f59 456
05cacb17 457 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
54450f59
HV		 458}
459
460static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
461{
b44b2e06 462 struct adv76xx_state *state = to_state(sd);
54450f59 463
b44b2e06 464 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 465}
466
467static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468{
b44b2e06 469 struct adv76xx_state *state = to_state(sd);
54450f59 470
b44b2e06 471 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
54450f59
HV		 472}
473
54450f59
HV		 474static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
475{
b44b2e06 476 struct adv76xx_state *state = to_state(sd);
54450f59 477
b44b2e06 478 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 479}
480
481static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
482{
b44b2e06 483 struct adv76xx_state *state = to_state(sd);
54450f59 484
b44b2e06 485 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
05cacb17 486 reg, val);
54450f59
HV		 487}
488
54450f59
HV		 489static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
490{
b44b2e06 491 struct adv76xx_state *state = to_state(sd);
54450f59 492
b44b2e06 493 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 494}
495
496static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497{
b44b2e06 498 struct adv76xx_state *state = to_state(sd);
54450f59 499
b44b2e06 500 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
54450f59
HV		 501}
502
503static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
504{
b44b2e06 505 struct adv76xx_state *state = to_state(sd);
54450f59 506
b44b2e06 507 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 508}
509
510static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
511{
b44b2e06 512 struct adv76xx_state *state = to_state(sd);
54450f59 513
b44b2e06 514 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
54450f59
HV		 515}
516
22d97e56 517static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 518{
22d97e56 519 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 520}
521
522static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
523{
b44b2e06 524 struct adv76xx_state *state = to_state(sd);
54450f59 525
b44b2e06 526 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 527}
528
529static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
530{
b44b2e06 531 struct adv76xx_state *state = to_state(sd);
54450f59 532
b44b2e06 533 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
54450f59
HV		 534}
535
54450f59
HV		 536static inline int edid_write_block(struct v4l2_subdev *sd,
537 unsigned len, const u8 *val)
538{
b44b2e06 539 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 540 int err = 0;
541 int i;
542
543 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
544
54450f59 545 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
b44b2e06 546 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
05cacb17 547 i, I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 548 return err;
549}
54450f59 550
b44b2e06 551static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 552{
553 unsigned int i;
554
269bd132 555 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 556 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 557
b44b2e06 558 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 559}
560
b44b2e06 561static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 562{
563 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 564 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 565 delayed_work_enable_hotplug);
566 struct v4l2_subdev *sd = &state->sd;
54450f59 567
dd08beb9 568 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 569
b44b2e06 570 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 571}
572
573static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
574{
b44b2e06 575 struct adv76xx_state *state = to_state(sd);
54450f59 576
b44b2e06 577 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 578}
579
51182a94
LP		 580static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
581{
582 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
583}
584
54450f59
HV		 585static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
586{
b44b2e06 587 struct adv76xx_state *state = to_state(sd);
54450f59 588
b44b2e06 589 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
54450f59
HV		 590}
591
22d97e56 592static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 593{
22d97e56 594 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 595}
596
54450f59
HV		 597static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598{
b44b2e06 599 struct adv76xx_state *state = to_state(sd);
54450f59 600
b44b2e06 601 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
54450f59
HV		 602}
603
604static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
605{
b44b2e06 606 struct adv76xx_state *state = to_state(sd);
54450f59 607
b44b2e06 608 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 609}
610
51182a94
LP		 611static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
612{
613 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
614}
615
54450f59
HV		 616static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
617{
b44b2e06 618 struct adv76xx_state *state = to_state(sd);
54450f59 619
b44b2e06 620 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
54450f59
HV		 621}
622
22d97e56 623static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 624{
22d97e56 625 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 626}
627
628static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
629{
b44b2e06 630 struct adv76xx_state *state = to_state(sd);
54450f59 631
05cacb17 632 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 633}
634
635static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
636{
b44b2e06 637 struct adv76xx_state *state = to_state(sd);
54450f59 638
05cacb17
LP		 639 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
640}
d42010a1 641
b44b2e06
PA		 642#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
643#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 644
645#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 646static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 647{
b44b2e06 648 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 649 unsigned int page = reg >> 8;
650
651 if (!(BIT(page) & state->info->page_mask))
652 return -EINVAL;
653
654 reg &= 0xff;
655
05cacb17 656 return adv_smbus_read_byte_data(state, page, reg);
d42010a1
LPC		 657}
658#endif
659
b44b2e06 660static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 661{
b44b2e06 662 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 663 unsigned int page = reg >> 8;
664
665 if (!(BIT(page) & state->info->page_mask))
666 return -EINVAL;
667
668 reg &= 0xff;
669
05cacb17 670 return adv_smbus_write_byte_data(state, page, reg, val);
d42010a1
LPC		 671}
672
b44b2e06
PA		 673static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
674 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 675{
676 unsigned int i;
677
b44b2e06
PA		 678 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
679 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 680}
681
539b33b0
LP		 682/* -----------------------------------------------------------------------------
683 * Format helpers
684 */
685
b44b2e06
PA		 686static const struct adv76xx_format_info adv7604_formats[] = {
687 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
688 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
689 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
690 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
691 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
692 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
693 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
694 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
695 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
696 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
697 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
698 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
699 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
700 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
701 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
703 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
705 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
707 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
709 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
711 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
712 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
713 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
714 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
715 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
716 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
717 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
719 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
721 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
723 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 725};
726
b44b2e06
PA		 727static const struct adv76xx_format_info adv7611_formats[] = {
728 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
729 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
730 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
731 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
732 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
733 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
734 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
735 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
736 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
737 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
738 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
739 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
740 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
741 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
742 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
743 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
744 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
745 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
746 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
747 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
748 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
749 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
750 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
751 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
752 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
753 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 754};
755
b44b2e06
PA		 756static const struct adv76xx_format_info *
757adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 758{
759 unsigned int i;
760
761 for (i = 0; i < state->info->nformats; ++i) {
762 if (state->info->formats[i].code == code)
763 return &state->info->formats[i];
764 }
765
766 return NULL;
767}
768
54450f59
HV		 769/* ----------------------------------------------------------------------- */
770
4a31a93a
MR		 771static inline bool is_analog_input(struct v4l2_subdev *sd)
772{
b44b2e06 773 struct adv76xx_state *state = to_state(sd);
4a31a93a 774
c784b1e2
LP		 775 return state->selected_input == ADV7604_PAD_VGA_RGB ||
776 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 777}
778
779static inline bool is_digital_input(struct v4l2_subdev *sd)
780{
b44b2e06 781 struct adv76xx_state *state = to_state(sd);
4a31a93a 782
b44b2e06 783 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 784 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
785 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
786 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 787}
788
789/* ----------------------------------------------------------------------- */
790
54450f59 791#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 792static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 793{
794 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
795 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
796 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
797 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
798 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
799 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
800 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
801 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
802 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
803 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
804 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
805 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
806 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
807}
808
b44b2e06 809static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 810 struct v4l2_dbg_register *reg)
811{
d42010a1
LPC		 812 int ret;
813
b44b2e06 814 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 815 if (ret < 0) {
54450f59 816 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 817 adv76xx_inv_register(sd);
d42010a1 818 return ret;
54450f59 819 }
d42010a1
LPC		 820
821 reg->size = 1;
822 reg->val = ret;
823
54450f59
HV		 824 return 0;
825}
826
b44b2e06 827static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 828 const struct v4l2_dbg_register *reg)
54450f59 829{
d42010a1 830 int ret;
1577461b 831
b44b2e06 832 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 833 if (ret < 0) {
54450f59 834 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 835 adv76xx_inv_register(sd);
d42010a1 836 return ret;
54450f59 837 }
d42010a1 838
54450f59
HV		 839 return 0;
840}
841#endif
842
d42010a1
LPC		 843static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
844{
845 u8 value = io_read(sd, 0x6f);
846
847 return ((value & 0x10) >> 4)
848 | ((value & 0x08) >> 2)
849 | ((value & 0x04) << 0)
850 | ((value & 0x02) << 2);
851}
852
853static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
854{
855 u8 value = io_read(sd, 0x6f);
856
857 return value & 1;
858}
859
b44b2e06 860static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 861{
b44b2e06
PA		 862 struct adv76xx_state *state = to_state(sd);
863 const struct adv76xx_chip_info *info = state->info;
54450f59 864
54450f59 865 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 866 info->read_cable_det(sd));
54450f59
HV		 867}
868
ccbd5bc4
HV		 869static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
870 u8 prim_mode,
b44b2e06 871 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 872 const struct v4l2_dv_timings *timings)
873{
ccbd5bc4
HV		 874 int i;
875
876 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 877 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 878 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 879 continue;
880 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
881 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
882 prim_mode); /* v_freq and prim mode */
883 return 0;
884 }
885
886 return -1;
887}
888
889static int configure_predefined_video_timings(struct v4l2_subdev *sd,
890 struct v4l2_dv_timings *timings)
54450f59 891{
b44b2e06 892 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 893 int err;
894
895 v4l2_dbg(1, debug, sd, "%s", __func__);
896
b44b2e06 897 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 898 /* reset to default values */
899 io_write(sd, 0x16, 0x43);
900 io_write(sd, 0x17, 0x5a);
901 }
ccbd5bc4 902 /* disable embedded syncs for auto graphics mode */
22d97e56 903 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 904 cp_write(sd, 0x8f, 0x00);
905 cp_write(sd, 0x90, 0x00);
906 cp_write(sd, 0xa2, 0x00);
907 cp_write(sd, 0xa3, 0x00);
908 cp_write(sd, 0xa4, 0x00);
909 cp_write(sd, 0xa5, 0x00);
910 cp_write(sd, 0xa6, 0x00);
911 cp_write(sd, 0xa7, 0x00);
912 cp_write(sd, 0xab, 0x00);
913 cp_write(sd, 0xac, 0x00);
914
4a31a93a 915 if (is_analog_input(sd)) {
ccbd5bc4
HV		 916 err = find_and_set_predefined_video_timings(sd,
917 0x01, adv7604_prim_mode_comp, timings);
918 if (err)
919 err = find_and_set_predefined_video_timings(sd,
920 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 921 } else if (is_digital_input(sd)) {
ccbd5bc4 922 err = find_and_set_predefined_video_timings(sd,
b44b2e06 923 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 924 if (err)
925 err = find_and_set_predefined_video_timings(sd,
b44b2e06 926 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 927 } else {
928 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
929 __func__, state->selected_input);
ccbd5bc4 930 err = -1;
ccbd5bc4
HV		 931 }
932
933
934 return err;
935}
936
937static void configure_custom_video_timings(struct v4l2_subdev *sd,
938 const struct v4l2_bt_timings *bt)
939{
b44b2e06 940 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 941 u32 width = htotal(bt);
942 u32 height = vtotal(bt);
943 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
944 u16 cp_start_eav = width - bt->hfrontporch;
945 u16 cp_start_vbi = height - bt->vfrontporch;
946 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
947 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 948 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 949 const u8 pll[2] = {
950 0xc0 | ((width >> 8) & 0x1f),
951 width & 0xff
952 };
54450f59
HV		 953
954 v4l2_dbg(2, debug, sd, "%s\n", __func__);
955
4a31a93a 956 if (is_analog_input(sd)) {
ccbd5bc4
HV		 957 /* auto graphics */
958 io_write(sd, 0x00, 0x07); /* video std */
959 io_write(sd, 0x01, 0x02); /* prim mode */
960 /* enable embedded syncs for auto graphics mode */
22d97e56 961 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 962
ccbd5bc4 963 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 964 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
965 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
b44b2e06 966 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
05cacb17 967 0x16, 2, pll))
54450f59 968 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 969
970 /* active video - horizontal timing */
54450f59 971 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 972 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 973 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 974 cp_write(sd, 0xa4, cp_start_eav & 0xff);
975
976 /* active video - vertical timing */
54450f59 977 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 978 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 979 ((cp_end_vbi >> 8) & 0xf));
54450f59 980 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 981 } else if (is_digital_input(sd)) {
ccbd5bc4 982 /* set default prim_mode/vid_std for HDMI
39c1cb2b 983 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 984 io_write(sd, 0x00, 0x02); /* video std */
985 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 986 } else {
987 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
988 __func__, state->selected_input);
54450f59 989 }
54450f59 990
ccbd5bc4
HV		 991 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
992 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
993 cp_write(sd, 0xab, (height >> 4) & 0xff);
994 cp_write(sd, 0xac, (height & 0x0f) << 4);
995}
54450f59 996
b44b2e06 997static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 998{
b44b2e06 999 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1000 u8 offset_buf[4];
1001
1002 if (auto_offset) {
1003 offset_a = 0x3ff;
1004 offset_b = 0x3ff;
1005 offset_c = 0x3ff;
1006 }
1007
1008 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1009 __func__, auto_offset ? "Auto" : "Manual",
1010 offset_a, offset_b, offset_c);
1011
1012 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1013 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1014 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1015 offset_buf[3] = offset_c & 0x0ff;
1016
1017 /* Registers must be written in this order with no i2c access in between */
b44b2e06 1018 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
05cacb17 1019 0x77, 4, offset_buf))
5c6c6349
MR		 1020 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1021}
1022
b44b2e06 1023static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1024{
b44b2e06 1025 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1026 u8 gain_buf[4];
1027 u8 gain_man = 1;
1028 u8 agc_mode_man = 1;
1029
1030 if (auto_gain) {
1031 gain_man = 0;
1032 agc_mode_man = 0;
1033 gain_a = 0x100;
1034 gain_b = 0x100;
1035 gain_c = 0x100;
1036 }
1037
1038 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1039 __func__, auto_gain ? "Auto" : "Manual",
1040 gain_a, gain_b, gain_c);
1041
1042 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1043 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1044 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1045 gain_buf[3] = ((gain_c & 0x0ff));
1046
1047 /* Registers must be written in this order with no i2c access in between */
b44b2e06 1048 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
05cacb17 1049 0x73, 4, gain_buf))
5c6c6349
MR		 1050 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1051}
1052
54450f59
HV		 1053static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1054{
b44b2e06 1055 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1056 bool rgb_output = io_read(sd, 0x02) & 0x02;
1057 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1058
1059 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1060 __func__, state->rgb_quantization_range,
1061 rgb_output, hdmi_signal);
54450f59 1062
b44b2e06
PA		 1063 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1064 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1065
54450f59
HV		 1066 switch (state->rgb_quantization_range) {
1067 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1068 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1069 /* Receiving analog RGB signal
1070 * Set RGB full range (0-255) */
22d97e56 1071 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1072 break;
1073 }
1074
c784b1e2 1075 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1076 /* Receiving analog YPbPr signal
1077 * Set automode */
22d97e56 1078 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1079 break;
1080 }
1081
5c6c6349 1082 if (hdmi_signal) {
9833239e
MR		 1083 /* Receiving HDMI signal
1084 * Set automode */
22d97e56 1085 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1086 break;
1087 }
1088
1089 /* Receiving DVI-D signal
1090 * ADV7604 selects RGB limited range regardless of
1091 * input format (CE/IT) in automatic mode */
680fee04 1092 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
9833239e 1093 /* RGB limited range (16-235) */
22d97e56 1094 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1095 } else {
1096 /* RGB full range (0-255) */
22d97e56 1097 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1098
1099 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1100 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1101 } else {
b44b2e06
PA		 1102 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1103 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1104 }
54450f59
HV		 1105 }
1106 break;
1107 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1108 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1109 /* YCrCb limited range (16-235) */
22d97e56 1110 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1111 break;
d261e842 1112 }
5c6c6349
MR		 1113
1114 /* RGB limited range (16-235) */
22d97e56 1115 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1116
54450f59
HV		 1117 break;
1118 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1119 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1120 /* YCrCb full range (0-255) */
22d97e56 1121 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1122 break;
1123 }
1124
1125 /* RGB full range (0-255) */
22d97e56 1126 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1127
1128 if (is_analog_input(sd) || hdmi_signal)
1129 break;
1130
1131 /* Adjust gain/offset for DVI-D signals only */
1132 if (rgb_output) {
b44b2e06 1133 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1134 } else {
b44b2e06
PA		 1135 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1136 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1137 }
54450f59
HV		 1138 break;
1139 }
1140}
1141
b44b2e06 1142static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1143{
c269887c 1144 struct v4l2_subdev *sd =
b44b2e06 1145 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1146
b44b2e06 1147 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1148
1149 switch (ctrl->id) {
1150 case V4L2_CID_BRIGHTNESS:
1151 cp_write(sd, 0x3c, ctrl->val);
1152 return 0;
1153 case V4L2_CID_CONTRAST:
1154 cp_write(sd, 0x3a, ctrl->val);
1155 return 0;
1156 case V4L2_CID_SATURATION:
1157 cp_write(sd, 0x3b, ctrl->val);
1158 return 0;
1159 case V4L2_CID_HUE:
1160 cp_write(sd, 0x3d, ctrl->val);
1161 return 0;
1162 case V4L2_CID_DV_RX_RGB_RANGE:
1163 state->rgb_quantization_range = ctrl->val;
1164 set_rgb_quantization_range(sd);
1165 return 0;
1166 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1167 if (!adv76xx_has_afe(state))
d42010a1 1168 return -EINVAL;
54450f59
HV		 1169 /* Set the analog sampling phase. This is needed to find the
1170 best sampling phase for analog video: an application or
1171 driver has to try a number of phases and analyze the picture
1172 quality before settling on the best performing phase. */
1173 afe_write(sd, 0xc8, ctrl->val);
1174 return 0;
1175 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1176 /* Use the default blue color for free running mode,
1177 or supply your own. */
22d97e56 1178 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1179 return 0;
1180 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1181 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1182 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1183 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1184 return 0;
1185 }
1186 return -EINVAL;
1187}
1188
54450f59
HV		 1189/* ----------------------------------------------------------------------- */
1190
1191static inline bool no_power(struct v4l2_subdev *sd)
1192{
1193 /* Entire chip or CP powered off */
1194 return io_read(sd, 0x0c) & 0x24;
1195}
1196
1197static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1198{
b44b2e06 1199 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1200
1201 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1202}
1203
1204static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1205{
b44b2e06
PA		 1206 struct adv76xx_state *state = to_state(sd);
1207 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1208
1209 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1210}
1211
bb88f325
MB		 1212static inline bool is_hdmi(struct v4l2_subdev *sd)
1213{
1214 return hdmi_read(sd, 0x05) & 0x80;
1215}
1216
54450f59
HV		 1217static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1218{
b44b2e06 1219 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1220
1221 /*
1222 * Chips without a AFE don't expose registers for the SSPD, so just assume
1223 * that we have a lock.
1224 */
b44b2e06 1225 if (adv76xx_has_afe(state))
d42010a1
LPC		 1226 return false;
1227
54450f59
HV		 1228 /* TODO channel 2 */
1229 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1230}
1231
1232static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1233{
1234 /* TODO channel 2 */
1235 return !(cp_read(sd, 0xb1) & 0x80);
1236}
1237
1238static inline bool no_signal(struct v4l2_subdev *sd)
1239{
54450f59
HV		 1240 bool ret;
1241
1242 ret = no_power(sd);
1243
1244 ret |= no_lock_stdi(sd);
1245 ret |= no_lock_sspd(sd);
1246
4a31a93a 1247 if (is_digital_input(sd)) {
54450f59
HV		 1248 ret |= no_lock_tmds(sd);
1249 ret |= no_signal_tmds(sd);
1250 }
1251
1252 return ret;
1253}
1254
1255static inline bool no_lock_cp(struct v4l2_subdev *sd)
1256{
b44b2e06 1257 struct adv76xx_state *state = to_state(sd);
d42010a1 1258
b44b2e06 1259 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1260 return false;
1261
54450f59
HV		 1262 /* CP has detected a non standard number of lines on the incoming
1263 video compared to what it is configured to receive by s_dv_timings */
1264 return io_read(sd, 0x12) & 0x01;
1265}
1266
58514625 1267static inline bool in_free_run(struct v4l2_subdev *sd)
1268{
1269 return cp_read(sd, 0xff) & 0x10;
1270}
1271
b44b2e06 1272static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1273{
54450f59
HV		 1274 *status = 0;
1275 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1276 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1277 if (!in_free_run(sd) && no_lock_cp(sd))
1278 *status |= is_digital_input(sd) ?
1279 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1280
1281 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1282
1283 return 0;
1284}
1285
1286/* ----------------------------------------------------------------------- */
1287
54450f59
HV		 1288struct stdi_readback {
1289 u16 bl, lcf, lcvs;
1290 u8 hs_pol, vs_pol;
1291 bool interlaced;
1292};
1293
1294static int stdi2dv_timings(struct v4l2_subdev *sd,
1295 struct stdi_readback *stdi,
1296 struct v4l2_dv_timings *timings)
1297{
b44b2e06
PA		 1298 struct adv76xx_state *state = to_state(sd);
1299 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1300 u32 pix_clk;
1301 int i;
1302
b44b2e06
PA		 1303 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1304 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
54450f59 1305 continue;
b44b2e06 1306 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
54450f59
HV		 1307 continue;
1308
b44b2e06 1309 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
54450f59 1310
b44b2e06
PA		 1311 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1312 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1313 *timings = adv76xx_timings[i];
54450f59
HV		 1314 return 0;
1315 }
1316 }
1317
1318 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1319 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1320 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1321 timings))
1322 return 0;
1323 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1324 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1325 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1326 state->aspect_ratio, timings))
1327 return 0;
1328
ccbd5bc4
HV		 1329 v4l2_dbg(2, debug, sd,
1330 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1331 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1332 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1333 return -1;
1334}
1335
d42010a1 1336
54450f59
HV		 1337static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1338{
b44b2e06
PA		 1339 struct adv76xx_state *state = to_state(sd);
1340 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1341 u8 polarity;
1342
54450f59
HV		 1343 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1344 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1345 return -1;
1346 }
1347
1348 /* read STDI */
51182a94 1349 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1350 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1351 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1352 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1353
b44b2e06 1354 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1355 /* read SSPD */
1356 polarity = cp_read(sd, 0xb5);
1357 if ((polarity & 0x03) == 0x01) {
1358 stdi->hs_pol = polarity & 0x10
1359 ? (polarity & 0x08 ? '+' : '-') : 'x';
1360 stdi->vs_pol = polarity & 0x40
1361 ? (polarity & 0x20 ? '+' : '-') : 'x';
1362 } else {
1363 stdi->hs_pol = 'x';
1364 stdi->vs_pol = 'x';
1365 }
54450f59 1366 } else {
d42010a1
LPC		 1367 polarity = hdmi_read(sd, 0x05);
1368 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1369 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1370 }
1371
1372 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1373 v4l2_dbg(2, debug, sd,
1374 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1375 return -1;
1376 }
1377
1378 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1379 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1380 memset(stdi, 0, sizeof(struct stdi_readback));
1381 return -1;
1382 }
1383
1384 v4l2_dbg(2, debug, sd,
1385 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1386 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1387 stdi->hs_pol, stdi->vs_pol,
1388 stdi->interlaced ? "interlaced" : "progressive");
1389
1390 return 0;
1391}
1392
b44b2e06 1393static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1394 struct v4l2_enum_dv_timings *timings)
1395{
b44b2e06 1396 struct adv76xx_state *state = to_state(sd);
afec5599 1397
b44b2e06 1398 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
54450f59 1399 return -EINVAL;
afec5599
LP		 1400
1401 if (timings->pad >= state->source_pad)
1402 return -EINVAL;
1403
54450f59 1404 memset(timings->reserved, 0, sizeof(timings->reserved));
b44b2e06 1405 timings->timings = adv76xx_timings[timings->index];
54450f59
HV		 1406 return 0;
1407}
1408
b44b2e06 1409static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1410 struct v4l2_dv_timings_cap *cap)
54450f59 1411{
b44b2e06 1412 struct adv76xx_state *state = to_state(sd);
7515e096
LP		 1413
1414 if (cap->pad >= state->source_pad)
1415 return -EINVAL;
1416
54450f59
HV		 1417 cap->type = V4L2_DV_BT_656_1120;
1418 cap->bt.max_width = 1920;
1419 cap->bt.max_height = 1200;
fe9c2564 1420 cap->bt.min_pixelclock = 25000000;
afec5599 1421
7515e096 1422 switch (cap->pad) {
b44b2e06 1423 case ADV76XX_PAD_HDMI_PORT_A:
afec5599
LP		 1424 case ADV7604_PAD_HDMI_PORT_B:
1425 case ADV7604_PAD_HDMI_PORT_C:
1426 case ADV7604_PAD_HDMI_PORT_D:
54450f59 1427 cap->bt.max_pixelclock = 225000000;
afec5599
LP		 1428 break;
1429 case ADV7604_PAD_VGA_RGB:
1430 case ADV7604_PAD_VGA_COMP:
1431 default:
54450f59 1432 cap->bt.max_pixelclock = 170000000;
afec5599
LP		 1433 break;
1434 }
1435
54450f59
HV		 1436 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1437 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1438 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1439 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1440 return 0;
1441}
1442
1443/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1444 if the format is listed in adv76xx_timings[] */
1445static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1446 struct v4l2_dv_timings *timings)
1447{
54450f59
HV		 1448 int i;
1449
b44b2e06
PA		 1450 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1451 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
4a31a93a 1452 is_digital_input(sd) ? 250000 : 1000000)) {
b44b2e06 1453 *timings = adv76xx_timings[i];
54450f59
HV		 1454 break;
1455 }
1456 }
1457}
1458
d42010a1
LPC		 1459static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1460{
1461 unsigned int freq;
1462 int a, b;
1463
1464 a = hdmi_read(sd, 0x06);
1465 b = hdmi_read(sd, 0x3b);
1466 if (a < 0 || b < 0)
1467 return 0;
1468 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1469
1470 if (is_hdmi(sd)) {
1471 /* adjust for deep color mode */
1472 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1473
1474 freq = freq * 8 / bits_per_channel;
1475 }
1476
1477 return freq;
1478}
1479
1480static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1481{
1482 int a, b;
1483
1484 a = hdmi_read(sd, 0x51);
1485 b = hdmi_read(sd, 0x52);
1486 if (a < 0 || b < 0)
1487 return 0;
1488 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1489}
1490
b44b2e06 1491static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1492 struct v4l2_dv_timings *timings)
1493{
b44b2e06
PA		 1494 struct adv76xx_state *state = to_state(sd);
1495 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1496 struct v4l2_bt_timings *bt = &timings->bt;
1497 struct stdi_readback stdi;
1498
1499 if (!timings)
1500 return -EINVAL;
1501
1502 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1503
1504 if (no_signal(sd)) {
1e0b9156 1505 state->restart_stdi_once = true;
54450f59
HV		 1506 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1507 return -ENOLINK;
1508 }
1509
1510 /* read STDI */
1511 if (read_stdi(sd, &stdi)) {
1512 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1513 return -ENOLINK;
1514 }
1515 bt->interlaced = stdi.interlaced ?
1516 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1517
4a31a93a 1518 if (is_digital_input(sd)) {
54450f59
HV		 1519 timings->type = V4L2_DV_BT_656_1120;
1520
5380baaf 1521 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1522 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
d42010a1 1523 bt->pixelclock = info->read_hdmi_pixelclock(sd);
5380baaf 1524 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1525 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1526 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1527 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1528 info->field0_vfrontporch_mask) / 2;
1529 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1530 bt->vbackporch = hdmi_read16(sd, 0x32,
1531 info->field0_vbackporch_mask) / 2;
54450f59
HV		 1532 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1533 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1534 if (bt->interlaced == V4L2_DV_INTERLACED) {
5380baaf 1535 bt->height += hdmi_read16(sd, 0x0b,
1536 info->field1_height_mask);
1537 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1538 info->field1_vfrontporch_mask) / 2;
1539 bt->il_vsync = hdmi_read16(sd, 0x30,
1540 info->field1_vsync_mask) / 2;
1541 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1542 info->field1_vbackporch_mask) / 2;
54450f59 1543 }
b44b2e06 1544 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1545 } else {
1546 /* find format
80939647 1547 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1548 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1549 */
1550 if (!stdi2dv_timings(sd, &stdi, timings))
1551 goto found;
1552 stdi.lcvs += 1;
1553 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1554 if (!stdi2dv_timings(sd, &stdi, timings))
1555 goto found;
1556 stdi.lcvs -= 2;
1557 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1558 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1559 /*
1560 * The STDI block may measure wrong values, especially
1561 * for lcvs and lcf. If the driver can not find any
1562 * valid timing, the STDI block is restarted to measure
1563 * the video timings again. The function will return an
1564 * error, but the restart of STDI will generate a new
1565 * STDI interrupt and the format detection process will
1566 * restart.
1567 */
1568 if (state->restart_stdi_once) {
1569 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1570 /* TODO restart STDI for Sync Channel 2 */
1571 /* enter one-shot mode */
22d97e56 1572 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1573 /* trigger STDI restart */
22d97e56 1574 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1575 /* reset to continuous mode */
22d97e56 1576 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1577 state->restart_stdi_once = false;
1578 return -ENOLINK;
1579 }
54450f59
HV		 1580 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1581 return -ERANGE;
1582 }
cf9afb1d 1583 state->restart_stdi_once = true;
54450f59
HV		 1584 }
1585found:
1586
1587 if (no_signal(sd)) {
1588 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1589 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1590 return -ENOLINK;
1591 }
1592
4a31a93a
MR		 1593 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1594 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1595 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1596 __func__, (u32)bt->pixelclock);
1597 return -ERANGE;
1598 }
1599
1600 if (debug > 1)
b44b2e06 1601 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1602 timings, true);
54450f59
HV		 1603
1604 return 0;
1605}
1606
b44b2e06 1607static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1608 struct v4l2_dv_timings *timings)
1609{
b44b2e06 1610 struct adv76xx_state *state = to_state(sd);
54450f59 1611 struct v4l2_bt_timings *bt;
ccbd5bc4 1612 int err;
54450f59
HV		 1613
1614 if (!timings)
1615 return -EINVAL;
1616
d48eb48c
MR		 1617 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1618 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1619 return 0;
1620 }
1621
54450f59
HV		 1622 bt = &timings->bt;
1623
4a31a93a
MR		 1624 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1625 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1626 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1627 __func__, (u32)bt->pixelclock);
1628 return -ERANGE;
1629 }
ccbd5bc4 1630
b44b2e06 1631 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1632
1633 state->timings = *timings;
1634
22d97e56 1635 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1636
1637 /* Use prim_mode and vid_std when available */
1638 err = configure_predefined_video_timings(sd, timings);
1639 if (err) {
1640 /* custom settings when the video format
1641 does not have prim_mode/vid_std */
1642 configure_custom_video_timings(sd, bt);
1643 }
54450f59
HV		 1644
1645 set_rgb_quantization_range(sd);
1646
54450f59 1647 if (debug > 1)
b44b2e06 1648 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1649 timings, true);
54450f59
HV		 1650 return 0;
1651}
1652
b44b2e06 1653static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1654 struct v4l2_dv_timings *timings)
1655{
b44b2e06 1656 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1657
1658 *timings = state->timings;
1659 return 0;
1660}
1661
d42010a1
LPC		 1662static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1663{
1664 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1665}
1666
1667static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1668{
1669 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1670}
1671
6b0d5d34 1672static void enable_input(struct v4l2_subdev *sd)
54450f59 1673{
b44b2e06 1674 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1675
4a31a93a 1676 if (is_analog_input(sd)) {
54450f59 1677 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1678 } else if (is_digital_input(sd)) {
22d97e56 1679 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1680 state->info->set_termination(sd, true);
54450f59 1681 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1682 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1683 } else {
1684 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1685 __func__, state->selected_input);
54450f59
HV		 1686 }
1687}
1688
1689static void disable_input(struct v4l2_subdev *sd)
1690{
b44b2e06 1691 struct adv76xx_state *state = to_state(sd);
d42010a1 1692
22d97e56 1693 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1694 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1695 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1696 state->info->set_termination(sd, false);
54450f59
HV		 1697}
1698
6b0d5d34 1699static void select_input(struct v4l2_subdev *sd)
54450f59 1700{
b44b2e06
PA		 1701 struct adv76xx_state *state = to_state(sd);
1702 const struct adv76xx_chip_info *info = state->info;
54450f59 1703
4a31a93a 1704 if (is_analog_input(sd)) {
b44b2e06 1705 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1706
1707 afe_write(sd, 0x00, 0x08); /* power up ADC */
1708 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1709 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1710 } else if (is_digital_input(sd)) {
1711 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1712
b44b2e06 1713 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1714
b44b2e06 1715 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1716 afe_write(sd, 0x00, 0xff); /* power down ADC */
1717 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1718 afe_write(sd, 0xc8, 0x40); /* phase control */
1719 }
1720
54450f59
HV		 1721 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1722 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1723 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1724 } else {
1725 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1726 __func__, state->selected_input);
54450f59
HV		 1727 }
1728}
1729
b44b2e06 1730static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1731 u32 input, u32 output, u32 config)
1732{
b44b2e06 1733 struct adv76xx_state *state = to_state(sd);
54450f59 1734
ff4f80fd
MR		 1735 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1736 __func__, input, state->selected_input);
1737
1738 if (input == state->selected_input)
1739 return 0;
54450f59 1740
d42010a1
LPC		 1741 if (input > state->info->max_port)
1742 return -EINVAL;
1743
4a31a93a 1744 state->selected_input = input;
54450f59
HV		 1745
1746 disable_input(sd);
1747
6b0d5d34 1748 select_input(sd);
54450f59 1749
6b0d5d34 1750 enable_input(sd);
54450f59
HV		 1751
1752 return 0;
1753}
1754
b44b2e06 1755static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1756 struct v4l2_subdev_pad_config *cfg,
539b33b0 1757 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1758{
b44b2e06 1759 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1760
1761 if (code->index >= state->info->nformats)
54450f59 1762 return -EINVAL;
539b33b0
LP		 1763
1764 code->code = state->info->formats[code->index].code;
1765
54450f59
HV		 1766 return 0;
1767}
1768
b44b2e06 1769static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1770 struct v4l2_mbus_framefmt *format)
54450f59 1771{
539b33b0 1772 memset(format, 0, sizeof(*format));
54450f59 1773
539b33b0
LP		 1774 format->width = state->timings.bt.width;
1775 format->height = state->timings.bt.height;
1776 format->field = V4L2_FIELD_NONE;
680fee04 1777 format->colorspace = V4L2_COLORSPACE_SRGB;
539b33b0 1778
680fee04 1779 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
539b33b0 1780 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1781 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1782}
1783
1784/*
1785 * Compute the op_ch_sel value required to obtain on the bus the component order
1786 * corresponding to the selected format taking into account bus reordering
1787 * applied by the board at the output of the device.
1788 *
1789 * The following table gives the op_ch_value from the format component order
1790 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1791 * adv76xx_bus_order value in row).
539b33b0
LP		 1792 *
1793 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1794 * ----------+-------------------------------------------------
1795 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1796 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1797 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1798 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1799 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1800 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1801 */
b44b2e06 1802static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1803{
1804#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1805 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1806 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1807#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1808
1809 static const unsigned int op_ch_sel[6][6] = {
1810 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1811 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1812 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1813 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1814 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1815 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1816 };
1817
1818 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1819}
1820
b44b2e06 1821static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1822{
1823 struct v4l2_subdev *sd = &state->sd;
1824
22d97e56 1825 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1826 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1827 io_write(sd, 0x03, state->format->op_format_sel |
1828 state->pdata.op_format_mode_sel);
b44b2e06 1829 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1830 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1831 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1832}
1833
f7234138
HV		 1834static int adv76xx_get_format(struct v4l2_subdev *sd,
1835 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1836 struct v4l2_subdev_format *format)
1837{
b44b2e06 1838 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1839
1840 if (format->pad != state->source_pad)
1841 return -EINVAL;
1842
b44b2e06 1843 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1844
1845 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1846 struct v4l2_mbus_framefmt *fmt;
1847
f7234138 1848 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1849 format->format.code = fmt->code;
1850 } else {
1851 format->format.code = state->format->code;
54450f59 1852 }
539b33b0
LP		 1853
1854 return 0;
1855}
1856
f7234138
HV		 1857static int adv76xx_set_format(struct v4l2_subdev *sd,
1858 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1859 struct v4l2_subdev_format *format)
1860{
b44b2e06
PA		 1861 struct adv76xx_state *state = to_state(sd);
1862 const struct adv76xx_format_info *info;
539b33b0
LP		 1863
1864 if (format->pad != state->source_pad)
1865 return -EINVAL;
1866
b44b2e06 1867 info = adv76xx_format_info(state, format->format.code);
539b33b0 1868 if (info == NULL)
b44b2e06 1869 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1870
b44b2e06 1871 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1872 format->format.code = info->code;
1873
1874 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1875 struct v4l2_mbus_framefmt *fmt;
1876
f7234138 1877 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1878 fmt->code = format->format.code;
1879 } else {
1880 state->format = info;
b44b2e06 1881 adv76xx_setup_format(state);
539b33b0
LP		 1882 }
1883
54450f59
HV		 1884 return 0;
1885}
1886
b44b2e06 1887static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1888{
b44b2e06
PA		 1889 struct adv76xx_state *state = to_state(sd);
1890 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1891 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1892 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1893 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1894 u8 fmt_change_digital;
1895 u8 fmt_change;
1896 u8 tx_5v;
1897
1898 if (irq_reg_0x43)
1899 io_write(sd, 0x44, irq_reg_0x43);
1900 if (irq_reg_0x70)
1901 io_write(sd, 0x71, irq_reg_0x70);
1902 if (irq_reg_0x6b)
1903 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1904
ff4f80fd
MR		 1905 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1906
54450f59 1907 /* format change */
f24d229c 1908 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1909 fmt_change_digital = is_digital_input(sd)
1910 ? irq_reg_0x6b & info->fmt_change_digital_mask
1911 : 0;
14d03233 1912
54450f59
HV		 1913 if (fmt_change || fmt_change_digital) {
1914 v4l2_dbg(1, debug, sd,
25a64ac9 1915 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1916 __func__, fmt_change, fmt_change_digital);
25a64ac9 1917
b44b2e06 1918 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
25a64ac9 1919
54450f59
HV		 1920 if (handled)
1921 *handled = true;
1922 }
f24d229c
MR		 1923 /* HDMI/DVI mode */
1924 if (irq_reg_0x6b & 0x01) {
1925 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1926 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1927 set_rgb_quantization_range(sd);
1928 if (handled)
1929 *handled = true;
1930 }
1931
54450f59 1932 /* tx 5v detect */
d42010a1 1933 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
54450f59
HV		 1934 if (tx_5v) {
1935 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1936 io_write(sd, 0x71, tx_5v);
b44b2e06 1937 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1938 if (handled)
1939 *handled = true;
1940 }
1941 return 0;
1942}
1943
b44b2e06 1944static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1945{
b44b2e06 1946 struct adv76xx_state *state = to_state(sd);
4a31a93a 1947 u8 *data = NULL;
54450f59 1948
dd9ac11a 1949 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1950
1951 switch (edid->pad) {
b44b2e06 1952 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1953 case ADV7604_PAD_HDMI_PORT_B:
1954 case ADV7604_PAD_HDMI_PORT_C:
1955 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1956 if (state->edid.present & (1 << edid->pad))
1957 data = state->edid.edid;
1958 break;
1959 default:
1960 return -EINVAL;
4a31a93a 1961 }
dd9ac11a
HV		 1962
1963 if (edid->start_block == 0 && edid->blocks == 0) {
1964 edid->blocks = data ? state->edid.blocks : 0;
1965 return 0;
1966 }
1967
1968 if (data == NULL)
4a31a93a
MR		 1969 return -ENODATA;
1970
dd9ac11a
HV		 1971 if (edid->start_block >= state->edid.blocks)
1972 return -EINVAL;
1973
1974 if (edid->start_block + edid->blocks > state->edid.blocks)
1975 edid->blocks = state->edid.blocks - edid->start_block;
1976
1977 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1978
54450f59
HV		 1979 return 0;
1980}
1981
dd08beb9 1982static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1983{
1984 u8 d;
1985
1986 if ((edid[0x7e] != 1) ||
1987 (edid[0x80] != 0x02) ||
1988 (edid[0x81] != 0x03)) {
1989 return -1;
1990 }
1991
1992 /* search Vendor Specific Data Block (tag 3) */
1993 d = edid[0x82] & 0x7f;
1994 if (d > 4) {
1995 int i = 0x84;
1996 int end = 0x80 + d;
1997
1998 do {
1999 u8 tag = edid[i] >> 5;
2000 u8 len = edid[i] & 0x1f;
2001
2002 if ((tag == 3) && (len >= 5))
2003 return i + 4;
2004 i += len + 1;
2005 } while (i < end);
2006 }
2007 return -1;
2008}
2009
b44b2e06 2010static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 2011{
b44b2e06
PA		 2012 struct adv76xx_state *state = to_state(sd);
2013 const struct adv76xx_chip_info *info = state->info;
dd08beb9 2014 int spa_loc;
54450f59 2015 int err;
dd08beb9 2016 int i;
54450f59 2017
dd9ac11a
HV		 2018 memset(edid->reserved, 0, sizeof(edid->reserved));
2019
c784b1e2 2020 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2021 return -EINVAL;
2022 if (edid->start_block != 0)
2023 return -EINVAL;
2024 if (edid->blocks == 0) {
3e86aa85 2025 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2026 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2027 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2028 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2029
54450f59
HV		 2030 /* Fall back to a 16:9 aspect ratio */
2031 state->aspect_ratio.numerator = 16;
2032 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2033
2034 if (!state->edid.present)
2035 state->edid.blocks = 0;
2036
2037 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2038 __func__, edid->pad, state->edid.present);
54450f59
HV		 2039 return 0;
2040 }
4a31a93a
MR		 2041 if (edid->blocks > 2) {
2042 edid->blocks = 2;
54450f59 2043 return -E2BIG;
4a31a93a 2044 }
4a31a93a 2045
dd08beb9
MR		 2046 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2047 __func__, edid->pad, state->edid.present);
2048
3e86aa85 2049 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2050 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2051 adv76xx_set_hpd(state, 0);
22d97e56 2052 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2053
dd08beb9
MR		 2054 spa_loc = get_edid_spa_location(edid->edid);
2055 if (spa_loc < 0)
2056 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2057
3e86aa85 2058 switch (edid->pad) {
b44b2e06 2059 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2060 state->spa_port_a[0] = edid->edid[spa_loc];
2061 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2062 break;
c784b1e2 2063 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2064 rep_write(sd, 0x70, edid->edid[spa_loc]);
2065 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2066 break;
c784b1e2 2067 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2068 rep_write(sd, 0x72, edid->edid[spa_loc]);
2069 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2070 break;
c784b1e2 2071 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2072 rep_write(sd, 0x74, edid->edid[spa_loc]);
2073 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2074 break;
dd08beb9
MR		 2075 default:
2076 return -EINVAL;
3e86aa85 2077 }
d42010a1
LPC		 2078
2079 if (info->type == ADV7604) {
2080 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2081 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2082 } else {
2083 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2084 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2085 }
3e86aa85 2086
dd08beb9
MR		 2087 edid->edid[spa_loc] = state->spa_port_a[0];
2088 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2089
2090 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2091 state->edid.blocks = edid->blocks;
54450f59
HV		 2092 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2093 edid->edid[0x16]);
3e86aa85 2094 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2095
2096 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2097 if (err < 0) {
3e86aa85 2098 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2099 return err;
2100 }
2101
b44b2e06 2102 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2103 EDID RAM from DDC port. */
22d97e56 2104 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2105
2106 for (i = 0; i < 1000; i++) {
d42010a1 2107 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2108 break;
2109 mdelay(1);
2110 }
2111 if (i == 1000) {
2112 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2113 return -EIO;
2114 }
2115
4a31a93a
MR		 2116 /* enable hotplug after 100 ms */
2117 queue_delayed_work(state->work_queues,
2118 &state->delayed_work_enable_hotplug, HZ / 10);
2119 return 0;
54450f59
HV		 2120}
2121
2122/*********** avi info frame CEA-861-E **************/
2123
2124static void print_avi_infoframe(struct v4l2_subdev *sd)
2125{
2126 int i;
2127 u8 buf[14];
2128 u8 avi_len;
2129 u8 avi_ver;
2130
bb88f325 2131 if (!is_hdmi(sd)) {
54450f59
HV		 2132 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2133 return;
2134 }
2135 if (!(io_read(sd, 0x60) & 0x01)) {
2136 v4l2_info(sd, "AVI infoframe not received\n");
2137 return;
2138 }
2139
2140 if (io_read(sd, 0x83) & 0x01) {
2141 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2142 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2143 if (io_read(sd, 0x83) & 0x01) {
2144 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2145 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2146 }
2147 }
2148
2149 avi_len = infoframe_read(sd, 0xe2);
2150 avi_ver = infoframe_read(sd, 0xe1);
2151 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2152 avi_ver, avi_len);
2153
2154 if (avi_ver != 0x02)
2155 return;
2156
2157 for (i = 0; i < 14; i++)
2158 buf[i] = infoframe_read(sd, i);
2159
2160 v4l2_info(sd,
2161 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2162 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2163 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2164}
2165
b44b2e06 2166static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2167{
b44b2e06
PA		 2168 struct adv76xx_state *state = to_state(sd);
2169 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2170 struct v4l2_dv_timings timings;
2171 struct stdi_readback stdi;
2172 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2173 u8 edid_enabled;
2174 u8 cable_det;
54450f59 2175
f216ccb3 2176 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2177 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2178 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2179 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2180 "reserved", "reserved", "reserved", "reserved", "manual"
2181 };
f216ccb3 2182 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2183 "RGB limited range (16-235)", "RGB full range (0-255)",
2184 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2185 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2186 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2187 "invalid", "invalid", "invalid", "invalid", "invalid",
2188 "invalid", "invalid", "automatic"
2189 };
f216ccb3 2190 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2191 "Automatic",
2192 "RGB limited range (16-235)",
2193 "RGB full range (0-255)",
2194 };
f216ccb3 2195 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2196 "8-bits per channel",
2197 "10-bits per channel",
2198 "12-bits per channel",
2199 "16-bits per channel (not supported)"
2200 };
54450f59
HV		 2201
2202 v4l2_info(sd, "-----Chip status-----\n");
2203 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2204 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2205 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2206 ((edid_enabled & 0x01) ? "Yes" : "No"),
2207 ((edid_enabled & 0x02) ? "Yes" : "No"),
2208 ((edid_enabled & 0x04) ? "Yes" : "No"),
2209 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2210 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2211 "enabled" : "disabled");
2212
2213 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2214 cable_det = info->read_cable_det(sd);
4a31a93a 2215 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2216 ((cable_det & 0x01) ? "Yes" : "No"),
2217 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2218 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2219 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2220 v4l2_info(sd, "TMDS signal detected: %s\n",
2221 no_signal_tmds(sd) ? "false" : "true");
2222 v4l2_info(sd, "TMDS signal locked: %s\n",
2223 no_lock_tmds(sd) ? "false" : "true");
2224 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2225 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2226 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2227 v4l2_info(sd, "CP free run: %s\n",
58514625 2228 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2229 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2230 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2231 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2232
2233 v4l2_info(sd, "-----Video Timings-----\n");
2234 if (read_stdi(sd, &stdi))
2235 v4l2_info(sd, "STDI: not locked\n");
2236 else
2237 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2238 stdi.lcf, stdi.bl, stdi.lcvs,
2239 stdi.interlaced ? "interlaced" : "progressive",
2240 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2241 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2242 v4l2_info(sd, "No video detected\n");
2243 else
11d034c8
HV		 2244 v4l2_print_dv_timings(sd->name, "Detected format: ",
2245 &timings, true);
2246 v4l2_print_dv_timings(sd->name, "Configured format: ",
2247 &state->timings, true);
54450f59 2248
76eb2d30
MR		 2249 if (no_signal(sd))
2250 return 0;
2251
54450f59
HV		 2252 v4l2_info(sd, "-----Color space-----\n");
2253 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2254 rgb_quantization_range_txt[state->rgb_quantization_range]);
2255 v4l2_info(sd, "Input color space: %s\n",
2256 input_color_space_txt[reg_io_0x02 >> 4]);
2257 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2258 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2259 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2260 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 2261 "enabled" : "disabled");
54450f59 2262 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2263 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2264
4a31a93a 2265 if (!is_digital_input(sd))
76eb2d30
MR		 2266 return 0;
2267
2268 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2269 v4l2_info(sd, "Digital video port selected: %c\n",
2270 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2271 v4l2_info(sd, "HDCP encrypted content: %s\n",
2272 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2273 v4l2_info(sd, "HDCP keys read: %s%s\n",
2274 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2275 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2276 if (is_hdmi(sd)) {
76eb2d30
MR		 2277 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2278 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2279 bool audio_mute = io_read(sd, 0x65) & 0x40;
2280
2281 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2282 audio_pll_locked ? "locked" : "not locked",
2283 audio_sample_packet_detect ? "detected" : "not detected",
2284 audio_mute ? "muted" : "enabled");
2285 if (audio_pll_locked && audio_sample_packet_detect) {
2286 v4l2_info(sd, "Audio format: %s\n",
2287 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2288 }
2289 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2290 (hdmi_read(sd, 0x5c) << 8) +
2291 (hdmi_read(sd, 0x5d) & 0xf0));
2292 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2293 (hdmi_read(sd, 0x5e) << 8) +
2294 hdmi_read(sd, 0x5f));
2295 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2296
2297 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2298
54450f59
HV		 2299 print_avi_infoframe(sd);
2300 }
2301
2302 return 0;
2303}
2304
2305/* ----------------------------------------------------------------------- */
2306
b44b2e06
PA		 2307static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2308 .s_ctrl = adv76xx_s_ctrl,
54450f59
HV		 2309};
2310
b44b2e06
PA		 2311static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2312 .log_status = adv76xx_log_status,
2313 .interrupt_service_routine = adv76xx_isr,
54450f59 2314#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2315 .g_register = adv76xx_g_register,
2316 .s_register = adv76xx_s_register,
54450f59
HV		 2317#endif
2318};
2319
b44b2e06
PA		 2320static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2321 .s_routing = adv76xx_s_routing,
2322 .g_input_status = adv76xx_g_input_status,
2323 .s_dv_timings = adv76xx_s_dv_timings,
2324 .g_dv_timings = adv76xx_g_dv_timings,
2325 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2326};
2327
b44b2e06
PA		 2328static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2329 .enum_mbus_code = adv76xx_enum_mbus_code,
2330 .get_fmt = adv76xx_get_format,
2331 .set_fmt = adv76xx_set_format,
2332 .get_edid = adv76xx_get_edid,
2333 .set_edid = adv76xx_set_edid,
2334 .dv_timings_cap = adv76xx_dv_timings_cap,
2335 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2336};
2337
b44b2e06
PA		 2338static const struct v4l2_subdev_ops adv76xx_ops = {
2339 .core = &adv76xx_core_ops,
2340 .video = &adv76xx_video_ops,
2341 .pad = &adv76xx_pad_ops,
54450f59
HV		 2342};
2343
2344/* -------------------------- custom ctrls ---------------------------------- */
2345
2346static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2347 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2348 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2349 .name = "Analog Sampling Phase",
2350 .type = V4L2_CTRL_TYPE_INTEGER,
2351 .min = 0,
2352 .max = 0x1f,
2353 .step = 1,
2354 .def = 0,
2355};
2356
b44b2e06
PA		 2357static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2358 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2359 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2360 .name = "Free Running Color, Manual",
2361 .type = V4L2_CTRL_TYPE_BOOLEAN,
2362 .min = false,
2363 .max = true,
2364 .step = 1,
2365 .def = false,
2366};
2367
b44b2e06
PA		 2368static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2369 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2370 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2371 .name = "Free Running Color",
2372 .type = V4L2_CTRL_TYPE_INTEGER,
2373 .min = 0x0,
2374 .max = 0xffffff,
2375 .step = 0x1,
2376 .def = 0x0,
2377};
2378
2379/* ----------------------------------------------------------------------- */
2380
b44b2e06 2381static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2382{
b44b2e06
PA		 2383 struct adv76xx_state *state = to_state(sd);
2384 const struct adv76xx_chip_info *info = state->info;
2385 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2386
2387 hdmi_write(sd, 0x48,
2388 (pdata->disable_pwrdnb ? 0x80 : 0) |
2389 (pdata->disable_cable_det_rst ? 0x40 : 0));
2390
2391 disable_input(sd);
2392
5ef54b59
LP		 2393 if (pdata->default_input >= 0 &&
2394 pdata->default_input < state->source_pad) {
2395 state->selected_input = pdata->default_input;
2396 select_input(sd);
2397 enable_input(sd);
2398 }
2399
54450f59
HV		 2400 /* power */
2401 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2402 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2403 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2404
2405 /* video format */
22d97e56 2406 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2407 pdata->alt_gamma << 3 |
2408 pdata->op_656_range << 2 |
54450f59 2409 pdata->alt_data_sat << 0);
22d97e56 2410 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2411 pdata->insert_av_codes << 2 |
2412 pdata->replicate_av_codes << 1);
b44b2e06 2413 adv76xx_setup_format(state);
54450f59 2414
54450f59 2415 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2416
2417 /* VS, HS polarities */
1b5ab875
LP		 2418 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2419 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2420
2421 /* Adjust drive strength */
2422 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2423 pdata->dr_str_clk << 2 |
2424 pdata->dr_str_sync);
2425
54450f59
HV		 2426 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2427 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2428 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2429 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2430 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2431 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2432 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2433 for digital formats */
2434
5474b983 2435 /* HDMI audio */
22d97e56
LP		 2436 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2437 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2438 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2439
54450f59
HV		 2440 /* TODO from platform data */
2441 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2442
b44b2e06 2443 if (adv76xx_has_afe(state)) {
d42010a1 2444 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2445 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2446 }
54450f59 2447
54450f59 2448 /* interrupts */
d42010a1 2449 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2450 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2451 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2452 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2453 info->setup_irqs(sd);
54450f59
HV		 2454
2455 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2456}
2457
d42010a1
LPC		 2458static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2459{
2460 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2461}
2462
2463static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2464{
2465 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2466}
2467
b44b2e06 2468static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2469{
05cacb17
LP		 2470 unsigned int i;
2471
2472 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2473 if (state->i2c_clients[i])
2474 i2c_unregister_device(state->i2c_clients[i]);
2475 }
54450f59
HV		 2476}
2477
b44b2e06 2478static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2479 u8 addr, u8 io_reg)
2480{
2481 struct i2c_client *client = v4l2_get_subdevdata(sd);
2482
2483 if (addr)
2484 io_write(sd, io_reg, addr << 1);
2485 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2486}
2487
b44b2e06 2488static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2489 /* reset ADI recommended settings for HDMI: */
2490 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2491 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2492 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2493 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2494 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2495 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2496 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2497 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2498 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2499 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2500 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2501 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2502 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2503
2504 /* set ADI recommended settings for digitizer */
2505 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2506 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2507 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2508 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2509 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2510 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2511
b44b2e06 2512 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2513};
2514
b44b2e06 2515static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2516 /* set ADI recommended settings for HDMI: */
2517 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2518 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2519 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2520 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2521 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2522 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2523 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2529
2530 /* reset ADI recommended settings for digitizer */
2531 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2532 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2533 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2534
b44b2e06 2535 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2536};
2537
b44b2e06 2538static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2539 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2540 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2541 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2542 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2543 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2544 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2545 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2546 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2547 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2548 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2549 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2550 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2551
2552 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2553};
2554
b44b2e06 2555static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2556 [ADV7604] = {
2557 .type = ADV7604,
2558 .has_afe = true,
c784b1e2 2559 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2560 .num_dv_ports = 4,
2561 .edid_enable_reg = 0x77,
2562 .edid_status_reg = 0x7d,
2563 .lcf_reg = 0xb3,
2564 .tdms_lock_mask = 0xe0,
2565 .cable_det_mask = 0x1e,
2566 .fmt_change_digital_mask = 0xc1,
80f4944e 2567 .cp_csc = 0xfc,
539b33b0
LP		 2568 .formats = adv7604_formats,
2569 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2570 .set_termination = adv7604_set_termination,
2571 .setup_irqs = adv7604_setup_irqs,
2572 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2573 .read_cable_det = adv7604_read_cable_det,
2574 .recommended_settings = {
2575 [0] = adv7604_recommended_settings_afe,
2576 [1] = adv7604_recommended_settings_hdmi,
2577 },
2578 .num_recommended_settings = {
2579 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2580 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2581 },
b44b2e06
PA		 2582 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2583 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2584 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2585 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2586 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2587 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1 2588 BIT(ADV7604_PAGE_VDP),
5380baaf 2589 .linewidth_mask = 0xfff,
2590 .field0_height_mask = 0xfff,
2591 .field1_height_mask = 0xfff,
2592 .hfrontporch_mask = 0x3ff,
2593 .hsync_mask = 0x3ff,
2594 .hbackporch_mask = 0x3ff,
2595 .field0_vfrontporch_mask = 0x1fff,
2596 .field0_vsync_mask = 0x1fff,
2597 .field0_vbackporch_mask = 0x1fff,
2598 .field1_vfrontporch_mask = 0x1fff,
2599 .field1_vsync_mask = 0x1fff,
2600 .field1_vbackporch_mask = 0x1fff,
d42010a1
LPC		 2601 },
2602 [ADV7611] = {
2603 .type = ADV7611,
2604 .has_afe = false,
b44b2e06 2605 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2606 .num_dv_ports = 1,
2607 .edid_enable_reg = 0x74,
2608 .edid_status_reg = 0x76,
2609 .lcf_reg = 0xa3,
2610 .tdms_lock_mask = 0x43,
2611 .cable_det_mask = 0x01,
2612 .fmt_change_digital_mask = 0x03,
80f4944e 2613 .cp_csc = 0xf4,
539b33b0
LP		 2614 .formats = adv7611_formats,
2615 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2616 .set_termination = adv7611_set_termination,
2617 .setup_irqs = adv7611_setup_irqs,
2618 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2619 .read_cable_det = adv7611_read_cable_det,
2620 .recommended_settings = {
2621 [1] = adv7611_recommended_settings_hdmi,
2622 },
2623 .num_recommended_settings = {
2624 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2625 },
b44b2e06
PA		 2626 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2627 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2628 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2629 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
5380baaf 2630 .linewidth_mask = 0x1fff,
2631 .field0_height_mask = 0x1fff,
2632 .field1_height_mask = 0x1fff,
2633 .hfrontporch_mask = 0x1fff,
2634 .hsync_mask = 0x1fff,
2635 .hbackporch_mask = 0x1fff,
2636 .field0_vfrontporch_mask = 0x3fff,
2637 .field0_vsync_mask = 0x3fff,
2638 .field0_vbackporch_mask = 0x3fff,
2639 .field1_vfrontporch_mask = 0x3fff,
2640 .field1_vsync_mask = 0x3fff,
2641 .field1_vbackporch_mask = 0x3fff,
d42010a1
LPC		 2642 },
2643};
2644
7f099a75 2645static const struct i2c_device_id adv76xx_i2c_id[] = {
b44b2e06
PA		 2646 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2647 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
f82f313e
LP		 2648 { }
2649};
b44b2e06 2650MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2651
7f099a75 2652static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
b44b2e06 2653 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
f82f313e
LP		 2654 { }
2655};
b44b2e06 2656MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2657
b44b2e06 2658static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2659{
6fa88045
LP		 2660 struct v4l2_of_endpoint bus_cfg;
2661 struct device_node *endpoint;
2662 struct device_node *np;
2663 unsigned int flags;
2664
b44b2e06 2665 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2666
2667 /* Parse the endpoint. */
2668 endpoint = of_graph_get_next_endpoint(np, NULL);
2669 if (!endpoint)
2670 return -EINVAL;
2671
2672 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2673 of_node_put(endpoint);
2674
2675 flags = bus_cfg.bus.parallel.flags;
2676
2677 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2678 state->pdata.inv_hs_pol = 1;
2679
2680 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2681 state->pdata.inv_vs_pol = 1;
2682
2683 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2684 state->pdata.inv_llc_pol = 1;
2685
2686 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2687 state->pdata.insert_av_codes = 1;
2688 state->pdata.op_656_range = 1;
2689 }
2690
f82f313e 2691 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2692 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2693
2694 /* Use the default I2C addresses. */
2695 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2696 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2697 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2698 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2699 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2700 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2701 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2702 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2703 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2704 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2705 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2706 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2707
2708 /* Hardcode the remaining platform data fields. */
2709 state->pdata.disable_pwrdnb = 0;
2710 state->pdata.disable_cable_det_rst = 0;
2711 state->pdata.default_input = -1;
2712 state->pdata.blank_data = 1;
f82f313e 2713 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2714 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2715 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2716
2717 return 0;
2718}
2719
b44b2e06 2720static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 2721 const struct i2c_device_id *id)
2722{
591b72fe
HV		 2723 static const struct v4l2_dv_timings cea640x480 =
2724 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 2725 struct adv76xx_state *state;
54450f59
HV		 2726 struct v4l2_ctrl_handler *hdl;
2727 struct v4l2_subdev *sd;
c784b1e2 2728 unsigned int i;
d42010a1 2729 u16 val;
54450f59
HV		 2730 int err;
2731
2732 /* Check if the adapter supports the needed features */
2733 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2734 return -EIO;
b44b2e06 2735 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 2736 client->addr << 1);
2737
c02b211d 2738 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 2739 if (!state) {
b44b2e06 2740 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 2741 return -ENOMEM;
2742 }
2743
b44b2e06 2744 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 2745
25a64ac9
MR		 2746 /* initialize variables */
2747 state->restart_stdi_once = true;
ff4f80fd 2748 state->selected_input = ~0;
25a64ac9 2749
f82f313e
LP		 2750 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2751 const struct of_device_id *oid;
2752
b44b2e06 2753 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 2754 state->info = oid->data;
2755
b44b2e06 2756 err = adv76xx_parse_dt(state);
f82f313e
LP		 2757 if (err < 0) {
2758 v4l_err(client, "DT parsing error\n");
2759 return err;
2760 }
2761 } else if (client->dev.platform_data) {
b44b2e06 2762 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 2763
b44b2e06 2764 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 2765 state->pdata = *pdata;
2766 } else {
54450f59 2767 v4l_err(client, "No platform data!\n");
c02b211d 2768 return -ENODEV;
54450f59 2769 }
e9d50e9e
LP		 2770
2771 /* Request GPIOs. */
2772 for (i = 0; i < state->info->num_dv_ports; ++i) {
2773 state->hpd_gpio[i] =
269bd132
UKK		 2774 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2775 GPIOD_OUT_LOW);
e9d50e9e 2776 if (IS_ERR(state->hpd_gpio[i]))
269bd132 2777 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 2778
269bd132
UKK		 2779 if (state->hpd_gpio[i])
2780 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e
LP		 2781 }
2782
591b72fe 2783 state->timings = cea640x480;
b44b2e06 2784 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 2785
2786 sd = &state->sd;
b44b2e06 2787 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 2788 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2789 id->name, i2c_adapter_id(client->adapter),
2790 client->addr);
54450f59 2791 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59 2792
d42010a1
LPC		 2793 /*
2794 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2795 * identifies the revision, while on ADV7611 it identifies the model as
2796 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2797 */
2798 if (state->info->type == ADV7604) {
2799 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2800 if (val != 0x68) {
2801 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2802 client->addr << 1);
2803 return -ENODEV;
2804 }
2805 } else {
2806 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2807 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2808 if (val != 0x2051) {
2809 v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2810 client->addr << 1);
2811 return -ENODEV;
2812 }
54450f59
HV		 2813 }
2814
2815 /* control handlers */
2816 hdl = &state->hdl;
b44b2e06 2817 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 2818
b44b2e06 2819 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 2820 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 2821 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 2822 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 2823 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 2824 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 2825 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 2826 V4L2_CID_HUE, 0, 128, 1, 0);
2827
2828 /* private controls */
2829 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 2830 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2831 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 2832 state->rgb_quantization_range_ctrl =
b44b2e06 2833 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 2834 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2835 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2836
2837 /* custom controls */
b44b2e06 2838 if (adv76xx_has_afe(state))
d42010a1
LPC		 2839 state->analog_sampling_phase_ctrl =
2840 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 2841 state->free_run_color_manual_ctrl =
b44b2e06 2842 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 2843 state->free_run_color_ctrl =
b44b2e06 2844 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 2845
2846 sd->ctrl_handler = hdl;
2847 if (hdl->error) {
2848 err = hdl->error;
2849 goto err_hdl;
2850 }
8c0eadb8
HV		 2851 state->detect_tx_5v_ctrl->is_private = true;
2852 state->rgb_quantization_range_ctrl->is_private = true;
b44b2e06 2853 if (adv76xx_has_afe(state))
d42010a1 2854 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 2855 state->free_run_color_manual_ctrl->is_private = true;
2856 state->free_run_color_ctrl->is_private = true;
2857
b44b2e06 2858 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 2859 err = -ENODEV;
2860 goto err_hdl;
2861 }
2862
b44b2e06 2863 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 2864 if (!(BIT(i) & state->info->page_mask))
2865 continue;
54450f59 2866
05cacb17 2867 state->i2c_clients[i] =
b44b2e06 2868 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 2869 0xf2 + i);
2870 if (state->i2c_clients[i] == NULL) {
d42010a1 2871 err = -ENOMEM;
05cacb17 2872 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 2873 goto err_i2c;
2874 }
2875 }
05cacb17 2876
54450f59
HV		 2877 /* work queues */
2878 state->work_queues = create_singlethread_workqueue(client->name);
2879 if (!state->work_queues) {
2880 v4l2_err(sd, "Could not create work queue\n");
2881 err = -ENOMEM;
2882 goto err_i2c;
2883 }
2884
2885 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 2886 adv76xx_delayed_work_enable_hotplug);
54450f59 2887
c784b1e2
LP		 2888 state->source_pad = state->info->num_dv_ports
2889 + (state->info->has_afe ? 2 : 0);
2890 for (i = 0; i < state->source_pad; ++i)
2891 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2892 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2893
2894 err = media_entity_init(&sd->entity, state->source_pad + 1,
2895 state->pads, 0);
54450f59
HV		 2896 if (err)
2897 goto err_work_queues;
2898
b44b2e06 2899 err = adv76xx_core_init(sd);
54450f59
HV		 2900 if (err)
2901 goto err_entity;
2902 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2903 client->addr << 1, client->adapter->name);
bedc3939
LPC		 2904
2905 err = v4l2_async_register_subdev(sd);
2906 if (err)
2907 goto err_entity;
2908
54450f59
HV		 2909 return 0;
2910
2911err_entity:
2912 media_entity_cleanup(&sd->entity);
2913err_work_queues:
2914 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2915 destroy_workqueue(state->work_queues);
2916err_i2c:
b44b2e06 2917 adv76xx_unregister_clients(state);
54450f59
HV		 2918err_hdl:
2919 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2920 return err;
2921}
2922
2923/* ----------------------------------------------------------------------- */
2924
b44b2e06 2925static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 2926{
2927 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 2928 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 2929
2930 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2931 destroy_workqueue(state->work_queues);
bedc3939 2932 v4l2_async_unregister_subdev(sd);
54450f59 2933 media_entity_cleanup(&sd->entity);
b44b2e06 2934 adv76xx_unregister_clients(to_state(sd));
54450f59 2935 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2936 return 0;
2937}
2938
2939/* ----------------------------------------------------------------------- */
2940
b44b2e06 2941static struct i2c_driver adv76xx_driver = {
54450f59
HV		 2942 .driver = {
2943 .owner = THIS_MODULE,
2944 .name = "adv7604",
b44b2e06 2945 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 2946 },
b44b2e06
PA		 2947 .probe = adv76xx_probe,
2948 .remove = adv76xx_remove,
2949 .id_table = adv76xx_i2c_id,
54450f59
HV		 2950};
2951
b44b2e06 2952module_i2c_driver(adv76xx_driver);
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