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[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
516613c1 32#include <linux/hdmi.h>
c72a53ce 33#include <linux/i2c.h>
54450f59
HV		 34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
c72a53ce 37#include <linux/v4l2-dv-timings.h>
54450f59
HV		 38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
f862f57d 40#include <linux/regmap.h>
c72a53ce 41
b5dcee22 42#include <media/i2c/adv7604.h>
54450f59 43#include <media/v4l2-ctrls.h>
c72a53ce 44#include <media/v4l2-device.h>
0975626d 45#include <media/v4l2-event.h>
25764158 46#include <media/v4l2-dv-timings.h>
6fa88045 47#include <media/v4l2-of.h>
54450f59
HV		 48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
54MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
56MODULE_LICENSE("GPL");
57
58/* ADV7604 system clock frequency */
b44b2e06 59#define ADV76XX_FSC (28636360)
54450f59 60
b44b2e06 61#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 62
b44b2e06 63#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 64#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 65#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 66
b44b2e06 67#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 68#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 69#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 70#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 71#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 72#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
73
b44b2e06
PA		 74#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
75#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
76#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
77#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
78#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
79#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 80
b44b2e06 81#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 82
b44b2e06 83enum adv76xx_type {
d42010a1
LPC		 84 ADV7604,
85 ADV7611,
8331d30b 86 ADV7612,
d42010a1
LPC		 87};
88
b44b2e06 89struct adv76xx_reg_seq {
d42010a1
LPC		 90 unsigned int reg;
91 u8 val;
92};
93
b44b2e06 94struct adv76xx_format_info {
f5fe58fd 95 u32 code;
539b33b0
LP		 96 u8 op_ch_sel;
97 bool rgb_out;
98 bool swap_cb_cr;
99 u8 op_format_sel;
100};
101
516613c1
HV		 102struct adv76xx_cfg_read_infoframe {
103 const char *desc;
104 u8 present_mask;
105 u8 head_addr;
106 u8 payload_addr;
107};
108
b44b2e06
PA		 109struct adv76xx_chip_info {
110 enum adv76xx_type type;
d42010a1
LPC		 111
112 bool has_afe;
113 unsigned int max_port;
114 unsigned int num_dv_ports;
115
116 unsigned int edid_enable_reg;
117 unsigned int edid_status_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
80f4944e 123 unsigned int cp_csc;
d42010a1 124
b44b2e06 125 const struct adv76xx_format_info *formats;
539b33b0
LP		 126 unsigned int nformats;
127
d42010a1
LPC		 128 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
129 void (*setup_irqs)(struct v4l2_subdev *sd);
130 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
131 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
132
133 /* 0 = AFE, 1 = HDMI */
b44b2e06 134 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 135 unsigned int num_recommended_settings[2];
136
137 unsigned long page_mask;
5380baaf 138
139 /* Masks for timings */
140 unsigned int linewidth_mask;
141 unsigned int field0_height_mask;
142 unsigned int field1_height_mask;
143 unsigned int hfrontporch_mask;
144 unsigned int hsync_mask;
145 unsigned int hbackporch_mask;
146 unsigned int field0_vfrontporch_mask;
147 unsigned int field1_vfrontporch_mask;
148 unsigned int field0_vsync_mask;
149 unsigned int field1_vsync_mask;
150 unsigned int field0_vbackporch_mask;
151 unsigned int field1_vbackporch_mask;
d42010a1
LPC		 152};
153
54450f59
HV		 154/*
155 **********************************************************************
156 *
157 * Arrays with configuration parameters for the ADV7604
158 *
159 **********************************************************************
160 */
c784b1e2 161
b44b2e06
PA		 162struct adv76xx_state {
163 const struct adv76xx_chip_info *info;
164 struct adv76xx_platform_data pdata;
539b33b0 165
e9d50e9e
LP		 166 struct gpio_desc *hpd_gpio[4];
167
54450f59 168 struct v4l2_subdev sd;
b44b2e06 169 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 170 unsigned int source_pad;
539b33b0 171
54450f59 172 struct v4l2_ctrl_handler hdl;
539b33b0 173
b44b2e06 174 enum adv76xx_pad selected_input;
539b33b0 175
54450f59 176 struct v4l2_dv_timings timings;
b44b2e06 177 const struct adv76xx_format_info *format;
539b33b0 178
4a31a93a
MR		 179 struct {
180 u8 edid[256];
181 u32 present;
182 unsigned blocks;
183 } edid;
dd08beb9 184 u16 spa_port_a[2];
54450f59
HV		 185 struct v4l2_fract aspect_ratio;
186 u32 rgb_quantization_range;
54450f59 187 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 188 bool restart_stdi_once;
54450f59
HV		 189
190 /* i2c clients */
b44b2e06 191 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59 192
f862f57d
PA		 193 /* Regmaps */
194 struct regmap *regmap[ADV76XX_PAGE_MAX];
195
54450f59
HV		 196 /* controls */
197 struct v4l2_ctrl *detect_tx_5v_ctrl;
198 struct v4l2_ctrl *analog_sampling_phase_ctrl;
199 struct v4l2_ctrl *free_run_color_manual_ctrl;
200 struct v4l2_ctrl *free_run_color_ctrl;
201 struct v4l2_ctrl *rgb_quantization_range_ctrl;
202};
203
b44b2e06 204static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 205{
206 return state->info->has_afe;
207}
208
bd3e275f
JMH		 209/* Unsupported timings. This device cannot support 720p30. */
210static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
211 V4L2_DV_BT_CEA_1280X720P30,
212 { }
54450f59
HV		 213};
214
bd3e275f
JMH		 215static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
216{
217 int i;
218
219 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
220 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
221 return false;
222 return true;
223}
224
b44b2e06 225struct adv76xx_video_standards {
ccbd5bc4
HV		 226 struct v4l2_dv_timings timings;
227 u8 vid_std;
228 u8 v_freq;
229};
230
231/* sorted by number of lines */
b44b2e06 232static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 233 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
234 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
235 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
236 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
237 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
238 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
239 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
240 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
241 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
242 /* TODO add 1920x1080P60_RB (CVT timing) */
243 { },
244};
245
246/* sorted by number of lines */
b44b2e06 247static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 248 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
249 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
250 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
251 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
252 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
253 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
254 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
255 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
256 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
257 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
258 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
259 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
260 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
261 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
262 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
263 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
264 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
265 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
266 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
267 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
268 /* TODO add 1600X1200P60_RB (not a DMT timing) */
269 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
270 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
271 { },
272};
273
274/* sorted by number of lines */
b44b2e06 275static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 276 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
277 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
278 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
279 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
280 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
281 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
282 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
283 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
284 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
285 { },
286};
287
288/* sorted by number of lines */
b44b2e06 289static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 290 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
291 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
292 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
293 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
294 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
295 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
296 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
297 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
298 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
299 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
300 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
301 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
302 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
303 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
304 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
305 { },
306};
307
48519838
HV		 308static const struct v4l2_event adv76xx_ev_fmt = {
309 .type = V4L2_EVENT_SOURCE_CHANGE,
310 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
311};
312
54450f59
HV		 313/* ----------------------------------------------------------------------- */
314
b44b2e06 315static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 316{
b44b2e06 317 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 318}
319
54450f59
HV		 320static inline unsigned htotal(const struct v4l2_bt_timings *t)
321{
eacf8f9a 322 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 323}
324
54450f59
HV		 325static inline unsigned vtotal(const struct v4l2_bt_timings *t)
326{
eacf8f9a 327 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 328}
329
330/* ----------------------------------------------------------------------- */
331
f862f57d
PA		 332static int adv76xx_read_check(struct adv76xx_state *state,
333 int client_page, u8 reg)
54450f59 334{
f862f57d 335 struct i2c_client *client = state->i2c_clients[client_page];
54450f59 336 int err;
f862f57d 337 unsigned int val;
54450f59 338
f862f57d
PA		 339 err = regmap_read(state->regmap[client_page], reg, &val);
340
341 if (err) {
342 v4l_err(client, "error reading %02x, %02x\n",
343 client->addr, reg);
344 return err;
54450f59 345 }
f862f57d 346 return val;
54450f59
HV		 347}
348
f862f57d
PA		 349/* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
350 * size to one or more registers.
351 *
352 * A value of zero will be returned on success, a negative errno will
353 * be returned in error cases.
354 */
355static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
356 unsigned int init_reg, const void *val,
357 size_t val_len)
54450f59 358{
f862f57d
PA		 359 struct regmap *regmap = state->regmap[client_page];
360
361 if (val_len > I2C_SMBUS_BLOCK_MAX)
362 val_len = I2C_SMBUS_BLOCK_MAX;
54450f59 363
f862f57d 364 return regmap_raw_write(regmap, init_reg, val, val_len);
54450f59
HV		 365}
366
367/* ----------------------------------------------------------------------- */
368
369static inline int io_read(struct v4l2_subdev *sd, u8 reg)
370{
b44b2e06 371 struct adv76xx_state *state = to_state(sd);
54450f59 372
f862f57d 373 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 374}
375
376static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
377{
b44b2e06 378 struct adv76xx_state *state = to_state(sd);
54450f59 379
f862f57d 380 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
54450f59
HV		 381}
382
22d97e56 383static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 384{
22d97e56 385 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 386}
387
388static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
389{
b44b2e06 390 struct adv76xx_state *state = to_state(sd);
54450f59 391
f862f57d 392 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 393}
394
395static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
396{
b44b2e06 397 struct adv76xx_state *state = to_state(sd);
54450f59 398
f862f57d 399 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
54450f59
HV		 400}
401
402static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
403{
b44b2e06 404 struct adv76xx_state *state = to_state(sd);
54450f59 405
f862f57d 406 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 407}
408
409static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
410{
b44b2e06 411 struct adv76xx_state *state = to_state(sd);
54450f59 412
f862f57d 413 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
54450f59
HV		 414}
415
54450f59
HV		 416static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
417{
b44b2e06 418 struct adv76xx_state *state = to_state(sd);
54450f59 419
f862f57d 420 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 421}
422
423static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
424{
b44b2e06 425 struct adv76xx_state *state = to_state(sd);
54450f59 426
f862f57d 427 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
54450f59
HV		 428}
429
54450f59
HV		 430static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
431{
b44b2e06 432 struct adv76xx_state *state = to_state(sd);
54450f59 433
f862f57d 434 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 435}
436
437static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
438{
b44b2e06 439 struct adv76xx_state *state = to_state(sd);
54450f59 440
f862f57d 441 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
54450f59
HV		 442}
443
444static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
445{
b44b2e06 446 struct adv76xx_state *state = to_state(sd);
54450f59 447
f862f57d 448 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 449}
450
451static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
452{
b44b2e06 453 struct adv76xx_state *state = to_state(sd);
54450f59 454
f862f57d 455 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
54450f59
HV		 456}
457
22d97e56 458static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 459{
22d97e56 460 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 461}
462
463static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
464{
b44b2e06 465 struct adv76xx_state *state = to_state(sd);
54450f59 466
f862f57d 467 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 468}
469
470static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
471{
b44b2e06 472 struct adv76xx_state *state = to_state(sd);
54450f59 473
f862f57d 474 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
54450f59
HV		 475}
476
54450f59 477static inline int edid_write_block(struct v4l2_subdev *sd,
f862f57d 478 unsigned int total_len, const u8 *val)
54450f59 479{
b44b2e06 480 struct adv76xx_state *state = to_state(sd);
54450f59 481 int err = 0;
f862f57d
PA		 482 int i = 0;
483 int len = 0;
54450f59 484
f862f57d
PA		 485 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
486 __func__, total_len);
487
488 while (!err && i < total_len) {
489 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
490 I2C_SMBUS_BLOCK_MAX :
491 (total_len - i);
492
493 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
494 i, val + i, len);
495 i += len;
496 }
54450f59 497
dd08beb9
MR		 498 return err;
499}
54450f59 500
b44b2e06 501static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 502{
503 unsigned int i;
504
269bd132 505 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 506 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 507
b44b2e06 508 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 509}
510
b44b2e06 511static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 512{
513 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 514 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 515 delayed_work_enable_hotplug);
516 struct v4l2_subdev *sd = &state->sd;
54450f59 517
dd08beb9 518 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 519
b44b2e06 520 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 521}
522
523static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
524{
b44b2e06 525 struct adv76xx_state *state = to_state(sd);
54450f59 526
f862f57d 527 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 528}
529
51182a94
LP		 530static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
531{
532 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
533}
534
54450f59
HV		 535static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
536{
b44b2e06 537 struct adv76xx_state *state = to_state(sd);
54450f59 538
f862f57d 539 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
54450f59
HV		 540}
541
22d97e56 542static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 543{
22d97e56 544 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 545}
546
54450f59
HV		 547static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
548{
b44b2e06 549 struct adv76xx_state *state = to_state(sd);
54450f59 550
f862f57d 551 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
54450f59
HV		 552}
553
554static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
555{
b44b2e06 556 struct adv76xx_state *state = to_state(sd);
54450f59 557
f862f57d 558 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 559}
560
51182a94
LP		 561static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
562{
563 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
564}
565
54450f59
HV		 566static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
567{
b44b2e06 568 struct adv76xx_state *state = to_state(sd);
54450f59 569
f862f57d 570 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
54450f59
HV		 571}
572
22d97e56 573static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 574{
22d97e56 575 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 576}
577
578static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
579{
b44b2e06 580 struct adv76xx_state *state = to_state(sd);
54450f59 581
f862f57d 582 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 583}
584
585static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
586{
b44b2e06 587 struct adv76xx_state *state = to_state(sd);
54450f59 588
f862f57d 589 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
05cacb17 590}
d42010a1 591
b44b2e06
PA		 592#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
593#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 594
595#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 596static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 597{
b44b2e06 598 struct adv76xx_state *state = to_state(sd);
d42010a1 599 unsigned int page = reg >> 8;
f862f57d
PA		 600 unsigned int val;
601 int err;
d42010a1
LPC		 602
603 if (!(BIT(page) & state->info->page_mask))
604 return -EINVAL;
605
606 reg &= 0xff;
f862f57d 607 err = regmap_read(state->regmap[page], reg, &val);
d42010a1 608
f862f57d 609 return err ? err : val;
d42010a1
LPC		 610}
611#endif
612
b44b2e06 613static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 614{
b44b2e06 615 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 616 unsigned int page = reg >> 8;
617
618 if (!(BIT(page) & state->info->page_mask))
619 return -EINVAL;
620
621 reg &= 0xff;
622
f862f57d 623 return regmap_write(state->regmap[page], reg, val);
d42010a1
LPC		 624}
625
b44b2e06
PA		 626static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
627 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 628{
629 unsigned int i;
630
b44b2e06
PA		 631 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
632 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 633}
634
539b33b0
LP		 635/* -----------------------------------------------------------------------------
636 * Format helpers
637 */
638
b44b2e06
PA		 639static const struct adv76xx_format_info adv7604_formats[] = {
640 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
641 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
642 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
643 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
644 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
645 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
646 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
647 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
648 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
649 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
650 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
651 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
652 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
653 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
654 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
655 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
656 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
657 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
658 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
659 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
660 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
661 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
662 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
663 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
664 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
665 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
666 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
667 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
668 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
669 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
670 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
671 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
672 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
673 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
674 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
675 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
676 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
677 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 678};
679
b44b2e06
PA		 680static const struct adv76xx_format_info adv7611_formats[] = {
681 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
682 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
683 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
684 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
685 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
686 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
687 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
688 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
689 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
690 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
691 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
693 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
695 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
697 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
699 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
701 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
703 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
705 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 707};
708
8331d30b
WT		 709static const struct adv76xx_format_info adv7612_formats[] = {
710 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
711 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
712 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
713 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
714 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
715 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
716 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
718 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
720 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
722 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
724};
725
b44b2e06
PA		 726static const struct adv76xx_format_info *
727adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 728{
729 unsigned int i;
730
731 for (i = 0; i < state->info->nformats; ++i) {
732 if (state->info->formats[i].code == code)
733 return &state->info->formats[i];
734 }
735
736 return NULL;
737}
738
54450f59
HV		 739/* ----------------------------------------------------------------------- */
740
4a31a93a
MR		 741static inline bool is_analog_input(struct v4l2_subdev *sd)
742{
b44b2e06 743 struct adv76xx_state *state = to_state(sd);
4a31a93a 744
c784b1e2
LP		 745 return state->selected_input == ADV7604_PAD_VGA_RGB ||
746 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 747}
748
749static inline bool is_digital_input(struct v4l2_subdev *sd)
750{
b44b2e06 751 struct adv76xx_state *state = to_state(sd);
4a31a93a 752
b44b2e06 753 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 754 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
755 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
756 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 757}
758
bd3e275f
JMH		 759static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
760 .type = V4L2_DV_BT_656_1120,
761 /* keep this initialization for compatibility with GCC < 4.4.6 */
762 .reserved = { 0 },
763 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
764 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
765 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
766 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
767 V4L2_DV_BT_CAP_CUSTOM)
768};
769
770static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
771 .type = V4L2_DV_BT_656_1120,
772 /* keep this initialization for compatibility with GCC < 4.4.6 */
773 .reserved = { 0 },
774 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
775 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
776 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
777 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
778 V4L2_DV_BT_CAP_CUSTOM)
779};
780
9c41e690
LP		 781/*
782 * Return the DV timings capabilities for the requested sink pad. As a special
783 * case, pad value -1 returns the capabilities for the currently selected input.
784 */
785static const struct v4l2_dv_timings_cap *
786adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
bd3e275f 787{
9c41e690
LP		 788 if (pad == -1) {
789 struct adv76xx_state *state = to_state(sd);
790
791 pad = state->selected_input;
792 }
793
794 switch (pad) {
795 case ADV76XX_PAD_HDMI_PORT_A:
796 case ADV7604_PAD_HDMI_PORT_B:
797 case ADV7604_PAD_HDMI_PORT_C:
798 case ADV7604_PAD_HDMI_PORT_D:
799 return &adv76xx_timings_cap_digital;
800
801 case ADV7604_PAD_VGA_RGB:
802 case ADV7604_PAD_VGA_COMP:
803 default:
804 return &adv7604_timings_cap_analog;
805 }
bd3e275f
JMH		 806}
807
808
4a31a93a
MR		 809/* ----------------------------------------------------------------------- */
810
54450f59 811#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 812static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 813{
814 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
815 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
816 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
817 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
818 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
819 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
820 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
821 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
822 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
823 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
824 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
825 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
826 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
827}
828
b44b2e06 829static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 830 struct v4l2_dbg_register *reg)
831{
d42010a1
LPC		 832 int ret;
833
b44b2e06 834 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 835 if (ret < 0) {
54450f59 836 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 837 adv76xx_inv_register(sd);
d42010a1 838 return ret;
54450f59 839 }
d42010a1
LPC		 840
841 reg->size = 1;
842 reg->val = ret;
843
54450f59
HV		 844 return 0;
845}
846
b44b2e06 847static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 848 const struct v4l2_dbg_register *reg)
54450f59 849{
d42010a1 850 int ret;
1577461b 851
b44b2e06 852 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 853 if (ret < 0) {
54450f59 854 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 855 adv76xx_inv_register(sd);
d42010a1 856 return ret;
54450f59 857 }
d42010a1 858
54450f59
HV		 859 return 0;
860}
861#endif
862
d42010a1
LPC		 863static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
864{
865 u8 value = io_read(sd, 0x6f);
866
867 return ((value & 0x10) >> 4)
868 | ((value & 0x08) >> 2)
869 | ((value & 0x04) << 0)
870 | ((value & 0x02) << 2);
871}
872
873static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
874{
875 u8 value = io_read(sd, 0x6f);
876
877 return value & 1;
878}
879
7111cddd
WT		 880static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
881{
882 /* Reads CABLE_DET_A_RAW. For input B support, need to
883 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
884 */
885 u8 value = io_read(sd, 0x6f);
886
887 return value & 1;
888}
889
b44b2e06 890static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 891{
b44b2e06
PA		 892 struct adv76xx_state *state = to_state(sd);
893 const struct adv76xx_chip_info *info = state->info;
54450f59 894
54450f59 895 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 896 info->read_cable_det(sd));
54450f59
HV		 897}
898
ccbd5bc4
HV		 899static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
900 u8 prim_mode,
b44b2e06 901 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 902 const struct v4l2_dv_timings *timings)
903{
ccbd5bc4
HV		 904 int i;
905
906 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 907 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
85f9e06c 908 is_digital_input(sd) ? 250000 : 1000000, false))
ccbd5bc4
HV		 909 continue;
910 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
911 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
912 prim_mode); /* v_freq and prim mode */
913 return 0;
914 }
915
916 return -1;
917}
918
919static int configure_predefined_video_timings(struct v4l2_subdev *sd,
920 struct v4l2_dv_timings *timings)
54450f59 921{
b44b2e06 922 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 923 int err;
924
925 v4l2_dbg(1, debug, sd, "%s", __func__);
926
b44b2e06 927 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 928 /* reset to default values */
929 io_write(sd, 0x16, 0x43);
930 io_write(sd, 0x17, 0x5a);
931 }
ccbd5bc4 932 /* disable embedded syncs for auto graphics mode */
22d97e56 933 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 934 cp_write(sd, 0x8f, 0x00);
935 cp_write(sd, 0x90, 0x00);
936 cp_write(sd, 0xa2, 0x00);
937 cp_write(sd, 0xa3, 0x00);
938 cp_write(sd, 0xa4, 0x00);
939 cp_write(sd, 0xa5, 0x00);
940 cp_write(sd, 0xa6, 0x00);
941 cp_write(sd, 0xa7, 0x00);
942 cp_write(sd, 0xab, 0x00);
943 cp_write(sd, 0xac, 0x00);
944
4a31a93a 945 if (is_analog_input(sd)) {
ccbd5bc4
HV		 946 err = find_and_set_predefined_video_timings(sd,
947 0x01, adv7604_prim_mode_comp, timings);
948 if (err)
949 err = find_and_set_predefined_video_timings(sd,
950 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 951 } else if (is_digital_input(sd)) {
ccbd5bc4 952 err = find_and_set_predefined_video_timings(sd,
b44b2e06 953 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 954 if (err)
955 err = find_and_set_predefined_video_timings(sd,
b44b2e06 956 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 957 } else {
958 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
959 __func__, state->selected_input);
ccbd5bc4 960 err = -1;
ccbd5bc4
HV		 961 }
962
963
964 return err;
965}
966
967static void configure_custom_video_timings(struct v4l2_subdev *sd,
968 const struct v4l2_bt_timings *bt)
969{
b44b2e06 970 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 971 u32 width = htotal(bt);
972 u32 height = vtotal(bt);
973 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
974 u16 cp_start_eav = width - bt->hfrontporch;
975 u16 cp_start_vbi = height - bt->vfrontporch;
976 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
977 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 978 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 979 const u8 pll[2] = {
980 0xc0 | ((width >> 8) & 0x1f),
981 width & 0xff
982 };
54450f59
HV		 983
984 v4l2_dbg(2, debug, sd, "%s\n", __func__);
985
4a31a93a 986 if (is_analog_input(sd)) {
ccbd5bc4
HV		 987 /* auto graphics */
988 io_write(sd, 0x00, 0x07); /* video std */
989 io_write(sd, 0x01, 0x02); /* prim mode */
990 /* enable embedded syncs for auto graphics mode */
22d97e56 991 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 992
ccbd5bc4 993 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 994 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
995 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
f862f57d
PA		 996 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
997 0x16, pll, 2))
54450f59 998 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 999
1000 /* active video - horizontal timing */
54450f59 1001 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 1002 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 1003 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 1004 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1005
1006 /* active video - vertical timing */
54450f59 1007 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 1008 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 1009 ((cp_end_vbi >> 8) & 0xf));
54450f59 1010 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 1011 } else if (is_digital_input(sd)) {
ccbd5bc4 1012 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1013 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 1014 io_write(sd, 0x00, 0x02); /* video std */
1015 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 1016 } else {
1017 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1018 __func__, state->selected_input);
54450f59 1019 }
54450f59 1020
ccbd5bc4
HV		 1021 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1022 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1023 cp_write(sd, 0xab, (height >> 4) & 0xff);
1024 cp_write(sd, 0xac, (height & 0x0f) << 4);
1025}
54450f59 1026
b44b2e06 1027static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 1028{
b44b2e06 1029 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1030 u8 offset_buf[4];
1031
1032 if (auto_offset) {
1033 offset_a = 0x3ff;
1034 offset_b = 0x3ff;
1035 offset_c = 0x3ff;
1036 }
1037
1038 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1039 __func__, auto_offset ? "Auto" : "Manual",
1040 offset_a, offset_b, offset_c);
1041
1042 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1043 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1044 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1045 offset_buf[3] = offset_c & 0x0ff;
1046
1047 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1048 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1049 0x77, offset_buf, 4))
5c6c6349
MR		 1050 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1051}
1052
b44b2e06 1053static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1054{
b44b2e06 1055 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1056 u8 gain_buf[4];
1057 u8 gain_man = 1;
1058 u8 agc_mode_man = 1;
1059
1060 if (auto_gain) {
1061 gain_man = 0;
1062 agc_mode_man = 0;
1063 gain_a = 0x100;
1064 gain_b = 0x100;
1065 gain_c = 0x100;
1066 }
1067
1068 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1069 __func__, auto_gain ? "Auto" : "Manual",
1070 gain_a, gain_b, gain_c);
1071
1072 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1073 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1074 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1075 gain_buf[3] = ((gain_c & 0x0ff));
1076
1077 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1078 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1079 0x73, gain_buf, 4))
5c6c6349
MR		 1080 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1081}
1082
54450f59
HV		 1083static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1084{
b44b2e06 1085 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1086 bool rgb_output = io_read(sd, 0x02) & 0x02;
1087 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1088
1089 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1090 __func__, state->rgb_quantization_range,
1091 rgb_output, hdmi_signal);
54450f59 1092
b44b2e06
PA		 1093 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1094 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1095
54450f59
HV		 1096 switch (state->rgb_quantization_range) {
1097 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1098 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1099 /* Receiving analog RGB signal
1100 * Set RGB full range (0-255) */
22d97e56 1101 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1102 break;
1103 }
1104
c784b1e2 1105 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1106 /* Receiving analog YPbPr signal
1107 * Set automode */
22d97e56 1108 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1109 break;
1110 }
1111
5c6c6349 1112 if (hdmi_signal) {
9833239e
MR		 1113 /* Receiving HDMI signal
1114 * Set automode */
22d97e56 1115 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1116 break;
1117 }
1118
1119 /* Receiving DVI-D signal
1120 * ADV7604 selects RGB limited range regardless of
1121 * input format (CE/IT) in automatic mode */
680fee04 1122 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
9833239e 1123 /* RGB limited range (16-235) */
22d97e56 1124 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1125 } else {
1126 /* RGB full range (0-255) */
22d97e56 1127 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1128
1129 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1130 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1131 } else {
b44b2e06
PA		 1132 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1133 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1134 }
54450f59
HV		 1135 }
1136 break;
1137 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1138 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1139 /* YCrCb limited range (16-235) */
22d97e56 1140 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1141 break;
d261e842 1142 }
5c6c6349
MR		 1143
1144 /* RGB limited range (16-235) */
22d97e56 1145 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1146
54450f59
HV		 1147 break;
1148 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1149 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1150 /* YCrCb full range (0-255) */
22d97e56 1151 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1152 break;
1153 }
1154
1155 /* RGB full range (0-255) */
22d97e56 1156 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1157
1158 if (is_analog_input(sd) || hdmi_signal)
1159 break;
1160
1161 /* Adjust gain/offset for DVI-D signals only */
1162 if (rgb_output) {
b44b2e06 1163 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1164 } else {
b44b2e06
PA		 1165 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1166 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1167 }
54450f59
HV		 1168 break;
1169 }
1170}
1171
b44b2e06 1172static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1173{
c269887c 1174 struct v4l2_subdev *sd =
b44b2e06 1175 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1176
b44b2e06 1177 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1178
1179 switch (ctrl->id) {
1180 case V4L2_CID_BRIGHTNESS:
1181 cp_write(sd, 0x3c, ctrl->val);
1182 return 0;
1183 case V4L2_CID_CONTRAST:
1184 cp_write(sd, 0x3a, ctrl->val);
1185 return 0;
1186 case V4L2_CID_SATURATION:
1187 cp_write(sd, 0x3b, ctrl->val);
1188 return 0;
1189 case V4L2_CID_HUE:
1190 cp_write(sd, 0x3d, ctrl->val);
1191 return 0;
1192 case V4L2_CID_DV_RX_RGB_RANGE:
1193 state->rgb_quantization_range = ctrl->val;
1194 set_rgb_quantization_range(sd);
1195 return 0;
1196 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1197 if (!adv76xx_has_afe(state))
d42010a1 1198 return -EINVAL;
54450f59
HV		 1199 /* Set the analog sampling phase. This is needed to find the
1200 best sampling phase for analog video: an application or
1201 driver has to try a number of phases and analyze the picture
1202 quality before settling on the best performing phase. */
1203 afe_write(sd, 0xc8, ctrl->val);
1204 return 0;
1205 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1206 /* Use the default blue color for free running mode,
1207 or supply your own. */
22d97e56 1208 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1209 return 0;
1210 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1211 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1212 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1213 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1214 return 0;
1215 }
1216 return -EINVAL;
1217}
1218
297a4144
HV		 1219static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1220{
1221 struct v4l2_subdev *sd =
1222 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1223
1224 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1225 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1226 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1227 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1228 return 0;
1229 }
1230 return -EINVAL;
1231}
1232
54450f59
HV		 1233/* ----------------------------------------------------------------------- */
1234
1235static inline bool no_power(struct v4l2_subdev *sd)
1236{
1237 /* Entire chip or CP powered off */
1238 return io_read(sd, 0x0c) & 0x24;
1239}
1240
1241static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1242{
b44b2e06 1243 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1244
1245 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1246}
1247
1248static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1249{
b44b2e06
PA		 1250 struct adv76xx_state *state = to_state(sd);
1251 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1252
1253 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1254}
1255
bb88f325
MB		 1256static inline bool is_hdmi(struct v4l2_subdev *sd)
1257{
1258 return hdmi_read(sd, 0x05) & 0x80;
1259}
1260
54450f59
HV		 1261static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1262{
b44b2e06 1263 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1264
1265 /*
1266 * Chips without a AFE don't expose registers for the SSPD, so just assume
1267 * that we have a lock.
1268 */
b44b2e06 1269 if (adv76xx_has_afe(state))
d42010a1
LPC		 1270 return false;
1271
54450f59
HV		 1272 /* TODO channel 2 */
1273 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1274}
1275
1276static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1277{
1278 /* TODO channel 2 */
1279 return !(cp_read(sd, 0xb1) & 0x80);
1280}
1281
1282static inline bool no_signal(struct v4l2_subdev *sd)
1283{
54450f59
HV		 1284 bool ret;
1285
1286 ret = no_power(sd);
1287
1288 ret |= no_lock_stdi(sd);
1289 ret |= no_lock_sspd(sd);
1290
4a31a93a 1291 if (is_digital_input(sd)) {
54450f59
HV		 1292 ret |= no_lock_tmds(sd);
1293 ret |= no_signal_tmds(sd);
1294 }
1295
1296 return ret;
1297}
1298
1299static inline bool no_lock_cp(struct v4l2_subdev *sd)
1300{
b44b2e06 1301 struct adv76xx_state *state = to_state(sd);
d42010a1 1302
b44b2e06 1303 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1304 return false;
1305
54450f59
HV		 1306 /* CP has detected a non standard number of lines on the incoming
1307 video compared to what it is configured to receive by s_dv_timings */
1308 return io_read(sd, 0x12) & 0x01;
1309}
1310
58514625 1311static inline bool in_free_run(struct v4l2_subdev *sd)
1312{
1313 return cp_read(sd, 0xff) & 0x10;
1314}
1315
b44b2e06 1316static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1317{
54450f59
HV		 1318 *status = 0;
1319 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1320 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1321 if (!in_free_run(sd) && no_lock_cp(sd))
1322 *status |= is_digital_input(sd) ?
1323 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1324
1325 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1326
1327 return 0;
1328}
1329
1330/* ----------------------------------------------------------------------- */
1331
54450f59
HV		 1332struct stdi_readback {
1333 u16 bl, lcf, lcvs;
1334 u8 hs_pol, vs_pol;
1335 bool interlaced;
1336};
1337
1338static int stdi2dv_timings(struct v4l2_subdev *sd,
1339 struct stdi_readback *stdi,
1340 struct v4l2_dv_timings *timings)
1341{
b44b2e06
PA		 1342 struct adv76xx_state *state = to_state(sd);
1343 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1344 u32 pix_clk;
1345 int i;
1346
bd3e275f
JMH		 1347 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1348 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1349
1350 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
9c41e690 1351 adv76xx_get_dv_timings_cap(sd, -1),
bd3e275f 1352 adv76xx_check_dv_timings, NULL))
54450f59 1353 continue;
bd3e275f
JMH		 1354 if (vtotal(bt) != stdi->lcf + 1)
1355 continue;
1356 if (bt->vsync != stdi->lcvs)
54450f59
HV		 1357 continue;
1358
bd3e275f 1359 pix_clk = hfreq * htotal(bt);
54450f59 1360
bd3e275f
JMH		 1361 if ((pix_clk < bt->pixelclock + 1000000) &&
1362 (pix_clk > bt->pixelclock - 1000000)) {
1363 *timings = v4l2_dv_timings_presets[i];
54450f59
HV		 1364 return 0;
1365 }
1366 }
1367
5fea1bb7 1368 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
54450f59
HV		 1369 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1370 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1371 false, timings))
54450f59
HV		 1372 return 0;
1373 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1374 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1375 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1376 false, state->aspect_ratio, timings))
54450f59
HV		 1377 return 0;
1378
ccbd5bc4
HV		 1379 v4l2_dbg(2, debug, sd,
1380 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1381 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1382 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1383 return -1;
1384}
1385
d42010a1 1386
54450f59
HV		 1387static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1388{
b44b2e06
PA		 1389 struct adv76xx_state *state = to_state(sd);
1390 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1391 u8 polarity;
1392
54450f59
HV		 1393 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1394 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1395 return -1;
1396 }
1397
1398 /* read STDI */
51182a94 1399 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1400 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1401 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1402 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1403
b44b2e06 1404 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1405 /* read SSPD */
1406 polarity = cp_read(sd, 0xb5);
1407 if ((polarity & 0x03) == 0x01) {
1408 stdi->hs_pol = polarity & 0x10
1409 ? (polarity & 0x08 ? '+' : '-') : 'x';
1410 stdi->vs_pol = polarity & 0x40
1411 ? (polarity & 0x20 ? '+' : '-') : 'x';
1412 } else {
1413 stdi->hs_pol = 'x';
1414 stdi->vs_pol = 'x';
1415 }
54450f59 1416 } else {
d42010a1
LPC		 1417 polarity = hdmi_read(sd, 0x05);
1418 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1419 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1420 }
1421
1422 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1423 v4l2_dbg(2, debug, sd,
1424 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1425 return -1;
1426 }
1427
1428 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1429 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1430 memset(stdi, 0, sizeof(struct stdi_readback));
1431 return -1;
1432 }
1433
1434 v4l2_dbg(2, debug, sd,
1435 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1436 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1437 stdi->hs_pol, stdi->vs_pol,
1438 stdi->interlaced ? "interlaced" : "progressive");
1439
1440 return 0;
1441}
1442
b44b2e06 1443static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1444 struct v4l2_enum_dv_timings *timings)
1445{
b44b2e06 1446 struct adv76xx_state *state = to_state(sd);
afec5599 1447
afec5599
LP		 1448 if (timings->pad >= state->source_pad)
1449 return -EINVAL;
1450
bd3e275f 1451 return v4l2_enum_dv_timings_cap(timings,
9c41e690
LP		 1452 adv76xx_get_dv_timings_cap(sd, timings->pad),
1453 adv76xx_check_dv_timings, NULL);
54450f59
HV		 1454}
1455
b44b2e06 1456static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1457 struct v4l2_dv_timings_cap *cap)
54450f59 1458{
b44b2e06 1459 struct adv76xx_state *state = to_state(sd);
9c41e690 1460 unsigned int pad = cap->pad;
7515e096
LP		 1461
1462 if (cap->pad >= state->source_pad)
1463 return -EINVAL;
1464
9c41e690
LP		 1465 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1466 cap->pad = pad;
1467
54450f59
HV		 1468 return 0;
1469}
1470
1471/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1472 if the format is listed in adv76xx_timings[] */
1473static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1474 struct v4l2_dv_timings *timings)
1475{
9c41e690
LP		 1476 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1477 is_digital_input(sd) ? 250000 : 1000000,
1478 adv76xx_check_dv_timings, NULL);
54450f59
HV		 1479}
1480
d42010a1
LPC		 1481static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1482{
1483 unsigned int freq;
1484 int a, b;
1485
1486 a = hdmi_read(sd, 0x06);
1487 b = hdmi_read(sd, 0x3b);
1488 if (a < 0 || b < 0)
1489 return 0;
1490 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1491
1492 if (is_hdmi(sd)) {
1493 /* adjust for deep color mode */
1494 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1495
1496 freq = freq * 8 / bits_per_channel;
1497 }
1498
1499 return freq;
1500}
1501
1502static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1503{
1504 int a, b;
1505
1506 a = hdmi_read(sd, 0x51);
1507 b = hdmi_read(sd, 0x52);
1508 if (a < 0 || b < 0)
1509 return 0;
1510 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1511}
1512
b44b2e06 1513static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1514 struct v4l2_dv_timings *timings)
1515{
b44b2e06
PA		 1516 struct adv76xx_state *state = to_state(sd);
1517 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1518 struct v4l2_bt_timings *bt = &timings->bt;
1519 struct stdi_readback stdi;
1520
1521 if (!timings)
1522 return -EINVAL;
1523
1524 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1525
1526 if (no_signal(sd)) {
1e0b9156 1527 state->restart_stdi_once = true;
54450f59
HV		 1528 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1529 return -ENOLINK;
1530 }
1531
1532 /* read STDI */
1533 if (read_stdi(sd, &stdi)) {
1534 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1535 return -ENOLINK;
1536 }
1537 bt->interlaced = stdi.interlaced ?
1538 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1539
4a31a93a 1540 if (is_digital_input(sd)) {
54450f59
HV		 1541 timings->type = V4L2_DV_BT_656_1120;
1542
5380baaf 1543 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1544 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
d42010a1 1545 bt->pixelclock = info->read_hdmi_pixelclock(sd);
5380baaf 1546 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1547 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1548 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1549 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1550 info->field0_vfrontporch_mask) / 2;
1551 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1552 bt->vbackporch = hdmi_read16(sd, 0x32,
1553 info->field0_vbackporch_mask) / 2;
54450f59
HV		 1554 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1555 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1556 if (bt->interlaced == V4L2_DV_INTERLACED) {
5380baaf 1557 bt->height += hdmi_read16(sd, 0x0b,
1558 info->field1_height_mask);
1559 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1560 info->field1_vfrontporch_mask) / 2;
1561 bt->il_vsync = hdmi_read16(sd, 0x30,
1562 info->field1_vsync_mask) / 2;
1563 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1564 info->field1_vbackporch_mask) / 2;
54450f59 1565 }
b44b2e06 1566 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1567 } else {
1568 /* find format
80939647 1569 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1570 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1571 */
1572 if (!stdi2dv_timings(sd, &stdi, timings))
1573 goto found;
1574 stdi.lcvs += 1;
1575 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1576 if (!stdi2dv_timings(sd, &stdi, timings))
1577 goto found;
1578 stdi.lcvs -= 2;
1579 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1580 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1581 /*
1582 * The STDI block may measure wrong values, especially
1583 * for lcvs and lcf. If the driver can not find any
1584 * valid timing, the STDI block is restarted to measure
1585 * the video timings again. The function will return an
1586 * error, but the restart of STDI will generate a new
1587 * STDI interrupt and the format detection process will
1588 * restart.
1589 */
1590 if (state->restart_stdi_once) {
1591 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1592 /* TODO restart STDI for Sync Channel 2 */
1593 /* enter one-shot mode */
22d97e56 1594 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1595 /* trigger STDI restart */
22d97e56 1596 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1597 /* reset to continuous mode */
22d97e56 1598 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1599 state->restart_stdi_once = false;
1600 return -ENOLINK;
1601 }
54450f59
HV		 1602 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1603 return -ERANGE;
1604 }
cf9afb1d 1605 state->restart_stdi_once = true;
54450f59
HV		 1606 }
1607found:
1608
1609 if (no_signal(sd)) {
1610 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1611 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1612 return -ENOLINK;
1613 }
1614
4a31a93a
MR		 1615 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1616 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1617 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1618 __func__, (u32)bt->pixelclock);
1619 return -ERANGE;
1620 }
1621
1622 if (debug > 1)
b44b2e06 1623 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1624 timings, true);
54450f59
HV		 1625
1626 return 0;
1627}
1628
b44b2e06 1629static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1630 struct v4l2_dv_timings *timings)
1631{
b44b2e06 1632 struct adv76xx_state *state = to_state(sd);
54450f59 1633 struct v4l2_bt_timings *bt;
ccbd5bc4 1634 int err;
54450f59
HV		 1635
1636 if (!timings)
1637 return -EINVAL;
1638
85f9e06c 1639 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
d48eb48c
MR		 1640 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1641 return 0;
1642 }
1643
54450f59
HV		 1644 bt = &timings->bt;
1645
9c41e690 1646 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
bd3e275f 1647 adv76xx_check_dv_timings, NULL))
54450f59 1648 return -ERANGE;
ccbd5bc4 1649
b44b2e06 1650 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1651
1652 state->timings = *timings;
1653
22d97e56 1654 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1655
1656 /* Use prim_mode and vid_std when available */
1657 err = configure_predefined_video_timings(sd, timings);
1658 if (err) {
1659 /* custom settings when the video format
1660 does not have prim_mode/vid_std */
1661 configure_custom_video_timings(sd, bt);
1662 }
54450f59
HV		 1663
1664 set_rgb_quantization_range(sd);
1665
54450f59 1666 if (debug > 1)
b44b2e06 1667 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1668 timings, true);
54450f59
HV		 1669 return 0;
1670}
1671
b44b2e06 1672static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1673 struct v4l2_dv_timings *timings)
1674{
b44b2e06 1675 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1676
1677 *timings = state->timings;
1678 return 0;
1679}
1680
d42010a1
LPC		 1681static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1682{
1683 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1684}
1685
1686static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1687{
1688 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1689}
1690
6b0d5d34 1691static void enable_input(struct v4l2_subdev *sd)
54450f59 1692{
b44b2e06 1693 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1694
4a31a93a 1695 if (is_analog_input(sd)) {
54450f59 1696 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1697 } else if (is_digital_input(sd)) {
22d97e56 1698 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1699 state->info->set_termination(sd, true);
54450f59 1700 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1701 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1702 } else {
1703 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1704 __func__, state->selected_input);
54450f59
HV		 1705 }
1706}
1707
1708static void disable_input(struct v4l2_subdev *sd)
1709{
b44b2e06 1710 struct adv76xx_state *state = to_state(sd);
d42010a1 1711
22d97e56 1712 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1713 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1714 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1715 state->info->set_termination(sd, false);
54450f59
HV		 1716}
1717
6b0d5d34 1718static void select_input(struct v4l2_subdev *sd)
54450f59 1719{
b44b2e06
PA		 1720 struct adv76xx_state *state = to_state(sd);
1721 const struct adv76xx_chip_info *info = state->info;
54450f59 1722
4a31a93a 1723 if (is_analog_input(sd)) {
b44b2e06 1724 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1725
1726 afe_write(sd, 0x00, 0x08); /* power up ADC */
1727 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1728 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1729 } else if (is_digital_input(sd)) {
1730 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1731
b44b2e06 1732 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1733
b44b2e06 1734 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1735 afe_write(sd, 0x00, 0xff); /* power down ADC */
1736 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1737 afe_write(sd, 0xc8, 0x40); /* phase control */
1738 }
1739
54450f59
HV		 1740 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1741 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1742 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1743 } else {
1744 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1745 __func__, state->selected_input);
54450f59
HV		 1746 }
1747}
1748
b44b2e06 1749static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1750 u32 input, u32 output, u32 config)
1751{
b44b2e06 1752 struct adv76xx_state *state = to_state(sd);
54450f59 1753
ff4f80fd
MR		 1754 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1755 __func__, input, state->selected_input);
1756
1757 if (input == state->selected_input)
1758 return 0;
54450f59 1759
d42010a1
LPC		 1760 if (input > state->info->max_port)
1761 return -EINVAL;
1762
4a31a93a 1763 state->selected_input = input;
54450f59
HV		 1764
1765 disable_input(sd);
6b0d5d34 1766 select_input(sd);
6b0d5d34 1767 enable_input(sd);
54450f59 1768
6f5bcfc3
LPC		 1769 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1770
54450f59
HV		 1771 return 0;
1772}
1773
b44b2e06 1774static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1775 struct v4l2_subdev_pad_config *cfg,
539b33b0 1776 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1777{
b44b2e06 1778 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1779
1780 if (code->index >= state->info->nformats)
54450f59 1781 return -EINVAL;
539b33b0
LP		 1782
1783 code->code = state->info->formats[code->index].code;
1784
54450f59
HV		 1785 return 0;
1786}
1787
b44b2e06 1788static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1789 struct v4l2_mbus_framefmt *format)
54450f59 1790{
539b33b0 1791 memset(format, 0, sizeof(*format));
54450f59 1792
539b33b0
LP		 1793 format->width = state->timings.bt.width;
1794 format->height = state->timings.bt.height;
1795 format->field = V4L2_FIELD_NONE;
680fee04 1796 format->colorspace = V4L2_COLORSPACE_SRGB;
539b33b0 1797
680fee04 1798 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
539b33b0 1799 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1800 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1801}
1802
1803/*
1804 * Compute the op_ch_sel value required to obtain on the bus the component order
1805 * corresponding to the selected format taking into account bus reordering
1806 * applied by the board at the output of the device.
1807 *
1808 * The following table gives the op_ch_value from the format component order
1809 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1810 * adv76xx_bus_order value in row).
539b33b0
LP		 1811 *
1812 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1813 * ----------+-------------------------------------------------
1814 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1815 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1816 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1817 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1818 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1819 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1820 */
b44b2e06 1821static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1822{
1823#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1824 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1825 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1826#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1827
1828 static const unsigned int op_ch_sel[6][6] = {
1829 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1830 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1831 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1832 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1833 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1834 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1835 };
1836
1837 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1838}
1839
b44b2e06 1840static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1841{
1842 struct v4l2_subdev *sd = &state->sd;
1843
22d97e56 1844 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1845 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1846 io_write(sd, 0x03, state->format->op_format_sel |
1847 state->pdata.op_format_mode_sel);
b44b2e06 1848 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1849 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1850 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1851}
1852
f7234138
HV		 1853static int adv76xx_get_format(struct v4l2_subdev *sd,
1854 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1855 struct v4l2_subdev_format *format)
1856{
b44b2e06 1857 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1858
1859 if (format->pad != state->source_pad)
1860 return -EINVAL;
1861
b44b2e06 1862 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1863
1864 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1865 struct v4l2_mbus_framefmt *fmt;
1866
f7234138 1867 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1868 format->format.code = fmt->code;
1869 } else {
1870 format->format.code = state->format->code;
54450f59 1871 }
539b33b0
LP		 1872
1873 return 0;
1874}
1875
b7d4d2f8
UH		 1876static int adv76xx_get_selection(struct v4l2_subdev *sd,
1877 struct v4l2_subdev_pad_config *cfg,
1878 struct v4l2_subdev_selection *sel)
1879{
1880 struct adv76xx_state *state = to_state(sd);
1881
1882 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1883 return -EINVAL;
1884 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1885 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1886 return -EINVAL;
1887
1888 sel->r.left = 0;
1889 sel->r.top = 0;
1890 sel->r.width = state->timings.bt.width;
1891 sel->r.height = state->timings.bt.height;
1892
1893 return 0;
1894}
1895
f7234138
HV		 1896static int adv76xx_set_format(struct v4l2_subdev *sd,
1897 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1898 struct v4l2_subdev_format *format)
1899{
b44b2e06
PA		 1900 struct adv76xx_state *state = to_state(sd);
1901 const struct adv76xx_format_info *info;
539b33b0
LP		 1902
1903 if (format->pad != state->source_pad)
1904 return -EINVAL;
1905
b44b2e06 1906 info = adv76xx_format_info(state, format->format.code);
539b33b0 1907 if (info == NULL)
b44b2e06 1908 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1909
b44b2e06 1910 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1911 format->format.code = info->code;
1912
1913 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1914 struct v4l2_mbus_framefmt *fmt;
1915
f7234138 1916 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1917 fmt->code = format->format.code;
1918 } else {
1919 state->format = info;
b44b2e06 1920 adv76xx_setup_format(state);
539b33b0
LP		 1921 }
1922
54450f59
HV		 1923 return 0;
1924}
1925
b44b2e06 1926static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1927{
b44b2e06
PA		 1928 struct adv76xx_state *state = to_state(sd);
1929 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1930 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1931 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1932 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1933 u8 fmt_change_digital;
1934 u8 fmt_change;
1935 u8 tx_5v;
1936
1937 if (irq_reg_0x43)
1938 io_write(sd, 0x44, irq_reg_0x43);
1939 if (irq_reg_0x70)
1940 io_write(sd, 0x71, irq_reg_0x70);
1941 if (irq_reg_0x6b)
1942 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1943
ff4f80fd
MR		 1944 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1945
54450f59 1946 /* format change */
f24d229c 1947 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1948 fmt_change_digital = is_digital_input(sd)
1949 ? irq_reg_0x6b & info->fmt_change_digital_mask
1950 : 0;
14d03233 1951
54450f59
HV		 1952 if (fmt_change || fmt_change_digital) {
1953 v4l2_dbg(1, debug, sd,
25a64ac9 1954 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1955 __func__, fmt_change, fmt_change_digital);
25a64ac9 1956
6f5bcfc3 1957 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
25a64ac9 1958
54450f59
HV		 1959 if (handled)
1960 *handled = true;
1961 }
f24d229c
MR		 1962 /* HDMI/DVI mode */
1963 if (irq_reg_0x6b & 0x01) {
1964 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1965 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1966 set_rgb_quantization_range(sd);
1967 if (handled)
1968 *handled = true;
1969 }
1970
54450f59 1971 /* tx 5v detect */
0ba4581c 1972 tx_5v = irq_reg_0x70 & info->cable_det_mask;
54450f59
HV		 1973 if (tx_5v) {
1974 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
b44b2e06 1975 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1976 if (handled)
1977 *handled = true;
1978 }
1979 return 0;
1980}
1981
b44b2e06 1982static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1983{
b44b2e06 1984 struct adv76xx_state *state = to_state(sd);
4a31a93a 1985 u8 *data = NULL;
54450f59 1986
dd9ac11a 1987 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1988
1989 switch (edid->pad) {
b44b2e06 1990 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1991 case ADV7604_PAD_HDMI_PORT_B:
1992 case ADV7604_PAD_HDMI_PORT_C:
1993 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1994 if (state->edid.present & (1 << edid->pad))
1995 data = state->edid.edid;
1996 break;
1997 default:
1998 return -EINVAL;
4a31a93a 1999 }
dd9ac11a
HV		 2000
2001 if (edid->start_block == 0 && edid->blocks == 0) {
2002 edid->blocks = data ? state->edid.blocks : 0;
2003 return 0;
2004 }
2005
2006 if (data == NULL)
4a31a93a
MR		 2007 return -ENODATA;
2008
dd9ac11a
HV		 2009 if (edid->start_block >= state->edid.blocks)
2010 return -EINVAL;
2011
2012 if (edid->start_block + edid->blocks > state->edid.blocks)
2013 edid->blocks = state->edid.blocks - edid->start_block;
2014
2015 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2016
54450f59
HV		 2017 return 0;
2018}
2019
dd08beb9 2020static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 2021{
2022 u8 d;
2023
2024 if ((edid[0x7e] != 1) ||
2025 (edid[0x80] != 0x02) ||
2026 (edid[0x81] != 0x03)) {
2027 return -1;
2028 }
2029
2030 /* search Vendor Specific Data Block (tag 3) */
2031 d = edid[0x82] & 0x7f;
2032 if (d > 4) {
2033 int i = 0x84;
2034 int end = 0x80 + d;
2035
2036 do {
2037 u8 tag = edid[i] >> 5;
2038 u8 len = edid[i] & 0x1f;
2039
2040 if ((tag == 3) && (len >= 5))
2041 return i + 4;
2042 i += len + 1;
2043 } while (i < end);
2044 }
2045 return -1;
2046}
2047
b44b2e06 2048static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 2049{
b44b2e06
PA		 2050 struct adv76xx_state *state = to_state(sd);
2051 const struct adv76xx_chip_info *info = state->info;
dd08beb9 2052 int spa_loc;
54450f59 2053 int err;
dd08beb9 2054 int i;
54450f59 2055
dd9ac11a
HV		 2056 memset(edid->reserved, 0, sizeof(edid->reserved));
2057
c784b1e2 2058 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2059 return -EINVAL;
2060 if (edid->start_block != 0)
2061 return -EINVAL;
2062 if (edid->blocks == 0) {
3e86aa85 2063 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2064 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2065 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2066 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2067
54450f59
HV		 2068 /* Fall back to a 16:9 aspect ratio */
2069 state->aspect_ratio.numerator = 16;
2070 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2071
2072 if (!state->edid.present)
2073 state->edid.blocks = 0;
2074
2075 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2076 __func__, edid->pad, state->edid.present);
54450f59
HV		 2077 return 0;
2078 }
4a31a93a
MR		 2079 if (edid->blocks > 2) {
2080 edid->blocks = 2;
54450f59 2081 return -E2BIG;
4a31a93a 2082 }
4a31a93a 2083
dd08beb9
MR		 2084 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2085 __func__, edid->pad, state->edid.present);
2086
3e86aa85 2087 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2088 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2089 adv76xx_set_hpd(state, 0);
22d97e56 2090 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2091
dd08beb9
MR		 2092 spa_loc = get_edid_spa_location(edid->edid);
2093 if (spa_loc < 0)
2094 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2095
3e86aa85 2096 switch (edid->pad) {
b44b2e06 2097 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2098 state->spa_port_a[0] = edid->edid[spa_loc];
2099 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2100 break;
c784b1e2 2101 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2102 rep_write(sd, 0x70, edid->edid[spa_loc]);
2103 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2104 break;
c784b1e2 2105 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2106 rep_write(sd, 0x72, edid->edid[spa_loc]);
2107 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2108 break;
c784b1e2 2109 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2110 rep_write(sd, 0x74, edid->edid[spa_loc]);
2111 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2112 break;
dd08beb9
MR		 2113 default:
2114 return -EINVAL;
3e86aa85 2115 }
d42010a1
LPC		 2116
2117 if (info->type == ADV7604) {
2118 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2119 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1 2120 } else {
b5a442aa
UH		 2121 /* ADV7612 Software Manual Rev. A, p. 15 */
2122 rep_write(sd, 0x70, spa_loc & 0xff);
22d97e56 2123 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2124 }
3e86aa85 2125
dd08beb9
MR		 2126 edid->edid[spa_loc] = state->spa_port_a[0];
2127 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2128
2129 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2130 state->edid.blocks = edid->blocks;
54450f59
HV		 2131 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2132 edid->edid[0x16]);
3e86aa85 2133 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2134
2135 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2136 if (err < 0) {
3e86aa85 2137 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2138 return err;
2139 }
2140
b44b2e06 2141 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2142 EDID RAM from DDC port. */
22d97e56 2143 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2144
2145 for (i = 0; i < 1000; i++) {
d42010a1 2146 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2147 break;
2148 mdelay(1);
2149 }
2150 if (i == 1000) {
2151 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2152 return -EIO;
2153 }
2154
4a31a93a 2155 /* enable hotplug after 100 ms */
0423ff9b 2156 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
4a31a93a 2157 return 0;
54450f59
HV		 2158}
2159
2160/*********** avi info frame CEA-861-E **************/
2161
516613c1
HV		 2162static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2163 { "AVI", 0x01, 0xe0, 0x00 },
2164 { "Audio", 0x02, 0xe3, 0x1c },
2165 { "SDP", 0x04, 0xe6, 0x2a },
2166 { "Vendor", 0x10, 0xec, 0x54 }
2167};
2168
2169static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2170 union hdmi_infoframe *frame)
54450f59 2171{
516613c1
HV		 2172 uint8_t buffer[32];
2173 u8 len;
54450f59 2174 int i;
54450f59 2175
516613c1
HV		 2176 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2177 v4l2_info(sd, "%s infoframe not received\n",
2178 adv76xx_cri[index].desc);
2179 return -ENOENT;
54450f59 2180 }
516613c1
HV		 2181
2182 for (i = 0; i < 3; i++)
2183 buffer[i] = infoframe_read(sd,
2184 adv76xx_cri[index].head_addr + i);
2185
2186 len = buffer[2] + 1;
2187
2188 if (len + 3 > sizeof(buffer)) {
2189 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2190 adv76xx_cri[index].desc, len);
2191 return -ENOENT;
54450f59
HV		 2192 }
2193
516613c1
HV		 2194 for (i = 0; i < len; i++)
2195 buffer[i + 3] = infoframe_read(sd,
2196 adv76xx_cri[index].payload_addr + i);
2197
2198 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2199 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2200 adv76xx_cri[index].desc);
2201 return -ENOENT;
54450f59 2202 }
516613c1
HV		 2203 return 0;
2204}
54450f59 2205
516613c1
HV		 2206static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2207{
2208 int i;
54450f59 2209
516613c1
HV		 2210 if (!is_hdmi(sd)) {
2211 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
54450f59 2212 return;
516613c1 2213 }
54450f59 2214
516613c1
HV		 2215 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2216 union hdmi_infoframe frame;
2217 struct i2c_client *client = v4l2_get_subdevdata(sd);
54450f59 2218
516613c1
HV		 2219 if (adv76xx_read_infoframe(sd, i, &frame))
2220 return;
2221 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2222 }
54450f59
HV		 2223}
2224
b44b2e06 2225static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2226{
b44b2e06
PA		 2227 struct adv76xx_state *state = to_state(sd);
2228 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2229 struct v4l2_dv_timings timings;
2230 struct stdi_readback stdi;
2231 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2232 u8 edid_enabled;
2233 u8 cable_det;
54450f59 2234
f216ccb3 2235 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2236 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2237 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2238 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2239 "reserved", "reserved", "reserved", "reserved", "manual"
2240 };
f216ccb3 2241 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2242 "RGB limited range (16-235)", "RGB full range (0-255)",
2243 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2244 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2245 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2246 "invalid", "invalid", "invalid", "invalid", "invalid",
2247 "invalid", "invalid", "automatic"
2248 };
7a5d99e7
HV		 2249 static const char * const hdmi_color_space_txt[16] = {
2250 "RGB limited range (16-235)", "RGB full range (0-255)",
2251 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2252 "xvYCC Bt.601", "xvYCC Bt.709",
2253 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2254 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2255 "invalid", "invalid", "invalid"
2256 };
f216ccb3 2257 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2258 "Automatic",
2259 "RGB limited range (16-235)",
2260 "RGB full range (0-255)",
2261 };
f216ccb3 2262 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2263 "8-bits per channel",
2264 "10-bits per channel",
2265 "12-bits per channel",
2266 "16-bits per channel (not supported)"
2267 };
54450f59
HV		 2268
2269 v4l2_info(sd, "-----Chip status-----\n");
2270 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2271 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2272 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2273 ((edid_enabled & 0x01) ? "Yes" : "No"),
2274 ((edid_enabled & 0x02) ? "Yes" : "No"),
2275 ((edid_enabled & 0x04) ? "Yes" : "No"),
2276 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2277 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2278 "enabled" : "disabled");
2279
2280 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2281 cable_det = info->read_cable_det(sd);
4a31a93a 2282 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2283 ((cable_det & 0x01) ? "Yes" : "No"),
2284 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2285 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2286 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2287 v4l2_info(sd, "TMDS signal detected: %s\n",
2288 no_signal_tmds(sd) ? "false" : "true");
2289 v4l2_info(sd, "TMDS signal locked: %s\n",
2290 no_lock_tmds(sd) ? "false" : "true");
2291 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2292 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2293 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2294 v4l2_info(sd, "CP free run: %s\n",
58514625 2295 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2296 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2297 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2298 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2299
2300 v4l2_info(sd, "-----Video Timings-----\n");
2301 if (read_stdi(sd, &stdi))
2302 v4l2_info(sd, "STDI: not locked\n");
2303 else
2304 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2305 stdi.lcf, stdi.bl, stdi.lcvs,
2306 stdi.interlaced ? "interlaced" : "progressive",
2307 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2308 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2309 v4l2_info(sd, "No video detected\n");
2310 else
11d034c8
HV		 2311 v4l2_print_dv_timings(sd->name, "Detected format: ",
2312 &timings, true);
2313 v4l2_print_dv_timings(sd->name, "Configured format: ",
2314 &state->timings, true);
54450f59 2315
76eb2d30
MR		 2316 if (no_signal(sd))
2317 return 0;
2318
54450f59
HV		 2319 v4l2_info(sd, "-----Color space-----\n");
2320 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2321 rgb_quantization_range_txt[state->rgb_quantization_range]);
2322 v4l2_info(sd, "Input color space: %s\n",
2323 input_color_space_txt[reg_io_0x02 >> 4]);
7a5d99e7 2324 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n",
54450f59
HV		 2325 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2326 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
5dd7d88a 2327 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
7a5d99e7
HV		 2328 "enabled" : "disabled",
2329 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
54450f59 2330 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2331 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2332
4a31a93a 2333 if (!is_digital_input(sd))
76eb2d30
MR		 2334 return 0;
2335
2336 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2337 v4l2_info(sd, "Digital video port selected: %c\n",
2338 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2339 v4l2_info(sd, "HDCP encrypted content: %s\n",
2340 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2341 v4l2_info(sd, "HDCP keys read: %s%s\n",
2342 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2343 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2344 if (is_hdmi(sd)) {
76eb2d30
MR		 2345 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2346 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2347 bool audio_mute = io_read(sd, 0x65) & 0x40;
2348
2349 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2350 audio_pll_locked ? "locked" : "not locked",
2351 audio_sample_packet_detect ? "detected" : "not detected",
2352 audio_mute ? "muted" : "enabled");
2353 if (audio_pll_locked && audio_sample_packet_detect) {
2354 v4l2_info(sd, "Audio format: %s\n",
2355 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2356 }
2357 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2358 (hdmi_read(sd, 0x5c) << 8) +
2359 (hdmi_read(sd, 0x5d) & 0xf0));
2360 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2361 (hdmi_read(sd, 0x5e) << 8) +
2362 hdmi_read(sd, 0x5f));
2363 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2364
2365 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
7a5d99e7 2366 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
76eb2d30 2367
516613c1 2368 adv76xx_log_infoframes(sd);
54450f59
HV		 2369 }
2370
2371 return 0;
2372}
2373
6f5bcfc3
LPC		 2374static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2375 struct v4l2_fh *fh,
2376 struct v4l2_event_subscription *sub)
2377{
2378 switch (sub->type) {
2379 case V4L2_EVENT_SOURCE_CHANGE:
2380 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2381 case V4L2_EVENT_CTRL:
2382 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2383 default:
2384 return -EINVAL;
2385 }
2386}
2387
54450f59
HV		 2388/* ----------------------------------------------------------------------- */
2389
b44b2e06
PA		 2390static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2391 .s_ctrl = adv76xx_s_ctrl,
297a4144 2392 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
54450f59
HV		 2393};
2394
b44b2e06
PA		 2395static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2396 .log_status = adv76xx_log_status,
2397 .interrupt_service_routine = adv76xx_isr,
6f5bcfc3 2398 .subscribe_event = adv76xx_subscribe_event,
0975626d 2399 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
54450f59 2400#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2401 .g_register = adv76xx_g_register,
2402 .s_register = adv76xx_s_register,
54450f59
HV		 2403#endif
2404};
2405
b44b2e06
PA		 2406static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2407 .s_routing = adv76xx_s_routing,
2408 .g_input_status = adv76xx_g_input_status,
2409 .s_dv_timings = adv76xx_s_dv_timings,
2410 .g_dv_timings = adv76xx_g_dv_timings,
2411 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2412};
2413
b44b2e06
PA		 2414static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2415 .enum_mbus_code = adv76xx_enum_mbus_code,
b7d4d2f8 2416 .get_selection = adv76xx_get_selection,
b44b2e06
PA		 2417 .get_fmt = adv76xx_get_format,
2418 .set_fmt = adv76xx_set_format,
2419 .get_edid = adv76xx_get_edid,
2420 .set_edid = adv76xx_set_edid,
2421 .dv_timings_cap = adv76xx_dv_timings_cap,
2422 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2423};
2424
b44b2e06
PA		 2425static const struct v4l2_subdev_ops adv76xx_ops = {
2426 .core = &adv76xx_core_ops,
2427 .video = &adv76xx_video_ops,
2428 .pad = &adv76xx_pad_ops,
54450f59
HV		 2429};
2430
2431/* -------------------------- custom ctrls ---------------------------------- */
2432
2433static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2434 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2435 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2436 .name = "Analog Sampling Phase",
2437 .type = V4L2_CTRL_TYPE_INTEGER,
2438 .min = 0,
2439 .max = 0x1f,
2440 .step = 1,
2441 .def = 0,
2442};
2443
b44b2e06
PA		 2444static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2445 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2446 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2447 .name = "Free Running Color, Manual",
2448 .type = V4L2_CTRL_TYPE_BOOLEAN,
2449 .min = false,
2450 .max = true,
2451 .step = 1,
2452 .def = false,
2453};
2454
b44b2e06
PA		 2455static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2456 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2457 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2458 .name = "Free Running Color",
2459 .type = V4L2_CTRL_TYPE_INTEGER,
2460 .min = 0x0,
2461 .max = 0xffffff,
2462 .step = 0x1,
2463 .def = 0x0,
2464};
2465
2466/* ----------------------------------------------------------------------- */
2467
b44b2e06 2468static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2469{
b44b2e06
PA		 2470 struct adv76xx_state *state = to_state(sd);
2471 const struct adv76xx_chip_info *info = state->info;
2472 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2473
2474 hdmi_write(sd, 0x48,
2475 (pdata->disable_pwrdnb ? 0x80 : 0) |
2476 (pdata->disable_cable_det_rst ? 0x40 : 0));
2477
2478 disable_input(sd);
2479
5ef54b59
LP		 2480 if (pdata->default_input >= 0 &&
2481 pdata->default_input < state->source_pad) {
2482 state->selected_input = pdata->default_input;
2483 select_input(sd);
2484 enable_input(sd);
2485 }
2486
54450f59
HV		 2487 /* power */
2488 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2489 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2490 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2491
2492 /* video format */
22d97e56 2493 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2494 pdata->alt_gamma << 3 |
2495 pdata->op_656_range << 2 |
54450f59 2496 pdata->alt_data_sat << 0);
22d97e56 2497 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2498 pdata->insert_av_codes << 2 |
2499 pdata->replicate_av_codes << 1);
b44b2e06 2500 adv76xx_setup_format(state);
54450f59 2501
54450f59 2502 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2503
2504 /* VS, HS polarities */
1b5ab875
LP		 2505 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2506 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2507
2508 /* Adjust drive strength */
2509 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2510 pdata->dr_str_clk << 2 |
2511 pdata->dr_str_sync);
2512
54450f59
HV		 2513 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2514 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2515 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2516 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2517 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2518 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2519 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2520 for digital formats */
2521
5474b983 2522 /* HDMI audio */
22d97e56
LP		 2523 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2524 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2525 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2526
54450f59
HV		 2527 /* TODO from platform data */
2528 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2529
b44b2e06 2530 if (adv76xx_has_afe(state)) {
d42010a1 2531 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2532 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2533 }
54450f59 2534
54450f59 2535 /* interrupts */
d42010a1 2536 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2537 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2538 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2539 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2540 info->setup_irqs(sd);
54450f59
HV		 2541
2542 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2543}
2544
d42010a1
LPC		 2545static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2546{
2547 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2548}
2549
2550static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2551{
2552 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2553}
2554
8331d30b
WT		 2555static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2556{
2557 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2558}
2559
b44b2e06 2560static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2561{
05cacb17
LP		 2562 unsigned int i;
2563
2564 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2565 if (state->i2c_clients[i])
2566 i2c_unregister_device(state->i2c_clients[i]);
2567 }
54450f59
HV		 2568}
2569
b44b2e06 2570static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2571 u8 addr, u8 io_reg)
2572{
2573 struct i2c_client *client = v4l2_get_subdevdata(sd);
2574
2575 if (addr)
2576 io_write(sd, io_reg, addr << 1);
2577 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2578}
2579
b44b2e06 2580static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2581 /* reset ADI recommended settings for HDMI: */
2582 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2583 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2584 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2585 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2586 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2587 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2588 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2589 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2590 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2591 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2592 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2593 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2594 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2595
2596 /* set ADI recommended settings for digitizer */
2597 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2598 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2599 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2600 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2601 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2602 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2603
b44b2e06 2604 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2605};
2606
b44b2e06 2607static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2608 /* set ADI recommended settings for HDMI: */
2609 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2610 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2611 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2612 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2613 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2614 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2615 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2616 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2617 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2618 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2619 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2620 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2621
2622 /* reset ADI recommended settings for digitizer */
2623 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2624 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2625 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2626
b44b2e06 2627 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2628};
2629
b44b2e06 2630static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2631 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2632 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2633 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2634 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2635 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2636 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2637 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2638 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2639 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2640 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2641 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2642 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2643
2644 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2645};
2646
8331d30b
WT		 2647static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2648 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2649 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2650 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2651 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2652 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2653 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2654 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2655 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2656 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2657 { ADV76XX_REG_SEQ_TERM, 0 },
2658};
2659
b44b2e06 2660static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2661 [ADV7604] = {
2662 .type = ADV7604,
2663 .has_afe = true,
c784b1e2 2664 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2665 .num_dv_ports = 4,
2666 .edid_enable_reg = 0x77,
2667 .edid_status_reg = 0x7d,
2668 .lcf_reg = 0xb3,
2669 .tdms_lock_mask = 0xe0,
2670 .cable_det_mask = 0x1e,
2671 .fmt_change_digital_mask = 0xc1,
80f4944e 2672 .cp_csc = 0xfc,
539b33b0
LP		 2673 .formats = adv7604_formats,
2674 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2675 .set_termination = adv7604_set_termination,
2676 .setup_irqs = adv7604_setup_irqs,
2677 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2678 .read_cable_det = adv7604_read_cable_det,
2679 .recommended_settings = {
2680 [0] = adv7604_recommended_settings_afe,
2681 [1] = adv7604_recommended_settings_hdmi,
2682 },
2683 .num_recommended_settings = {
2684 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2685 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2686 },
b44b2e06
PA		 2687 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2688 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2689 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2690 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2691 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2692 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1 2693 BIT(ADV7604_PAGE_VDP),
5380baaf 2694 .linewidth_mask = 0xfff,
2695 .field0_height_mask = 0xfff,
2696 .field1_height_mask = 0xfff,
2697 .hfrontporch_mask = 0x3ff,
2698 .hsync_mask = 0x3ff,
2699 .hbackporch_mask = 0x3ff,
2700 .field0_vfrontporch_mask = 0x1fff,
2701 .field0_vsync_mask = 0x1fff,
2702 .field0_vbackporch_mask = 0x1fff,
2703 .field1_vfrontporch_mask = 0x1fff,
2704 .field1_vsync_mask = 0x1fff,
2705 .field1_vbackporch_mask = 0x1fff,
d42010a1
LPC		 2706 },
2707 [ADV7611] = {
2708 .type = ADV7611,
2709 .has_afe = false,
b44b2e06 2710 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2711 .num_dv_ports = 1,
2712 .edid_enable_reg = 0x74,
2713 .edid_status_reg = 0x76,
2714 .lcf_reg = 0xa3,
2715 .tdms_lock_mask = 0x43,
2716 .cable_det_mask = 0x01,
2717 .fmt_change_digital_mask = 0x03,
80f4944e 2718 .cp_csc = 0xf4,
539b33b0
LP		 2719 .formats = adv7611_formats,
2720 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2721 .set_termination = adv7611_set_termination,
2722 .setup_irqs = adv7611_setup_irqs,
2723 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2724 .read_cable_det = adv7611_read_cable_det,
2725 .recommended_settings = {
2726 [1] = adv7611_recommended_settings_hdmi,
2727 },
2728 .num_recommended_settings = {
2729 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2730 },
b44b2e06
PA		 2731 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2732 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2733 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2734 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
5380baaf 2735 .linewidth_mask = 0x1fff,
2736 .field0_height_mask = 0x1fff,
2737 .field1_height_mask = 0x1fff,
2738 .hfrontporch_mask = 0x1fff,
2739 .hsync_mask = 0x1fff,
2740 .hbackporch_mask = 0x1fff,
2741 .field0_vfrontporch_mask = 0x3fff,
2742 .field0_vsync_mask = 0x3fff,
2743 .field0_vbackporch_mask = 0x3fff,
2744 .field1_vfrontporch_mask = 0x3fff,
2745 .field1_vsync_mask = 0x3fff,
2746 .field1_vbackporch_mask = 0x3fff,
d42010a1 2747 },
8331d30b
WT		 2748 [ADV7612] = {
2749 .type = ADV7612,
2750 .has_afe = false,
7111cddd
WT		 2751 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
2752 .num_dv_ports = 1, /* normally 2 */
8331d30b
WT		 2753 .edid_enable_reg = 0x74,
2754 .edid_status_reg = 0x76,
2755 .lcf_reg = 0xa3,
2756 .tdms_lock_mask = 0x43,
2757 .cable_det_mask = 0x01,
2758 .fmt_change_digital_mask = 0x03,
7111cddd 2759 .cp_csc = 0xf4,
8331d30b
WT		 2760 .formats = adv7612_formats,
2761 .nformats = ARRAY_SIZE(adv7612_formats),
2762 .set_termination = adv7611_set_termination,
2763 .setup_irqs = adv7612_setup_irqs,
2764 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
7111cddd 2765 .read_cable_det = adv7612_read_cable_det,
8331d30b
WT		 2766 .recommended_settings = {
2767 [1] = adv7612_recommended_settings_hdmi,
2768 },
2769 .num_recommended_settings = {
2770 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
2771 },
2772 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2773 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2774 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2775 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2776 .linewidth_mask = 0x1fff,
2777 .field0_height_mask = 0x1fff,
2778 .field1_height_mask = 0x1fff,
2779 .hfrontporch_mask = 0x1fff,
2780 .hsync_mask = 0x1fff,
2781 .hbackporch_mask = 0x1fff,
2782 .field0_vfrontporch_mask = 0x3fff,
2783 .field0_vsync_mask = 0x3fff,
2784 .field0_vbackporch_mask = 0x3fff,
2785 .field1_vfrontporch_mask = 0x3fff,
2786 .field1_vsync_mask = 0x3fff,
2787 .field1_vbackporch_mask = 0x3fff,
2788 },
d42010a1
LPC		 2789};
2790
7f099a75 2791static const struct i2c_device_id adv76xx_i2c_id[] = {
b44b2e06
PA		 2792 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2793 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
8331d30b 2794 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2795 { }
2796};
b44b2e06 2797MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2798
7f099a75 2799static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
b44b2e06 2800 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
8331d30b 2801 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2802 { }
2803};
b44b2e06 2804MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2805
b44b2e06 2806static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2807{
6fa88045
LP		 2808 struct v4l2_of_endpoint bus_cfg;
2809 struct device_node *endpoint;
2810 struct device_node *np;
2811 unsigned int flags;
7f6cd6c4 2812 int ret;
bf9c8227 2813 u32 v;
6fa88045 2814
b44b2e06 2815 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2816
2817 /* Parse the endpoint. */
2818 endpoint = of_graph_get_next_endpoint(np, NULL);
2819 if (!endpoint)
2820 return -EINVAL;
2821
7f6cd6c4
JMC		 2822 ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2823 if (ret) {
2824 of_node_put(endpoint);
2825 return ret;
2826 }
bf9c8227
IM		 2827
2828 if (!of_property_read_u32(endpoint, "default-input", &v))
2829 state->pdata.default_input = v;
2830 else
2831 state->pdata.default_input = -1;
2832
6fa88045
LP		 2833 of_node_put(endpoint);
2834
2835 flags = bus_cfg.bus.parallel.flags;
2836
2837 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2838 state->pdata.inv_hs_pol = 1;
2839
2840 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2841 state->pdata.inv_vs_pol = 1;
2842
2843 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2844 state->pdata.inv_llc_pol = 1;
2845
2846 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2847 state->pdata.insert_av_codes = 1;
2848 state->pdata.op_656_range = 1;
2849 }
2850
f82f313e 2851 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2852 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2853
2854 /* Use the default I2C addresses. */
2855 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2856 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2857 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2858 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2859 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2860 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2861 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2862 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2863 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2864 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2865 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2866 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2867
2868 /* Hardcode the remaining platform data fields. */
2869 state->pdata.disable_pwrdnb = 0;
2870 state->pdata.disable_cable_det_rst = 0;
f82f313e 2871 state->pdata.blank_data = 1;
f82f313e 2872 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2873 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2874 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2875
2876 return 0;
2877}
2878
f862f57d
PA		 2879static const struct regmap_config adv76xx_regmap_cnf[] = {
2880 {
2881 .name = "io",
2882 .reg_bits = 8,
2883 .val_bits = 8,
2884
2885 .max_register = 0xff,
2886 .cache_type = REGCACHE_NONE,
2887 },
2888 {
2889 .name = "avlink",
2890 .reg_bits = 8,
2891 .val_bits = 8,
2892
2893 .max_register = 0xff,
2894 .cache_type = REGCACHE_NONE,
2895 },
2896 {
2897 .name = "cec",
2898 .reg_bits = 8,
2899 .val_bits = 8,
2900
2901 .max_register = 0xff,
2902 .cache_type = REGCACHE_NONE,
2903 },
2904 {
2905 .name = "infoframe",
2906 .reg_bits = 8,
2907 .val_bits = 8,
2908
2909 .max_register = 0xff,
2910 .cache_type = REGCACHE_NONE,
2911 },
2912 {
2913 .name = "esdp",
2914 .reg_bits = 8,
2915 .val_bits = 8,
2916
2917 .max_register = 0xff,
2918 .cache_type = REGCACHE_NONE,
2919 },
2920 {
2921 .name = "epp",
2922 .reg_bits = 8,
2923 .val_bits = 8,
2924
2925 .max_register = 0xff,
2926 .cache_type = REGCACHE_NONE,
2927 },
2928 {
2929 .name = "afe",
2930 .reg_bits = 8,
2931 .val_bits = 8,
2932
2933 .max_register = 0xff,
2934 .cache_type = REGCACHE_NONE,
2935 },
2936 {
2937 .name = "rep",
2938 .reg_bits = 8,
2939 .val_bits = 8,
2940
2941 .max_register = 0xff,
2942 .cache_type = REGCACHE_NONE,
2943 },
2944 {
2945 .name = "edid",
2946 .reg_bits = 8,
2947 .val_bits = 8,
2948
2949 .max_register = 0xff,
2950 .cache_type = REGCACHE_NONE,
2951 },
2952
2953 {
2954 .name = "hdmi",
2955 .reg_bits = 8,
2956 .val_bits = 8,
2957
2958 .max_register = 0xff,
2959 .cache_type = REGCACHE_NONE,
2960 },
2961 {
2962 .name = "test",
2963 .reg_bits = 8,
2964 .val_bits = 8,
2965
2966 .max_register = 0xff,
2967 .cache_type = REGCACHE_NONE,
2968 },
2969 {
2970 .name = "cp",
2971 .reg_bits = 8,
2972 .val_bits = 8,
2973
2974 .max_register = 0xff,
2975 .cache_type = REGCACHE_NONE,
2976 },
2977 {
2978 .name = "vdp",
2979 .reg_bits = 8,
2980 .val_bits = 8,
2981
2982 .max_register = 0xff,
2983 .cache_type = REGCACHE_NONE,
2984 },
2985};
2986
2987static int configure_regmap(struct adv76xx_state *state, int region)
2988{
2989 int err;
2990
2991 if (!state->i2c_clients[region])
2992 return -ENODEV;
2993
2994 state->regmap[region] =
2995 devm_regmap_init_i2c(state->i2c_clients[region],
2996 &adv76xx_regmap_cnf[region]);
2997
2998 if (IS_ERR(state->regmap[region])) {
2999 err = PTR_ERR(state->regmap[region]);
3000 v4l_err(state->i2c_clients[region],
3001 "Error initializing regmap %d with error %d\n",
3002 region, err);
3003 return -EINVAL;
3004 }
3005
3006 return 0;
3007}
3008
3009static int configure_regmaps(struct adv76xx_state *state)
3010{
3011 int i, err;
3012
3013 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3014 err = configure_regmap(state, i);
3015 if (err && (err != -ENODEV))
3016 return err;
3017 }
3018 return 0;
3019}
3020
b44b2e06 3021static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 3022 const struct i2c_device_id *id)
3023{
591b72fe
HV		 3024 static const struct v4l2_dv_timings cea640x480 =
3025 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 3026 struct adv76xx_state *state;
54450f59 3027 struct v4l2_ctrl_handler *hdl;
297a4144 3028 struct v4l2_ctrl *ctrl;
54450f59 3029 struct v4l2_subdev *sd;
c784b1e2 3030 unsigned int i;
f862f57d 3031 unsigned int val, val2;
54450f59
HV		 3032 int err;
3033
3034 /* Check if the adapter supports the needed features */
3035 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3036 return -EIO;
b44b2e06 3037 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 3038 client->addr << 1);
3039
c02b211d 3040 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 3041 if (!state) {
b44b2e06 3042 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 3043 return -ENOMEM;
3044 }
3045
b44b2e06 3046 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 3047
25a64ac9
MR		 3048 /* initialize variables */
3049 state->restart_stdi_once = true;
ff4f80fd 3050 state->selected_input = ~0;
25a64ac9 3051
f82f313e
LP		 3052 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3053 const struct of_device_id *oid;
3054
b44b2e06 3055 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 3056 state->info = oid->data;
3057
b44b2e06 3058 err = adv76xx_parse_dt(state);
f82f313e
LP		 3059 if (err < 0) {
3060 v4l_err(client, "DT parsing error\n");
3061 return err;
3062 }
3063 } else if (client->dev.platform_data) {
b44b2e06 3064 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 3065
b44b2e06 3066 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 3067 state->pdata = *pdata;
3068 } else {
54450f59 3069 v4l_err(client, "No platform data!\n");
c02b211d 3070 return -ENODEV;
54450f59 3071 }
e9d50e9e
LP		 3072
3073 /* Request GPIOs. */
3074 for (i = 0; i < state->info->num_dv_ports; ++i) {
3075 state->hpd_gpio[i] =
269bd132
UKK		 3076 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3077 GPIOD_OUT_LOW);
e9d50e9e 3078 if (IS_ERR(state->hpd_gpio[i]))
269bd132 3079 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 3080
269bd132
UKK		 3081 if (state->hpd_gpio[i])
3082 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e
LP		 3083 }
3084
591b72fe 3085 state->timings = cea640x480;
b44b2e06 3086 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 3087
3088 sd = &state->sd;
b44b2e06 3089 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 3090 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3091 id->name, i2c_adapter_id(client->adapter),
3092 client->addr);
0975626d 3093 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
54450f59 3094
f862f57d
PA		 3095 /* Configure IO Regmap region */
3096 err = configure_regmap(state, ADV76XX_PAGE_IO);
3097
3098 if (err) {
3099 v4l2_err(sd, "Error configuring IO regmap region\n");
3100 return -ENODEV;
3101 }
3102
d42010a1
LPC		 3103 /*
3104 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3105 * identifies the revision, while on ADV7611 it identifies the model as
3106 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3107 */
8331d30b
WT		 3108 switch (state->info->type) {
3109 case ADV7604:
f862f57d
PA		 3110 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3111 if (err) {
3112 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3113 return -ENODEV;
3114 }
d42010a1 3115 if (val != 0x68) {
f862f57d 3116 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
d42010a1
LPC		 3117 client->addr << 1);
3118 return -ENODEV;
3119 }
8331d30b
WT		 3120 break;
3121 case ADV7611:
3122 case ADV7612:
f862f57d
PA		 3123 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3124 0xea,
3125 &val);
3126 if (err) {
3127 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3128 return -ENODEV;
3129 }
3130 val2 = val << 8;
3131 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3132 0xeb,
3133 &val);
3134 if (err) {
3135 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3136 return -ENODEV;
3137 }
c1362384 3138 val |= val2;
8331d30b
WT		 3139 if ((state->info->type == ADV7611 && val != 0x2051) ||
3140 (state->info->type == ADV7612 && val != 0x2041)) {
3141 v4l2_err(sd, "not an adv761x on address 0x%x\n",
d42010a1
LPC		 3142 client->addr << 1);
3143 return -ENODEV;
3144 }
8331d30b 3145 break;
54450f59
HV		 3146 }
3147
3148 /* control handlers */
3149 hdl = &state->hdl;
b44b2e06 3150 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 3151
b44b2e06 3152 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3153 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 3154 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3155 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 3156 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3157 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 3158 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3159 V4L2_CID_HUE, 0, 128, 1, 0);
297a4144
HV		 3160 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3161 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3162 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3163 if (ctrl)
3164 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
54450f59 3165
54450f59 3166 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 3167 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3168 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 3169 state->rgb_quantization_range_ctrl =
b44b2e06 3170 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3171 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3172 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 3173
3174 /* custom controls */
b44b2e06 3175 if (adv76xx_has_afe(state))
d42010a1
LPC		 3176 state->analog_sampling_phase_ctrl =
3177 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 3178 state->free_run_color_manual_ctrl =
b44b2e06 3179 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 3180 state->free_run_color_ctrl =
b44b2e06 3181 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 3182
3183 sd->ctrl_handler = hdl;
3184 if (hdl->error) {
3185 err = hdl->error;
3186 goto err_hdl;
3187 }
b44b2e06 3188 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 3189 err = -ENODEV;
3190 goto err_hdl;
3191 }
3192
b44b2e06 3193 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 3194 if (!(BIT(i) & state->info->page_mask))
3195 continue;
54450f59 3196
05cacb17 3197 state->i2c_clients[i] =
b44b2e06 3198 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 3199 0xf2 + i);
3200 if (state->i2c_clients[i] == NULL) {
d42010a1 3201 err = -ENOMEM;
05cacb17 3202 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 3203 goto err_i2c;
3204 }
3205 }
05cacb17 3206
54450f59 3207 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 3208 adv76xx_delayed_work_enable_hotplug);
54450f59 3209
c784b1e2
LP		 3210 state->source_pad = state->info->num_dv_ports
3211 + (state->info->has_afe ? 2 : 0);
3212 for (i = 0; i < state->source_pad; ++i)
3213 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3214 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3215
ab22e77c 3216 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
18095107 3217 state->pads);
54450f59
HV		 3218 if (err)
3219 goto err_work_queues;
3220
f862f57d
PA		 3221 /* Configure regmaps */
3222 err = configure_regmaps(state);
3223 if (err)
3224 goto err_entity;
3225
b44b2e06 3226 err = adv76xx_core_init(sd);
54450f59
HV		 3227 if (err)
3228 goto err_entity;
3229 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3230 client->addr << 1, client->adapter->name);
bedc3939
LPC		 3231
3232 err = v4l2_async_register_subdev(sd);
3233 if (err)
3234 goto err_entity;
3235
54450f59
HV		 3236 return 0;
3237
3238err_entity:
3239 media_entity_cleanup(&sd->entity);
3240err_work_queues:
3241 cancel_delayed_work(&state->delayed_work_enable_hotplug);
54450f59 3242err_i2c:
b44b2e06 3243 adv76xx_unregister_clients(state);
54450f59
HV		 3244err_hdl:
3245 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 3246 return err;
3247}
3248
3249/* ----------------------------------------------------------------------- */
3250
b44b2e06 3251static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 3252{
3253 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 3254 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 3255
3256 cancel_delayed_work(&state->delayed_work_enable_hotplug);
bedc3939 3257 v4l2_async_unregister_subdev(sd);
54450f59 3258 media_entity_cleanup(&sd->entity);
b44b2e06 3259 adv76xx_unregister_clients(to_state(sd));
54450f59 3260 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 3261 return 0;
3262}
3263
3264/* ----------------------------------------------------------------------- */
3265
b44b2e06 3266static struct i2c_driver adv76xx_driver = {
54450f59 3267 .driver = {
54450f59 3268 .name = "adv7604",
b44b2e06 3269 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 3270 },
b44b2e06
PA		 3271 .probe = adv76xx_probe,
3272 .remove = adv76xx_remove,
3273 .id_table = adv76xx_i2c_id,
54450f59
HV		 3274};
3275
b44b2e06 3276module_i2c_driver(adv76xx_driver);
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