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54450f59 HV |
1 | /* |
2 | * adv7604 - Analog Devices ADV7604 video decoder driver | |
3 | * | |
4 | * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. | |
5 | * | |
6 | * This program is free software; you may redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
17 | * SOFTWARE. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * References (c = chapter, p = page): | |
23 | * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, | |
24 | * Revision 2.5, June 2010 | |
25 | * REF_02 - Analog devices, Register map documentation, Documentation of | |
26 | * the register maps, Software manual, Rev. F, June 2010 | |
27 | * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 | |
28 | */ | |
29 | ||
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/i2c.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/videodev2.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/v4l2-dv-timings.h> | |
39 | #include <media/v4l2-device.h> | |
40 | #include <media/v4l2-ctrls.h> | |
25764158 | 41 | #include <media/v4l2-dv-timings.h> |
54450f59 HV |
42 | #include <media/adv7604.h> |
43 | ||
44 | static int debug; | |
45 | module_param(debug, int, 0644); | |
46 | MODULE_PARM_DESC(debug, "debug level (0-2)"); | |
47 | ||
48 | MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); | |
49 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); | |
50 | MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
53 | /* ADV7604 system clock frequency */ | |
54 | #define ADV7604_fsc (28636360) | |
55 | ||
539b33b0 LP |
56 | #define ADV7604_RGB_OUT (1 << 1) |
57 | ||
58 | #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) | |
59 | #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) | |
60 | #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) | |
61 | ||
62 | #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) | |
63 | #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) | |
64 | #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) | |
65 | #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) | |
66 | #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) | |
67 | #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) | |
68 | ||
69 | #define ADV7604_OP_CH_SEL_GBR (0 << 5) | |
70 | #define ADV7604_OP_CH_SEL_GRB (1 << 5) | |
71 | #define ADV7604_OP_CH_SEL_BGR (2 << 5) | |
72 | #define ADV7604_OP_CH_SEL_RGB (3 << 5) | |
73 | #define ADV7604_OP_CH_SEL_BRG (4 << 5) | |
74 | #define ADV7604_OP_CH_SEL_RBG (5 << 5) | |
75 | ||
76 | #define ADV7604_OP_SWAP_CB_CR (1 << 0) | |
77 | ||
d42010a1 LPC |
78 | enum adv7604_type { |
79 | ADV7604, | |
80 | ADV7611, | |
81 | }; | |
82 | ||
83 | struct adv7604_reg_seq { | |
84 | unsigned int reg; | |
85 | u8 val; | |
86 | }; | |
87 | ||
539b33b0 LP |
88 | struct adv7604_format_info { |
89 | enum v4l2_mbus_pixelcode code; | |
90 | u8 op_ch_sel; | |
91 | bool rgb_out; | |
92 | bool swap_cb_cr; | |
93 | u8 op_format_sel; | |
94 | }; | |
95 | ||
d42010a1 LPC |
96 | struct adv7604_chip_info { |
97 | enum adv7604_type type; | |
98 | ||
99 | bool has_afe; | |
100 | unsigned int max_port; | |
101 | unsigned int num_dv_ports; | |
102 | ||
103 | unsigned int edid_enable_reg; | |
104 | unsigned int edid_status_reg; | |
105 | unsigned int lcf_reg; | |
106 | ||
107 | unsigned int cable_det_mask; | |
108 | unsigned int tdms_lock_mask; | |
109 | unsigned int fmt_change_digital_mask; | |
110 | ||
539b33b0 LP |
111 | const struct adv7604_format_info *formats; |
112 | unsigned int nformats; | |
113 | ||
d42010a1 LPC |
114 | void (*set_termination)(struct v4l2_subdev *sd, bool enable); |
115 | void (*setup_irqs)(struct v4l2_subdev *sd); | |
116 | unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); | |
117 | unsigned int (*read_cable_det)(struct v4l2_subdev *sd); | |
118 | ||
119 | /* 0 = AFE, 1 = HDMI */ | |
120 | const struct adv7604_reg_seq *recommended_settings[2]; | |
121 | unsigned int num_recommended_settings[2]; | |
122 | ||
123 | unsigned long page_mask; | |
124 | }; | |
125 | ||
54450f59 HV |
126 | /* |
127 | ********************************************************************** | |
128 | * | |
129 | * Arrays with configuration parameters for the ADV7604 | |
130 | * | |
131 | ********************************************************************** | |
132 | */ | |
c784b1e2 | 133 | |
54450f59 | 134 | struct adv7604_state { |
d42010a1 | 135 | const struct adv7604_chip_info *info; |
54450f59 | 136 | struct adv7604_platform_data pdata; |
539b33b0 | 137 | |
54450f59 | 138 | struct v4l2_subdev sd; |
c784b1e2 LP |
139 | struct media_pad pads[ADV7604_PAD_MAX]; |
140 | unsigned int source_pad; | |
539b33b0 | 141 | |
54450f59 | 142 | struct v4l2_ctrl_handler hdl; |
539b33b0 | 143 | |
c784b1e2 | 144 | enum adv7604_pad selected_input; |
539b33b0 | 145 | |
54450f59 | 146 | struct v4l2_dv_timings timings; |
539b33b0 LP |
147 | const struct adv7604_format_info *format; |
148 | ||
4a31a93a MR |
149 | struct { |
150 | u8 edid[256]; | |
151 | u32 present; | |
152 | unsigned blocks; | |
153 | } edid; | |
dd08beb9 | 154 | u16 spa_port_a[2]; |
54450f59 HV |
155 | struct v4l2_fract aspect_ratio; |
156 | u32 rgb_quantization_range; | |
157 | struct workqueue_struct *work_queues; | |
158 | struct delayed_work delayed_work_enable_hotplug; | |
cf9afb1d | 159 | bool restart_stdi_once; |
54450f59 HV |
160 | |
161 | /* i2c clients */ | |
05cacb17 | 162 | struct i2c_client *i2c_clients[ADV7604_PAGE_MAX]; |
54450f59 HV |
163 | |
164 | /* controls */ | |
165 | struct v4l2_ctrl *detect_tx_5v_ctrl; | |
166 | struct v4l2_ctrl *analog_sampling_phase_ctrl; | |
167 | struct v4l2_ctrl *free_run_color_manual_ctrl; | |
168 | struct v4l2_ctrl *free_run_color_ctrl; | |
169 | struct v4l2_ctrl *rgb_quantization_range_ctrl; | |
170 | }; | |
171 | ||
d42010a1 LPC |
172 | static bool adv7604_has_afe(struct adv7604_state *state) |
173 | { | |
174 | return state->info->has_afe; | |
175 | } | |
176 | ||
54450f59 HV |
177 | /* Supported CEA and DMT timings */ |
178 | static const struct v4l2_dv_timings adv7604_timings[] = { | |
179 | V4L2_DV_BT_CEA_720X480P59_94, | |
180 | V4L2_DV_BT_CEA_720X576P50, | |
181 | V4L2_DV_BT_CEA_1280X720P24, | |
182 | V4L2_DV_BT_CEA_1280X720P25, | |
54450f59 HV |
183 | V4L2_DV_BT_CEA_1280X720P50, |
184 | V4L2_DV_BT_CEA_1280X720P60, | |
185 | V4L2_DV_BT_CEA_1920X1080P24, | |
186 | V4L2_DV_BT_CEA_1920X1080P25, | |
187 | V4L2_DV_BT_CEA_1920X1080P30, | |
188 | V4L2_DV_BT_CEA_1920X1080P50, | |
189 | V4L2_DV_BT_CEA_1920X1080P60, | |
190 | ||
ccbd5bc4 | 191 | /* sorted by DMT ID */ |
54450f59 HV |
192 | V4L2_DV_BT_DMT_640X350P85, |
193 | V4L2_DV_BT_DMT_640X400P85, | |
194 | V4L2_DV_BT_DMT_720X400P85, | |
195 | V4L2_DV_BT_DMT_640X480P60, | |
196 | V4L2_DV_BT_DMT_640X480P72, | |
197 | V4L2_DV_BT_DMT_640X480P75, | |
198 | V4L2_DV_BT_DMT_640X480P85, | |
199 | V4L2_DV_BT_DMT_800X600P56, | |
200 | V4L2_DV_BT_DMT_800X600P60, | |
201 | V4L2_DV_BT_DMT_800X600P72, | |
202 | V4L2_DV_BT_DMT_800X600P75, | |
203 | V4L2_DV_BT_DMT_800X600P85, | |
204 | V4L2_DV_BT_DMT_848X480P60, | |
205 | V4L2_DV_BT_DMT_1024X768P60, | |
206 | V4L2_DV_BT_DMT_1024X768P70, | |
207 | V4L2_DV_BT_DMT_1024X768P75, | |
208 | V4L2_DV_BT_DMT_1024X768P85, | |
209 | V4L2_DV_BT_DMT_1152X864P75, | |
210 | V4L2_DV_BT_DMT_1280X768P60_RB, | |
211 | V4L2_DV_BT_DMT_1280X768P60, | |
212 | V4L2_DV_BT_DMT_1280X768P75, | |
213 | V4L2_DV_BT_DMT_1280X768P85, | |
214 | V4L2_DV_BT_DMT_1280X800P60_RB, | |
215 | V4L2_DV_BT_DMT_1280X800P60, | |
216 | V4L2_DV_BT_DMT_1280X800P75, | |
217 | V4L2_DV_BT_DMT_1280X800P85, | |
218 | V4L2_DV_BT_DMT_1280X960P60, | |
219 | V4L2_DV_BT_DMT_1280X960P85, | |
220 | V4L2_DV_BT_DMT_1280X1024P60, | |
221 | V4L2_DV_BT_DMT_1280X1024P75, | |
222 | V4L2_DV_BT_DMT_1280X1024P85, | |
223 | V4L2_DV_BT_DMT_1360X768P60, | |
224 | V4L2_DV_BT_DMT_1400X1050P60_RB, | |
225 | V4L2_DV_BT_DMT_1400X1050P60, | |
226 | V4L2_DV_BT_DMT_1400X1050P75, | |
227 | V4L2_DV_BT_DMT_1400X1050P85, | |
228 | V4L2_DV_BT_DMT_1440X900P60_RB, | |
229 | V4L2_DV_BT_DMT_1440X900P60, | |
230 | V4L2_DV_BT_DMT_1600X1200P60, | |
231 | V4L2_DV_BT_DMT_1680X1050P60_RB, | |
232 | V4L2_DV_BT_DMT_1680X1050P60, | |
233 | V4L2_DV_BT_DMT_1792X1344P60, | |
234 | V4L2_DV_BT_DMT_1856X1392P60, | |
235 | V4L2_DV_BT_DMT_1920X1200P60_RB, | |
547ed542 | 236 | V4L2_DV_BT_DMT_1366X768P60_RB, |
54450f59 HV |
237 | V4L2_DV_BT_DMT_1366X768P60, |
238 | V4L2_DV_BT_DMT_1920X1080P60, | |
239 | { }, | |
240 | }; | |
241 | ||
ccbd5bc4 HV |
242 | struct adv7604_video_standards { |
243 | struct v4l2_dv_timings timings; | |
244 | u8 vid_std; | |
245 | u8 v_freq; | |
246 | }; | |
247 | ||
248 | /* sorted by number of lines */ | |
249 | static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { | |
250 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ | |
251 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
252 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, | |
253 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, | |
254 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
255 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
256 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
257 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
258 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
259 | /* TODO add 1920x1080P60_RB (CVT timing) */ | |
260 | { }, | |
261 | }; | |
262 | ||
263 | /* sorted by number of lines */ | |
264 | static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { | |
265 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
266 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
267 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
268 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
269 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
270 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
271 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
272 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
273 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
274 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
275 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
276 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
277 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
278 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
279 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
280 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, | |
281 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, | |
282 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, | |
283 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, | |
284 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ | |
285 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ | |
286 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, | |
287 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ | |
288 | { }, | |
289 | }; | |
290 | ||
291 | /* sorted by number of lines */ | |
292 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { | |
293 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, | |
294 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
295 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, | |
296 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, | |
297 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
298 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
299 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
300 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
301 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
302 | { }, | |
303 | }; | |
304 | ||
305 | /* sorted by number of lines */ | |
306 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { | |
307 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
308 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
309 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
310 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
311 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
312 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
313 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
314 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
315 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
316 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
317 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
318 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
319 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
320 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
321 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
322 | { }, | |
323 | }; | |
324 | ||
54450f59 HV |
325 | /* ----------------------------------------------------------------------- */ |
326 | ||
327 | static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) | |
328 | { | |
329 | return container_of(sd, struct adv7604_state, sd); | |
330 | } | |
331 | ||
54450f59 HV |
332 | static inline unsigned hblanking(const struct v4l2_bt_timings *t) |
333 | { | |
eacf8f9a | 334 | return V4L2_DV_BT_BLANKING_WIDTH(t); |
54450f59 HV |
335 | } |
336 | ||
337 | static inline unsigned htotal(const struct v4l2_bt_timings *t) | |
338 | { | |
eacf8f9a | 339 | return V4L2_DV_BT_FRAME_WIDTH(t); |
54450f59 HV |
340 | } |
341 | ||
342 | static inline unsigned vblanking(const struct v4l2_bt_timings *t) | |
343 | { | |
eacf8f9a | 344 | return V4L2_DV_BT_BLANKING_HEIGHT(t); |
54450f59 HV |
345 | } |
346 | ||
347 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) | |
348 | { | |
eacf8f9a | 349 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
54450f59 HV |
350 | } |
351 | ||
352 | /* ----------------------------------------------------------------------- */ | |
353 | ||
354 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, | |
355 | u8 command, bool check) | |
356 | { | |
357 | union i2c_smbus_data data; | |
358 | ||
359 | if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
360 | I2C_SMBUS_READ, command, | |
361 | I2C_SMBUS_BYTE_DATA, &data)) | |
362 | return data.byte; | |
363 | if (check) | |
364 | v4l_err(client, "error reading %02x, %02x\n", | |
365 | client->addr, command); | |
366 | return -EIO; | |
367 | } | |
368 | ||
05cacb17 LP |
369 | static s32 adv_smbus_read_byte_data(struct adv7604_state *state, |
370 | enum adv7604_page page, u8 command) | |
54450f59 | 371 | { |
05cacb17 LP |
372 | return adv_smbus_read_byte_data_check(state->i2c_clients[page], |
373 | command, true); | |
54450f59 HV |
374 | } |
375 | ||
05cacb17 LP |
376 | static s32 adv_smbus_write_byte_data(struct adv7604_state *state, |
377 | enum adv7604_page page, u8 command, | |
378 | u8 value) | |
54450f59 | 379 | { |
05cacb17 | 380 | struct i2c_client *client = state->i2c_clients[page]; |
54450f59 HV |
381 | union i2c_smbus_data data; |
382 | int err; | |
383 | int i; | |
384 | ||
385 | data.byte = value; | |
386 | for (i = 0; i < 3; i++) { | |
387 | err = i2c_smbus_xfer(client->adapter, client->addr, | |
388 | client->flags, | |
389 | I2C_SMBUS_WRITE, command, | |
390 | I2C_SMBUS_BYTE_DATA, &data); | |
391 | if (!err) | |
392 | break; | |
393 | } | |
394 | if (err < 0) | |
395 | v4l_err(client, "error writing %02x, %02x, %02x\n", | |
396 | client->addr, command, value); | |
397 | return err; | |
398 | } | |
399 | ||
05cacb17 LP |
400 | static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state, |
401 | enum adv7604_page page, u8 command, | |
402 | unsigned length, const u8 *values) | |
54450f59 | 403 | { |
05cacb17 | 404 | struct i2c_client *client = state->i2c_clients[page]; |
54450f59 HV |
405 | union i2c_smbus_data data; |
406 | ||
407 | if (length > I2C_SMBUS_BLOCK_MAX) | |
408 | length = I2C_SMBUS_BLOCK_MAX; | |
409 | data.block[0] = length; | |
410 | memcpy(data.block + 1, values, length); | |
411 | return i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
412 | I2C_SMBUS_WRITE, command, | |
413 | I2C_SMBUS_I2C_BLOCK_DATA, &data); | |
414 | } | |
415 | ||
416 | /* ----------------------------------------------------------------------- */ | |
417 | ||
418 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) | |
419 | { | |
05cacb17 | 420 | struct adv7604_state *state = to_state(sd); |
54450f59 | 421 | |
05cacb17 | 422 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg); |
54450f59 HV |
423 | } |
424 | ||
425 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
426 | { | |
05cacb17 | 427 | struct adv7604_state *state = to_state(sd); |
54450f59 | 428 | |
05cacb17 | 429 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val); |
54450f59 HV |
430 | } |
431 | ||
22d97e56 | 432 | static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 433 | { |
22d97e56 | 434 | return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); |
54450f59 HV |
435 | } |
436 | ||
437 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) | |
438 | { | |
439 | struct adv7604_state *state = to_state(sd); | |
440 | ||
05cacb17 | 441 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); |
54450f59 HV |
442 | } |
443 | ||
444 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
445 | { | |
446 | struct adv7604_state *state = to_state(sd); | |
447 | ||
05cacb17 | 448 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); |
54450f59 HV |
449 | } |
450 | ||
451 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) | |
452 | { | |
453 | struct adv7604_state *state = to_state(sd); | |
454 | ||
05cacb17 | 455 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg); |
54450f59 HV |
456 | } |
457 | ||
458 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
459 | { | |
460 | struct adv7604_state *state = to_state(sd); | |
461 | ||
05cacb17 | 462 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val); |
54450f59 HV |
463 | } |
464 | ||
22d97e56 | 465 | static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 466 | { |
22d97e56 | 467 | return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); |
54450f59 HV |
468 | } |
469 | ||
470 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) | |
471 | { | |
472 | struct adv7604_state *state = to_state(sd); | |
473 | ||
05cacb17 | 474 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg); |
54450f59 HV |
475 | } |
476 | ||
477 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
478 | { | |
479 | struct adv7604_state *state = to_state(sd); | |
480 | ||
05cacb17 LP |
481 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME, |
482 | reg, val); | |
54450f59 HV |
483 | } |
484 | ||
485 | static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) | |
486 | { | |
487 | struct adv7604_state *state = to_state(sd); | |
488 | ||
05cacb17 | 489 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg); |
54450f59 HV |
490 | } |
491 | ||
492 | static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
493 | { | |
494 | struct adv7604_state *state = to_state(sd); | |
495 | ||
05cacb17 | 496 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val); |
54450f59 HV |
497 | } |
498 | ||
499 | static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) | |
500 | { | |
501 | struct adv7604_state *state = to_state(sd); | |
502 | ||
05cacb17 | 503 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg); |
54450f59 HV |
504 | } |
505 | ||
506 | static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
507 | { | |
508 | struct adv7604_state *state = to_state(sd); | |
509 | ||
05cacb17 | 510 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val); |
54450f59 HV |
511 | } |
512 | ||
513 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) | |
514 | { | |
515 | struct adv7604_state *state = to_state(sd); | |
516 | ||
05cacb17 | 517 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg); |
54450f59 HV |
518 | } |
519 | ||
520 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
521 | { | |
522 | struct adv7604_state *state = to_state(sd); | |
523 | ||
05cacb17 | 524 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val); |
54450f59 HV |
525 | } |
526 | ||
527 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) | |
528 | { | |
529 | struct adv7604_state *state = to_state(sd); | |
530 | ||
05cacb17 | 531 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg); |
54450f59 HV |
532 | } |
533 | ||
534 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
535 | { | |
536 | struct adv7604_state *state = to_state(sd); | |
537 | ||
05cacb17 | 538 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val); |
54450f59 HV |
539 | } |
540 | ||
22d97e56 | 541 | static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 542 | { |
22d97e56 | 543 | return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); |
54450f59 HV |
544 | } |
545 | ||
546 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) | |
547 | { | |
548 | struct adv7604_state *state = to_state(sd); | |
549 | ||
05cacb17 | 550 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg); |
54450f59 HV |
551 | } |
552 | ||
553 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
554 | { | |
555 | struct adv7604_state *state = to_state(sd); | |
556 | ||
05cacb17 | 557 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val); |
54450f59 HV |
558 | } |
559 | ||
560 | static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) | |
561 | { | |
562 | struct adv7604_state *state = to_state(sd); | |
05cacb17 | 563 | struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID]; |
54450f59 HV |
564 | u8 msgbuf0[1] = { 0 }; |
565 | u8 msgbuf1[256]; | |
09f29673 S |
566 | struct i2c_msg msg[2] = { |
567 | { | |
568 | .addr = client->addr, | |
569 | .len = 1, | |
570 | .buf = msgbuf0 | |
571 | }, | |
572 | { | |
573 | .addr = client->addr, | |
574 | .flags = I2C_M_RD, | |
575 | .len = len, | |
576 | .buf = msgbuf1 | |
577 | }, | |
578 | }; | |
54450f59 HV |
579 | |
580 | if (i2c_transfer(client->adapter, msg, 2) < 0) | |
581 | return -EIO; | |
582 | memcpy(val, msgbuf1, len); | |
583 | return 0; | |
584 | } | |
585 | ||
54450f59 HV |
586 | static inline int edid_write_block(struct v4l2_subdev *sd, |
587 | unsigned len, const u8 *val) | |
588 | { | |
54450f59 HV |
589 | struct adv7604_state *state = to_state(sd); |
590 | int err = 0; | |
591 | int i; | |
592 | ||
593 | v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); | |
594 | ||
54450f59 | 595 | for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) |
05cacb17 LP |
596 | err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID, |
597 | i, I2C_SMBUS_BLOCK_MAX, val + i); | |
dd08beb9 MR |
598 | return err; |
599 | } | |
54450f59 | 600 | |
dd08beb9 MR |
601 | static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) |
602 | { | |
603 | struct delayed_work *dwork = to_delayed_work(work); | |
604 | struct adv7604_state *state = container_of(dwork, struct adv7604_state, | |
605 | delayed_work_enable_hotplug); | |
606 | struct v4l2_subdev *sd = &state->sd; | |
54450f59 | 607 | |
dd08beb9 | 608 | v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); |
54450f59 | 609 | |
dd08beb9 | 610 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); |
54450f59 HV |
611 | } |
612 | ||
613 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) | |
614 | { | |
615 | struct adv7604_state *state = to_state(sd); | |
616 | ||
05cacb17 | 617 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg); |
54450f59 HV |
618 | } |
619 | ||
51182a94 LP |
620 | static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
621 | { | |
622 | return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; | |
623 | } | |
624 | ||
54450f59 HV |
625 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
626 | { | |
627 | struct adv7604_state *state = to_state(sd); | |
628 | ||
05cacb17 | 629 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val); |
54450f59 HV |
630 | } |
631 | ||
22d97e56 | 632 | static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
4a31a93a | 633 | { |
22d97e56 | 634 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); |
4a31a93a MR |
635 | } |
636 | ||
54450f59 HV |
637 | static inline int test_read(struct v4l2_subdev *sd, u8 reg) |
638 | { | |
639 | struct adv7604_state *state = to_state(sd); | |
640 | ||
05cacb17 | 641 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg); |
54450f59 HV |
642 | } |
643 | ||
644 | static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
645 | { | |
646 | struct adv7604_state *state = to_state(sd); | |
647 | ||
05cacb17 | 648 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val); |
54450f59 HV |
649 | } |
650 | ||
651 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) | |
652 | { | |
653 | struct adv7604_state *state = to_state(sd); | |
654 | ||
05cacb17 | 655 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg); |
54450f59 HV |
656 | } |
657 | ||
51182a94 LP |
658 | static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
659 | { | |
660 | return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; | |
661 | } | |
662 | ||
54450f59 HV |
663 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
664 | { | |
665 | struct adv7604_state *state = to_state(sd); | |
666 | ||
05cacb17 | 667 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val); |
54450f59 HV |
668 | } |
669 | ||
22d97e56 | 670 | static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 671 | { |
22d97e56 | 672 | return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); |
54450f59 HV |
673 | } |
674 | ||
675 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) | |
676 | { | |
677 | struct adv7604_state *state = to_state(sd); | |
678 | ||
05cacb17 | 679 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); |
54450f59 HV |
680 | } |
681 | ||
682 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
683 | { | |
684 | struct adv7604_state *state = to_state(sd); | |
685 | ||
05cacb17 LP |
686 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); |
687 | } | |
d42010a1 LPC |
688 | |
689 | #define ADV7604_REG(page, offset) (((page) << 8) | (offset)) | |
690 | #define ADV7604_REG_SEQ_TERM 0xffff | |
691 | ||
692 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
693 | static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) | |
694 | { | |
695 | struct adv7604_state *state = to_state(sd); | |
696 | unsigned int page = reg >> 8; | |
697 | ||
698 | if (!(BIT(page) & state->info->page_mask)) | |
699 | return -EINVAL; | |
700 | ||
701 | reg &= 0xff; | |
702 | ||
05cacb17 | 703 | return adv_smbus_read_byte_data(state, page, reg); |
d42010a1 LPC |
704 | } |
705 | #endif | |
706 | ||
707 | static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) | |
708 | { | |
709 | struct adv7604_state *state = to_state(sd); | |
710 | unsigned int page = reg >> 8; | |
711 | ||
712 | if (!(BIT(page) & state->info->page_mask)) | |
713 | return -EINVAL; | |
714 | ||
715 | reg &= 0xff; | |
716 | ||
05cacb17 | 717 | return adv_smbus_write_byte_data(state, page, reg, val); |
d42010a1 LPC |
718 | } |
719 | ||
720 | static void adv7604_write_reg_seq(struct v4l2_subdev *sd, | |
721 | const struct adv7604_reg_seq *reg_seq) | |
722 | { | |
723 | unsigned int i; | |
724 | ||
725 | for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) | |
726 | adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); | |
727 | } | |
728 | ||
539b33b0 LP |
729 | /* ----------------------------------------------------------------------------- |
730 | * Format helpers | |
731 | */ | |
732 | ||
733 | static const struct adv7604_format_info adv7604_formats[] = { | |
734 | { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, | |
735 | ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
736 | { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, | |
737 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
738 | { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, | |
739 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
740 | { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, | |
741 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
742 | { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, | |
743 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
744 | { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, | |
745 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
746 | { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, | |
747 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
748 | { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, | |
749 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
750 | { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, | |
751 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
752 | { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, | |
753 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
754 | { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, | |
755 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
756 | { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, | |
757 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
758 | { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, | |
759 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
760 | { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, | |
761 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
762 | { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, | |
763 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
764 | { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, | |
765 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
766 | { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, | |
767 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
768 | { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, | |
769 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
770 | { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, | |
771 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
772 | }; | |
773 | ||
774 | static const struct adv7604_format_info adv7611_formats[] = { | |
775 | { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, | |
776 | ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
777 | { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, | |
778 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
779 | { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, | |
780 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
781 | { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, | |
782 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
783 | { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, | |
784 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
785 | { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, | |
786 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
787 | { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, | |
788 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
789 | { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, | |
790 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
791 | { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, | |
792 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
793 | { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, | |
794 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
795 | { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, | |
796 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
797 | { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, | |
798 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
799 | { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, | |
800 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
801 | }; | |
802 | ||
803 | static const struct adv7604_format_info * | |
804 | adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code) | |
805 | { | |
806 | unsigned int i; | |
807 | ||
808 | for (i = 0; i < state->info->nformats; ++i) { | |
809 | if (state->info->formats[i].code == code) | |
810 | return &state->info->formats[i]; | |
811 | } | |
812 | ||
813 | return NULL; | |
814 | } | |
815 | ||
54450f59 HV |
816 | /* ----------------------------------------------------------------------- */ |
817 | ||
4a31a93a MR |
818 | static inline bool is_analog_input(struct v4l2_subdev *sd) |
819 | { | |
820 | struct adv7604_state *state = to_state(sd); | |
821 | ||
c784b1e2 LP |
822 | return state->selected_input == ADV7604_PAD_VGA_RGB || |
823 | state->selected_input == ADV7604_PAD_VGA_COMP; | |
4a31a93a MR |
824 | } |
825 | ||
826 | static inline bool is_digital_input(struct v4l2_subdev *sd) | |
827 | { | |
828 | struct adv7604_state *state = to_state(sd); | |
829 | ||
c784b1e2 LP |
830 | return state->selected_input == ADV7604_PAD_HDMI_PORT_A || |
831 | state->selected_input == ADV7604_PAD_HDMI_PORT_B || | |
832 | state->selected_input == ADV7604_PAD_HDMI_PORT_C || | |
833 | state->selected_input == ADV7604_PAD_HDMI_PORT_D; | |
4a31a93a MR |
834 | } |
835 | ||
836 | /* ----------------------------------------------------------------------- */ | |
837 | ||
54450f59 HV |
838 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
839 | static void adv7604_inv_register(struct v4l2_subdev *sd) | |
840 | { | |
841 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); | |
842 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); | |
843 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); | |
844 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); | |
845 | v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); | |
846 | v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); | |
847 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); | |
848 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); | |
849 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); | |
850 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); | |
851 | v4l2_info(sd, "0xa00-0xaff: Test Map\n"); | |
852 | v4l2_info(sd, "0xb00-0xbff: CP Map\n"); | |
853 | v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); | |
854 | } | |
855 | ||
856 | static int adv7604_g_register(struct v4l2_subdev *sd, | |
857 | struct v4l2_dbg_register *reg) | |
858 | { | |
d42010a1 LPC |
859 | int ret; |
860 | ||
861 | ret = adv7604_read_reg(sd, reg->reg); | |
862 | if (ret < 0) { | |
54450f59 HV |
863 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
864 | adv7604_inv_register(sd); | |
d42010a1 | 865 | return ret; |
54450f59 | 866 | } |
d42010a1 LPC |
867 | |
868 | reg->size = 1; | |
869 | reg->val = ret; | |
870 | ||
54450f59 HV |
871 | return 0; |
872 | } | |
873 | ||
874 | static int adv7604_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 875 | const struct v4l2_dbg_register *reg) |
54450f59 | 876 | { |
d42010a1 | 877 | int ret; |
1577461b | 878 | |
d42010a1 LPC |
879 | ret = adv7604_write_reg(sd, reg->reg, reg->val); |
880 | if (ret < 0) { | |
54450f59 HV |
881 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
882 | adv7604_inv_register(sd); | |
d42010a1 | 883 | return ret; |
54450f59 | 884 | } |
d42010a1 | 885 | |
54450f59 HV |
886 | return 0; |
887 | } | |
888 | #endif | |
889 | ||
d42010a1 LPC |
890 | static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) |
891 | { | |
892 | u8 value = io_read(sd, 0x6f); | |
893 | ||
894 | return ((value & 0x10) >> 4) | |
895 | | ((value & 0x08) >> 2) | |
896 | | ((value & 0x04) << 0) | |
897 | | ((value & 0x02) << 2); | |
898 | } | |
899 | ||
900 | static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) | |
901 | { | |
902 | u8 value = io_read(sd, 0x6f); | |
903 | ||
904 | return value & 1; | |
905 | } | |
906 | ||
54450f59 HV |
907 | static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) |
908 | { | |
909 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 910 | const struct adv7604_chip_info *info = state->info; |
54450f59 | 911 | |
54450f59 | 912 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, |
d42010a1 | 913 | info->read_cable_det(sd)); |
54450f59 HV |
914 | } |
915 | ||
ccbd5bc4 HV |
916 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
917 | u8 prim_mode, | |
918 | const struct adv7604_video_standards *predef_vid_timings, | |
919 | const struct v4l2_dv_timings *timings) | |
920 | { | |
ccbd5bc4 HV |
921 | int i; |
922 | ||
923 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { | |
ef1ed8f5 | 924 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, |
4a31a93a | 925 | is_digital_input(sd) ? 250000 : 1000000)) |
ccbd5bc4 HV |
926 | continue; |
927 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ | |
928 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + | |
929 | prim_mode); /* v_freq and prim mode */ | |
930 | return 0; | |
931 | } | |
932 | ||
933 | return -1; | |
934 | } | |
935 | ||
936 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, | |
937 | struct v4l2_dv_timings *timings) | |
54450f59 | 938 | { |
ccbd5bc4 HV |
939 | struct adv7604_state *state = to_state(sd); |
940 | int err; | |
941 | ||
942 | v4l2_dbg(1, debug, sd, "%s", __func__); | |
943 | ||
d42010a1 LPC |
944 | if (adv7604_has_afe(state)) { |
945 | /* reset to default values */ | |
946 | io_write(sd, 0x16, 0x43); | |
947 | io_write(sd, 0x17, 0x5a); | |
948 | } | |
ccbd5bc4 | 949 | /* disable embedded syncs for auto graphics mode */ |
22d97e56 | 950 | cp_write_clr_set(sd, 0x81, 0x10, 0x00); |
ccbd5bc4 HV |
951 | cp_write(sd, 0x8f, 0x00); |
952 | cp_write(sd, 0x90, 0x00); | |
953 | cp_write(sd, 0xa2, 0x00); | |
954 | cp_write(sd, 0xa3, 0x00); | |
955 | cp_write(sd, 0xa4, 0x00); | |
956 | cp_write(sd, 0xa5, 0x00); | |
957 | cp_write(sd, 0xa6, 0x00); | |
958 | cp_write(sd, 0xa7, 0x00); | |
959 | cp_write(sd, 0xab, 0x00); | |
960 | cp_write(sd, 0xac, 0x00); | |
961 | ||
4a31a93a | 962 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
963 | err = find_and_set_predefined_video_timings(sd, |
964 | 0x01, adv7604_prim_mode_comp, timings); | |
965 | if (err) | |
966 | err = find_and_set_predefined_video_timings(sd, | |
967 | 0x02, adv7604_prim_mode_gr, timings); | |
4a31a93a | 968 | } else if (is_digital_input(sd)) { |
ccbd5bc4 HV |
969 | err = find_and_set_predefined_video_timings(sd, |
970 | 0x05, adv7604_prim_mode_hdmi_comp, timings); | |
971 | if (err) | |
972 | err = find_and_set_predefined_video_timings(sd, | |
973 | 0x06, adv7604_prim_mode_hdmi_gr, timings); | |
4a31a93a MR |
974 | } else { |
975 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
976 | __func__, state->selected_input); | |
ccbd5bc4 | 977 | err = -1; |
ccbd5bc4 HV |
978 | } |
979 | ||
980 | ||
981 | return err; | |
982 | } | |
983 | ||
984 | static void configure_custom_video_timings(struct v4l2_subdev *sd, | |
985 | const struct v4l2_bt_timings *bt) | |
986 | { | |
987 | struct adv7604_state *state = to_state(sd); | |
ccbd5bc4 HV |
988 | u32 width = htotal(bt); |
989 | u32 height = vtotal(bt); | |
990 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; | |
991 | u16 cp_start_eav = width - bt->hfrontporch; | |
992 | u16 cp_start_vbi = height - bt->vfrontporch; | |
993 | u16 cp_end_vbi = bt->vsync + bt->vbackporch; | |
994 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? | |
995 | ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; | |
996 | const u8 pll[2] = { | |
997 | 0xc0 | ((width >> 8) & 0x1f), | |
998 | width & 0xff | |
999 | }; | |
54450f59 HV |
1000 | |
1001 | v4l2_dbg(2, debug, sd, "%s\n", __func__); | |
1002 | ||
4a31a93a | 1003 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
1004 | /* auto graphics */ |
1005 | io_write(sd, 0x00, 0x07); /* video std */ | |
1006 | io_write(sd, 0x01, 0x02); /* prim mode */ | |
1007 | /* enable embedded syncs for auto graphics mode */ | |
22d97e56 | 1008 | cp_write_clr_set(sd, 0x81, 0x10, 0x10); |
54450f59 | 1009 | |
ccbd5bc4 | 1010 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
54450f59 HV |
1011 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
1012 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ | |
05cacb17 LP |
1013 | if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO, |
1014 | 0x16, 2, pll)) | |
54450f59 | 1015 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); |
54450f59 HV |
1016 | |
1017 | /* active video - horizontal timing */ | |
54450f59 | 1018 | cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); |
ccbd5bc4 | 1019 | cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | |
4a31a93a | 1020 | ((cp_start_eav >> 8) & 0x0f)); |
54450f59 HV |
1021 | cp_write(sd, 0xa4, cp_start_eav & 0xff); |
1022 | ||
1023 | /* active video - vertical timing */ | |
54450f59 | 1024 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); |
ccbd5bc4 | 1025 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | |
4a31a93a | 1026 | ((cp_end_vbi >> 8) & 0xf)); |
54450f59 | 1027 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); |
4a31a93a | 1028 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 1029 | /* set default prim_mode/vid_std for HDMI |
39c1cb2b | 1030 | according to [REF_03, c. 4.2] */ |
ccbd5bc4 HV |
1031 | io_write(sd, 0x00, 0x02); /* video std */ |
1032 | io_write(sd, 0x01, 0x06); /* prim mode */ | |
4a31a93a MR |
1033 | } else { |
1034 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1035 | __func__, state->selected_input); | |
54450f59 | 1036 | } |
54450f59 | 1037 | |
ccbd5bc4 HV |
1038 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); |
1039 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); | |
1040 | cp_write(sd, 0xab, (height >> 4) & 0xff); | |
1041 | cp_write(sd, 0xac, (height & 0x0f) << 4); | |
1042 | } | |
54450f59 | 1043 | |
5c6c6349 MR |
1044 | static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) |
1045 | { | |
1046 | struct adv7604_state *state = to_state(sd); | |
1047 | u8 offset_buf[4]; | |
1048 | ||
1049 | if (auto_offset) { | |
1050 | offset_a = 0x3ff; | |
1051 | offset_b = 0x3ff; | |
1052 | offset_c = 0x3ff; | |
1053 | } | |
1054 | ||
1055 | v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1056 | __func__, auto_offset ? "Auto" : "Manual", | |
1057 | offset_a, offset_b, offset_c); | |
1058 | ||
1059 | offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); | |
1060 | offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); | |
1061 | offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); | |
1062 | offset_buf[3] = offset_c & 0x0ff; | |
1063 | ||
1064 | /* Registers must be written in this order with no i2c access in between */ | |
05cacb17 LP |
1065 | if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, |
1066 | 0x77, 4, offset_buf)) | |
5c6c6349 MR |
1067 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); |
1068 | } | |
1069 | ||
1070 | static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) | |
1071 | { | |
1072 | struct adv7604_state *state = to_state(sd); | |
1073 | u8 gain_buf[4]; | |
1074 | u8 gain_man = 1; | |
1075 | u8 agc_mode_man = 1; | |
1076 | ||
1077 | if (auto_gain) { | |
1078 | gain_man = 0; | |
1079 | agc_mode_man = 0; | |
1080 | gain_a = 0x100; | |
1081 | gain_b = 0x100; | |
1082 | gain_c = 0x100; | |
1083 | } | |
1084 | ||
1085 | v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1086 | __func__, auto_gain ? "Auto" : "Manual", | |
1087 | gain_a, gain_b, gain_c); | |
1088 | ||
1089 | gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); | |
1090 | gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); | |
1091 | gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); | |
1092 | gain_buf[3] = ((gain_c & 0x0ff)); | |
1093 | ||
1094 | /* Registers must be written in this order with no i2c access in between */ | |
05cacb17 LP |
1095 | if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, |
1096 | 0x73, 4, gain_buf)) | |
5c6c6349 MR |
1097 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); |
1098 | } | |
1099 | ||
54450f59 HV |
1100 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) |
1101 | { | |
1102 | struct adv7604_state *state = to_state(sd); | |
5c6c6349 MR |
1103 | bool rgb_output = io_read(sd, 0x02) & 0x02; |
1104 | bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; | |
1105 | ||
1106 | v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", | |
1107 | __func__, state->rgb_quantization_range, | |
1108 | rgb_output, hdmi_signal); | |
54450f59 | 1109 | |
5c6c6349 MR |
1110 | adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); |
1111 | adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); | |
9833239e | 1112 | |
54450f59 HV |
1113 | switch (state->rgb_quantization_range) { |
1114 | case V4L2_DV_RGB_RANGE_AUTO: | |
c784b1e2 | 1115 | if (state->selected_input == ADV7604_PAD_VGA_RGB) { |
9833239e MR |
1116 | /* Receiving analog RGB signal |
1117 | * Set RGB full range (0-255) */ | |
22d97e56 | 1118 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
9833239e MR |
1119 | break; |
1120 | } | |
1121 | ||
c784b1e2 | 1122 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
9833239e MR |
1123 | /* Receiving analog YPbPr signal |
1124 | * Set automode */ | |
22d97e56 | 1125 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); |
9833239e MR |
1126 | break; |
1127 | } | |
1128 | ||
5c6c6349 | 1129 | if (hdmi_signal) { |
9833239e MR |
1130 | /* Receiving HDMI signal |
1131 | * Set automode */ | |
22d97e56 | 1132 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); |
9833239e MR |
1133 | break; |
1134 | } | |
1135 | ||
1136 | /* Receiving DVI-D signal | |
1137 | * ADV7604 selects RGB limited range regardless of | |
1138 | * input format (CE/IT) in automatic mode */ | |
1139 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { | |
1140 | /* RGB limited range (16-235) */ | |
22d97e56 | 1141 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); |
9833239e MR |
1142 | } else { |
1143 | /* RGB full range (0-255) */ | |
22d97e56 | 1144 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
5c6c6349 MR |
1145 | |
1146 | if (is_digital_input(sd) && rgb_output) { | |
1147 | adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); | |
1148 | } else { | |
1149 | adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); | |
1150 | adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); | |
1151 | } | |
54450f59 HV |
1152 | } |
1153 | break; | |
1154 | case V4L2_DV_RGB_RANGE_LIMITED: | |
c784b1e2 | 1155 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 | 1156 | /* YCrCb limited range (16-235) */ |
22d97e56 | 1157 | io_write_clr_set(sd, 0x02, 0xf0, 0x20); |
5c6c6349 | 1158 | break; |
d261e842 | 1159 | } |
5c6c6349 MR |
1160 | |
1161 | /* RGB limited range (16-235) */ | |
22d97e56 | 1162 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); |
5c6c6349 | 1163 | |
54450f59 HV |
1164 | break; |
1165 | case V4L2_DV_RGB_RANGE_FULL: | |
c784b1e2 | 1166 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 | 1167 | /* YCrCb full range (0-255) */ |
22d97e56 | 1168 | io_write_clr_set(sd, 0x02, 0xf0, 0x60); |
5c6c6349 MR |
1169 | break; |
1170 | } | |
1171 | ||
1172 | /* RGB full range (0-255) */ | |
22d97e56 | 1173 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
5c6c6349 MR |
1174 | |
1175 | if (is_analog_input(sd) || hdmi_signal) | |
1176 | break; | |
1177 | ||
1178 | /* Adjust gain/offset for DVI-D signals only */ | |
1179 | if (rgb_output) { | |
1180 | adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); | |
d261e842 | 1181 | } else { |
5c6c6349 MR |
1182 | adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); |
1183 | adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); | |
d261e842 | 1184 | } |
54450f59 HV |
1185 | break; |
1186 | } | |
1187 | } | |
1188 | ||
54450f59 HV |
1189 | static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) |
1190 | { | |
c269887c LP |
1191 | struct v4l2_subdev *sd = |
1192 | &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; | |
1193 | ||
54450f59 HV |
1194 | struct adv7604_state *state = to_state(sd); |
1195 | ||
1196 | switch (ctrl->id) { | |
1197 | case V4L2_CID_BRIGHTNESS: | |
1198 | cp_write(sd, 0x3c, ctrl->val); | |
1199 | return 0; | |
1200 | case V4L2_CID_CONTRAST: | |
1201 | cp_write(sd, 0x3a, ctrl->val); | |
1202 | return 0; | |
1203 | case V4L2_CID_SATURATION: | |
1204 | cp_write(sd, 0x3b, ctrl->val); | |
1205 | return 0; | |
1206 | case V4L2_CID_HUE: | |
1207 | cp_write(sd, 0x3d, ctrl->val); | |
1208 | return 0; | |
1209 | case V4L2_CID_DV_RX_RGB_RANGE: | |
1210 | state->rgb_quantization_range = ctrl->val; | |
1211 | set_rgb_quantization_range(sd); | |
1212 | return 0; | |
1213 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: | |
d42010a1 LPC |
1214 | if (!adv7604_has_afe(state)) |
1215 | return -EINVAL; | |
54450f59 HV |
1216 | /* Set the analog sampling phase. This is needed to find the |
1217 | best sampling phase for analog video: an application or | |
1218 | driver has to try a number of phases and analyze the picture | |
1219 | quality before settling on the best performing phase. */ | |
1220 | afe_write(sd, 0xc8, ctrl->val); | |
1221 | return 0; | |
1222 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: | |
1223 | /* Use the default blue color for free running mode, | |
1224 | or supply your own. */ | |
22d97e56 | 1225 | cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); |
54450f59 HV |
1226 | return 0; |
1227 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: | |
1228 | cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); | |
1229 | cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); | |
1230 | cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); | |
1231 | return 0; | |
1232 | } | |
1233 | return -EINVAL; | |
1234 | } | |
1235 | ||
54450f59 HV |
1236 | /* ----------------------------------------------------------------------- */ |
1237 | ||
1238 | static inline bool no_power(struct v4l2_subdev *sd) | |
1239 | { | |
1240 | /* Entire chip or CP powered off */ | |
1241 | return io_read(sd, 0x0c) & 0x24; | |
1242 | } | |
1243 | ||
1244 | static inline bool no_signal_tmds(struct v4l2_subdev *sd) | |
1245 | { | |
4a31a93a MR |
1246 | struct adv7604_state *state = to_state(sd); |
1247 | ||
1248 | return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); | |
54450f59 HV |
1249 | } |
1250 | ||
1251 | static inline bool no_lock_tmds(struct v4l2_subdev *sd) | |
1252 | { | |
d42010a1 LPC |
1253 | struct adv7604_state *state = to_state(sd); |
1254 | const struct adv7604_chip_info *info = state->info; | |
1255 | ||
1256 | return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; | |
54450f59 HV |
1257 | } |
1258 | ||
bb88f325 MB |
1259 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
1260 | { | |
1261 | return hdmi_read(sd, 0x05) & 0x80; | |
1262 | } | |
1263 | ||
54450f59 HV |
1264 | static inline bool no_lock_sspd(struct v4l2_subdev *sd) |
1265 | { | |
d42010a1 LPC |
1266 | struct adv7604_state *state = to_state(sd); |
1267 | ||
1268 | /* | |
1269 | * Chips without a AFE don't expose registers for the SSPD, so just assume | |
1270 | * that we have a lock. | |
1271 | */ | |
1272 | if (adv7604_has_afe(state)) | |
1273 | return false; | |
1274 | ||
54450f59 HV |
1275 | /* TODO channel 2 */ |
1276 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); | |
1277 | } | |
1278 | ||
1279 | static inline bool no_lock_stdi(struct v4l2_subdev *sd) | |
1280 | { | |
1281 | /* TODO channel 2 */ | |
1282 | return !(cp_read(sd, 0xb1) & 0x80); | |
1283 | } | |
1284 | ||
1285 | static inline bool no_signal(struct v4l2_subdev *sd) | |
1286 | { | |
54450f59 HV |
1287 | bool ret; |
1288 | ||
1289 | ret = no_power(sd); | |
1290 | ||
1291 | ret |= no_lock_stdi(sd); | |
1292 | ret |= no_lock_sspd(sd); | |
1293 | ||
4a31a93a | 1294 | if (is_digital_input(sd)) { |
54450f59 HV |
1295 | ret |= no_lock_tmds(sd); |
1296 | ret |= no_signal_tmds(sd); | |
1297 | } | |
1298 | ||
1299 | return ret; | |
1300 | } | |
1301 | ||
1302 | static inline bool no_lock_cp(struct v4l2_subdev *sd) | |
1303 | { | |
d42010a1 LPC |
1304 | struct adv7604_state *state = to_state(sd); |
1305 | ||
1306 | if (!adv7604_has_afe(state)) | |
1307 | return false; | |
1308 | ||
54450f59 HV |
1309 | /* CP has detected a non standard number of lines on the incoming |
1310 | video compared to what it is configured to receive by s_dv_timings */ | |
1311 | return io_read(sd, 0x12) & 0x01; | |
1312 | } | |
1313 | ||
1314 | static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) | |
1315 | { | |
54450f59 HV |
1316 | *status = 0; |
1317 | *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; | |
1318 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; | |
1319 | if (no_lock_cp(sd)) | |
4a31a93a | 1320 | *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; |
54450f59 HV |
1321 | |
1322 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | /* ----------------------------------------------------------------------- */ | |
1328 | ||
54450f59 HV |
1329 | struct stdi_readback { |
1330 | u16 bl, lcf, lcvs; | |
1331 | u8 hs_pol, vs_pol; | |
1332 | bool interlaced; | |
1333 | }; | |
1334 | ||
1335 | static int stdi2dv_timings(struct v4l2_subdev *sd, | |
1336 | struct stdi_readback *stdi, | |
1337 | struct v4l2_dv_timings *timings) | |
1338 | { | |
1339 | struct adv7604_state *state = to_state(sd); | |
1340 | u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; | |
1341 | u32 pix_clk; | |
1342 | int i; | |
1343 | ||
1344 | for (i = 0; adv7604_timings[i].bt.height; i++) { | |
1345 | if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) | |
1346 | continue; | |
1347 | if (adv7604_timings[i].bt.vsync != stdi->lcvs) | |
1348 | continue; | |
1349 | ||
1350 | pix_clk = hfreq * htotal(&adv7604_timings[i].bt); | |
1351 | ||
1352 | if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && | |
1353 | (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { | |
1354 | *timings = adv7604_timings[i]; | |
1355 | return 0; | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1360 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1361 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1362 | timings)) | |
1363 | return 0; | |
1364 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1365 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1366 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1367 | state->aspect_ratio, timings)) | |
1368 | return 0; | |
1369 | ||
ccbd5bc4 HV |
1370 | v4l2_dbg(2, debug, sd, |
1371 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", | |
1372 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, | |
1373 | stdi->hs_pol, stdi->vs_pol); | |
54450f59 HV |
1374 | return -1; |
1375 | } | |
1376 | ||
d42010a1 | 1377 | |
54450f59 HV |
1378 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) |
1379 | { | |
d42010a1 LPC |
1380 | struct adv7604_state *state = to_state(sd); |
1381 | const struct adv7604_chip_info *info = state->info; | |
4a2ccdd2 LP |
1382 | u8 polarity; |
1383 | ||
54450f59 HV |
1384 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { |
1385 | v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); | |
1386 | return -1; | |
1387 | } | |
1388 | ||
1389 | /* read STDI */ | |
51182a94 | 1390 | stdi->bl = cp_read16(sd, 0xb1, 0x3fff); |
d42010a1 | 1391 | stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); |
54450f59 HV |
1392 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; |
1393 | stdi->interlaced = io_read(sd, 0x12) & 0x10; | |
1394 | ||
d42010a1 LPC |
1395 | if (adv7604_has_afe(state)) { |
1396 | /* read SSPD */ | |
1397 | polarity = cp_read(sd, 0xb5); | |
1398 | if ((polarity & 0x03) == 0x01) { | |
1399 | stdi->hs_pol = polarity & 0x10 | |
1400 | ? (polarity & 0x08 ? '+' : '-') : 'x'; | |
1401 | stdi->vs_pol = polarity & 0x40 | |
1402 | ? (polarity & 0x20 ? '+' : '-') : 'x'; | |
1403 | } else { | |
1404 | stdi->hs_pol = 'x'; | |
1405 | stdi->vs_pol = 'x'; | |
1406 | } | |
54450f59 | 1407 | } else { |
d42010a1 LPC |
1408 | polarity = hdmi_read(sd, 0x05); |
1409 | stdi->hs_pol = polarity & 0x20 ? '+' : '-'; | |
1410 | stdi->vs_pol = polarity & 0x10 ? '+' : '-'; | |
54450f59 HV |
1411 | } |
1412 | ||
1413 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1414 | v4l2_dbg(2, debug, sd, | |
1415 | "%s: signal lost during readout of STDI/SSPD\n", __func__); | |
1416 | return -1; | |
1417 | } | |
1418 | ||
1419 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { | |
1420 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); | |
1421 | memset(stdi, 0, sizeof(struct stdi_readback)); | |
1422 | return -1; | |
1423 | } | |
1424 | ||
1425 | v4l2_dbg(2, debug, sd, | |
1426 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", | |
1427 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, | |
1428 | stdi->hs_pol, stdi->vs_pol, | |
1429 | stdi->interlaced ? "interlaced" : "progressive"); | |
1430 | ||
1431 | return 0; | |
1432 | } | |
1433 | ||
1434 | static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, | |
1435 | struct v4l2_enum_dv_timings *timings) | |
1436 | { | |
afec5599 LP |
1437 | struct adv7604_state *state = to_state(sd); |
1438 | ||
54450f59 HV |
1439 | if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) |
1440 | return -EINVAL; | |
afec5599 LP |
1441 | |
1442 | if (timings->pad >= state->source_pad) | |
1443 | return -EINVAL; | |
1444 | ||
54450f59 HV |
1445 | memset(timings->reserved, 0, sizeof(timings->reserved)); |
1446 | timings->timings = adv7604_timings[timings->index]; | |
1447 | return 0; | |
1448 | } | |
1449 | ||
7515e096 LP |
1450 | static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, |
1451 | struct v4l2_dv_timings_cap *cap) | |
54450f59 | 1452 | { |
7515e096 LP |
1453 | struct adv7604_state *state = to_state(sd); |
1454 | ||
1455 | if (cap->pad >= state->source_pad) | |
1456 | return -EINVAL; | |
1457 | ||
54450f59 HV |
1458 | cap->type = V4L2_DV_BT_656_1120; |
1459 | cap->bt.max_width = 1920; | |
1460 | cap->bt.max_height = 1200; | |
fe9c2564 | 1461 | cap->bt.min_pixelclock = 25000000; |
afec5599 | 1462 | |
7515e096 | 1463 | switch (cap->pad) { |
afec5599 LP |
1464 | case ADV7604_PAD_HDMI_PORT_A: |
1465 | case ADV7604_PAD_HDMI_PORT_B: | |
1466 | case ADV7604_PAD_HDMI_PORT_C: | |
1467 | case ADV7604_PAD_HDMI_PORT_D: | |
54450f59 | 1468 | cap->bt.max_pixelclock = 225000000; |
afec5599 LP |
1469 | break; |
1470 | case ADV7604_PAD_VGA_RGB: | |
1471 | case ADV7604_PAD_VGA_COMP: | |
1472 | default: | |
54450f59 | 1473 | cap->bt.max_pixelclock = 170000000; |
afec5599 LP |
1474 | break; |
1475 | } | |
1476 | ||
54450f59 HV |
1477 | cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
1478 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; | |
1479 | cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | | |
1480 | V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; | |
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings | |
1485 | if the format is listed in adv7604_timings[] */ | |
1486 | static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, | |
1487 | struct v4l2_dv_timings *timings) | |
1488 | { | |
54450f59 HV |
1489 | int i; |
1490 | ||
1491 | for (i = 0; adv7604_timings[i].bt.width; i++) { | |
ef1ed8f5 | 1492 | if (v4l2_match_dv_timings(timings, &adv7604_timings[i], |
4a31a93a | 1493 | is_digital_input(sd) ? 250000 : 1000000)) { |
54450f59 HV |
1494 | *timings = adv7604_timings[i]; |
1495 | break; | |
1496 | } | |
1497 | } | |
1498 | } | |
1499 | ||
d42010a1 LPC |
1500 | static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) |
1501 | { | |
1502 | unsigned int freq; | |
1503 | int a, b; | |
1504 | ||
1505 | a = hdmi_read(sd, 0x06); | |
1506 | b = hdmi_read(sd, 0x3b); | |
1507 | if (a < 0 || b < 0) | |
1508 | return 0; | |
1509 | freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; | |
1510 | ||
1511 | if (is_hdmi(sd)) { | |
1512 | /* adjust for deep color mode */ | |
1513 | unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; | |
1514 | ||
1515 | freq = freq * 8 / bits_per_channel; | |
1516 | } | |
1517 | ||
1518 | return freq; | |
1519 | } | |
1520 | ||
1521 | static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) | |
1522 | { | |
1523 | int a, b; | |
1524 | ||
1525 | a = hdmi_read(sd, 0x51); | |
1526 | b = hdmi_read(sd, 0x52); | |
1527 | if (a < 0 || b < 0) | |
1528 | return 0; | |
1529 | return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; | |
1530 | } | |
1531 | ||
54450f59 HV |
1532 | static int adv7604_query_dv_timings(struct v4l2_subdev *sd, |
1533 | struct v4l2_dv_timings *timings) | |
1534 | { | |
1535 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 1536 | const struct adv7604_chip_info *info = state->info; |
54450f59 HV |
1537 | struct v4l2_bt_timings *bt = &timings->bt; |
1538 | struct stdi_readback stdi; | |
1539 | ||
1540 | if (!timings) | |
1541 | return -EINVAL; | |
1542 | ||
1543 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1544 | ||
1545 | if (no_signal(sd)) { | |
1e0b9156 | 1546 | state->restart_stdi_once = true; |
54450f59 HV |
1547 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); |
1548 | return -ENOLINK; | |
1549 | } | |
1550 | ||
1551 | /* read STDI */ | |
1552 | if (read_stdi(sd, &stdi)) { | |
1553 | v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); | |
1554 | return -ENOLINK; | |
1555 | } | |
1556 | bt->interlaced = stdi.interlaced ? | |
1557 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; | |
1558 | ||
4a31a93a | 1559 | if (is_digital_input(sd)) { |
54450f59 HV |
1560 | timings->type = V4L2_DV_BT_656_1120; |
1561 | ||
d42010a1 | 1562 | /* FIXME: All masks are incorrect for ADV7611 */ |
51182a94 LP |
1563 | bt->width = hdmi_read16(sd, 0x07, 0xfff); |
1564 | bt->height = hdmi_read16(sd, 0x09, 0xfff); | |
d42010a1 | 1565 | bt->pixelclock = info->read_hdmi_pixelclock(sd); |
51182a94 LP |
1566 | bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff); |
1567 | bt->hsync = hdmi_read16(sd, 0x22, 0x3ff); | |
1568 | bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff); | |
1569 | bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2; | |
1570 | bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2; | |
1571 | bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2; | |
54450f59 HV |
1572 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | |
1573 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); | |
1574 | if (bt->interlaced == V4L2_DV_INTERLACED) { | |
51182a94 LP |
1575 | bt->height += hdmi_read16(sd, 0x0b, 0xfff); |
1576 | bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2; | |
1577 | bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; | |
1578 | bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; | |
54450f59 HV |
1579 | } |
1580 | adv7604_fill_optional_dv_timings_fields(sd, timings); | |
1581 | } else { | |
1582 | /* find format | |
80939647 | 1583 | * Since LCVS values are inaccurate [REF_03, p. 275-276], |
54450f59 HV |
1584 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. |
1585 | */ | |
1586 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1587 | goto found; | |
1588 | stdi.lcvs += 1; | |
1589 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); | |
1590 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1591 | goto found; | |
1592 | stdi.lcvs -= 2; | |
1593 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); | |
1594 | if (stdi2dv_timings(sd, &stdi, timings)) { | |
cf9afb1d HV |
1595 | /* |
1596 | * The STDI block may measure wrong values, especially | |
1597 | * for lcvs and lcf. If the driver can not find any | |
1598 | * valid timing, the STDI block is restarted to measure | |
1599 | * the video timings again. The function will return an | |
1600 | * error, but the restart of STDI will generate a new | |
1601 | * STDI interrupt and the format detection process will | |
1602 | * restart. | |
1603 | */ | |
1604 | if (state->restart_stdi_once) { | |
1605 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); | |
1606 | /* TODO restart STDI for Sync Channel 2 */ | |
1607 | /* enter one-shot mode */ | |
22d97e56 | 1608 | cp_write_clr_set(sd, 0x86, 0x06, 0x00); |
cf9afb1d | 1609 | /* trigger STDI restart */ |
22d97e56 | 1610 | cp_write_clr_set(sd, 0x86, 0x06, 0x04); |
cf9afb1d | 1611 | /* reset to continuous mode */ |
22d97e56 | 1612 | cp_write_clr_set(sd, 0x86, 0x06, 0x02); |
cf9afb1d HV |
1613 | state->restart_stdi_once = false; |
1614 | return -ENOLINK; | |
1615 | } | |
54450f59 HV |
1616 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); |
1617 | return -ERANGE; | |
1618 | } | |
cf9afb1d | 1619 | state->restart_stdi_once = true; |
54450f59 HV |
1620 | } |
1621 | found: | |
1622 | ||
1623 | if (no_signal(sd)) { | |
1624 | v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); | |
1625 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1626 | return -ENOLINK; | |
1627 | } | |
1628 | ||
4a31a93a MR |
1629 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1630 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1631 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1632 | __func__, (u32)bt->pixelclock); | |
1633 | return -ERANGE; | |
1634 | } | |
1635 | ||
1636 | if (debug > 1) | |
11d034c8 HV |
1637 | v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", |
1638 | timings, true); | |
54450f59 HV |
1639 | |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | static int adv7604_s_dv_timings(struct v4l2_subdev *sd, | |
1644 | struct v4l2_dv_timings *timings) | |
1645 | { | |
1646 | struct adv7604_state *state = to_state(sd); | |
1647 | struct v4l2_bt_timings *bt; | |
ccbd5bc4 | 1648 | int err; |
54450f59 HV |
1649 | |
1650 | if (!timings) | |
1651 | return -EINVAL; | |
1652 | ||
d48eb48c MR |
1653 | if (v4l2_match_dv_timings(&state->timings, timings, 0)) { |
1654 | v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); | |
1655 | return 0; | |
1656 | } | |
1657 | ||
54450f59 HV |
1658 | bt = &timings->bt; |
1659 | ||
4a31a93a MR |
1660 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1661 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1662 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1663 | __func__, (u32)bt->pixelclock); | |
1664 | return -ERANGE; | |
1665 | } | |
ccbd5bc4 | 1666 | |
54450f59 HV |
1667 | adv7604_fill_optional_dv_timings_fields(sd, timings); |
1668 | ||
1669 | state->timings = *timings; | |
1670 | ||
22d97e56 | 1671 | cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); |
ccbd5bc4 HV |
1672 | |
1673 | /* Use prim_mode and vid_std when available */ | |
1674 | err = configure_predefined_video_timings(sd, timings); | |
1675 | if (err) { | |
1676 | /* custom settings when the video format | |
1677 | does not have prim_mode/vid_std */ | |
1678 | configure_custom_video_timings(sd, bt); | |
1679 | } | |
54450f59 HV |
1680 | |
1681 | set_rgb_quantization_range(sd); | |
1682 | ||
54450f59 | 1683 | if (debug > 1) |
11d034c8 HV |
1684 | v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", |
1685 | timings, true); | |
54450f59 HV |
1686 | return 0; |
1687 | } | |
1688 | ||
1689 | static int adv7604_g_dv_timings(struct v4l2_subdev *sd, | |
1690 | struct v4l2_dv_timings *timings) | |
1691 | { | |
1692 | struct adv7604_state *state = to_state(sd); | |
1693 | ||
1694 | *timings = state->timings; | |
1695 | return 0; | |
1696 | } | |
1697 | ||
d42010a1 LPC |
1698 | static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) |
1699 | { | |
1700 | hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); | |
1701 | } | |
1702 | ||
1703 | static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) | |
1704 | { | |
1705 | hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); | |
1706 | } | |
1707 | ||
6b0d5d34 | 1708 | static void enable_input(struct v4l2_subdev *sd) |
54450f59 | 1709 | { |
6b0d5d34 HV |
1710 | struct adv7604_state *state = to_state(sd); |
1711 | ||
4a31a93a | 1712 | if (is_analog_input(sd)) { |
54450f59 | 1713 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ |
4a31a93a | 1714 | } else if (is_digital_input(sd)) { |
22d97e56 | 1715 | hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); |
d42010a1 | 1716 | state->info->set_termination(sd, true); |
54450f59 | 1717 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ |
22d97e56 | 1718 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ |
4a31a93a MR |
1719 | } else { |
1720 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1721 | __func__, state->selected_input); | |
54450f59 HV |
1722 | } |
1723 | } | |
1724 | ||
1725 | static void disable_input(struct v4l2_subdev *sd) | |
1726 | { | |
d42010a1 LPC |
1727 | struct adv7604_state *state = to_state(sd); |
1728 | ||
22d97e56 | 1729 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ |
5474b983 | 1730 | msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ |
54450f59 | 1731 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ |
d42010a1 | 1732 | state->info->set_termination(sd, false); |
54450f59 HV |
1733 | } |
1734 | ||
6b0d5d34 | 1735 | static void select_input(struct v4l2_subdev *sd) |
54450f59 | 1736 | { |
6b0d5d34 | 1737 | struct adv7604_state *state = to_state(sd); |
d42010a1 | 1738 | const struct adv7604_chip_info *info = state->info; |
54450f59 | 1739 | |
4a31a93a | 1740 | if (is_analog_input(sd)) { |
d42010a1 | 1741 | adv7604_write_reg_seq(sd, info->recommended_settings[0]); |
54450f59 HV |
1742 | |
1743 | afe_write(sd, 0x00, 0x08); /* power up ADC */ | |
1744 | afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ | |
1745 | afe_write(sd, 0xc8, 0x00); /* phase control */ | |
4a31a93a MR |
1746 | } else if (is_digital_input(sd)) { |
1747 | hdmi_write(sd, 0x00, state->selected_input & 0x03); | |
54450f59 | 1748 | |
d42010a1 LPC |
1749 | adv7604_write_reg_seq(sd, info->recommended_settings[1]); |
1750 | ||
1751 | if (adv7604_has_afe(state)) { | |
1752 | afe_write(sd, 0x00, 0xff); /* power down ADC */ | |
1753 | afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ | |
1754 | afe_write(sd, 0xc8, 0x40); /* phase control */ | |
1755 | } | |
1756 | ||
54450f59 HV |
1757 | cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ |
1758 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1759 | cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ | |
4a31a93a MR |
1760 | } else { |
1761 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1762 | __func__, state->selected_input); | |
54450f59 HV |
1763 | } |
1764 | } | |
1765 | ||
1766 | static int adv7604_s_routing(struct v4l2_subdev *sd, | |
1767 | u32 input, u32 output, u32 config) | |
1768 | { | |
1769 | struct adv7604_state *state = to_state(sd); | |
1770 | ||
ff4f80fd MR |
1771 | v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", |
1772 | __func__, input, state->selected_input); | |
1773 | ||
1774 | if (input == state->selected_input) | |
1775 | return 0; | |
54450f59 | 1776 | |
d42010a1 LPC |
1777 | if (input > state->info->max_port) |
1778 | return -EINVAL; | |
1779 | ||
4a31a93a | 1780 | state->selected_input = input; |
54450f59 HV |
1781 | |
1782 | disable_input(sd); | |
1783 | ||
6b0d5d34 | 1784 | select_input(sd); |
54450f59 | 1785 | |
6b0d5d34 | 1786 | enable_input(sd); |
54450f59 HV |
1787 | |
1788 | return 0; | |
1789 | } | |
1790 | ||
539b33b0 LP |
1791 | static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, |
1792 | struct v4l2_subdev_fh *fh, | |
1793 | struct v4l2_subdev_mbus_code_enum *code) | |
54450f59 | 1794 | { |
539b33b0 LP |
1795 | struct adv7604_state *state = to_state(sd); |
1796 | ||
1797 | if (code->index >= state->info->nformats) | |
54450f59 | 1798 | return -EINVAL; |
539b33b0 LP |
1799 | |
1800 | code->code = state->info->formats[code->index].code; | |
1801 | ||
54450f59 HV |
1802 | return 0; |
1803 | } | |
1804 | ||
539b33b0 LP |
1805 | static void adv7604_fill_format(struct adv7604_state *state, |
1806 | struct v4l2_mbus_framefmt *format) | |
54450f59 | 1807 | { |
539b33b0 | 1808 | memset(format, 0, sizeof(*format)); |
54450f59 | 1809 | |
539b33b0 LP |
1810 | format->width = state->timings.bt.width; |
1811 | format->height = state->timings.bt.height; | |
1812 | format->field = V4L2_FIELD_NONE; | |
1813 | ||
1814 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) | |
1815 | format->colorspace = (state->timings.bt.height <= 576) ? | |
54450f59 | 1816 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; |
539b33b0 LP |
1817 | } |
1818 | ||
1819 | /* | |
1820 | * Compute the op_ch_sel value required to obtain on the bus the component order | |
1821 | * corresponding to the selected format taking into account bus reordering | |
1822 | * applied by the board at the output of the device. | |
1823 | * | |
1824 | * The following table gives the op_ch_value from the format component order | |
1825 | * (expressed as op_ch_sel value in column) and the bus reordering (expressed as | |
1826 | * adv7604_bus_order value in row). | |
1827 | * | |
1828 | * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) | |
1829 | * ----------+------------------------------------------------- | |
1830 | * RGB (NOP) | GBR GRB BGR RGB BRG RBG | |
1831 | * GRB (1-2) | BGR RGB GBR GRB RBG BRG | |
1832 | * RBG (2-3) | GRB GBR BRG RBG BGR RGB | |
1833 | * BGR (1-3) | RBG BRG RGB BGR GRB GBR | |
1834 | * BRG (ROR) | BRG RBG GRB GBR RGB BGR | |
1835 | * GBR (ROL) | RGB BGR RBG BRG GBR GRB | |
1836 | */ | |
1837 | static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) | |
1838 | { | |
1839 | #define _SEL(a,b,c,d,e,f) { \ | |
1840 | ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ | |
1841 | ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } | |
1842 | #define _BUS(x) [ADV7604_BUS_ORDER_##x] | |
1843 | ||
1844 | static const unsigned int op_ch_sel[6][6] = { | |
1845 | _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), | |
1846 | _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), | |
1847 | _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), | |
1848 | _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), | |
1849 | _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), | |
1850 | _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), | |
1851 | }; | |
1852 | ||
1853 | return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; | |
1854 | } | |
1855 | ||
1856 | static void adv7604_setup_format(struct adv7604_state *state) | |
1857 | { | |
1858 | struct v4l2_subdev *sd = &state->sd; | |
1859 | ||
22d97e56 | 1860 | io_write_clr_set(sd, 0x02, 0x02, |
539b33b0 LP |
1861 | state->format->rgb_out ? ADV7604_RGB_OUT : 0); |
1862 | io_write(sd, 0x03, state->format->op_format_sel | | |
1863 | state->pdata.op_format_mode_sel); | |
22d97e56 LP |
1864 | io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state)); |
1865 | io_write_clr_set(sd, 0x05, 0x01, | |
539b33b0 LP |
1866 | state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); |
1867 | } | |
1868 | ||
1869 | static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
1870 | struct v4l2_subdev_format *format) | |
1871 | { | |
1872 | struct adv7604_state *state = to_state(sd); | |
1873 | ||
1874 | if (format->pad != state->source_pad) | |
1875 | return -EINVAL; | |
1876 | ||
1877 | adv7604_fill_format(state, &format->format); | |
1878 | ||
1879 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1880 | struct v4l2_mbus_framefmt *fmt; | |
1881 | ||
1882 | fmt = v4l2_subdev_get_try_format(fh, format->pad); | |
1883 | format->format.code = fmt->code; | |
1884 | } else { | |
1885 | format->format.code = state->format->code; | |
54450f59 | 1886 | } |
539b33b0 LP |
1887 | |
1888 | return 0; | |
1889 | } | |
1890 | ||
1891 | static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
1892 | struct v4l2_subdev_format *format) | |
1893 | { | |
1894 | struct adv7604_state *state = to_state(sd); | |
1895 | const struct adv7604_format_info *info; | |
1896 | ||
1897 | if (format->pad != state->source_pad) | |
1898 | return -EINVAL; | |
1899 | ||
1900 | info = adv7604_format_info(state, format->format.code); | |
1901 | if (info == NULL) | |
1902 | info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); | |
1903 | ||
1904 | adv7604_fill_format(state, &format->format); | |
1905 | format->format.code = info->code; | |
1906 | ||
1907 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1908 | struct v4l2_mbus_framefmt *fmt; | |
1909 | ||
1910 | fmt = v4l2_subdev_get_try_format(fh, format->pad); | |
1911 | fmt->code = format->format.code; | |
1912 | } else { | |
1913 | state->format = info; | |
1914 | adv7604_setup_format(state); | |
1915 | } | |
1916 | ||
54450f59 HV |
1917 | return 0; |
1918 | } | |
1919 | ||
1920 | static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) | |
1921 | { | |
d42010a1 LPC |
1922 | struct adv7604_state *state = to_state(sd); |
1923 | const struct adv7604_chip_info *info = state->info; | |
f24d229c MR |
1924 | const u8 irq_reg_0x43 = io_read(sd, 0x43); |
1925 | const u8 irq_reg_0x6b = io_read(sd, 0x6b); | |
1926 | const u8 irq_reg_0x70 = io_read(sd, 0x70); | |
1927 | u8 fmt_change_digital; | |
1928 | u8 fmt_change; | |
1929 | u8 tx_5v; | |
1930 | ||
1931 | if (irq_reg_0x43) | |
1932 | io_write(sd, 0x44, irq_reg_0x43); | |
1933 | if (irq_reg_0x70) | |
1934 | io_write(sd, 0x71, irq_reg_0x70); | |
1935 | if (irq_reg_0x6b) | |
1936 | io_write(sd, 0x6c, irq_reg_0x6b); | |
54450f59 | 1937 | |
ff4f80fd MR |
1938 | v4l2_dbg(2, debug, sd, "%s: ", __func__); |
1939 | ||
54450f59 | 1940 | /* format change */ |
f24d229c | 1941 | fmt_change = irq_reg_0x43 & 0x98; |
d42010a1 LPC |
1942 | fmt_change_digital = is_digital_input(sd) |
1943 | ? irq_reg_0x6b & info->fmt_change_digital_mask | |
1944 | : 0; | |
14d03233 | 1945 | |
54450f59 HV |
1946 | if (fmt_change || fmt_change_digital) { |
1947 | v4l2_dbg(1, debug, sd, | |
25a64ac9 | 1948 | "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", |
54450f59 | 1949 | __func__, fmt_change, fmt_change_digital); |
25a64ac9 | 1950 | |
14d03233 | 1951 | v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); |
25a64ac9 | 1952 | |
54450f59 HV |
1953 | if (handled) |
1954 | *handled = true; | |
1955 | } | |
f24d229c MR |
1956 | /* HDMI/DVI mode */ |
1957 | if (irq_reg_0x6b & 0x01) { | |
1958 | v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, | |
1959 | (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); | |
1960 | set_rgb_quantization_range(sd); | |
1961 | if (handled) | |
1962 | *handled = true; | |
1963 | } | |
1964 | ||
54450f59 | 1965 | /* tx 5v detect */ |
d42010a1 | 1966 | tx_5v = io_read(sd, 0x70) & info->cable_det_mask; |
54450f59 HV |
1967 | if (tx_5v) { |
1968 | v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); | |
1969 | io_write(sd, 0x71, tx_5v); | |
1970 | adv7604_s_detect_tx_5v_ctrl(sd); | |
1971 | if (handled) | |
1972 | *handled = true; | |
1973 | } | |
1974 | return 0; | |
1975 | } | |
1976 | ||
b09dfac8 | 1977 | static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 HV |
1978 | { |
1979 | struct adv7604_state *state = to_state(sd); | |
4a31a93a | 1980 | u8 *data = NULL; |
54450f59 | 1981 | |
c784b1e2 | 1982 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) |
54450f59 HV |
1983 | return -EINVAL; |
1984 | if (edid->blocks == 0) | |
1985 | return -EINVAL; | |
4a31a93a | 1986 | if (edid->blocks > 2) |
54450f59 | 1987 | return -EINVAL; |
4a31a93a MR |
1988 | if (edid->start_block > 1) |
1989 | return -EINVAL; | |
1990 | if (edid->start_block == 1) | |
1991 | edid->blocks = 1; | |
4a31a93a MR |
1992 | |
1993 | if (edid->blocks > state->edid.blocks) | |
1994 | edid->blocks = state->edid.blocks; | |
1995 | ||
1996 | switch (edid->pad) { | |
c784b1e2 LP |
1997 | case ADV7604_PAD_HDMI_PORT_A: |
1998 | case ADV7604_PAD_HDMI_PORT_B: | |
1999 | case ADV7604_PAD_HDMI_PORT_C: | |
2000 | case ADV7604_PAD_HDMI_PORT_D: | |
4a31a93a MR |
2001 | if (state->edid.present & (1 << edid->pad)) |
2002 | data = state->edid.edid; | |
2003 | break; | |
2004 | default: | |
2005 | return -EINVAL; | |
2006 | break; | |
2007 | } | |
2008 | if (!data) | |
2009 | return -ENODATA; | |
2010 | ||
2011 | memcpy(edid->edid, | |
2012 | data + edid->start_block * 128, | |
54450f59 HV |
2013 | edid->blocks * 128); |
2014 | return 0; | |
2015 | } | |
2016 | ||
dd08beb9 | 2017 | static int get_edid_spa_location(const u8 *edid) |
3e86aa85 MR |
2018 | { |
2019 | u8 d; | |
2020 | ||
2021 | if ((edid[0x7e] != 1) || | |
2022 | (edid[0x80] != 0x02) || | |
2023 | (edid[0x81] != 0x03)) { | |
2024 | return -1; | |
2025 | } | |
2026 | ||
2027 | /* search Vendor Specific Data Block (tag 3) */ | |
2028 | d = edid[0x82] & 0x7f; | |
2029 | if (d > 4) { | |
2030 | int i = 0x84; | |
2031 | int end = 0x80 + d; | |
2032 | ||
2033 | do { | |
2034 | u8 tag = edid[i] >> 5; | |
2035 | u8 len = edid[i] & 0x1f; | |
2036 | ||
2037 | if ((tag == 3) && (len >= 5)) | |
2038 | return i + 4; | |
2039 | i += len + 1; | |
2040 | } while (i < end); | |
2041 | } | |
2042 | return -1; | |
2043 | } | |
2044 | ||
b09dfac8 | 2045 | static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 HV |
2046 | { |
2047 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 2048 | const struct adv7604_chip_info *info = state->info; |
dd08beb9 | 2049 | int spa_loc; |
3e86aa85 | 2050 | int tmp = 0; |
54450f59 | 2051 | int err; |
dd08beb9 | 2052 | int i; |
54450f59 | 2053 | |
c784b1e2 | 2054 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) |
54450f59 HV |
2055 | return -EINVAL; |
2056 | if (edid->start_block != 0) | |
2057 | return -EINVAL; | |
2058 | if (edid->blocks == 0) { | |
3e86aa85 | 2059 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a MR |
2060 | state->edid.present &= ~(1 << edid->pad); |
2061 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); | |
22d97e56 | 2062 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); |
3e86aa85 | 2063 | |
54450f59 HV |
2064 | /* Fall back to a 16:9 aspect ratio */ |
2065 | state->aspect_ratio.numerator = 16; | |
2066 | state->aspect_ratio.denominator = 9; | |
3e86aa85 MR |
2067 | |
2068 | if (!state->edid.present) | |
2069 | state->edid.blocks = 0; | |
2070 | ||
2071 | v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", | |
2072 | __func__, edid->pad, state->edid.present); | |
54450f59 HV |
2073 | return 0; |
2074 | } | |
4a31a93a MR |
2075 | if (edid->blocks > 2) { |
2076 | edid->blocks = 2; | |
54450f59 | 2077 | return -E2BIG; |
4a31a93a | 2078 | } |
4a31a93a | 2079 | |
dd08beb9 MR |
2080 | v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", |
2081 | __func__, edid->pad, state->edid.present); | |
2082 | ||
3e86aa85 | 2083 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a | 2084 | cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); |
3e86aa85 | 2085 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp); |
22d97e56 | 2086 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); |
3e86aa85 | 2087 | |
dd08beb9 MR |
2088 | spa_loc = get_edid_spa_location(edid->edid); |
2089 | if (spa_loc < 0) | |
2090 | spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ | |
2091 | ||
3e86aa85 | 2092 | switch (edid->pad) { |
c784b1e2 | 2093 | case ADV7604_PAD_HDMI_PORT_A: |
dd08beb9 MR |
2094 | state->spa_port_a[0] = edid->edid[spa_loc]; |
2095 | state->spa_port_a[1] = edid->edid[spa_loc + 1]; | |
3e86aa85 | 2096 | break; |
c784b1e2 | 2097 | case ADV7604_PAD_HDMI_PORT_B: |
dd08beb9 MR |
2098 | rep_write(sd, 0x70, edid->edid[spa_loc]); |
2099 | rep_write(sd, 0x71, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2100 | break; |
c784b1e2 | 2101 | case ADV7604_PAD_HDMI_PORT_C: |
dd08beb9 MR |
2102 | rep_write(sd, 0x72, edid->edid[spa_loc]); |
2103 | rep_write(sd, 0x73, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2104 | break; |
c784b1e2 | 2105 | case ADV7604_PAD_HDMI_PORT_D: |
dd08beb9 MR |
2106 | rep_write(sd, 0x74, edid->edid[spa_loc]); |
2107 | rep_write(sd, 0x75, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2108 | break; |
dd08beb9 MR |
2109 | default: |
2110 | return -EINVAL; | |
3e86aa85 | 2111 | } |
d42010a1 LPC |
2112 | |
2113 | if (info->type == ADV7604) { | |
2114 | rep_write(sd, 0x76, spa_loc & 0xff); | |
22d97e56 | 2115 | rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); |
d42010a1 LPC |
2116 | } else { |
2117 | /* FIXME: Where is the SPA location LSB register ? */ | |
22d97e56 | 2118 | rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); |
d42010a1 | 2119 | } |
3e86aa85 | 2120 | |
dd08beb9 MR |
2121 | edid->edid[spa_loc] = state->spa_port_a[0]; |
2122 | edid->edid[spa_loc + 1] = state->spa_port_a[1]; | |
4a31a93a MR |
2123 | |
2124 | memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); | |
2125 | state->edid.blocks = edid->blocks; | |
54450f59 HV |
2126 | state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], |
2127 | edid->edid[0x16]); | |
3e86aa85 | 2128 | state->edid.present |= 1 << edid->pad; |
4a31a93a MR |
2129 | |
2130 | err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); | |
2131 | if (err < 0) { | |
3e86aa85 | 2132 | v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); |
4a31a93a MR |
2133 | return err; |
2134 | } | |
2135 | ||
dd08beb9 MR |
2136 | /* adv7604 calculates the checksums and enables I2C access to internal |
2137 | EDID RAM from DDC port. */ | |
22d97e56 | 2138 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); |
dd08beb9 MR |
2139 | |
2140 | for (i = 0; i < 1000; i++) { | |
d42010a1 | 2141 | if (rep_read(sd, info->edid_status_reg) & state->edid.present) |
dd08beb9 MR |
2142 | break; |
2143 | mdelay(1); | |
2144 | } | |
2145 | if (i == 1000) { | |
2146 | v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); | |
2147 | return -EIO; | |
2148 | } | |
2149 | ||
2150 | ||
4a31a93a MR |
2151 | /* enable hotplug after 100 ms */ |
2152 | queue_delayed_work(state->work_queues, | |
2153 | &state->delayed_work_enable_hotplug, HZ / 10); | |
2154 | return 0; | |
54450f59 HV |
2155 | } |
2156 | ||
2157 | /*********** avi info frame CEA-861-E **************/ | |
2158 | ||
2159 | static void print_avi_infoframe(struct v4l2_subdev *sd) | |
2160 | { | |
2161 | int i; | |
2162 | u8 buf[14]; | |
2163 | u8 avi_len; | |
2164 | u8 avi_ver; | |
2165 | ||
bb88f325 | 2166 | if (!is_hdmi(sd)) { |
54450f59 HV |
2167 | v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); |
2168 | return; | |
2169 | } | |
2170 | if (!(io_read(sd, 0x60) & 0x01)) { | |
2171 | v4l2_info(sd, "AVI infoframe not received\n"); | |
2172 | return; | |
2173 | } | |
2174 | ||
2175 | if (io_read(sd, 0x83) & 0x01) { | |
2176 | v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); | |
2177 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
2178 | if (io_read(sd, 0x83) & 0x01) { | |
2179 | v4l2_info(sd, "AVI infoframe checksum error still present\n"); | |
2180 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
2181 | } | |
2182 | } | |
2183 | ||
2184 | avi_len = infoframe_read(sd, 0xe2); | |
2185 | avi_ver = infoframe_read(sd, 0xe1); | |
2186 | v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", | |
2187 | avi_ver, avi_len); | |
2188 | ||
2189 | if (avi_ver != 0x02) | |
2190 | return; | |
2191 | ||
2192 | for (i = 0; i < 14; i++) | |
2193 | buf[i] = infoframe_read(sd, i); | |
2194 | ||
2195 | v4l2_info(sd, | |
2196 | "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", | |
2197 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], | |
2198 | buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); | |
2199 | } | |
2200 | ||
2201 | static int adv7604_log_status(struct v4l2_subdev *sd) | |
2202 | { | |
2203 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 2204 | const struct adv7604_chip_info *info = state->info; |
54450f59 HV |
2205 | struct v4l2_dv_timings timings; |
2206 | struct stdi_readback stdi; | |
2207 | u8 reg_io_0x02 = io_read(sd, 0x02); | |
4a2ccdd2 LP |
2208 | u8 edid_enabled; |
2209 | u8 cable_det; | |
54450f59 | 2210 | |
f216ccb3 | 2211 | static const char * const csc_coeff_sel_rb[16] = { |
54450f59 HV |
2212 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", |
2213 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", | |
2214 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", | |
2215 | "reserved", "reserved", "reserved", "reserved", "manual" | |
2216 | }; | |
f216ccb3 | 2217 | static const char * const input_color_space_txt[16] = { |
54450f59 HV |
2218 | "RGB limited range (16-235)", "RGB full range (0-255)", |
2219 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
9833239e | 2220 | "xvYCC Bt.601", "xvYCC Bt.709", |
54450f59 HV |
2221 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", |
2222 | "invalid", "invalid", "invalid", "invalid", "invalid", | |
2223 | "invalid", "invalid", "automatic" | |
2224 | }; | |
f216ccb3 | 2225 | static const char * const rgb_quantization_range_txt[] = { |
54450f59 HV |
2226 | "Automatic", |
2227 | "RGB limited range (16-235)", | |
2228 | "RGB full range (0-255)", | |
2229 | }; | |
f216ccb3 | 2230 | static const char * const deep_color_mode_txt[4] = { |
bb88f325 MB |
2231 | "8-bits per channel", |
2232 | "10-bits per channel", | |
2233 | "12-bits per channel", | |
2234 | "16-bits per channel (not supported)" | |
2235 | }; | |
54450f59 HV |
2236 | |
2237 | v4l2_info(sd, "-----Chip status-----\n"); | |
2238 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); | |
d42010a1 | 2239 | edid_enabled = rep_read(sd, info->edid_status_reg); |
4a31a93a | 2240 | v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", |
4a2ccdd2 LP |
2241 | ((edid_enabled & 0x01) ? "Yes" : "No"), |
2242 | ((edid_enabled & 0x02) ? "Yes" : "No"), | |
2243 | ((edid_enabled & 0x04) ? "Yes" : "No"), | |
2244 | ((edid_enabled & 0x08) ? "Yes" : "No")); | |
54450f59 HV |
2245 | v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? |
2246 | "enabled" : "disabled"); | |
2247 | ||
2248 | v4l2_info(sd, "-----Signal status-----\n"); | |
d42010a1 | 2249 | cable_det = info->read_cable_det(sd); |
4a31a93a | 2250 | v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", |
d42010a1 LPC |
2251 | ((cable_det & 0x01) ? "Yes" : "No"), |
2252 | ((cable_det & 0x02) ? "Yes" : "No"), | |
4a2ccdd2 | 2253 | ((cable_det & 0x04) ? "Yes" : "No"), |
d42010a1 | 2254 | ((cable_det & 0x08) ? "Yes" : "No")); |
54450f59 HV |
2255 | v4l2_info(sd, "TMDS signal detected: %s\n", |
2256 | no_signal_tmds(sd) ? "false" : "true"); | |
2257 | v4l2_info(sd, "TMDS signal locked: %s\n", | |
2258 | no_lock_tmds(sd) ? "false" : "true"); | |
2259 | v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); | |
2260 | v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); | |
2261 | v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); | |
2262 | v4l2_info(sd, "CP free run: %s\n", | |
2263 | (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); | |
ccbd5bc4 HV |
2264 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", |
2265 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, | |
2266 | (io_read(sd, 0x01) & 0x70) >> 4); | |
54450f59 HV |
2267 | |
2268 | v4l2_info(sd, "-----Video Timings-----\n"); | |
2269 | if (read_stdi(sd, &stdi)) | |
2270 | v4l2_info(sd, "STDI: not locked\n"); | |
2271 | else | |
2272 | v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", | |
2273 | stdi.lcf, stdi.bl, stdi.lcvs, | |
2274 | stdi.interlaced ? "interlaced" : "progressive", | |
2275 | stdi.hs_pol, stdi.vs_pol); | |
2276 | if (adv7604_query_dv_timings(sd, &timings)) | |
2277 | v4l2_info(sd, "No video detected\n"); | |
2278 | else | |
11d034c8 HV |
2279 | v4l2_print_dv_timings(sd->name, "Detected format: ", |
2280 | &timings, true); | |
2281 | v4l2_print_dv_timings(sd->name, "Configured format: ", | |
2282 | &state->timings, true); | |
54450f59 | 2283 | |
76eb2d30 MR |
2284 | if (no_signal(sd)) |
2285 | return 0; | |
2286 | ||
54450f59 HV |
2287 | v4l2_info(sd, "-----Color space-----\n"); |
2288 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", | |
2289 | rgb_quantization_range_txt[state->rgb_quantization_range]); | |
2290 | v4l2_info(sd, "Input color space: %s\n", | |
2291 | input_color_space_txt[reg_io_0x02 >> 4]); | |
2292 | v4l2_info(sd, "Output color space: %s %s, saturator %s\n", | |
2293 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", | |
2294 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", | |
2295 | ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? | |
76eb2d30 | 2296 | "enabled" : "disabled"); |
54450f59 HV |
2297 | v4l2_info(sd, "Color space conversion: %s\n", |
2298 | csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); | |
2299 | ||
4a31a93a | 2300 | if (!is_digital_input(sd)) |
76eb2d30 MR |
2301 | return 0; |
2302 | ||
2303 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); | |
4a31a93a MR |
2304 | v4l2_info(sd, "Digital video port selected: %c\n", |
2305 | (hdmi_read(sd, 0x00) & 0x03) + 'A'); | |
2306 | v4l2_info(sd, "HDCP encrypted content: %s\n", | |
2307 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); | |
76eb2d30 MR |
2308 | v4l2_info(sd, "HDCP keys read: %s%s\n", |
2309 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", | |
2310 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); | |
2311 | if (!is_hdmi(sd)) { | |
2312 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; | |
2313 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; | |
2314 | bool audio_mute = io_read(sd, 0x65) & 0x40; | |
2315 | ||
2316 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", | |
2317 | audio_pll_locked ? "locked" : "not locked", | |
2318 | audio_sample_packet_detect ? "detected" : "not detected", | |
2319 | audio_mute ? "muted" : "enabled"); | |
2320 | if (audio_pll_locked && audio_sample_packet_detect) { | |
2321 | v4l2_info(sd, "Audio format: %s\n", | |
2322 | (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); | |
2323 | } | |
2324 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + | |
2325 | (hdmi_read(sd, 0x5c) << 8) + | |
2326 | (hdmi_read(sd, 0x5d) & 0xf0)); | |
2327 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + | |
2328 | (hdmi_read(sd, 0x5e) << 8) + | |
2329 | hdmi_read(sd, 0x5f)); | |
2330 | v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); | |
2331 | ||
2332 | v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); | |
2333 | ||
54450f59 HV |
2334 | print_avi_infoframe(sd); |
2335 | } | |
2336 | ||
2337 | return 0; | |
2338 | } | |
2339 | ||
2340 | /* ----------------------------------------------------------------------- */ | |
2341 | ||
2342 | static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { | |
2343 | .s_ctrl = adv7604_s_ctrl, | |
2344 | }; | |
2345 | ||
2346 | static const struct v4l2_subdev_core_ops adv7604_core_ops = { | |
2347 | .log_status = adv7604_log_status, | |
54450f59 HV |
2348 | .interrupt_service_routine = adv7604_isr, |
2349 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
2350 | .g_register = adv7604_g_register, | |
2351 | .s_register = adv7604_s_register, | |
2352 | #endif | |
2353 | }; | |
2354 | ||
2355 | static const struct v4l2_subdev_video_ops adv7604_video_ops = { | |
2356 | .s_routing = adv7604_s_routing, | |
2357 | .g_input_status = adv7604_g_input_status, | |
2358 | .s_dv_timings = adv7604_s_dv_timings, | |
2359 | .g_dv_timings = adv7604_g_dv_timings, | |
2360 | .query_dv_timings = adv7604_query_dv_timings, | |
54450f59 HV |
2361 | }; |
2362 | ||
2363 | static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { | |
539b33b0 LP |
2364 | .enum_mbus_code = adv7604_enum_mbus_code, |
2365 | .get_fmt = adv7604_get_format, | |
2366 | .set_fmt = adv7604_set_format, | |
54450f59 HV |
2367 | .get_edid = adv7604_get_edid, |
2368 | .set_edid = adv7604_set_edid, | |
7515e096 | 2369 | .dv_timings_cap = adv7604_dv_timings_cap, |
afec5599 | 2370 | .enum_dv_timings = adv7604_enum_dv_timings, |
54450f59 HV |
2371 | }; |
2372 | ||
2373 | static const struct v4l2_subdev_ops adv7604_ops = { | |
2374 | .core = &adv7604_core_ops, | |
2375 | .video = &adv7604_video_ops, | |
2376 | .pad = &adv7604_pad_ops, | |
2377 | }; | |
2378 | ||
2379 | /* -------------------------- custom ctrls ---------------------------------- */ | |
2380 | ||
2381 | static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { | |
2382 | .ops = &adv7604_ctrl_ops, | |
2383 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, | |
2384 | .name = "Analog Sampling Phase", | |
2385 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2386 | .min = 0, | |
2387 | .max = 0x1f, | |
2388 | .step = 1, | |
2389 | .def = 0, | |
2390 | }; | |
2391 | ||
2392 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { | |
2393 | .ops = &adv7604_ctrl_ops, | |
2394 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, | |
2395 | .name = "Free Running Color, Manual", | |
2396 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
2397 | .min = false, | |
2398 | .max = true, | |
2399 | .step = 1, | |
2400 | .def = false, | |
2401 | }; | |
2402 | ||
2403 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { | |
2404 | .ops = &adv7604_ctrl_ops, | |
2405 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, | |
2406 | .name = "Free Running Color", | |
2407 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2408 | .min = 0x0, | |
2409 | .max = 0xffffff, | |
2410 | .step = 0x1, | |
2411 | .def = 0x0, | |
2412 | }; | |
2413 | ||
2414 | /* ----------------------------------------------------------------------- */ | |
2415 | ||
2416 | static int adv7604_core_init(struct v4l2_subdev *sd) | |
2417 | { | |
2418 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 2419 | const struct adv7604_chip_info *info = state->info; |
54450f59 HV |
2420 | struct adv7604_platform_data *pdata = &state->pdata; |
2421 | ||
2422 | hdmi_write(sd, 0x48, | |
2423 | (pdata->disable_pwrdnb ? 0x80 : 0) | | |
2424 | (pdata->disable_cable_det_rst ? 0x40 : 0)); | |
2425 | ||
2426 | disable_input(sd); | |
2427 | ||
2428 | /* power */ | |
2429 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ | |
2430 | io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ | |
2431 | cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ | |
2432 | ||
2433 | /* video format */ | |
22d97e56 | 2434 | io_write_clr_set(sd, 0x02, 0x0f, |
54450f59 HV |
2435 | pdata->alt_gamma << 3 | |
2436 | pdata->op_656_range << 2 | | |
54450f59 | 2437 | pdata->alt_data_sat << 0); |
22d97e56 | 2438 | io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | |
539b33b0 LP |
2439 | pdata->insert_av_codes << 2 | |
2440 | pdata->replicate_av_codes << 1); | |
2441 | adv7604_setup_format(state); | |
54450f59 | 2442 | |
54450f59 | 2443 | cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ |
98908696 MB |
2444 | |
2445 | /* VS, HS polarities */ | |
2446 | io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1); | |
f31b62e1 MK |
2447 | |
2448 | /* Adjust drive strength */ | |
2449 | io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | | |
2450 | pdata->dr_str_clk << 2 | | |
2451 | pdata->dr_str_sync); | |
2452 | ||
54450f59 HV |
2453 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ |
2454 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ | |
2455 | cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - | |
80939647 | 2456 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 | 2457 | cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - |
80939647 | 2458 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 HV |
2459 | cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution |
2460 | for digital formats */ | |
2461 | ||
5474b983 | 2462 | /* HDMI audio */ |
22d97e56 LP |
2463 | hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ |
2464 | hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ | |
2465 | hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ | |
5474b983 | 2466 | |
54450f59 HV |
2467 | /* TODO from platform data */ |
2468 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ | |
2469 | ||
d42010a1 LPC |
2470 | if (adv7604_has_afe(state)) { |
2471 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ | |
22d97e56 | 2472 | io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); |
d42010a1 | 2473 | } |
54450f59 | 2474 | |
54450f59 | 2475 | /* interrupts */ |
d42010a1 | 2476 | io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ |
54450f59 | 2477 | io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ |
d42010a1 LPC |
2478 | io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ |
2479 | io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ | |
2480 | info->setup_irqs(sd); | |
54450f59 HV |
2481 | |
2482 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); | |
2483 | } | |
2484 | ||
d42010a1 LPC |
2485 | static void adv7604_setup_irqs(struct v4l2_subdev *sd) |
2486 | { | |
2487 | io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ | |
2488 | } | |
2489 | ||
2490 | static void adv7611_setup_irqs(struct v4l2_subdev *sd) | |
2491 | { | |
2492 | io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ | |
2493 | } | |
2494 | ||
54450f59 HV |
2495 | static void adv7604_unregister_clients(struct adv7604_state *state) |
2496 | { | |
05cacb17 LP |
2497 | unsigned int i; |
2498 | ||
2499 | for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { | |
2500 | if (state->i2c_clients[i]) | |
2501 | i2c_unregister_device(state->i2c_clients[i]); | |
2502 | } | |
54450f59 HV |
2503 | } |
2504 | ||
2505 | static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, | |
2506 | u8 addr, u8 io_reg) | |
2507 | { | |
2508 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2509 | ||
2510 | if (addr) | |
2511 | io_write(sd, io_reg, addr << 1); | |
2512 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); | |
2513 | } | |
2514 | ||
d42010a1 LPC |
2515 | static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { |
2516 | /* reset ADI recommended settings for HDMI: */ | |
2517 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
2518 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2519 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2520 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ | |
2521 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ | |
2522 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2523 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ | |
2524 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ | |
2525 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2526 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2527 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ | |
2528 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ | |
2529 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ | |
2530 | ||
2531 | /* set ADI recommended settings for digitizer */ | |
2532 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
2533 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ | |
2534 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ | |
2535 | { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ | |
2536 | { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ | |
2537 | { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ | |
2538 | ||
2539 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2540 | }; | |
2541 | ||
2542 | static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { | |
2543 | /* set ADI recommended settings for HDMI: */ | |
2544 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
2545 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ | |
2546 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ | |
2547 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ | |
2548 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2549 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ | |
2550 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ | |
2551 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2552 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2553 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ | |
2554 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ | |
2555 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ | |
2556 | ||
2557 | /* reset ADI recommended settings for digitizer */ | |
2558 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
2559 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ | |
2560 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ | |
2561 | ||
2562 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2563 | }; | |
2564 | ||
2565 | static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { | |
2566 | { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, | |
2567 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c }, | |
2568 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, | |
2569 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, | |
2570 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, | |
2571 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, | |
2572 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, | |
2573 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, | |
2574 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, | |
2575 | ||
2576 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2577 | }; | |
2578 | ||
2579 | static const struct adv7604_chip_info adv7604_chip_info[] = { | |
2580 | [ADV7604] = { | |
2581 | .type = ADV7604, | |
2582 | .has_afe = true, | |
c784b1e2 | 2583 | .max_port = ADV7604_PAD_VGA_COMP, |
d42010a1 LPC |
2584 | .num_dv_ports = 4, |
2585 | .edid_enable_reg = 0x77, | |
2586 | .edid_status_reg = 0x7d, | |
2587 | .lcf_reg = 0xb3, | |
2588 | .tdms_lock_mask = 0xe0, | |
2589 | .cable_det_mask = 0x1e, | |
2590 | .fmt_change_digital_mask = 0xc1, | |
539b33b0 LP |
2591 | .formats = adv7604_formats, |
2592 | .nformats = ARRAY_SIZE(adv7604_formats), | |
d42010a1 LPC |
2593 | .set_termination = adv7604_set_termination, |
2594 | .setup_irqs = adv7604_setup_irqs, | |
2595 | .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, | |
2596 | .read_cable_det = adv7604_read_cable_det, | |
2597 | .recommended_settings = { | |
2598 | [0] = adv7604_recommended_settings_afe, | |
2599 | [1] = adv7604_recommended_settings_hdmi, | |
2600 | }, | |
2601 | .num_recommended_settings = { | |
2602 | [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), | |
2603 | [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), | |
2604 | }, | |
2605 | .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | | |
2606 | BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | | |
2607 | BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | | |
2608 | BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | | |
2609 | BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | | |
2610 | BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | | |
2611 | BIT(ADV7604_PAGE_VDP), | |
2612 | }, | |
2613 | [ADV7611] = { | |
2614 | .type = ADV7611, | |
2615 | .has_afe = false, | |
c784b1e2 | 2616 | .max_port = ADV7604_PAD_HDMI_PORT_A, |
d42010a1 LPC |
2617 | .num_dv_ports = 1, |
2618 | .edid_enable_reg = 0x74, | |
2619 | .edid_status_reg = 0x76, | |
2620 | .lcf_reg = 0xa3, | |
2621 | .tdms_lock_mask = 0x43, | |
2622 | .cable_det_mask = 0x01, | |
2623 | .fmt_change_digital_mask = 0x03, | |
539b33b0 LP |
2624 | .formats = adv7611_formats, |
2625 | .nformats = ARRAY_SIZE(adv7611_formats), | |
d42010a1 LPC |
2626 | .set_termination = adv7611_set_termination, |
2627 | .setup_irqs = adv7611_setup_irqs, | |
2628 | .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, | |
2629 | .read_cable_det = adv7611_read_cable_det, | |
2630 | .recommended_settings = { | |
2631 | [1] = adv7611_recommended_settings_hdmi, | |
2632 | }, | |
2633 | .num_recommended_settings = { | |
2634 | [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), | |
2635 | }, | |
2636 | .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | | |
2637 | BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | | |
2638 | BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | | |
2639 | BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), | |
2640 | }, | |
2641 | }; | |
2642 | ||
54450f59 HV |
2643 | static int adv7604_probe(struct i2c_client *client, |
2644 | const struct i2c_device_id *id) | |
2645 | { | |
591b72fe HV |
2646 | static const struct v4l2_dv_timings cea640x480 = |
2647 | V4L2_DV_BT_CEA_640X480P59_94; | |
54450f59 HV |
2648 | struct adv7604_state *state; |
2649 | struct adv7604_platform_data *pdata = client->dev.platform_data; | |
2650 | struct v4l2_ctrl_handler *hdl; | |
2651 | struct v4l2_subdev *sd; | |
c784b1e2 | 2652 | unsigned int i; |
d42010a1 | 2653 | u16 val; |
54450f59 HV |
2654 | int err; |
2655 | ||
2656 | /* Check if the adapter supports the needed features */ | |
2657 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
2658 | return -EIO; | |
2659 | v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", | |
2660 | client->addr << 1); | |
2661 | ||
c02b211d | 2662 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
54450f59 HV |
2663 | if (!state) { |
2664 | v4l_err(client, "Could not allocate adv7604_state memory!\n"); | |
2665 | return -ENOMEM; | |
2666 | } | |
2667 | ||
d42010a1 | 2668 | state->info = &adv7604_chip_info[id->driver_data]; |
05cacb17 | 2669 | state->i2c_clients[ADV7604_PAGE_IO] = client; |
d42010a1 | 2670 | |
25a64ac9 MR |
2671 | /* initialize variables */ |
2672 | state->restart_stdi_once = true; | |
ff4f80fd | 2673 | state->selected_input = ~0; |
25a64ac9 | 2674 | |
54450f59 HV |
2675 | /* platform data */ |
2676 | if (!pdata) { | |
2677 | v4l_err(client, "No platform data!\n"); | |
c02b211d | 2678 | return -ENODEV; |
54450f59 | 2679 | } |
591b72fe HV |
2680 | state->pdata = *pdata; |
2681 | state->timings = cea640x480; | |
539b33b0 | 2682 | state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); |
54450f59 HV |
2683 | |
2684 | sd = &state->sd; | |
2685 | v4l2_i2c_subdev_init(sd, client, &adv7604_ops); | |
d42010a1 LPC |
2686 | snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", |
2687 | id->name, i2c_adapter_id(client->adapter), | |
2688 | client->addr); | |
54450f59 | 2689 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
54450f59 | 2690 | |
d42010a1 LPC |
2691 | /* |
2692 | * Verify that the chip is present. On ADV7604 the RD_INFO register only | |
2693 | * identifies the revision, while on ADV7611 it identifies the model as | |
2694 | * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. | |
2695 | */ | |
2696 | if (state->info->type == ADV7604) { | |
2697 | val = adv_smbus_read_byte_data_check(client, 0xfb, false); | |
2698 | if (val != 0x68) { | |
2699 | v4l2_info(sd, "not an adv7604 on address 0x%x\n", | |
2700 | client->addr << 1); | |
2701 | return -ENODEV; | |
2702 | } | |
2703 | } else { | |
2704 | val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) | |
2705 | | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); | |
2706 | if (val != 0x2051) { | |
2707 | v4l2_info(sd, "not an adv7611 on address 0x%x\n", | |
2708 | client->addr << 1); | |
2709 | return -ENODEV; | |
2710 | } | |
54450f59 HV |
2711 | } |
2712 | ||
2713 | /* control handlers */ | |
2714 | hdl = &state->hdl; | |
d42010a1 | 2715 | v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); |
54450f59 HV |
2716 | |
2717 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2718 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); | |
2719 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2720 | V4L2_CID_CONTRAST, 0, 255, 1, 128); | |
2721 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2722 | V4L2_CID_SATURATION, 0, 255, 1, 128); | |
2723 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2724 | V4L2_CID_HUE, 0, 128, 1, 0); | |
2725 | ||
2726 | /* private controls */ | |
2727 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, | |
d42010a1 LPC |
2728 | V4L2_CID_DV_RX_POWER_PRESENT, 0, |
2729 | (1 << state->info->num_dv_ports) - 1, 0, 0); | |
54450f59 HV |
2730 | state->rgb_quantization_range_ctrl = |
2731 | v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, | |
2732 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, | |
2733 | 0, V4L2_DV_RGB_RANGE_AUTO); | |
54450f59 HV |
2734 | |
2735 | /* custom controls */ | |
d42010a1 LPC |
2736 | if (adv7604_has_afe(state)) |
2737 | state->analog_sampling_phase_ctrl = | |
2738 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); | |
54450f59 HV |
2739 | state->free_run_color_manual_ctrl = |
2740 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); | |
54450f59 HV |
2741 | state->free_run_color_ctrl = |
2742 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); | |
54450f59 HV |
2743 | |
2744 | sd->ctrl_handler = hdl; | |
2745 | if (hdl->error) { | |
2746 | err = hdl->error; | |
2747 | goto err_hdl; | |
2748 | } | |
8c0eadb8 HV |
2749 | state->detect_tx_5v_ctrl->is_private = true; |
2750 | state->rgb_quantization_range_ctrl->is_private = true; | |
d42010a1 LPC |
2751 | if (adv7604_has_afe(state)) |
2752 | state->analog_sampling_phase_ctrl->is_private = true; | |
8c0eadb8 HV |
2753 | state->free_run_color_manual_ctrl->is_private = true; |
2754 | state->free_run_color_ctrl->is_private = true; | |
2755 | ||
54450f59 HV |
2756 | if (adv7604_s_detect_tx_5v_ctrl(sd)) { |
2757 | err = -ENODEV; | |
2758 | goto err_hdl; | |
2759 | } | |
2760 | ||
05cacb17 LP |
2761 | for (i = 1; i < ADV7604_PAGE_MAX; ++i) { |
2762 | if (!(BIT(i) & state->info->page_mask)) | |
2763 | continue; | |
54450f59 | 2764 | |
05cacb17 LP |
2765 | state->i2c_clients[i] = |
2766 | adv7604_dummy_client(sd, pdata->i2c_addresses[i], | |
2767 | 0xf2 + i); | |
2768 | if (state->i2c_clients[i] == NULL) { | |
d42010a1 | 2769 | err = -ENOMEM; |
05cacb17 | 2770 | v4l2_err(sd, "failed to create i2c client %u\n", i); |
d42010a1 LPC |
2771 | goto err_i2c; |
2772 | } | |
2773 | } | |
05cacb17 | 2774 | |
54450f59 HV |
2775 | /* work queues */ |
2776 | state->work_queues = create_singlethread_workqueue(client->name); | |
2777 | if (!state->work_queues) { | |
2778 | v4l2_err(sd, "Could not create work queue\n"); | |
2779 | err = -ENOMEM; | |
2780 | goto err_i2c; | |
2781 | } | |
2782 | ||
2783 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, | |
2784 | adv7604_delayed_work_enable_hotplug); | |
2785 | ||
c784b1e2 LP |
2786 | state->source_pad = state->info->num_dv_ports |
2787 | + (state->info->has_afe ? 2 : 0); | |
2788 | for (i = 0; i < state->source_pad; ++i) | |
2789 | state->pads[i].flags = MEDIA_PAD_FL_SINK; | |
2790 | state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; | |
2791 | ||
2792 | err = media_entity_init(&sd->entity, state->source_pad + 1, | |
2793 | state->pads, 0); | |
54450f59 HV |
2794 | if (err) |
2795 | goto err_work_queues; | |
2796 | ||
2797 | err = adv7604_core_init(sd); | |
2798 | if (err) | |
2799 | goto err_entity; | |
2800 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, | |
2801 | client->addr << 1, client->adapter->name); | |
bedc3939 LPC |
2802 | |
2803 | err = v4l2_async_register_subdev(sd); | |
2804 | if (err) | |
2805 | goto err_entity; | |
2806 | ||
54450f59 HV |
2807 | return 0; |
2808 | ||
2809 | err_entity: | |
2810 | media_entity_cleanup(&sd->entity); | |
2811 | err_work_queues: | |
2812 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2813 | destroy_workqueue(state->work_queues); | |
2814 | err_i2c: | |
2815 | adv7604_unregister_clients(state); | |
2816 | err_hdl: | |
2817 | v4l2_ctrl_handler_free(hdl); | |
54450f59 HV |
2818 | return err; |
2819 | } | |
2820 | ||
2821 | /* ----------------------------------------------------------------------- */ | |
2822 | ||
2823 | static int adv7604_remove(struct i2c_client *client) | |
2824 | { | |
2825 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
2826 | struct adv7604_state *state = to_state(sd); | |
2827 | ||
2828 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2829 | destroy_workqueue(state->work_queues); | |
bedc3939 | 2830 | v4l2_async_unregister_subdev(sd); |
54450f59 HV |
2831 | v4l2_device_unregister_subdev(sd); |
2832 | media_entity_cleanup(&sd->entity); | |
2833 | adv7604_unregister_clients(to_state(sd)); | |
2834 | v4l2_ctrl_handler_free(sd->ctrl_handler); | |
54450f59 HV |
2835 | return 0; |
2836 | } | |
2837 | ||
2838 | /* ----------------------------------------------------------------------- */ | |
2839 | ||
2840 | static struct i2c_device_id adv7604_id[] = { | |
d42010a1 LPC |
2841 | { "adv7604", ADV7604 }, |
2842 | { "adv7611", ADV7611 }, | |
54450f59 HV |
2843 | { } |
2844 | }; | |
2845 | MODULE_DEVICE_TABLE(i2c, adv7604_id); | |
2846 | ||
2847 | static struct i2c_driver adv7604_driver = { | |
2848 | .driver = { | |
2849 | .owner = THIS_MODULE, | |
2850 | .name = "adv7604", | |
2851 | }, | |
2852 | .probe = adv7604_probe, | |
2853 | .remove = adv7604_remove, | |
2854 | .id_table = adv7604_id, | |
2855 | }; | |
2856 | ||
2857 | module_i2c_driver(adv7604_driver); |