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Commit | Line | Data |
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54450f59 HV |
1 | /* |
2 | * adv7604 - Analog Devices ADV7604 video decoder driver | |
3 | * | |
4 | * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. | |
5 | * | |
6 | * This program is free software; you may redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
17 | * SOFTWARE. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * References (c = chapter, p = page): | |
23 | * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, | |
24 | * Revision 2.5, June 2010 | |
25 | * REF_02 - Analog devices, Register map documentation, Documentation of | |
26 | * the register maps, Software manual, Rev. F, June 2010 | |
27 | * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 | |
28 | */ | |
29 | ||
c72a53ce | 30 | #include <linux/delay.h> |
e9d50e9e | 31 | #include <linux/gpio/consumer.h> |
516613c1 | 32 | #include <linux/hdmi.h> |
c72a53ce | 33 | #include <linux/i2c.h> |
54450f59 HV |
34 | #include <linux/kernel.h> |
35 | #include <linux/module.h> | |
36 | #include <linux/slab.h> | |
c72a53ce | 37 | #include <linux/v4l2-dv-timings.h> |
54450f59 HV |
38 | #include <linux/videodev2.h> |
39 | #include <linux/workqueue.h> | |
c72a53ce LP |
40 | |
41 | #include <media/adv7604.h> | |
54450f59 | 42 | #include <media/v4l2-ctrls.h> |
c72a53ce | 43 | #include <media/v4l2-device.h> |
25764158 | 44 | #include <media/v4l2-dv-timings.h> |
6fa88045 | 45 | #include <media/v4l2-of.h> |
54450f59 HV |
46 | |
47 | static int debug; | |
48 | module_param(debug, int, 0644); | |
49 | MODULE_PARM_DESC(debug, "debug level (0-2)"); | |
50 | ||
51 | MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); | |
52 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); | |
53 | MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); | |
54 | MODULE_LICENSE("GPL"); | |
55 | ||
56 | /* ADV7604 system clock frequency */ | |
b44b2e06 | 57 | #define ADV76XX_FSC (28636360) |
54450f59 | 58 | |
b44b2e06 | 59 | #define ADV76XX_RGB_OUT (1 << 1) |
539b33b0 | 60 | |
b44b2e06 | 61 | #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) |
539b33b0 | 62 | #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) |
b44b2e06 | 63 | #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) |
539b33b0 | 64 | |
b44b2e06 | 65 | #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) |
539b33b0 | 66 | #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) |
b44b2e06 | 67 | #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) |
539b33b0 | 68 | #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) |
b44b2e06 | 69 | #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) |
539b33b0 LP |
70 | #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) |
71 | ||
b44b2e06 PA |
72 | #define ADV76XX_OP_CH_SEL_GBR (0 << 5) |
73 | #define ADV76XX_OP_CH_SEL_GRB (1 << 5) | |
74 | #define ADV76XX_OP_CH_SEL_BGR (2 << 5) | |
75 | #define ADV76XX_OP_CH_SEL_RGB (3 << 5) | |
76 | #define ADV76XX_OP_CH_SEL_BRG (4 << 5) | |
77 | #define ADV76XX_OP_CH_SEL_RBG (5 << 5) | |
539b33b0 | 78 | |
b44b2e06 | 79 | #define ADV76XX_OP_SWAP_CB_CR (1 << 0) |
539b33b0 | 80 | |
b44b2e06 | 81 | enum adv76xx_type { |
d42010a1 LPC |
82 | ADV7604, |
83 | ADV7611, | |
84 | }; | |
85 | ||
b44b2e06 | 86 | struct adv76xx_reg_seq { |
d42010a1 LPC |
87 | unsigned int reg; |
88 | u8 val; | |
89 | }; | |
90 | ||
b44b2e06 | 91 | struct adv76xx_format_info { |
f5fe58fd | 92 | u32 code; |
539b33b0 LP |
93 | u8 op_ch_sel; |
94 | bool rgb_out; | |
95 | bool swap_cb_cr; | |
96 | u8 op_format_sel; | |
97 | }; | |
98 | ||
516613c1 HV |
99 | struct adv76xx_cfg_read_infoframe { |
100 | const char *desc; | |
101 | u8 present_mask; | |
102 | u8 head_addr; | |
103 | u8 payload_addr; | |
104 | }; | |
105 | ||
b44b2e06 PA |
106 | struct adv76xx_chip_info { |
107 | enum adv76xx_type type; | |
d42010a1 LPC |
108 | |
109 | bool has_afe; | |
110 | unsigned int max_port; | |
111 | unsigned int num_dv_ports; | |
112 | ||
113 | unsigned int edid_enable_reg; | |
114 | unsigned int edid_status_reg; | |
115 | unsigned int lcf_reg; | |
116 | ||
117 | unsigned int cable_det_mask; | |
118 | unsigned int tdms_lock_mask; | |
119 | unsigned int fmt_change_digital_mask; | |
80f4944e | 120 | unsigned int cp_csc; |
d42010a1 | 121 | |
b44b2e06 | 122 | const struct adv76xx_format_info *formats; |
539b33b0 LP |
123 | unsigned int nformats; |
124 | ||
d42010a1 LPC |
125 | void (*set_termination)(struct v4l2_subdev *sd, bool enable); |
126 | void (*setup_irqs)(struct v4l2_subdev *sd); | |
127 | unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); | |
128 | unsigned int (*read_cable_det)(struct v4l2_subdev *sd); | |
129 | ||
130 | /* 0 = AFE, 1 = HDMI */ | |
b44b2e06 | 131 | const struct adv76xx_reg_seq *recommended_settings[2]; |
d42010a1 LPC |
132 | unsigned int num_recommended_settings[2]; |
133 | ||
134 | unsigned long page_mask; | |
5380baaf | 135 | |
136 | /* Masks for timings */ | |
137 | unsigned int linewidth_mask; | |
138 | unsigned int field0_height_mask; | |
139 | unsigned int field1_height_mask; | |
140 | unsigned int hfrontporch_mask; | |
141 | unsigned int hsync_mask; | |
142 | unsigned int hbackporch_mask; | |
143 | unsigned int field0_vfrontporch_mask; | |
144 | unsigned int field1_vfrontporch_mask; | |
145 | unsigned int field0_vsync_mask; | |
146 | unsigned int field1_vsync_mask; | |
147 | unsigned int field0_vbackporch_mask; | |
148 | unsigned int field1_vbackporch_mask; | |
d42010a1 LPC |
149 | }; |
150 | ||
54450f59 HV |
151 | /* |
152 | ********************************************************************** | |
153 | * | |
154 | * Arrays with configuration parameters for the ADV7604 | |
155 | * | |
156 | ********************************************************************** | |
157 | */ | |
c784b1e2 | 158 | |
b44b2e06 PA |
159 | struct adv76xx_state { |
160 | const struct adv76xx_chip_info *info; | |
161 | struct adv76xx_platform_data pdata; | |
539b33b0 | 162 | |
e9d50e9e LP |
163 | struct gpio_desc *hpd_gpio[4]; |
164 | ||
54450f59 | 165 | struct v4l2_subdev sd; |
b44b2e06 | 166 | struct media_pad pads[ADV76XX_PAD_MAX]; |
c784b1e2 | 167 | unsigned int source_pad; |
539b33b0 | 168 | |
54450f59 | 169 | struct v4l2_ctrl_handler hdl; |
539b33b0 | 170 | |
b44b2e06 | 171 | enum adv76xx_pad selected_input; |
539b33b0 | 172 | |
54450f59 | 173 | struct v4l2_dv_timings timings; |
b44b2e06 | 174 | const struct adv76xx_format_info *format; |
539b33b0 | 175 | |
4a31a93a MR |
176 | struct { |
177 | u8 edid[256]; | |
178 | u32 present; | |
179 | unsigned blocks; | |
180 | } edid; | |
dd08beb9 | 181 | u16 spa_port_a[2]; |
54450f59 HV |
182 | struct v4l2_fract aspect_ratio; |
183 | u32 rgb_quantization_range; | |
184 | struct workqueue_struct *work_queues; | |
185 | struct delayed_work delayed_work_enable_hotplug; | |
cf9afb1d | 186 | bool restart_stdi_once; |
54450f59 HV |
187 | |
188 | /* i2c clients */ | |
b44b2e06 | 189 | struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; |
54450f59 HV |
190 | |
191 | /* controls */ | |
192 | struct v4l2_ctrl *detect_tx_5v_ctrl; | |
193 | struct v4l2_ctrl *analog_sampling_phase_ctrl; | |
194 | struct v4l2_ctrl *free_run_color_manual_ctrl; | |
195 | struct v4l2_ctrl *free_run_color_ctrl; | |
196 | struct v4l2_ctrl *rgb_quantization_range_ctrl; | |
197 | }; | |
198 | ||
b44b2e06 | 199 | static bool adv76xx_has_afe(struct adv76xx_state *state) |
d42010a1 LPC |
200 | { |
201 | return state->info->has_afe; | |
202 | } | |
203 | ||
54450f59 | 204 | /* Supported CEA and DMT timings */ |
b44b2e06 | 205 | static const struct v4l2_dv_timings adv76xx_timings[] = { |
54450f59 HV |
206 | V4L2_DV_BT_CEA_720X480P59_94, |
207 | V4L2_DV_BT_CEA_720X576P50, | |
208 | V4L2_DV_BT_CEA_1280X720P24, | |
209 | V4L2_DV_BT_CEA_1280X720P25, | |
54450f59 HV |
210 | V4L2_DV_BT_CEA_1280X720P50, |
211 | V4L2_DV_BT_CEA_1280X720P60, | |
212 | V4L2_DV_BT_CEA_1920X1080P24, | |
213 | V4L2_DV_BT_CEA_1920X1080P25, | |
214 | V4L2_DV_BT_CEA_1920X1080P30, | |
215 | V4L2_DV_BT_CEA_1920X1080P50, | |
216 | V4L2_DV_BT_CEA_1920X1080P60, | |
217 | ||
ccbd5bc4 | 218 | /* sorted by DMT ID */ |
54450f59 HV |
219 | V4L2_DV_BT_DMT_640X350P85, |
220 | V4L2_DV_BT_DMT_640X400P85, | |
221 | V4L2_DV_BT_DMT_720X400P85, | |
222 | V4L2_DV_BT_DMT_640X480P60, | |
223 | V4L2_DV_BT_DMT_640X480P72, | |
224 | V4L2_DV_BT_DMT_640X480P75, | |
225 | V4L2_DV_BT_DMT_640X480P85, | |
226 | V4L2_DV_BT_DMT_800X600P56, | |
227 | V4L2_DV_BT_DMT_800X600P60, | |
228 | V4L2_DV_BT_DMT_800X600P72, | |
229 | V4L2_DV_BT_DMT_800X600P75, | |
230 | V4L2_DV_BT_DMT_800X600P85, | |
231 | V4L2_DV_BT_DMT_848X480P60, | |
232 | V4L2_DV_BT_DMT_1024X768P60, | |
233 | V4L2_DV_BT_DMT_1024X768P70, | |
234 | V4L2_DV_BT_DMT_1024X768P75, | |
235 | V4L2_DV_BT_DMT_1024X768P85, | |
236 | V4L2_DV_BT_DMT_1152X864P75, | |
237 | V4L2_DV_BT_DMT_1280X768P60_RB, | |
238 | V4L2_DV_BT_DMT_1280X768P60, | |
239 | V4L2_DV_BT_DMT_1280X768P75, | |
240 | V4L2_DV_BT_DMT_1280X768P85, | |
241 | V4L2_DV_BT_DMT_1280X800P60_RB, | |
242 | V4L2_DV_BT_DMT_1280X800P60, | |
243 | V4L2_DV_BT_DMT_1280X800P75, | |
244 | V4L2_DV_BT_DMT_1280X800P85, | |
245 | V4L2_DV_BT_DMT_1280X960P60, | |
246 | V4L2_DV_BT_DMT_1280X960P85, | |
247 | V4L2_DV_BT_DMT_1280X1024P60, | |
248 | V4L2_DV_BT_DMT_1280X1024P75, | |
249 | V4L2_DV_BT_DMT_1280X1024P85, | |
250 | V4L2_DV_BT_DMT_1360X768P60, | |
251 | V4L2_DV_BT_DMT_1400X1050P60_RB, | |
252 | V4L2_DV_BT_DMT_1400X1050P60, | |
253 | V4L2_DV_BT_DMT_1400X1050P75, | |
254 | V4L2_DV_BT_DMT_1400X1050P85, | |
255 | V4L2_DV_BT_DMT_1440X900P60_RB, | |
256 | V4L2_DV_BT_DMT_1440X900P60, | |
257 | V4L2_DV_BT_DMT_1600X1200P60, | |
258 | V4L2_DV_BT_DMT_1680X1050P60_RB, | |
259 | V4L2_DV_BT_DMT_1680X1050P60, | |
260 | V4L2_DV_BT_DMT_1792X1344P60, | |
261 | V4L2_DV_BT_DMT_1856X1392P60, | |
262 | V4L2_DV_BT_DMT_1920X1200P60_RB, | |
547ed542 | 263 | V4L2_DV_BT_DMT_1366X768P60_RB, |
54450f59 HV |
264 | V4L2_DV_BT_DMT_1366X768P60, |
265 | V4L2_DV_BT_DMT_1920X1080P60, | |
266 | { }, | |
267 | }; | |
268 | ||
b44b2e06 | 269 | struct adv76xx_video_standards { |
ccbd5bc4 HV |
270 | struct v4l2_dv_timings timings; |
271 | u8 vid_std; | |
272 | u8 v_freq; | |
273 | }; | |
274 | ||
275 | /* sorted by number of lines */ | |
b44b2e06 | 276 | static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { |
ccbd5bc4 HV |
277 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ |
278 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
279 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, | |
280 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, | |
281 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
282 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
283 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
284 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
285 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
286 | /* TODO add 1920x1080P60_RB (CVT timing) */ | |
287 | { }, | |
288 | }; | |
289 | ||
290 | /* sorted by number of lines */ | |
b44b2e06 | 291 | static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { |
ccbd5bc4 HV |
292 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
293 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
294 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
295 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
296 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
297 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
298 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
299 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
300 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
301 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
302 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
303 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
304 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
305 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
306 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
307 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, | |
308 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, | |
309 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, | |
310 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, | |
311 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ | |
312 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ | |
313 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, | |
314 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ | |
315 | { }, | |
316 | }; | |
317 | ||
318 | /* sorted by number of lines */ | |
b44b2e06 | 319 | static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { |
ccbd5bc4 HV |
320 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, |
321 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
322 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, | |
323 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, | |
324 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
325 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
326 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
327 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
328 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
329 | { }, | |
330 | }; | |
331 | ||
332 | /* sorted by number of lines */ | |
b44b2e06 | 333 | static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { |
ccbd5bc4 HV |
334 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
335 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
336 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
337 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
338 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
339 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
340 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
341 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
342 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
343 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
344 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
345 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
346 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
347 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
348 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
349 | { }, | |
350 | }; | |
351 | ||
48519838 HV |
352 | static const struct v4l2_event adv76xx_ev_fmt = { |
353 | .type = V4L2_EVENT_SOURCE_CHANGE, | |
354 | .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, | |
355 | }; | |
356 | ||
54450f59 HV |
357 | /* ----------------------------------------------------------------------- */ |
358 | ||
b44b2e06 | 359 | static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) |
54450f59 | 360 | { |
b44b2e06 | 361 | return container_of(sd, struct adv76xx_state, sd); |
54450f59 HV |
362 | } |
363 | ||
54450f59 HV |
364 | static inline unsigned htotal(const struct v4l2_bt_timings *t) |
365 | { | |
eacf8f9a | 366 | return V4L2_DV_BT_FRAME_WIDTH(t); |
54450f59 HV |
367 | } |
368 | ||
54450f59 HV |
369 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) |
370 | { | |
eacf8f9a | 371 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
54450f59 HV |
372 | } |
373 | ||
374 | /* ----------------------------------------------------------------------- */ | |
375 | ||
376 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, | |
377 | u8 command, bool check) | |
378 | { | |
379 | union i2c_smbus_data data; | |
380 | ||
381 | if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
382 | I2C_SMBUS_READ, command, | |
383 | I2C_SMBUS_BYTE_DATA, &data)) | |
384 | return data.byte; | |
385 | if (check) | |
386 | v4l_err(client, "error reading %02x, %02x\n", | |
387 | client->addr, command); | |
388 | return -EIO; | |
389 | } | |
390 | ||
b44b2e06 PA |
391 | static s32 adv_smbus_read_byte_data(struct adv76xx_state *state, |
392 | enum adv76xx_page page, u8 command) | |
54450f59 | 393 | { |
05cacb17 LP |
394 | return adv_smbus_read_byte_data_check(state->i2c_clients[page], |
395 | command, true); | |
54450f59 HV |
396 | } |
397 | ||
b44b2e06 PA |
398 | static s32 adv_smbus_write_byte_data(struct adv76xx_state *state, |
399 | enum adv76xx_page page, u8 command, | |
05cacb17 | 400 | u8 value) |
54450f59 | 401 | { |
05cacb17 | 402 | struct i2c_client *client = state->i2c_clients[page]; |
54450f59 HV |
403 | union i2c_smbus_data data; |
404 | int err; | |
405 | int i; | |
406 | ||
407 | data.byte = value; | |
408 | for (i = 0; i < 3; i++) { | |
409 | err = i2c_smbus_xfer(client->adapter, client->addr, | |
410 | client->flags, | |
411 | I2C_SMBUS_WRITE, command, | |
412 | I2C_SMBUS_BYTE_DATA, &data); | |
413 | if (!err) | |
414 | break; | |
415 | } | |
416 | if (err < 0) | |
417 | v4l_err(client, "error writing %02x, %02x, %02x\n", | |
418 | client->addr, command, value); | |
419 | return err; | |
420 | } | |
421 | ||
b44b2e06 PA |
422 | static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state, |
423 | enum adv76xx_page page, u8 command, | |
05cacb17 | 424 | unsigned length, const u8 *values) |
54450f59 | 425 | { |
05cacb17 | 426 | struct i2c_client *client = state->i2c_clients[page]; |
54450f59 HV |
427 | union i2c_smbus_data data; |
428 | ||
429 | if (length > I2C_SMBUS_BLOCK_MAX) | |
430 | length = I2C_SMBUS_BLOCK_MAX; | |
431 | data.block[0] = length; | |
432 | memcpy(data.block + 1, values, length); | |
433 | return i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
434 | I2C_SMBUS_WRITE, command, | |
435 | I2C_SMBUS_I2C_BLOCK_DATA, &data); | |
436 | } | |
437 | ||
438 | /* ----------------------------------------------------------------------- */ | |
439 | ||
440 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) | |
441 | { | |
b44b2e06 | 442 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 443 | |
b44b2e06 | 444 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg); |
54450f59 HV |
445 | } |
446 | ||
447 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
448 | { | |
b44b2e06 | 449 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 450 | |
b44b2e06 | 451 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val); |
54450f59 HV |
452 | } |
453 | ||
22d97e56 | 454 | static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 455 | { |
22d97e56 | 456 | return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); |
54450f59 HV |
457 | } |
458 | ||
459 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) | |
460 | { | |
b44b2e06 | 461 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 462 | |
05cacb17 | 463 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); |
54450f59 HV |
464 | } |
465 | ||
466 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
467 | { | |
b44b2e06 | 468 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 469 | |
05cacb17 | 470 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); |
54450f59 HV |
471 | } |
472 | ||
473 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) | |
474 | { | |
b44b2e06 | 475 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 476 | |
b44b2e06 | 477 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg); |
54450f59 HV |
478 | } |
479 | ||
480 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
481 | { | |
b44b2e06 | 482 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 483 | |
b44b2e06 | 484 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val); |
54450f59 HV |
485 | } |
486 | ||
54450f59 HV |
487 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) |
488 | { | |
b44b2e06 | 489 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 490 | |
b44b2e06 | 491 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg); |
54450f59 HV |
492 | } |
493 | ||
494 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
495 | { | |
b44b2e06 | 496 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 497 | |
b44b2e06 | 498 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME, |
05cacb17 | 499 | reg, val); |
54450f59 HV |
500 | } |
501 | ||
54450f59 HV |
502 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) |
503 | { | |
b44b2e06 | 504 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 505 | |
b44b2e06 | 506 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg); |
54450f59 HV |
507 | } |
508 | ||
509 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
510 | { | |
b44b2e06 | 511 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 512 | |
b44b2e06 | 513 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val); |
54450f59 HV |
514 | } |
515 | ||
516 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) | |
517 | { | |
b44b2e06 | 518 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 519 | |
b44b2e06 | 520 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg); |
54450f59 HV |
521 | } |
522 | ||
523 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
524 | { | |
b44b2e06 | 525 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 526 | |
b44b2e06 | 527 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val); |
54450f59 HV |
528 | } |
529 | ||
22d97e56 | 530 | static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 531 | { |
22d97e56 | 532 | return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); |
54450f59 HV |
533 | } |
534 | ||
535 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) | |
536 | { | |
b44b2e06 | 537 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 538 | |
b44b2e06 | 539 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg); |
54450f59 HV |
540 | } |
541 | ||
542 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
543 | { | |
b44b2e06 | 544 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 545 | |
b44b2e06 | 546 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val); |
54450f59 HV |
547 | } |
548 | ||
54450f59 HV |
549 | static inline int edid_write_block(struct v4l2_subdev *sd, |
550 | unsigned len, const u8 *val) | |
551 | { | |
b44b2e06 | 552 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
553 | int err = 0; |
554 | int i; | |
555 | ||
556 | v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); | |
557 | ||
54450f59 | 558 | for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) |
b44b2e06 | 559 | err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID, |
05cacb17 | 560 | i, I2C_SMBUS_BLOCK_MAX, val + i); |
dd08beb9 MR |
561 | return err; |
562 | } | |
54450f59 | 563 | |
b44b2e06 | 564 | static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) |
e9d50e9e LP |
565 | { |
566 | unsigned int i; | |
567 | ||
269bd132 | 568 | for (i = 0; i < state->info->num_dv_ports; ++i) |
e9d50e9e | 569 | gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); |
e9d50e9e | 570 | |
b44b2e06 | 571 | v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); |
e9d50e9e LP |
572 | } |
573 | ||
b44b2e06 | 574 | static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) |
dd08beb9 MR |
575 | { |
576 | struct delayed_work *dwork = to_delayed_work(work); | |
b44b2e06 | 577 | struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, |
dd08beb9 MR |
578 | delayed_work_enable_hotplug); |
579 | struct v4l2_subdev *sd = &state->sd; | |
54450f59 | 580 | |
dd08beb9 | 581 | v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); |
54450f59 | 582 | |
b44b2e06 | 583 | adv76xx_set_hpd(state, state->edid.present); |
54450f59 HV |
584 | } |
585 | ||
586 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) | |
587 | { | |
b44b2e06 | 588 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 589 | |
b44b2e06 | 590 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg); |
54450f59 HV |
591 | } |
592 | ||
51182a94 LP |
593 | static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
594 | { | |
595 | return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; | |
596 | } | |
597 | ||
54450f59 HV |
598 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
599 | { | |
b44b2e06 | 600 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 601 | |
b44b2e06 | 602 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val); |
54450f59 HV |
603 | } |
604 | ||
22d97e56 | 605 | static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
4a31a93a | 606 | { |
22d97e56 | 607 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); |
4a31a93a MR |
608 | } |
609 | ||
54450f59 HV |
610 | static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
611 | { | |
b44b2e06 | 612 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 613 | |
b44b2e06 | 614 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val); |
54450f59 HV |
615 | } |
616 | ||
617 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) | |
618 | { | |
b44b2e06 | 619 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 620 | |
b44b2e06 | 621 | return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg); |
54450f59 HV |
622 | } |
623 | ||
51182a94 LP |
624 | static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
625 | { | |
626 | return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; | |
627 | } | |
628 | ||
54450f59 HV |
629 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
630 | { | |
b44b2e06 | 631 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 632 | |
b44b2e06 | 633 | return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val); |
54450f59 HV |
634 | } |
635 | ||
22d97e56 | 636 | static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 637 | { |
22d97e56 | 638 | return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); |
54450f59 HV |
639 | } |
640 | ||
641 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) | |
642 | { | |
b44b2e06 | 643 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 644 | |
05cacb17 | 645 | return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); |
54450f59 HV |
646 | } |
647 | ||
648 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
649 | { | |
b44b2e06 | 650 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 651 | |
05cacb17 LP |
652 | return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); |
653 | } | |
d42010a1 | 654 | |
b44b2e06 PA |
655 | #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) |
656 | #define ADV76XX_REG_SEQ_TERM 0xffff | |
d42010a1 LPC |
657 | |
658 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
b44b2e06 | 659 | static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) |
d42010a1 | 660 | { |
b44b2e06 | 661 | struct adv76xx_state *state = to_state(sd); |
d42010a1 LPC |
662 | unsigned int page = reg >> 8; |
663 | ||
664 | if (!(BIT(page) & state->info->page_mask)) | |
665 | return -EINVAL; | |
666 | ||
667 | reg &= 0xff; | |
668 | ||
05cacb17 | 669 | return adv_smbus_read_byte_data(state, page, reg); |
d42010a1 LPC |
670 | } |
671 | #endif | |
672 | ||
b44b2e06 | 673 | static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) |
d42010a1 | 674 | { |
b44b2e06 | 675 | struct adv76xx_state *state = to_state(sd); |
d42010a1 LPC |
676 | unsigned int page = reg >> 8; |
677 | ||
678 | if (!(BIT(page) & state->info->page_mask)) | |
679 | return -EINVAL; | |
680 | ||
681 | reg &= 0xff; | |
682 | ||
05cacb17 | 683 | return adv_smbus_write_byte_data(state, page, reg, val); |
d42010a1 LPC |
684 | } |
685 | ||
b44b2e06 PA |
686 | static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, |
687 | const struct adv76xx_reg_seq *reg_seq) | |
d42010a1 LPC |
688 | { |
689 | unsigned int i; | |
690 | ||
b44b2e06 PA |
691 | for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) |
692 | adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); | |
d42010a1 LPC |
693 | } |
694 | ||
539b33b0 LP |
695 | /* ----------------------------------------------------------------------------- |
696 | * Format helpers | |
697 | */ | |
698 | ||
b44b2e06 PA |
699 | static const struct adv76xx_format_info adv7604_formats[] = { |
700 | { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, | |
701 | ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
702 | { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, | |
703 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
704 | { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, | |
705 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
706 | { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, | |
707 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
708 | { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, | |
709 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
710 | { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, | |
711 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
712 | { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, | |
713 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
714 | { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, | |
715 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
716 | { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, | |
717 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
718 | { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, | |
719 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
720 | { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, | |
721 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
722 | { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, | |
723 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
724 | { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, | |
725 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
726 | { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, | |
727 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
728 | { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, | |
729 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
730 | { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, | |
731 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
732 | { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, | |
733 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
734 | { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, | |
735 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
736 | { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, | |
737 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
539b33b0 LP |
738 | }; |
739 | ||
b44b2e06 PA |
740 | static const struct adv76xx_format_info adv7611_formats[] = { |
741 | { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, | |
742 | ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
743 | { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, | |
744 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
745 | { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, | |
746 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
747 | { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, | |
748 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
749 | { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, | |
750 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
751 | { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, | |
752 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
753 | { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, | |
754 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
755 | { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, | |
756 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
757 | { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, | |
758 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
759 | { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, | |
760 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
761 | { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, | |
762 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
763 | { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, | |
764 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
765 | { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, | |
766 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
539b33b0 LP |
767 | }; |
768 | ||
b44b2e06 PA |
769 | static const struct adv76xx_format_info * |
770 | adv76xx_format_info(struct adv76xx_state *state, u32 code) | |
539b33b0 LP |
771 | { |
772 | unsigned int i; | |
773 | ||
774 | for (i = 0; i < state->info->nformats; ++i) { | |
775 | if (state->info->formats[i].code == code) | |
776 | return &state->info->formats[i]; | |
777 | } | |
778 | ||
779 | return NULL; | |
780 | } | |
781 | ||
54450f59 HV |
782 | /* ----------------------------------------------------------------------- */ |
783 | ||
4a31a93a MR |
784 | static inline bool is_analog_input(struct v4l2_subdev *sd) |
785 | { | |
b44b2e06 | 786 | struct adv76xx_state *state = to_state(sd); |
4a31a93a | 787 | |
c784b1e2 LP |
788 | return state->selected_input == ADV7604_PAD_VGA_RGB || |
789 | state->selected_input == ADV7604_PAD_VGA_COMP; | |
4a31a93a MR |
790 | } |
791 | ||
792 | static inline bool is_digital_input(struct v4l2_subdev *sd) | |
793 | { | |
b44b2e06 | 794 | struct adv76xx_state *state = to_state(sd); |
4a31a93a | 795 | |
b44b2e06 | 796 | return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || |
c784b1e2 LP |
797 | state->selected_input == ADV7604_PAD_HDMI_PORT_B || |
798 | state->selected_input == ADV7604_PAD_HDMI_PORT_C || | |
799 | state->selected_input == ADV7604_PAD_HDMI_PORT_D; | |
4a31a93a MR |
800 | } |
801 | ||
802 | /* ----------------------------------------------------------------------- */ | |
803 | ||
54450f59 | 804 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
b44b2e06 | 805 | static void adv76xx_inv_register(struct v4l2_subdev *sd) |
54450f59 HV |
806 | { |
807 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); | |
808 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); | |
809 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); | |
810 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); | |
811 | v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); | |
812 | v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); | |
813 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); | |
814 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); | |
815 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); | |
816 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); | |
817 | v4l2_info(sd, "0xa00-0xaff: Test Map\n"); | |
818 | v4l2_info(sd, "0xb00-0xbff: CP Map\n"); | |
819 | v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); | |
820 | } | |
821 | ||
b44b2e06 | 822 | static int adv76xx_g_register(struct v4l2_subdev *sd, |
54450f59 HV |
823 | struct v4l2_dbg_register *reg) |
824 | { | |
d42010a1 LPC |
825 | int ret; |
826 | ||
b44b2e06 | 827 | ret = adv76xx_read_reg(sd, reg->reg); |
d42010a1 | 828 | if (ret < 0) { |
54450f59 | 829 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
b44b2e06 | 830 | adv76xx_inv_register(sd); |
d42010a1 | 831 | return ret; |
54450f59 | 832 | } |
d42010a1 LPC |
833 | |
834 | reg->size = 1; | |
835 | reg->val = ret; | |
836 | ||
54450f59 HV |
837 | return 0; |
838 | } | |
839 | ||
b44b2e06 | 840 | static int adv76xx_s_register(struct v4l2_subdev *sd, |
977ba3b1 | 841 | const struct v4l2_dbg_register *reg) |
54450f59 | 842 | { |
d42010a1 | 843 | int ret; |
1577461b | 844 | |
b44b2e06 | 845 | ret = adv76xx_write_reg(sd, reg->reg, reg->val); |
d42010a1 | 846 | if (ret < 0) { |
54450f59 | 847 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
b44b2e06 | 848 | adv76xx_inv_register(sd); |
d42010a1 | 849 | return ret; |
54450f59 | 850 | } |
d42010a1 | 851 | |
54450f59 HV |
852 | return 0; |
853 | } | |
854 | #endif | |
855 | ||
d42010a1 LPC |
856 | static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) |
857 | { | |
858 | u8 value = io_read(sd, 0x6f); | |
859 | ||
860 | return ((value & 0x10) >> 4) | |
861 | | ((value & 0x08) >> 2) | |
862 | | ((value & 0x04) << 0) | |
863 | | ((value & 0x02) << 2); | |
864 | } | |
865 | ||
866 | static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) | |
867 | { | |
868 | u8 value = io_read(sd, 0x6f); | |
869 | ||
870 | return value & 1; | |
871 | } | |
872 | ||
b44b2e06 | 873 | static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) |
54450f59 | 874 | { |
b44b2e06 PA |
875 | struct adv76xx_state *state = to_state(sd); |
876 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 | 877 | |
54450f59 | 878 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, |
d42010a1 | 879 | info->read_cable_det(sd)); |
54450f59 HV |
880 | } |
881 | ||
ccbd5bc4 HV |
882 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
883 | u8 prim_mode, | |
b44b2e06 | 884 | const struct adv76xx_video_standards *predef_vid_timings, |
ccbd5bc4 HV |
885 | const struct v4l2_dv_timings *timings) |
886 | { | |
ccbd5bc4 HV |
887 | int i; |
888 | ||
889 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { | |
ef1ed8f5 | 890 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, |
4a31a93a | 891 | is_digital_input(sd) ? 250000 : 1000000)) |
ccbd5bc4 HV |
892 | continue; |
893 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ | |
894 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + | |
895 | prim_mode); /* v_freq and prim mode */ | |
896 | return 0; | |
897 | } | |
898 | ||
899 | return -1; | |
900 | } | |
901 | ||
902 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, | |
903 | struct v4l2_dv_timings *timings) | |
54450f59 | 904 | { |
b44b2e06 | 905 | struct adv76xx_state *state = to_state(sd); |
ccbd5bc4 HV |
906 | int err; |
907 | ||
908 | v4l2_dbg(1, debug, sd, "%s", __func__); | |
909 | ||
b44b2e06 | 910 | if (adv76xx_has_afe(state)) { |
d42010a1 LPC |
911 | /* reset to default values */ |
912 | io_write(sd, 0x16, 0x43); | |
913 | io_write(sd, 0x17, 0x5a); | |
914 | } | |
ccbd5bc4 | 915 | /* disable embedded syncs for auto graphics mode */ |
22d97e56 | 916 | cp_write_clr_set(sd, 0x81, 0x10, 0x00); |
ccbd5bc4 HV |
917 | cp_write(sd, 0x8f, 0x00); |
918 | cp_write(sd, 0x90, 0x00); | |
919 | cp_write(sd, 0xa2, 0x00); | |
920 | cp_write(sd, 0xa3, 0x00); | |
921 | cp_write(sd, 0xa4, 0x00); | |
922 | cp_write(sd, 0xa5, 0x00); | |
923 | cp_write(sd, 0xa6, 0x00); | |
924 | cp_write(sd, 0xa7, 0x00); | |
925 | cp_write(sd, 0xab, 0x00); | |
926 | cp_write(sd, 0xac, 0x00); | |
927 | ||
4a31a93a | 928 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
929 | err = find_and_set_predefined_video_timings(sd, |
930 | 0x01, adv7604_prim_mode_comp, timings); | |
931 | if (err) | |
932 | err = find_and_set_predefined_video_timings(sd, | |
933 | 0x02, adv7604_prim_mode_gr, timings); | |
4a31a93a | 934 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 935 | err = find_and_set_predefined_video_timings(sd, |
b44b2e06 | 936 | 0x05, adv76xx_prim_mode_hdmi_comp, timings); |
ccbd5bc4 HV |
937 | if (err) |
938 | err = find_and_set_predefined_video_timings(sd, | |
b44b2e06 | 939 | 0x06, adv76xx_prim_mode_hdmi_gr, timings); |
4a31a93a MR |
940 | } else { |
941 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
942 | __func__, state->selected_input); | |
ccbd5bc4 | 943 | err = -1; |
ccbd5bc4 HV |
944 | } |
945 | ||
946 | ||
947 | return err; | |
948 | } | |
949 | ||
950 | static void configure_custom_video_timings(struct v4l2_subdev *sd, | |
951 | const struct v4l2_bt_timings *bt) | |
952 | { | |
b44b2e06 | 953 | struct adv76xx_state *state = to_state(sd); |
ccbd5bc4 HV |
954 | u32 width = htotal(bt); |
955 | u32 height = vtotal(bt); | |
956 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; | |
957 | u16 cp_start_eav = width - bt->hfrontporch; | |
958 | u16 cp_start_vbi = height - bt->vfrontporch; | |
959 | u16 cp_end_vbi = bt->vsync + bt->vbackporch; | |
960 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? | |
b44b2e06 | 961 | ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; |
ccbd5bc4 HV |
962 | const u8 pll[2] = { |
963 | 0xc0 | ((width >> 8) & 0x1f), | |
964 | width & 0xff | |
965 | }; | |
54450f59 HV |
966 | |
967 | v4l2_dbg(2, debug, sd, "%s\n", __func__); | |
968 | ||
4a31a93a | 969 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
970 | /* auto graphics */ |
971 | io_write(sd, 0x00, 0x07); /* video std */ | |
972 | io_write(sd, 0x01, 0x02); /* prim mode */ | |
973 | /* enable embedded syncs for auto graphics mode */ | |
22d97e56 | 974 | cp_write_clr_set(sd, 0x81, 0x10, 0x10); |
54450f59 | 975 | |
ccbd5bc4 | 976 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
54450f59 HV |
977 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
978 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ | |
b44b2e06 | 979 | if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO, |
05cacb17 | 980 | 0x16, 2, pll)) |
54450f59 | 981 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); |
54450f59 HV |
982 | |
983 | /* active video - horizontal timing */ | |
54450f59 | 984 | cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); |
ccbd5bc4 | 985 | cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | |
4a31a93a | 986 | ((cp_start_eav >> 8) & 0x0f)); |
54450f59 HV |
987 | cp_write(sd, 0xa4, cp_start_eav & 0xff); |
988 | ||
989 | /* active video - vertical timing */ | |
54450f59 | 990 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); |
ccbd5bc4 | 991 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | |
4a31a93a | 992 | ((cp_end_vbi >> 8) & 0xf)); |
54450f59 | 993 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); |
4a31a93a | 994 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 995 | /* set default prim_mode/vid_std for HDMI |
39c1cb2b | 996 | according to [REF_03, c. 4.2] */ |
ccbd5bc4 HV |
997 | io_write(sd, 0x00, 0x02); /* video std */ |
998 | io_write(sd, 0x01, 0x06); /* prim mode */ | |
4a31a93a MR |
999 | } else { |
1000 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1001 | __func__, state->selected_input); | |
54450f59 | 1002 | } |
54450f59 | 1003 | |
ccbd5bc4 HV |
1004 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); |
1005 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); | |
1006 | cp_write(sd, 0xab, (height >> 4) & 0xff); | |
1007 | cp_write(sd, 0xac, (height & 0x0f) << 4); | |
1008 | } | |
54450f59 | 1009 | |
b44b2e06 | 1010 | static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) |
5c6c6349 | 1011 | { |
b44b2e06 | 1012 | struct adv76xx_state *state = to_state(sd); |
5c6c6349 MR |
1013 | u8 offset_buf[4]; |
1014 | ||
1015 | if (auto_offset) { | |
1016 | offset_a = 0x3ff; | |
1017 | offset_b = 0x3ff; | |
1018 | offset_c = 0x3ff; | |
1019 | } | |
1020 | ||
1021 | v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1022 | __func__, auto_offset ? "Auto" : "Manual", | |
1023 | offset_a, offset_b, offset_c); | |
1024 | ||
1025 | offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); | |
1026 | offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); | |
1027 | offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); | |
1028 | offset_buf[3] = offset_c & 0x0ff; | |
1029 | ||
1030 | /* Registers must be written in this order with no i2c access in between */ | |
b44b2e06 | 1031 | if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP, |
05cacb17 | 1032 | 0x77, 4, offset_buf)) |
5c6c6349 MR |
1033 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); |
1034 | } | |
1035 | ||
b44b2e06 | 1036 | static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) |
5c6c6349 | 1037 | { |
b44b2e06 | 1038 | struct adv76xx_state *state = to_state(sd); |
5c6c6349 MR |
1039 | u8 gain_buf[4]; |
1040 | u8 gain_man = 1; | |
1041 | u8 agc_mode_man = 1; | |
1042 | ||
1043 | if (auto_gain) { | |
1044 | gain_man = 0; | |
1045 | agc_mode_man = 0; | |
1046 | gain_a = 0x100; | |
1047 | gain_b = 0x100; | |
1048 | gain_c = 0x100; | |
1049 | } | |
1050 | ||
1051 | v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1052 | __func__, auto_gain ? "Auto" : "Manual", | |
1053 | gain_a, gain_b, gain_c); | |
1054 | ||
1055 | gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); | |
1056 | gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); | |
1057 | gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); | |
1058 | gain_buf[3] = ((gain_c & 0x0ff)); | |
1059 | ||
1060 | /* Registers must be written in this order with no i2c access in between */ | |
b44b2e06 | 1061 | if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP, |
05cacb17 | 1062 | 0x73, 4, gain_buf)) |
5c6c6349 MR |
1063 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); |
1064 | } | |
1065 | ||
54450f59 HV |
1066 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) |
1067 | { | |
b44b2e06 | 1068 | struct adv76xx_state *state = to_state(sd); |
5c6c6349 MR |
1069 | bool rgb_output = io_read(sd, 0x02) & 0x02; |
1070 | bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; | |
1071 | ||
1072 | v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", | |
1073 | __func__, state->rgb_quantization_range, | |
1074 | rgb_output, hdmi_signal); | |
54450f59 | 1075 | |
b44b2e06 PA |
1076 | adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); |
1077 | adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); | |
9833239e | 1078 | |
54450f59 HV |
1079 | switch (state->rgb_quantization_range) { |
1080 | case V4L2_DV_RGB_RANGE_AUTO: | |
c784b1e2 | 1081 | if (state->selected_input == ADV7604_PAD_VGA_RGB) { |
9833239e MR |
1082 | /* Receiving analog RGB signal |
1083 | * Set RGB full range (0-255) */ | |
22d97e56 | 1084 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
9833239e MR |
1085 | break; |
1086 | } | |
1087 | ||
c784b1e2 | 1088 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
9833239e MR |
1089 | /* Receiving analog YPbPr signal |
1090 | * Set automode */ | |
22d97e56 | 1091 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); |
9833239e MR |
1092 | break; |
1093 | } | |
1094 | ||
5c6c6349 | 1095 | if (hdmi_signal) { |
9833239e MR |
1096 | /* Receiving HDMI signal |
1097 | * Set automode */ | |
22d97e56 | 1098 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); |
9833239e MR |
1099 | break; |
1100 | } | |
1101 | ||
1102 | /* Receiving DVI-D signal | |
1103 | * ADV7604 selects RGB limited range regardless of | |
1104 | * input format (CE/IT) in automatic mode */ | |
680fee04 | 1105 | if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { |
9833239e | 1106 | /* RGB limited range (16-235) */ |
22d97e56 | 1107 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); |
9833239e MR |
1108 | } else { |
1109 | /* RGB full range (0-255) */ | |
22d97e56 | 1110 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
5c6c6349 MR |
1111 | |
1112 | if (is_digital_input(sd) && rgb_output) { | |
b44b2e06 | 1113 | adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); |
5c6c6349 | 1114 | } else { |
b44b2e06 PA |
1115 | adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); |
1116 | adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); | |
5c6c6349 | 1117 | } |
54450f59 HV |
1118 | } |
1119 | break; | |
1120 | case V4L2_DV_RGB_RANGE_LIMITED: | |
c784b1e2 | 1121 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 | 1122 | /* YCrCb limited range (16-235) */ |
22d97e56 | 1123 | io_write_clr_set(sd, 0x02, 0xf0, 0x20); |
5c6c6349 | 1124 | break; |
d261e842 | 1125 | } |
5c6c6349 MR |
1126 | |
1127 | /* RGB limited range (16-235) */ | |
22d97e56 | 1128 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); |
5c6c6349 | 1129 | |
54450f59 HV |
1130 | break; |
1131 | case V4L2_DV_RGB_RANGE_FULL: | |
c784b1e2 | 1132 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 | 1133 | /* YCrCb full range (0-255) */ |
22d97e56 | 1134 | io_write_clr_set(sd, 0x02, 0xf0, 0x60); |
5c6c6349 MR |
1135 | break; |
1136 | } | |
1137 | ||
1138 | /* RGB full range (0-255) */ | |
22d97e56 | 1139 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
5c6c6349 MR |
1140 | |
1141 | if (is_analog_input(sd) || hdmi_signal) | |
1142 | break; | |
1143 | ||
1144 | /* Adjust gain/offset for DVI-D signals only */ | |
1145 | if (rgb_output) { | |
b44b2e06 | 1146 | adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); |
d261e842 | 1147 | } else { |
b44b2e06 PA |
1148 | adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); |
1149 | adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); | |
d261e842 | 1150 | } |
54450f59 HV |
1151 | break; |
1152 | } | |
1153 | } | |
1154 | ||
b44b2e06 | 1155 | static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) |
54450f59 | 1156 | { |
c269887c | 1157 | struct v4l2_subdev *sd = |
b44b2e06 | 1158 | &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; |
c269887c | 1159 | |
b44b2e06 | 1160 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
1161 | |
1162 | switch (ctrl->id) { | |
1163 | case V4L2_CID_BRIGHTNESS: | |
1164 | cp_write(sd, 0x3c, ctrl->val); | |
1165 | return 0; | |
1166 | case V4L2_CID_CONTRAST: | |
1167 | cp_write(sd, 0x3a, ctrl->val); | |
1168 | return 0; | |
1169 | case V4L2_CID_SATURATION: | |
1170 | cp_write(sd, 0x3b, ctrl->val); | |
1171 | return 0; | |
1172 | case V4L2_CID_HUE: | |
1173 | cp_write(sd, 0x3d, ctrl->val); | |
1174 | return 0; | |
1175 | case V4L2_CID_DV_RX_RGB_RANGE: | |
1176 | state->rgb_quantization_range = ctrl->val; | |
1177 | set_rgb_quantization_range(sd); | |
1178 | return 0; | |
1179 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: | |
b44b2e06 | 1180 | if (!adv76xx_has_afe(state)) |
d42010a1 | 1181 | return -EINVAL; |
54450f59 HV |
1182 | /* Set the analog sampling phase. This is needed to find the |
1183 | best sampling phase for analog video: an application or | |
1184 | driver has to try a number of phases and analyze the picture | |
1185 | quality before settling on the best performing phase. */ | |
1186 | afe_write(sd, 0xc8, ctrl->val); | |
1187 | return 0; | |
1188 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: | |
1189 | /* Use the default blue color for free running mode, | |
1190 | or supply your own. */ | |
22d97e56 | 1191 | cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); |
54450f59 HV |
1192 | return 0; |
1193 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: | |
1194 | cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); | |
1195 | cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); | |
1196 | cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); | |
1197 | return 0; | |
1198 | } | |
1199 | return -EINVAL; | |
1200 | } | |
1201 | ||
54450f59 HV |
1202 | /* ----------------------------------------------------------------------- */ |
1203 | ||
1204 | static inline bool no_power(struct v4l2_subdev *sd) | |
1205 | { | |
1206 | /* Entire chip or CP powered off */ | |
1207 | return io_read(sd, 0x0c) & 0x24; | |
1208 | } | |
1209 | ||
1210 | static inline bool no_signal_tmds(struct v4l2_subdev *sd) | |
1211 | { | |
b44b2e06 | 1212 | struct adv76xx_state *state = to_state(sd); |
4a31a93a MR |
1213 | |
1214 | return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); | |
54450f59 HV |
1215 | } |
1216 | ||
1217 | static inline bool no_lock_tmds(struct v4l2_subdev *sd) | |
1218 | { | |
b44b2e06 PA |
1219 | struct adv76xx_state *state = to_state(sd); |
1220 | const struct adv76xx_chip_info *info = state->info; | |
d42010a1 LPC |
1221 | |
1222 | return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; | |
54450f59 HV |
1223 | } |
1224 | ||
bb88f325 MB |
1225 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
1226 | { | |
1227 | return hdmi_read(sd, 0x05) & 0x80; | |
1228 | } | |
1229 | ||
54450f59 HV |
1230 | static inline bool no_lock_sspd(struct v4l2_subdev *sd) |
1231 | { | |
b44b2e06 | 1232 | struct adv76xx_state *state = to_state(sd); |
d42010a1 LPC |
1233 | |
1234 | /* | |
1235 | * Chips without a AFE don't expose registers for the SSPD, so just assume | |
1236 | * that we have a lock. | |
1237 | */ | |
b44b2e06 | 1238 | if (adv76xx_has_afe(state)) |
d42010a1 LPC |
1239 | return false; |
1240 | ||
54450f59 HV |
1241 | /* TODO channel 2 */ |
1242 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); | |
1243 | } | |
1244 | ||
1245 | static inline bool no_lock_stdi(struct v4l2_subdev *sd) | |
1246 | { | |
1247 | /* TODO channel 2 */ | |
1248 | return !(cp_read(sd, 0xb1) & 0x80); | |
1249 | } | |
1250 | ||
1251 | static inline bool no_signal(struct v4l2_subdev *sd) | |
1252 | { | |
54450f59 HV |
1253 | bool ret; |
1254 | ||
1255 | ret = no_power(sd); | |
1256 | ||
1257 | ret |= no_lock_stdi(sd); | |
1258 | ret |= no_lock_sspd(sd); | |
1259 | ||
4a31a93a | 1260 | if (is_digital_input(sd)) { |
54450f59 HV |
1261 | ret |= no_lock_tmds(sd); |
1262 | ret |= no_signal_tmds(sd); | |
1263 | } | |
1264 | ||
1265 | return ret; | |
1266 | } | |
1267 | ||
1268 | static inline bool no_lock_cp(struct v4l2_subdev *sd) | |
1269 | { | |
b44b2e06 | 1270 | struct adv76xx_state *state = to_state(sd); |
d42010a1 | 1271 | |
b44b2e06 | 1272 | if (!adv76xx_has_afe(state)) |
d42010a1 LPC |
1273 | return false; |
1274 | ||
54450f59 HV |
1275 | /* CP has detected a non standard number of lines on the incoming |
1276 | video compared to what it is configured to receive by s_dv_timings */ | |
1277 | return io_read(sd, 0x12) & 0x01; | |
1278 | } | |
1279 | ||
58514625 | 1280 | static inline bool in_free_run(struct v4l2_subdev *sd) |
1281 | { | |
1282 | return cp_read(sd, 0xff) & 0x10; | |
1283 | } | |
1284 | ||
b44b2e06 | 1285 | static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) |
54450f59 | 1286 | { |
54450f59 HV |
1287 | *status = 0; |
1288 | *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; | |
1289 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; | |
58514625 | 1290 | if (!in_free_run(sd) && no_lock_cp(sd)) |
1291 | *status |= is_digital_input(sd) ? | |
1292 | V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; | |
54450f59 HV |
1293 | |
1294 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | /* ----------------------------------------------------------------------- */ | |
1300 | ||
54450f59 HV |
1301 | struct stdi_readback { |
1302 | u16 bl, lcf, lcvs; | |
1303 | u8 hs_pol, vs_pol; | |
1304 | bool interlaced; | |
1305 | }; | |
1306 | ||
1307 | static int stdi2dv_timings(struct v4l2_subdev *sd, | |
1308 | struct stdi_readback *stdi, | |
1309 | struct v4l2_dv_timings *timings) | |
1310 | { | |
b44b2e06 PA |
1311 | struct adv76xx_state *state = to_state(sd); |
1312 | u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; | |
54450f59 HV |
1313 | u32 pix_clk; |
1314 | int i; | |
1315 | ||
b44b2e06 PA |
1316 | for (i = 0; adv76xx_timings[i].bt.height; i++) { |
1317 | if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1) | |
54450f59 | 1318 | continue; |
b44b2e06 | 1319 | if (adv76xx_timings[i].bt.vsync != stdi->lcvs) |
54450f59 HV |
1320 | continue; |
1321 | ||
b44b2e06 | 1322 | pix_clk = hfreq * htotal(&adv76xx_timings[i].bt); |
54450f59 | 1323 | |
b44b2e06 PA |
1324 | if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) && |
1325 | (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) { | |
1326 | *timings = adv76xx_timings[i]; | |
54450f59 HV |
1327 | return 0; |
1328 | } | |
1329 | } | |
1330 | ||
1331 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1332 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1333 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
061ddda6 | 1334 | false, timings)) |
54450f59 HV |
1335 | return 0; |
1336 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1337 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1338 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
061ddda6 | 1339 | false, state->aspect_ratio, timings)) |
54450f59 HV |
1340 | return 0; |
1341 | ||
ccbd5bc4 HV |
1342 | v4l2_dbg(2, debug, sd, |
1343 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", | |
1344 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, | |
1345 | stdi->hs_pol, stdi->vs_pol); | |
54450f59 HV |
1346 | return -1; |
1347 | } | |
1348 | ||
d42010a1 | 1349 | |
54450f59 HV |
1350 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) |
1351 | { | |
b44b2e06 PA |
1352 | struct adv76xx_state *state = to_state(sd); |
1353 | const struct adv76xx_chip_info *info = state->info; | |
4a2ccdd2 LP |
1354 | u8 polarity; |
1355 | ||
54450f59 HV |
1356 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { |
1357 | v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); | |
1358 | return -1; | |
1359 | } | |
1360 | ||
1361 | /* read STDI */ | |
51182a94 | 1362 | stdi->bl = cp_read16(sd, 0xb1, 0x3fff); |
d42010a1 | 1363 | stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); |
54450f59 HV |
1364 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; |
1365 | stdi->interlaced = io_read(sd, 0x12) & 0x10; | |
1366 | ||
b44b2e06 | 1367 | if (adv76xx_has_afe(state)) { |
d42010a1 LPC |
1368 | /* read SSPD */ |
1369 | polarity = cp_read(sd, 0xb5); | |
1370 | if ((polarity & 0x03) == 0x01) { | |
1371 | stdi->hs_pol = polarity & 0x10 | |
1372 | ? (polarity & 0x08 ? '+' : '-') : 'x'; | |
1373 | stdi->vs_pol = polarity & 0x40 | |
1374 | ? (polarity & 0x20 ? '+' : '-') : 'x'; | |
1375 | } else { | |
1376 | stdi->hs_pol = 'x'; | |
1377 | stdi->vs_pol = 'x'; | |
1378 | } | |
54450f59 | 1379 | } else { |
d42010a1 LPC |
1380 | polarity = hdmi_read(sd, 0x05); |
1381 | stdi->hs_pol = polarity & 0x20 ? '+' : '-'; | |
1382 | stdi->vs_pol = polarity & 0x10 ? '+' : '-'; | |
54450f59 HV |
1383 | } |
1384 | ||
1385 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1386 | v4l2_dbg(2, debug, sd, | |
1387 | "%s: signal lost during readout of STDI/SSPD\n", __func__); | |
1388 | return -1; | |
1389 | } | |
1390 | ||
1391 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { | |
1392 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); | |
1393 | memset(stdi, 0, sizeof(struct stdi_readback)); | |
1394 | return -1; | |
1395 | } | |
1396 | ||
1397 | v4l2_dbg(2, debug, sd, | |
1398 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", | |
1399 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, | |
1400 | stdi->hs_pol, stdi->vs_pol, | |
1401 | stdi->interlaced ? "interlaced" : "progressive"); | |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
b44b2e06 | 1406 | static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1407 | struct v4l2_enum_dv_timings *timings) |
1408 | { | |
b44b2e06 | 1409 | struct adv76xx_state *state = to_state(sd); |
afec5599 | 1410 | |
b44b2e06 | 1411 | if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1) |
54450f59 | 1412 | return -EINVAL; |
afec5599 LP |
1413 | |
1414 | if (timings->pad >= state->source_pad) | |
1415 | return -EINVAL; | |
1416 | ||
54450f59 | 1417 | memset(timings->reserved, 0, sizeof(timings->reserved)); |
b44b2e06 | 1418 | timings->timings = adv76xx_timings[timings->index]; |
54450f59 HV |
1419 | return 0; |
1420 | } | |
1421 | ||
b44b2e06 | 1422 | static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, |
7515e096 | 1423 | struct v4l2_dv_timings_cap *cap) |
54450f59 | 1424 | { |
b44b2e06 | 1425 | struct adv76xx_state *state = to_state(sd); |
7515e096 LP |
1426 | |
1427 | if (cap->pad >= state->source_pad) | |
1428 | return -EINVAL; | |
1429 | ||
54450f59 HV |
1430 | cap->type = V4L2_DV_BT_656_1120; |
1431 | cap->bt.max_width = 1920; | |
1432 | cap->bt.max_height = 1200; | |
fe9c2564 | 1433 | cap->bt.min_pixelclock = 25000000; |
afec5599 | 1434 | |
7515e096 | 1435 | switch (cap->pad) { |
b44b2e06 | 1436 | case ADV76XX_PAD_HDMI_PORT_A: |
afec5599 LP |
1437 | case ADV7604_PAD_HDMI_PORT_B: |
1438 | case ADV7604_PAD_HDMI_PORT_C: | |
1439 | case ADV7604_PAD_HDMI_PORT_D: | |
54450f59 | 1440 | cap->bt.max_pixelclock = 225000000; |
afec5599 LP |
1441 | break; |
1442 | case ADV7604_PAD_VGA_RGB: | |
1443 | case ADV7604_PAD_VGA_COMP: | |
1444 | default: | |
54450f59 | 1445 | cap->bt.max_pixelclock = 170000000; |
afec5599 LP |
1446 | break; |
1447 | } | |
1448 | ||
54450f59 HV |
1449 | cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
1450 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; | |
1451 | cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | | |
1452 | V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; | |
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings | |
b44b2e06 PA |
1457 | if the format is listed in adv76xx_timings[] */ |
1458 | static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, | |
54450f59 HV |
1459 | struct v4l2_dv_timings *timings) |
1460 | { | |
54450f59 HV |
1461 | int i; |
1462 | ||
b44b2e06 PA |
1463 | for (i = 0; adv76xx_timings[i].bt.width; i++) { |
1464 | if (v4l2_match_dv_timings(timings, &adv76xx_timings[i], | |
4a31a93a | 1465 | is_digital_input(sd) ? 250000 : 1000000)) { |
b44b2e06 | 1466 | *timings = adv76xx_timings[i]; |
54450f59 HV |
1467 | break; |
1468 | } | |
1469 | } | |
1470 | } | |
1471 | ||
d42010a1 LPC |
1472 | static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) |
1473 | { | |
1474 | unsigned int freq; | |
1475 | int a, b; | |
1476 | ||
1477 | a = hdmi_read(sd, 0x06); | |
1478 | b = hdmi_read(sd, 0x3b); | |
1479 | if (a < 0 || b < 0) | |
1480 | return 0; | |
1481 | freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; | |
1482 | ||
1483 | if (is_hdmi(sd)) { | |
1484 | /* adjust for deep color mode */ | |
1485 | unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; | |
1486 | ||
1487 | freq = freq * 8 / bits_per_channel; | |
1488 | } | |
1489 | ||
1490 | return freq; | |
1491 | } | |
1492 | ||
1493 | static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) | |
1494 | { | |
1495 | int a, b; | |
1496 | ||
1497 | a = hdmi_read(sd, 0x51); | |
1498 | b = hdmi_read(sd, 0x52); | |
1499 | if (a < 0 || b < 0) | |
1500 | return 0; | |
1501 | return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; | |
1502 | } | |
1503 | ||
b44b2e06 | 1504 | static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1505 | struct v4l2_dv_timings *timings) |
1506 | { | |
b44b2e06 PA |
1507 | struct adv76xx_state *state = to_state(sd); |
1508 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 HV |
1509 | struct v4l2_bt_timings *bt = &timings->bt; |
1510 | struct stdi_readback stdi; | |
1511 | ||
1512 | if (!timings) | |
1513 | return -EINVAL; | |
1514 | ||
1515 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1516 | ||
1517 | if (no_signal(sd)) { | |
1e0b9156 | 1518 | state->restart_stdi_once = true; |
54450f59 HV |
1519 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); |
1520 | return -ENOLINK; | |
1521 | } | |
1522 | ||
1523 | /* read STDI */ | |
1524 | if (read_stdi(sd, &stdi)) { | |
1525 | v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); | |
1526 | return -ENOLINK; | |
1527 | } | |
1528 | bt->interlaced = stdi.interlaced ? | |
1529 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; | |
1530 | ||
4a31a93a | 1531 | if (is_digital_input(sd)) { |
54450f59 HV |
1532 | timings->type = V4L2_DV_BT_656_1120; |
1533 | ||
5380baaf | 1534 | bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask); |
1535 | bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask); | |
d42010a1 | 1536 | bt->pixelclock = info->read_hdmi_pixelclock(sd); |
5380baaf | 1537 | bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); |
1538 | bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); | |
1539 | bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); | |
1540 | bt->vfrontporch = hdmi_read16(sd, 0x2a, | |
1541 | info->field0_vfrontporch_mask) / 2; | |
1542 | bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; | |
1543 | bt->vbackporch = hdmi_read16(sd, 0x32, | |
1544 | info->field0_vbackporch_mask) / 2; | |
54450f59 HV |
1545 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | |
1546 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); | |
1547 | if (bt->interlaced == V4L2_DV_INTERLACED) { | |
5380baaf | 1548 | bt->height += hdmi_read16(sd, 0x0b, |
1549 | info->field1_height_mask); | |
1550 | bt->il_vfrontporch = hdmi_read16(sd, 0x2c, | |
1551 | info->field1_vfrontporch_mask) / 2; | |
1552 | bt->il_vsync = hdmi_read16(sd, 0x30, | |
1553 | info->field1_vsync_mask) / 2; | |
1554 | bt->il_vbackporch = hdmi_read16(sd, 0x34, | |
1555 | info->field1_vbackporch_mask) / 2; | |
54450f59 | 1556 | } |
b44b2e06 | 1557 | adv76xx_fill_optional_dv_timings_fields(sd, timings); |
54450f59 HV |
1558 | } else { |
1559 | /* find format | |
80939647 | 1560 | * Since LCVS values are inaccurate [REF_03, p. 275-276], |
54450f59 HV |
1561 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. |
1562 | */ | |
1563 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1564 | goto found; | |
1565 | stdi.lcvs += 1; | |
1566 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); | |
1567 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1568 | goto found; | |
1569 | stdi.lcvs -= 2; | |
1570 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); | |
1571 | if (stdi2dv_timings(sd, &stdi, timings)) { | |
cf9afb1d HV |
1572 | /* |
1573 | * The STDI block may measure wrong values, especially | |
1574 | * for lcvs and lcf. If the driver can not find any | |
1575 | * valid timing, the STDI block is restarted to measure | |
1576 | * the video timings again. The function will return an | |
1577 | * error, but the restart of STDI will generate a new | |
1578 | * STDI interrupt and the format detection process will | |
1579 | * restart. | |
1580 | */ | |
1581 | if (state->restart_stdi_once) { | |
1582 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); | |
1583 | /* TODO restart STDI for Sync Channel 2 */ | |
1584 | /* enter one-shot mode */ | |
22d97e56 | 1585 | cp_write_clr_set(sd, 0x86, 0x06, 0x00); |
cf9afb1d | 1586 | /* trigger STDI restart */ |
22d97e56 | 1587 | cp_write_clr_set(sd, 0x86, 0x06, 0x04); |
cf9afb1d | 1588 | /* reset to continuous mode */ |
22d97e56 | 1589 | cp_write_clr_set(sd, 0x86, 0x06, 0x02); |
cf9afb1d HV |
1590 | state->restart_stdi_once = false; |
1591 | return -ENOLINK; | |
1592 | } | |
54450f59 HV |
1593 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); |
1594 | return -ERANGE; | |
1595 | } | |
cf9afb1d | 1596 | state->restart_stdi_once = true; |
54450f59 HV |
1597 | } |
1598 | found: | |
1599 | ||
1600 | if (no_signal(sd)) { | |
1601 | v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); | |
1602 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1603 | return -ENOLINK; | |
1604 | } | |
1605 | ||
4a31a93a MR |
1606 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1607 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1608 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1609 | __func__, (u32)bt->pixelclock); | |
1610 | return -ERANGE; | |
1611 | } | |
1612 | ||
1613 | if (debug > 1) | |
b44b2e06 | 1614 | v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", |
11d034c8 | 1615 | timings, true); |
54450f59 HV |
1616 | |
1617 | return 0; | |
1618 | } | |
1619 | ||
b44b2e06 | 1620 | static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1621 | struct v4l2_dv_timings *timings) |
1622 | { | |
b44b2e06 | 1623 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 1624 | struct v4l2_bt_timings *bt; |
ccbd5bc4 | 1625 | int err; |
54450f59 HV |
1626 | |
1627 | if (!timings) | |
1628 | return -EINVAL; | |
1629 | ||
d48eb48c MR |
1630 | if (v4l2_match_dv_timings(&state->timings, timings, 0)) { |
1631 | v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); | |
1632 | return 0; | |
1633 | } | |
1634 | ||
54450f59 HV |
1635 | bt = &timings->bt; |
1636 | ||
4a31a93a MR |
1637 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1638 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1639 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1640 | __func__, (u32)bt->pixelclock); | |
1641 | return -ERANGE; | |
1642 | } | |
ccbd5bc4 | 1643 | |
b44b2e06 | 1644 | adv76xx_fill_optional_dv_timings_fields(sd, timings); |
54450f59 HV |
1645 | |
1646 | state->timings = *timings; | |
1647 | ||
22d97e56 | 1648 | cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); |
ccbd5bc4 HV |
1649 | |
1650 | /* Use prim_mode and vid_std when available */ | |
1651 | err = configure_predefined_video_timings(sd, timings); | |
1652 | if (err) { | |
1653 | /* custom settings when the video format | |
1654 | does not have prim_mode/vid_std */ | |
1655 | configure_custom_video_timings(sd, bt); | |
1656 | } | |
54450f59 HV |
1657 | |
1658 | set_rgb_quantization_range(sd); | |
1659 | ||
54450f59 | 1660 | if (debug > 1) |
b44b2e06 | 1661 | v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", |
11d034c8 | 1662 | timings, true); |
54450f59 HV |
1663 | return 0; |
1664 | } | |
1665 | ||
b44b2e06 | 1666 | static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1667 | struct v4l2_dv_timings *timings) |
1668 | { | |
b44b2e06 | 1669 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
1670 | |
1671 | *timings = state->timings; | |
1672 | return 0; | |
1673 | } | |
1674 | ||
d42010a1 LPC |
1675 | static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) |
1676 | { | |
1677 | hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); | |
1678 | } | |
1679 | ||
1680 | static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) | |
1681 | { | |
1682 | hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); | |
1683 | } | |
1684 | ||
6b0d5d34 | 1685 | static void enable_input(struct v4l2_subdev *sd) |
54450f59 | 1686 | { |
b44b2e06 | 1687 | struct adv76xx_state *state = to_state(sd); |
6b0d5d34 | 1688 | |
4a31a93a | 1689 | if (is_analog_input(sd)) { |
54450f59 | 1690 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ |
4a31a93a | 1691 | } else if (is_digital_input(sd)) { |
22d97e56 | 1692 | hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); |
d42010a1 | 1693 | state->info->set_termination(sd, true); |
54450f59 | 1694 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ |
22d97e56 | 1695 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ |
4a31a93a MR |
1696 | } else { |
1697 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1698 | __func__, state->selected_input); | |
54450f59 HV |
1699 | } |
1700 | } | |
1701 | ||
1702 | static void disable_input(struct v4l2_subdev *sd) | |
1703 | { | |
b44b2e06 | 1704 | struct adv76xx_state *state = to_state(sd); |
d42010a1 | 1705 | |
22d97e56 | 1706 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ |
5474b983 | 1707 | msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ |
54450f59 | 1708 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ |
d42010a1 | 1709 | state->info->set_termination(sd, false); |
54450f59 HV |
1710 | } |
1711 | ||
6b0d5d34 | 1712 | static void select_input(struct v4l2_subdev *sd) |
54450f59 | 1713 | { |
b44b2e06 PA |
1714 | struct adv76xx_state *state = to_state(sd); |
1715 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 | 1716 | |
4a31a93a | 1717 | if (is_analog_input(sd)) { |
b44b2e06 | 1718 | adv76xx_write_reg_seq(sd, info->recommended_settings[0]); |
54450f59 HV |
1719 | |
1720 | afe_write(sd, 0x00, 0x08); /* power up ADC */ | |
1721 | afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ | |
1722 | afe_write(sd, 0xc8, 0x00); /* phase control */ | |
4a31a93a MR |
1723 | } else if (is_digital_input(sd)) { |
1724 | hdmi_write(sd, 0x00, state->selected_input & 0x03); | |
54450f59 | 1725 | |
b44b2e06 | 1726 | adv76xx_write_reg_seq(sd, info->recommended_settings[1]); |
d42010a1 | 1727 | |
b44b2e06 | 1728 | if (adv76xx_has_afe(state)) { |
d42010a1 LPC |
1729 | afe_write(sd, 0x00, 0xff); /* power down ADC */ |
1730 | afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ | |
1731 | afe_write(sd, 0xc8, 0x40); /* phase control */ | |
1732 | } | |
1733 | ||
54450f59 HV |
1734 | cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ |
1735 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1736 | cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ | |
4a31a93a MR |
1737 | } else { |
1738 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1739 | __func__, state->selected_input); | |
54450f59 HV |
1740 | } |
1741 | } | |
1742 | ||
b44b2e06 | 1743 | static int adv76xx_s_routing(struct v4l2_subdev *sd, |
54450f59 HV |
1744 | u32 input, u32 output, u32 config) |
1745 | { | |
b44b2e06 | 1746 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 1747 | |
ff4f80fd MR |
1748 | v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", |
1749 | __func__, input, state->selected_input); | |
1750 | ||
1751 | if (input == state->selected_input) | |
1752 | return 0; | |
54450f59 | 1753 | |
d42010a1 LPC |
1754 | if (input > state->info->max_port) |
1755 | return -EINVAL; | |
1756 | ||
4a31a93a | 1757 | state->selected_input = input; |
54450f59 HV |
1758 | |
1759 | disable_input(sd); | |
6b0d5d34 | 1760 | select_input(sd); |
6b0d5d34 | 1761 | enable_input(sd); |
54450f59 | 1762 | |
48519838 HV |
1763 | v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT, |
1764 | (void *)&adv76xx_ev_fmt); | |
54450f59 HV |
1765 | return 0; |
1766 | } | |
1767 | ||
b44b2e06 | 1768 | static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, |
f7234138 | 1769 | struct v4l2_subdev_pad_config *cfg, |
539b33b0 | 1770 | struct v4l2_subdev_mbus_code_enum *code) |
54450f59 | 1771 | { |
b44b2e06 | 1772 | struct adv76xx_state *state = to_state(sd); |
539b33b0 LP |
1773 | |
1774 | if (code->index >= state->info->nformats) | |
54450f59 | 1775 | return -EINVAL; |
539b33b0 LP |
1776 | |
1777 | code->code = state->info->formats[code->index].code; | |
1778 | ||
54450f59 HV |
1779 | return 0; |
1780 | } | |
1781 | ||
b44b2e06 | 1782 | static void adv76xx_fill_format(struct adv76xx_state *state, |
539b33b0 | 1783 | struct v4l2_mbus_framefmt *format) |
54450f59 | 1784 | { |
539b33b0 | 1785 | memset(format, 0, sizeof(*format)); |
54450f59 | 1786 | |
539b33b0 LP |
1787 | format->width = state->timings.bt.width; |
1788 | format->height = state->timings.bt.height; | |
1789 | format->field = V4L2_FIELD_NONE; | |
680fee04 | 1790 | format->colorspace = V4L2_COLORSPACE_SRGB; |
539b33b0 | 1791 | |
680fee04 | 1792 | if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) |
539b33b0 | 1793 | format->colorspace = (state->timings.bt.height <= 576) ? |
54450f59 | 1794 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; |
539b33b0 LP |
1795 | } |
1796 | ||
1797 | /* | |
1798 | * Compute the op_ch_sel value required to obtain on the bus the component order | |
1799 | * corresponding to the selected format taking into account bus reordering | |
1800 | * applied by the board at the output of the device. | |
1801 | * | |
1802 | * The following table gives the op_ch_value from the format component order | |
1803 | * (expressed as op_ch_sel value in column) and the bus reordering (expressed as | |
b44b2e06 | 1804 | * adv76xx_bus_order value in row). |
539b33b0 LP |
1805 | * |
1806 | * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) | |
1807 | * ----------+------------------------------------------------- | |
1808 | * RGB (NOP) | GBR GRB BGR RGB BRG RBG | |
1809 | * GRB (1-2) | BGR RGB GBR GRB RBG BRG | |
1810 | * RBG (2-3) | GRB GBR BRG RBG BGR RGB | |
1811 | * BGR (1-3) | RBG BRG RGB BGR GRB GBR | |
1812 | * BRG (ROR) | BRG RBG GRB GBR RGB BGR | |
1813 | * GBR (ROL) | RGB BGR RBG BRG GBR GRB | |
1814 | */ | |
b44b2e06 | 1815 | static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) |
539b33b0 LP |
1816 | { |
1817 | #define _SEL(a,b,c,d,e,f) { \ | |
b44b2e06 PA |
1818 | ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ |
1819 | ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } | |
539b33b0 LP |
1820 | #define _BUS(x) [ADV7604_BUS_ORDER_##x] |
1821 | ||
1822 | static const unsigned int op_ch_sel[6][6] = { | |
1823 | _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), | |
1824 | _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), | |
1825 | _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), | |
1826 | _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), | |
1827 | _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), | |
1828 | _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), | |
1829 | }; | |
1830 | ||
1831 | return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; | |
1832 | } | |
1833 | ||
b44b2e06 | 1834 | static void adv76xx_setup_format(struct adv76xx_state *state) |
539b33b0 LP |
1835 | { |
1836 | struct v4l2_subdev *sd = &state->sd; | |
1837 | ||
22d97e56 | 1838 | io_write_clr_set(sd, 0x02, 0x02, |
b44b2e06 | 1839 | state->format->rgb_out ? ADV76XX_RGB_OUT : 0); |
539b33b0 LP |
1840 | io_write(sd, 0x03, state->format->op_format_sel | |
1841 | state->pdata.op_format_mode_sel); | |
b44b2e06 | 1842 | io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); |
22d97e56 | 1843 | io_write_clr_set(sd, 0x05, 0x01, |
b44b2e06 | 1844 | state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); |
539b33b0 LP |
1845 | } |
1846 | ||
f7234138 HV |
1847 | static int adv76xx_get_format(struct v4l2_subdev *sd, |
1848 | struct v4l2_subdev_pad_config *cfg, | |
539b33b0 LP |
1849 | struct v4l2_subdev_format *format) |
1850 | { | |
b44b2e06 | 1851 | struct adv76xx_state *state = to_state(sd); |
539b33b0 LP |
1852 | |
1853 | if (format->pad != state->source_pad) | |
1854 | return -EINVAL; | |
1855 | ||
b44b2e06 | 1856 | adv76xx_fill_format(state, &format->format); |
539b33b0 LP |
1857 | |
1858 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1859 | struct v4l2_mbus_framefmt *fmt; | |
1860 | ||
f7234138 | 1861 | fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); |
539b33b0 LP |
1862 | format->format.code = fmt->code; |
1863 | } else { | |
1864 | format->format.code = state->format->code; | |
54450f59 | 1865 | } |
539b33b0 LP |
1866 | |
1867 | return 0; | |
1868 | } | |
1869 | ||
f7234138 HV |
1870 | static int adv76xx_set_format(struct v4l2_subdev *sd, |
1871 | struct v4l2_subdev_pad_config *cfg, | |
539b33b0 LP |
1872 | struct v4l2_subdev_format *format) |
1873 | { | |
b44b2e06 PA |
1874 | struct adv76xx_state *state = to_state(sd); |
1875 | const struct adv76xx_format_info *info; | |
539b33b0 LP |
1876 | |
1877 | if (format->pad != state->source_pad) | |
1878 | return -EINVAL; | |
1879 | ||
b44b2e06 | 1880 | info = adv76xx_format_info(state, format->format.code); |
539b33b0 | 1881 | if (info == NULL) |
b44b2e06 | 1882 | info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); |
539b33b0 | 1883 | |
b44b2e06 | 1884 | adv76xx_fill_format(state, &format->format); |
539b33b0 LP |
1885 | format->format.code = info->code; |
1886 | ||
1887 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1888 | struct v4l2_mbus_framefmt *fmt; | |
1889 | ||
f7234138 | 1890 | fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); |
539b33b0 LP |
1891 | fmt->code = format->format.code; |
1892 | } else { | |
1893 | state->format = info; | |
b44b2e06 | 1894 | adv76xx_setup_format(state); |
539b33b0 LP |
1895 | } |
1896 | ||
54450f59 HV |
1897 | return 0; |
1898 | } | |
1899 | ||
b44b2e06 | 1900 | static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) |
54450f59 | 1901 | { |
b44b2e06 PA |
1902 | struct adv76xx_state *state = to_state(sd); |
1903 | const struct adv76xx_chip_info *info = state->info; | |
f24d229c MR |
1904 | const u8 irq_reg_0x43 = io_read(sd, 0x43); |
1905 | const u8 irq_reg_0x6b = io_read(sd, 0x6b); | |
1906 | const u8 irq_reg_0x70 = io_read(sd, 0x70); | |
1907 | u8 fmt_change_digital; | |
1908 | u8 fmt_change; | |
1909 | u8 tx_5v; | |
1910 | ||
1911 | if (irq_reg_0x43) | |
1912 | io_write(sd, 0x44, irq_reg_0x43); | |
1913 | if (irq_reg_0x70) | |
1914 | io_write(sd, 0x71, irq_reg_0x70); | |
1915 | if (irq_reg_0x6b) | |
1916 | io_write(sd, 0x6c, irq_reg_0x6b); | |
54450f59 | 1917 | |
ff4f80fd MR |
1918 | v4l2_dbg(2, debug, sd, "%s: ", __func__); |
1919 | ||
54450f59 | 1920 | /* format change */ |
f24d229c | 1921 | fmt_change = irq_reg_0x43 & 0x98; |
d42010a1 LPC |
1922 | fmt_change_digital = is_digital_input(sd) |
1923 | ? irq_reg_0x6b & info->fmt_change_digital_mask | |
1924 | : 0; | |
14d03233 | 1925 | |
54450f59 HV |
1926 | if (fmt_change || fmt_change_digital) { |
1927 | v4l2_dbg(1, debug, sd, | |
25a64ac9 | 1928 | "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", |
54450f59 | 1929 | __func__, fmt_change, fmt_change_digital); |
25a64ac9 | 1930 | |
48519838 HV |
1931 | v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT, |
1932 | (void *)&adv76xx_ev_fmt); | |
25a64ac9 | 1933 | |
54450f59 HV |
1934 | if (handled) |
1935 | *handled = true; | |
1936 | } | |
f24d229c MR |
1937 | /* HDMI/DVI mode */ |
1938 | if (irq_reg_0x6b & 0x01) { | |
1939 | v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, | |
1940 | (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); | |
1941 | set_rgb_quantization_range(sd); | |
1942 | if (handled) | |
1943 | *handled = true; | |
1944 | } | |
1945 | ||
54450f59 | 1946 | /* tx 5v detect */ |
d42010a1 | 1947 | tx_5v = io_read(sd, 0x70) & info->cable_det_mask; |
54450f59 HV |
1948 | if (tx_5v) { |
1949 | v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); | |
1950 | io_write(sd, 0x71, tx_5v); | |
b44b2e06 | 1951 | adv76xx_s_detect_tx_5v_ctrl(sd); |
54450f59 HV |
1952 | if (handled) |
1953 | *handled = true; | |
1954 | } | |
1955 | return 0; | |
1956 | } | |
1957 | ||
b44b2e06 | 1958 | static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 | 1959 | { |
b44b2e06 | 1960 | struct adv76xx_state *state = to_state(sd); |
4a31a93a | 1961 | u8 *data = NULL; |
54450f59 | 1962 | |
dd9ac11a | 1963 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
4a31a93a MR |
1964 | |
1965 | switch (edid->pad) { | |
b44b2e06 | 1966 | case ADV76XX_PAD_HDMI_PORT_A: |
c784b1e2 LP |
1967 | case ADV7604_PAD_HDMI_PORT_B: |
1968 | case ADV7604_PAD_HDMI_PORT_C: | |
1969 | case ADV7604_PAD_HDMI_PORT_D: | |
4a31a93a MR |
1970 | if (state->edid.present & (1 << edid->pad)) |
1971 | data = state->edid.edid; | |
1972 | break; | |
1973 | default: | |
1974 | return -EINVAL; | |
4a31a93a | 1975 | } |
dd9ac11a HV |
1976 | |
1977 | if (edid->start_block == 0 && edid->blocks == 0) { | |
1978 | edid->blocks = data ? state->edid.blocks : 0; | |
1979 | return 0; | |
1980 | } | |
1981 | ||
1982 | if (data == NULL) | |
4a31a93a MR |
1983 | return -ENODATA; |
1984 | ||
dd9ac11a HV |
1985 | if (edid->start_block >= state->edid.blocks) |
1986 | return -EINVAL; | |
1987 | ||
1988 | if (edid->start_block + edid->blocks > state->edid.blocks) | |
1989 | edid->blocks = state->edid.blocks - edid->start_block; | |
1990 | ||
1991 | memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); | |
1992 | ||
54450f59 HV |
1993 | return 0; |
1994 | } | |
1995 | ||
dd08beb9 | 1996 | static int get_edid_spa_location(const u8 *edid) |
3e86aa85 MR |
1997 | { |
1998 | u8 d; | |
1999 | ||
2000 | if ((edid[0x7e] != 1) || | |
2001 | (edid[0x80] != 0x02) || | |
2002 | (edid[0x81] != 0x03)) { | |
2003 | return -1; | |
2004 | } | |
2005 | ||
2006 | /* search Vendor Specific Data Block (tag 3) */ | |
2007 | d = edid[0x82] & 0x7f; | |
2008 | if (d > 4) { | |
2009 | int i = 0x84; | |
2010 | int end = 0x80 + d; | |
2011 | ||
2012 | do { | |
2013 | u8 tag = edid[i] >> 5; | |
2014 | u8 len = edid[i] & 0x1f; | |
2015 | ||
2016 | if ((tag == 3) && (len >= 5)) | |
2017 | return i + 4; | |
2018 | i += len + 1; | |
2019 | } while (i < end); | |
2020 | } | |
2021 | return -1; | |
2022 | } | |
2023 | ||
b44b2e06 | 2024 | static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 | 2025 | { |
b44b2e06 PA |
2026 | struct adv76xx_state *state = to_state(sd); |
2027 | const struct adv76xx_chip_info *info = state->info; | |
dd08beb9 | 2028 | int spa_loc; |
54450f59 | 2029 | int err; |
dd08beb9 | 2030 | int i; |
54450f59 | 2031 | |
dd9ac11a HV |
2032 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
2033 | ||
c784b1e2 | 2034 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) |
54450f59 HV |
2035 | return -EINVAL; |
2036 | if (edid->start_block != 0) | |
2037 | return -EINVAL; | |
2038 | if (edid->blocks == 0) { | |
3e86aa85 | 2039 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a | 2040 | state->edid.present &= ~(1 << edid->pad); |
b44b2e06 | 2041 | adv76xx_set_hpd(state, state->edid.present); |
22d97e56 | 2042 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); |
3e86aa85 | 2043 | |
54450f59 HV |
2044 | /* Fall back to a 16:9 aspect ratio */ |
2045 | state->aspect_ratio.numerator = 16; | |
2046 | state->aspect_ratio.denominator = 9; | |
3e86aa85 MR |
2047 | |
2048 | if (!state->edid.present) | |
2049 | state->edid.blocks = 0; | |
2050 | ||
2051 | v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", | |
2052 | __func__, edid->pad, state->edid.present); | |
54450f59 HV |
2053 | return 0; |
2054 | } | |
4a31a93a MR |
2055 | if (edid->blocks > 2) { |
2056 | edid->blocks = 2; | |
54450f59 | 2057 | return -E2BIG; |
4a31a93a | 2058 | } |
4a31a93a | 2059 | |
dd08beb9 MR |
2060 | v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", |
2061 | __func__, edid->pad, state->edid.present); | |
2062 | ||
3e86aa85 | 2063 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a | 2064 | cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); |
b44b2e06 | 2065 | adv76xx_set_hpd(state, 0); |
22d97e56 | 2066 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); |
3e86aa85 | 2067 | |
dd08beb9 MR |
2068 | spa_loc = get_edid_spa_location(edid->edid); |
2069 | if (spa_loc < 0) | |
2070 | spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ | |
2071 | ||
3e86aa85 | 2072 | switch (edid->pad) { |
b44b2e06 | 2073 | case ADV76XX_PAD_HDMI_PORT_A: |
dd08beb9 MR |
2074 | state->spa_port_a[0] = edid->edid[spa_loc]; |
2075 | state->spa_port_a[1] = edid->edid[spa_loc + 1]; | |
3e86aa85 | 2076 | break; |
c784b1e2 | 2077 | case ADV7604_PAD_HDMI_PORT_B: |
dd08beb9 MR |
2078 | rep_write(sd, 0x70, edid->edid[spa_loc]); |
2079 | rep_write(sd, 0x71, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2080 | break; |
c784b1e2 | 2081 | case ADV7604_PAD_HDMI_PORT_C: |
dd08beb9 MR |
2082 | rep_write(sd, 0x72, edid->edid[spa_loc]); |
2083 | rep_write(sd, 0x73, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2084 | break; |
c784b1e2 | 2085 | case ADV7604_PAD_HDMI_PORT_D: |
dd08beb9 MR |
2086 | rep_write(sd, 0x74, edid->edid[spa_loc]); |
2087 | rep_write(sd, 0x75, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2088 | break; |
dd08beb9 MR |
2089 | default: |
2090 | return -EINVAL; | |
3e86aa85 | 2091 | } |
d42010a1 LPC |
2092 | |
2093 | if (info->type == ADV7604) { | |
2094 | rep_write(sd, 0x76, spa_loc & 0xff); | |
22d97e56 | 2095 | rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); |
d42010a1 LPC |
2096 | } else { |
2097 | /* FIXME: Where is the SPA location LSB register ? */ | |
22d97e56 | 2098 | rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); |
d42010a1 | 2099 | } |
3e86aa85 | 2100 | |
dd08beb9 MR |
2101 | edid->edid[spa_loc] = state->spa_port_a[0]; |
2102 | edid->edid[spa_loc + 1] = state->spa_port_a[1]; | |
4a31a93a MR |
2103 | |
2104 | memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); | |
2105 | state->edid.blocks = edid->blocks; | |
54450f59 HV |
2106 | state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], |
2107 | edid->edid[0x16]); | |
3e86aa85 | 2108 | state->edid.present |= 1 << edid->pad; |
4a31a93a MR |
2109 | |
2110 | err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); | |
2111 | if (err < 0) { | |
3e86aa85 | 2112 | v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); |
4a31a93a MR |
2113 | return err; |
2114 | } | |
2115 | ||
b44b2e06 | 2116 | /* adv76xx calculates the checksums and enables I2C access to internal |
dd08beb9 | 2117 | EDID RAM from DDC port. */ |
22d97e56 | 2118 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); |
dd08beb9 MR |
2119 | |
2120 | for (i = 0; i < 1000; i++) { | |
d42010a1 | 2121 | if (rep_read(sd, info->edid_status_reg) & state->edid.present) |
dd08beb9 MR |
2122 | break; |
2123 | mdelay(1); | |
2124 | } | |
2125 | if (i == 1000) { | |
2126 | v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); | |
2127 | return -EIO; | |
2128 | } | |
2129 | ||
4a31a93a MR |
2130 | /* enable hotplug after 100 ms */ |
2131 | queue_delayed_work(state->work_queues, | |
2132 | &state->delayed_work_enable_hotplug, HZ / 10); | |
2133 | return 0; | |
54450f59 HV |
2134 | } |
2135 | ||
2136 | /*********** avi info frame CEA-861-E **************/ | |
2137 | ||
516613c1 HV |
2138 | static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { |
2139 | { "AVI", 0x01, 0xe0, 0x00 }, | |
2140 | { "Audio", 0x02, 0xe3, 0x1c }, | |
2141 | { "SDP", 0x04, 0xe6, 0x2a }, | |
2142 | { "Vendor", 0x10, 0xec, 0x54 } | |
2143 | }; | |
2144 | ||
2145 | static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, | |
2146 | union hdmi_infoframe *frame) | |
54450f59 | 2147 | { |
516613c1 HV |
2148 | uint8_t buffer[32]; |
2149 | u8 len; | |
54450f59 | 2150 | int i; |
54450f59 | 2151 | |
516613c1 HV |
2152 | if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { |
2153 | v4l2_info(sd, "%s infoframe not received\n", | |
2154 | adv76xx_cri[index].desc); | |
2155 | return -ENOENT; | |
54450f59 | 2156 | } |
516613c1 HV |
2157 | |
2158 | for (i = 0; i < 3; i++) | |
2159 | buffer[i] = infoframe_read(sd, | |
2160 | adv76xx_cri[index].head_addr + i); | |
2161 | ||
2162 | len = buffer[2] + 1; | |
2163 | ||
2164 | if (len + 3 > sizeof(buffer)) { | |
2165 | v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, | |
2166 | adv76xx_cri[index].desc, len); | |
2167 | return -ENOENT; | |
54450f59 HV |
2168 | } |
2169 | ||
516613c1 HV |
2170 | for (i = 0; i < len; i++) |
2171 | buffer[i + 3] = infoframe_read(sd, | |
2172 | adv76xx_cri[index].payload_addr + i); | |
2173 | ||
2174 | if (hdmi_infoframe_unpack(frame, buffer) < 0) { | |
2175 | v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, | |
2176 | adv76xx_cri[index].desc); | |
2177 | return -ENOENT; | |
54450f59 | 2178 | } |
516613c1 HV |
2179 | return 0; |
2180 | } | |
54450f59 | 2181 | |
516613c1 HV |
2182 | static void adv76xx_log_infoframes(struct v4l2_subdev *sd) |
2183 | { | |
2184 | int i; | |
54450f59 | 2185 | |
516613c1 HV |
2186 | if (!is_hdmi(sd)) { |
2187 | v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); | |
54450f59 | 2188 | return; |
516613c1 | 2189 | } |
54450f59 | 2190 | |
516613c1 HV |
2191 | for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { |
2192 | union hdmi_infoframe frame; | |
2193 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
54450f59 | 2194 | |
516613c1 HV |
2195 | if (adv76xx_read_infoframe(sd, i, &frame)) |
2196 | return; | |
2197 | hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); | |
2198 | } | |
54450f59 HV |
2199 | } |
2200 | ||
b44b2e06 | 2201 | static int adv76xx_log_status(struct v4l2_subdev *sd) |
54450f59 | 2202 | { |
b44b2e06 PA |
2203 | struct adv76xx_state *state = to_state(sd); |
2204 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 HV |
2205 | struct v4l2_dv_timings timings; |
2206 | struct stdi_readback stdi; | |
2207 | u8 reg_io_0x02 = io_read(sd, 0x02); | |
4a2ccdd2 LP |
2208 | u8 edid_enabled; |
2209 | u8 cable_det; | |
54450f59 | 2210 | |
f216ccb3 | 2211 | static const char * const csc_coeff_sel_rb[16] = { |
54450f59 HV |
2212 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", |
2213 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", | |
2214 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", | |
2215 | "reserved", "reserved", "reserved", "reserved", "manual" | |
2216 | }; | |
f216ccb3 | 2217 | static const char * const input_color_space_txt[16] = { |
54450f59 HV |
2218 | "RGB limited range (16-235)", "RGB full range (0-255)", |
2219 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
9833239e | 2220 | "xvYCC Bt.601", "xvYCC Bt.709", |
54450f59 HV |
2221 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", |
2222 | "invalid", "invalid", "invalid", "invalid", "invalid", | |
2223 | "invalid", "invalid", "automatic" | |
2224 | }; | |
7a5d99e7 HV |
2225 | static const char * const hdmi_color_space_txt[16] = { |
2226 | "RGB limited range (16-235)", "RGB full range (0-255)", | |
2227 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
2228 | "xvYCC Bt.601", "xvYCC Bt.709", | |
2229 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", | |
2230 | "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid", | |
2231 | "invalid", "invalid", "invalid" | |
2232 | }; | |
f216ccb3 | 2233 | static const char * const rgb_quantization_range_txt[] = { |
54450f59 HV |
2234 | "Automatic", |
2235 | "RGB limited range (16-235)", | |
2236 | "RGB full range (0-255)", | |
2237 | }; | |
f216ccb3 | 2238 | static const char * const deep_color_mode_txt[4] = { |
bb88f325 MB |
2239 | "8-bits per channel", |
2240 | "10-bits per channel", | |
2241 | "12-bits per channel", | |
2242 | "16-bits per channel (not supported)" | |
2243 | }; | |
54450f59 HV |
2244 | |
2245 | v4l2_info(sd, "-----Chip status-----\n"); | |
2246 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); | |
d42010a1 | 2247 | edid_enabled = rep_read(sd, info->edid_status_reg); |
4a31a93a | 2248 | v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", |
4a2ccdd2 LP |
2249 | ((edid_enabled & 0x01) ? "Yes" : "No"), |
2250 | ((edid_enabled & 0x02) ? "Yes" : "No"), | |
2251 | ((edid_enabled & 0x04) ? "Yes" : "No"), | |
2252 | ((edid_enabled & 0x08) ? "Yes" : "No")); | |
54450f59 HV |
2253 | v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? |
2254 | "enabled" : "disabled"); | |
2255 | ||
2256 | v4l2_info(sd, "-----Signal status-----\n"); | |
d42010a1 | 2257 | cable_det = info->read_cable_det(sd); |
4a31a93a | 2258 | v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", |
d42010a1 LPC |
2259 | ((cable_det & 0x01) ? "Yes" : "No"), |
2260 | ((cable_det & 0x02) ? "Yes" : "No"), | |
4a2ccdd2 | 2261 | ((cable_det & 0x04) ? "Yes" : "No"), |
d42010a1 | 2262 | ((cable_det & 0x08) ? "Yes" : "No")); |
54450f59 HV |
2263 | v4l2_info(sd, "TMDS signal detected: %s\n", |
2264 | no_signal_tmds(sd) ? "false" : "true"); | |
2265 | v4l2_info(sd, "TMDS signal locked: %s\n", | |
2266 | no_lock_tmds(sd) ? "false" : "true"); | |
2267 | v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); | |
2268 | v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); | |
2269 | v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); | |
2270 | v4l2_info(sd, "CP free run: %s\n", | |
58514625 | 2271 | (in_free_run(sd)) ? "on" : "off"); |
ccbd5bc4 HV |
2272 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", |
2273 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, | |
2274 | (io_read(sd, 0x01) & 0x70) >> 4); | |
54450f59 HV |
2275 | |
2276 | v4l2_info(sd, "-----Video Timings-----\n"); | |
2277 | if (read_stdi(sd, &stdi)) | |
2278 | v4l2_info(sd, "STDI: not locked\n"); | |
2279 | else | |
2280 | v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", | |
2281 | stdi.lcf, stdi.bl, stdi.lcvs, | |
2282 | stdi.interlaced ? "interlaced" : "progressive", | |
2283 | stdi.hs_pol, stdi.vs_pol); | |
b44b2e06 | 2284 | if (adv76xx_query_dv_timings(sd, &timings)) |
54450f59 HV |
2285 | v4l2_info(sd, "No video detected\n"); |
2286 | else | |
11d034c8 HV |
2287 | v4l2_print_dv_timings(sd->name, "Detected format: ", |
2288 | &timings, true); | |
2289 | v4l2_print_dv_timings(sd->name, "Configured format: ", | |
2290 | &state->timings, true); | |
54450f59 | 2291 | |
76eb2d30 MR |
2292 | if (no_signal(sd)) |
2293 | return 0; | |
2294 | ||
54450f59 HV |
2295 | v4l2_info(sd, "-----Color space-----\n"); |
2296 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", | |
2297 | rgb_quantization_range_txt[state->rgb_quantization_range]); | |
2298 | v4l2_info(sd, "Input color space: %s\n", | |
2299 | input_color_space_txt[reg_io_0x02 >> 4]); | |
7a5d99e7 | 2300 | v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n", |
54450f59 HV |
2301 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", |
2302 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", | |
5dd7d88a | 2303 | (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? |
7a5d99e7 HV |
2304 | "enabled" : "disabled", |
2305 | (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); | |
54450f59 | 2306 | v4l2_info(sd, "Color space conversion: %s\n", |
80f4944e | 2307 | csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); |
54450f59 | 2308 | |
4a31a93a | 2309 | if (!is_digital_input(sd)) |
76eb2d30 MR |
2310 | return 0; |
2311 | ||
2312 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); | |
4a31a93a MR |
2313 | v4l2_info(sd, "Digital video port selected: %c\n", |
2314 | (hdmi_read(sd, 0x00) & 0x03) + 'A'); | |
2315 | v4l2_info(sd, "HDCP encrypted content: %s\n", | |
2316 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); | |
76eb2d30 MR |
2317 | v4l2_info(sd, "HDCP keys read: %s%s\n", |
2318 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", | |
2319 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); | |
77639ff2 | 2320 | if (is_hdmi(sd)) { |
76eb2d30 MR |
2321 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; |
2322 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; | |
2323 | bool audio_mute = io_read(sd, 0x65) & 0x40; | |
2324 | ||
2325 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", | |
2326 | audio_pll_locked ? "locked" : "not locked", | |
2327 | audio_sample_packet_detect ? "detected" : "not detected", | |
2328 | audio_mute ? "muted" : "enabled"); | |
2329 | if (audio_pll_locked && audio_sample_packet_detect) { | |
2330 | v4l2_info(sd, "Audio format: %s\n", | |
2331 | (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); | |
2332 | } | |
2333 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + | |
2334 | (hdmi_read(sd, 0x5c) << 8) + | |
2335 | (hdmi_read(sd, 0x5d) & 0xf0)); | |
2336 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + | |
2337 | (hdmi_read(sd, 0x5e) << 8) + | |
2338 | hdmi_read(sd, 0x5f)); | |
2339 | v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); | |
2340 | ||
2341 | v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); | |
7a5d99e7 | 2342 | v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); |
76eb2d30 | 2343 | |
516613c1 | 2344 | adv76xx_log_infoframes(sd); |
54450f59 HV |
2345 | } |
2346 | ||
2347 | return 0; | |
2348 | } | |
2349 | ||
2350 | /* ----------------------------------------------------------------------- */ | |
2351 | ||
b44b2e06 PA |
2352 | static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { |
2353 | .s_ctrl = adv76xx_s_ctrl, | |
54450f59 HV |
2354 | }; |
2355 | ||
b44b2e06 PA |
2356 | static const struct v4l2_subdev_core_ops adv76xx_core_ops = { |
2357 | .log_status = adv76xx_log_status, | |
2358 | .interrupt_service_routine = adv76xx_isr, | |
54450f59 | 2359 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
b44b2e06 PA |
2360 | .g_register = adv76xx_g_register, |
2361 | .s_register = adv76xx_s_register, | |
54450f59 HV |
2362 | #endif |
2363 | }; | |
2364 | ||
b44b2e06 PA |
2365 | static const struct v4l2_subdev_video_ops adv76xx_video_ops = { |
2366 | .s_routing = adv76xx_s_routing, | |
2367 | .g_input_status = adv76xx_g_input_status, | |
2368 | .s_dv_timings = adv76xx_s_dv_timings, | |
2369 | .g_dv_timings = adv76xx_g_dv_timings, | |
2370 | .query_dv_timings = adv76xx_query_dv_timings, | |
54450f59 HV |
2371 | }; |
2372 | ||
b44b2e06 PA |
2373 | static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { |
2374 | .enum_mbus_code = adv76xx_enum_mbus_code, | |
2375 | .get_fmt = adv76xx_get_format, | |
2376 | .set_fmt = adv76xx_set_format, | |
2377 | .get_edid = adv76xx_get_edid, | |
2378 | .set_edid = adv76xx_set_edid, | |
2379 | .dv_timings_cap = adv76xx_dv_timings_cap, | |
2380 | .enum_dv_timings = adv76xx_enum_dv_timings, | |
54450f59 HV |
2381 | }; |
2382 | ||
b44b2e06 PA |
2383 | static const struct v4l2_subdev_ops adv76xx_ops = { |
2384 | .core = &adv76xx_core_ops, | |
2385 | .video = &adv76xx_video_ops, | |
2386 | .pad = &adv76xx_pad_ops, | |
54450f59 HV |
2387 | }; |
2388 | ||
2389 | /* -------------------------- custom ctrls ---------------------------------- */ | |
2390 | ||
2391 | static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { | |
b44b2e06 | 2392 | .ops = &adv76xx_ctrl_ops, |
54450f59 HV |
2393 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, |
2394 | .name = "Analog Sampling Phase", | |
2395 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2396 | .min = 0, | |
2397 | .max = 0x1f, | |
2398 | .step = 1, | |
2399 | .def = 0, | |
2400 | }; | |
2401 | ||
b44b2e06 PA |
2402 | static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { |
2403 | .ops = &adv76xx_ctrl_ops, | |
54450f59 HV |
2404 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, |
2405 | .name = "Free Running Color, Manual", | |
2406 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
2407 | .min = false, | |
2408 | .max = true, | |
2409 | .step = 1, | |
2410 | .def = false, | |
2411 | }; | |
2412 | ||
b44b2e06 PA |
2413 | static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { |
2414 | .ops = &adv76xx_ctrl_ops, | |
54450f59 HV |
2415 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, |
2416 | .name = "Free Running Color", | |
2417 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2418 | .min = 0x0, | |
2419 | .max = 0xffffff, | |
2420 | .step = 0x1, | |
2421 | .def = 0x0, | |
2422 | }; | |
2423 | ||
2424 | /* ----------------------------------------------------------------------- */ | |
2425 | ||
b44b2e06 | 2426 | static int adv76xx_core_init(struct v4l2_subdev *sd) |
54450f59 | 2427 | { |
b44b2e06 PA |
2428 | struct adv76xx_state *state = to_state(sd); |
2429 | const struct adv76xx_chip_info *info = state->info; | |
2430 | struct adv76xx_platform_data *pdata = &state->pdata; | |
54450f59 HV |
2431 | |
2432 | hdmi_write(sd, 0x48, | |
2433 | (pdata->disable_pwrdnb ? 0x80 : 0) | | |
2434 | (pdata->disable_cable_det_rst ? 0x40 : 0)); | |
2435 | ||
2436 | disable_input(sd); | |
2437 | ||
5ef54b59 LP |
2438 | if (pdata->default_input >= 0 && |
2439 | pdata->default_input < state->source_pad) { | |
2440 | state->selected_input = pdata->default_input; | |
2441 | select_input(sd); | |
2442 | enable_input(sd); | |
2443 | } | |
2444 | ||
54450f59 HV |
2445 | /* power */ |
2446 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ | |
2447 | io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ | |
2448 | cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ | |
2449 | ||
2450 | /* video format */ | |
22d97e56 | 2451 | io_write_clr_set(sd, 0x02, 0x0f, |
54450f59 HV |
2452 | pdata->alt_gamma << 3 | |
2453 | pdata->op_656_range << 2 | | |
54450f59 | 2454 | pdata->alt_data_sat << 0); |
22d97e56 | 2455 | io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | |
539b33b0 LP |
2456 | pdata->insert_av_codes << 2 | |
2457 | pdata->replicate_av_codes << 1); | |
b44b2e06 | 2458 | adv76xx_setup_format(state); |
54450f59 | 2459 | |
54450f59 | 2460 | cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ |
98908696 MB |
2461 | |
2462 | /* VS, HS polarities */ | |
1b5ab875 LP |
2463 | io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | |
2464 | pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); | |
f31b62e1 MK |
2465 | |
2466 | /* Adjust drive strength */ | |
2467 | io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | | |
2468 | pdata->dr_str_clk << 2 | | |
2469 | pdata->dr_str_sync); | |
2470 | ||
54450f59 HV |
2471 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ |
2472 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ | |
2473 | cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - | |
80939647 | 2474 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 | 2475 | cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - |
80939647 | 2476 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 HV |
2477 | cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution |
2478 | for digital formats */ | |
2479 | ||
5474b983 | 2480 | /* HDMI audio */ |
22d97e56 LP |
2481 | hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ |
2482 | hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ | |
2483 | hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ | |
5474b983 | 2484 | |
54450f59 HV |
2485 | /* TODO from platform data */ |
2486 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ | |
2487 | ||
b44b2e06 | 2488 | if (adv76xx_has_afe(state)) { |
d42010a1 | 2489 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ |
22d97e56 | 2490 | io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); |
d42010a1 | 2491 | } |
54450f59 | 2492 | |
54450f59 | 2493 | /* interrupts */ |
d42010a1 | 2494 | io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ |
54450f59 | 2495 | io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ |
d42010a1 LPC |
2496 | io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ |
2497 | io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ | |
2498 | info->setup_irqs(sd); | |
54450f59 HV |
2499 | |
2500 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); | |
2501 | } | |
2502 | ||
d42010a1 LPC |
2503 | static void adv7604_setup_irqs(struct v4l2_subdev *sd) |
2504 | { | |
2505 | io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ | |
2506 | } | |
2507 | ||
2508 | static void adv7611_setup_irqs(struct v4l2_subdev *sd) | |
2509 | { | |
2510 | io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ | |
2511 | } | |
2512 | ||
b44b2e06 | 2513 | static void adv76xx_unregister_clients(struct adv76xx_state *state) |
54450f59 | 2514 | { |
05cacb17 LP |
2515 | unsigned int i; |
2516 | ||
2517 | for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { | |
2518 | if (state->i2c_clients[i]) | |
2519 | i2c_unregister_device(state->i2c_clients[i]); | |
2520 | } | |
54450f59 HV |
2521 | } |
2522 | ||
b44b2e06 | 2523 | static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, |
54450f59 HV |
2524 | u8 addr, u8 io_reg) |
2525 | { | |
2526 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2527 | ||
2528 | if (addr) | |
2529 | io_write(sd, io_reg, addr << 1); | |
2530 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); | |
2531 | } | |
2532 | ||
b44b2e06 | 2533 | static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { |
d42010a1 LPC |
2534 | /* reset ADI recommended settings for HDMI: */ |
2535 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
b44b2e06 PA |
2536 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ |
2537 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2538 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ | |
2539 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ | |
2540 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2541 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ | |
2542 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ | |
2543 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2544 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2545 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ | |
2546 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ | |
2547 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ | |
d42010a1 LPC |
2548 | |
2549 | /* set ADI recommended settings for digitizer */ | |
2550 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
b44b2e06 PA |
2551 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ |
2552 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ | |
2553 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ | |
2554 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ | |
2555 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ | |
d42010a1 | 2556 | |
b44b2e06 | 2557 | { ADV76XX_REG_SEQ_TERM, 0 }, |
d42010a1 LPC |
2558 | }; |
2559 | ||
b44b2e06 | 2560 | static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { |
d42010a1 LPC |
2561 | /* set ADI recommended settings for HDMI: */ |
2562 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
b44b2e06 PA |
2563 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ |
2564 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ | |
2565 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ | |
2566 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2567 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ | |
2568 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ | |
2569 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2570 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2571 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ | |
2572 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ | |
2573 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ | |
d42010a1 LPC |
2574 | |
2575 | /* reset ADI recommended settings for digitizer */ | |
2576 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
b44b2e06 PA |
2577 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ |
2578 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ | |
d42010a1 | 2579 | |
b44b2e06 | 2580 | { ADV76XX_REG_SEQ_TERM, 0 }, |
d42010a1 LPC |
2581 | }; |
2582 | ||
b44b2e06 | 2583 | static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { |
c41ad9c3 | 2584 | /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ |
b44b2e06 PA |
2585 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, |
2586 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, | |
2587 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, | |
2588 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, | |
2589 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, | |
2590 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, | |
2591 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, | |
2592 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, | |
2593 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, | |
2594 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, | |
2595 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, | |
2596 | ||
2597 | { ADV76XX_REG_SEQ_TERM, 0 }, | |
d42010a1 LPC |
2598 | }; |
2599 | ||
b44b2e06 | 2600 | static const struct adv76xx_chip_info adv76xx_chip_info[] = { |
d42010a1 LPC |
2601 | [ADV7604] = { |
2602 | .type = ADV7604, | |
2603 | .has_afe = true, | |
c784b1e2 | 2604 | .max_port = ADV7604_PAD_VGA_COMP, |
d42010a1 LPC |
2605 | .num_dv_ports = 4, |
2606 | .edid_enable_reg = 0x77, | |
2607 | .edid_status_reg = 0x7d, | |
2608 | .lcf_reg = 0xb3, | |
2609 | .tdms_lock_mask = 0xe0, | |
2610 | .cable_det_mask = 0x1e, | |
2611 | .fmt_change_digital_mask = 0xc1, | |
80f4944e | 2612 | .cp_csc = 0xfc, |
539b33b0 LP |
2613 | .formats = adv7604_formats, |
2614 | .nformats = ARRAY_SIZE(adv7604_formats), | |
d42010a1 LPC |
2615 | .set_termination = adv7604_set_termination, |
2616 | .setup_irqs = adv7604_setup_irqs, | |
2617 | .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, | |
2618 | .read_cable_det = adv7604_read_cable_det, | |
2619 | .recommended_settings = { | |
2620 | [0] = adv7604_recommended_settings_afe, | |
2621 | [1] = adv7604_recommended_settings_hdmi, | |
2622 | }, | |
2623 | .num_recommended_settings = { | |
2624 | [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), | |
2625 | [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), | |
2626 | }, | |
b44b2e06 PA |
2627 | .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | |
2628 | BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | | |
d42010a1 | 2629 | BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | |
b44b2e06 PA |
2630 | BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | |
2631 | BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | | |
2632 | BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | | |
d42010a1 | 2633 | BIT(ADV7604_PAGE_VDP), |
5380baaf | 2634 | .linewidth_mask = 0xfff, |
2635 | .field0_height_mask = 0xfff, | |
2636 | .field1_height_mask = 0xfff, | |
2637 | .hfrontporch_mask = 0x3ff, | |
2638 | .hsync_mask = 0x3ff, | |
2639 | .hbackporch_mask = 0x3ff, | |
2640 | .field0_vfrontporch_mask = 0x1fff, | |
2641 | .field0_vsync_mask = 0x1fff, | |
2642 | .field0_vbackporch_mask = 0x1fff, | |
2643 | .field1_vfrontporch_mask = 0x1fff, | |
2644 | .field1_vsync_mask = 0x1fff, | |
2645 | .field1_vbackporch_mask = 0x1fff, | |
d42010a1 LPC |
2646 | }, |
2647 | [ADV7611] = { | |
2648 | .type = ADV7611, | |
2649 | .has_afe = false, | |
b44b2e06 | 2650 | .max_port = ADV76XX_PAD_HDMI_PORT_A, |
d42010a1 LPC |
2651 | .num_dv_ports = 1, |
2652 | .edid_enable_reg = 0x74, | |
2653 | .edid_status_reg = 0x76, | |
2654 | .lcf_reg = 0xa3, | |
2655 | .tdms_lock_mask = 0x43, | |
2656 | .cable_det_mask = 0x01, | |
2657 | .fmt_change_digital_mask = 0x03, | |
80f4944e | 2658 | .cp_csc = 0xf4, |
539b33b0 LP |
2659 | .formats = adv7611_formats, |
2660 | .nformats = ARRAY_SIZE(adv7611_formats), | |
d42010a1 LPC |
2661 | .set_termination = adv7611_set_termination, |
2662 | .setup_irqs = adv7611_setup_irqs, | |
2663 | .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, | |
2664 | .read_cable_det = adv7611_read_cable_det, | |
2665 | .recommended_settings = { | |
2666 | [1] = adv7611_recommended_settings_hdmi, | |
2667 | }, | |
2668 | .num_recommended_settings = { | |
2669 | [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), | |
2670 | }, | |
b44b2e06 PA |
2671 | .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | |
2672 | BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | | |
2673 | BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | | |
2674 | BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), | |
5380baaf | 2675 | .linewidth_mask = 0x1fff, |
2676 | .field0_height_mask = 0x1fff, | |
2677 | .field1_height_mask = 0x1fff, | |
2678 | .hfrontporch_mask = 0x1fff, | |
2679 | .hsync_mask = 0x1fff, | |
2680 | .hbackporch_mask = 0x1fff, | |
2681 | .field0_vfrontporch_mask = 0x3fff, | |
2682 | .field0_vsync_mask = 0x3fff, | |
2683 | .field0_vbackporch_mask = 0x3fff, | |
2684 | .field1_vfrontporch_mask = 0x3fff, | |
2685 | .field1_vsync_mask = 0x3fff, | |
2686 | .field1_vbackporch_mask = 0x3fff, | |
d42010a1 LPC |
2687 | }, |
2688 | }; | |
2689 | ||
7f099a75 | 2690 | static const struct i2c_device_id adv76xx_i2c_id[] = { |
b44b2e06 PA |
2691 | { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, |
2692 | { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, | |
f82f313e LP |
2693 | { } |
2694 | }; | |
b44b2e06 | 2695 | MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); |
f82f313e | 2696 | |
7f099a75 | 2697 | static const struct of_device_id adv76xx_of_id[] __maybe_unused = { |
b44b2e06 | 2698 | { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, |
f82f313e LP |
2699 | { } |
2700 | }; | |
b44b2e06 | 2701 | MODULE_DEVICE_TABLE(of, adv76xx_of_id); |
f82f313e | 2702 | |
b44b2e06 | 2703 | static int adv76xx_parse_dt(struct adv76xx_state *state) |
f82f313e | 2704 | { |
6fa88045 LP |
2705 | struct v4l2_of_endpoint bus_cfg; |
2706 | struct device_node *endpoint; | |
2707 | struct device_node *np; | |
2708 | unsigned int flags; | |
2709 | ||
b44b2e06 | 2710 | np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; |
6fa88045 LP |
2711 | |
2712 | /* Parse the endpoint. */ | |
2713 | endpoint = of_graph_get_next_endpoint(np, NULL); | |
2714 | if (!endpoint) | |
2715 | return -EINVAL; | |
2716 | ||
2717 | v4l2_of_parse_endpoint(endpoint, &bus_cfg); | |
2718 | of_node_put(endpoint); | |
2719 | ||
2720 | flags = bus_cfg.bus.parallel.flags; | |
2721 | ||
2722 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
2723 | state->pdata.inv_hs_pol = 1; | |
2724 | ||
2725 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
2726 | state->pdata.inv_vs_pol = 1; | |
2727 | ||
2728 | if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
2729 | state->pdata.inv_llc_pol = 1; | |
2730 | ||
2731 | if (bus_cfg.bus_type == V4L2_MBUS_BT656) { | |
2732 | state->pdata.insert_av_codes = 1; | |
2733 | state->pdata.op_656_range = 1; | |
2734 | } | |
2735 | ||
f82f313e | 2736 | /* Disable the interrupt for now as no DT-based board uses it. */ |
b44b2e06 | 2737 | state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; |
f82f313e LP |
2738 | |
2739 | /* Use the default I2C addresses. */ | |
2740 | state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; | |
b44b2e06 PA |
2741 | state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40; |
2742 | state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e; | |
f82f313e LP |
2743 | state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; |
2744 | state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; | |
b44b2e06 PA |
2745 | state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26; |
2746 | state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32; | |
2747 | state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36; | |
2748 | state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34; | |
2749 | state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30; | |
2750 | state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22; | |
f82f313e LP |
2751 | state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; |
2752 | ||
2753 | /* Hardcode the remaining platform data fields. */ | |
2754 | state->pdata.disable_pwrdnb = 0; | |
2755 | state->pdata.disable_cable_det_rst = 0; | |
2756 | state->pdata.default_input = -1; | |
2757 | state->pdata.blank_data = 1; | |
f82f313e | 2758 | state->pdata.alt_data_sat = 1; |
f82f313e LP |
2759 | state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; |
2760 | state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; | |
2761 | ||
2762 | return 0; | |
2763 | } | |
2764 | ||
b44b2e06 | 2765 | static int adv76xx_probe(struct i2c_client *client, |
54450f59 HV |
2766 | const struct i2c_device_id *id) |
2767 | { | |
591b72fe HV |
2768 | static const struct v4l2_dv_timings cea640x480 = |
2769 | V4L2_DV_BT_CEA_640X480P59_94; | |
b44b2e06 | 2770 | struct adv76xx_state *state; |
54450f59 HV |
2771 | struct v4l2_ctrl_handler *hdl; |
2772 | struct v4l2_subdev *sd; | |
c784b1e2 | 2773 | unsigned int i; |
d42010a1 | 2774 | u16 val; |
54450f59 HV |
2775 | int err; |
2776 | ||
2777 | /* Check if the adapter supports the needed features */ | |
2778 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
2779 | return -EIO; | |
b44b2e06 | 2780 | v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", |
54450f59 HV |
2781 | client->addr << 1); |
2782 | ||
c02b211d | 2783 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
54450f59 | 2784 | if (!state) { |
b44b2e06 | 2785 | v4l_err(client, "Could not allocate adv76xx_state memory!\n"); |
54450f59 HV |
2786 | return -ENOMEM; |
2787 | } | |
2788 | ||
b44b2e06 | 2789 | state->i2c_clients[ADV76XX_PAGE_IO] = client; |
d42010a1 | 2790 | |
25a64ac9 MR |
2791 | /* initialize variables */ |
2792 | state->restart_stdi_once = true; | |
ff4f80fd | 2793 | state->selected_input = ~0; |
25a64ac9 | 2794 | |
f82f313e LP |
2795 | if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { |
2796 | const struct of_device_id *oid; | |
2797 | ||
b44b2e06 | 2798 | oid = of_match_node(adv76xx_of_id, client->dev.of_node); |
f82f313e LP |
2799 | state->info = oid->data; |
2800 | ||
b44b2e06 | 2801 | err = adv76xx_parse_dt(state); |
f82f313e LP |
2802 | if (err < 0) { |
2803 | v4l_err(client, "DT parsing error\n"); | |
2804 | return err; | |
2805 | } | |
2806 | } else if (client->dev.platform_data) { | |
b44b2e06 | 2807 | struct adv76xx_platform_data *pdata = client->dev.platform_data; |
f82f313e | 2808 | |
b44b2e06 | 2809 | state->info = (const struct adv76xx_chip_info *)id->driver_data; |
f82f313e LP |
2810 | state->pdata = *pdata; |
2811 | } else { | |
54450f59 | 2812 | v4l_err(client, "No platform data!\n"); |
c02b211d | 2813 | return -ENODEV; |
54450f59 | 2814 | } |
e9d50e9e LP |
2815 | |
2816 | /* Request GPIOs. */ | |
2817 | for (i = 0; i < state->info->num_dv_ports; ++i) { | |
2818 | state->hpd_gpio[i] = | |
269bd132 UKK |
2819 | devm_gpiod_get_index_optional(&client->dev, "hpd", i, |
2820 | GPIOD_OUT_LOW); | |
e9d50e9e | 2821 | if (IS_ERR(state->hpd_gpio[i])) |
269bd132 | 2822 | return PTR_ERR(state->hpd_gpio[i]); |
e9d50e9e | 2823 | |
269bd132 UKK |
2824 | if (state->hpd_gpio[i]) |
2825 | v4l_info(client, "Handling HPD %u GPIO\n", i); | |
e9d50e9e LP |
2826 | } |
2827 | ||
591b72fe | 2828 | state->timings = cea640x480; |
b44b2e06 | 2829 | state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); |
54450f59 HV |
2830 | |
2831 | sd = &state->sd; | |
b44b2e06 | 2832 | v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); |
d42010a1 LPC |
2833 | snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", |
2834 | id->name, i2c_adapter_id(client->adapter), | |
2835 | client->addr); | |
54450f59 | 2836 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
54450f59 | 2837 | |
d42010a1 LPC |
2838 | /* |
2839 | * Verify that the chip is present. On ADV7604 the RD_INFO register only | |
2840 | * identifies the revision, while on ADV7611 it identifies the model as | |
2841 | * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. | |
2842 | */ | |
2843 | if (state->info->type == ADV7604) { | |
2844 | val = adv_smbus_read_byte_data_check(client, 0xfb, false); | |
2845 | if (val != 0x68) { | |
2846 | v4l2_info(sd, "not an adv7604 on address 0x%x\n", | |
2847 | client->addr << 1); | |
2848 | return -ENODEV; | |
2849 | } | |
2850 | } else { | |
2851 | val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) | |
2852 | | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); | |
2853 | if (val != 0x2051) { | |
2854 | v4l2_info(sd, "not an adv7611 on address 0x%x\n", | |
2855 | client->addr << 1); | |
2856 | return -ENODEV; | |
2857 | } | |
54450f59 HV |
2858 | } |
2859 | ||
2860 | /* control handlers */ | |
2861 | hdl = &state->hdl; | |
b44b2e06 | 2862 | v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); |
54450f59 | 2863 | |
b44b2e06 | 2864 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 | 2865 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); |
b44b2e06 | 2866 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 | 2867 | V4L2_CID_CONTRAST, 0, 255, 1, 128); |
b44b2e06 | 2868 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 | 2869 | V4L2_CID_SATURATION, 0, 255, 1, 128); |
b44b2e06 | 2870 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 HV |
2871 | V4L2_CID_HUE, 0, 128, 1, 0); |
2872 | ||
2873 | /* private controls */ | |
2874 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, | |
d42010a1 LPC |
2875 | V4L2_CID_DV_RX_POWER_PRESENT, 0, |
2876 | (1 << state->info->num_dv_ports) - 1, 0, 0); | |
54450f59 | 2877 | state->rgb_quantization_range_ctrl = |
b44b2e06 | 2878 | v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, |
54450f59 HV |
2879 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, |
2880 | 0, V4L2_DV_RGB_RANGE_AUTO); | |
54450f59 HV |
2881 | |
2882 | /* custom controls */ | |
b44b2e06 | 2883 | if (adv76xx_has_afe(state)) |
d42010a1 LPC |
2884 | state->analog_sampling_phase_ctrl = |
2885 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); | |
54450f59 | 2886 | state->free_run_color_manual_ctrl = |
b44b2e06 | 2887 | v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); |
54450f59 | 2888 | state->free_run_color_ctrl = |
b44b2e06 | 2889 | v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); |
54450f59 HV |
2890 | |
2891 | sd->ctrl_handler = hdl; | |
2892 | if (hdl->error) { | |
2893 | err = hdl->error; | |
2894 | goto err_hdl; | |
2895 | } | |
8c0eadb8 HV |
2896 | state->detect_tx_5v_ctrl->is_private = true; |
2897 | state->rgb_quantization_range_ctrl->is_private = true; | |
b44b2e06 | 2898 | if (adv76xx_has_afe(state)) |
d42010a1 | 2899 | state->analog_sampling_phase_ctrl->is_private = true; |
8c0eadb8 HV |
2900 | state->free_run_color_manual_ctrl->is_private = true; |
2901 | state->free_run_color_ctrl->is_private = true; | |
2902 | ||
b44b2e06 | 2903 | if (adv76xx_s_detect_tx_5v_ctrl(sd)) { |
54450f59 HV |
2904 | err = -ENODEV; |
2905 | goto err_hdl; | |
2906 | } | |
2907 | ||
b44b2e06 | 2908 | for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { |
05cacb17 LP |
2909 | if (!(BIT(i) & state->info->page_mask)) |
2910 | continue; | |
54450f59 | 2911 | |
05cacb17 | 2912 | state->i2c_clients[i] = |
b44b2e06 | 2913 | adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i], |
05cacb17 LP |
2914 | 0xf2 + i); |
2915 | if (state->i2c_clients[i] == NULL) { | |
d42010a1 | 2916 | err = -ENOMEM; |
05cacb17 | 2917 | v4l2_err(sd, "failed to create i2c client %u\n", i); |
d42010a1 LPC |
2918 | goto err_i2c; |
2919 | } | |
2920 | } | |
05cacb17 | 2921 | |
54450f59 HV |
2922 | /* work queues */ |
2923 | state->work_queues = create_singlethread_workqueue(client->name); | |
2924 | if (!state->work_queues) { | |
2925 | v4l2_err(sd, "Could not create work queue\n"); | |
2926 | err = -ENOMEM; | |
2927 | goto err_i2c; | |
2928 | } | |
2929 | ||
2930 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, | |
b44b2e06 | 2931 | adv76xx_delayed_work_enable_hotplug); |
54450f59 | 2932 | |
c784b1e2 LP |
2933 | state->source_pad = state->info->num_dv_ports |
2934 | + (state->info->has_afe ? 2 : 0); | |
2935 | for (i = 0; i < state->source_pad; ++i) | |
2936 | state->pads[i].flags = MEDIA_PAD_FL_SINK; | |
2937 | state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; | |
2938 | ||
2939 | err = media_entity_init(&sd->entity, state->source_pad + 1, | |
2940 | state->pads, 0); | |
54450f59 HV |
2941 | if (err) |
2942 | goto err_work_queues; | |
2943 | ||
b44b2e06 | 2944 | err = adv76xx_core_init(sd); |
54450f59 HV |
2945 | if (err) |
2946 | goto err_entity; | |
2947 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, | |
2948 | client->addr << 1, client->adapter->name); | |
bedc3939 LPC |
2949 | |
2950 | err = v4l2_async_register_subdev(sd); | |
2951 | if (err) | |
2952 | goto err_entity; | |
2953 | ||
54450f59 HV |
2954 | return 0; |
2955 | ||
2956 | err_entity: | |
2957 | media_entity_cleanup(&sd->entity); | |
2958 | err_work_queues: | |
2959 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2960 | destroy_workqueue(state->work_queues); | |
2961 | err_i2c: | |
b44b2e06 | 2962 | adv76xx_unregister_clients(state); |
54450f59 HV |
2963 | err_hdl: |
2964 | v4l2_ctrl_handler_free(hdl); | |
54450f59 HV |
2965 | return err; |
2966 | } | |
2967 | ||
2968 | /* ----------------------------------------------------------------------- */ | |
2969 | ||
b44b2e06 | 2970 | static int adv76xx_remove(struct i2c_client *client) |
54450f59 HV |
2971 | { |
2972 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
b44b2e06 | 2973 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
2974 | |
2975 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2976 | destroy_workqueue(state->work_queues); | |
bedc3939 | 2977 | v4l2_async_unregister_subdev(sd); |
54450f59 | 2978 | media_entity_cleanup(&sd->entity); |
b44b2e06 | 2979 | adv76xx_unregister_clients(to_state(sd)); |
54450f59 | 2980 | v4l2_ctrl_handler_free(sd->ctrl_handler); |
54450f59 HV |
2981 | return 0; |
2982 | } | |
2983 | ||
2984 | /* ----------------------------------------------------------------------- */ | |
2985 | ||
b44b2e06 | 2986 | static struct i2c_driver adv76xx_driver = { |
54450f59 HV |
2987 | .driver = { |
2988 | .owner = THIS_MODULE, | |
2989 | .name = "adv7604", | |
b44b2e06 | 2990 | .of_match_table = of_match_ptr(adv76xx_of_id), |
54450f59 | 2991 | }, |
b44b2e06 PA |
2992 | .probe = adv76xx_probe, |
2993 | .remove = adv76xx_remove, | |
2994 | .id_table = adv76xx_i2c_id, | |
54450f59 HV |
2995 | }; |
2996 | ||
b44b2e06 | 2997 | module_i2c_driver(adv76xx_driver); |