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[mirror_ubuntu-eoan-kernel.git] / drivers / media / i2c / adv7604.c
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54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
41#include <media/v4l2-chip-ident.h>
42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
6b0d5d34 56#define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
54450f59
HV		 57
58/*
59 **********************************************************************
60 *
61 * Arrays with configuration parameters for the ADV7604
62 *
63 **********************************************************************
64 */
65struct adv7604_state {
66 struct adv7604_platform_data pdata;
67 struct v4l2_subdev sd;
68 struct media_pad pad;
69 struct v4l2_ctrl_handler hdl;
6b0d5d34 70 enum adv7604_mode mode;
54450f59
HV		 71 struct v4l2_dv_timings timings;
72 u8 edid[256];
73 unsigned edid_blocks;
74 struct v4l2_fract aspect_ratio;
75 u32 rgb_quantization_range;
76 struct workqueue_struct *work_queues;
77 struct delayed_work delayed_work_enable_hotplug;
78 bool connector_hdmi;
cf9afb1d 79 bool restart_stdi_once;
54450f59
HV		 80
81 /* i2c clients */
82 struct i2c_client *i2c_avlink;
83 struct i2c_client *i2c_cec;
84 struct i2c_client *i2c_infoframe;
85 struct i2c_client *i2c_esdp;
86 struct i2c_client *i2c_dpp;
87 struct i2c_client *i2c_afe;
88 struct i2c_client *i2c_repeater;
89 struct i2c_client *i2c_edid;
90 struct i2c_client *i2c_hdmi;
91 struct i2c_client *i2c_test;
92 struct i2c_client *i2c_cp;
93 struct i2c_client *i2c_vdp;
94
95 /* controls */
96 struct v4l2_ctrl *detect_tx_5v_ctrl;
97 struct v4l2_ctrl *analog_sampling_phase_ctrl;
98 struct v4l2_ctrl *free_run_color_manual_ctrl;
99 struct v4l2_ctrl *free_run_color_ctrl;
100 struct v4l2_ctrl *rgb_quantization_range_ctrl;
101};
102
103/* Supported CEA and DMT timings */
104static const struct v4l2_dv_timings adv7604_timings[] = {
105 V4L2_DV_BT_CEA_720X480P59_94,
106 V4L2_DV_BT_CEA_720X576P50,
107 V4L2_DV_BT_CEA_1280X720P24,
108 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 109 V4L2_DV_BT_CEA_1280X720P50,
110 V4L2_DV_BT_CEA_1280X720P60,
111 V4L2_DV_BT_CEA_1920X1080P24,
112 V4L2_DV_BT_CEA_1920X1080P25,
113 V4L2_DV_BT_CEA_1920X1080P30,
114 V4L2_DV_BT_CEA_1920X1080P50,
115 V4L2_DV_BT_CEA_1920X1080P60,
116
ccbd5bc4 117 /* sorted by DMT ID */
54450f59
HV		 118 V4L2_DV_BT_DMT_640X350P85,
119 V4L2_DV_BT_DMT_640X400P85,
120 V4L2_DV_BT_DMT_720X400P85,
121 V4L2_DV_BT_DMT_640X480P60,
122 V4L2_DV_BT_DMT_640X480P72,
123 V4L2_DV_BT_DMT_640X480P75,
124 V4L2_DV_BT_DMT_640X480P85,
125 V4L2_DV_BT_DMT_800X600P56,
126 V4L2_DV_BT_DMT_800X600P60,
127 V4L2_DV_BT_DMT_800X600P72,
128 V4L2_DV_BT_DMT_800X600P75,
129 V4L2_DV_BT_DMT_800X600P85,
130 V4L2_DV_BT_DMT_848X480P60,
131 V4L2_DV_BT_DMT_1024X768P60,
132 V4L2_DV_BT_DMT_1024X768P70,
133 V4L2_DV_BT_DMT_1024X768P75,
134 V4L2_DV_BT_DMT_1024X768P85,
135 V4L2_DV_BT_DMT_1152X864P75,
136 V4L2_DV_BT_DMT_1280X768P60_RB,
137 V4L2_DV_BT_DMT_1280X768P60,
138 V4L2_DV_BT_DMT_1280X768P75,
139 V4L2_DV_BT_DMT_1280X768P85,
140 V4L2_DV_BT_DMT_1280X800P60_RB,
141 V4L2_DV_BT_DMT_1280X800P60,
142 V4L2_DV_BT_DMT_1280X800P75,
143 V4L2_DV_BT_DMT_1280X800P85,
144 V4L2_DV_BT_DMT_1280X960P60,
145 V4L2_DV_BT_DMT_1280X960P85,
146 V4L2_DV_BT_DMT_1280X1024P60,
147 V4L2_DV_BT_DMT_1280X1024P75,
148 V4L2_DV_BT_DMT_1280X1024P85,
149 V4L2_DV_BT_DMT_1360X768P60,
150 V4L2_DV_BT_DMT_1400X1050P60_RB,
151 V4L2_DV_BT_DMT_1400X1050P60,
152 V4L2_DV_BT_DMT_1400X1050P75,
153 V4L2_DV_BT_DMT_1400X1050P85,
154 V4L2_DV_BT_DMT_1440X900P60_RB,
155 V4L2_DV_BT_DMT_1440X900P60,
156 V4L2_DV_BT_DMT_1600X1200P60,
157 V4L2_DV_BT_DMT_1680X1050P60_RB,
158 V4L2_DV_BT_DMT_1680X1050P60,
159 V4L2_DV_BT_DMT_1792X1344P60,
160 V4L2_DV_BT_DMT_1856X1392P60,
161 V4L2_DV_BT_DMT_1920X1200P60_RB,
162 V4L2_DV_BT_DMT_1366X768P60,
163 V4L2_DV_BT_DMT_1920X1080P60,
164 { },
165};
166
ccbd5bc4
HV		 167struct adv7604_video_standards {
168 struct v4l2_dv_timings timings;
169 u8 vid_std;
170 u8 v_freq;
171};
172
173/* sorted by number of lines */
174static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
175 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
176 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
177 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
178 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
179 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
180 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
181 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
182 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
183 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
184 /* TODO add 1920x1080P60_RB (CVT timing) */
185 { },
186};
187
188/* sorted by number of lines */
189static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
190 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
204 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
205 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
206 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
207 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
208 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
209 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
210 /* TODO add 1600X1200P60_RB (not a DMT timing) */
211 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
212 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
213 { },
214};
215
216/* sorted by number of lines */
217static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
218 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
219 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
220 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
221 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
222 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
223 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
224 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
225 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
226 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
227 { },
228};
229
230/* sorted by number of lines */
231static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
232 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
233 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
234 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
236 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
237 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
241 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
242 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
245 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
246 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
247 { },
248};
249
54450f59
HV		 250/* ----------------------------------------------------------------------- */
251
252static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
253{
254 return container_of(sd, struct adv7604_state, sd);
255}
256
257static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
258{
259 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
260}
261
262static inline unsigned hblanking(const struct v4l2_bt_timings *t)
263{
264 return t->hfrontporch + t->hsync + t->hbackporch;
265}
266
267static inline unsigned htotal(const struct v4l2_bt_timings *t)
268{
269 return t->width + t->hfrontporch + t->hsync + t->hbackporch;
270}
271
272static inline unsigned vblanking(const struct v4l2_bt_timings *t)
273{
274 return t->vfrontporch + t->vsync + t->vbackporch;
275}
276
277static inline unsigned vtotal(const struct v4l2_bt_timings *t)
278{
279 return t->height + t->vfrontporch + t->vsync + t->vbackporch;
280}
281
282/* ----------------------------------------------------------------------- */
283
284static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
285 u8 command, bool check)
286{
287 union i2c_smbus_data data;
288
289 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
290 I2C_SMBUS_READ, command,
291 I2C_SMBUS_BYTE_DATA, &data))
292 return data.byte;
293 if (check)
294 v4l_err(client, "error reading %02x, %02x\n",
295 client->addr, command);
296 return -EIO;
297}
298
299static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
300{
301 return adv_smbus_read_byte_data_check(client, command, true);
302}
303
304static s32 adv_smbus_write_byte_data(struct i2c_client *client,
305 u8 command, u8 value)
306{
307 union i2c_smbus_data data;
308 int err;
309 int i;
310
311 data.byte = value;
312 for (i = 0; i < 3; i++) {
313 err = i2c_smbus_xfer(client->adapter, client->addr,
314 client->flags,
315 I2C_SMBUS_WRITE, command,
316 I2C_SMBUS_BYTE_DATA, &data);
317 if (!err)
318 break;
319 }
320 if (err < 0)
321 v4l_err(client, "error writing %02x, %02x, %02x\n",
322 client->addr, command, value);
323 return err;
324}
325
326static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
327 u8 command, unsigned length, const u8 *values)
328{
329 union i2c_smbus_data data;
330
331 if (length > I2C_SMBUS_BLOCK_MAX)
332 length = I2C_SMBUS_BLOCK_MAX;
333 data.block[0] = length;
334 memcpy(data.block + 1, values, length);
335 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
336 I2C_SMBUS_WRITE, command,
337 I2C_SMBUS_I2C_BLOCK_DATA, &data);
338}
339
340/* ----------------------------------------------------------------------- */
341
342static inline int io_read(struct v4l2_subdev *sd, u8 reg)
343{
344 struct i2c_client *client = v4l2_get_subdevdata(sd);
345
346 return adv_smbus_read_byte_data(client, reg);
347}
348
349static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
350{
351 struct i2c_client *client = v4l2_get_subdevdata(sd);
352
353 return adv_smbus_write_byte_data(client, reg, val);
354}
355
356static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
357{
358 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
359}
360
361static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
362{
363 struct adv7604_state *state = to_state(sd);
364
365 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
366}
367
368static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
369{
370 struct adv7604_state *state = to_state(sd);
371
372 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
373}
374
375static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
376{
377 struct adv7604_state *state = to_state(sd);
378
379 return adv_smbus_read_byte_data(state->i2c_cec, reg);
380}
381
382static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
383{
384 struct adv7604_state *state = to_state(sd);
385
386 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
387}
388
389static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
390{
391 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
392}
393
394static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
395{
396 struct adv7604_state *state = to_state(sd);
397
398 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
399}
400
401static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
402{
403 struct adv7604_state *state = to_state(sd);
404
405 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
406}
407
408static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
409{
410 struct adv7604_state *state = to_state(sd);
411
412 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
413}
414
415static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
416{
417 struct adv7604_state *state = to_state(sd);
418
419 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
420}
421
422static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
423{
424 struct adv7604_state *state = to_state(sd);
425
426 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
427}
428
429static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
430{
431 struct adv7604_state *state = to_state(sd);
432
433 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
434}
435
436static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
437{
438 struct adv7604_state *state = to_state(sd);
439
440 return adv_smbus_read_byte_data(state->i2c_afe, reg);
441}
442
443static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
444{
445 struct adv7604_state *state = to_state(sd);
446
447 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
448}
449
450static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
451{
452 struct adv7604_state *state = to_state(sd);
453
454 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
455}
456
457static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
458{
459 struct adv7604_state *state = to_state(sd);
460
461 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
462}
463
464static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
465{
466 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
467}
468
469static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
470{
471 struct adv7604_state *state = to_state(sd);
472
473 return adv_smbus_read_byte_data(state->i2c_edid, reg);
474}
475
476static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
477{
478 struct adv7604_state *state = to_state(sd);
479
480 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
481}
482
483static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
484{
485 struct adv7604_state *state = to_state(sd);
486 struct i2c_client *client = state->i2c_edid;
487 u8 msgbuf0[1] = { 0 };
488 u8 msgbuf1[256];
09f29673
S		 489 struct i2c_msg msg[2] = {
490 {
491 .addr = client->addr,
492 .len = 1,
493 .buf = msgbuf0
494 },
495 {
496 .addr = client->addr,
497 .flags = I2C_M_RD,
498 .len = len,
499 .buf = msgbuf1
500 },
501 };
54450f59
HV		 502
503 if (i2c_transfer(client->adapter, msg, 2) < 0)
504 return -EIO;
505 memcpy(val, msgbuf1, len);
506 return 0;
507}
508
509static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
510{
511 struct delayed_work *dwork = to_delayed_work(work);
512 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
513 delayed_work_enable_hotplug);
514 struct v4l2_subdev *sd = &state->sd;
515
516 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
517
518 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
519}
520
521static inline int edid_write_block(struct v4l2_subdev *sd,
522 unsigned len, const u8 *val)
523{
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
525 struct adv7604_state *state = to_state(sd);
526 int err = 0;
527 int i;
528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530
531 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
532
533 /* Disables I2C access to internal EDID ram from DDC port */
534 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
535
536 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
537 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
538 I2C_SMBUS_BLOCK_MAX, val + i);
539 if (err)
540 return err;
541
542 /* adv7604 calculates the checksums and enables I2C access to internal
543 EDID ram from DDC port. */
544 rep_write_and_or(sd, 0x77, 0xf0, 0x1);
545
546 for (i = 0; i < 1000; i++) {
547 if (rep_read(sd, 0x7d) & 1)
548 break;
549 mdelay(1);
550 }
551 if (i == 1000) {
552 v4l_err(client, "error enabling edid\n");
553 return -EIO;
554 }
555
556 /* enable hotplug after 100 ms */
557 queue_delayed_work(state->work_queues,
558 &state->delayed_work_enable_hotplug, HZ / 10);
559 return 0;
560}
561
562static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
563{
564 struct adv7604_state *state = to_state(sd);
565
566 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
567}
568
569static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
570{
571 struct adv7604_state *state = to_state(sd);
572
573 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
574}
575
576static inline int test_read(struct v4l2_subdev *sd, u8 reg)
577{
578 struct adv7604_state *state = to_state(sd);
579
580 return adv_smbus_read_byte_data(state->i2c_test, reg);
581}
582
583static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584{
585 struct adv7604_state *state = to_state(sd);
586
587 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
588}
589
590static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
591{
592 struct adv7604_state *state = to_state(sd);
593
594 return adv_smbus_read_byte_data(state->i2c_cp, reg);
595}
596
597static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598{
599 struct adv7604_state *state = to_state(sd);
600
601 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
602}
603
604static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
605{
606 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
607}
608
609static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
610{
611 struct adv7604_state *state = to_state(sd);
612
613 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
614}
615
616static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
617{
618 struct adv7604_state *state = to_state(sd);
619
620 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
621}
622
623/* ----------------------------------------------------------------------- */
624
625#ifdef CONFIG_VIDEO_ADV_DEBUG
626static void adv7604_inv_register(struct v4l2_subdev *sd)
627{
628 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
629 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
630 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
631 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
632 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
633 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
634 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
635 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
636 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
637 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
638 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
639 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
640 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
641}
642
643static int adv7604_g_register(struct v4l2_subdev *sd,
644 struct v4l2_dbg_register *reg)
645{
646 struct i2c_client *client = v4l2_get_subdevdata(sd);
647
648 if (!v4l2_chip_match_i2c_client(client, &reg->match))
649 return -EINVAL;
650 if (!capable(CAP_SYS_ADMIN))
651 return -EPERM;
652 reg->size = 1;
653 switch (reg->reg >> 8) {
654 case 0:
655 reg->val = io_read(sd, reg->reg & 0xff);
656 break;
657 case 1:
658 reg->val = avlink_read(sd, reg->reg & 0xff);
659 break;
660 case 2:
661 reg->val = cec_read(sd, reg->reg & 0xff);
662 break;
663 case 3:
664 reg->val = infoframe_read(sd, reg->reg & 0xff);
665 break;
666 case 4:
667 reg->val = esdp_read(sd, reg->reg & 0xff);
668 break;
669 case 5:
670 reg->val = dpp_read(sd, reg->reg & 0xff);
671 break;
672 case 6:
673 reg->val = afe_read(sd, reg->reg & 0xff);
674 break;
675 case 7:
676 reg->val = rep_read(sd, reg->reg & 0xff);
677 break;
678 case 8:
679 reg->val = edid_read(sd, reg->reg & 0xff);
680 break;
681 case 9:
682 reg->val = hdmi_read(sd, reg->reg & 0xff);
683 break;
684 case 0xa:
685 reg->val = test_read(sd, reg->reg & 0xff);
686 break;
687 case 0xb:
688 reg->val = cp_read(sd, reg->reg & 0xff);
689 break;
690 case 0xc:
691 reg->val = vdp_read(sd, reg->reg & 0xff);
692 break;
693 default:
694 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
695 adv7604_inv_register(sd);
696 break;
697 }
698 return 0;
699}
700
701static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 702 const struct v4l2_dbg_register *reg)
54450f59
HV		 703{
704 struct i2c_client *client = v4l2_get_subdevdata(sd);
705
706 if (!v4l2_chip_match_i2c_client(client, &reg->match))
707 return -EINVAL;
708 if (!capable(CAP_SYS_ADMIN))
709 return -EPERM;
710 switch (reg->reg >> 8) {
711 case 0:
712 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
713 break;
714 case 1:
715 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
716 break;
717 case 2:
718 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
719 break;
720 case 3:
721 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
722 break;
723 case 4:
724 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
725 break;
726 case 5:
727 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
728 break;
729 case 6:
730 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
731 break;
732 case 7:
733 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
734 break;
735 case 8:
736 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
737 break;
738 case 9:
739 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
740 break;
741 case 0xa:
742 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
743 break;
744 case 0xb:
745 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
746 break;
747 case 0xc:
748 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
749 break;
750 default:
751 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
752 adv7604_inv_register(sd);
753 break;
754 }
755 return 0;
756}
757#endif
758
759static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
760{
761 struct adv7604_state *state = to_state(sd);
762
763 /* port A only */
764 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
765 ((io_read(sd, 0x6f) & 0x10) >> 4));
766}
767
ccbd5bc4
HV		 768static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
769 u8 prim_mode,
770 const struct adv7604_video_standards *predef_vid_timings,
771 const struct v4l2_dv_timings *timings)
772{
773 struct adv7604_state *state = to_state(sd);
774 int i;
775
776 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
777 if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings,
778 DIGITAL_INPUT ? 250000 : 1000000))
779 continue;
780 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
781 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
782 prim_mode); /* v_freq and prim mode */
783 return 0;
784 }
785
786 return -1;
787}
788
789static int configure_predefined_video_timings(struct v4l2_subdev *sd,
790 struct v4l2_dv_timings *timings)
54450f59 791{
ccbd5bc4
HV		 792 struct adv7604_state *state = to_state(sd);
793 int err;
794
795 v4l2_dbg(1, debug, sd, "%s", __func__);
796
797 /* reset to default values */
798 io_write(sd, 0x16, 0x43);
799 io_write(sd, 0x17, 0x5a);
800 /* disable embedded syncs for auto graphics mode */
801 cp_write_and_or(sd, 0x81, 0xef, 0x00);
802 cp_write(sd, 0x8f, 0x00);
803 cp_write(sd, 0x90, 0x00);
804 cp_write(sd, 0xa2, 0x00);
805 cp_write(sd, 0xa3, 0x00);
806 cp_write(sd, 0xa4, 0x00);
807 cp_write(sd, 0xa5, 0x00);
808 cp_write(sd, 0xa6, 0x00);
809 cp_write(sd, 0xa7, 0x00);
810 cp_write(sd, 0xab, 0x00);
811 cp_write(sd, 0xac, 0x00);
812
813 switch (state->mode) {
814 case ADV7604_MODE_COMP:
815 case ADV7604_MODE_GR:
816 err = find_and_set_predefined_video_timings(sd,
817 0x01, adv7604_prim_mode_comp, timings);
818 if (err)
819 err = find_and_set_predefined_video_timings(sd,
820 0x02, adv7604_prim_mode_gr, timings);
821 break;
822 case ADV7604_MODE_HDMI:
823 err = find_and_set_predefined_video_timings(sd,
824 0x05, adv7604_prim_mode_hdmi_comp, timings);
825 if (err)
826 err = find_and_set_predefined_video_timings(sd,
827 0x06, adv7604_prim_mode_hdmi_gr, timings);
828 break;
829 default:
830 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
831 __func__, state->mode);
832 err = -1;
833 break;
834 }
835
836
837 return err;
838}
839
840static void configure_custom_video_timings(struct v4l2_subdev *sd,
841 const struct v4l2_bt_timings *bt)
842{
843 struct adv7604_state *state = to_state(sd);
54450f59 844 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 845 u32 width = htotal(bt);
846 u32 height = vtotal(bt);
847 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
848 u16 cp_start_eav = width - bt->hfrontporch;
849 u16 cp_start_vbi = height - bt->vfrontporch;
850 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
851 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
852 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
853 const u8 pll[2] = {
854 0xc0 | ((width >> 8) & 0x1f),
855 width & 0xff
856 };
54450f59
HV		 857
858 v4l2_dbg(2, debug, sd, "%s\n", __func__);
859
ccbd5bc4
HV		 860 switch (state->mode) {
861 case ADV7604_MODE_COMP:
862 case ADV7604_MODE_GR:
863 /* auto graphics */
864 io_write(sd, 0x00, 0x07); /* video std */
865 io_write(sd, 0x01, 0x02); /* prim mode */
866 /* enable embedded syncs for auto graphics mode */
867 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 868
ccbd5bc4 869 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 870 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
871 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
872 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
873 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
ccbd5bc4 874 break;
54450f59
HV		 875 }
876
877 /* active video - horizontal timing */
54450f59 878 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4
HV		 879 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
880 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 881 cp_write(sd, 0xa4, cp_start_eav & 0xff);
882
883 /* active video - vertical timing */
54450f59 884 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4
HV		 885 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
886 ((cp_end_vbi >> 8) & 0xf));
54450f59 887 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
ccbd5bc4
HV		 888 break;
889 case ADV7604_MODE_HDMI:
890 /* set default prim_mode/vid_std for HDMI
891 accoring to [REF_03, c. 4.2] */
892 io_write(sd, 0x00, 0x02); /* video std */
893 io_write(sd, 0x01, 0x06); /* prim mode */
894 break;
895 default:
896 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
897 __func__, state->mode);
898 break;
54450f59 899 }
54450f59 900
ccbd5bc4
HV		 901 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
902 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
903 cp_write(sd, 0xab, (height >> 4) & 0xff);
904 cp_write(sd, 0xac, (height & 0x0f) << 4);
905}
54450f59
HV		 906
907static void set_rgb_quantization_range(struct v4l2_subdev *sd)
908{
909 struct adv7604_state *state = to_state(sd);
910
911 switch (state->rgb_quantization_range) {
912 case V4L2_DV_RGB_RANGE_AUTO:
913 /* automatic */
6b0d5d34 914 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
54450f59
HV		 915 /* receiving DVI-D signal */
916
917 /* ADV7604 selects RGB limited range regardless of
918 input format (CE/IT) in automatic mode */
919 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
920 /* RGB limited range (16-235) */
921 io_write_and_or(sd, 0x02, 0x0f, 0x00);
922
923 } else {
924 /* RGB full range (0-255) */
925 io_write_and_or(sd, 0x02, 0x0f, 0x10);
926 }
6b0d5d34
HV		 927 } else {
928 /* receiving HDMI or analog signal, set automode */
929 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
54450f59
HV		 930 }
931 break;
932 case V4L2_DV_RGB_RANGE_LIMITED:
933 /* RGB limited range (16-235) */
934 io_write_and_or(sd, 0x02, 0x0f, 0x00);
935 break;
936 case V4L2_DV_RGB_RANGE_FULL:
937 /* RGB full range (0-255) */
938 io_write_and_or(sd, 0x02, 0x0f, 0x10);
939 break;
940 }
941}
942
943
944static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
945{
946 struct v4l2_subdev *sd = to_sd(ctrl);
947 struct adv7604_state *state = to_state(sd);
948
949 switch (ctrl->id) {
950 case V4L2_CID_BRIGHTNESS:
951 cp_write(sd, 0x3c, ctrl->val);
952 return 0;
953 case V4L2_CID_CONTRAST:
954 cp_write(sd, 0x3a, ctrl->val);
955 return 0;
956 case V4L2_CID_SATURATION:
957 cp_write(sd, 0x3b, ctrl->val);
958 return 0;
959 case V4L2_CID_HUE:
960 cp_write(sd, 0x3d, ctrl->val);
961 return 0;
962 case V4L2_CID_DV_RX_RGB_RANGE:
963 state->rgb_quantization_range = ctrl->val;
964 set_rgb_quantization_range(sd);
965 return 0;
966 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
967 /* Set the analog sampling phase. This is needed to find the
968 best sampling phase for analog video: an application or
969 driver has to try a number of phases and analyze the picture
970 quality before settling on the best performing phase. */
971 afe_write(sd, 0xc8, ctrl->val);
972 return 0;
973 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
974 /* Use the default blue color for free running mode,
975 or supply your own. */
976 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
977 return 0;
978 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
979 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
980 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
981 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
982 return 0;
983 }
984 return -EINVAL;
985}
986
987static int adv7604_g_chip_ident(struct v4l2_subdev *sd,
988 struct v4l2_dbg_chip_ident *chip)
989{
990 struct i2c_client *client = v4l2_get_subdevdata(sd);
991
992 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7604, 0);
993}
994
995/* ----------------------------------------------------------------------- */
996
997static inline bool no_power(struct v4l2_subdev *sd)
998{
999 /* Entire chip or CP powered off */
1000 return io_read(sd, 0x0c) & 0x24;
1001}
1002
1003static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1004{
1005 /* TODO port B, C and D */
1006 return !(io_read(sd, 0x6a) & 0x10);
1007}
1008
1009static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1010{
1011 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1012}
1013
1014static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1015{
1016 /* TODO channel 2 */
1017 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1018}
1019
1020static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1021{
1022 /* TODO channel 2 */
1023 return !(cp_read(sd, 0xb1) & 0x80);
1024}
1025
1026static inline bool no_signal(struct v4l2_subdev *sd)
1027{
1028 struct adv7604_state *state = to_state(sd);
1029 bool ret;
1030
1031 ret = no_power(sd);
1032
1033 ret |= no_lock_stdi(sd);
1034 ret |= no_lock_sspd(sd);
1035
1036 if (DIGITAL_INPUT) {
1037 ret |= no_lock_tmds(sd);
1038 ret |= no_signal_tmds(sd);
1039 }
1040
1041 return ret;
1042}
1043
1044static inline bool no_lock_cp(struct v4l2_subdev *sd)
1045{
1046 /* CP has detected a non standard number of lines on the incoming
1047 video compared to what it is configured to receive by s_dv_timings */
1048 return io_read(sd, 0x12) & 0x01;
1049}
1050
1051static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1052{
1053 struct adv7604_state *state = to_state(sd);
1054
1055 *status = 0;
1056 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1057 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1058 if (no_lock_cp(sd))
1059 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1060
1061 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1062
1063 return 0;
1064}
1065
1066/* ----------------------------------------------------------------------- */
1067
1068static void adv7604_print_timings(struct v4l2_subdev *sd,
1069 struct v4l2_dv_timings *timings, const char *txt, bool detailed)
1070{
1071 struct v4l2_bt_timings *bt = &timings->bt;
1072 u32 htot, vtot;
1073
1074 if (timings->type != V4L2_DV_BT_656_1120)
1075 return;
1076
1077 htot = htotal(bt);
1078 vtot = vtotal(bt);
1079
1080 v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
1081 txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
1082 (htot * vtot) > 0 ? ((u32)bt->pixelclock /
1083 (htot * vtot)) : 0,
1084 htot, vtot);
1085
1086 if (detailed) {
1087 v4l2_info(sd, " horizontal: fp = %d, %ssync = %d, bp = %d\n",
1088 bt->hfrontporch,
1089 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
1090 bt->hsync, bt->hbackporch);
1091 v4l2_info(sd, " vertical: fp = %d, %ssync = %d, bp = %d\n",
1092 bt->vfrontporch,
1093 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
1094 bt->vsync, bt->vbackporch);
1095 v4l2_info(sd, " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1096 bt->pixelclock, bt->flags, bt->standards);
1097 }
1098}
1099
1100struct stdi_readback {
1101 u16 bl, lcf, lcvs;
1102 u8 hs_pol, vs_pol;
1103 bool interlaced;
1104};
1105
1106static int stdi2dv_timings(struct v4l2_subdev *sd,
1107 struct stdi_readback *stdi,
1108 struct v4l2_dv_timings *timings)
1109{
1110 struct adv7604_state *state = to_state(sd);
1111 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1112 u32 pix_clk;
1113 int i;
1114
1115 for (i = 0; adv7604_timings[i].bt.height; i++) {
1116 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1117 continue;
1118 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1119 continue;
1120
1121 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1122
1123 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1124 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1125 *timings = adv7604_timings[i];
1126 return 0;
1127 }
1128 }
1129
1130 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1131 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1132 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1133 timings))
1134 return 0;
1135 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1136 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1137 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1138 state->aspect_ratio, timings))
1139 return 0;
1140
ccbd5bc4
HV		 1141 v4l2_dbg(2, debug, sd,
1142 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1143 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1144 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1145 return -1;
1146}
1147
1148static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1149{
1150 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1151 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1152 return -1;
1153 }
1154
1155 /* read STDI */
1156 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1157 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1158 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1159 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1160
1161 /* read SSPD */
1162 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1163 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1164 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1165 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1166 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1167 } else {
1168 stdi->hs_pol = 'x';
1169 stdi->vs_pol = 'x';
1170 }
1171
1172 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1173 v4l2_dbg(2, debug, sd,
1174 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1175 return -1;
1176 }
1177
1178 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1179 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1180 memset(stdi, 0, sizeof(struct stdi_readback));
1181 return -1;
1182 }
1183
1184 v4l2_dbg(2, debug, sd,
1185 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1186 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1187 stdi->hs_pol, stdi->vs_pol,
1188 stdi->interlaced ? "interlaced" : "progressive");
1189
1190 return 0;
1191}
1192
1193static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1194 struct v4l2_enum_dv_timings *timings)
1195{
1196 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1197 return -EINVAL;
1198 memset(timings->reserved, 0, sizeof(timings->reserved));
1199 timings->timings = adv7604_timings[timings->index];
1200 return 0;
1201}
1202
1203static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1204 struct v4l2_dv_timings_cap *cap)
1205{
1206 struct adv7604_state *state = to_state(sd);
1207
1208 cap->type = V4L2_DV_BT_656_1120;
1209 cap->bt.max_width = 1920;
1210 cap->bt.max_height = 1200;
1211 cap->bt.min_pixelclock = 27000000;
1212 if (DIGITAL_INPUT)
1213 cap->bt.max_pixelclock = 225000000;
1214 else
1215 cap->bt.max_pixelclock = 170000000;
1216 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1217 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1218 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1219 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1220 return 0;
1221}
1222
1223/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1224 if the format is listed in adv7604_timings[] */
1225static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1226 struct v4l2_dv_timings *timings)
1227{
1228 struct adv7604_state *state = to_state(sd);
1229 int i;
1230
1231 for (i = 0; adv7604_timings[i].bt.width; i++) {
1232 if (v4l_match_dv_timings(timings, &adv7604_timings[i],
1233 DIGITAL_INPUT ? 250000 : 1000000)) {
1234 *timings = adv7604_timings[i];
1235 break;
1236 }
1237 }
1238}
1239
1240static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1241 struct v4l2_dv_timings *timings)
1242{
1243 struct adv7604_state *state = to_state(sd);
1244 struct v4l2_bt_timings *bt = &timings->bt;
1245 struct stdi_readback stdi;
1246
1247 if (!timings)
1248 return -EINVAL;
1249
1250 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1251
1252 if (no_signal(sd)) {
1253 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1254 return -ENOLINK;
1255 }
1256
1257 /* read STDI */
1258 if (read_stdi(sd, &stdi)) {
1259 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1260 return -ENOLINK;
1261 }
1262 bt->interlaced = stdi.interlaced ?
1263 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1264
1265 if (DIGITAL_INPUT) {
1266 timings->type = V4L2_DV_BT_656_1120;
1267
1268 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1269 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1270 bt->pixelclock = (hdmi_read(sd, 0x06) * 1000000) +
1271 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1272 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1273 hdmi_read(sd, 0x21);
1274 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1275 hdmi_read(sd, 0x23);
1276 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1277 hdmi_read(sd, 0x25);
1278 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1279 hdmi_read(sd, 0x2b)) / 2;
1280 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1281 hdmi_read(sd, 0x2f)) / 2;
1282 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1283 hdmi_read(sd, 0x33)) / 2;
1284 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1285 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1286 if (bt->interlaced == V4L2_DV_INTERLACED) {
1287 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1288 hdmi_read(sd, 0x0c);
1289 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1290 hdmi_read(sd, 0x2d)) / 2;
1291 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1292 hdmi_read(sd, 0x31)) / 2;
1293 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1294 hdmi_read(sd, 0x35)) / 2;
1295 }
1296 adv7604_fill_optional_dv_timings_fields(sd, timings);
1297 } else {
1298 /* find format
80939647 1299 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1300 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1301 */
1302 if (!stdi2dv_timings(sd, &stdi, timings))
1303 goto found;
1304 stdi.lcvs += 1;
1305 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1306 if (!stdi2dv_timings(sd, &stdi, timings))
1307 goto found;
1308 stdi.lcvs -= 2;
1309 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1310 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1311 /*
1312 * The STDI block may measure wrong values, especially
1313 * for lcvs and lcf. If the driver can not find any
1314 * valid timing, the STDI block is restarted to measure
1315 * the video timings again. The function will return an
1316 * error, but the restart of STDI will generate a new
1317 * STDI interrupt and the format detection process will
1318 * restart.
1319 */
1320 if (state->restart_stdi_once) {
1321 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1322 /* TODO restart STDI for Sync Channel 2 */
1323 /* enter one-shot mode */
1324 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1325 /* trigger STDI restart */
1326 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1327 /* reset to continuous mode */
1328 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1329 state->restart_stdi_once = false;
1330 return -ENOLINK;
1331 }
54450f59
HV		 1332 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1333 return -ERANGE;
1334 }
cf9afb1d 1335 state->restart_stdi_once = true;
54450f59
HV		 1336 }
1337found:
1338
1339 if (no_signal(sd)) {
1340 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1341 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1342 return -ENOLINK;
1343 }
1344
1345 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1346 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1347 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1348 __func__, (u32)bt->pixelclock);
1349 return -ERANGE;
1350 }
1351
1352 if (debug > 1)
1353 adv7604_print_timings(sd, timings,
1354 "adv7604_query_dv_timings:", true);
1355
1356 return 0;
1357}
1358
1359static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1360 struct v4l2_dv_timings *timings)
1361{
1362 struct adv7604_state *state = to_state(sd);
1363 struct v4l2_bt_timings *bt;
ccbd5bc4 1364 int err;
54450f59
HV		 1365
1366 if (!timings)
1367 return -EINVAL;
1368
1369 bt = &timings->bt;
1370
1371 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1372 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1373 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1374 __func__, (u32)bt->pixelclock);
1375 return -ERANGE;
1376 }
ccbd5bc4 1377
54450f59
HV		 1378 adv7604_fill_optional_dv_timings_fields(sd, timings);
1379
1380 state->timings = *timings;
1381
ccbd5bc4
HV		 1382 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1383
1384 /* Use prim_mode and vid_std when available */
1385 err = configure_predefined_video_timings(sd, timings);
1386 if (err) {
1387 /* custom settings when the video format
1388 does not have prim_mode/vid_std */
1389 configure_custom_video_timings(sd, bt);
1390 }
54450f59
HV		 1391
1392 set_rgb_quantization_range(sd);
1393
1394
1395 if (debug > 1)
1396 adv7604_print_timings(sd, timings,
1397 "adv7604_s_dv_timings:", true);
1398 return 0;
1399}
1400
1401static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1402 struct v4l2_dv_timings *timings)
1403{
1404 struct adv7604_state *state = to_state(sd);
1405
1406 *timings = state->timings;
1407 return 0;
1408}
1409
6b0d5d34 1410static void enable_input(struct v4l2_subdev *sd)
54450f59 1411{
6b0d5d34
HV		 1412 struct adv7604_state *state = to_state(sd);
1413
1414 switch (state->mode) {
1415 case ADV7604_MODE_COMP:
1416 case ADV7604_MODE_GR:
54450f59
HV		 1417 /* enable */
1418 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1419 break;
6b0d5d34 1420 case ADV7604_MODE_HDMI:
54450f59
HV		 1421 /* enable */
1422 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1423 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1424 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1425 break;
1426 default:
6b0d5d34
HV		 1427 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1428 __func__, state->mode);
54450f59
HV		 1429 break;
1430 }
1431}
1432
1433static void disable_input(struct v4l2_subdev *sd)
1434{
1435 /* disable */
1436 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1437 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1438 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1439}
1440
6b0d5d34 1441static void select_input(struct v4l2_subdev *sd)
54450f59 1442{
6b0d5d34 1443 struct adv7604_state *state = to_state(sd);
54450f59 1444
6b0d5d34
HV		 1445 switch (state->mode) {
1446 case ADV7604_MODE_COMP:
1447 case ADV7604_MODE_GR:
54450f59
HV		 1448 /* reset ADI recommended settings for HDMI: */
1449 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1450 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1451 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1452 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1453 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1454 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1455 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1456 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1457 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1458 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1459 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1460 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1461
1462 afe_write(sd, 0x00, 0x08); /* power up ADC */
1463 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1464 afe_write(sd, 0xc8, 0x00); /* phase control */
1465
1466 /* set ADI recommended settings for digitizer */
1467 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1468 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1469 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1470 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1471 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1472 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1473 break;
1474
6b0d5d34 1475 case ADV7604_MODE_HDMI:
54450f59
HV		 1476 /* set ADI recommended settings for HDMI: */
1477 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1478 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1479 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1480 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1481 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1482 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1483 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1484 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1485 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1486 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1487 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1488 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1489
1490 afe_write(sd, 0x00, 0xff); /* power down ADC */
1491 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1492 afe_write(sd, 0xc8, 0x40); /* phase control */
1493
1494 /* reset ADI recommended settings for digitizer */
1495 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1496 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1497 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1498 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1499 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1500 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1501
1502 break;
1503 default:
6b0d5d34
HV		 1504 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1505 __func__, state->mode);
54450f59
HV		 1506 break;
1507 }
1508}
1509
1510static int adv7604_s_routing(struct v4l2_subdev *sd,
1511 u32 input, u32 output, u32 config)
1512{
1513 struct adv7604_state *state = to_state(sd);
1514
1515 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1516
6b0d5d34 1517 state->mode = input;
54450f59
HV		 1518
1519 disable_input(sd);
1520
6b0d5d34 1521 select_input(sd);
54450f59 1522
6b0d5d34 1523 enable_input(sd);
54450f59
HV		 1524
1525 return 0;
1526}
1527
1528static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1529 enum v4l2_mbus_pixelcode *code)
1530{
1531 if (index)
1532 return -EINVAL;
1533 /* Good enough for now */
1534 *code = V4L2_MBUS_FMT_FIXED;
1535 return 0;
1536}
1537
1538static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1539 struct v4l2_mbus_framefmt *fmt)
1540{
1541 struct adv7604_state *state = to_state(sd);
1542
1543 fmt->width = state->timings.bt.width;
1544 fmt->height = state->timings.bt.height;
1545 fmt->code = V4L2_MBUS_FMT_FIXED;
1546 fmt->field = V4L2_FIELD_NONE;
1547 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1548 fmt->colorspace = (state->timings.bt.height <= 576) ?
1549 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1550 }
1551 return 0;
1552}
1553
1554static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1555{
1556 struct adv7604_state *state = to_state(sd);
1557 u8 fmt_change, fmt_change_digital, tx_5v;
1558
1559 /* format change */
1560 fmt_change = io_read(sd, 0x43) & 0x98;
1561 if (fmt_change)
1562 io_write(sd, 0x44, fmt_change);
1563 fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1564 if (fmt_change_digital)
1565 io_write(sd, 0x6c, fmt_change_digital);
1566 if (fmt_change || fmt_change_digital) {
1567 v4l2_dbg(1, debug, sd,
1568 "%s: ADV7604_FMT_CHANGE, fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1569 __func__, fmt_change, fmt_change_digital);
1570 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1571 if (handled)
1572 *handled = true;
1573 }
1574 /* tx 5v detect */
1575 tx_5v = io_read(sd, 0x70) & 0x10;
1576 if (tx_5v) {
1577 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1578 io_write(sd, 0x71, tx_5v);
1579 adv7604_s_detect_tx_5v_ctrl(sd);
1580 if (handled)
1581 *handled = true;
1582 }
1583 return 0;
1584}
1585
1586static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1587{
1588 struct adv7604_state *state = to_state(sd);
1589
1590 if (edid->pad != 0)
1591 return -EINVAL;
1592 if (edid->blocks == 0)
1593 return -EINVAL;
1594 if (edid->start_block >= state->edid_blocks)
1595 return -EINVAL;
1596 if (edid->start_block + edid->blocks > state->edid_blocks)
1597 edid->blocks = state->edid_blocks - edid->start_block;
1598 if (!edid->edid)
1599 return -EINVAL;
1600 memcpy(edid->edid + edid->start_block * 128,
1601 state->edid + edid->start_block * 128,
1602 edid->blocks * 128);
1603 return 0;
1604}
1605
1606static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1607{
1608 struct adv7604_state *state = to_state(sd);
1609 int err;
1610
1611 if (edid->pad != 0)
1612 return -EINVAL;
1613 if (edid->start_block != 0)
1614 return -EINVAL;
1615 if (edid->blocks == 0) {
1616 /* Pull down the hotplug pin */
1617 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1618 /* Disables I2C access to internal EDID ram from DDC port */
1619 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1620 state->edid_blocks = 0;
1621 /* Fall back to a 16:9 aspect ratio */
1622 state->aspect_ratio.numerator = 16;
1623 state->aspect_ratio.denominator = 9;
1624 return 0;
1625 }
1626 if (edid->blocks > 2)
1627 return -E2BIG;
1628 if (!edid->edid)
1629 return -EINVAL;
1630 memcpy(state->edid, edid->edid, 128 * edid->blocks);
1631 state->edid_blocks = edid->blocks;
1632 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1633 edid->edid[0x16]);
1634 err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1635 if (err < 0)
1636 v4l2_err(sd, "error %d writing edid\n", err);
1637 return err;
1638}
1639
1640/*********** avi info frame CEA-861-E **************/
1641
1642static void print_avi_infoframe(struct v4l2_subdev *sd)
1643{
1644 int i;
1645 u8 buf[14];
1646 u8 avi_len;
1647 u8 avi_ver;
1648
1649 if (!(hdmi_read(sd, 0x05) & 0x80)) {
1650 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1651 return;
1652 }
1653 if (!(io_read(sd, 0x60) & 0x01)) {
1654 v4l2_info(sd, "AVI infoframe not received\n");
1655 return;
1656 }
1657
1658 if (io_read(sd, 0x83) & 0x01) {
1659 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1660 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1661 if (io_read(sd, 0x83) & 0x01) {
1662 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1663 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1664 }
1665 }
1666
1667 avi_len = infoframe_read(sd, 0xe2);
1668 avi_ver = infoframe_read(sd, 0xe1);
1669 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1670 avi_ver, avi_len);
1671
1672 if (avi_ver != 0x02)
1673 return;
1674
1675 for (i = 0; i < 14; i++)
1676 buf[i] = infoframe_read(sd, i);
1677
1678 v4l2_info(sd,
1679 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1680 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1681 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1682}
1683
1684static int adv7604_log_status(struct v4l2_subdev *sd)
1685{
1686 struct adv7604_state *state = to_state(sd);
1687 struct v4l2_dv_timings timings;
1688 struct stdi_readback stdi;
1689 u8 reg_io_0x02 = io_read(sd, 0x02);
1690
1691 char *csc_coeff_sel_rb[16] = {
1692 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1693 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1694 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1695 "reserved", "reserved", "reserved", "reserved", "manual"
1696 };
1697 char *input_color_space_txt[16] = {
1698 "RGB limited range (16-235)", "RGB full range (0-255)",
1699 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1700 "XvYCC Bt.601", "XvYCC Bt.709",
1701 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1702 "invalid", "invalid", "invalid", "invalid", "invalid",
1703 "invalid", "invalid", "automatic"
1704 };
1705 char *rgb_quantization_range_txt[] = {
1706 "Automatic",
1707 "RGB limited range (16-235)",
1708 "RGB full range (0-255)",
1709 };
1710
1711 v4l2_info(sd, "-----Chip status-----\n");
1712 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1713 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1714 "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1715 v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1716 (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1717 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1718 "enabled" : "disabled");
1719
1720 v4l2_info(sd, "-----Signal status-----\n");
1721 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1722 (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1723 v4l2_info(sd, "TMDS signal detected: %s\n",
1724 no_signal_tmds(sd) ? "false" : "true");
1725 v4l2_info(sd, "TMDS signal locked: %s\n",
1726 no_lock_tmds(sd) ? "false" : "true");
1727 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1728 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1729 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1730 v4l2_info(sd, "CP free run: %s\n",
1731 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1732 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1733 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1734 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1735
1736 v4l2_info(sd, "-----Video Timings-----\n");
1737 if (read_stdi(sd, &stdi))
1738 v4l2_info(sd, "STDI: not locked\n");
1739 else
1740 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1741 stdi.lcf, stdi.bl, stdi.lcvs,
1742 stdi.interlaced ? "interlaced" : "progressive",
1743 stdi.hs_pol, stdi.vs_pol);
1744 if (adv7604_query_dv_timings(sd, &timings))
1745 v4l2_info(sd, "No video detected\n");
1746 else
1747 adv7604_print_timings(sd, &timings, "Detected format:", true);
1748 adv7604_print_timings(sd, &state->timings, "Configured format:", true);
1749
1750 v4l2_info(sd, "-----Color space-----\n");
1751 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1752 rgb_quantization_range_txt[state->rgb_quantization_range]);
1753 v4l2_info(sd, "Input color space: %s\n",
1754 input_color_space_txt[reg_io_0x02 >> 4]);
1755 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1756 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1757 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1758 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1759 "enabled" : "disabled");
1760 v4l2_info(sd, "Color space conversion: %s\n",
1761 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1762
1763 /* Digital video */
1764 if (DIGITAL_INPUT) {
1765 v4l2_info(sd, "-----HDMI status-----\n");
1766 v4l2_info(sd, "HDCP encrypted content: %s\n",
1767 hdmi_read(sd, 0x05) & 0x40 ? "true" : "false");
1768
1769 print_avi_infoframe(sd);
1770 }
1771
1772 return 0;
1773}
1774
1775/* ----------------------------------------------------------------------- */
1776
1777static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1778 .s_ctrl = adv7604_s_ctrl,
1779};
1780
1781static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1782 .log_status = adv7604_log_status,
1783 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1784 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1785 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1786 .g_ctrl = v4l2_subdev_g_ctrl,
1787 .s_ctrl = v4l2_subdev_s_ctrl,
1788 .queryctrl = v4l2_subdev_queryctrl,
1789 .querymenu = v4l2_subdev_querymenu,
1790 .g_chip_ident = adv7604_g_chip_ident,
1791 .interrupt_service_routine = adv7604_isr,
1792#ifdef CONFIG_VIDEO_ADV_DEBUG
1793 .g_register = adv7604_g_register,
1794 .s_register = adv7604_s_register,
1795#endif
1796};
1797
1798static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1799 .s_routing = adv7604_s_routing,
1800 .g_input_status = adv7604_g_input_status,
1801 .s_dv_timings = adv7604_s_dv_timings,
1802 .g_dv_timings = adv7604_g_dv_timings,
1803 .query_dv_timings = adv7604_query_dv_timings,
1804 .enum_dv_timings = adv7604_enum_dv_timings,
1805 .dv_timings_cap = adv7604_dv_timings_cap,
1806 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1807 .g_mbus_fmt = adv7604_g_mbus_fmt,
1808 .try_mbus_fmt = adv7604_g_mbus_fmt,
1809 .s_mbus_fmt = adv7604_g_mbus_fmt,
1810};
1811
1812static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1813 .get_edid = adv7604_get_edid,
1814 .set_edid = adv7604_set_edid,
1815};
1816
1817static const struct v4l2_subdev_ops adv7604_ops = {
1818 .core = &adv7604_core_ops,
1819 .video = &adv7604_video_ops,
1820 .pad = &adv7604_pad_ops,
1821};
1822
1823/* -------------------------- custom ctrls ---------------------------------- */
1824
1825static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1826 .ops = &adv7604_ctrl_ops,
1827 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1828 .name = "Analog Sampling Phase",
1829 .type = V4L2_CTRL_TYPE_INTEGER,
1830 .min = 0,
1831 .max = 0x1f,
1832 .step = 1,
1833 .def = 0,
1834};
1835
1836static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1837 .ops = &adv7604_ctrl_ops,
1838 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1839 .name = "Free Running Color, Manual",
1840 .type = V4L2_CTRL_TYPE_BOOLEAN,
1841 .min = false,
1842 .max = true,
1843 .step = 1,
1844 .def = false,
1845};
1846
1847static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1848 .ops = &adv7604_ctrl_ops,
1849 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1850 .name = "Free Running Color",
1851 .type = V4L2_CTRL_TYPE_INTEGER,
1852 .min = 0x0,
1853 .max = 0xffffff,
1854 .step = 0x1,
1855 .def = 0x0,
1856};
1857
1858/* ----------------------------------------------------------------------- */
1859
1860static int adv7604_core_init(struct v4l2_subdev *sd)
1861{
1862 struct adv7604_state *state = to_state(sd);
1863 struct adv7604_platform_data *pdata = &state->pdata;
1864
1865 hdmi_write(sd, 0x48,
1866 (pdata->disable_pwrdnb ? 0x80 : 0) |
1867 (pdata->disable_cable_det_rst ? 0x40 : 0));
1868
1869 disable_input(sd);
1870
1871 /* power */
1872 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
1873 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
1874 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
1875
1876 /* video format */
1877 io_write_and_or(sd, 0x02, 0xf0,
1878 pdata->alt_gamma << 3 |
1879 pdata->op_656_range << 2 |
1880 pdata->rgb_out << 1 |
1881 pdata->alt_data_sat << 0);
1882 io_write(sd, 0x03, pdata->op_format_sel);
1883 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1884 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1885 pdata->insert_av_codes << 2 |
1886 pdata->replicate_av_codes << 1 |
1887 pdata->invert_cbcr << 0);
1888
1889 /* TODO from platform data */
1890 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
1891 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
1892 io_write(sd, 0x14, 0x7f); /* Drive strength adjusted to max */
1893 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1894 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1895 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 1896 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 1897 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 1898 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 1899 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1900 for digital formats */
1901
1902 /* TODO from platform data */
1903 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1904
1905 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1906 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1907
54450f59
HV		 1908 /* interrupts */
1909 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1910 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1911 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1912 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1913 io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1914
1915 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1916}
1917
1918static void adv7604_unregister_clients(struct adv7604_state *state)
1919{
1920 if (state->i2c_avlink)
1921 i2c_unregister_device(state->i2c_avlink);
1922 if (state->i2c_cec)
1923 i2c_unregister_device(state->i2c_cec);
1924 if (state->i2c_infoframe)
1925 i2c_unregister_device(state->i2c_infoframe);
1926 if (state->i2c_esdp)
1927 i2c_unregister_device(state->i2c_esdp);
1928 if (state->i2c_dpp)
1929 i2c_unregister_device(state->i2c_dpp);
1930 if (state->i2c_afe)
1931 i2c_unregister_device(state->i2c_afe);
1932 if (state->i2c_repeater)
1933 i2c_unregister_device(state->i2c_repeater);
1934 if (state->i2c_edid)
1935 i2c_unregister_device(state->i2c_edid);
1936 if (state->i2c_hdmi)
1937 i2c_unregister_device(state->i2c_hdmi);
1938 if (state->i2c_test)
1939 i2c_unregister_device(state->i2c_test);
1940 if (state->i2c_cp)
1941 i2c_unregister_device(state->i2c_cp);
1942 if (state->i2c_vdp)
1943 i2c_unregister_device(state->i2c_vdp);
1944}
1945
1946static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1947 u8 addr, u8 io_reg)
1948{
1949 struct i2c_client *client = v4l2_get_subdevdata(sd);
1950
1951 if (addr)
1952 io_write(sd, io_reg, addr << 1);
1953 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1954}
1955
1956static int adv7604_probe(struct i2c_client *client,
1957 const struct i2c_device_id *id)
1958{
1959 struct adv7604_state *state;
1960 struct adv7604_platform_data *pdata = client->dev.platform_data;
1961 struct v4l2_ctrl_handler *hdl;
1962 struct v4l2_subdev *sd;
1963 int err;
1964
1965 /* Check if the adapter supports the needed features */
1966 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1967 return -EIO;
1968 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1969 client->addr << 1);
1970
1971 state = kzalloc(sizeof(struct adv7604_state), GFP_KERNEL);
1972 if (!state) {
1973 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1974 return -ENOMEM;
1975 }
1976
1977 /* platform data */
1978 if (!pdata) {
1979 v4l_err(client, "No platform data!\n");
1980 err = -ENODEV;
1981 goto err_state;
1982 }
1983 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1984
1985 sd = &state->sd;
1986 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1987 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1988 state->connector_hdmi = pdata->connector_hdmi;
1989
1990 /* i2c access to adv7604? */
1991 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
1992 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
1993 client->addr << 1);
1994 err = -ENODEV;
1995 goto err_state;
1996 }
1997
1998 /* control handlers */
1999 hdl = &state->hdl;
2000 v4l2_ctrl_handler_init(hdl, 9);
2001
2002 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2003 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2004 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2005 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2006 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2007 V4L2_CID_SATURATION, 0, 255, 1, 128);
2008 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2009 V4L2_CID_HUE, 0, 128, 1, 0);
2010
2011 /* private controls */
2012 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2013 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2014 state->detect_tx_5v_ctrl->is_private = true;
2015 state->rgb_quantization_range_ctrl =
2016 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2017 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2018 0, V4L2_DV_RGB_RANGE_AUTO);
2019 state->rgb_quantization_range_ctrl->is_private = true;
2020
2021 /* custom controls */
2022 state->analog_sampling_phase_ctrl =
2023 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2024 state->analog_sampling_phase_ctrl->is_private = true;
2025 state->free_run_color_manual_ctrl =
2026 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2027 state->free_run_color_manual_ctrl->is_private = true;
2028 state->free_run_color_ctrl =
2029 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2030 state->free_run_color_ctrl->is_private = true;
2031
2032 sd->ctrl_handler = hdl;
2033 if (hdl->error) {
2034 err = hdl->error;
2035 goto err_hdl;
2036 }
2037 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2038 err = -ENODEV;
2039 goto err_hdl;
2040 }
2041
2042 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2043 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2044 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2045 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2046 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2047 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2048 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2049 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2050 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2051 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2052 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2053 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2054 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2055 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2056 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2057 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2058 err = -ENOMEM;
2059 v4l2_err(sd, "failed to create all i2c clients\n");
2060 goto err_i2c;
2061 }
cf9afb1d 2062 state->restart_stdi_once = true;
54450f59
HV		 2063
2064 /* work queues */
2065 state->work_queues = create_singlethread_workqueue(client->name);
2066 if (!state->work_queues) {
2067 v4l2_err(sd, "Could not create work queue\n");
2068 err = -ENOMEM;
2069 goto err_i2c;
2070 }
2071
2072 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2073 adv7604_delayed_work_enable_hotplug);
2074
2075 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2076 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2077 if (err)
2078 goto err_work_queues;
2079
2080 err = adv7604_core_init(sd);
2081 if (err)
2082 goto err_entity;
2083 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2084 client->addr << 1, client->adapter->name);
2085 return 0;
2086
2087err_entity:
2088 media_entity_cleanup(&sd->entity);
2089err_work_queues:
2090 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2091 destroy_workqueue(state->work_queues);
2092err_i2c:
2093 adv7604_unregister_clients(state);
2094err_hdl:
2095 v4l2_ctrl_handler_free(hdl);
2096err_state:
2097 kfree(state);
2098 return err;
2099}
2100
2101/* ----------------------------------------------------------------------- */
2102
2103static int adv7604_remove(struct i2c_client *client)
2104{
2105 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2106 struct adv7604_state *state = to_state(sd);
2107
2108 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2109 destroy_workqueue(state->work_queues);
2110 v4l2_device_unregister_subdev(sd);
2111 media_entity_cleanup(&sd->entity);
2112 adv7604_unregister_clients(to_state(sd));
2113 v4l2_ctrl_handler_free(sd->ctrl_handler);
2114 kfree(to_state(sd));
2115 return 0;
2116}
2117
2118/* ----------------------------------------------------------------------- */
2119
2120static struct i2c_device_id adv7604_id[] = {
2121 { "adv7604", 0 },
2122 { }
2123};
2124MODULE_DEVICE_TABLE(i2c, adv7604_id);
2125
2126static struct i2c_driver adv7604_driver = {
2127 .driver = {
2128 .owner = THIS_MODULE,
2129 .name = "adv7604",
2130 },
2131 .probe = adv7604_probe,
2132 .remove = adv7604_remove,
2133 .id_table = adv7604_id,
2134};
2135
2136module_i2c_driver(adv7604_driver);
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