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54450f59 HV |
1 | /* |
2 | * adv7604 - Analog Devices ADV7604 video decoder driver | |
3 | * | |
4 | * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. | |
5 | * | |
6 | * This program is free software; you may redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
17 | * SOFTWARE. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * References (c = chapter, p = page): | |
23 | * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, | |
24 | * Revision 2.5, June 2010 | |
25 | * REF_02 - Analog devices, Register map documentation, Documentation of | |
26 | * the register maps, Software manual, Rev. F, June 2010 | |
27 | * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 | |
28 | */ | |
29 | ||
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/i2c.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/videodev2.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/v4l2-dv-timings.h> | |
39 | #include <media/v4l2-device.h> | |
40 | #include <media/v4l2-ctrls.h> | |
25764158 | 41 | #include <media/v4l2-dv-timings.h> |
54450f59 HV |
42 | #include <media/adv7604.h> |
43 | ||
44 | static int debug; | |
45 | module_param(debug, int, 0644); | |
46 | MODULE_PARM_DESC(debug, "debug level (0-2)"); | |
47 | ||
48 | MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); | |
49 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); | |
50 | MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
53 | /* ADV7604 system clock frequency */ | |
54 | #define ADV7604_fsc (28636360) | |
55 | ||
54450f59 HV |
56 | /* |
57 | ********************************************************************** | |
58 | * | |
59 | * Arrays with configuration parameters for the ADV7604 | |
60 | * | |
61 | ********************************************************************** | |
62 | */ | |
63 | struct adv7604_state { | |
64 | struct adv7604_platform_data pdata; | |
65 | struct v4l2_subdev sd; | |
66 | struct media_pad pad; | |
67 | struct v4l2_ctrl_handler hdl; | |
4a31a93a | 68 | enum adv7604_input_port selected_input; |
54450f59 | 69 | struct v4l2_dv_timings timings; |
4a31a93a MR |
70 | struct { |
71 | u8 edid[256]; | |
72 | u32 present; | |
73 | unsigned blocks; | |
74 | } edid; | |
54450f59 HV |
75 | struct v4l2_fract aspect_ratio; |
76 | u32 rgb_quantization_range; | |
77 | struct workqueue_struct *work_queues; | |
78 | struct delayed_work delayed_work_enable_hotplug; | |
79 | bool connector_hdmi; | |
cf9afb1d | 80 | bool restart_stdi_once; |
25a64ac9 | 81 | u32 prev_input_status; |
54450f59 HV |
82 | |
83 | /* i2c clients */ | |
84 | struct i2c_client *i2c_avlink; | |
85 | struct i2c_client *i2c_cec; | |
86 | struct i2c_client *i2c_infoframe; | |
87 | struct i2c_client *i2c_esdp; | |
88 | struct i2c_client *i2c_dpp; | |
89 | struct i2c_client *i2c_afe; | |
90 | struct i2c_client *i2c_repeater; | |
91 | struct i2c_client *i2c_edid; | |
92 | struct i2c_client *i2c_hdmi; | |
93 | struct i2c_client *i2c_test; | |
94 | struct i2c_client *i2c_cp; | |
95 | struct i2c_client *i2c_vdp; | |
96 | ||
97 | /* controls */ | |
98 | struct v4l2_ctrl *detect_tx_5v_ctrl; | |
99 | struct v4l2_ctrl *analog_sampling_phase_ctrl; | |
100 | struct v4l2_ctrl *free_run_color_manual_ctrl; | |
101 | struct v4l2_ctrl *free_run_color_ctrl; | |
102 | struct v4l2_ctrl *rgb_quantization_range_ctrl; | |
103 | }; | |
104 | ||
105 | /* Supported CEA and DMT timings */ | |
106 | static const struct v4l2_dv_timings adv7604_timings[] = { | |
107 | V4L2_DV_BT_CEA_720X480P59_94, | |
108 | V4L2_DV_BT_CEA_720X576P50, | |
109 | V4L2_DV_BT_CEA_1280X720P24, | |
110 | V4L2_DV_BT_CEA_1280X720P25, | |
54450f59 HV |
111 | V4L2_DV_BT_CEA_1280X720P50, |
112 | V4L2_DV_BT_CEA_1280X720P60, | |
113 | V4L2_DV_BT_CEA_1920X1080P24, | |
114 | V4L2_DV_BT_CEA_1920X1080P25, | |
115 | V4L2_DV_BT_CEA_1920X1080P30, | |
116 | V4L2_DV_BT_CEA_1920X1080P50, | |
117 | V4L2_DV_BT_CEA_1920X1080P60, | |
118 | ||
ccbd5bc4 | 119 | /* sorted by DMT ID */ |
54450f59 HV |
120 | V4L2_DV_BT_DMT_640X350P85, |
121 | V4L2_DV_BT_DMT_640X400P85, | |
122 | V4L2_DV_BT_DMT_720X400P85, | |
123 | V4L2_DV_BT_DMT_640X480P60, | |
124 | V4L2_DV_BT_DMT_640X480P72, | |
125 | V4L2_DV_BT_DMT_640X480P75, | |
126 | V4L2_DV_BT_DMT_640X480P85, | |
127 | V4L2_DV_BT_DMT_800X600P56, | |
128 | V4L2_DV_BT_DMT_800X600P60, | |
129 | V4L2_DV_BT_DMT_800X600P72, | |
130 | V4L2_DV_BT_DMT_800X600P75, | |
131 | V4L2_DV_BT_DMT_800X600P85, | |
132 | V4L2_DV_BT_DMT_848X480P60, | |
133 | V4L2_DV_BT_DMT_1024X768P60, | |
134 | V4L2_DV_BT_DMT_1024X768P70, | |
135 | V4L2_DV_BT_DMT_1024X768P75, | |
136 | V4L2_DV_BT_DMT_1024X768P85, | |
137 | V4L2_DV_BT_DMT_1152X864P75, | |
138 | V4L2_DV_BT_DMT_1280X768P60_RB, | |
139 | V4L2_DV_BT_DMT_1280X768P60, | |
140 | V4L2_DV_BT_DMT_1280X768P75, | |
141 | V4L2_DV_BT_DMT_1280X768P85, | |
142 | V4L2_DV_BT_DMT_1280X800P60_RB, | |
143 | V4L2_DV_BT_DMT_1280X800P60, | |
144 | V4L2_DV_BT_DMT_1280X800P75, | |
145 | V4L2_DV_BT_DMT_1280X800P85, | |
146 | V4L2_DV_BT_DMT_1280X960P60, | |
147 | V4L2_DV_BT_DMT_1280X960P85, | |
148 | V4L2_DV_BT_DMT_1280X1024P60, | |
149 | V4L2_DV_BT_DMT_1280X1024P75, | |
150 | V4L2_DV_BT_DMT_1280X1024P85, | |
151 | V4L2_DV_BT_DMT_1360X768P60, | |
152 | V4L2_DV_BT_DMT_1400X1050P60_RB, | |
153 | V4L2_DV_BT_DMT_1400X1050P60, | |
154 | V4L2_DV_BT_DMT_1400X1050P75, | |
155 | V4L2_DV_BT_DMT_1400X1050P85, | |
156 | V4L2_DV_BT_DMT_1440X900P60_RB, | |
157 | V4L2_DV_BT_DMT_1440X900P60, | |
158 | V4L2_DV_BT_DMT_1600X1200P60, | |
159 | V4L2_DV_BT_DMT_1680X1050P60_RB, | |
160 | V4L2_DV_BT_DMT_1680X1050P60, | |
161 | V4L2_DV_BT_DMT_1792X1344P60, | |
162 | V4L2_DV_BT_DMT_1856X1392P60, | |
163 | V4L2_DV_BT_DMT_1920X1200P60_RB, | |
547ed542 | 164 | V4L2_DV_BT_DMT_1366X768P60_RB, |
54450f59 HV |
165 | V4L2_DV_BT_DMT_1366X768P60, |
166 | V4L2_DV_BT_DMT_1920X1080P60, | |
167 | { }, | |
168 | }; | |
169 | ||
ccbd5bc4 HV |
170 | struct adv7604_video_standards { |
171 | struct v4l2_dv_timings timings; | |
172 | u8 vid_std; | |
173 | u8 v_freq; | |
174 | }; | |
175 | ||
176 | /* sorted by number of lines */ | |
177 | static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { | |
178 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ | |
179 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
180 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, | |
181 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, | |
182 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
183 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
184 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
185 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
186 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
187 | /* TODO add 1920x1080P60_RB (CVT timing) */ | |
188 | { }, | |
189 | }; | |
190 | ||
191 | /* sorted by number of lines */ | |
192 | static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { | |
193 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
194 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
195 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
196 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
197 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
198 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
199 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
200 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
201 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
202 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
203 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
204 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
205 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
206 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
207 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
208 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, | |
209 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, | |
210 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, | |
211 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, | |
212 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ | |
213 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ | |
214 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, | |
215 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ | |
216 | { }, | |
217 | }; | |
218 | ||
219 | /* sorted by number of lines */ | |
220 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { | |
221 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, | |
222 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
223 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, | |
224 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, | |
225 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
226 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
227 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
228 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
229 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
230 | { }, | |
231 | }; | |
232 | ||
233 | /* sorted by number of lines */ | |
234 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { | |
235 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
236 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
237 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
238 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
239 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
240 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
241 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
242 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
243 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
244 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
245 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
246 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
247 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
248 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
249 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
250 | { }, | |
251 | }; | |
252 | ||
54450f59 HV |
253 | /* ----------------------------------------------------------------------- */ |
254 | ||
255 | static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) | |
256 | { | |
257 | return container_of(sd, struct adv7604_state, sd); | |
258 | } | |
259 | ||
260 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) | |
261 | { | |
262 | return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; | |
263 | } | |
264 | ||
265 | static inline unsigned hblanking(const struct v4l2_bt_timings *t) | |
266 | { | |
eacf8f9a | 267 | return V4L2_DV_BT_BLANKING_WIDTH(t); |
54450f59 HV |
268 | } |
269 | ||
270 | static inline unsigned htotal(const struct v4l2_bt_timings *t) | |
271 | { | |
eacf8f9a | 272 | return V4L2_DV_BT_FRAME_WIDTH(t); |
54450f59 HV |
273 | } |
274 | ||
275 | static inline unsigned vblanking(const struct v4l2_bt_timings *t) | |
276 | { | |
eacf8f9a | 277 | return V4L2_DV_BT_BLANKING_HEIGHT(t); |
54450f59 HV |
278 | } |
279 | ||
280 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) | |
281 | { | |
eacf8f9a | 282 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
54450f59 HV |
283 | } |
284 | ||
285 | /* ----------------------------------------------------------------------- */ | |
286 | ||
287 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, | |
288 | u8 command, bool check) | |
289 | { | |
290 | union i2c_smbus_data data; | |
291 | ||
292 | if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
293 | I2C_SMBUS_READ, command, | |
294 | I2C_SMBUS_BYTE_DATA, &data)) | |
295 | return data.byte; | |
296 | if (check) | |
297 | v4l_err(client, "error reading %02x, %02x\n", | |
298 | client->addr, command); | |
299 | return -EIO; | |
300 | } | |
301 | ||
302 | static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) | |
303 | { | |
304 | return adv_smbus_read_byte_data_check(client, command, true); | |
305 | } | |
306 | ||
307 | static s32 adv_smbus_write_byte_data(struct i2c_client *client, | |
308 | u8 command, u8 value) | |
309 | { | |
310 | union i2c_smbus_data data; | |
311 | int err; | |
312 | int i; | |
313 | ||
314 | data.byte = value; | |
315 | for (i = 0; i < 3; i++) { | |
316 | err = i2c_smbus_xfer(client->adapter, client->addr, | |
317 | client->flags, | |
318 | I2C_SMBUS_WRITE, command, | |
319 | I2C_SMBUS_BYTE_DATA, &data); | |
320 | if (!err) | |
321 | break; | |
322 | } | |
323 | if (err < 0) | |
324 | v4l_err(client, "error writing %02x, %02x, %02x\n", | |
325 | client->addr, command, value); | |
326 | return err; | |
327 | } | |
328 | ||
329 | static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, | |
330 | u8 command, unsigned length, const u8 *values) | |
331 | { | |
332 | union i2c_smbus_data data; | |
333 | ||
334 | if (length > I2C_SMBUS_BLOCK_MAX) | |
335 | length = I2C_SMBUS_BLOCK_MAX; | |
336 | data.block[0] = length; | |
337 | memcpy(data.block + 1, values, length); | |
338 | return i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
339 | I2C_SMBUS_WRITE, command, | |
340 | I2C_SMBUS_I2C_BLOCK_DATA, &data); | |
341 | } | |
342 | ||
343 | /* ----------------------------------------------------------------------- */ | |
344 | ||
345 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) | |
346 | { | |
347 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
348 | ||
349 | return adv_smbus_read_byte_data(client, reg); | |
350 | } | |
351 | ||
352 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
353 | { | |
354 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
355 | ||
356 | return adv_smbus_write_byte_data(client, reg, val); | |
357 | } | |
358 | ||
359 | static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
360 | { | |
361 | return io_write(sd, reg, (io_read(sd, reg) & mask) | val); | |
362 | } | |
363 | ||
364 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) | |
365 | { | |
366 | struct adv7604_state *state = to_state(sd); | |
367 | ||
368 | return adv_smbus_read_byte_data(state->i2c_avlink, reg); | |
369 | } | |
370 | ||
371 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
372 | { | |
373 | struct adv7604_state *state = to_state(sd); | |
374 | ||
375 | return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); | |
376 | } | |
377 | ||
378 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) | |
379 | { | |
380 | struct adv7604_state *state = to_state(sd); | |
381 | ||
382 | return adv_smbus_read_byte_data(state->i2c_cec, reg); | |
383 | } | |
384 | ||
385 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
386 | { | |
387 | struct adv7604_state *state = to_state(sd); | |
388 | ||
389 | return adv_smbus_write_byte_data(state->i2c_cec, reg, val); | |
390 | } | |
391 | ||
392 | static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
393 | { | |
394 | return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); | |
395 | } | |
396 | ||
397 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) | |
398 | { | |
399 | struct adv7604_state *state = to_state(sd); | |
400 | ||
401 | return adv_smbus_read_byte_data(state->i2c_infoframe, reg); | |
402 | } | |
403 | ||
404 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
405 | { | |
406 | struct adv7604_state *state = to_state(sd); | |
407 | ||
408 | return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); | |
409 | } | |
410 | ||
411 | static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) | |
412 | { | |
413 | struct adv7604_state *state = to_state(sd); | |
414 | ||
415 | return adv_smbus_read_byte_data(state->i2c_esdp, reg); | |
416 | } | |
417 | ||
418 | static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
419 | { | |
420 | struct adv7604_state *state = to_state(sd); | |
421 | ||
422 | return adv_smbus_write_byte_data(state->i2c_esdp, reg, val); | |
423 | } | |
424 | ||
425 | static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) | |
426 | { | |
427 | struct adv7604_state *state = to_state(sd); | |
428 | ||
429 | return adv_smbus_read_byte_data(state->i2c_dpp, reg); | |
430 | } | |
431 | ||
432 | static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
433 | { | |
434 | struct adv7604_state *state = to_state(sd); | |
435 | ||
436 | return adv_smbus_write_byte_data(state->i2c_dpp, reg, val); | |
437 | } | |
438 | ||
439 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) | |
440 | { | |
441 | struct adv7604_state *state = to_state(sd); | |
442 | ||
443 | return adv_smbus_read_byte_data(state->i2c_afe, reg); | |
444 | } | |
445 | ||
446 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
447 | { | |
448 | struct adv7604_state *state = to_state(sd); | |
449 | ||
450 | return adv_smbus_write_byte_data(state->i2c_afe, reg, val); | |
451 | } | |
452 | ||
453 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) | |
454 | { | |
455 | struct adv7604_state *state = to_state(sd); | |
456 | ||
457 | return adv_smbus_read_byte_data(state->i2c_repeater, reg); | |
458 | } | |
459 | ||
460 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
461 | { | |
462 | struct adv7604_state *state = to_state(sd); | |
463 | ||
464 | return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); | |
465 | } | |
466 | ||
467 | static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
468 | { | |
469 | return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); | |
470 | } | |
471 | ||
472 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) | |
473 | { | |
474 | struct adv7604_state *state = to_state(sd); | |
475 | ||
476 | return adv_smbus_read_byte_data(state->i2c_edid, reg); | |
477 | } | |
478 | ||
479 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
480 | { | |
481 | struct adv7604_state *state = to_state(sd); | |
482 | ||
483 | return adv_smbus_write_byte_data(state->i2c_edid, reg, val); | |
484 | } | |
485 | ||
486 | static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) | |
487 | { | |
488 | struct adv7604_state *state = to_state(sd); | |
489 | struct i2c_client *client = state->i2c_edid; | |
490 | u8 msgbuf0[1] = { 0 }; | |
491 | u8 msgbuf1[256]; | |
09f29673 S |
492 | struct i2c_msg msg[2] = { |
493 | { | |
494 | .addr = client->addr, | |
495 | .len = 1, | |
496 | .buf = msgbuf0 | |
497 | }, | |
498 | { | |
499 | .addr = client->addr, | |
500 | .flags = I2C_M_RD, | |
501 | .len = len, | |
502 | .buf = msgbuf1 | |
503 | }, | |
504 | }; | |
54450f59 HV |
505 | |
506 | if (i2c_transfer(client->adapter, msg, 2) < 0) | |
507 | return -EIO; | |
508 | memcpy(val, msgbuf1, len); | |
509 | return 0; | |
510 | } | |
511 | ||
512 | static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) | |
513 | { | |
514 | struct delayed_work *dwork = to_delayed_work(work); | |
515 | struct adv7604_state *state = container_of(dwork, struct adv7604_state, | |
516 | delayed_work_enable_hotplug); | |
517 | struct v4l2_subdev *sd = &state->sd; | |
518 | ||
519 | v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); | |
520 | ||
4a31a93a | 521 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); |
54450f59 HV |
522 | } |
523 | ||
524 | static inline int edid_write_block(struct v4l2_subdev *sd, | |
525 | unsigned len, const u8 *val) | |
526 | { | |
527 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
528 | struct adv7604_state *state = to_state(sd); | |
529 | int err = 0; | |
530 | int i; | |
531 | ||
532 | v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); | |
533 | ||
54450f59 HV |
534 | /* Disables I2C access to internal EDID ram from DDC port */ |
535 | rep_write_and_or(sd, 0x77, 0xf0, 0x0); | |
536 | ||
537 | for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) | |
538 | err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, | |
539 | I2C_SMBUS_BLOCK_MAX, val + i); | |
540 | if (err) | |
541 | return err; | |
542 | ||
543 | /* adv7604 calculates the checksums and enables I2C access to internal | |
4a31a93a MR |
544 | EDID RAM from DDC port. */ |
545 | rep_write_and_or(sd, 0x77, 0xf0, state->edid.present); | |
54450f59 HV |
546 | |
547 | for (i = 0; i < 1000; i++) { | |
4a31a93a | 548 | if (rep_read(sd, 0x7d) & state->edid.present) |
54450f59 HV |
549 | break; |
550 | mdelay(1); | |
551 | } | |
552 | if (i == 1000) { | |
4a31a93a | 553 | v4l_err(client, "error enabling edid (0x%x)\n", state->edid.present); |
54450f59 HV |
554 | return -EIO; |
555 | } | |
556 | ||
54450f59 HV |
557 | return 0; |
558 | } | |
559 | ||
560 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) | |
561 | { | |
562 | struct adv7604_state *state = to_state(sd); | |
563 | ||
564 | return adv_smbus_read_byte_data(state->i2c_hdmi, reg); | |
565 | } | |
566 | ||
567 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
568 | { | |
569 | struct adv7604_state *state = to_state(sd); | |
570 | ||
571 | return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); | |
572 | } | |
573 | ||
4a31a93a MR |
574 | static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
575 | { | |
576 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); | |
577 | } | |
578 | ||
54450f59 HV |
579 | static inline int test_read(struct v4l2_subdev *sd, u8 reg) |
580 | { | |
581 | struct adv7604_state *state = to_state(sd); | |
582 | ||
583 | return adv_smbus_read_byte_data(state->i2c_test, reg); | |
584 | } | |
585 | ||
586 | static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
587 | { | |
588 | struct adv7604_state *state = to_state(sd); | |
589 | ||
590 | return adv_smbus_write_byte_data(state->i2c_test, reg, val); | |
591 | } | |
592 | ||
593 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) | |
594 | { | |
595 | struct adv7604_state *state = to_state(sd); | |
596 | ||
597 | return adv_smbus_read_byte_data(state->i2c_cp, reg); | |
598 | } | |
599 | ||
600 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
601 | { | |
602 | struct adv7604_state *state = to_state(sd); | |
603 | ||
604 | return adv_smbus_write_byte_data(state->i2c_cp, reg, val); | |
605 | } | |
606 | ||
607 | static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
608 | { | |
609 | return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); | |
610 | } | |
611 | ||
612 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) | |
613 | { | |
614 | struct adv7604_state *state = to_state(sd); | |
615 | ||
616 | return adv_smbus_read_byte_data(state->i2c_vdp, reg); | |
617 | } | |
618 | ||
619 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
620 | { | |
621 | struct adv7604_state *state = to_state(sd); | |
622 | ||
623 | return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); | |
624 | } | |
625 | ||
626 | /* ----------------------------------------------------------------------- */ | |
627 | ||
4a31a93a MR |
628 | static inline bool is_analog_input(struct v4l2_subdev *sd) |
629 | { | |
630 | struct adv7604_state *state = to_state(sd); | |
631 | ||
632 | return state->selected_input == ADV7604_INPUT_VGA_RGB || | |
633 | state->selected_input == ADV7604_INPUT_VGA_COMP; | |
634 | } | |
635 | ||
636 | static inline bool is_digital_input(struct v4l2_subdev *sd) | |
637 | { | |
638 | struct adv7604_state *state = to_state(sd); | |
639 | ||
640 | return state->selected_input == ADV7604_INPUT_HDMI_PORT_A || | |
641 | state->selected_input == ADV7604_INPUT_HDMI_PORT_B || | |
642 | state->selected_input == ADV7604_INPUT_HDMI_PORT_C || | |
643 | state->selected_input == ADV7604_INPUT_HDMI_PORT_D; | |
644 | } | |
645 | ||
646 | /* ----------------------------------------------------------------------- */ | |
647 | ||
54450f59 HV |
648 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
649 | static void adv7604_inv_register(struct v4l2_subdev *sd) | |
650 | { | |
651 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); | |
652 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); | |
653 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); | |
654 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); | |
655 | v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); | |
656 | v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); | |
657 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); | |
658 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); | |
659 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); | |
660 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); | |
661 | v4l2_info(sd, "0xa00-0xaff: Test Map\n"); | |
662 | v4l2_info(sd, "0xb00-0xbff: CP Map\n"); | |
663 | v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); | |
664 | } | |
665 | ||
666 | static int adv7604_g_register(struct v4l2_subdev *sd, | |
667 | struct v4l2_dbg_register *reg) | |
668 | { | |
54450f59 HV |
669 | reg->size = 1; |
670 | switch (reg->reg >> 8) { | |
671 | case 0: | |
672 | reg->val = io_read(sd, reg->reg & 0xff); | |
673 | break; | |
674 | case 1: | |
675 | reg->val = avlink_read(sd, reg->reg & 0xff); | |
676 | break; | |
677 | case 2: | |
678 | reg->val = cec_read(sd, reg->reg & 0xff); | |
679 | break; | |
680 | case 3: | |
681 | reg->val = infoframe_read(sd, reg->reg & 0xff); | |
682 | break; | |
683 | case 4: | |
684 | reg->val = esdp_read(sd, reg->reg & 0xff); | |
685 | break; | |
686 | case 5: | |
687 | reg->val = dpp_read(sd, reg->reg & 0xff); | |
688 | break; | |
689 | case 6: | |
690 | reg->val = afe_read(sd, reg->reg & 0xff); | |
691 | break; | |
692 | case 7: | |
693 | reg->val = rep_read(sd, reg->reg & 0xff); | |
694 | break; | |
695 | case 8: | |
696 | reg->val = edid_read(sd, reg->reg & 0xff); | |
697 | break; | |
698 | case 9: | |
699 | reg->val = hdmi_read(sd, reg->reg & 0xff); | |
700 | break; | |
701 | case 0xa: | |
702 | reg->val = test_read(sd, reg->reg & 0xff); | |
703 | break; | |
704 | case 0xb: | |
705 | reg->val = cp_read(sd, reg->reg & 0xff); | |
706 | break; | |
707 | case 0xc: | |
708 | reg->val = vdp_read(sd, reg->reg & 0xff); | |
709 | break; | |
710 | default: | |
711 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); | |
712 | adv7604_inv_register(sd); | |
713 | break; | |
714 | } | |
715 | return 0; | |
716 | } | |
717 | ||
718 | static int adv7604_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 719 | const struct v4l2_dbg_register *reg) |
54450f59 | 720 | { |
1577461b HV |
721 | u8 val = reg->val & 0xff; |
722 | ||
54450f59 HV |
723 | switch (reg->reg >> 8) { |
724 | case 0: | |
1577461b | 725 | io_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
726 | break; |
727 | case 1: | |
1577461b | 728 | avlink_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
729 | break; |
730 | case 2: | |
1577461b | 731 | cec_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
732 | break; |
733 | case 3: | |
1577461b | 734 | infoframe_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
735 | break; |
736 | case 4: | |
1577461b | 737 | esdp_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
738 | break; |
739 | case 5: | |
1577461b | 740 | dpp_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
741 | break; |
742 | case 6: | |
1577461b | 743 | afe_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
744 | break; |
745 | case 7: | |
1577461b | 746 | rep_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
747 | break; |
748 | case 8: | |
1577461b | 749 | edid_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
750 | break; |
751 | case 9: | |
1577461b | 752 | hdmi_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
753 | break; |
754 | case 0xa: | |
1577461b | 755 | test_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
756 | break; |
757 | case 0xb: | |
1577461b | 758 | cp_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
759 | break; |
760 | case 0xc: | |
1577461b | 761 | vdp_write(sd, reg->reg & 0xff, val); |
54450f59 HV |
762 | break; |
763 | default: | |
764 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); | |
765 | adv7604_inv_register(sd); | |
766 | break; | |
767 | } | |
768 | return 0; | |
769 | } | |
770 | #endif | |
771 | ||
772 | static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) | |
773 | { | |
774 | struct adv7604_state *state = to_state(sd); | |
4a31a93a | 775 | u8 reg_io_6f = io_read(sd, 0x6f); |
54450f59 | 776 | |
54450f59 | 777 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, |
4a31a93a MR |
778 | ((reg_io_6f & 0x10) >> 4) | |
779 | ((reg_io_6f & 0x08) >> 2) | | |
780 | (reg_io_6f & 0x04) | | |
781 | ((reg_io_6f & 0x02) << 2)); | |
54450f59 HV |
782 | } |
783 | ||
ccbd5bc4 HV |
784 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
785 | u8 prim_mode, | |
786 | const struct adv7604_video_standards *predef_vid_timings, | |
787 | const struct v4l2_dv_timings *timings) | |
788 | { | |
ccbd5bc4 HV |
789 | int i; |
790 | ||
791 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { | |
ef1ed8f5 | 792 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, |
4a31a93a | 793 | is_digital_input(sd) ? 250000 : 1000000)) |
ccbd5bc4 HV |
794 | continue; |
795 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ | |
796 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + | |
797 | prim_mode); /* v_freq and prim mode */ | |
798 | return 0; | |
799 | } | |
800 | ||
801 | return -1; | |
802 | } | |
803 | ||
804 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, | |
805 | struct v4l2_dv_timings *timings) | |
54450f59 | 806 | { |
ccbd5bc4 HV |
807 | struct adv7604_state *state = to_state(sd); |
808 | int err; | |
809 | ||
810 | v4l2_dbg(1, debug, sd, "%s", __func__); | |
811 | ||
812 | /* reset to default values */ | |
813 | io_write(sd, 0x16, 0x43); | |
814 | io_write(sd, 0x17, 0x5a); | |
815 | /* disable embedded syncs for auto graphics mode */ | |
816 | cp_write_and_or(sd, 0x81, 0xef, 0x00); | |
817 | cp_write(sd, 0x8f, 0x00); | |
818 | cp_write(sd, 0x90, 0x00); | |
819 | cp_write(sd, 0xa2, 0x00); | |
820 | cp_write(sd, 0xa3, 0x00); | |
821 | cp_write(sd, 0xa4, 0x00); | |
822 | cp_write(sd, 0xa5, 0x00); | |
823 | cp_write(sd, 0xa6, 0x00); | |
824 | cp_write(sd, 0xa7, 0x00); | |
825 | cp_write(sd, 0xab, 0x00); | |
826 | cp_write(sd, 0xac, 0x00); | |
827 | ||
4a31a93a | 828 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
829 | err = find_and_set_predefined_video_timings(sd, |
830 | 0x01, adv7604_prim_mode_comp, timings); | |
831 | if (err) | |
832 | err = find_and_set_predefined_video_timings(sd, | |
833 | 0x02, adv7604_prim_mode_gr, timings); | |
4a31a93a | 834 | } else if (is_digital_input(sd)) { |
ccbd5bc4 HV |
835 | err = find_and_set_predefined_video_timings(sd, |
836 | 0x05, adv7604_prim_mode_hdmi_comp, timings); | |
837 | if (err) | |
838 | err = find_and_set_predefined_video_timings(sd, | |
839 | 0x06, adv7604_prim_mode_hdmi_gr, timings); | |
4a31a93a MR |
840 | } else { |
841 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
842 | __func__, state->selected_input); | |
ccbd5bc4 | 843 | err = -1; |
ccbd5bc4 HV |
844 | } |
845 | ||
846 | ||
847 | return err; | |
848 | } | |
849 | ||
850 | static void configure_custom_video_timings(struct v4l2_subdev *sd, | |
851 | const struct v4l2_bt_timings *bt) | |
852 | { | |
853 | struct adv7604_state *state = to_state(sd); | |
54450f59 | 854 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ccbd5bc4 HV |
855 | u32 width = htotal(bt); |
856 | u32 height = vtotal(bt); | |
857 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; | |
858 | u16 cp_start_eav = width - bt->hfrontporch; | |
859 | u16 cp_start_vbi = height - bt->vfrontporch; | |
860 | u16 cp_end_vbi = bt->vsync + bt->vbackporch; | |
861 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? | |
862 | ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; | |
863 | const u8 pll[2] = { | |
864 | 0xc0 | ((width >> 8) & 0x1f), | |
865 | width & 0xff | |
866 | }; | |
54450f59 HV |
867 | |
868 | v4l2_dbg(2, debug, sd, "%s\n", __func__); | |
869 | ||
4a31a93a | 870 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
871 | /* auto graphics */ |
872 | io_write(sd, 0x00, 0x07); /* video std */ | |
873 | io_write(sd, 0x01, 0x02); /* prim mode */ | |
874 | /* enable embedded syncs for auto graphics mode */ | |
875 | cp_write_and_or(sd, 0x81, 0xef, 0x10); | |
54450f59 | 876 | |
ccbd5bc4 | 877 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
54450f59 HV |
878 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
879 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ | |
4a31a93a | 880 | if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) |
54450f59 | 881 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); |
54450f59 HV |
882 | |
883 | /* active video - horizontal timing */ | |
54450f59 | 884 | cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); |
ccbd5bc4 | 885 | cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | |
4a31a93a | 886 | ((cp_start_eav >> 8) & 0x0f)); |
54450f59 HV |
887 | cp_write(sd, 0xa4, cp_start_eav & 0xff); |
888 | ||
889 | /* active video - vertical timing */ | |
54450f59 | 890 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); |
ccbd5bc4 | 891 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | |
4a31a93a | 892 | ((cp_end_vbi >> 8) & 0xf)); |
54450f59 | 893 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); |
4a31a93a | 894 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 895 | /* set default prim_mode/vid_std for HDMI |
39c1cb2b | 896 | according to [REF_03, c. 4.2] */ |
ccbd5bc4 HV |
897 | io_write(sd, 0x00, 0x02); /* video std */ |
898 | io_write(sd, 0x01, 0x06); /* prim mode */ | |
4a31a93a MR |
899 | } else { |
900 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
901 | __func__, state->selected_input); | |
54450f59 | 902 | } |
54450f59 | 903 | |
ccbd5bc4 HV |
904 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); |
905 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); | |
906 | cp_write(sd, 0xab, (height >> 4) & 0xff); | |
907 | cp_write(sd, 0xac, (height & 0x0f) << 4); | |
908 | } | |
54450f59 HV |
909 | |
910 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) | |
911 | { | |
912 | struct adv7604_state *state = to_state(sd); | |
913 | ||
9833239e MR |
914 | v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n", |
915 | __func__, state->rgb_quantization_range); | |
916 | ||
54450f59 HV |
917 | switch (state->rgb_quantization_range) { |
918 | case V4L2_DV_RGB_RANGE_AUTO: | |
9833239e MR |
919 | if (state->selected_input == ADV7604_INPUT_VGA_RGB) { |
920 | /* Receiving analog RGB signal | |
921 | * Set RGB full range (0-255) */ | |
922 | io_write_and_or(sd, 0x02, 0x0f, 0x10); | |
923 | break; | |
924 | } | |
925 | ||
926 | if (state->selected_input == ADV7604_INPUT_VGA_COMP) { | |
927 | /* Receiving analog YPbPr signal | |
928 | * Set automode */ | |
929 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); | |
930 | break; | |
931 | } | |
932 | ||
933 | if (hdmi_read(sd, 0x05) & 0x80) { | |
934 | /* Receiving HDMI signal | |
935 | * Set automode */ | |
6b0d5d34 | 936 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); |
9833239e MR |
937 | break; |
938 | } | |
939 | ||
940 | /* Receiving DVI-D signal | |
941 | * ADV7604 selects RGB limited range regardless of | |
942 | * input format (CE/IT) in automatic mode */ | |
943 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { | |
944 | /* RGB limited range (16-235) */ | |
945 | io_write_and_or(sd, 0x02, 0x0f, 0x00); | |
946 | } else { | |
947 | /* RGB full range (0-255) */ | |
948 | io_write_and_or(sd, 0x02, 0x0f, 0x10); | |
54450f59 HV |
949 | } |
950 | break; | |
951 | case V4L2_DV_RGB_RANGE_LIMITED: | |
952 | /* RGB limited range (16-235) */ | |
953 | io_write_and_or(sd, 0x02, 0x0f, 0x00); | |
954 | break; | |
955 | case V4L2_DV_RGB_RANGE_FULL: | |
956 | /* RGB full range (0-255) */ | |
957 | io_write_and_or(sd, 0x02, 0x0f, 0x10); | |
958 | break; | |
959 | } | |
960 | } | |
961 | ||
962 | ||
963 | static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) | |
964 | { | |
965 | struct v4l2_subdev *sd = to_sd(ctrl); | |
966 | struct adv7604_state *state = to_state(sd); | |
967 | ||
968 | switch (ctrl->id) { | |
969 | case V4L2_CID_BRIGHTNESS: | |
970 | cp_write(sd, 0x3c, ctrl->val); | |
971 | return 0; | |
972 | case V4L2_CID_CONTRAST: | |
973 | cp_write(sd, 0x3a, ctrl->val); | |
974 | return 0; | |
975 | case V4L2_CID_SATURATION: | |
976 | cp_write(sd, 0x3b, ctrl->val); | |
977 | return 0; | |
978 | case V4L2_CID_HUE: | |
979 | cp_write(sd, 0x3d, ctrl->val); | |
980 | return 0; | |
981 | case V4L2_CID_DV_RX_RGB_RANGE: | |
982 | state->rgb_quantization_range = ctrl->val; | |
983 | set_rgb_quantization_range(sd); | |
984 | return 0; | |
985 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: | |
986 | /* Set the analog sampling phase. This is needed to find the | |
987 | best sampling phase for analog video: an application or | |
988 | driver has to try a number of phases and analyze the picture | |
989 | quality before settling on the best performing phase. */ | |
990 | afe_write(sd, 0xc8, ctrl->val); | |
991 | return 0; | |
992 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: | |
993 | /* Use the default blue color for free running mode, | |
994 | or supply your own. */ | |
995 | cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); | |
996 | return 0; | |
997 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: | |
998 | cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); | |
999 | cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); | |
1000 | cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); | |
1001 | return 0; | |
1002 | } | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | ||
54450f59 HV |
1006 | /* ----------------------------------------------------------------------- */ |
1007 | ||
1008 | static inline bool no_power(struct v4l2_subdev *sd) | |
1009 | { | |
1010 | /* Entire chip or CP powered off */ | |
1011 | return io_read(sd, 0x0c) & 0x24; | |
1012 | } | |
1013 | ||
1014 | static inline bool no_signal_tmds(struct v4l2_subdev *sd) | |
1015 | { | |
4a31a93a MR |
1016 | struct adv7604_state *state = to_state(sd); |
1017 | ||
1018 | return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); | |
54450f59 HV |
1019 | } |
1020 | ||
1021 | static inline bool no_lock_tmds(struct v4l2_subdev *sd) | |
1022 | { | |
1023 | return (io_read(sd, 0x6a) & 0xe0) != 0xe0; | |
1024 | } | |
1025 | ||
bb88f325 MB |
1026 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
1027 | { | |
1028 | return hdmi_read(sd, 0x05) & 0x80; | |
1029 | } | |
1030 | ||
54450f59 HV |
1031 | static inline bool no_lock_sspd(struct v4l2_subdev *sd) |
1032 | { | |
1033 | /* TODO channel 2 */ | |
1034 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); | |
1035 | } | |
1036 | ||
1037 | static inline bool no_lock_stdi(struct v4l2_subdev *sd) | |
1038 | { | |
1039 | /* TODO channel 2 */ | |
1040 | return !(cp_read(sd, 0xb1) & 0x80); | |
1041 | } | |
1042 | ||
1043 | static inline bool no_signal(struct v4l2_subdev *sd) | |
1044 | { | |
54450f59 HV |
1045 | bool ret; |
1046 | ||
1047 | ret = no_power(sd); | |
1048 | ||
1049 | ret |= no_lock_stdi(sd); | |
1050 | ret |= no_lock_sspd(sd); | |
1051 | ||
4a31a93a | 1052 | if (is_digital_input(sd)) { |
54450f59 HV |
1053 | ret |= no_lock_tmds(sd); |
1054 | ret |= no_signal_tmds(sd); | |
1055 | } | |
1056 | ||
1057 | return ret; | |
1058 | } | |
1059 | ||
1060 | static inline bool no_lock_cp(struct v4l2_subdev *sd) | |
1061 | { | |
1062 | /* CP has detected a non standard number of lines on the incoming | |
1063 | video compared to what it is configured to receive by s_dv_timings */ | |
1064 | return io_read(sd, 0x12) & 0x01; | |
1065 | } | |
1066 | ||
1067 | static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) | |
1068 | { | |
54450f59 HV |
1069 | *status = 0; |
1070 | *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; | |
1071 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; | |
1072 | if (no_lock_cp(sd)) | |
4a31a93a | 1073 | *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; |
54450f59 HV |
1074 | |
1075 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | /* ----------------------------------------------------------------------- */ | |
1081 | ||
54450f59 HV |
1082 | struct stdi_readback { |
1083 | u16 bl, lcf, lcvs; | |
1084 | u8 hs_pol, vs_pol; | |
1085 | bool interlaced; | |
1086 | }; | |
1087 | ||
1088 | static int stdi2dv_timings(struct v4l2_subdev *sd, | |
1089 | struct stdi_readback *stdi, | |
1090 | struct v4l2_dv_timings *timings) | |
1091 | { | |
1092 | struct adv7604_state *state = to_state(sd); | |
1093 | u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; | |
1094 | u32 pix_clk; | |
1095 | int i; | |
1096 | ||
1097 | for (i = 0; adv7604_timings[i].bt.height; i++) { | |
1098 | if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) | |
1099 | continue; | |
1100 | if (adv7604_timings[i].bt.vsync != stdi->lcvs) | |
1101 | continue; | |
1102 | ||
1103 | pix_clk = hfreq * htotal(&adv7604_timings[i].bt); | |
1104 | ||
1105 | if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && | |
1106 | (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { | |
1107 | *timings = adv7604_timings[i]; | |
1108 | return 0; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1113 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1114 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1115 | timings)) | |
1116 | return 0; | |
1117 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1118 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1119 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1120 | state->aspect_ratio, timings)) | |
1121 | return 0; | |
1122 | ||
ccbd5bc4 HV |
1123 | v4l2_dbg(2, debug, sd, |
1124 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", | |
1125 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, | |
1126 | stdi->hs_pol, stdi->vs_pol); | |
54450f59 HV |
1127 | return -1; |
1128 | } | |
1129 | ||
1130 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) | |
1131 | { | |
1132 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1133 | v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); | |
1134 | return -1; | |
1135 | } | |
1136 | ||
1137 | /* read STDI */ | |
1138 | stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); | |
1139 | stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); | |
1140 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; | |
1141 | stdi->interlaced = io_read(sd, 0x12) & 0x10; | |
1142 | ||
1143 | /* read SSPD */ | |
1144 | if ((cp_read(sd, 0xb5) & 0x03) == 0x01) { | |
1145 | stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? | |
1146 | ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); | |
1147 | stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? | |
1148 | ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); | |
1149 | } else { | |
1150 | stdi->hs_pol = 'x'; | |
1151 | stdi->vs_pol = 'x'; | |
1152 | } | |
1153 | ||
1154 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1155 | v4l2_dbg(2, debug, sd, | |
1156 | "%s: signal lost during readout of STDI/SSPD\n", __func__); | |
1157 | return -1; | |
1158 | } | |
1159 | ||
1160 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { | |
1161 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); | |
1162 | memset(stdi, 0, sizeof(struct stdi_readback)); | |
1163 | return -1; | |
1164 | } | |
1165 | ||
1166 | v4l2_dbg(2, debug, sd, | |
1167 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", | |
1168 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, | |
1169 | stdi->hs_pol, stdi->vs_pol, | |
1170 | stdi->interlaced ? "interlaced" : "progressive"); | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, | |
1176 | struct v4l2_enum_dv_timings *timings) | |
1177 | { | |
1178 | if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) | |
1179 | return -EINVAL; | |
1180 | memset(timings->reserved, 0, sizeof(timings->reserved)); | |
1181 | timings->timings = adv7604_timings[timings->index]; | |
1182 | return 0; | |
1183 | } | |
1184 | ||
1185 | static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, | |
1186 | struct v4l2_dv_timings_cap *cap) | |
1187 | { | |
54450f59 HV |
1188 | cap->type = V4L2_DV_BT_656_1120; |
1189 | cap->bt.max_width = 1920; | |
1190 | cap->bt.max_height = 1200; | |
fe9c2564 | 1191 | cap->bt.min_pixelclock = 25000000; |
4a31a93a | 1192 | if (is_digital_input(sd)) |
54450f59 HV |
1193 | cap->bt.max_pixelclock = 225000000; |
1194 | else | |
1195 | cap->bt.max_pixelclock = 170000000; | |
1196 | cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | | |
1197 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; | |
1198 | cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | | |
1199 | V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings | |
1204 | if the format is listed in adv7604_timings[] */ | |
1205 | static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, | |
1206 | struct v4l2_dv_timings *timings) | |
1207 | { | |
54450f59 HV |
1208 | int i; |
1209 | ||
1210 | for (i = 0; adv7604_timings[i].bt.width; i++) { | |
ef1ed8f5 | 1211 | if (v4l2_match_dv_timings(timings, &adv7604_timings[i], |
4a31a93a | 1212 | is_digital_input(sd) ? 250000 : 1000000)) { |
54450f59 HV |
1213 | *timings = adv7604_timings[i]; |
1214 | break; | |
1215 | } | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | static int adv7604_query_dv_timings(struct v4l2_subdev *sd, | |
1220 | struct v4l2_dv_timings *timings) | |
1221 | { | |
1222 | struct adv7604_state *state = to_state(sd); | |
1223 | struct v4l2_bt_timings *bt = &timings->bt; | |
1224 | struct stdi_readback stdi; | |
1225 | ||
1226 | if (!timings) | |
1227 | return -EINVAL; | |
1228 | ||
1229 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1230 | ||
1231 | if (no_signal(sd)) { | |
1232 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); | |
1233 | return -ENOLINK; | |
1234 | } | |
1235 | ||
1236 | /* read STDI */ | |
1237 | if (read_stdi(sd, &stdi)) { | |
1238 | v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); | |
1239 | return -ENOLINK; | |
1240 | } | |
1241 | bt->interlaced = stdi.interlaced ? | |
1242 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; | |
1243 | ||
4a31a93a | 1244 | if (is_digital_input(sd)) { |
bb88f325 MB |
1245 | uint32_t freq; |
1246 | ||
54450f59 HV |
1247 | timings->type = V4L2_DV_BT_656_1120; |
1248 | ||
1249 | bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); | |
1250 | bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); | |
bb88f325 | 1251 | freq = (hdmi_read(sd, 0x06) * 1000000) + |
54450f59 | 1252 | ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000; |
bb88f325 MB |
1253 | if (is_hdmi(sd)) { |
1254 | /* adjust for deep color mode */ | |
1255 | unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; | |
1256 | ||
1257 | freq = freq * 8 / bits_per_channel; | |
1258 | } | |
1259 | bt->pixelclock = freq; | |
54450f59 HV |
1260 | bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + |
1261 | hdmi_read(sd, 0x21); | |
1262 | bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + | |
1263 | hdmi_read(sd, 0x23); | |
1264 | bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + | |
1265 | hdmi_read(sd, 0x25); | |
1266 | bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + | |
1267 | hdmi_read(sd, 0x2b)) / 2; | |
1268 | bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + | |
1269 | hdmi_read(sd, 0x2f)) / 2; | |
1270 | bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + | |
1271 | hdmi_read(sd, 0x33)) / 2; | |
1272 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | | |
1273 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); | |
1274 | if (bt->interlaced == V4L2_DV_INTERLACED) { | |
1275 | bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + | |
1276 | hdmi_read(sd, 0x0c); | |
1277 | bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + | |
1278 | hdmi_read(sd, 0x2d)) / 2; | |
1279 | bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + | |
1280 | hdmi_read(sd, 0x31)) / 2; | |
1281 | bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + | |
1282 | hdmi_read(sd, 0x35)) / 2; | |
1283 | } | |
1284 | adv7604_fill_optional_dv_timings_fields(sd, timings); | |
1285 | } else { | |
1286 | /* find format | |
80939647 | 1287 | * Since LCVS values are inaccurate [REF_03, p. 275-276], |
54450f59 HV |
1288 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. |
1289 | */ | |
1290 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1291 | goto found; | |
1292 | stdi.lcvs += 1; | |
1293 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); | |
1294 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1295 | goto found; | |
1296 | stdi.lcvs -= 2; | |
1297 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); | |
1298 | if (stdi2dv_timings(sd, &stdi, timings)) { | |
cf9afb1d HV |
1299 | /* |
1300 | * The STDI block may measure wrong values, especially | |
1301 | * for lcvs and lcf. If the driver can not find any | |
1302 | * valid timing, the STDI block is restarted to measure | |
1303 | * the video timings again. The function will return an | |
1304 | * error, but the restart of STDI will generate a new | |
1305 | * STDI interrupt and the format detection process will | |
1306 | * restart. | |
1307 | */ | |
1308 | if (state->restart_stdi_once) { | |
1309 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); | |
1310 | /* TODO restart STDI for Sync Channel 2 */ | |
1311 | /* enter one-shot mode */ | |
1312 | cp_write_and_or(sd, 0x86, 0xf9, 0x00); | |
1313 | /* trigger STDI restart */ | |
1314 | cp_write_and_or(sd, 0x86, 0xf9, 0x04); | |
1315 | /* reset to continuous mode */ | |
1316 | cp_write_and_or(sd, 0x86, 0xf9, 0x02); | |
1317 | state->restart_stdi_once = false; | |
1318 | return -ENOLINK; | |
1319 | } | |
54450f59 HV |
1320 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); |
1321 | return -ERANGE; | |
1322 | } | |
cf9afb1d | 1323 | state->restart_stdi_once = true; |
54450f59 HV |
1324 | } |
1325 | found: | |
1326 | ||
1327 | if (no_signal(sd)) { | |
1328 | v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); | |
1329 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1330 | return -ENOLINK; | |
1331 | } | |
1332 | ||
4a31a93a MR |
1333 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1334 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1335 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1336 | __func__, (u32)bt->pixelclock); | |
1337 | return -ERANGE; | |
1338 | } | |
1339 | ||
1340 | if (debug > 1) | |
11d034c8 HV |
1341 | v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", |
1342 | timings, true); | |
54450f59 HV |
1343 | |
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | static int adv7604_s_dv_timings(struct v4l2_subdev *sd, | |
1348 | struct v4l2_dv_timings *timings) | |
1349 | { | |
1350 | struct adv7604_state *state = to_state(sd); | |
1351 | struct v4l2_bt_timings *bt; | |
ccbd5bc4 | 1352 | int err; |
54450f59 HV |
1353 | |
1354 | if (!timings) | |
1355 | return -EINVAL; | |
1356 | ||
1357 | bt = &timings->bt; | |
1358 | ||
4a31a93a MR |
1359 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1360 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1361 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1362 | __func__, (u32)bt->pixelclock); | |
1363 | return -ERANGE; | |
1364 | } | |
ccbd5bc4 | 1365 | |
54450f59 HV |
1366 | adv7604_fill_optional_dv_timings_fields(sd, timings); |
1367 | ||
1368 | state->timings = *timings; | |
1369 | ||
ccbd5bc4 HV |
1370 | cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10); |
1371 | ||
1372 | /* Use prim_mode and vid_std when available */ | |
1373 | err = configure_predefined_video_timings(sd, timings); | |
1374 | if (err) { | |
1375 | /* custom settings when the video format | |
1376 | does not have prim_mode/vid_std */ | |
1377 | configure_custom_video_timings(sd, bt); | |
1378 | } | |
54450f59 HV |
1379 | |
1380 | set_rgb_quantization_range(sd); | |
1381 | ||
1382 | ||
1383 | if (debug > 1) | |
11d034c8 HV |
1384 | v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", |
1385 | timings, true); | |
54450f59 HV |
1386 | return 0; |
1387 | } | |
1388 | ||
1389 | static int adv7604_g_dv_timings(struct v4l2_subdev *sd, | |
1390 | struct v4l2_dv_timings *timings) | |
1391 | { | |
1392 | struct adv7604_state *state = to_state(sd); | |
1393 | ||
1394 | *timings = state->timings; | |
1395 | return 0; | |
1396 | } | |
1397 | ||
6b0d5d34 | 1398 | static void enable_input(struct v4l2_subdev *sd) |
54450f59 | 1399 | { |
6b0d5d34 HV |
1400 | struct adv7604_state *state = to_state(sd); |
1401 | ||
4a31a93a | 1402 | if (is_analog_input(sd)) { |
54450f59 HV |
1403 | /* enable */ |
1404 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ | |
4a31a93a | 1405 | } else if (is_digital_input(sd)) { |
54450f59 | 1406 | /* enable */ |
4a31a93a | 1407 | hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input); |
54450f59 HV |
1408 | hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */ |
1409 | hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ | |
1410 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ | |
4a31a93a MR |
1411 | } else { |
1412 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1413 | __func__, state->selected_input); | |
54450f59 HV |
1414 | } |
1415 | } | |
1416 | ||
1417 | static void disable_input(struct v4l2_subdev *sd) | |
1418 | { | |
1419 | /* disable */ | |
1420 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ | |
1421 | hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */ | |
1422 | hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ | |
1423 | } | |
1424 | ||
6b0d5d34 | 1425 | static void select_input(struct v4l2_subdev *sd) |
54450f59 | 1426 | { |
6b0d5d34 | 1427 | struct adv7604_state *state = to_state(sd); |
54450f59 | 1428 | |
4a31a93a | 1429 | if (is_analog_input(sd)) { |
54450f59 HV |
1430 | /* reset ADI recommended settings for HDMI: */ |
1431 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
1432 | hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */ | |
1433 | hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */ | |
1434 | hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */ | |
1435 | hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */ | |
1436 | hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */ | |
1437 | hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */ | |
1438 | hdmi_write(sd, 0x8d, 0x18); /* equaliser */ | |
1439 | hdmi_write(sd, 0x8e, 0x34); /* equaliser */ | |
1440 | hdmi_write(sd, 0x93, 0x88); /* equaliser */ | |
1441 | hdmi_write(sd, 0x94, 0x2e); /* equaliser */ | |
1442 | hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */ | |
1443 | ||
1444 | afe_write(sd, 0x00, 0x08); /* power up ADC */ | |
1445 | afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ | |
1446 | afe_write(sd, 0xc8, 0x00); /* phase control */ | |
1447 | ||
1448 | /* set ADI recommended settings for digitizer */ | |
1449 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
1450 | afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */ | |
1451 | afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */ | |
1452 | cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ | |
1453 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1454 | cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ | |
4a31a93a MR |
1455 | } else if (is_digital_input(sd)) { |
1456 | hdmi_write(sd, 0x00, state->selected_input & 0x03); | |
54450f59 | 1457 | |
54450f59 HV |
1458 | /* set ADI recommended settings for HDMI: */ |
1459 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
1460 | hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */ | |
1461 | hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */ | |
1462 | hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */ | |
1463 | hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */ | |
1464 | hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ | |
1465 | hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ | |
1466 | hdmi_write(sd, 0x8d, 0x18); /* equaliser */ | |
1467 | hdmi_write(sd, 0x8e, 0x34); /* equaliser */ | |
1468 | hdmi_write(sd, 0x93, 0x8b); /* equaliser */ | |
1469 | hdmi_write(sd, 0x94, 0x2d); /* equaliser */ | |
1470 | hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */ | |
1471 | ||
1472 | afe_write(sd, 0x00, 0xff); /* power down ADC */ | |
1473 | afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ | |
1474 | afe_write(sd, 0xc8, 0x40); /* phase control */ | |
1475 | ||
1476 | /* reset ADI recommended settings for digitizer */ | |
1477 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
1478 | afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ | |
1479 | afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ | |
1480 | cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ | |
1481 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1482 | cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ | |
4a31a93a MR |
1483 | } else { |
1484 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1485 | __func__, state->selected_input); | |
54450f59 HV |
1486 | } |
1487 | } | |
1488 | ||
1489 | static int adv7604_s_routing(struct v4l2_subdev *sd, | |
1490 | u32 input, u32 output, u32 config) | |
1491 | { | |
1492 | struct adv7604_state *state = to_state(sd); | |
1493 | ||
1494 | v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input); | |
1495 | ||
4a31a93a | 1496 | state->selected_input = input; |
54450f59 HV |
1497 | |
1498 | disable_input(sd); | |
1499 | ||
6b0d5d34 | 1500 | select_input(sd); |
54450f59 | 1501 | |
6b0d5d34 | 1502 | enable_input(sd); |
54450f59 HV |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, | |
1508 | enum v4l2_mbus_pixelcode *code) | |
1509 | { | |
1510 | if (index) | |
1511 | return -EINVAL; | |
1512 | /* Good enough for now */ | |
1513 | *code = V4L2_MBUS_FMT_FIXED; | |
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd, | |
1518 | struct v4l2_mbus_framefmt *fmt) | |
1519 | { | |
1520 | struct adv7604_state *state = to_state(sd); | |
1521 | ||
1522 | fmt->width = state->timings.bt.width; | |
1523 | fmt->height = state->timings.bt.height; | |
1524 | fmt->code = V4L2_MBUS_FMT_FIXED; | |
1525 | fmt->field = V4L2_FIELD_NONE; | |
1526 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { | |
1527 | fmt->colorspace = (state->timings.bt.height <= 576) ? | |
1528 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; | |
1529 | } | |
1530 | return 0; | |
1531 | } | |
1532 | ||
1533 | static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) | |
1534 | { | |
1535 | struct adv7604_state *state = to_state(sd); | |
1536 | u8 fmt_change, fmt_change_digital, tx_5v; | |
25a64ac9 | 1537 | u32 input_status; |
54450f59 HV |
1538 | |
1539 | /* format change */ | |
1540 | fmt_change = io_read(sd, 0x43) & 0x98; | |
1541 | if (fmt_change) | |
1542 | io_write(sd, 0x44, fmt_change); | |
4a31a93a | 1543 | fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0; |
54450f59 HV |
1544 | if (fmt_change_digital) |
1545 | io_write(sd, 0x6c, fmt_change_digital); | |
1546 | if (fmt_change || fmt_change_digital) { | |
1547 | v4l2_dbg(1, debug, sd, | |
25a64ac9 | 1548 | "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", |
54450f59 | 1549 | __func__, fmt_change, fmt_change_digital); |
25a64ac9 MR |
1550 | |
1551 | adv7604_g_input_status(sd, &input_status); | |
1552 | if (input_status != state->prev_input_status) { | |
1553 | v4l2_dbg(1, debug, sd, | |
1554 | "%s: input_status = 0x%x, prev_input_status = 0x%x\n", | |
1555 | __func__, input_status, state->prev_input_status); | |
1556 | state->prev_input_status = input_status; | |
1557 | v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); | |
1558 | } | |
1559 | ||
54450f59 HV |
1560 | if (handled) |
1561 | *handled = true; | |
1562 | } | |
1563 | /* tx 5v detect */ | |
4a31a93a | 1564 | tx_5v = io_read(sd, 0x70) & 0x1e; |
54450f59 HV |
1565 | if (tx_5v) { |
1566 | v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); | |
1567 | io_write(sd, 0x71, tx_5v); | |
1568 | adv7604_s_detect_tx_5v_ctrl(sd); | |
1569 | if (handled) | |
1570 | *handled = true; | |
1571 | } | |
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) | |
1576 | { | |
1577 | struct adv7604_state *state = to_state(sd); | |
4a31a93a | 1578 | u8 *data = NULL; |
54450f59 | 1579 | |
4a31a93a | 1580 | if (edid->pad > ADV7604_EDID_PORT_D) |
54450f59 HV |
1581 | return -EINVAL; |
1582 | if (edid->blocks == 0) | |
1583 | return -EINVAL; | |
4a31a93a | 1584 | if (edid->blocks > 2) |
54450f59 | 1585 | return -EINVAL; |
4a31a93a MR |
1586 | if (edid->start_block > 1) |
1587 | return -EINVAL; | |
1588 | if (edid->start_block == 1) | |
1589 | edid->blocks = 1; | |
54450f59 HV |
1590 | if (!edid->edid) |
1591 | return -EINVAL; | |
4a31a93a MR |
1592 | |
1593 | if (edid->blocks > state->edid.blocks) | |
1594 | edid->blocks = state->edid.blocks; | |
1595 | ||
1596 | switch (edid->pad) { | |
1597 | case ADV7604_EDID_PORT_A: | |
1598 | case ADV7604_EDID_PORT_B: | |
1599 | case ADV7604_EDID_PORT_C: | |
1600 | case ADV7604_EDID_PORT_D: | |
1601 | if (state->edid.present & (1 << edid->pad)) | |
1602 | data = state->edid.edid; | |
1603 | break; | |
1604 | default: | |
1605 | return -EINVAL; | |
1606 | break; | |
1607 | } | |
1608 | if (!data) | |
1609 | return -ENODATA; | |
1610 | ||
1611 | memcpy(edid->edid, | |
1612 | data + edid->start_block * 128, | |
54450f59 HV |
1613 | edid->blocks * 128); |
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) | |
1618 | { | |
1619 | struct adv7604_state *state = to_state(sd); | |
1620 | int err; | |
1621 | ||
4a31a93a | 1622 | if (edid->pad > ADV7604_EDID_PORT_D) |
54450f59 HV |
1623 | return -EINVAL; |
1624 | if (edid->start_block != 0) | |
1625 | return -EINVAL; | |
1626 | if (edid->blocks == 0) { | |
1627 | /* Pull down the hotplug pin */ | |
4a31a93a MR |
1628 | state->edid.present &= ~(1 << edid->pad); |
1629 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); | |
54450f59 HV |
1630 | /* Disables I2C access to internal EDID ram from DDC port */ |
1631 | rep_write_and_or(sd, 0x77, 0xf0, 0x0); | |
4a31a93a | 1632 | state->edid.blocks = 0; |
54450f59 HV |
1633 | /* Fall back to a 16:9 aspect ratio */ |
1634 | state->aspect_ratio.numerator = 16; | |
1635 | state->aspect_ratio.denominator = 9; | |
4a31a93a | 1636 | v4l2_dbg(2, debug, sd, "%s: clear edid\n", __func__); |
54450f59 HV |
1637 | return 0; |
1638 | } | |
4a31a93a MR |
1639 | if (edid->blocks > 2) { |
1640 | edid->blocks = 2; | |
54450f59 | 1641 | return -E2BIG; |
4a31a93a | 1642 | } |
54450f59 HV |
1643 | if (!edid->edid) |
1644 | return -EINVAL; | |
4a31a93a MR |
1645 | |
1646 | cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); | |
1647 | state->edid.present &= ~(1 << edid->pad); | |
1648 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); | |
1649 | ||
1650 | memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); | |
1651 | state->edid.blocks = edid->blocks; | |
54450f59 HV |
1652 | state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], |
1653 | edid->edid[0x16]); | |
4a31a93a MR |
1654 | state->edid.present |= edid->pad; |
1655 | ||
1656 | err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); | |
1657 | if (err < 0) { | |
54450f59 | 1658 | v4l2_err(sd, "error %d writing edid\n", err); |
4a31a93a MR |
1659 | return err; |
1660 | } | |
1661 | ||
1662 | /* enable hotplug after 100 ms */ | |
1663 | queue_delayed_work(state->work_queues, | |
1664 | &state->delayed_work_enable_hotplug, HZ / 10); | |
1665 | return 0; | |
54450f59 HV |
1666 | } |
1667 | ||
1668 | /*********** avi info frame CEA-861-E **************/ | |
1669 | ||
1670 | static void print_avi_infoframe(struct v4l2_subdev *sd) | |
1671 | { | |
1672 | int i; | |
1673 | u8 buf[14]; | |
1674 | u8 avi_len; | |
1675 | u8 avi_ver; | |
1676 | ||
bb88f325 | 1677 | if (!is_hdmi(sd)) { |
54450f59 HV |
1678 | v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); |
1679 | return; | |
1680 | } | |
1681 | if (!(io_read(sd, 0x60) & 0x01)) { | |
1682 | v4l2_info(sd, "AVI infoframe not received\n"); | |
1683 | return; | |
1684 | } | |
1685 | ||
1686 | if (io_read(sd, 0x83) & 0x01) { | |
1687 | v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); | |
1688 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
1689 | if (io_read(sd, 0x83) & 0x01) { | |
1690 | v4l2_info(sd, "AVI infoframe checksum error still present\n"); | |
1691 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
1692 | } | |
1693 | } | |
1694 | ||
1695 | avi_len = infoframe_read(sd, 0xe2); | |
1696 | avi_ver = infoframe_read(sd, 0xe1); | |
1697 | v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", | |
1698 | avi_ver, avi_len); | |
1699 | ||
1700 | if (avi_ver != 0x02) | |
1701 | return; | |
1702 | ||
1703 | for (i = 0; i < 14; i++) | |
1704 | buf[i] = infoframe_read(sd, i); | |
1705 | ||
1706 | v4l2_info(sd, | |
1707 | "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", | |
1708 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], | |
1709 | buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); | |
1710 | } | |
1711 | ||
1712 | static int adv7604_log_status(struct v4l2_subdev *sd) | |
1713 | { | |
1714 | struct adv7604_state *state = to_state(sd); | |
1715 | struct v4l2_dv_timings timings; | |
1716 | struct stdi_readback stdi; | |
1717 | u8 reg_io_0x02 = io_read(sd, 0x02); | |
1718 | ||
1719 | char *csc_coeff_sel_rb[16] = { | |
1720 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", | |
1721 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", | |
1722 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", | |
1723 | "reserved", "reserved", "reserved", "reserved", "manual" | |
1724 | }; | |
1725 | char *input_color_space_txt[16] = { | |
1726 | "RGB limited range (16-235)", "RGB full range (0-255)", | |
1727 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
9833239e | 1728 | "xvYCC Bt.601", "xvYCC Bt.709", |
54450f59 HV |
1729 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", |
1730 | "invalid", "invalid", "invalid", "invalid", "invalid", | |
1731 | "invalid", "invalid", "automatic" | |
1732 | }; | |
1733 | char *rgb_quantization_range_txt[] = { | |
1734 | "Automatic", | |
1735 | "RGB limited range (16-235)", | |
1736 | "RGB full range (0-255)", | |
1737 | }; | |
bb88f325 MB |
1738 | char *deep_color_mode_txt[4] = { |
1739 | "8-bits per channel", | |
1740 | "10-bits per channel", | |
1741 | "12-bits per channel", | |
1742 | "16-bits per channel (not supported)" | |
1743 | }; | |
54450f59 HV |
1744 | |
1745 | v4l2_info(sd, "-----Chip status-----\n"); | |
1746 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); | |
1747 | v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ? | |
4a31a93a MR |
1748 | "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A")); |
1749 | v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", | |
1750 | ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"), | |
1751 | ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"), | |
1752 | ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"), | |
1753 | ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No")); | |
54450f59 HV |
1754 | v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? |
1755 | "enabled" : "disabled"); | |
1756 | ||
1757 | v4l2_info(sd, "-----Signal status-----\n"); | |
4a31a93a MR |
1758 | v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", |
1759 | ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"), | |
1760 | ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"), | |
1761 | ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"), | |
1762 | ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No")); | |
54450f59 HV |
1763 | v4l2_info(sd, "TMDS signal detected: %s\n", |
1764 | no_signal_tmds(sd) ? "false" : "true"); | |
1765 | v4l2_info(sd, "TMDS signal locked: %s\n", | |
1766 | no_lock_tmds(sd) ? "false" : "true"); | |
1767 | v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); | |
1768 | v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); | |
1769 | v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); | |
1770 | v4l2_info(sd, "CP free run: %s\n", | |
1771 | (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); | |
ccbd5bc4 HV |
1772 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", |
1773 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, | |
1774 | (io_read(sd, 0x01) & 0x70) >> 4); | |
54450f59 HV |
1775 | |
1776 | v4l2_info(sd, "-----Video Timings-----\n"); | |
1777 | if (read_stdi(sd, &stdi)) | |
1778 | v4l2_info(sd, "STDI: not locked\n"); | |
1779 | else | |
1780 | v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", | |
1781 | stdi.lcf, stdi.bl, stdi.lcvs, | |
1782 | stdi.interlaced ? "interlaced" : "progressive", | |
1783 | stdi.hs_pol, stdi.vs_pol); | |
1784 | if (adv7604_query_dv_timings(sd, &timings)) | |
1785 | v4l2_info(sd, "No video detected\n"); | |
1786 | else | |
11d034c8 HV |
1787 | v4l2_print_dv_timings(sd->name, "Detected format: ", |
1788 | &timings, true); | |
1789 | v4l2_print_dv_timings(sd->name, "Configured format: ", | |
1790 | &state->timings, true); | |
54450f59 | 1791 | |
76eb2d30 MR |
1792 | if (no_signal(sd)) |
1793 | return 0; | |
1794 | ||
54450f59 HV |
1795 | v4l2_info(sd, "-----Color space-----\n"); |
1796 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", | |
1797 | rgb_quantization_range_txt[state->rgb_quantization_range]); | |
1798 | v4l2_info(sd, "Input color space: %s\n", | |
1799 | input_color_space_txt[reg_io_0x02 >> 4]); | |
1800 | v4l2_info(sd, "Output color space: %s %s, saturator %s\n", | |
1801 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", | |
1802 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", | |
1803 | ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? | |
76eb2d30 | 1804 | "enabled" : "disabled"); |
54450f59 HV |
1805 | v4l2_info(sd, "Color space conversion: %s\n", |
1806 | csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); | |
1807 | ||
4a31a93a | 1808 | if (!is_digital_input(sd)) |
76eb2d30 MR |
1809 | return 0; |
1810 | ||
1811 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); | |
4a31a93a MR |
1812 | v4l2_info(sd, "Digital video port selected: %c\n", |
1813 | (hdmi_read(sd, 0x00) & 0x03) + 'A'); | |
1814 | v4l2_info(sd, "HDCP encrypted content: %s\n", | |
1815 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); | |
76eb2d30 MR |
1816 | v4l2_info(sd, "HDCP keys read: %s%s\n", |
1817 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", | |
1818 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); | |
1819 | if (!is_hdmi(sd)) { | |
1820 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; | |
1821 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; | |
1822 | bool audio_mute = io_read(sd, 0x65) & 0x40; | |
1823 | ||
1824 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", | |
1825 | audio_pll_locked ? "locked" : "not locked", | |
1826 | audio_sample_packet_detect ? "detected" : "not detected", | |
1827 | audio_mute ? "muted" : "enabled"); | |
1828 | if (audio_pll_locked && audio_sample_packet_detect) { | |
1829 | v4l2_info(sd, "Audio format: %s\n", | |
1830 | (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); | |
1831 | } | |
1832 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + | |
1833 | (hdmi_read(sd, 0x5c) << 8) + | |
1834 | (hdmi_read(sd, 0x5d) & 0xf0)); | |
1835 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + | |
1836 | (hdmi_read(sd, 0x5e) << 8) + | |
1837 | hdmi_read(sd, 0x5f)); | |
1838 | v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); | |
1839 | ||
1840 | v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); | |
1841 | ||
54450f59 HV |
1842 | print_avi_infoframe(sd); |
1843 | } | |
1844 | ||
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | /* ----------------------------------------------------------------------- */ | |
1849 | ||
1850 | static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { | |
1851 | .s_ctrl = adv7604_s_ctrl, | |
1852 | }; | |
1853 | ||
1854 | static const struct v4l2_subdev_core_ops adv7604_core_ops = { | |
1855 | .log_status = adv7604_log_status, | |
1856 | .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, | |
1857 | .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, | |
1858 | .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, | |
1859 | .g_ctrl = v4l2_subdev_g_ctrl, | |
1860 | .s_ctrl = v4l2_subdev_s_ctrl, | |
1861 | .queryctrl = v4l2_subdev_queryctrl, | |
1862 | .querymenu = v4l2_subdev_querymenu, | |
54450f59 HV |
1863 | .interrupt_service_routine = adv7604_isr, |
1864 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1865 | .g_register = adv7604_g_register, | |
1866 | .s_register = adv7604_s_register, | |
1867 | #endif | |
1868 | }; | |
1869 | ||
1870 | static const struct v4l2_subdev_video_ops adv7604_video_ops = { | |
1871 | .s_routing = adv7604_s_routing, | |
1872 | .g_input_status = adv7604_g_input_status, | |
1873 | .s_dv_timings = adv7604_s_dv_timings, | |
1874 | .g_dv_timings = adv7604_g_dv_timings, | |
1875 | .query_dv_timings = adv7604_query_dv_timings, | |
1876 | .enum_dv_timings = adv7604_enum_dv_timings, | |
1877 | .dv_timings_cap = adv7604_dv_timings_cap, | |
1878 | .enum_mbus_fmt = adv7604_enum_mbus_fmt, | |
1879 | .g_mbus_fmt = adv7604_g_mbus_fmt, | |
1880 | .try_mbus_fmt = adv7604_g_mbus_fmt, | |
1881 | .s_mbus_fmt = adv7604_g_mbus_fmt, | |
1882 | }; | |
1883 | ||
1884 | static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { | |
1885 | .get_edid = adv7604_get_edid, | |
1886 | .set_edid = adv7604_set_edid, | |
1887 | }; | |
1888 | ||
1889 | static const struct v4l2_subdev_ops adv7604_ops = { | |
1890 | .core = &adv7604_core_ops, | |
1891 | .video = &adv7604_video_ops, | |
1892 | .pad = &adv7604_pad_ops, | |
1893 | }; | |
1894 | ||
1895 | /* -------------------------- custom ctrls ---------------------------------- */ | |
1896 | ||
1897 | static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { | |
1898 | .ops = &adv7604_ctrl_ops, | |
1899 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, | |
1900 | .name = "Analog Sampling Phase", | |
1901 | .type = V4L2_CTRL_TYPE_INTEGER, | |
1902 | .min = 0, | |
1903 | .max = 0x1f, | |
1904 | .step = 1, | |
1905 | .def = 0, | |
1906 | }; | |
1907 | ||
1908 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { | |
1909 | .ops = &adv7604_ctrl_ops, | |
1910 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, | |
1911 | .name = "Free Running Color, Manual", | |
1912 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
1913 | .min = false, | |
1914 | .max = true, | |
1915 | .step = 1, | |
1916 | .def = false, | |
1917 | }; | |
1918 | ||
1919 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { | |
1920 | .ops = &adv7604_ctrl_ops, | |
1921 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, | |
1922 | .name = "Free Running Color", | |
1923 | .type = V4L2_CTRL_TYPE_INTEGER, | |
1924 | .min = 0x0, | |
1925 | .max = 0xffffff, | |
1926 | .step = 0x1, | |
1927 | .def = 0x0, | |
1928 | }; | |
1929 | ||
1930 | /* ----------------------------------------------------------------------- */ | |
1931 | ||
1932 | static int adv7604_core_init(struct v4l2_subdev *sd) | |
1933 | { | |
1934 | struct adv7604_state *state = to_state(sd); | |
1935 | struct adv7604_platform_data *pdata = &state->pdata; | |
1936 | ||
1937 | hdmi_write(sd, 0x48, | |
1938 | (pdata->disable_pwrdnb ? 0x80 : 0) | | |
1939 | (pdata->disable_cable_det_rst ? 0x40 : 0)); | |
1940 | ||
1941 | disable_input(sd); | |
1942 | ||
1943 | /* power */ | |
1944 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ | |
1945 | io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ | |
1946 | cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ | |
1947 | ||
1948 | /* video format */ | |
1949 | io_write_and_or(sd, 0x02, 0xf0, | |
1950 | pdata->alt_gamma << 3 | | |
1951 | pdata->op_656_range << 2 | | |
1952 | pdata->rgb_out << 1 | | |
1953 | pdata->alt_data_sat << 0); | |
1954 | io_write(sd, 0x03, pdata->op_format_sel); | |
1955 | io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); | |
1956 | io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | | |
1957 | pdata->insert_av_codes << 2 | | |
1958 | pdata->replicate_av_codes << 1 | | |
1959 | pdata->invert_cbcr << 0); | |
1960 | ||
1961 | /* TODO from platform data */ | |
1962 | cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ | |
1963 | io_write(sd, 0x06, 0xa6); /* positive VS and HS */ | |
f31b62e1 MK |
1964 | |
1965 | /* Adjust drive strength */ | |
1966 | io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | | |
1967 | pdata->dr_str_clk << 2 | | |
1968 | pdata->dr_str_sync); | |
1969 | ||
54450f59 HV |
1970 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ |
1971 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ | |
1972 | cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - | |
80939647 | 1973 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 | 1974 | cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - |
80939647 | 1975 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 HV |
1976 | cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution |
1977 | for digital formats */ | |
4a31a93a | 1978 | rep_write(sd, 0x76, 0xc0); /* SPA location for port B, C and D */ |
54450f59 HV |
1979 | |
1980 | /* TODO from platform data */ | |
1981 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ | |
1982 | ||
1983 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ | |
1984 | io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); | |
1985 | ||
54450f59 HV |
1986 | /* interrupts */ |
1987 | io_write(sd, 0x40, 0xc2); /* Configure INT1 */ | |
1988 | io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ | |
1989 | io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ | |
1990 | io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ | |
4a31a93a | 1991 | io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */ |
54450f59 HV |
1992 | |
1993 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); | |
1994 | } | |
1995 | ||
1996 | static void adv7604_unregister_clients(struct adv7604_state *state) | |
1997 | { | |
1998 | if (state->i2c_avlink) | |
1999 | i2c_unregister_device(state->i2c_avlink); | |
2000 | if (state->i2c_cec) | |
2001 | i2c_unregister_device(state->i2c_cec); | |
2002 | if (state->i2c_infoframe) | |
2003 | i2c_unregister_device(state->i2c_infoframe); | |
2004 | if (state->i2c_esdp) | |
2005 | i2c_unregister_device(state->i2c_esdp); | |
2006 | if (state->i2c_dpp) | |
2007 | i2c_unregister_device(state->i2c_dpp); | |
2008 | if (state->i2c_afe) | |
2009 | i2c_unregister_device(state->i2c_afe); | |
2010 | if (state->i2c_repeater) | |
2011 | i2c_unregister_device(state->i2c_repeater); | |
2012 | if (state->i2c_edid) | |
2013 | i2c_unregister_device(state->i2c_edid); | |
2014 | if (state->i2c_hdmi) | |
2015 | i2c_unregister_device(state->i2c_hdmi); | |
2016 | if (state->i2c_test) | |
2017 | i2c_unregister_device(state->i2c_test); | |
2018 | if (state->i2c_cp) | |
2019 | i2c_unregister_device(state->i2c_cp); | |
2020 | if (state->i2c_vdp) | |
2021 | i2c_unregister_device(state->i2c_vdp); | |
2022 | } | |
2023 | ||
2024 | static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, | |
2025 | u8 addr, u8 io_reg) | |
2026 | { | |
2027 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2028 | ||
2029 | if (addr) | |
2030 | io_write(sd, io_reg, addr << 1); | |
2031 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); | |
2032 | } | |
2033 | ||
2034 | static int adv7604_probe(struct i2c_client *client, | |
2035 | const struct i2c_device_id *id) | |
2036 | { | |
2037 | struct adv7604_state *state; | |
2038 | struct adv7604_platform_data *pdata = client->dev.platform_data; | |
2039 | struct v4l2_ctrl_handler *hdl; | |
2040 | struct v4l2_subdev *sd; | |
2041 | int err; | |
2042 | ||
2043 | /* Check if the adapter supports the needed features */ | |
2044 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
2045 | return -EIO; | |
2046 | v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", | |
2047 | client->addr << 1); | |
2048 | ||
c02b211d | 2049 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
54450f59 HV |
2050 | if (!state) { |
2051 | v4l_err(client, "Could not allocate adv7604_state memory!\n"); | |
2052 | return -ENOMEM; | |
2053 | } | |
2054 | ||
25a64ac9 MR |
2055 | /* initialize variables */ |
2056 | state->restart_stdi_once = true; | |
2057 | state->prev_input_status = ~0; | |
2058 | ||
54450f59 HV |
2059 | /* platform data */ |
2060 | if (!pdata) { | |
2061 | v4l_err(client, "No platform data!\n"); | |
c02b211d | 2062 | return -ENODEV; |
54450f59 HV |
2063 | } |
2064 | memcpy(&state->pdata, pdata, sizeof(state->pdata)); | |
2065 | ||
2066 | sd = &state->sd; | |
2067 | v4l2_i2c_subdev_init(sd, client, &adv7604_ops); | |
2068 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
2069 | state->connector_hdmi = pdata->connector_hdmi; | |
2070 | ||
2071 | /* i2c access to adv7604? */ | |
2072 | if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) { | |
2073 | v4l2_info(sd, "not an adv7604 on address 0x%x\n", | |
2074 | client->addr << 1); | |
c02b211d | 2075 | return -ENODEV; |
54450f59 HV |
2076 | } |
2077 | ||
2078 | /* control handlers */ | |
2079 | hdl = &state->hdl; | |
2080 | v4l2_ctrl_handler_init(hdl, 9); | |
2081 | ||
2082 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2083 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); | |
2084 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2085 | V4L2_CID_CONTRAST, 0, 255, 1, 128); | |
2086 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2087 | V4L2_CID_SATURATION, 0, 255, 1, 128); | |
2088 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2089 | V4L2_CID_HUE, 0, 128, 1, 0); | |
2090 | ||
2091 | /* private controls */ | |
2092 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, | |
4a31a93a | 2093 | V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0); |
54450f59 HV |
2094 | state->rgb_quantization_range_ctrl = |
2095 | v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, | |
2096 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, | |
2097 | 0, V4L2_DV_RGB_RANGE_AUTO); | |
54450f59 HV |
2098 | |
2099 | /* custom controls */ | |
2100 | state->analog_sampling_phase_ctrl = | |
2101 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); | |
54450f59 HV |
2102 | state->free_run_color_manual_ctrl = |
2103 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); | |
54450f59 HV |
2104 | state->free_run_color_ctrl = |
2105 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); | |
54450f59 HV |
2106 | |
2107 | sd->ctrl_handler = hdl; | |
2108 | if (hdl->error) { | |
2109 | err = hdl->error; | |
2110 | goto err_hdl; | |
2111 | } | |
8c0eadb8 HV |
2112 | state->detect_tx_5v_ctrl->is_private = true; |
2113 | state->rgb_quantization_range_ctrl->is_private = true; | |
2114 | state->analog_sampling_phase_ctrl->is_private = true; | |
2115 | state->free_run_color_manual_ctrl->is_private = true; | |
2116 | state->free_run_color_ctrl->is_private = true; | |
2117 | ||
54450f59 HV |
2118 | if (adv7604_s_detect_tx_5v_ctrl(sd)) { |
2119 | err = -ENODEV; | |
2120 | goto err_hdl; | |
2121 | } | |
2122 | ||
2123 | state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3); | |
2124 | state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4); | |
2125 | state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5); | |
2126 | state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6); | |
2127 | state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7); | |
2128 | state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8); | |
2129 | state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9); | |
2130 | state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa); | |
2131 | state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb); | |
2132 | state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc); | |
2133 | state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd); | |
2134 | state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe); | |
2135 | if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe || | |
2136 | !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe || | |
2137 | !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi || | |
2138 | !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) { | |
2139 | err = -ENOMEM; | |
2140 | v4l2_err(sd, "failed to create all i2c clients\n"); | |
2141 | goto err_i2c; | |
2142 | } | |
2143 | ||
2144 | /* work queues */ | |
2145 | state->work_queues = create_singlethread_workqueue(client->name); | |
2146 | if (!state->work_queues) { | |
2147 | v4l2_err(sd, "Could not create work queue\n"); | |
2148 | err = -ENOMEM; | |
2149 | goto err_i2c; | |
2150 | } | |
2151 | ||
2152 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, | |
2153 | adv7604_delayed_work_enable_hotplug); | |
2154 | ||
2155 | state->pad.flags = MEDIA_PAD_FL_SOURCE; | |
2156 | err = media_entity_init(&sd->entity, 1, &state->pad, 0); | |
2157 | if (err) | |
2158 | goto err_work_queues; | |
2159 | ||
2160 | err = adv7604_core_init(sd); | |
2161 | if (err) | |
2162 | goto err_entity; | |
2163 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, | |
2164 | client->addr << 1, client->adapter->name); | |
2165 | return 0; | |
2166 | ||
2167 | err_entity: | |
2168 | media_entity_cleanup(&sd->entity); | |
2169 | err_work_queues: | |
2170 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2171 | destroy_workqueue(state->work_queues); | |
2172 | err_i2c: | |
2173 | adv7604_unregister_clients(state); | |
2174 | err_hdl: | |
2175 | v4l2_ctrl_handler_free(hdl); | |
54450f59 HV |
2176 | return err; |
2177 | } | |
2178 | ||
2179 | /* ----------------------------------------------------------------------- */ | |
2180 | ||
2181 | static int adv7604_remove(struct i2c_client *client) | |
2182 | { | |
2183 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
2184 | struct adv7604_state *state = to_state(sd); | |
2185 | ||
2186 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2187 | destroy_workqueue(state->work_queues); | |
2188 | v4l2_device_unregister_subdev(sd); | |
2189 | media_entity_cleanup(&sd->entity); | |
2190 | adv7604_unregister_clients(to_state(sd)); | |
2191 | v4l2_ctrl_handler_free(sd->ctrl_handler); | |
54450f59 HV |
2192 | return 0; |
2193 | } | |
2194 | ||
2195 | /* ----------------------------------------------------------------------- */ | |
2196 | ||
2197 | static struct i2c_device_id adv7604_id[] = { | |
2198 | { "adv7604", 0 }, | |
2199 | { } | |
2200 | }; | |
2201 | MODULE_DEVICE_TABLE(i2c, adv7604_id); | |
2202 | ||
2203 | static struct i2c_driver adv7604_driver = { | |
2204 | .driver = { | |
2205 | .owner = THIS_MODULE, | |
2206 | .name = "adv7604", | |
2207 | }, | |
2208 | .probe = adv7604_probe, | |
2209 | .remove = adv7604_remove, | |
2210 | .id_table = adv7604_id, | |
2211 | }; | |
2212 | ||
2213 | module_i2c_driver(adv7604_driver); |