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[media] adv7604: Add support for asynchronous probing
[mirror_ubuntu-eoan-kernel.git] / drivers / media / i2c / adv7604.c
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54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
25764158 41#include <media/v4l2-dv-timings.h>
54450f59
HV		 42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
54450f59
HV		 56/*
57 **********************************************************************
58 *
59 * Arrays with configuration parameters for the ADV7604
60 *
61 **********************************************************************
62 */
63struct adv7604_state {
64 struct adv7604_platform_data pdata;
65 struct v4l2_subdev sd;
66 struct media_pad pad;
67 struct v4l2_ctrl_handler hdl;
4a31a93a 68 enum adv7604_input_port selected_input;
54450f59 69 struct v4l2_dv_timings timings;
4a31a93a
MR		 70 struct {
71 u8 edid[256];
72 u32 present;
73 unsigned blocks;
74 } edid;
dd08beb9 75 u16 spa_port_a[2];
54450f59
HV		 76 struct v4l2_fract aspect_ratio;
77 u32 rgb_quantization_range;
78 struct workqueue_struct *work_queues;
79 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 80 bool restart_stdi_once;
54450f59
HV		 81
82 /* i2c clients */
83 struct i2c_client *i2c_avlink;
84 struct i2c_client *i2c_cec;
85 struct i2c_client *i2c_infoframe;
86 struct i2c_client *i2c_esdp;
87 struct i2c_client *i2c_dpp;
88 struct i2c_client *i2c_afe;
89 struct i2c_client *i2c_repeater;
90 struct i2c_client *i2c_edid;
91 struct i2c_client *i2c_hdmi;
92 struct i2c_client *i2c_test;
93 struct i2c_client *i2c_cp;
94 struct i2c_client *i2c_vdp;
95
96 /* controls */
97 struct v4l2_ctrl *detect_tx_5v_ctrl;
98 struct v4l2_ctrl *analog_sampling_phase_ctrl;
99 struct v4l2_ctrl *free_run_color_manual_ctrl;
100 struct v4l2_ctrl *free_run_color_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102};
103
104/* Supported CEA and DMT timings */
105static const struct v4l2_dv_timings adv7604_timings[] = {
106 V4L2_DV_BT_CEA_720X480P59_94,
107 V4L2_DV_BT_CEA_720X576P50,
108 V4L2_DV_BT_CEA_1280X720P24,
109 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 110 V4L2_DV_BT_CEA_1280X720P50,
111 V4L2_DV_BT_CEA_1280X720P60,
112 V4L2_DV_BT_CEA_1920X1080P24,
113 V4L2_DV_BT_CEA_1920X1080P25,
114 V4L2_DV_BT_CEA_1920X1080P30,
115 V4L2_DV_BT_CEA_1920X1080P50,
116 V4L2_DV_BT_CEA_1920X1080P60,
117
ccbd5bc4 118 /* sorted by DMT ID */
54450f59
HV		 119 V4L2_DV_BT_DMT_640X350P85,
120 V4L2_DV_BT_DMT_640X400P85,
121 V4L2_DV_BT_DMT_720X400P85,
122 V4L2_DV_BT_DMT_640X480P60,
123 V4L2_DV_BT_DMT_640X480P72,
124 V4L2_DV_BT_DMT_640X480P75,
125 V4L2_DV_BT_DMT_640X480P85,
126 V4L2_DV_BT_DMT_800X600P56,
127 V4L2_DV_BT_DMT_800X600P60,
128 V4L2_DV_BT_DMT_800X600P72,
129 V4L2_DV_BT_DMT_800X600P75,
130 V4L2_DV_BT_DMT_800X600P85,
131 V4L2_DV_BT_DMT_848X480P60,
132 V4L2_DV_BT_DMT_1024X768P60,
133 V4L2_DV_BT_DMT_1024X768P70,
134 V4L2_DV_BT_DMT_1024X768P75,
135 V4L2_DV_BT_DMT_1024X768P85,
136 V4L2_DV_BT_DMT_1152X864P75,
137 V4L2_DV_BT_DMT_1280X768P60_RB,
138 V4L2_DV_BT_DMT_1280X768P60,
139 V4L2_DV_BT_DMT_1280X768P75,
140 V4L2_DV_BT_DMT_1280X768P85,
141 V4L2_DV_BT_DMT_1280X800P60_RB,
142 V4L2_DV_BT_DMT_1280X800P60,
143 V4L2_DV_BT_DMT_1280X800P75,
144 V4L2_DV_BT_DMT_1280X800P85,
145 V4L2_DV_BT_DMT_1280X960P60,
146 V4L2_DV_BT_DMT_1280X960P85,
147 V4L2_DV_BT_DMT_1280X1024P60,
148 V4L2_DV_BT_DMT_1280X1024P75,
149 V4L2_DV_BT_DMT_1280X1024P85,
150 V4L2_DV_BT_DMT_1360X768P60,
151 V4L2_DV_BT_DMT_1400X1050P60_RB,
152 V4L2_DV_BT_DMT_1400X1050P60,
153 V4L2_DV_BT_DMT_1400X1050P75,
154 V4L2_DV_BT_DMT_1400X1050P85,
155 V4L2_DV_BT_DMT_1440X900P60_RB,
156 V4L2_DV_BT_DMT_1440X900P60,
157 V4L2_DV_BT_DMT_1600X1200P60,
158 V4L2_DV_BT_DMT_1680X1050P60_RB,
159 V4L2_DV_BT_DMT_1680X1050P60,
160 V4L2_DV_BT_DMT_1792X1344P60,
161 V4L2_DV_BT_DMT_1856X1392P60,
162 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 163 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 164 V4L2_DV_BT_DMT_1366X768P60,
165 V4L2_DV_BT_DMT_1920X1080P60,
166 { },
167};
168
ccbd5bc4
HV		 169struct adv7604_video_standards {
170 struct v4l2_dv_timings timings;
171 u8 vid_std;
172 u8 v_freq;
173};
174
175/* sorted by number of lines */
176static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
177 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
178 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
179 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
180 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
181 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
182 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
183 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
184 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
185 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
186 /* TODO add 1920x1080P60_RB (CVT timing) */
187 { },
188};
189
190/* sorted by number of lines */
191static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
192 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
207 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
208 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
209 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
211 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
212 /* TODO add 1600X1200P60_RB (not a DMT timing) */
213 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
214 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
215 { },
216};
217
218/* sorted by number of lines */
219static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
220 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
221 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
222 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
223 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
224 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
225 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
226 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
227 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
228 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
229 { },
230};
231
232/* sorted by number of lines */
233static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
234 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
247 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
249 { },
250};
251
54450f59
HV		 252/* ----------------------------------------------------------------------- */
253
254static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
255{
256 return container_of(sd, struct adv7604_state, sd);
257}
258
259static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
260{
261 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
262}
263
264static inline unsigned hblanking(const struct v4l2_bt_timings *t)
265{
eacf8f9a 266 return V4L2_DV_BT_BLANKING_WIDTH(t);
54450f59
HV		 267}
268
269static inline unsigned htotal(const struct v4l2_bt_timings *t)
270{
eacf8f9a 271 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 272}
273
274static inline unsigned vblanking(const struct v4l2_bt_timings *t)
275{
eacf8f9a 276 return V4L2_DV_BT_BLANKING_HEIGHT(t);
54450f59
HV		 277}
278
279static inline unsigned vtotal(const struct v4l2_bt_timings *t)
280{
eacf8f9a 281 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 282}
283
284/* ----------------------------------------------------------------------- */
285
286static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
287 u8 command, bool check)
288{
289 union i2c_smbus_data data;
290
291 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
292 I2C_SMBUS_READ, command,
293 I2C_SMBUS_BYTE_DATA, &data))
294 return data.byte;
295 if (check)
296 v4l_err(client, "error reading %02x, %02x\n",
297 client->addr, command);
298 return -EIO;
299}
300
301static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
302{
303 return adv_smbus_read_byte_data_check(client, command, true);
304}
305
306static s32 adv_smbus_write_byte_data(struct i2c_client *client,
307 u8 command, u8 value)
308{
309 union i2c_smbus_data data;
310 int err;
311 int i;
312
313 data.byte = value;
314 for (i = 0; i < 3; i++) {
315 err = i2c_smbus_xfer(client->adapter, client->addr,
316 client->flags,
317 I2C_SMBUS_WRITE, command,
318 I2C_SMBUS_BYTE_DATA, &data);
319 if (!err)
320 break;
321 }
322 if (err < 0)
323 v4l_err(client, "error writing %02x, %02x, %02x\n",
324 client->addr, command, value);
325 return err;
326}
327
328static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
329 u8 command, unsigned length, const u8 *values)
330{
331 union i2c_smbus_data data;
332
333 if (length > I2C_SMBUS_BLOCK_MAX)
334 length = I2C_SMBUS_BLOCK_MAX;
335 data.block[0] = length;
336 memcpy(data.block + 1, values, length);
337 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
338 I2C_SMBUS_WRITE, command,
339 I2C_SMBUS_I2C_BLOCK_DATA, &data);
340}
341
342/* ----------------------------------------------------------------------- */
343
344static inline int io_read(struct v4l2_subdev *sd, u8 reg)
345{
346 struct i2c_client *client = v4l2_get_subdevdata(sd);
347
348 return adv_smbus_read_byte_data(client, reg);
349}
350
351static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
352{
353 struct i2c_client *client = v4l2_get_subdevdata(sd);
354
355 return adv_smbus_write_byte_data(client, reg, val);
356}
357
358static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
359{
360 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
361}
362
363static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
364{
365 struct adv7604_state *state = to_state(sd);
366
367 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
368}
369
370static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
371{
372 struct adv7604_state *state = to_state(sd);
373
374 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
375}
376
377static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
378{
379 struct adv7604_state *state = to_state(sd);
380
381 return adv_smbus_read_byte_data(state->i2c_cec, reg);
382}
383
384static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
385{
386 struct adv7604_state *state = to_state(sd);
387
388 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
389}
390
391static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
392{
393 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
394}
395
396static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
397{
398 struct adv7604_state *state = to_state(sd);
399
400 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
401}
402
403static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
404{
405 struct adv7604_state *state = to_state(sd);
406
407 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
408}
409
410static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
411{
412 struct adv7604_state *state = to_state(sd);
413
414 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
415}
416
417static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
418{
419 struct adv7604_state *state = to_state(sd);
420
421 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
422}
423
424static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
425{
426 struct adv7604_state *state = to_state(sd);
427
428 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
429}
430
431static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
432{
433 struct adv7604_state *state = to_state(sd);
434
435 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
436}
437
438static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
439{
440 struct adv7604_state *state = to_state(sd);
441
442 return adv_smbus_read_byte_data(state->i2c_afe, reg);
443}
444
445static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
446{
447 struct adv7604_state *state = to_state(sd);
448
449 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
450}
451
452static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
453{
454 struct adv7604_state *state = to_state(sd);
455
456 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
457}
458
459static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
460{
461 struct adv7604_state *state = to_state(sd);
462
463 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
464}
465
466static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
467{
468 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
469}
470
471static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
472{
473 struct adv7604_state *state = to_state(sd);
474
475 return adv_smbus_read_byte_data(state->i2c_edid, reg);
476}
477
478static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
479{
480 struct adv7604_state *state = to_state(sd);
481
482 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
483}
484
485static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
486{
487 struct adv7604_state *state = to_state(sd);
488 struct i2c_client *client = state->i2c_edid;
489 u8 msgbuf0[1] = { 0 };
490 u8 msgbuf1[256];
09f29673
S		 491 struct i2c_msg msg[2] = {
492 {
493 .addr = client->addr,
494 .len = 1,
495 .buf = msgbuf0
496 },
497 {
498 .addr = client->addr,
499 .flags = I2C_M_RD,
500 .len = len,
501 .buf = msgbuf1
502 },
503 };
54450f59
HV		 504
505 if (i2c_transfer(client->adapter, msg, 2) < 0)
506 return -EIO;
507 memcpy(val, msgbuf1, len);
508 return 0;
509}
510
54450f59
HV		 511static inline int edid_write_block(struct v4l2_subdev *sd,
512 unsigned len, const u8 *val)
513{
54450f59
HV		 514 struct adv7604_state *state = to_state(sd);
515 int err = 0;
516 int i;
517
518 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
519
54450f59
HV		 520 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
521 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
522 I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 523 return err;
524}
54450f59 525
dd08beb9
MR		 526static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
527{
528 struct delayed_work *dwork = to_delayed_work(work);
529 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
530 delayed_work_enable_hotplug);
531 struct v4l2_subdev *sd = &state->sd;
54450f59 532
dd08beb9 533 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 534
dd08beb9 535 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
54450f59
HV		 536}
537
538static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
539{
540 struct adv7604_state *state = to_state(sd);
541
542 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
543}
544
545static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
546{
547 struct adv7604_state *state = to_state(sd);
548
549 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
550}
551
4a31a93a
MR		 552static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
553{
554 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
555}
556
54450f59
HV		 557static inline int test_read(struct v4l2_subdev *sd, u8 reg)
558{
559 struct adv7604_state *state = to_state(sd);
560
561 return adv_smbus_read_byte_data(state->i2c_test, reg);
562}
563
564static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
565{
566 struct adv7604_state *state = to_state(sd);
567
568 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
569}
570
571static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
572{
573 struct adv7604_state *state = to_state(sd);
574
575 return adv_smbus_read_byte_data(state->i2c_cp, reg);
576}
577
578static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
579{
580 struct adv7604_state *state = to_state(sd);
581
582 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
583}
584
585static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
586{
587 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
588}
589
590static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
591{
592 struct adv7604_state *state = to_state(sd);
593
594 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
595}
596
597static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598{
599 struct adv7604_state *state = to_state(sd);
600
601 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
602}
603
604/* ----------------------------------------------------------------------- */
605
4a31a93a
MR		 606static inline bool is_analog_input(struct v4l2_subdev *sd)
607{
608 struct adv7604_state *state = to_state(sd);
609
610 return state->selected_input == ADV7604_INPUT_VGA_RGB ||
611 state->selected_input == ADV7604_INPUT_VGA_COMP;
612}
613
614static inline bool is_digital_input(struct v4l2_subdev *sd)
615{
616 struct adv7604_state *state = to_state(sd);
617
618 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
619 state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
620 state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
621 state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
622}
623
624/* ----------------------------------------------------------------------- */
625
54450f59
HV		 626#ifdef CONFIG_VIDEO_ADV_DEBUG
627static void adv7604_inv_register(struct v4l2_subdev *sd)
628{
629 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
630 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
631 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
632 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
633 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
634 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
635 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
636 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
637 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
638 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
639 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
640 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
641 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
642}
643
644static int adv7604_g_register(struct v4l2_subdev *sd,
645 struct v4l2_dbg_register *reg)
646{
54450f59
HV		 647 reg->size = 1;
648 switch (reg->reg >> 8) {
649 case 0:
650 reg->val = io_read(sd, reg->reg & 0xff);
651 break;
652 case 1:
653 reg->val = avlink_read(sd, reg->reg & 0xff);
654 break;
655 case 2:
656 reg->val = cec_read(sd, reg->reg & 0xff);
657 break;
658 case 3:
659 reg->val = infoframe_read(sd, reg->reg & 0xff);
660 break;
661 case 4:
662 reg->val = esdp_read(sd, reg->reg & 0xff);
663 break;
664 case 5:
665 reg->val = dpp_read(sd, reg->reg & 0xff);
666 break;
667 case 6:
668 reg->val = afe_read(sd, reg->reg & 0xff);
669 break;
670 case 7:
671 reg->val = rep_read(sd, reg->reg & 0xff);
672 break;
673 case 8:
674 reg->val = edid_read(sd, reg->reg & 0xff);
675 break;
676 case 9:
677 reg->val = hdmi_read(sd, reg->reg & 0xff);
678 break;
679 case 0xa:
680 reg->val = test_read(sd, reg->reg & 0xff);
681 break;
682 case 0xb:
683 reg->val = cp_read(sd, reg->reg & 0xff);
684 break;
685 case 0xc:
686 reg->val = vdp_read(sd, reg->reg & 0xff);
687 break;
688 default:
689 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
690 adv7604_inv_register(sd);
691 break;
692 }
693 return 0;
694}
695
696static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 697 const struct v4l2_dbg_register *reg)
54450f59 698{
1577461b
HV		 699 u8 val = reg->val & 0xff;
700
54450f59
HV		 701 switch (reg->reg >> 8) {
702 case 0:
1577461b 703 io_write(sd, reg->reg & 0xff, val);
54450f59
HV		 704 break;
705 case 1:
1577461b 706 avlink_write(sd, reg->reg & 0xff, val);
54450f59
HV		 707 break;
708 case 2:
1577461b 709 cec_write(sd, reg->reg & 0xff, val);
54450f59
HV		 710 break;
711 case 3:
1577461b 712 infoframe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 713 break;
714 case 4:
1577461b 715 esdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 716 break;
717 case 5:
1577461b 718 dpp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 719 break;
720 case 6:
1577461b 721 afe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 722 break;
723 case 7:
1577461b 724 rep_write(sd, reg->reg & 0xff, val);
54450f59
HV		 725 break;
726 case 8:
1577461b 727 edid_write(sd, reg->reg & 0xff, val);
54450f59
HV		 728 break;
729 case 9:
1577461b 730 hdmi_write(sd, reg->reg & 0xff, val);
54450f59
HV		 731 break;
732 case 0xa:
1577461b 733 test_write(sd, reg->reg & 0xff, val);
54450f59
HV		 734 break;
735 case 0xb:
1577461b 736 cp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 737 break;
738 case 0xc:
1577461b 739 vdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 740 break;
741 default:
742 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
743 adv7604_inv_register(sd);
744 break;
745 }
746 return 0;
747}
748#endif
749
750static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
751{
752 struct adv7604_state *state = to_state(sd);
4a31a93a 753 u8 reg_io_6f = io_read(sd, 0x6f);
54450f59 754
54450f59 755 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
4a31a93a
MR		 756 ((reg_io_6f & 0x10) >> 4) |
757 ((reg_io_6f & 0x08) >> 2) |
758 (reg_io_6f & 0x04) |
759 ((reg_io_6f & 0x02) << 2));
54450f59
HV		 760}
761
ccbd5bc4
HV		 762static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
763 u8 prim_mode,
764 const struct adv7604_video_standards *predef_vid_timings,
765 const struct v4l2_dv_timings *timings)
766{
ccbd5bc4
HV		 767 int i;
768
769 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 770 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 771 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 772 continue;
773 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
774 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
775 prim_mode); /* v_freq and prim mode */
776 return 0;
777 }
778
779 return -1;
780}
781
782static int configure_predefined_video_timings(struct v4l2_subdev *sd,
783 struct v4l2_dv_timings *timings)
54450f59 784{
ccbd5bc4
HV		 785 struct adv7604_state *state = to_state(sd);
786 int err;
787
788 v4l2_dbg(1, debug, sd, "%s", __func__);
789
790 /* reset to default values */
791 io_write(sd, 0x16, 0x43);
792 io_write(sd, 0x17, 0x5a);
793 /* disable embedded syncs for auto graphics mode */
794 cp_write_and_or(sd, 0x81, 0xef, 0x00);
795 cp_write(sd, 0x8f, 0x00);
796 cp_write(sd, 0x90, 0x00);
797 cp_write(sd, 0xa2, 0x00);
798 cp_write(sd, 0xa3, 0x00);
799 cp_write(sd, 0xa4, 0x00);
800 cp_write(sd, 0xa5, 0x00);
801 cp_write(sd, 0xa6, 0x00);
802 cp_write(sd, 0xa7, 0x00);
803 cp_write(sd, 0xab, 0x00);
804 cp_write(sd, 0xac, 0x00);
805
4a31a93a 806 if (is_analog_input(sd)) {
ccbd5bc4
HV		 807 err = find_and_set_predefined_video_timings(sd,
808 0x01, adv7604_prim_mode_comp, timings);
809 if (err)
810 err = find_and_set_predefined_video_timings(sd,
811 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 812 } else if (is_digital_input(sd)) {
ccbd5bc4
HV		 813 err = find_and_set_predefined_video_timings(sd,
814 0x05, adv7604_prim_mode_hdmi_comp, timings);
815 if (err)
816 err = find_and_set_predefined_video_timings(sd,
817 0x06, adv7604_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 818 } else {
819 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
820 __func__, state->selected_input);
ccbd5bc4 821 err = -1;
ccbd5bc4
HV		 822 }
823
824
825 return err;
826}
827
828static void configure_custom_video_timings(struct v4l2_subdev *sd,
829 const struct v4l2_bt_timings *bt)
830{
831 struct adv7604_state *state = to_state(sd);
54450f59 832 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 833 u32 width = htotal(bt);
834 u32 height = vtotal(bt);
835 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
836 u16 cp_start_eav = width - bt->hfrontporch;
837 u16 cp_start_vbi = height - bt->vfrontporch;
838 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
839 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
840 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
841 const u8 pll[2] = {
842 0xc0 | ((width >> 8) & 0x1f),
843 width & 0xff
844 };
54450f59
HV		 845
846 v4l2_dbg(2, debug, sd, "%s\n", __func__);
847
4a31a93a 848 if (is_analog_input(sd)) {
ccbd5bc4
HV		 849 /* auto graphics */
850 io_write(sd, 0x00, 0x07); /* video std */
851 io_write(sd, 0x01, 0x02); /* prim mode */
852 /* enable embedded syncs for auto graphics mode */
853 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 854
ccbd5bc4 855 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 856 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
857 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
4a31a93a 858 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
54450f59 859 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 860
861 /* active video - horizontal timing */
54450f59 862 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 863 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 864 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 865 cp_write(sd, 0xa4, cp_start_eav & 0xff);
866
867 /* active video - vertical timing */
54450f59 868 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 869 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 870 ((cp_end_vbi >> 8) & 0xf));
54450f59 871 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 872 } else if (is_digital_input(sd)) {
ccbd5bc4 873 /* set default prim_mode/vid_std for HDMI
39c1cb2b 874 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 875 io_write(sd, 0x00, 0x02); /* video std */
876 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 877 } else {
878 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
879 __func__, state->selected_input);
54450f59 880 }
54450f59 881
ccbd5bc4
HV		 882 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
883 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
884 cp_write(sd, 0xab, (height >> 4) & 0xff);
885 cp_write(sd, 0xac, (height & 0x0f) << 4);
886}
54450f59 887
5c6c6349
MR		 888static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
889{
890 struct adv7604_state *state = to_state(sd);
891 u8 offset_buf[4];
892
893 if (auto_offset) {
894 offset_a = 0x3ff;
895 offset_b = 0x3ff;
896 offset_c = 0x3ff;
897 }
898
899 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
900 __func__, auto_offset ? "Auto" : "Manual",
901 offset_a, offset_b, offset_c);
902
903 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
904 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
905 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
906 offset_buf[3] = offset_c & 0x0ff;
907
908 /* Registers must be written in this order with no i2c access in between */
909 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
910 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
911}
912
913static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
914{
915 struct adv7604_state *state = to_state(sd);
916 u8 gain_buf[4];
917 u8 gain_man = 1;
918 u8 agc_mode_man = 1;
919
920 if (auto_gain) {
921 gain_man = 0;
922 agc_mode_man = 0;
923 gain_a = 0x100;
924 gain_b = 0x100;
925 gain_c = 0x100;
926 }
927
928 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
929 __func__, auto_gain ? "Auto" : "Manual",
930 gain_a, gain_b, gain_c);
931
932 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
933 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
934 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
935 gain_buf[3] = ((gain_c & 0x0ff));
936
937 /* Registers must be written in this order with no i2c access in between */
938 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
939 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
940}
941
54450f59
HV		 942static void set_rgb_quantization_range(struct v4l2_subdev *sd)
943{
944 struct adv7604_state *state = to_state(sd);
5c6c6349
MR		 945 bool rgb_output = io_read(sd, 0x02) & 0x02;
946 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
947
948 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
949 __func__, state->rgb_quantization_range,
950 rgb_output, hdmi_signal);
54450f59 951
5c6c6349
MR		 952 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
953 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 954
54450f59
HV		 955 switch (state->rgb_quantization_range) {
956 case V4L2_DV_RGB_RANGE_AUTO:
9833239e
MR		 957 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
958 /* Receiving analog RGB signal
959 * Set RGB full range (0-255) */
960 io_write_and_or(sd, 0x02, 0x0f, 0x10);
961 break;
962 }
963
964 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
965 /* Receiving analog YPbPr signal
966 * Set automode */
967 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
968 break;
969 }
970
5c6c6349 971 if (hdmi_signal) {
9833239e
MR		 972 /* Receiving HDMI signal
973 * Set automode */
6b0d5d34 974 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
9833239e
MR		 975 break;
976 }
977
978 /* Receiving DVI-D signal
979 * ADV7604 selects RGB limited range regardless of
980 * input format (CE/IT) in automatic mode */
981 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
982 /* RGB limited range (16-235) */
983 io_write_and_or(sd, 0x02, 0x0f, 0x00);
984 } else {
985 /* RGB full range (0-255) */
986 io_write_and_or(sd, 0x02, 0x0f, 0x10);
5c6c6349
MR		 987
988 if (is_digital_input(sd) && rgb_output) {
989 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
990 } else {
991 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
992 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
993 }
54450f59
HV		 994 }
995 break;
996 case V4L2_DV_RGB_RANGE_LIMITED:
d261e842
MR		 997 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
998 /* YCrCb limited range (16-235) */
999 io_write_and_or(sd, 0x02, 0x0f, 0x20);
5c6c6349 1000 break;
d261e842 1001 }
5c6c6349
MR		 1002
1003 /* RGB limited range (16-235) */
1004 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1005
54450f59
HV		 1006 break;
1007 case V4L2_DV_RGB_RANGE_FULL:
d261e842
MR		 1008 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
1009 /* YCrCb full range (0-255) */
1010 io_write_and_or(sd, 0x02, 0x0f, 0x60);
5c6c6349
MR		 1011 break;
1012 }
1013
1014 /* RGB full range (0-255) */
1015 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1016
1017 if (is_analog_input(sd) || hdmi_signal)
1018 break;
1019
1020 /* Adjust gain/offset for DVI-D signals only */
1021 if (rgb_output) {
1022 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1023 } else {
5c6c6349
MR		 1024 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1025 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1026 }
54450f59
HV		 1027 break;
1028 }
1029}
1030
54450f59
HV		 1031static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1032{
1033 struct v4l2_subdev *sd = to_sd(ctrl);
1034 struct adv7604_state *state = to_state(sd);
1035
1036 switch (ctrl->id) {
1037 case V4L2_CID_BRIGHTNESS:
1038 cp_write(sd, 0x3c, ctrl->val);
1039 return 0;
1040 case V4L2_CID_CONTRAST:
1041 cp_write(sd, 0x3a, ctrl->val);
1042 return 0;
1043 case V4L2_CID_SATURATION:
1044 cp_write(sd, 0x3b, ctrl->val);
1045 return 0;
1046 case V4L2_CID_HUE:
1047 cp_write(sd, 0x3d, ctrl->val);
1048 return 0;
1049 case V4L2_CID_DV_RX_RGB_RANGE:
1050 state->rgb_quantization_range = ctrl->val;
1051 set_rgb_quantization_range(sd);
1052 return 0;
1053 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1054 /* Set the analog sampling phase. This is needed to find the
1055 best sampling phase for analog video: an application or
1056 driver has to try a number of phases and analyze the picture
1057 quality before settling on the best performing phase. */
1058 afe_write(sd, 0xc8, ctrl->val);
1059 return 0;
1060 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1061 /* Use the default blue color for free running mode,
1062 or supply your own. */
1063 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1064 return 0;
1065 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1066 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1067 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1068 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1069 return 0;
1070 }
1071 return -EINVAL;
1072}
1073
54450f59
HV		 1074/* ----------------------------------------------------------------------- */
1075
1076static inline bool no_power(struct v4l2_subdev *sd)
1077{
1078 /* Entire chip or CP powered off */
1079 return io_read(sd, 0x0c) & 0x24;
1080}
1081
1082static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1083{
4a31a93a
MR		 1084 struct adv7604_state *state = to_state(sd);
1085
1086 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1087}
1088
1089static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1090{
1091 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1092}
1093
bb88f325
MB		 1094static inline bool is_hdmi(struct v4l2_subdev *sd)
1095{
1096 return hdmi_read(sd, 0x05) & 0x80;
1097}
1098
54450f59
HV		 1099static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1100{
1101 /* TODO channel 2 */
1102 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1103}
1104
1105static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1106{
1107 /* TODO channel 2 */
1108 return !(cp_read(sd, 0xb1) & 0x80);
1109}
1110
1111static inline bool no_signal(struct v4l2_subdev *sd)
1112{
54450f59
HV		 1113 bool ret;
1114
1115 ret = no_power(sd);
1116
1117 ret |= no_lock_stdi(sd);
1118 ret |= no_lock_sspd(sd);
1119
4a31a93a 1120 if (is_digital_input(sd)) {
54450f59
HV		 1121 ret |= no_lock_tmds(sd);
1122 ret |= no_signal_tmds(sd);
1123 }
1124
1125 return ret;
1126}
1127
1128static inline bool no_lock_cp(struct v4l2_subdev *sd)
1129{
1130 /* CP has detected a non standard number of lines on the incoming
1131 video compared to what it is configured to receive by s_dv_timings */
1132 return io_read(sd, 0x12) & 0x01;
1133}
1134
1135static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1136{
54450f59
HV		 1137 *status = 0;
1138 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1139 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1140 if (no_lock_cp(sd))
4a31a93a 1141 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1142
1143 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1144
1145 return 0;
1146}
1147
1148/* ----------------------------------------------------------------------- */
1149
54450f59
HV		 1150struct stdi_readback {
1151 u16 bl, lcf, lcvs;
1152 u8 hs_pol, vs_pol;
1153 bool interlaced;
1154};
1155
1156static int stdi2dv_timings(struct v4l2_subdev *sd,
1157 struct stdi_readback *stdi,
1158 struct v4l2_dv_timings *timings)
1159{
1160 struct adv7604_state *state = to_state(sd);
1161 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1162 u32 pix_clk;
1163 int i;
1164
1165 for (i = 0; adv7604_timings[i].bt.height; i++) {
1166 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1167 continue;
1168 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1169 continue;
1170
1171 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1172
1173 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1174 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1175 *timings = adv7604_timings[i];
1176 return 0;
1177 }
1178 }
1179
1180 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1181 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1182 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1183 timings))
1184 return 0;
1185 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1186 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1187 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1188 state->aspect_ratio, timings))
1189 return 0;
1190
ccbd5bc4
HV		 1191 v4l2_dbg(2, debug, sd,
1192 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1193 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1194 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1195 return -1;
1196}
1197
1198static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1199{
1200 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1201 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1202 return -1;
1203 }
1204
1205 /* read STDI */
1206 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1207 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1208 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1209 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1210
1211 /* read SSPD */
1212 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1213 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1214 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1215 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1216 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1217 } else {
1218 stdi->hs_pol = 'x';
1219 stdi->vs_pol = 'x';
1220 }
1221
1222 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1223 v4l2_dbg(2, debug, sd,
1224 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1225 return -1;
1226 }
1227
1228 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1229 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1230 memset(stdi, 0, sizeof(struct stdi_readback));
1231 return -1;
1232 }
1233
1234 v4l2_dbg(2, debug, sd,
1235 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1236 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1237 stdi->hs_pol, stdi->vs_pol,
1238 stdi->interlaced ? "interlaced" : "progressive");
1239
1240 return 0;
1241}
1242
1243static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1244 struct v4l2_enum_dv_timings *timings)
1245{
1246 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1247 return -EINVAL;
1248 memset(timings->reserved, 0, sizeof(timings->reserved));
1249 timings->timings = adv7604_timings[timings->index];
1250 return 0;
1251}
1252
1253static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1254 struct v4l2_dv_timings_cap *cap)
1255{
54450f59
HV		 1256 cap->type = V4L2_DV_BT_656_1120;
1257 cap->bt.max_width = 1920;
1258 cap->bt.max_height = 1200;
fe9c2564 1259 cap->bt.min_pixelclock = 25000000;
4a31a93a 1260 if (is_digital_input(sd))
54450f59
HV		 1261 cap->bt.max_pixelclock = 225000000;
1262 else
1263 cap->bt.max_pixelclock = 170000000;
1264 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1265 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1266 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1267 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1268 return 0;
1269}
1270
1271/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1272 if the format is listed in adv7604_timings[] */
1273static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1274 struct v4l2_dv_timings *timings)
1275{
54450f59
HV		 1276 int i;
1277
1278 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1279 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
4a31a93a 1280 is_digital_input(sd) ? 250000 : 1000000)) {
54450f59
HV		 1281 *timings = adv7604_timings[i];
1282 break;
1283 }
1284 }
1285}
1286
1287static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1288 struct v4l2_dv_timings *timings)
1289{
1290 struct adv7604_state *state = to_state(sd);
1291 struct v4l2_bt_timings *bt = &timings->bt;
1292 struct stdi_readback stdi;
1293
1294 if (!timings)
1295 return -EINVAL;
1296
1297 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1298
1299 if (no_signal(sd)) {
1e0b9156 1300 state->restart_stdi_once = true;
54450f59
HV		 1301 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1302 return -ENOLINK;
1303 }
1304
1305 /* read STDI */
1306 if (read_stdi(sd, &stdi)) {
1307 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1308 return -ENOLINK;
1309 }
1310 bt->interlaced = stdi.interlaced ?
1311 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1312
4a31a93a 1313 if (is_digital_input(sd)) {
bb88f325
MB		 1314 uint32_t freq;
1315
54450f59
HV		 1316 timings->type = V4L2_DV_BT_656_1120;
1317
1318 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1319 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
bb88f325 1320 freq = (hdmi_read(sd, 0x06) * 1000000) +
54450f59 1321 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
bb88f325
MB		 1322 if (is_hdmi(sd)) {
1323 /* adjust for deep color mode */
1324 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1325
1326 freq = freq * 8 / bits_per_channel;
1327 }
1328 bt->pixelclock = freq;
54450f59
HV		 1329 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1330 hdmi_read(sd, 0x21);
1331 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1332 hdmi_read(sd, 0x23);
1333 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1334 hdmi_read(sd, 0x25);
1335 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1336 hdmi_read(sd, 0x2b)) / 2;
1337 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1338 hdmi_read(sd, 0x2f)) / 2;
1339 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1340 hdmi_read(sd, 0x33)) / 2;
1341 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1342 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1343 if (bt->interlaced == V4L2_DV_INTERLACED) {
1344 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1345 hdmi_read(sd, 0x0c);
1346 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1347 hdmi_read(sd, 0x2d)) / 2;
1348 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1349 hdmi_read(sd, 0x31)) / 2;
1350 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1351 hdmi_read(sd, 0x35)) / 2;
1352 }
1353 adv7604_fill_optional_dv_timings_fields(sd, timings);
1354 } else {
1355 /* find format
80939647 1356 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1357 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1358 */
1359 if (!stdi2dv_timings(sd, &stdi, timings))
1360 goto found;
1361 stdi.lcvs += 1;
1362 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1363 if (!stdi2dv_timings(sd, &stdi, timings))
1364 goto found;
1365 stdi.lcvs -= 2;
1366 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1367 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1368 /*
1369 * The STDI block may measure wrong values, especially
1370 * for lcvs and lcf. If the driver can not find any
1371 * valid timing, the STDI block is restarted to measure
1372 * the video timings again. The function will return an
1373 * error, but the restart of STDI will generate a new
1374 * STDI interrupt and the format detection process will
1375 * restart.
1376 */
1377 if (state->restart_stdi_once) {
1378 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1379 /* TODO restart STDI for Sync Channel 2 */
1380 /* enter one-shot mode */
1381 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1382 /* trigger STDI restart */
1383 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1384 /* reset to continuous mode */
1385 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1386 state->restart_stdi_once = false;
1387 return -ENOLINK;
1388 }
54450f59
HV		 1389 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1390 return -ERANGE;
1391 }
cf9afb1d 1392 state->restart_stdi_once = true;
54450f59
HV		 1393 }
1394found:
1395
1396 if (no_signal(sd)) {
1397 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1398 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1399 return -ENOLINK;
1400 }
1401
4a31a93a
MR		 1402 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1403 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1404 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1405 __func__, (u32)bt->pixelclock);
1406 return -ERANGE;
1407 }
1408
1409 if (debug > 1)
11d034c8
HV		 1410 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1411 timings, true);
54450f59
HV		 1412
1413 return 0;
1414}
1415
1416static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1417 struct v4l2_dv_timings *timings)
1418{
1419 struct adv7604_state *state = to_state(sd);
1420 struct v4l2_bt_timings *bt;
ccbd5bc4 1421 int err;
54450f59
HV		 1422
1423 if (!timings)
1424 return -EINVAL;
1425
d48eb48c
MR		 1426 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1427 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1428 return 0;
1429 }
1430
54450f59
HV		 1431 bt = &timings->bt;
1432
4a31a93a
MR		 1433 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1434 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1435 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1436 __func__, (u32)bt->pixelclock);
1437 return -ERANGE;
1438 }
ccbd5bc4 1439
54450f59
HV		 1440 adv7604_fill_optional_dv_timings_fields(sd, timings);
1441
1442 state->timings = *timings;
1443
ccbd5bc4
HV		 1444 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1445
1446 /* Use prim_mode and vid_std when available */
1447 err = configure_predefined_video_timings(sd, timings);
1448 if (err) {
1449 /* custom settings when the video format
1450 does not have prim_mode/vid_std */
1451 configure_custom_video_timings(sd, bt);
1452 }
54450f59
HV		 1453
1454 set_rgb_quantization_range(sd);
1455
54450f59 1456 if (debug > 1)
11d034c8
HV		 1457 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1458 timings, true);
54450f59
HV		 1459 return 0;
1460}
1461
1462static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1463 struct v4l2_dv_timings *timings)
1464{
1465 struct adv7604_state *state = to_state(sd);
1466
1467 *timings = state->timings;
1468 return 0;
1469}
1470
6b0d5d34 1471static void enable_input(struct v4l2_subdev *sd)
54450f59 1472{
6b0d5d34
HV		 1473 struct adv7604_state *state = to_state(sd);
1474
4a31a93a 1475 if (is_analog_input(sd)) {
54450f59 1476 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1477 } else if (is_digital_input(sd)) {
4a31a93a 1478 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
54450f59
HV		 1479 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1480 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5474b983 1481 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
4a31a93a
MR		 1482 } else {
1483 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1484 __func__, state->selected_input);
54450f59
HV		 1485 }
1486}
1487
1488static void disable_input(struct v4l2_subdev *sd)
1489{
5474b983
MR		 1490 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */
1491 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1492 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
54450f59
HV		 1493 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1494}
1495
6b0d5d34 1496static void select_input(struct v4l2_subdev *sd)
54450f59 1497{
6b0d5d34 1498 struct adv7604_state *state = to_state(sd);
54450f59 1499
4a31a93a 1500 if (is_analog_input(sd)) {
54450f59
HV		 1501 /* reset ADI recommended settings for HDMI: */
1502 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1503 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1504 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1505 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1506 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1507 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1508 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1509 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1510 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1511 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1512 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1513 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1514
1515 afe_write(sd, 0x00, 0x08); /* power up ADC */
1516 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1517 afe_write(sd, 0xc8, 0x00); /* phase control */
1518
1519 /* set ADI recommended settings for digitizer */
1520 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1521 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1522 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1523 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1524 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1525 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1526 } else if (is_digital_input(sd)) {
1527 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1528
54450f59
HV		 1529 /* set ADI recommended settings for HDMI: */
1530 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1531 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1532 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1533 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1534 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1535 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1536 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1537 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1538 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1539 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1540 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1541 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1542
1543 afe_write(sd, 0x00, 0xff); /* power down ADC */
1544 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1545 afe_write(sd, 0xc8, 0x40); /* phase control */
1546
1547 /* reset ADI recommended settings for digitizer */
1548 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1549 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1550 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1551 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1552 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1553 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1554 } else {
1555 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1556 __func__, state->selected_input);
54450f59
HV		 1557 }
1558}
1559
1560static int adv7604_s_routing(struct v4l2_subdev *sd,
1561 u32 input, u32 output, u32 config)
1562{
1563 struct adv7604_state *state = to_state(sd);
1564
ff4f80fd
MR		 1565 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1566 __func__, input, state->selected_input);
1567
1568 if (input == state->selected_input)
1569 return 0;
54450f59 1570
4a31a93a 1571 state->selected_input = input;
54450f59
HV		 1572
1573 disable_input(sd);
1574
6b0d5d34 1575 select_input(sd);
54450f59 1576
6b0d5d34 1577 enable_input(sd);
54450f59
HV		 1578
1579 return 0;
1580}
1581
1582static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1583 enum v4l2_mbus_pixelcode *code)
1584{
1585 if (index)
1586 return -EINVAL;
1587 /* Good enough for now */
1588 *code = V4L2_MBUS_FMT_FIXED;
1589 return 0;
1590}
1591
1592static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1593 struct v4l2_mbus_framefmt *fmt)
1594{
1595 struct adv7604_state *state = to_state(sd);
1596
1597 fmt->width = state->timings.bt.width;
1598 fmt->height = state->timings.bt.height;
1599 fmt->code = V4L2_MBUS_FMT_FIXED;
1600 fmt->field = V4L2_FIELD_NONE;
1601 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1602 fmt->colorspace = (state->timings.bt.height <= 576) ?
1603 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1604 }
1605 return 0;
1606}
1607
1608static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1609{
f24d229c
MR		 1610 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1611 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1612 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1613 u8 fmt_change_digital;
1614 u8 fmt_change;
1615 u8 tx_5v;
1616
1617 if (irq_reg_0x43)
1618 io_write(sd, 0x44, irq_reg_0x43);
1619 if (irq_reg_0x70)
1620 io_write(sd, 0x71, irq_reg_0x70);
1621 if (irq_reg_0x6b)
1622 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1623
ff4f80fd
MR		 1624 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1625
54450f59 1626 /* format change */
f24d229c
MR		 1627 fmt_change = irq_reg_0x43 & 0x98;
1628 fmt_change_digital = is_digital_input(sd) ? (irq_reg_0x6b & 0xc0) : 0;
14d03233 1629
54450f59
HV		 1630 if (fmt_change || fmt_change_digital) {
1631 v4l2_dbg(1, debug, sd,
25a64ac9 1632 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1633 __func__, fmt_change, fmt_change_digital);
25a64ac9 1634
14d03233 1635 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
25a64ac9 1636
54450f59
HV		 1637 if (handled)
1638 *handled = true;
1639 }
f24d229c
MR		 1640 /* HDMI/DVI mode */
1641 if (irq_reg_0x6b & 0x01) {
1642 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1643 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1644 set_rgb_quantization_range(sd);
1645 if (handled)
1646 *handled = true;
1647 }
1648
54450f59 1649 /* tx 5v detect */
4a31a93a 1650 tx_5v = io_read(sd, 0x70) & 0x1e;
54450f59
HV		 1651 if (tx_5v) {
1652 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1653 io_write(sd, 0x71, tx_5v);
1654 adv7604_s_detect_tx_5v_ctrl(sd);
1655 if (handled)
1656 *handled = true;
1657 }
1658 return 0;
1659}
1660
b09dfac8 1661static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59
HV		 1662{
1663 struct adv7604_state *state = to_state(sd);
4a31a93a 1664 u8 *data = NULL;
54450f59 1665
4a31a93a 1666 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1667 return -EINVAL;
1668 if (edid->blocks == 0)
1669 return -EINVAL;
4a31a93a 1670 if (edid->blocks > 2)
54450f59 1671 return -EINVAL;
4a31a93a
MR		 1672 if (edid->start_block > 1)
1673 return -EINVAL;
1674 if (edid->start_block == 1)
1675 edid->blocks = 1;
4a31a93a
MR		 1676
1677 if (edid->blocks > state->edid.blocks)
1678 edid->blocks = state->edid.blocks;
1679
1680 switch (edid->pad) {
1681 case ADV7604_EDID_PORT_A:
1682 case ADV7604_EDID_PORT_B:
1683 case ADV7604_EDID_PORT_C:
1684 case ADV7604_EDID_PORT_D:
1685 if (state->edid.present & (1 << edid->pad))
1686 data = state->edid.edid;
1687 break;
1688 default:
1689 return -EINVAL;
1690 break;
1691 }
1692 if (!data)
1693 return -ENODATA;
1694
1695 memcpy(edid->edid,
1696 data + edid->start_block * 128,
54450f59
HV		 1697 edid->blocks * 128);
1698 return 0;
1699}
1700
dd08beb9 1701static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1702{
1703 u8 d;
1704
1705 if ((edid[0x7e] != 1) ||
1706 (edid[0x80] != 0x02) ||
1707 (edid[0x81] != 0x03)) {
1708 return -1;
1709 }
1710
1711 /* search Vendor Specific Data Block (tag 3) */
1712 d = edid[0x82] & 0x7f;
1713 if (d > 4) {
1714 int i = 0x84;
1715 int end = 0x80 + d;
1716
1717 do {
1718 u8 tag = edid[i] >> 5;
1719 u8 len = edid[i] & 0x1f;
1720
1721 if ((tag == 3) && (len >= 5))
1722 return i + 4;
1723 i += len + 1;
1724 } while (i < end);
1725 }
1726 return -1;
1727}
1728
b09dfac8 1729static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59
HV		 1730{
1731 struct adv7604_state *state = to_state(sd);
dd08beb9 1732 int spa_loc;
3e86aa85 1733 int tmp = 0;
54450f59 1734 int err;
dd08beb9 1735 int i;
54450f59 1736
4a31a93a 1737 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1738 return -EINVAL;
1739 if (edid->start_block != 0)
1740 return -EINVAL;
1741 if (edid->blocks == 0) {
3e86aa85 1742 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a
MR		 1743 state->edid.present &= ~(1 << edid->pad);
1744 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
3e86aa85
MR		 1745 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1746
54450f59
HV		 1747 /* Fall back to a 16:9 aspect ratio */
1748 state->aspect_ratio.numerator = 16;
1749 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 1750
1751 if (!state->edid.present)
1752 state->edid.blocks = 0;
1753
1754 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1755 __func__, edid->pad, state->edid.present);
54450f59
HV		 1756 return 0;
1757 }
4a31a93a
MR		 1758 if (edid->blocks > 2) {
1759 edid->blocks = 2;
54450f59 1760 return -E2BIG;
4a31a93a 1761 }
4a31a93a 1762
dd08beb9
MR		 1763 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1764 __func__, edid->pad, state->edid.present);
1765
3e86aa85 1766 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 1767 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3e86aa85
MR		 1768 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1769 rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1770
dd08beb9
MR		 1771 spa_loc = get_edid_spa_location(edid->edid);
1772 if (spa_loc < 0)
1773 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1774
3e86aa85
MR		 1775 switch (edid->pad) {
1776 case ADV7604_EDID_PORT_A:
dd08beb9
MR		 1777 state->spa_port_a[0] = edid->edid[spa_loc];
1778 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85
MR		 1779 break;
1780 case ADV7604_EDID_PORT_B:
dd08beb9
MR		 1781 rep_write(sd, 0x70, edid->edid[spa_loc]);
1782 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85
MR		 1783 break;
1784 case ADV7604_EDID_PORT_C:
dd08beb9
MR		 1785 rep_write(sd, 0x72, edid->edid[spa_loc]);
1786 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85
MR		 1787 break;
1788 case ADV7604_EDID_PORT_D:
dd08beb9
MR		 1789 rep_write(sd, 0x74, edid->edid[spa_loc]);
1790 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 1791 break;
dd08beb9
MR		 1792 default:
1793 return -EINVAL;
3e86aa85 1794 }
dd08beb9
MR		 1795 rep_write(sd, 0x76, spa_loc & 0xff);
1796 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
3e86aa85 1797
dd08beb9
MR		 1798 edid->edid[spa_loc] = state->spa_port_a[0];
1799 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 1800
1801 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1802 state->edid.blocks = edid->blocks;
54450f59
HV		 1803 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1804 edid->edid[0x16]);
3e86aa85 1805 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 1806
1807 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1808 if (err < 0) {
3e86aa85 1809 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 1810 return err;
1811 }
1812
dd08beb9
MR		 1813 /* adv7604 calculates the checksums and enables I2C access to internal
1814 EDID RAM from DDC port. */
1815 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1816
1817 for (i = 0; i < 1000; i++) {
1818 if (rep_read(sd, 0x7d) & state->edid.present)
1819 break;
1820 mdelay(1);
1821 }
1822 if (i == 1000) {
1823 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1824 return -EIO;
1825 }
1826
1827
4a31a93a
MR		 1828 /* enable hotplug after 100 ms */
1829 queue_delayed_work(state->work_queues,
1830 &state->delayed_work_enable_hotplug, HZ / 10);
1831 return 0;
54450f59
HV		 1832}
1833
1834/*********** avi info frame CEA-861-E **************/
1835
1836static void print_avi_infoframe(struct v4l2_subdev *sd)
1837{
1838 int i;
1839 u8 buf[14];
1840 u8 avi_len;
1841 u8 avi_ver;
1842
bb88f325 1843 if (!is_hdmi(sd)) {
54450f59
HV		 1844 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1845 return;
1846 }
1847 if (!(io_read(sd, 0x60) & 0x01)) {
1848 v4l2_info(sd, "AVI infoframe not received\n");
1849 return;
1850 }
1851
1852 if (io_read(sd, 0x83) & 0x01) {
1853 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1854 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1855 if (io_read(sd, 0x83) & 0x01) {
1856 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1857 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1858 }
1859 }
1860
1861 avi_len = infoframe_read(sd, 0xe2);
1862 avi_ver = infoframe_read(sd, 0xe1);
1863 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1864 avi_ver, avi_len);
1865
1866 if (avi_ver != 0x02)
1867 return;
1868
1869 for (i = 0; i < 14; i++)
1870 buf[i] = infoframe_read(sd, i);
1871
1872 v4l2_info(sd,
1873 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1874 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1875 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1876}
1877
1878static int adv7604_log_status(struct v4l2_subdev *sd)
1879{
1880 struct adv7604_state *state = to_state(sd);
1881 struct v4l2_dv_timings timings;
1882 struct stdi_readback stdi;
1883 u8 reg_io_0x02 = io_read(sd, 0x02);
1884
1885 char *csc_coeff_sel_rb[16] = {
1886 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1887 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1888 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1889 "reserved", "reserved", "reserved", "reserved", "manual"
1890 };
1891 char *input_color_space_txt[16] = {
1892 "RGB limited range (16-235)", "RGB full range (0-255)",
1893 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 1894 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 1895 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1896 "invalid", "invalid", "invalid", "invalid", "invalid",
1897 "invalid", "invalid", "automatic"
1898 };
1899 char *rgb_quantization_range_txt[] = {
1900 "Automatic",
1901 "RGB limited range (16-235)",
1902 "RGB full range (0-255)",
1903 };
bb88f325
MB		 1904 char *deep_color_mode_txt[4] = {
1905 "8-bits per channel",
1906 "10-bits per channel",
1907 "12-bits per channel",
1908 "16-bits per channel (not supported)"
1909 };
54450f59
HV		 1910
1911 v4l2_info(sd, "-----Chip status-----\n");
1912 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
4a31a93a
MR		 1913 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1914 ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1915 ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1916 ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1917 ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
54450f59
HV		 1918 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1919 "enabled" : "disabled");
1920
1921 v4l2_info(sd, "-----Signal status-----\n");
4a31a93a
MR		 1922 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1923 ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1924 ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1925 ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1926 ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
54450f59
HV		 1927 v4l2_info(sd, "TMDS signal detected: %s\n",
1928 no_signal_tmds(sd) ? "false" : "true");
1929 v4l2_info(sd, "TMDS signal locked: %s\n",
1930 no_lock_tmds(sd) ? "false" : "true");
1931 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1932 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1933 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1934 v4l2_info(sd, "CP free run: %s\n",
1935 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1936 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1937 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1938 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1939
1940 v4l2_info(sd, "-----Video Timings-----\n");
1941 if (read_stdi(sd, &stdi))
1942 v4l2_info(sd, "STDI: not locked\n");
1943 else
1944 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1945 stdi.lcf, stdi.bl, stdi.lcvs,
1946 stdi.interlaced ? "interlaced" : "progressive",
1947 stdi.hs_pol, stdi.vs_pol);
1948 if (adv7604_query_dv_timings(sd, &timings))
1949 v4l2_info(sd, "No video detected\n");
1950 else
11d034c8
HV		 1951 v4l2_print_dv_timings(sd->name, "Detected format: ",
1952 &timings, true);
1953 v4l2_print_dv_timings(sd->name, "Configured format: ",
1954 &state->timings, true);
54450f59 1955
76eb2d30
MR		 1956 if (no_signal(sd))
1957 return 0;
1958
54450f59
HV		 1959 v4l2_info(sd, "-----Color space-----\n");
1960 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1961 rgb_quantization_range_txt[state->rgb_quantization_range]);
1962 v4l2_info(sd, "Input color space: %s\n",
1963 input_color_space_txt[reg_io_0x02 >> 4]);
1964 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1965 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1966 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1967 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 1968 "enabled" : "disabled");
54450f59
HV		 1969 v4l2_info(sd, "Color space conversion: %s\n",
1970 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1971
4a31a93a 1972 if (!is_digital_input(sd))
76eb2d30
MR		 1973 return 0;
1974
1975 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 1976 v4l2_info(sd, "Digital video port selected: %c\n",
1977 (hdmi_read(sd, 0x00) & 0x03) + 'A');
1978 v4l2_info(sd, "HDCP encrypted content: %s\n",
1979 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 1980 v4l2_info(sd, "HDCP keys read: %s%s\n",
1981 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1982 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1983 if (!is_hdmi(sd)) {
1984 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1985 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1986 bool audio_mute = io_read(sd, 0x65) & 0x40;
1987
1988 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1989 audio_pll_locked ? "locked" : "not locked",
1990 audio_sample_packet_detect ? "detected" : "not detected",
1991 audio_mute ? "muted" : "enabled");
1992 if (audio_pll_locked && audio_sample_packet_detect) {
1993 v4l2_info(sd, "Audio format: %s\n",
1994 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1995 }
1996 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1997 (hdmi_read(sd, 0x5c) << 8) +
1998 (hdmi_read(sd, 0x5d) & 0xf0));
1999 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2000 (hdmi_read(sd, 0x5e) << 8) +
2001 hdmi_read(sd, 0x5f));
2002 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2003
2004 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2005
54450f59
HV		 2006 print_avi_infoframe(sd);
2007 }
2008
2009 return 0;
2010}
2011
2012/* ----------------------------------------------------------------------- */
2013
2014static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
2015 .s_ctrl = adv7604_s_ctrl,
2016};
2017
2018static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2019 .log_status = adv7604_log_status,
2020 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
2021 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
2022 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
2023 .g_ctrl = v4l2_subdev_g_ctrl,
2024 .s_ctrl = v4l2_subdev_s_ctrl,
2025 .queryctrl = v4l2_subdev_queryctrl,
2026 .querymenu = v4l2_subdev_querymenu,
54450f59
HV		 2027 .interrupt_service_routine = adv7604_isr,
2028#ifdef CONFIG_VIDEO_ADV_DEBUG
2029 .g_register = adv7604_g_register,
2030 .s_register = adv7604_s_register,
2031#endif
2032};
2033
2034static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2035 .s_routing = adv7604_s_routing,
2036 .g_input_status = adv7604_g_input_status,
2037 .s_dv_timings = adv7604_s_dv_timings,
2038 .g_dv_timings = adv7604_g_dv_timings,
2039 .query_dv_timings = adv7604_query_dv_timings,
2040 .enum_dv_timings = adv7604_enum_dv_timings,
2041 .dv_timings_cap = adv7604_dv_timings_cap,
2042 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
2043 .g_mbus_fmt = adv7604_g_mbus_fmt,
2044 .try_mbus_fmt = adv7604_g_mbus_fmt,
2045 .s_mbus_fmt = adv7604_g_mbus_fmt,
2046};
2047
2048static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
2049 .get_edid = adv7604_get_edid,
2050 .set_edid = adv7604_set_edid,
2051};
2052
2053static const struct v4l2_subdev_ops adv7604_ops = {
2054 .core = &adv7604_core_ops,
2055 .video = &adv7604_video_ops,
2056 .pad = &adv7604_pad_ops,
2057};
2058
2059/* -------------------------- custom ctrls ---------------------------------- */
2060
2061static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2062 .ops = &adv7604_ctrl_ops,
2063 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2064 .name = "Analog Sampling Phase",
2065 .type = V4L2_CTRL_TYPE_INTEGER,
2066 .min = 0,
2067 .max = 0x1f,
2068 .step = 1,
2069 .def = 0,
2070};
2071
2072static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2073 .ops = &adv7604_ctrl_ops,
2074 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2075 .name = "Free Running Color, Manual",
2076 .type = V4L2_CTRL_TYPE_BOOLEAN,
2077 .min = false,
2078 .max = true,
2079 .step = 1,
2080 .def = false,
2081};
2082
2083static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2084 .ops = &adv7604_ctrl_ops,
2085 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2086 .name = "Free Running Color",
2087 .type = V4L2_CTRL_TYPE_INTEGER,
2088 .min = 0x0,
2089 .max = 0xffffff,
2090 .step = 0x1,
2091 .def = 0x0,
2092};
2093
2094/* ----------------------------------------------------------------------- */
2095
2096static int adv7604_core_init(struct v4l2_subdev *sd)
2097{
2098 struct adv7604_state *state = to_state(sd);
2099 struct adv7604_platform_data *pdata = &state->pdata;
2100
2101 hdmi_write(sd, 0x48,
2102 (pdata->disable_pwrdnb ? 0x80 : 0) |
2103 (pdata->disable_cable_det_rst ? 0x40 : 0));
2104
2105 disable_input(sd);
2106
2107 /* power */
2108 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2109 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2110 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2111
2112 /* video format */
2113 io_write_and_or(sd, 0x02, 0xf0,
2114 pdata->alt_gamma << 3 |
2115 pdata->op_656_range << 2 |
2116 pdata->rgb_out << 1 |
2117 pdata->alt_data_sat << 0);
2118 io_write(sd, 0x03, pdata->op_format_sel);
2119 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2120 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2121 pdata->insert_av_codes << 2 |
2122 pdata->replicate_av_codes << 1 |
2123 pdata->invert_cbcr << 0);
2124
54450f59 2125 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2126
2127 /* VS, HS polarities */
2128 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1);
f31b62e1
MK		 2129
2130 /* Adjust drive strength */
2131 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2132 pdata->dr_str_clk << 2 |
2133 pdata->dr_str_sync);
2134
54450f59
HV		 2135 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2136 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2137 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2138 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2139 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2140 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2141 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2142 for digital formats */
2143
5474b983
MR		 2144 /* HDMI audio */
2145 hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2146 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2147 hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2148
54450f59
HV		 2149 /* TODO from platform data */
2150 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2151
2152 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2153 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2154
54450f59
HV		 2155 /* interrupts */
2156 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2157 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2158 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
f24d229c 2159 io_write(sd, 0x6e, 0xc1); /* Enable V_LOCKED, DE_REGEN_LCK, HDMI_MODE interrupts */
4a31a93a 2160 io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
54450f59
HV		 2161
2162 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2163}
2164
2165static void adv7604_unregister_clients(struct adv7604_state *state)
2166{
2167 if (state->i2c_avlink)
2168 i2c_unregister_device(state->i2c_avlink);
2169 if (state->i2c_cec)
2170 i2c_unregister_device(state->i2c_cec);
2171 if (state->i2c_infoframe)
2172 i2c_unregister_device(state->i2c_infoframe);
2173 if (state->i2c_esdp)
2174 i2c_unregister_device(state->i2c_esdp);
2175 if (state->i2c_dpp)
2176 i2c_unregister_device(state->i2c_dpp);
2177 if (state->i2c_afe)
2178 i2c_unregister_device(state->i2c_afe);
2179 if (state->i2c_repeater)
2180 i2c_unregister_device(state->i2c_repeater);
2181 if (state->i2c_edid)
2182 i2c_unregister_device(state->i2c_edid);
2183 if (state->i2c_hdmi)
2184 i2c_unregister_device(state->i2c_hdmi);
2185 if (state->i2c_test)
2186 i2c_unregister_device(state->i2c_test);
2187 if (state->i2c_cp)
2188 i2c_unregister_device(state->i2c_cp);
2189 if (state->i2c_vdp)
2190 i2c_unregister_device(state->i2c_vdp);
2191}
2192
2193static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2194 u8 addr, u8 io_reg)
2195{
2196 struct i2c_client *client = v4l2_get_subdevdata(sd);
2197
2198 if (addr)
2199 io_write(sd, io_reg, addr << 1);
2200 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2201}
2202
2203static int adv7604_probe(struct i2c_client *client,
2204 const struct i2c_device_id *id)
2205{
591b72fe
HV		 2206 static const struct v4l2_dv_timings cea640x480 =
2207 V4L2_DV_BT_CEA_640X480P59_94;
54450f59
HV		 2208 struct adv7604_state *state;
2209 struct adv7604_platform_data *pdata = client->dev.platform_data;
2210 struct v4l2_ctrl_handler *hdl;
2211 struct v4l2_subdev *sd;
2212 int err;
2213
2214 /* Check if the adapter supports the needed features */
2215 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2216 return -EIO;
2217 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2218 client->addr << 1);
2219
c02b211d 2220 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 2221 if (!state) {
2222 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2223 return -ENOMEM;
2224 }
2225
25a64ac9
MR		 2226 /* initialize variables */
2227 state->restart_stdi_once = true;
ff4f80fd 2228 state->selected_input = ~0;
25a64ac9 2229
54450f59
HV		 2230 /* platform data */
2231 if (!pdata) {
2232 v4l_err(client, "No platform data!\n");
c02b211d 2233 return -ENODEV;
54450f59 2234 }
591b72fe
HV		 2235 state->pdata = *pdata;
2236 state->timings = cea640x480;
54450f59
HV		 2237
2238 sd = &state->sd;
2239 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2240 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59
HV		 2241
2242 /* i2c access to adv7604? */
2243 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2244 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2245 client->addr << 1);
c02b211d 2246 return -ENODEV;
54450f59
HV		 2247 }
2248
2249 /* control handlers */
2250 hdl = &state->hdl;
2251 v4l2_ctrl_handler_init(hdl, 9);
2252
2253 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2254 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2255 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2256 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2257 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2258 V4L2_CID_SATURATION, 0, 255, 1, 128);
2259 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2260 V4L2_CID_HUE, 0, 128, 1, 0);
2261
2262 /* private controls */
2263 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
4a31a93a 2264 V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
54450f59
HV		 2265 state->rgb_quantization_range_ctrl =
2266 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2267 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2268 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2269
2270 /* custom controls */
2271 state->analog_sampling_phase_ctrl =
2272 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2273 state->free_run_color_manual_ctrl =
2274 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2275 state->free_run_color_ctrl =
2276 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2277
2278 sd->ctrl_handler = hdl;
2279 if (hdl->error) {
2280 err = hdl->error;
2281 goto err_hdl;
2282 }
8c0eadb8
HV		 2283 state->detect_tx_5v_ctrl->is_private = true;
2284 state->rgb_quantization_range_ctrl->is_private = true;
2285 state->analog_sampling_phase_ctrl->is_private = true;
2286 state->free_run_color_manual_ctrl->is_private = true;
2287 state->free_run_color_ctrl->is_private = true;
2288
54450f59
HV		 2289 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2290 err = -ENODEV;
2291 goto err_hdl;
2292 }
2293
2294 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2295 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2296 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2297 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2298 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2299 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2300 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2301 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2302 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2303 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2304 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2305 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2306 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2307 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2308 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2309 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2310 err = -ENOMEM;
2311 v4l2_err(sd, "failed to create all i2c clients\n");
2312 goto err_i2c;
2313 }
2314
2315 /* work queues */
2316 state->work_queues = create_singlethread_workqueue(client->name);
2317 if (!state->work_queues) {
2318 v4l2_err(sd, "Could not create work queue\n");
2319 err = -ENOMEM;
2320 goto err_i2c;
2321 }
2322
2323 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2324 adv7604_delayed_work_enable_hotplug);
2325
2326 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2327 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2328 if (err)
2329 goto err_work_queues;
2330
2331 err = adv7604_core_init(sd);
2332 if (err)
2333 goto err_entity;
2334 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2335 client->addr << 1, client->adapter->name);
bedc3939
LPC		 2336
2337 err = v4l2_async_register_subdev(sd);
2338 if (err)
2339 goto err_entity;
2340
54450f59
HV		 2341 return 0;
2342
2343err_entity:
2344 media_entity_cleanup(&sd->entity);
2345err_work_queues:
2346 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2347 destroy_workqueue(state->work_queues);
2348err_i2c:
2349 adv7604_unregister_clients(state);
2350err_hdl:
2351 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2352 return err;
2353}
2354
2355/* ----------------------------------------------------------------------- */
2356
2357static int adv7604_remove(struct i2c_client *client)
2358{
2359 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2360 struct adv7604_state *state = to_state(sd);
2361
2362 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2363 destroy_workqueue(state->work_queues);
bedc3939 2364 v4l2_async_unregister_subdev(sd);
54450f59
HV		 2365 v4l2_device_unregister_subdev(sd);
2366 media_entity_cleanup(&sd->entity);
2367 adv7604_unregister_clients(to_state(sd));
2368 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2369 return 0;
2370}
2371
2372/* ----------------------------------------------------------------------- */
2373
2374static struct i2c_device_id adv7604_id[] = {
2375 { "adv7604", 0 },
2376 { }
2377};
2378MODULE_DEVICE_TABLE(i2c, adv7604_id);
2379
2380static struct i2c_driver adv7604_driver = {
2381 .driver = {
2382 .owner = THIS_MODULE,
2383 .name = "adv7604",
2384 },
2385 .probe = adv7604_probe,
2386 .remove = adv7604_remove,
2387 .id_table = adv7604_id,
2388};
2389
2390module_i2c_driver(adv7604_driver);
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