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[mirror_ubuntu-eoan-kernel.git] / drivers / media / i2c / adv7604.c
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54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
c72a53ce 32#include <linux/i2c.h>
54450f59
HV		 33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
c72a53ce 36#include <linux/v4l2-dv-timings.h>
54450f59
HV		 37#include <linux/videodev2.h>
38#include <linux/workqueue.h>
c72a53ce
LP		 39
40#include <media/adv7604.h>
54450f59 41#include <media/v4l2-ctrls.h>
c72a53ce 42#include <media/v4l2-device.h>
25764158 43#include <media/v4l2-dv-timings.h>
6fa88045 44#include <media/v4l2-of.h>
54450f59
HV		 45
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7604 system clock frequency */
56#define ADV7604_fsc (28636360)
57
539b33b0
LP		 58#define ADV7604_RGB_OUT (1 << 1)
59
60#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0)
61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
62#define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0)
63
64#define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5)
65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66#define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5)
67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
68#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5)
69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70
71#define ADV7604_OP_CH_SEL_GBR (0 << 5)
72#define ADV7604_OP_CH_SEL_GRB (1 << 5)
73#define ADV7604_OP_CH_SEL_BGR (2 << 5)
74#define ADV7604_OP_CH_SEL_RGB (3 << 5)
75#define ADV7604_OP_CH_SEL_BRG (4 << 5)
76#define ADV7604_OP_CH_SEL_RBG (5 << 5)
77
78#define ADV7604_OP_SWAP_CB_CR (1 << 0)
79
d42010a1
LPC		 80enum adv7604_type {
81 ADV7604,
82 ADV7611,
83};
84
85struct adv7604_reg_seq {
86 unsigned int reg;
87 u8 val;
88};
89
539b33b0 90struct adv7604_format_info {
f5fe58fd 91 u32 code;
539b33b0
LP		 92 u8 op_ch_sel;
93 bool rgb_out;
94 bool swap_cb_cr;
95 u8 op_format_sel;
96};
97
d42010a1
LPC		 98struct adv7604_chip_info {
99 enum adv7604_type type;
100
101 bool has_afe;
102 unsigned int max_port;
103 unsigned int num_dv_ports;
104
105 unsigned int edid_enable_reg;
106 unsigned int edid_status_reg;
107 unsigned int lcf_reg;
108
109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask;
80f4944e 112 unsigned int cp_csc;
d42010a1 113
539b33b0
LP		 114 const struct adv7604_format_info *formats;
115 unsigned int nformats;
116
d42010a1
LPC		 117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
118 void (*setup_irqs)(struct v4l2_subdev *sd);
119 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
121
122 /* 0 = AFE, 1 = HDMI */
123 const struct adv7604_reg_seq *recommended_settings[2];
124 unsigned int num_recommended_settings[2];
125
126 unsigned long page_mask;
127};
128
54450f59
HV		 129/*
130 **********************************************************************
131 *
132 * Arrays with configuration parameters for the ADV7604
133 *
134 **********************************************************************
135 */
c784b1e2 136
54450f59 137struct adv7604_state {
d42010a1 138 const struct adv7604_chip_info *info;
54450f59 139 struct adv7604_platform_data pdata;
539b33b0 140
e9d50e9e
LP		 141 struct gpio_desc *hpd_gpio[4];
142
54450f59 143 struct v4l2_subdev sd;
c784b1e2
LP		 144 struct media_pad pads[ADV7604_PAD_MAX];
145 unsigned int source_pad;
539b33b0 146
54450f59 147 struct v4l2_ctrl_handler hdl;
539b33b0 148
c784b1e2 149 enum adv7604_pad selected_input;
539b33b0 150
54450f59 151 struct v4l2_dv_timings timings;
539b33b0
LP		 152 const struct adv7604_format_info *format;
153
4a31a93a
MR		 154 struct {
155 u8 edid[256];
156 u32 present;
157 unsigned blocks;
158 } edid;
dd08beb9 159 u16 spa_port_a[2];
54450f59
HV		 160 struct v4l2_fract aspect_ratio;
161 u32 rgb_quantization_range;
162 struct workqueue_struct *work_queues;
163 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 164 bool restart_stdi_once;
54450f59
HV		 165
166 /* i2c clients */
05cacb17 167 struct i2c_client *i2c_clients[ADV7604_PAGE_MAX];
54450f59
HV		 168
169 /* controls */
170 struct v4l2_ctrl *detect_tx_5v_ctrl;
171 struct v4l2_ctrl *analog_sampling_phase_ctrl;
172 struct v4l2_ctrl *free_run_color_manual_ctrl;
173 struct v4l2_ctrl *free_run_color_ctrl;
174 struct v4l2_ctrl *rgb_quantization_range_ctrl;
175};
176
d42010a1
LPC		 177static bool adv7604_has_afe(struct adv7604_state *state)
178{
179 return state->info->has_afe;
180}
181
54450f59
HV		 182/* Supported CEA and DMT timings */
183static const struct v4l2_dv_timings adv7604_timings[] = {
184 V4L2_DV_BT_CEA_720X480P59_94,
185 V4L2_DV_BT_CEA_720X576P50,
186 V4L2_DV_BT_CEA_1280X720P24,
187 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 188 V4L2_DV_BT_CEA_1280X720P50,
189 V4L2_DV_BT_CEA_1280X720P60,
190 V4L2_DV_BT_CEA_1920X1080P24,
191 V4L2_DV_BT_CEA_1920X1080P25,
192 V4L2_DV_BT_CEA_1920X1080P30,
193 V4L2_DV_BT_CEA_1920X1080P50,
194 V4L2_DV_BT_CEA_1920X1080P60,
195
ccbd5bc4 196 /* sorted by DMT ID */
54450f59
HV		 197 V4L2_DV_BT_DMT_640X350P85,
198 V4L2_DV_BT_DMT_640X400P85,
199 V4L2_DV_BT_DMT_720X400P85,
200 V4L2_DV_BT_DMT_640X480P60,
201 V4L2_DV_BT_DMT_640X480P72,
202 V4L2_DV_BT_DMT_640X480P75,
203 V4L2_DV_BT_DMT_640X480P85,
204 V4L2_DV_BT_DMT_800X600P56,
205 V4L2_DV_BT_DMT_800X600P60,
206 V4L2_DV_BT_DMT_800X600P72,
207 V4L2_DV_BT_DMT_800X600P75,
208 V4L2_DV_BT_DMT_800X600P85,
209 V4L2_DV_BT_DMT_848X480P60,
210 V4L2_DV_BT_DMT_1024X768P60,
211 V4L2_DV_BT_DMT_1024X768P70,
212 V4L2_DV_BT_DMT_1024X768P75,
213 V4L2_DV_BT_DMT_1024X768P85,
214 V4L2_DV_BT_DMT_1152X864P75,
215 V4L2_DV_BT_DMT_1280X768P60_RB,
216 V4L2_DV_BT_DMT_1280X768P60,
217 V4L2_DV_BT_DMT_1280X768P75,
218 V4L2_DV_BT_DMT_1280X768P85,
219 V4L2_DV_BT_DMT_1280X800P60_RB,
220 V4L2_DV_BT_DMT_1280X800P60,
221 V4L2_DV_BT_DMT_1280X800P75,
222 V4L2_DV_BT_DMT_1280X800P85,
223 V4L2_DV_BT_DMT_1280X960P60,
224 V4L2_DV_BT_DMT_1280X960P85,
225 V4L2_DV_BT_DMT_1280X1024P60,
226 V4L2_DV_BT_DMT_1280X1024P75,
227 V4L2_DV_BT_DMT_1280X1024P85,
228 V4L2_DV_BT_DMT_1360X768P60,
229 V4L2_DV_BT_DMT_1400X1050P60_RB,
230 V4L2_DV_BT_DMT_1400X1050P60,
231 V4L2_DV_BT_DMT_1400X1050P75,
232 V4L2_DV_BT_DMT_1400X1050P85,
233 V4L2_DV_BT_DMT_1440X900P60_RB,
234 V4L2_DV_BT_DMT_1440X900P60,
235 V4L2_DV_BT_DMT_1600X1200P60,
236 V4L2_DV_BT_DMT_1680X1050P60_RB,
237 V4L2_DV_BT_DMT_1680X1050P60,
238 V4L2_DV_BT_DMT_1792X1344P60,
239 V4L2_DV_BT_DMT_1856X1392P60,
240 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 241 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 242 V4L2_DV_BT_DMT_1366X768P60,
243 V4L2_DV_BT_DMT_1920X1080P60,
244 { },
245};
246
ccbd5bc4
HV		 247struct adv7604_video_standards {
248 struct v4l2_dv_timings timings;
249 u8 vid_std;
250 u8 v_freq;
251};
252
253/* sorted by number of lines */
254static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
258 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
259 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
260 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
261 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
262 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
263 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
264 /* TODO add 1920x1080P60_RB (CVT timing) */
265 { },
266};
267
268/* sorted by number of lines */
269static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
273 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
274 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
275 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
276 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
277 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
278 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
279 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
280 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
281 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
282 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
283 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
284 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
285 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
286 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
287 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
288 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
289 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
290 /* TODO add 1600X1200P60_RB (not a DMT timing) */
291 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
292 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
293 { },
294};
295
296/* sorted by number of lines */
297static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
301 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
302 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
303 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
304 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
305 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
306 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
307 { },
308};
309
310/* sorted by number of lines */
311static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
315 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
316 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
317 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
318 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
319 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
320 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
321 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
322 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
323 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
324 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
325 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
326 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
327 { },
328};
329
54450f59
HV		 330/* ----------------------------------------------------------------------- */
331
332static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
333{
334 return container_of(sd, struct adv7604_state, sd);
335}
336
54450f59
HV		 337static inline unsigned htotal(const struct v4l2_bt_timings *t)
338{
eacf8f9a 339 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 340}
341
54450f59
HV		 342static inline unsigned vtotal(const struct v4l2_bt_timings *t)
343{
eacf8f9a 344 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 345}
346
347/* ----------------------------------------------------------------------- */
348
349static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
350 u8 command, bool check)
351{
352 union i2c_smbus_data data;
353
354 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
355 I2C_SMBUS_READ, command,
356 I2C_SMBUS_BYTE_DATA, &data))
357 return data.byte;
358 if (check)
359 v4l_err(client, "error reading %02x, %02x\n",
360 client->addr, command);
361 return -EIO;
362}
363
05cacb17
LP		 364static s32 adv_smbus_read_byte_data(struct adv7604_state *state,
365 enum adv7604_page page, u8 command)
54450f59 366{
05cacb17
LP		 367 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
368 command, true);
54450f59
HV		 369}
370
05cacb17
LP		 371static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
372 enum adv7604_page page, u8 command,
373 u8 value)
54450f59 374{
05cacb17 375 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 376 union i2c_smbus_data data;
377 int err;
378 int i;
379
380 data.byte = value;
381 for (i = 0; i < 3; i++) {
382 err = i2c_smbus_xfer(client->adapter, client->addr,
383 client->flags,
384 I2C_SMBUS_WRITE, command,
385 I2C_SMBUS_BYTE_DATA, &data);
386 if (!err)
387 break;
388 }
389 if (err < 0)
390 v4l_err(client, "error writing %02x, %02x, %02x\n",
391 client->addr, command, value);
392 return err;
393}
394
05cacb17
LP		 395static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
396 enum adv7604_page page, u8 command,
397 unsigned length, const u8 *values)
54450f59 398{
05cacb17 399 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 400 union i2c_smbus_data data;
401
402 if (length > I2C_SMBUS_BLOCK_MAX)
403 length = I2C_SMBUS_BLOCK_MAX;
404 data.block[0] = length;
405 memcpy(data.block + 1, values, length);
406 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
407 I2C_SMBUS_WRITE, command,
408 I2C_SMBUS_I2C_BLOCK_DATA, &data);
409}
410
411/* ----------------------------------------------------------------------- */
412
413static inline int io_read(struct v4l2_subdev *sd, u8 reg)
414{
05cacb17 415 struct adv7604_state *state = to_state(sd);
54450f59 416
05cacb17 417 return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg);
54450f59
HV		 418}
419
420static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421{
05cacb17 422 struct adv7604_state *state = to_state(sd);
54450f59 423
05cacb17 424 return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
54450f59
HV		 425}
426
22d97e56 427static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 428{
22d97e56 429 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 430}
431
432static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
433{
434 struct adv7604_state *state = to_state(sd);
435
05cacb17 436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 437}
438
439static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440{
441 struct adv7604_state *state = to_state(sd);
442
05cacb17 443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
54450f59
HV		 444}
445
446static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
447{
448 struct adv7604_state *state = to_state(sd);
449
05cacb17 450 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg);
54450f59
HV		 451}
452
453static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
454{
455 struct adv7604_state *state = to_state(sd);
456
05cacb17 457 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
54450f59
HV		 458}
459
54450f59
HV		 460static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
461{
462 struct adv7604_state *state = to_state(sd);
463
05cacb17 464 return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg);
54450f59
HV		 465}
466
467static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468{
469 struct adv7604_state *state = to_state(sd);
470
05cacb17
LP		 471 return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME,
472 reg, val);
54450f59
HV		 473}
474
54450f59
HV		 475static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
476{
477 struct adv7604_state *state = to_state(sd);
478
05cacb17 479 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg);
54450f59
HV		 480}
481
482static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
483{
484 struct adv7604_state *state = to_state(sd);
485
05cacb17 486 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val);
54450f59
HV		 487}
488
489static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
490{
491 struct adv7604_state *state = to_state(sd);
492
05cacb17 493 return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg);
54450f59
HV		 494}
495
496static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497{
498 struct adv7604_state *state = to_state(sd);
499
05cacb17 500 return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
54450f59
HV		 501}
502
22d97e56 503static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 504{
22d97e56 505 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 506}
507
508static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
509{
510 struct adv7604_state *state = to_state(sd);
511
05cacb17 512 return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg);
54450f59
HV		 513}
514
515static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
516{
517 struct adv7604_state *state = to_state(sd);
518
05cacb17 519 return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val);
54450f59
HV		 520}
521
54450f59
HV		 522static inline int edid_write_block(struct v4l2_subdev *sd,
523 unsigned len, const u8 *val)
524{
54450f59
HV		 525 struct adv7604_state *state = to_state(sd);
526 int err = 0;
527 int i;
528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530
54450f59 531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
05cacb17
LP		 532 err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID,
533 i, I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 534 return err;
535}
54450f59 536
e9d50e9e
LP		 537static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd)
538{
539 unsigned int i;
540
541 for (i = 0; i < state->info->num_dv_ports; ++i) {
542 if (IS_ERR(state->hpd_gpio[i]))
543 continue;
544
545 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
546 }
547
548 v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd);
549}
550
dd08beb9
MR		 551static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
552{
553 struct delayed_work *dwork = to_delayed_work(work);
554 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
555 delayed_work_enable_hotplug);
556 struct v4l2_subdev *sd = &state->sd;
54450f59 557
dd08beb9 558 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 559
e9d50e9e 560 adv7604_set_hpd(state, state->edid.present);
54450f59
HV		 561}
562
563static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
564{
565 struct adv7604_state *state = to_state(sd);
566
05cacb17 567 return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg);
54450f59
HV		 568}
569
51182a94
LP		 570static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
571{
572 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
573}
574
54450f59
HV		 575static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
576{
577 struct adv7604_state *state = to_state(sd);
578
05cacb17 579 return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
54450f59
HV		 580}
581
22d97e56 582static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 583{
22d97e56 584 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 585}
586
54450f59
HV		 587static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
588{
589 struct adv7604_state *state = to_state(sd);
590
05cacb17 591 return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val);
54450f59
HV		 592}
593
594static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
595{
596 struct adv7604_state *state = to_state(sd);
597
05cacb17 598 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg);
54450f59
HV		 599}
600
51182a94
LP		 601static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
602{
603 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
604}
605
54450f59
HV		 606static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
607{
608 struct adv7604_state *state = to_state(sd);
609
05cacb17 610 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
54450f59
HV		 611}
612
22d97e56 613static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 614{
22d97e56 615 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 616}
617
618static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
619{
620 struct adv7604_state *state = to_state(sd);
621
05cacb17 622 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 623}
624
625static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
626{
627 struct adv7604_state *state = to_state(sd);
628
05cacb17
LP		 629 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
630}
d42010a1
LPC		 631
632#define ADV7604_REG(page, offset) (((page) << 8) | (offset))
633#define ADV7604_REG_SEQ_TERM 0xffff
634
635#ifdef CONFIG_VIDEO_ADV_DEBUG
636static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
637{
638 struct adv7604_state *state = to_state(sd);
639 unsigned int page = reg >> 8;
640
641 if (!(BIT(page) & state->info->page_mask))
642 return -EINVAL;
643
644 reg &= 0xff;
645
05cacb17 646 return adv_smbus_read_byte_data(state, page, reg);
d42010a1
LPC		 647}
648#endif
649
650static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
651{
652 struct adv7604_state *state = to_state(sd);
653 unsigned int page = reg >> 8;
654
655 if (!(BIT(page) & state->info->page_mask))
656 return -EINVAL;
657
658 reg &= 0xff;
659
05cacb17 660 return adv_smbus_write_byte_data(state, page, reg, val);
d42010a1
LPC		 661}
662
663static void adv7604_write_reg_seq(struct v4l2_subdev *sd,
664 const struct adv7604_reg_seq *reg_seq)
665{
666 unsigned int i;
667
668 for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++)
669 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
670}
671
539b33b0
LP		 672/* -----------------------------------------------------------------------------
673 * Format helpers
674 */
675
676static const struct adv7604_format_info adv7604_formats[] = {
f5fe58fd 677 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
539b33b0 678 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 679 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 680 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 681 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 682 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 683 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 684 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 685 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 686 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 687 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 688 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 689 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 690 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 691 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 692 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 693 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 694 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 695 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 696 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 697 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 698 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 699 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 700 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 701 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 702 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 703 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 704 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 705 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 706 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 707 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 708 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 709 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 710 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 711 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 712 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 713 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0
LP		 714 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
715};
716
717static const struct adv7604_format_info adv7611_formats[] = {
f5fe58fd 718 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
539b33b0 719 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 720 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 721 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 722 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 723 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 724 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 725 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 726 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 727 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 728 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 729 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 730 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 731 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 732 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 733 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 734 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 735 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 736 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 737 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 738 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 739 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 740 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 741 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 742 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0
LP		 743 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
744};
745
746static const struct adv7604_format_info *
f5fe58fd 747adv7604_format_info(struct adv7604_state *state, u32 code)
539b33b0
LP		 748{
749 unsigned int i;
750
751 for (i = 0; i < state->info->nformats; ++i) {
752 if (state->info->formats[i].code == code)
753 return &state->info->formats[i];
754 }
755
756 return NULL;
757}
758
54450f59
HV		 759/* ----------------------------------------------------------------------- */
760
4a31a93a
MR		 761static inline bool is_analog_input(struct v4l2_subdev *sd)
762{
763 struct adv7604_state *state = to_state(sd);
764
c784b1e2
LP		 765 return state->selected_input == ADV7604_PAD_VGA_RGB ||
766 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 767}
768
769static inline bool is_digital_input(struct v4l2_subdev *sd)
770{
771 struct adv7604_state *state = to_state(sd);
772
c784b1e2
LP		 773 return state->selected_input == ADV7604_PAD_HDMI_PORT_A ||
774 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
775 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
776 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 777}
778
779/* ----------------------------------------------------------------------- */
780
54450f59
HV		 781#ifdef CONFIG_VIDEO_ADV_DEBUG
782static void adv7604_inv_register(struct v4l2_subdev *sd)
783{
784 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
785 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
786 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
787 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
788 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
789 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
790 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
791 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
792 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
793 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
794 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
795 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
796 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
797}
798
799static int adv7604_g_register(struct v4l2_subdev *sd,
800 struct v4l2_dbg_register *reg)
801{
d42010a1
LPC		 802 int ret;
803
804 ret = adv7604_read_reg(sd, reg->reg);
805 if (ret < 0) {
54450f59
HV		 806 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
807 adv7604_inv_register(sd);
d42010a1 808 return ret;
54450f59 809 }
d42010a1
LPC		 810
811 reg->size = 1;
812 reg->val = ret;
813
54450f59
HV		 814 return 0;
815}
816
817static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 818 const struct v4l2_dbg_register *reg)
54450f59 819{
d42010a1 820 int ret;
1577461b 821
d42010a1
LPC		 822 ret = adv7604_write_reg(sd, reg->reg, reg->val);
823 if (ret < 0) {
54450f59
HV		 824 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
825 adv7604_inv_register(sd);
d42010a1 826 return ret;
54450f59 827 }
d42010a1 828
54450f59
HV		 829 return 0;
830}
831#endif
832
d42010a1
LPC		 833static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
834{
835 u8 value = io_read(sd, 0x6f);
836
837 return ((value & 0x10) >> 4)
838 | ((value & 0x08) >> 2)
839 | ((value & 0x04) << 0)
840 | ((value & 0x02) << 2);
841}
842
843static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
844{
845 u8 value = io_read(sd, 0x6f);
846
847 return value & 1;
848}
849
54450f59
HV		 850static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
851{
852 struct adv7604_state *state = to_state(sd);
d42010a1 853 const struct adv7604_chip_info *info = state->info;
54450f59 854
54450f59 855 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 856 info->read_cable_det(sd));
54450f59
HV		 857}
858
ccbd5bc4
HV		 859static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
860 u8 prim_mode,
861 const struct adv7604_video_standards *predef_vid_timings,
862 const struct v4l2_dv_timings *timings)
863{
ccbd5bc4
HV		 864 int i;
865
866 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 867 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 868 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 869 continue;
870 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
871 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
872 prim_mode); /* v_freq and prim mode */
873 return 0;
874 }
875
876 return -1;
877}
878
879static int configure_predefined_video_timings(struct v4l2_subdev *sd,
880 struct v4l2_dv_timings *timings)
54450f59 881{
ccbd5bc4
HV		 882 struct adv7604_state *state = to_state(sd);
883 int err;
884
885 v4l2_dbg(1, debug, sd, "%s", __func__);
886
d42010a1
LPC		 887 if (adv7604_has_afe(state)) {
888 /* reset to default values */
889 io_write(sd, 0x16, 0x43);
890 io_write(sd, 0x17, 0x5a);
891 }
ccbd5bc4 892 /* disable embedded syncs for auto graphics mode */
22d97e56 893 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 894 cp_write(sd, 0x8f, 0x00);
895 cp_write(sd, 0x90, 0x00);
896 cp_write(sd, 0xa2, 0x00);
897 cp_write(sd, 0xa3, 0x00);
898 cp_write(sd, 0xa4, 0x00);
899 cp_write(sd, 0xa5, 0x00);
900 cp_write(sd, 0xa6, 0x00);
901 cp_write(sd, 0xa7, 0x00);
902 cp_write(sd, 0xab, 0x00);
903 cp_write(sd, 0xac, 0x00);
904
4a31a93a 905 if (is_analog_input(sd)) {
ccbd5bc4
HV		 906 err = find_and_set_predefined_video_timings(sd,
907 0x01, adv7604_prim_mode_comp, timings);
908 if (err)
909 err = find_and_set_predefined_video_timings(sd,
910 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 911 } else if (is_digital_input(sd)) {
ccbd5bc4
HV		 912 err = find_and_set_predefined_video_timings(sd,
913 0x05, adv7604_prim_mode_hdmi_comp, timings);
914 if (err)
915 err = find_and_set_predefined_video_timings(sd,
916 0x06, adv7604_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 917 } else {
918 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
919 __func__, state->selected_input);
ccbd5bc4 920 err = -1;
ccbd5bc4
HV		 921 }
922
923
924 return err;
925}
926
927static void configure_custom_video_timings(struct v4l2_subdev *sd,
928 const struct v4l2_bt_timings *bt)
929{
930 struct adv7604_state *state = to_state(sd);
ccbd5bc4
HV		 931 u32 width = htotal(bt);
932 u32 height = vtotal(bt);
933 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
934 u16 cp_start_eav = width - bt->hfrontporch;
935 u16 cp_start_vbi = height - bt->vfrontporch;
936 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
937 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
938 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
939 const u8 pll[2] = {
940 0xc0 | ((width >> 8) & 0x1f),
941 width & 0xff
942 };
54450f59
HV		 943
944 v4l2_dbg(2, debug, sd, "%s\n", __func__);
945
4a31a93a 946 if (is_analog_input(sd)) {
ccbd5bc4
HV		 947 /* auto graphics */
948 io_write(sd, 0x00, 0x07); /* video std */
949 io_write(sd, 0x01, 0x02); /* prim mode */
950 /* enable embedded syncs for auto graphics mode */
22d97e56 951 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 952
ccbd5bc4 953 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 954 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
955 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
05cacb17
LP		 956 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO,
957 0x16, 2, pll))
54450f59 958 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 959
960 /* active video - horizontal timing */
54450f59 961 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 962 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 963 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 964 cp_write(sd, 0xa4, cp_start_eav & 0xff);
965
966 /* active video - vertical timing */
54450f59 967 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 968 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 969 ((cp_end_vbi >> 8) & 0xf));
54450f59 970 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 971 } else if (is_digital_input(sd)) {
ccbd5bc4 972 /* set default prim_mode/vid_std for HDMI
39c1cb2b 973 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 974 io_write(sd, 0x00, 0x02); /* video std */
975 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 976 } else {
977 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
978 __func__, state->selected_input);
54450f59 979 }
54450f59 980
ccbd5bc4
HV		 981 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
982 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
983 cp_write(sd, 0xab, (height >> 4) & 0xff);
984 cp_write(sd, 0xac, (height & 0x0f) << 4);
985}
54450f59 986
5c6c6349
MR		 987static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
988{
989 struct adv7604_state *state = to_state(sd);
990 u8 offset_buf[4];
991
992 if (auto_offset) {
993 offset_a = 0x3ff;
994 offset_b = 0x3ff;
995 offset_c = 0x3ff;
996 }
997
998 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
999 __func__, auto_offset ? "Auto" : "Manual",
1000 offset_a, offset_b, offset_c);
1001
1002 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1003 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1004 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1005 offset_buf[3] = offset_c & 0x0ff;
1006
1007 /* Registers must be written in this order with no i2c access in between */
05cacb17
LP		 1008 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1009 0x77, 4, offset_buf))
5c6c6349
MR		 1010 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1011}
1012
1013static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1014{
1015 struct adv7604_state *state = to_state(sd);
1016 u8 gain_buf[4];
1017 u8 gain_man = 1;
1018 u8 agc_mode_man = 1;
1019
1020 if (auto_gain) {
1021 gain_man = 0;
1022 agc_mode_man = 0;
1023 gain_a = 0x100;
1024 gain_b = 0x100;
1025 gain_c = 0x100;
1026 }
1027
1028 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1029 __func__, auto_gain ? "Auto" : "Manual",
1030 gain_a, gain_b, gain_c);
1031
1032 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1033 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1034 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1035 gain_buf[3] = ((gain_c & 0x0ff));
1036
1037 /* Registers must be written in this order with no i2c access in between */
05cacb17
LP		 1038 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1039 0x73, 4, gain_buf))
5c6c6349
MR		 1040 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1041}
1042
54450f59
HV		 1043static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1044{
1045 struct adv7604_state *state = to_state(sd);
5c6c6349
MR		 1046 bool rgb_output = io_read(sd, 0x02) & 0x02;
1047 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1048
1049 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1050 __func__, state->rgb_quantization_range,
1051 rgb_output, hdmi_signal);
54450f59 1052
5c6c6349
MR		 1053 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
1054 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1055
54450f59
HV		 1056 switch (state->rgb_quantization_range) {
1057 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1058 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1059 /* Receiving analog RGB signal
1060 * Set RGB full range (0-255) */
22d97e56 1061 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1062 break;
1063 }
1064
c784b1e2 1065 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1066 /* Receiving analog YPbPr signal
1067 * Set automode */
22d97e56 1068 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1069 break;
1070 }
1071
5c6c6349 1072 if (hdmi_signal) {
9833239e
MR		 1073 /* Receiving HDMI signal
1074 * Set automode */
22d97e56 1075 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1076 break;
1077 }
1078
1079 /* Receiving DVI-D signal
1080 * ADV7604 selects RGB limited range regardless of
1081 * input format (CE/IT) in automatic mode */
1082 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1083 /* RGB limited range (16-235) */
22d97e56 1084 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1085 } else {
1086 /* RGB full range (0-255) */
22d97e56 1087 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1088
1089 if (is_digital_input(sd) && rgb_output) {
1090 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1091 } else {
1092 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1093 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1094 }
54450f59
HV		 1095 }
1096 break;
1097 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1098 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1099 /* YCrCb limited range (16-235) */
22d97e56 1100 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1101 break;
d261e842 1102 }
5c6c6349
MR		 1103
1104 /* RGB limited range (16-235) */
22d97e56 1105 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1106
54450f59
HV		 1107 break;
1108 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1109 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1110 /* YCrCb full range (0-255) */
22d97e56 1111 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1112 break;
1113 }
1114
1115 /* RGB full range (0-255) */
22d97e56 1116 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1117
1118 if (is_analog_input(sd) || hdmi_signal)
1119 break;
1120
1121 /* Adjust gain/offset for DVI-D signals only */
1122 if (rgb_output) {
1123 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1124 } else {
5c6c6349
MR		 1125 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1126 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1127 }
54450f59
HV		 1128 break;
1129 }
1130}
1131
54450f59
HV		 1132static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1133{
c269887c
LP		 1134 struct v4l2_subdev *sd =
1135 &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
1136
54450f59
HV		 1137 struct adv7604_state *state = to_state(sd);
1138
1139 switch (ctrl->id) {
1140 case V4L2_CID_BRIGHTNESS:
1141 cp_write(sd, 0x3c, ctrl->val);
1142 return 0;
1143 case V4L2_CID_CONTRAST:
1144 cp_write(sd, 0x3a, ctrl->val);
1145 return 0;
1146 case V4L2_CID_SATURATION:
1147 cp_write(sd, 0x3b, ctrl->val);
1148 return 0;
1149 case V4L2_CID_HUE:
1150 cp_write(sd, 0x3d, ctrl->val);
1151 return 0;
1152 case V4L2_CID_DV_RX_RGB_RANGE:
1153 state->rgb_quantization_range = ctrl->val;
1154 set_rgb_quantization_range(sd);
1155 return 0;
1156 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
d42010a1
LPC		 1157 if (!adv7604_has_afe(state))
1158 return -EINVAL;
54450f59
HV		 1159 /* Set the analog sampling phase. This is needed to find the
1160 best sampling phase for analog video: an application or
1161 driver has to try a number of phases and analyze the picture
1162 quality before settling on the best performing phase. */
1163 afe_write(sd, 0xc8, ctrl->val);
1164 return 0;
1165 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1166 /* Use the default blue color for free running mode,
1167 or supply your own. */
22d97e56 1168 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1169 return 0;
1170 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1171 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1172 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1173 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1174 return 0;
1175 }
1176 return -EINVAL;
1177}
1178
54450f59
HV		 1179/* ----------------------------------------------------------------------- */
1180
1181static inline bool no_power(struct v4l2_subdev *sd)
1182{
1183 /* Entire chip or CP powered off */
1184 return io_read(sd, 0x0c) & 0x24;
1185}
1186
1187static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1188{
4a31a93a
MR		 1189 struct adv7604_state *state = to_state(sd);
1190
1191 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1192}
1193
1194static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1195{
d42010a1
LPC		 1196 struct adv7604_state *state = to_state(sd);
1197 const struct adv7604_chip_info *info = state->info;
1198
1199 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1200}
1201
bb88f325
MB		 1202static inline bool is_hdmi(struct v4l2_subdev *sd)
1203{
1204 return hdmi_read(sd, 0x05) & 0x80;
1205}
1206
54450f59
HV		 1207static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1208{
d42010a1
LPC		 1209 struct adv7604_state *state = to_state(sd);
1210
1211 /*
1212 * Chips without a AFE don't expose registers for the SSPD, so just assume
1213 * that we have a lock.
1214 */
1215 if (adv7604_has_afe(state))
1216 return false;
1217
54450f59
HV		 1218 /* TODO channel 2 */
1219 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1220}
1221
1222static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1223{
1224 /* TODO channel 2 */
1225 return !(cp_read(sd, 0xb1) & 0x80);
1226}
1227
1228static inline bool no_signal(struct v4l2_subdev *sd)
1229{
54450f59
HV		 1230 bool ret;
1231
1232 ret = no_power(sd);
1233
1234 ret |= no_lock_stdi(sd);
1235 ret |= no_lock_sspd(sd);
1236
4a31a93a 1237 if (is_digital_input(sd)) {
54450f59
HV		 1238 ret |= no_lock_tmds(sd);
1239 ret |= no_signal_tmds(sd);
1240 }
1241
1242 return ret;
1243}
1244
1245static inline bool no_lock_cp(struct v4l2_subdev *sd)
1246{
d42010a1
LPC		 1247 struct adv7604_state *state = to_state(sd);
1248
1249 if (!adv7604_has_afe(state))
1250 return false;
1251
54450f59
HV		 1252 /* CP has detected a non standard number of lines on the incoming
1253 video compared to what it is configured to receive by s_dv_timings */
1254 return io_read(sd, 0x12) & 0x01;
1255}
1256
58514625 1257static inline bool in_free_run(struct v4l2_subdev *sd)
1258{
1259 return cp_read(sd, 0xff) & 0x10;
1260}
1261
54450f59
HV		 1262static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1263{
54450f59
HV		 1264 *status = 0;
1265 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1266 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1267 if (!in_free_run(sd) && no_lock_cp(sd))
1268 *status |= is_digital_input(sd) ?
1269 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1270
1271 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1272
1273 return 0;
1274}
1275
1276/* ----------------------------------------------------------------------- */
1277
54450f59
HV		 1278struct stdi_readback {
1279 u16 bl, lcf, lcvs;
1280 u8 hs_pol, vs_pol;
1281 bool interlaced;
1282};
1283
1284static int stdi2dv_timings(struct v4l2_subdev *sd,
1285 struct stdi_readback *stdi,
1286 struct v4l2_dv_timings *timings)
1287{
1288 struct adv7604_state *state = to_state(sd);
1289 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1290 u32 pix_clk;
1291 int i;
1292
1293 for (i = 0; adv7604_timings[i].bt.height; i++) {
1294 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1295 continue;
1296 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1297 continue;
1298
1299 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1300
1301 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1302 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1303 *timings = adv7604_timings[i];
1304 return 0;
1305 }
1306 }
1307
1308 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1309 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1310 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1311 timings))
1312 return 0;
1313 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1314 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1315 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1316 state->aspect_ratio, timings))
1317 return 0;
1318
ccbd5bc4
HV		 1319 v4l2_dbg(2, debug, sd,
1320 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1321 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1322 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1323 return -1;
1324}
1325
d42010a1 1326
54450f59
HV		 1327static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1328{
d42010a1
LPC		 1329 struct adv7604_state *state = to_state(sd);
1330 const struct adv7604_chip_info *info = state->info;
4a2ccdd2
LP		 1331 u8 polarity;
1332
54450f59
HV		 1333 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1334 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1335 return -1;
1336 }
1337
1338 /* read STDI */
51182a94 1339 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1340 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1341 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1342 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1343
d42010a1
LPC		 1344 if (adv7604_has_afe(state)) {
1345 /* read SSPD */
1346 polarity = cp_read(sd, 0xb5);
1347 if ((polarity & 0x03) == 0x01) {
1348 stdi->hs_pol = polarity & 0x10
1349 ? (polarity & 0x08 ? '+' : '-') : 'x';
1350 stdi->vs_pol = polarity & 0x40
1351 ? (polarity & 0x20 ? '+' : '-') : 'x';
1352 } else {
1353 stdi->hs_pol = 'x';
1354 stdi->vs_pol = 'x';
1355 }
54450f59 1356 } else {
d42010a1
LPC		 1357 polarity = hdmi_read(sd, 0x05);
1358 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1359 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1360 }
1361
1362 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1363 v4l2_dbg(2, debug, sd,
1364 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1365 return -1;
1366 }
1367
1368 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1369 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1370 memset(stdi, 0, sizeof(struct stdi_readback));
1371 return -1;
1372 }
1373
1374 v4l2_dbg(2, debug, sd,
1375 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1376 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1377 stdi->hs_pol, stdi->vs_pol,
1378 stdi->interlaced ? "interlaced" : "progressive");
1379
1380 return 0;
1381}
1382
1383static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1384 struct v4l2_enum_dv_timings *timings)
1385{
afec5599
LP		 1386 struct adv7604_state *state = to_state(sd);
1387
54450f59
HV		 1388 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1389 return -EINVAL;
afec5599
LP		 1390
1391 if (timings->pad >= state->source_pad)
1392 return -EINVAL;
1393
54450f59
HV		 1394 memset(timings->reserved, 0, sizeof(timings->reserved));
1395 timings->timings = adv7604_timings[timings->index];
1396 return 0;
1397}
1398
7515e096
LP		 1399static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1400 struct v4l2_dv_timings_cap *cap)
54450f59 1401{
7515e096
LP		 1402 struct adv7604_state *state = to_state(sd);
1403
1404 if (cap->pad >= state->source_pad)
1405 return -EINVAL;
1406
54450f59
HV		 1407 cap->type = V4L2_DV_BT_656_1120;
1408 cap->bt.max_width = 1920;
1409 cap->bt.max_height = 1200;
fe9c2564 1410 cap->bt.min_pixelclock = 25000000;
afec5599 1411
7515e096 1412 switch (cap->pad) {
afec5599
LP		 1413 case ADV7604_PAD_HDMI_PORT_A:
1414 case ADV7604_PAD_HDMI_PORT_B:
1415 case ADV7604_PAD_HDMI_PORT_C:
1416 case ADV7604_PAD_HDMI_PORT_D:
54450f59 1417 cap->bt.max_pixelclock = 225000000;
afec5599
LP		 1418 break;
1419 case ADV7604_PAD_VGA_RGB:
1420 case ADV7604_PAD_VGA_COMP:
1421 default:
54450f59 1422 cap->bt.max_pixelclock = 170000000;
afec5599
LP		 1423 break;
1424 }
1425
54450f59
HV		 1426 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1427 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1428 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1429 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1430 return 0;
1431}
1432
1433/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1434 if the format is listed in adv7604_timings[] */
1435static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1436 struct v4l2_dv_timings *timings)
1437{
54450f59
HV		 1438 int i;
1439
1440 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1441 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
4a31a93a 1442 is_digital_input(sd) ? 250000 : 1000000)) {
54450f59
HV		 1443 *timings = adv7604_timings[i];
1444 break;
1445 }
1446 }
1447}
1448
d42010a1
LPC		 1449static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1450{
1451 unsigned int freq;
1452 int a, b;
1453
1454 a = hdmi_read(sd, 0x06);
1455 b = hdmi_read(sd, 0x3b);
1456 if (a < 0 || b < 0)
1457 return 0;
1458 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1459
1460 if (is_hdmi(sd)) {
1461 /* adjust for deep color mode */
1462 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1463
1464 freq = freq * 8 / bits_per_channel;
1465 }
1466
1467 return freq;
1468}
1469
1470static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1471{
1472 int a, b;
1473
1474 a = hdmi_read(sd, 0x51);
1475 b = hdmi_read(sd, 0x52);
1476 if (a < 0 || b < 0)
1477 return 0;
1478 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1479}
1480
54450f59
HV		 1481static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1482 struct v4l2_dv_timings *timings)
1483{
1484 struct adv7604_state *state = to_state(sd);
d42010a1 1485 const struct adv7604_chip_info *info = state->info;
54450f59
HV		 1486 struct v4l2_bt_timings *bt = &timings->bt;
1487 struct stdi_readback stdi;
1488
1489 if (!timings)
1490 return -EINVAL;
1491
1492 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1493
1494 if (no_signal(sd)) {
1e0b9156 1495 state->restart_stdi_once = true;
54450f59
HV		 1496 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1497 return -ENOLINK;
1498 }
1499
1500 /* read STDI */
1501 if (read_stdi(sd, &stdi)) {
1502 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1503 return -ENOLINK;
1504 }
1505 bt->interlaced = stdi.interlaced ?
1506 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1507
4a31a93a 1508 if (is_digital_input(sd)) {
54450f59
HV		 1509 timings->type = V4L2_DV_BT_656_1120;
1510
d42010a1 1511 /* FIXME: All masks are incorrect for ADV7611 */
51182a94
LP		 1512 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1513 bt->height = hdmi_read16(sd, 0x09, 0xfff);
d42010a1 1514 bt->pixelclock = info->read_hdmi_pixelclock(sd);
51182a94
LP		 1515 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1516 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1517 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1518 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1519 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1520 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
54450f59
HV		 1521 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1522 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1523 if (bt->interlaced == V4L2_DV_INTERLACED) {
51182a94
LP		 1524 bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1525 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1526 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
f8789e6d 1527 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
54450f59
HV		 1528 }
1529 adv7604_fill_optional_dv_timings_fields(sd, timings);
1530 } else {
1531 /* find format
80939647 1532 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1533 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1534 */
1535 if (!stdi2dv_timings(sd, &stdi, timings))
1536 goto found;
1537 stdi.lcvs += 1;
1538 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1539 if (!stdi2dv_timings(sd, &stdi, timings))
1540 goto found;
1541 stdi.lcvs -= 2;
1542 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1543 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1544 /*
1545 * The STDI block may measure wrong values, especially
1546 * for lcvs and lcf. If the driver can not find any
1547 * valid timing, the STDI block is restarted to measure
1548 * the video timings again. The function will return an
1549 * error, but the restart of STDI will generate a new
1550 * STDI interrupt and the format detection process will
1551 * restart.
1552 */
1553 if (state->restart_stdi_once) {
1554 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1555 /* TODO restart STDI for Sync Channel 2 */
1556 /* enter one-shot mode */
22d97e56 1557 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1558 /* trigger STDI restart */
22d97e56 1559 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1560 /* reset to continuous mode */
22d97e56 1561 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1562 state->restart_stdi_once = false;
1563 return -ENOLINK;
1564 }
54450f59
HV		 1565 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1566 return -ERANGE;
1567 }
cf9afb1d 1568 state->restart_stdi_once = true;
54450f59
HV		 1569 }
1570found:
1571
1572 if (no_signal(sd)) {
1573 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1574 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1575 return -ENOLINK;
1576 }
1577
4a31a93a
MR		 1578 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1579 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1580 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1581 __func__, (u32)bt->pixelclock);
1582 return -ERANGE;
1583 }
1584
1585 if (debug > 1)
11d034c8
HV		 1586 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1587 timings, true);
54450f59
HV		 1588
1589 return 0;
1590}
1591
1592static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1593 struct v4l2_dv_timings *timings)
1594{
1595 struct adv7604_state *state = to_state(sd);
1596 struct v4l2_bt_timings *bt;
ccbd5bc4 1597 int err;
54450f59
HV		 1598
1599 if (!timings)
1600 return -EINVAL;
1601
d48eb48c
MR		 1602 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1603 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1604 return 0;
1605 }
1606
54450f59
HV		 1607 bt = &timings->bt;
1608
4a31a93a
MR		 1609 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1610 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1611 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1612 __func__, (u32)bt->pixelclock);
1613 return -ERANGE;
1614 }
ccbd5bc4 1615
54450f59
HV		 1616 adv7604_fill_optional_dv_timings_fields(sd, timings);
1617
1618 state->timings = *timings;
1619
22d97e56 1620 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1621
1622 /* Use prim_mode and vid_std when available */
1623 err = configure_predefined_video_timings(sd, timings);
1624 if (err) {
1625 /* custom settings when the video format
1626 does not have prim_mode/vid_std */
1627 configure_custom_video_timings(sd, bt);
1628 }
54450f59
HV		 1629
1630 set_rgb_quantization_range(sd);
1631
54450f59 1632 if (debug > 1)
11d034c8
HV		 1633 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1634 timings, true);
54450f59
HV		 1635 return 0;
1636}
1637
1638static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1639 struct v4l2_dv_timings *timings)
1640{
1641 struct adv7604_state *state = to_state(sd);
1642
1643 *timings = state->timings;
1644 return 0;
1645}
1646
d42010a1
LPC		 1647static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1648{
1649 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1650}
1651
1652static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1653{
1654 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1655}
1656
6b0d5d34 1657static void enable_input(struct v4l2_subdev *sd)
54450f59 1658{
6b0d5d34
HV		 1659 struct adv7604_state *state = to_state(sd);
1660
4a31a93a 1661 if (is_analog_input(sd)) {
54450f59 1662 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1663 } else if (is_digital_input(sd)) {
22d97e56 1664 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1665 state->info->set_termination(sd, true);
54450f59 1666 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1667 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1668 } else {
1669 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1670 __func__, state->selected_input);
54450f59
HV		 1671 }
1672}
1673
1674static void disable_input(struct v4l2_subdev *sd)
1675{
d42010a1
LPC		 1676 struct adv7604_state *state = to_state(sd);
1677
22d97e56 1678 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1679 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1680 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1681 state->info->set_termination(sd, false);
54450f59
HV		 1682}
1683
6b0d5d34 1684static void select_input(struct v4l2_subdev *sd)
54450f59 1685{
6b0d5d34 1686 struct adv7604_state *state = to_state(sd);
d42010a1 1687 const struct adv7604_chip_info *info = state->info;
54450f59 1688
4a31a93a 1689 if (is_analog_input(sd)) {
d42010a1 1690 adv7604_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1691
1692 afe_write(sd, 0x00, 0x08); /* power up ADC */
1693 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1694 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1695 } else if (is_digital_input(sd)) {
1696 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1697
d42010a1
LPC		 1698 adv7604_write_reg_seq(sd, info->recommended_settings[1]);
1699
1700 if (adv7604_has_afe(state)) {
1701 afe_write(sd, 0x00, 0xff); /* power down ADC */
1702 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1703 afe_write(sd, 0xc8, 0x40); /* phase control */
1704 }
1705
54450f59
HV		 1706 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1707 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1708 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1709 } else {
1710 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1711 __func__, state->selected_input);
54450f59
HV		 1712 }
1713}
1714
1715static int adv7604_s_routing(struct v4l2_subdev *sd,
1716 u32 input, u32 output, u32 config)
1717{
1718 struct adv7604_state *state = to_state(sd);
1719
ff4f80fd
MR		 1720 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1721 __func__, input, state->selected_input);
1722
1723 if (input == state->selected_input)
1724 return 0;
54450f59 1725
d42010a1
LPC		 1726 if (input > state->info->max_port)
1727 return -EINVAL;
1728
4a31a93a 1729 state->selected_input = input;
54450f59
HV		 1730
1731 disable_input(sd);
1732
6b0d5d34 1733 select_input(sd);
54450f59 1734
6b0d5d34 1735 enable_input(sd);
54450f59
HV		 1736
1737 return 0;
1738}
1739
539b33b0
LP		 1740static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
1741 struct v4l2_subdev_fh *fh,
1742 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1743{
539b33b0
LP		 1744 struct adv7604_state *state = to_state(sd);
1745
1746 if (code->index >= state->info->nformats)
54450f59 1747 return -EINVAL;
539b33b0
LP		 1748
1749 code->code = state->info->formats[code->index].code;
1750
54450f59
HV		 1751 return 0;
1752}
1753
539b33b0
LP		 1754static void adv7604_fill_format(struct adv7604_state *state,
1755 struct v4l2_mbus_framefmt *format)
54450f59 1756{
539b33b0 1757 memset(format, 0, sizeof(*format));
54450f59 1758
539b33b0
LP		 1759 format->width = state->timings.bt.width;
1760 format->height = state->timings.bt.height;
1761 format->field = V4L2_FIELD_NONE;
1762
1763 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
1764 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1765 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1766}
1767
1768/*
1769 * Compute the op_ch_sel value required to obtain on the bus the component order
1770 * corresponding to the selected format taking into account bus reordering
1771 * applied by the board at the output of the device.
1772 *
1773 * The following table gives the op_ch_value from the format component order
1774 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1775 * adv7604_bus_order value in row).
1776 *
1777 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1778 * ----------+-------------------------------------------------
1779 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1780 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1781 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1782 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1783 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1784 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1785 */
1786static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
1787{
1788#define _SEL(a,b,c,d,e,f) { \
1789 ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
1790 ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
1791#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1792
1793 static const unsigned int op_ch_sel[6][6] = {
1794 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1795 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1796 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1797 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1798 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1799 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1800 };
1801
1802 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1803}
1804
1805static void adv7604_setup_format(struct adv7604_state *state)
1806{
1807 struct v4l2_subdev *sd = &state->sd;
1808
22d97e56 1809 io_write_clr_set(sd, 0x02, 0x02,
539b33b0
LP		 1810 state->format->rgb_out ? ADV7604_RGB_OUT : 0);
1811 io_write(sd, 0x03, state->format->op_format_sel |
1812 state->pdata.op_format_mode_sel);
22d97e56
LP		 1813 io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
1814 io_write_clr_set(sd, 0x05, 0x01,
539b33b0
LP		 1815 state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
1816}
1817
1818static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1819 struct v4l2_subdev_format *format)
1820{
1821 struct adv7604_state *state = to_state(sd);
1822
1823 if (format->pad != state->source_pad)
1824 return -EINVAL;
1825
1826 adv7604_fill_format(state, &format->format);
1827
1828 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1829 struct v4l2_mbus_framefmt *fmt;
1830
1831 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1832 format->format.code = fmt->code;
1833 } else {
1834 format->format.code = state->format->code;
54450f59 1835 }
539b33b0
LP		 1836
1837 return 0;
1838}
1839
1840static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1841 struct v4l2_subdev_format *format)
1842{
1843 struct adv7604_state *state = to_state(sd);
1844 const struct adv7604_format_info *info;
1845
1846 if (format->pad != state->source_pad)
1847 return -EINVAL;
1848
1849 info = adv7604_format_info(state, format->format.code);
1850 if (info == NULL)
f5fe58fd 1851 info = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0
LP		 1852
1853 adv7604_fill_format(state, &format->format);
1854 format->format.code = info->code;
1855
1856 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1857 struct v4l2_mbus_framefmt *fmt;
1858
1859 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1860 fmt->code = format->format.code;
1861 } else {
1862 state->format = info;
1863 adv7604_setup_format(state);
1864 }
1865
54450f59
HV		 1866 return 0;
1867}
1868
1869static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1870{
d42010a1
LPC		 1871 struct adv7604_state *state = to_state(sd);
1872 const struct adv7604_chip_info *info = state->info;
f24d229c
MR		 1873 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1874 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1875 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1876 u8 fmt_change_digital;
1877 u8 fmt_change;
1878 u8 tx_5v;
1879
1880 if (irq_reg_0x43)
1881 io_write(sd, 0x44, irq_reg_0x43);
1882 if (irq_reg_0x70)
1883 io_write(sd, 0x71, irq_reg_0x70);
1884 if (irq_reg_0x6b)
1885 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1886
ff4f80fd
MR		 1887 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1888
54450f59 1889 /* format change */
f24d229c 1890 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1891 fmt_change_digital = is_digital_input(sd)
1892 ? irq_reg_0x6b & info->fmt_change_digital_mask
1893 : 0;
14d03233 1894
54450f59
HV		 1895 if (fmt_change || fmt_change_digital) {
1896 v4l2_dbg(1, debug, sd,
25a64ac9 1897 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1898 __func__, fmt_change, fmt_change_digital);
25a64ac9 1899
14d03233 1900 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
25a64ac9 1901
54450f59
HV		 1902 if (handled)
1903 *handled = true;
1904 }
f24d229c
MR		 1905 /* HDMI/DVI mode */
1906 if (irq_reg_0x6b & 0x01) {
1907 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1908 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1909 set_rgb_quantization_range(sd);
1910 if (handled)
1911 *handled = true;
1912 }
1913
54450f59 1914 /* tx 5v detect */
d42010a1 1915 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
54450f59
HV		 1916 if (tx_5v) {
1917 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1918 io_write(sd, 0x71, tx_5v);
1919 adv7604_s_detect_tx_5v_ctrl(sd);
1920 if (handled)
1921 *handled = true;
1922 }
1923 return 0;
1924}
1925
b09dfac8 1926static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59
HV		 1927{
1928 struct adv7604_state *state = to_state(sd);
4a31a93a 1929 u8 *data = NULL;
54450f59 1930
dd9ac11a 1931 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1932
1933 switch (edid->pad) {
c784b1e2
LP		 1934 case ADV7604_PAD_HDMI_PORT_A:
1935 case ADV7604_PAD_HDMI_PORT_B:
1936 case ADV7604_PAD_HDMI_PORT_C:
1937 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1938 if (state->edid.present & (1 << edid->pad))
1939 data = state->edid.edid;
1940 break;
1941 default:
1942 return -EINVAL;
4a31a93a 1943 }
dd9ac11a
HV		 1944
1945 if (edid->start_block == 0 && edid->blocks == 0) {
1946 edid->blocks = data ? state->edid.blocks : 0;
1947 return 0;
1948 }
1949
1950 if (data == NULL)
4a31a93a
MR		 1951 return -ENODATA;
1952
dd9ac11a
HV		 1953 if (edid->start_block >= state->edid.blocks)
1954 return -EINVAL;
1955
1956 if (edid->start_block + edid->blocks > state->edid.blocks)
1957 edid->blocks = state->edid.blocks - edid->start_block;
1958
1959 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1960
54450f59
HV		 1961 return 0;
1962}
1963
dd08beb9 1964static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1965{
1966 u8 d;
1967
1968 if ((edid[0x7e] != 1) ||
1969 (edid[0x80] != 0x02) ||
1970 (edid[0x81] != 0x03)) {
1971 return -1;
1972 }
1973
1974 /* search Vendor Specific Data Block (tag 3) */
1975 d = edid[0x82] & 0x7f;
1976 if (d > 4) {
1977 int i = 0x84;
1978 int end = 0x80 + d;
1979
1980 do {
1981 u8 tag = edid[i] >> 5;
1982 u8 len = edid[i] & 0x1f;
1983
1984 if ((tag == 3) && (len >= 5))
1985 return i + 4;
1986 i += len + 1;
1987 } while (i < end);
1988 }
1989 return -1;
1990}
1991
b09dfac8 1992static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59
HV		 1993{
1994 struct adv7604_state *state = to_state(sd);
d42010a1 1995 const struct adv7604_chip_info *info = state->info;
dd08beb9 1996 int spa_loc;
54450f59 1997 int err;
dd08beb9 1998 int i;
54450f59 1999
dd9ac11a
HV		 2000 memset(edid->reserved, 0, sizeof(edid->reserved));
2001
c784b1e2 2002 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2003 return -EINVAL;
2004 if (edid->start_block != 0)
2005 return -EINVAL;
2006 if (edid->blocks == 0) {
3e86aa85 2007 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2008 state->edid.present &= ~(1 << edid->pad);
e9d50e9e 2009 adv7604_set_hpd(state, state->edid.present);
22d97e56 2010 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2011
54450f59
HV		 2012 /* Fall back to a 16:9 aspect ratio */
2013 state->aspect_ratio.numerator = 16;
2014 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2015
2016 if (!state->edid.present)
2017 state->edid.blocks = 0;
2018
2019 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2020 __func__, edid->pad, state->edid.present);
54450f59
HV		 2021 return 0;
2022 }
4a31a93a
MR		 2023 if (edid->blocks > 2) {
2024 edid->blocks = 2;
54450f59 2025 return -E2BIG;
4a31a93a 2026 }
4a31a93a 2027
dd08beb9
MR		 2028 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2029 __func__, edid->pad, state->edid.present);
2030
3e86aa85 2031 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2032 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
e9d50e9e 2033 adv7604_set_hpd(state, 0);
22d97e56 2034 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2035
dd08beb9
MR		 2036 spa_loc = get_edid_spa_location(edid->edid);
2037 if (spa_loc < 0)
2038 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2039
3e86aa85 2040 switch (edid->pad) {
c784b1e2 2041 case ADV7604_PAD_HDMI_PORT_A:
dd08beb9
MR		 2042 state->spa_port_a[0] = edid->edid[spa_loc];
2043 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2044 break;
c784b1e2 2045 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2046 rep_write(sd, 0x70, edid->edid[spa_loc]);
2047 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2048 break;
c784b1e2 2049 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2050 rep_write(sd, 0x72, edid->edid[spa_loc]);
2051 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2052 break;
c784b1e2 2053 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2054 rep_write(sd, 0x74, edid->edid[spa_loc]);
2055 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2056 break;
dd08beb9
MR		 2057 default:
2058 return -EINVAL;
3e86aa85 2059 }
d42010a1
LPC		 2060
2061 if (info->type == ADV7604) {
2062 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2063 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2064 } else {
2065 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2066 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2067 }
3e86aa85 2068
dd08beb9
MR		 2069 edid->edid[spa_loc] = state->spa_port_a[0];
2070 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2071
2072 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2073 state->edid.blocks = edid->blocks;
54450f59
HV		 2074 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2075 edid->edid[0x16]);
3e86aa85 2076 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2077
2078 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2079 if (err < 0) {
3e86aa85 2080 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2081 return err;
2082 }
2083
dd08beb9
MR		 2084 /* adv7604 calculates the checksums and enables I2C access to internal
2085 EDID RAM from DDC port. */
22d97e56 2086 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2087
2088 for (i = 0; i < 1000; i++) {
d42010a1 2089 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2090 break;
2091 mdelay(1);
2092 }
2093 if (i == 1000) {
2094 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2095 return -EIO;
2096 }
2097
4a31a93a
MR		 2098 /* enable hotplug after 100 ms */
2099 queue_delayed_work(state->work_queues,
2100 &state->delayed_work_enable_hotplug, HZ / 10);
2101 return 0;
54450f59
HV		 2102}
2103
2104/*********** avi info frame CEA-861-E **************/
2105
2106static void print_avi_infoframe(struct v4l2_subdev *sd)
2107{
2108 int i;
2109 u8 buf[14];
2110 u8 avi_len;
2111 u8 avi_ver;
2112
bb88f325 2113 if (!is_hdmi(sd)) {
54450f59
HV		 2114 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2115 return;
2116 }
2117 if (!(io_read(sd, 0x60) & 0x01)) {
2118 v4l2_info(sd, "AVI infoframe not received\n");
2119 return;
2120 }
2121
2122 if (io_read(sd, 0x83) & 0x01) {
2123 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2124 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2125 if (io_read(sd, 0x83) & 0x01) {
2126 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2127 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2128 }
2129 }
2130
2131 avi_len = infoframe_read(sd, 0xe2);
2132 avi_ver = infoframe_read(sd, 0xe1);
2133 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2134 avi_ver, avi_len);
2135
2136 if (avi_ver != 0x02)
2137 return;
2138
2139 for (i = 0; i < 14; i++)
2140 buf[i] = infoframe_read(sd, i);
2141
2142 v4l2_info(sd,
2143 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2144 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2145 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2146}
2147
2148static int adv7604_log_status(struct v4l2_subdev *sd)
2149{
2150 struct adv7604_state *state = to_state(sd);
d42010a1 2151 const struct adv7604_chip_info *info = state->info;
54450f59
HV		 2152 struct v4l2_dv_timings timings;
2153 struct stdi_readback stdi;
2154 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2155 u8 edid_enabled;
2156 u8 cable_det;
54450f59 2157
f216ccb3 2158 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2159 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2160 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2161 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2162 "reserved", "reserved", "reserved", "reserved", "manual"
2163 };
f216ccb3 2164 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2165 "RGB limited range (16-235)", "RGB full range (0-255)",
2166 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2167 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2168 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2169 "invalid", "invalid", "invalid", "invalid", "invalid",
2170 "invalid", "invalid", "automatic"
2171 };
f216ccb3 2172 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2173 "Automatic",
2174 "RGB limited range (16-235)",
2175 "RGB full range (0-255)",
2176 };
f216ccb3 2177 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2178 "8-bits per channel",
2179 "10-bits per channel",
2180 "12-bits per channel",
2181 "16-bits per channel (not supported)"
2182 };
54450f59
HV		 2183
2184 v4l2_info(sd, "-----Chip status-----\n");
2185 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2186 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2187 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2188 ((edid_enabled & 0x01) ? "Yes" : "No"),
2189 ((edid_enabled & 0x02) ? "Yes" : "No"),
2190 ((edid_enabled & 0x04) ? "Yes" : "No"),
2191 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2192 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2193 "enabled" : "disabled");
2194
2195 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2196 cable_det = info->read_cable_det(sd);
4a31a93a 2197 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2198 ((cable_det & 0x01) ? "Yes" : "No"),
2199 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2200 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2201 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2202 v4l2_info(sd, "TMDS signal detected: %s\n",
2203 no_signal_tmds(sd) ? "false" : "true");
2204 v4l2_info(sd, "TMDS signal locked: %s\n",
2205 no_lock_tmds(sd) ? "false" : "true");
2206 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2207 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2208 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2209 v4l2_info(sd, "CP free run: %s\n",
58514625 2210 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2211 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2212 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2213 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2214
2215 v4l2_info(sd, "-----Video Timings-----\n");
2216 if (read_stdi(sd, &stdi))
2217 v4l2_info(sd, "STDI: not locked\n");
2218 else
2219 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2220 stdi.lcf, stdi.bl, stdi.lcvs,
2221 stdi.interlaced ? "interlaced" : "progressive",
2222 stdi.hs_pol, stdi.vs_pol);
2223 if (adv7604_query_dv_timings(sd, &timings))
2224 v4l2_info(sd, "No video detected\n");
2225 else
11d034c8
HV		 2226 v4l2_print_dv_timings(sd->name, "Detected format: ",
2227 &timings, true);
2228 v4l2_print_dv_timings(sd->name, "Configured format: ",
2229 &state->timings, true);
54450f59 2230
76eb2d30
MR		 2231 if (no_signal(sd))
2232 return 0;
2233
54450f59
HV		 2234 v4l2_info(sd, "-----Color space-----\n");
2235 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2236 rgb_quantization_range_txt[state->rgb_quantization_range]);
2237 v4l2_info(sd, "Input color space: %s\n",
2238 input_color_space_txt[reg_io_0x02 >> 4]);
2239 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2240 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2241 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2242 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 2243 "enabled" : "disabled");
54450f59 2244 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2245 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2246
4a31a93a 2247 if (!is_digital_input(sd))
76eb2d30
MR		 2248 return 0;
2249
2250 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2251 v4l2_info(sd, "Digital video port selected: %c\n",
2252 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2253 v4l2_info(sd, "HDCP encrypted content: %s\n",
2254 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2255 v4l2_info(sd, "HDCP keys read: %s%s\n",
2256 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2257 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2258 if (is_hdmi(sd)) {
76eb2d30
MR		 2259 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2260 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2261 bool audio_mute = io_read(sd, 0x65) & 0x40;
2262
2263 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2264 audio_pll_locked ? "locked" : "not locked",
2265 audio_sample_packet_detect ? "detected" : "not detected",
2266 audio_mute ? "muted" : "enabled");
2267 if (audio_pll_locked && audio_sample_packet_detect) {
2268 v4l2_info(sd, "Audio format: %s\n",
2269 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2270 }
2271 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2272 (hdmi_read(sd, 0x5c) << 8) +
2273 (hdmi_read(sd, 0x5d) & 0xf0));
2274 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2275 (hdmi_read(sd, 0x5e) << 8) +
2276 hdmi_read(sd, 0x5f));
2277 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2278
2279 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2280
54450f59
HV		 2281 print_avi_infoframe(sd);
2282 }
2283
2284 return 0;
2285}
2286
2287/* ----------------------------------------------------------------------- */
2288
2289static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
2290 .s_ctrl = adv7604_s_ctrl,
2291};
2292
2293static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2294 .log_status = adv7604_log_status,
54450f59
HV		 2295 .interrupt_service_routine = adv7604_isr,
2296#ifdef CONFIG_VIDEO_ADV_DEBUG
2297 .g_register = adv7604_g_register,
2298 .s_register = adv7604_s_register,
2299#endif
2300};
2301
2302static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2303 .s_routing = adv7604_s_routing,
2304 .g_input_status = adv7604_g_input_status,
2305 .s_dv_timings = adv7604_s_dv_timings,
2306 .g_dv_timings = adv7604_g_dv_timings,
2307 .query_dv_timings = adv7604_query_dv_timings,
54450f59
HV		 2308};
2309
2310static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
539b33b0
LP		 2311 .enum_mbus_code = adv7604_enum_mbus_code,
2312 .get_fmt = adv7604_get_format,
2313 .set_fmt = adv7604_set_format,
54450f59
HV		 2314 .get_edid = adv7604_get_edid,
2315 .set_edid = adv7604_set_edid,
7515e096 2316 .dv_timings_cap = adv7604_dv_timings_cap,
afec5599 2317 .enum_dv_timings = adv7604_enum_dv_timings,
54450f59
HV		 2318};
2319
2320static const struct v4l2_subdev_ops adv7604_ops = {
2321 .core = &adv7604_core_ops,
2322 .video = &adv7604_video_ops,
2323 .pad = &adv7604_pad_ops,
2324};
2325
2326/* -------------------------- custom ctrls ---------------------------------- */
2327
2328static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2329 .ops = &adv7604_ctrl_ops,
2330 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2331 .name = "Analog Sampling Phase",
2332 .type = V4L2_CTRL_TYPE_INTEGER,
2333 .min = 0,
2334 .max = 0x1f,
2335 .step = 1,
2336 .def = 0,
2337};
2338
2339static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2340 .ops = &adv7604_ctrl_ops,
2341 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2342 .name = "Free Running Color, Manual",
2343 .type = V4L2_CTRL_TYPE_BOOLEAN,
2344 .min = false,
2345 .max = true,
2346 .step = 1,
2347 .def = false,
2348};
2349
2350static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2351 .ops = &adv7604_ctrl_ops,
2352 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2353 .name = "Free Running Color",
2354 .type = V4L2_CTRL_TYPE_INTEGER,
2355 .min = 0x0,
2356 .max = 0xffffff,
2357 .step = 0x1,
2358 .def = 0x0,
2359};
2360
2361/* ----------------------------------------------------------------------- */
2362
2363static int adv7604_core_init(struct v4l2_subdev *sd)
2364{
2365 struct adv7604_state *state = to_state(sd);
d42010a1 2366 const struct adv7604_chip_info *info = state->info;
54450f59
HV		 2367 struct adv7604_platform_data *pdata = &state->pdata;
2368
2369 hdmi_write(sd, 0x48,
2370 (pdata->disable_pwrdnb ? 0x80 : 0) |
2371 (pdata->disable_cable_det_rst ? 0x40 : 0));
2372
2373 disable_input(sd);
2374
5ef54b59
LP		 2375 if (pdata->default_input >= 0 &&
2376 pdata->default_input < state->source_pad) {
2377 state->selected_input = pdata->default_input;
2378 select_input(sd);
2379 enable_input(sd);
2380 }
2381
54450f59
HV		 2382 /* power */
2383 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2384 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2385 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2386
2387 /* video format */
22d97e56 2388 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2389 pdata->alt_gamma << 3 |
2390 pdata->op_656_range << 2 |
54450f59 2391 pdata->alt_data_sat << 0);
22d97e56 2392 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2393 pdata->insert_av_codes << 2 |
2394 pdata->replicate_av_codes << 1);
2395 adv7604_setup_format(state);
54450f59 2396
54450f59 2397 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2398
2399 /* VS, HS polarities */
1b5ab875
LP		 2400 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2401 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2402
2403 /* Adjust drive strength */
2404 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2405 pdata->dr_str_clk << 2 |
2406 pdata->dr_str_sync);
2407
54450f59
HV		 2408 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2409 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2410 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2411 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2412 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2413 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2414 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2415 for digital formats */
2416
5474b983 2417 /* HDMI audio */
22d97e56
LP		 2418 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2419 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2420 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2421
54450f59
HV		 2422 /* TODO from platform data */
2423 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2424
d42010a1
LPC		 2425 if (adv7604_has_afe(state)) {
2426 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2427 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2428 }
54450f59 2429
54450f59 2430 /* interrupts */
d42010a1 2431 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2432 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2433 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2434 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2435 info->setup_irqs(sd);
54450f59
HV		 2436
2437 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2438}
2439
d42010a1
LPC		 2440static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2441{
2442 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2443}
2444
2445static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2446{
2447 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2448}
2449
54450f59
HV		 2450static void adv7604_unregister_clients(struct adv7604_state *state)
2451{
05cacb17
LP		 2452 unsigned int i;
2453
2454 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2455 if (state->i2c_clients[i])
2456 i2c_unregister_device(state->i2c_clients[i]);
2457 }
54450f59
HV		 2458}
2459
2460static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2461 u8 addr, u8 io_reg)
2462{
2463 struct i2c_client *client = v4l2_get_subdevdata(sd);
2464
2465 if (addr)
2466 io_write(sd, io_reg, addr << 1);
2467 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2468}
2469
d42010a1
LPC		 2470static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = {
2471 /* reset ADI recommended settings for HDMI: */
2472 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2473 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2474 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2475 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2476 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2477 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2478 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2479 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2480 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2481 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2482 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2483 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2484 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2485
2486 /* set ADI recommended settings for digitizer */
2487 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2488 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2489 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2490 { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2491 { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2492 { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2493
2494 { ADV7604_REG_SEQ_TERM, 0 },
2495};
2496
2497static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = {
2498 /* set ADI recommended settings for HDMI: */
2499 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2500 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2501 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2502 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2503 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2504 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2505 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2506 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2507 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2508 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2509 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2510 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2511
2512 /* reset ADI recommended settings for digitizer */
2513 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2514 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2515 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2516
2517 { ADV7604_REG_SEQ_TERM, 0 },
2518};
2519
2520static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2521 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
d42010a1 2522 { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 },
c41ad9c3
LPC		 2523 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x9b), 0x03 },
2524 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x08 },
2525 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x85), 0x1f },
d42010a1
LPC		 2526 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 },
2527 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda },
2528 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 },
2529 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 },
2530 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 },
2531 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 },
2532 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e },
2533
2534 { ADV7604_REG_SEQ_TERM, 0 },
2535};
2536
2537static const struct adv7604_chip_info adv7604_chip_info[] = {
2538 [ADV7604] = {
2539 .type = ADV7604,
2540 .has_afe = true,
c784b1e2 2541 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2542 .num_dv_ports = 4,
2543 .edid_enable_reg = 0x77,
2544 .edid_status_reg = 0x7d,
2545 .lcf_reg = 0xb3,
2546 .tdms_lock_mask = 0xe0,
2547 .cable_det_mask = 0x1e,
2548 .fmt_change_digital_mask = 0xc1,
80f4944e 2549 .cp_csc = 0xfc,
539b33b0
LP		 2550 .formats = adv7604_formats,
2551 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2552 .set_termination = adv7604_set_termination,
2553 .setup_irqs = adv7604_setup_irqs,
2554 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2555 .read_cable_det = adv7604_read_cable_det,
2556 .recommended_settings = {
2557 [0] = adv7604_recommended_settings_afe,
2558 [1] = adv7604_recommended_settings_hdmi,
2559 },
2560 .num_recommended_settings = {
2561 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2562 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2563 },
2564 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2565 BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) |
2566 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2567 BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) |
2568 BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) |
2569 BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) |
2570 BIT(ADV7604_PAGE_VDP),
2571 },
2572 [ADV7611] = {
2573 .type = ADV7611,
2574 .has_afe = false,
c784b1e2 2575 .max_port = ADV7604_PAD_HDMI_PORT_A,
d42010a1
LPC		 2576 .num_dv_ports = 1,
2577 .edid_enable_reg = 0x74,
2578 .edid_status_reg = 0x76,
2579 .lcf_reg = 0xa3,
2580 .tdms_lock_mask = 0x43,
2581 .cable_det_mask = 0x01,
2582 .fmt_change_digital_mask = 0x03,
80f4944e 2583 .cp_csc = 0xf4,
539b33b0
LP		 2584 .formats = adv7611_formats,
2585 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2586 .set_termination = adv7611_set_termination,
2587 .setup_irqs = adv7611_setup_irqs,
2588 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2589 .read_cable_det = adv7611_read_cable_det,
2590 .recommended_settings = {
2591 [1] = adv7611_recommended_settings_hdmi,
2592 },
2593 .num_recommended_settings = {
2594 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2595 },
2596 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) |
2597 BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) |
2598 BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) |
2599 BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP),
2600 },
2601};
2602
f82f313e
LP		 2603static struct i2c_device_id adv7604_i2c_id[] = {
2604 { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] },
2605 { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] },
2606 { }
2607};
2608MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id);
2609
2610static struct of_device_id adv7604_of_id[] __maybe_unused = {
2611 { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] },
2612 { }
2613};
2614MODULE_DEVICE_TABLE(of, adv7604_of_id);
2615
2616static int adv7604_parse_dt(struct adv7604_state *state)
2617{
6fa88045
LP		 2618 struct v4l2_of_endpoint bus_cfg;
2619 struct device_node *endpoint;
2620 struct device_node *np;
2621 unsigned int flags;
2622
2623 np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node;
2624
2625 /* Parse the endpoint. */
2626 endpoint = of_graph_get_next_endpoint(np, NULL);
2627 if (!endpoint)
2628 return -EINVAL;
2629
2630 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2631 of_node_put(endpoint);
2632
2633 flags = bus_cfg.bus.parallel.flags;
2634
2635 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2636 state->pdata.inv_hs_pol = 1;
2637
2638 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2639 state->pdata.inv_vs_pol = 1;
2640
2641 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2642 state->pdata.inv_llc_pol = 1;
2643
2644 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2645 state->pdata.insert_av_codes = 1;
2646 state->pdata.op_656_range = 1;
2647 }
2648
f82f313e
LP		 2649 /* Disable the interrupt for now as no DT-based board uses it. */
2650 state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED;
2651
2652 /* Use the default I2C addresses. */
2653 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2654 state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40;
2655 state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e;
2656 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2657 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2658 state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26;
2659 state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32;
2660 state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36;
2661 state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34;
2662 state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30;
2663 state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22;
2664 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2665
2666 /* Hardcode the remaining platform data fields. */
2667 state->pdata.disable_pwrdnb = 0;
2668 state->pdata.disable_cable_det_rst = 0;
2669 state->pdata.default_input = -1;
2670 state->pdata.blank_data = 1;
f82f313e 2671 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2672 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2673 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2674
2675 return 0;
2676}
2677
54450f59
HV		 2678static int adv7604_probe(struct i2c_client *client,
2679 const struct i2c_device_id *id)
2680{
591b72fe
HV		 2681 static const struct v4l2_dv_timings cea640x480 =
2682 V4L2_DV_BT_CEA_640X480P59_94;
54450f59 2683 struct adv7604_state *state;
54450f59
HV		 2684 struct v4l2_ctrl_handler *hdl;
2685 struct v4l2_subdev *sd;
c784b1e2 2686 unsigned int i;
d42010a1 2687 u16 val;
54450f59
HV		 2688 int err;
2689
2690 /* Check if the adapter supports the needed features */
2691 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2692 return -EIO;
2693 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2694 client->addr << 1);
2695
c02b211d 2696 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 2697 if (!state) {
2698 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2699 return -ENOMEM;
2700 }
2701
05cacb17 2702 state->i2c_clients[ADV7604_PAGE_IO] = client;
d42010a1 2703
25a64ac9
MR		 2704 /* initialize variables */
2705 state->restart_stdi_once = true;
ff4f80fd 2706 state->selected_input = ~0;
25a64ac9 2707
f82f313e
LP		 2708 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2709 const struct of_device_id *oid;
2710
2711 oid = of_match_node(adv7604_of_id, client->dev.of_node);
2712 state->info = oid->data;
2713
2714 err = adv7604_parse_dt(state);
2715 if (err < 0) {
2716 v4l_err(client, "DT parsing error\n");
2717 return err;
2718 }
2719 } else if (client->dev.platform_data) {
2720 struct adv7604_platform_data *pdata = client->dev.platform_data;
2721
2722 state->info = (const struct adv7604_chip_info *)id->driver_data;
2723 state->pdata = *pdata;
2724 } else {
54450f59 2725 v4l_err(client, "No platform data!\n");
c02b211d 2726 return -ENODEV;
54450f59 2727 }
e9d50e9e
LP		 2728
2729 /* Request GPIOs. */
2730 for (i = 0; i < state->info->num_dv_ports; ++i) {
2731 state->hpd_gpio[i] =
2732 devm_gpiod_get_index(&client->dev, "hpd", i);
2733 if (IS_ERR(state->hpd_gpio[i]))
2734 continue;
2735
9b2c3823 2736 gpiod_direction_output(state->hpd_gpio[i], 0);
e9d50e9e
LP		 2737
2738 v4l_info(client, "Handling HPD %u GPIO\n", i);
2739 }
2740
591b72fe 2741 state->timings = cea640x480;
f5fe58fd 2742 state->format = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 2743
2744 sd = &state->sd;
2745 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
d42010a1
LPC		 2746 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2747 id->name, i2c_adapter_id(client->adapter),
2748 client->addr);
54450f59 2749 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59 2750
d42010a1
LPC		 2751 /*
2752 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2753 * identifies the revision, while on ADV7611 it identifies the model as
2754 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2755 */
2756 if (state->info->type == ADV7604) {
2757 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2758 if (val != 0x68) {
2759 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2760 client->addr << 1);
2761 return -ENODEV;
2762 }
2763 } else {
2764 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2765 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2766 if (val != 0x2051) {
2767 v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2768 client->addr << 1);
2769 return -ENODEV;
2770 }
54450f59
HV		 2771 }
2772
2773 /* control handlers */
2774 hdl = &state->hdl;
d42010a1 2775 v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8);
54450f59
HV		 2776
2777 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2778 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2779 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2780 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2781 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2782 V4L2_CID_SATURATION, 0, 255, 1, 128);
2783 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2784 V4L2_CID_HUE, 0, 128, 1, 0);
2785
2786 /* private controls */
2787 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 2788 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2789 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59
HV		 2790 state->rgb_quantization_range_ctrl =
2791 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2792 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2793 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2794
2795 /* custom controls */
d42010a1
LPC		 2796 if (adv7604_has_afe(state))
2797 state->analog_sampling_phase_ctrl =
2798 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2799 state->free_run_color_manual_ctrl =
2800 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2801 state->free_run_color_ctrl =
2802 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2803
2804 sd->ctrl_handler = hdl;
2805 if (hdl->error) {
2806 err = hdl->error;
2807 goto err_hdl;
2808 }
8c0eadb8
HV		 2809 state->detect_tx_5v_ctrl->is_private = true;
2810 state->rgb_quantization_range_ctrl->is_private = true;
d42010a1
LPC		 2811 if (adv7604_has_afe(state))
2812 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 2813 state->free_run_color_manual_ctrl->is_private = true;
2814 state->free_run_color_ctrl->is_private = true;
2815
54450f59
HV		 2816 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2817 err = -ENODEV;
2818 goto err_hdl;
2819 }
2820
05cacb17
LP		 2821 for (i = 1; i < ADV7604_PAGE_MAX; ++i) {
2822 if (!(BIT(i) & state->info->page_mask))
2823 continue;
54450f59 2824
05cacb17 2825 state->i2c_clients[i] =
f82f313e 2826 adv7604_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 2827 0xf2 + i);
2828 if (state->i2c_clients[i] == NULL) {
d42010a1 2829 err = -ENOMEM;
05cacb17 2830 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 2831 goto err_i2c;
2832 }
2833 }
05cacb17 2834
54450f59
HV		 2835 /* work queues */
2836 state->work_queues = create_singlethread_workqueue(client->name);
2837 if (!state->work_queues) {
2838 v4l2_err(sd, "Could not create work queue\n");
2839 err = -ENOMEM;
2840 goto err_i2c;
2841 }
2842
2843 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2844 adv7604_delayed_work_enable_hotplug);
2845
c784b1e2
LP		 2846 state->source_pad = state->info->num_dv_ports
2847 + (state->info->has_afe ? 2 : 0);
2848 for (i = 0; i < state->source_pad; ++i)
2849 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2850 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2851
2852 err = media_entity_init(&sd->entity, state->source_pad + 1,
2853 state->pads, 0);
54450f59
HV		 2854 if (err)
2855 goto err_work_queues;
2856
2857 err = adv7604_core_init(sd);
2858 if (err)
2859 goto err_entity;
2860 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2861 client->addr << 1, client->adapter->name);
bedc3939
LPC		 2862
2863 err = v4l2_async_register_subdev(sd);
2864 if (err)
2865 goto err_entity;
2866
54450f59
HV		 2867 return 0;
2868
2869err_entity:
2870 media_entity_cleanup(&sd->entity);
2871err_work_queues:
2872 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2873 destroy_workqueue(state->work_queues);
2874err_i2c:
2875 adv7604_unregister_clients(state);
2876err_hdl:
2877 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2878 return err;
2879}
2880
2881/* ----------------------------------------------------------------------- */
2882
2883static int adv7604_remove(struct i2c_client *client)
2884{
2885 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2886 struct adv7604_state *state = to_state(sd);
2887
2888 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2889 destroy_workqueue(state->work_queues);
bedc3939 2890 v4l2_async_unregister_subdev(sd);
54450f59
HV		 2891 v4l2_device_unregister_subdev(sd);
2892 media_entity_cleanup(&sd->entity);
2893 adv7604_unregister_clients(to_state(sd));
2894 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2895 return 0;
2896}
2897
2898/* ----------------------------------------------------------------------- */
2899
54450f59
HV		 2900static struct i2c_driver adv7604_driver = {
2901 .driver = {
2902 .owner = THIS_MODULE,
2903 .name = "adv7604",
f82f313e 2904 .of_match_table = of_match_ptr(adv7604_of_id),
54450f59
HV		 2905 },
2906 .probe = adv7604_probe,
2907 .remove = adv7604_remove,
f82f313e 2908 .id_table = adv7604_i2c_id,
54450f59
HV		 2909};
2910
2911module_i2c_driver(adv7604_driver);
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