]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/media/i2c/adv7604.c
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] adv7604: select YPbPr if RGB_RANGE_FULL/LIMITED is set for VGA_COMP inputs
[mirror_ubuntu-eoan-kernel.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
25764158 41#include <media/v4l2-dv-timings.h>
54450f59
HV		 42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
54450f59
HV		 56/*
57 **********************************************************************
58 *
59 * Arrays with configuration parameters for the ADV7604
60 *
61 **********************************************************************
62 */
63struct adv7604_state {
64 struct adv7604_platform_data pdata;
65 struct v4l2_subdev sd;
66 struct media_pad pad;
67 struct v4l2_ctrl_handler hdl;
4a31a93a 68 enum adv7604_input_port selected_input;
54450f59 69 struct v4l2_dv_timings timings;
4a31a93a
MR		 70 struct {
71 u8 edid[256];
72 u32 present;
73 unsigned blocks;
74 } edid;
54450f59
HV		 75 struct v4l2_fract aspect_ratio;
76 u32 rgb_quantization_range;
77 struct workqueue_struct *work_queues;
78 struct delayed_work delayed_work_enable_hotplug;
79 bool connector_hdmi;
cf9afb1d 80 bool restart_stdi_once;
25a64ac9 81 u32 prev_input_status;
54450f59
HV		 82
83 /* i2c clients */
84 struct i2c_client *i2c_avlink;
85 struct i2c_client *i2c_cec;
86 struct i2c_client *i2c_infoframe;
87 struct i2c_client *i2c_esdp;
88 struct i2c_client *i2c_dpp;
89 struct i2c_client *i2c_afe;
90 struct i2c_client *i2c_repeater;
91 struct i2c_client *i2c_edid;
92 struct i2c_client *i2c_hdmi;
93 struct i2c_client *i2c_test;
94 struct i2c_client *i2c_cp;
95 struct i2c_client *i2c_vdp;
96
97 /* controls */
98 struct v4l2_ctrl *detect_tx_5v_ctrl;
99 struct v4l2_ctrl *analog_sampling_phase_ctrl;
100 struct v4l2_ctrl *free_run_color_manual_ctrl;
101 struct v4l2_ctrl *free_run_color_ctrl;
102 struct v4l2_ctrl *rgb_quantization_range_ctrl;
103};
104
105/* Supported CEA and DMT timings */
106static const struct v4l2_dv_timings adv7604_timings[] = {
107 V4L2_DV_BT_CEA_720X480P59_94,
108 V4L2_DV_BT_CEA_720X576P50,
109 V4L2_DV_BT_CEA_1280X720P24,
110 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 111 V4L2_DV_BT_CEA_1280X720P50,
112 V4L2_DV_BT_CEA_1280X720P60,
113 V4L2_DV_BT_CEA_1920X1080P24,
114 V4L2_DV_BT_CEA_1920X1080P25,
115 V4L2_DV_BT_CEA_1920X1080P30,
116 V4L2_DV_BT_CEA_1920X1080P50,
117 V4L2_DV_BT_CEA_1920X1080P60,
118
ccbd5bc4 119 /* sorted by DMT ID */
54450f59
HV		 120 V4L2_DV_BT_DMT_640X350P85,
121 V4L2_DV_BT_DMT_640X400P85,
122 V4L2_DV_BT_DMT_720X400P85,
123 V4L2_DV_BT_DMT_640X480P60,
124 V4L2_DV_BT_DMT_640X480P72,
125 V4L2_DV_BT_DMT_640X480P75,
126 V4L2_DV_BT_DMT_640X480P85,
127 V4L2_DV_BT_DMT_800X600P56,
128 V4L2_DV_BT_DMT_800X600P60,
129 V4L2_DV_BT_DMT_800X600P72,
130 V4L2_DV_BT_DMT_800X600P75,
131 V4L2_DV_BT_DMT_800X600P85,
132 V4L2_DV_BT_DMT_848X480P60,
133 V4L2_DV_BT_DMT_1024X768P60,
134 V4L2_DV_BT_DMT_1024X768P70,
135 V4L2_DV_BT_DMT_1024X768P75,
136 V4L2_DV_BT_DMT_1024X768P85,
137 V4L2_DV_BT_DMT_1152X864P75,
138 V4L2_DV_BT_DMT_1280X768P60_RB,
139 V4L2_DV_BT_DMT_1280X768P60,
140 V4L2_DV_BT_DMT_1280X768P75,
141 V4L2_DV_BT_DMT_1280X768P85,
142 V4L2_DV_BT_DMT_1280X800P60_RB,
143 V4L2_DV_BT_DMT_1280X800P60,
144 V4L2_DV_BT_DMT_1280X800P75,
145 V4L2_DV_BT_DMT_1280X800P85,
146 V4L2_DV_BT_DMT_1280X960P60,
147 V4L2_DV_BT_DMT_1280X960P85,
148 V4L2_DV_BT_DMT_1280X1024P60,
149 V4L2_DV_BT_DMT_1280X1024P75,
150 V4L2_DV_BT_DMT_1280X1024P85,
151 V4L2_DV_BT_DMT_1360X768P60,
152 V4L2_DV_BT_DMT_1400X1050P60_RB,
153 V4L2_DV_BT_DMT_1400X1050P60,
154 V4L2_DV_BT_DMT_1400X1050P75,
155 V4L2_DV_BT_DMT_1400X1050P85,
156 V4L2_DV_BT_DMT_1440X900P60_RB,
157 V4L2_DV_BT_DMT_1440X900P60,
158 V4L2_DV_BT_DMT_1600X1200P60,
159 V4L2_DV_BT_DMT_1680X1050P60_RB,
160 V4L2_DV_BT_DMT_1680X1050P60,
161 V4L2_DV_BT_DMT_1792X1344P60,
162 V4L2_DV_BT_DMT_1856X1392P60,
163 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 164 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 165 V4L2_DV_BT_DMT_1366X768P60,
166 V4L2_DV_BT_DMT_1920X1080P60,
167 { },
168};
169
ccbd5bc4
HV		 170struct adv7604_video_standards {
171 struct v4l2_dv_timings timings;
172 u8 vid_std;
173 u8 v_freq;
174};
175
176/* sorted by number of lines */
177static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
178 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
179 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
180 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
181 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
182 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
183 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
184 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
185 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
186 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
187 /* TODO add 1920x1080P60_RB (CVT timing) */
188 { },
189};
190
191/* sorted by number of lines */
192static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
208 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
209 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
211 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
212 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
213 /* TODO add 1600X1200P60_RB (not a DMT timing) */
214 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
215 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
216 { },
217};
218
219/* sorted by number of lines */
220static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
221 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
222 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
223 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
224 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
225 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
226 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
227 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
228 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
229 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
230 { },
231};
232
233/* sorted by number of lines */
234static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
235 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
238 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
243 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
247 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
249 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
250 { },
251};
252
54450f59
HV		 253/* ----------------------------------------------------------------------- */
254
255static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
256{
257 return container_of(sd, struct adv7604_state, sd);
258}
259
260static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
261{
262 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
263}
264
265static inline unsigned hblanking(const struct v4l2_bt_timings *t)
266{
eacf8f9a 267 return V4L2_DV_BT_BLANKING_WIDTH(t);
54450f59
HV		 268}
269
270static inline unsigned htotal(const struct v4l2_bt_timings *t)
271{
eacf8f9a 272 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 273}
274
275static inline unsigned vblanking(const struct v4l2_bt_timings *t)
276{
eacf8f9a 277 return V4L2_DV_BT_BLANKING_HEIGHT(t);
54450f59
HV		 278}
279
280static inline unsigned vtotal(const struct v4l2_bt_timings *t)
281{
eacf8f9a 282 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 283}
284
285/* ----------------------------------------------------------------------- */
286
287static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
288 u8 command, bool check)
289{
290 union i2c_smbus_data data;
291
292 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
293 I2C_SMBUS_READ, command,
294 I2C_SMBUS_BYTE_DATA, &data))
295 return data.byte;
296 if (check)
297 v4l_err(client, "error reading %02x, %02x\n",
298 client->addr, command);
299 return -EIO;
300}
301
302static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
303{
304 return adv_smbus_read_byte_data_check(client, command, true);
305}
306
307static s32 adv_smbus_write_byte_data(struct i2c_client *client,
308 u8 command, u8 value)
309{
310 union i2c_smbus_data data;
311 int err;
312 int i;
313
314 data.byte = value;
315 for (i = 0; i < 3; i++) {
316 err = i2c_smbus_xfer(client->adapter, client->addr,
317 client->flags,
318 I2C_SMBUS_WRITE, command,
319 I2C_SMBUS_BYTE_DATA, &data);
320 if (!err)
321 break;
322 }
323 if (err < 0)
324 v4l_err(client, "error writing %02x, %02x, %02x\n",
325 client->addr, command, value);
326 return err;
327}
328
329static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
330 u8 command, unsigned length, const u8 *values)
331{
332 union i2c_smbus_data data;
333
334 if (length > I2C_SMBUS_BLOCK_MAX)
335 length = I2C_SMBUS_BLOCK_MAX;
336 data.block[0] = length;
337 memcpy(data.block + 1, values, length);
338 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
339 I2C_SMBUS_WRITE, command,
340 I2C_SMBUS_I2C_BLOCK_DATA, &data);
341}
342
343/* ----------------------------------------------------------------------- */
344
345static inline int io_read(struct v4l2_subdev *sd, u8 reg)
346{
347 struct i2c_client *client = v4l2_get_subdevdata(sd);
348
349 return adv_smbus_read_byte_data(client, reg);
350}
351
352static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
353{
354 struct i2c_client *client = v4l2_get_subdevdata(sd);
355
356 return adv_smbus_write_byte_data(client, reg, val);
357}
358
359static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
360{
361 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
362}
363
364static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
365{
366 struct adv7604_state *state = to_state(sd);
367
368 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
369}
370
371static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
372{
373 struct adv7604_state *state = to_state(sd);
374
375 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
376}
377
378static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
379{
380 struct adv7604_state *state = to_state(sd);
381
382 return adv_smbus_read_byte_data(state->i2c_cec, reg);
383}
384
385static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
386{
387 struct adv7604_state *state = to_state(sd);
388
389 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
390}
391
392static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
393{
394 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
395}
396
397static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
398{
399 struct adv7604_state *state = to_state(sd);
400
401 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
402}
403
404static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
405{
406 struct adv7604_state *state = to_state(sd);
407
408 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
409}
410
411static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
412{
413 struct adv7604_state *state = to_state(sd);
414
415 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
416}
417
418static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
419{
420 struct adv7604_state *state = to_state(sd);
421
422 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
423}
424
425static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
426{
427 struct adv7604_state *state = to_state(sd);
428
429 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
430}
431
432static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
433{
434 struct adv7604_state *state = to_state(sd);
435
436 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
437}
438
439static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
440{
441 struct adv7604_state *state = to_state(sd);
442
443 return adv_smbus_read_byte_data(state->i2c_afe, reg);
444}
445
446static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
447{
448 struct adv7604_state *state = to_state(sd);
449
450 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
451}
452
453static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
454{
455 struct adv7604_state *state = to_state(sd);
456
457 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
458}
459
460static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
461{
462 struct adv7604_state *state = to_state(sd);
463
464 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
465}
466
467static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
468{
469 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
470}
471
472static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
473{
474 struct adv7604_state *state = to_state(sd);
475
476 return adv_smbus_read_byte_data(state->i2c_edid, reg);
477}
478
479static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
480{
481 struct adv7604_state *state = to_state(sd);
482
483 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
484}
485
486static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
487{
488 struct adv7604_state *state = to_state(sd);
489 struct i2c_client *client = state->i2c_edid;
490 u8 msgbuf0[1] = { 0 };
491 u8 msgbuf1[256];
09f29673
S		 492 struct i2c_msg msg[2] = {
493 {
494 .addr = client->addr,
495 .len = 1,
496 .buf = msgbuf0
497 },
498 {
499 .addr = client->addr,
500 .flags = I2C_M_RD,
501 .len = len,
502 .buf = msgbuf1
503 },
504 };
54450f59
HV		 505
506 if (i2c_transfer(client->adapter, msg, 2) < 0)
507 return -EIO;
508 memcpy(val, msgbuf1, len);
509 return 0;
510}
511
512static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
513{
514 struct delayed_work *dwork = to_delayed_work(work);
515 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
516 delayed_work_enable_hotplug);
517 struct v4l2_subdev *sd = &state->sd;
518
519 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
520
4a31a93a 521 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
54450f59
HV		 522}
523
524static inline int edid_write_block(struct v4l2_subdev *sd,
525 unsigned len, const u8 *val)
526{
527 struct i2c_client *client = v4l2_get_subdevdata(sd);
528 struct adv7604_state *state = to_state(sd);
529 int err = 0;
530 int i;
531
532 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
533
54450f59
HV		 534 /* Disables I2C access to internal EDID ram from DDC port */
535 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
536
537 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
538 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
539 I2C_SMBUS_BLOCK_MAX, val + i);
540 if (err)
541 return err;
542
543 /* adv7604 calculates the checksums and enables I2C access to internal
4a31a93a
MR		 544 EDID RAM from DDC port. */
545 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
54450f59
HV		 546
547 for (i = 0; i < 1000; i++) {
4a31a93a 548 if (rep_read(sd, 0x7d) & state->edid.present)
54450f59
HV		 549 break;
550 mdelay(1);
551 }
552 if (i == 1000) {
4a31a93a 553 v4l_err(client, "error enabling edid (0x%x)\n", state->edid.present);
54450f59
HV		 554 return -EIO;
555 }
556
54450f59
HV		 557 return 0;
558}
559
560static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
561{
562 struct adv7604_state *state = to_state(sd);
563
564 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
565}
566
567static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
568{
569 struct adv7604_state *state = to_state(sd);
570
571 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
572}
573
4a31a93a
MR		 574static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
575{
576 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
577}
578
54450f59
HV		 579static inline int test_read(struct v4l2_subdev *sd, u8 reg)
580{
581 struct adv7604_state *state = to_state(sd);
582
583 return adv_smbus_read_byte_data(state->i2c_test, reg);
584}
585
586static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587{
588 struct adv7604_state *state = to_state(sd);
589
590 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
591}
592
593static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
594{
595 struct adv7604_state *state = to_state(sd);
596
597 return adv_smbus_read_byte_data(state->i2c_cp, reg);
598}
599
600static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
601{
602 struct adv7604_state *state = to_state(sd);
603
604 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
605}
606
607static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
608{
609 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
610}
611
612static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
613{
614 struct adv7604_state *state = to_state(sd);
615
616 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
617}
618
619static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
620{
621 struct adv7604_state *state = to_state(sd);
622
623 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
624}
625
626/* ----------------------------------------------------------------------- */
627
4a31a93a
MR		 628static inline bool is_analog_input(struct v4l2_subdev *sd)
629{
630 struct adv7604_state *state = to_state(sd);
631
632 return state->selected_input == ADV7604_INPUT_VGA_RGB ||
633 state->selected_input == ADV7604_INPUT_VGA_COMP;
634}
635
636static inline bool is_digital_input(struct v4l2_subdev *sd)
637{
638 struct adv7604_state *state = to_state(sd);
639
640 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
641 state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
642 state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
643 state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
644}
645
646/* ----------------------------------------------------------------------- */
647
54450f59
HV		 648#ifdef CONFIG_VIDEO_ADV_DEBUG
649static void adv7604_inv_register(struct v4l2_subdev *sd)
650{
651 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
652 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
653 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
654 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
655 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
656 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
657 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
658 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
659 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
660 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
661 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
662 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
663 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
664}
665
666static int adv7604_g_register(struct v4l2_subdev *sd,
667 struct v4l2_dbg_register *reg)
668{
54450f59
HV		 669 reg->size = 1;
670 switch (reg->reg >> 8) {
671 case 0:
672 reg->val = io_read(sd, reg->reg & 0xff);
673 break;
674 case 1:
675 reg->val = avlink_read(sd, reg->reg & 0xff);
676 break;
677 case 2:
678 reg->val = cec_read(sd, reg->reg & 0xff);
679 break;
680 case 3:
681 reg->val = infoframe_read(sd, reg->reg & 0xff);
682 break;
683 case 4:
684 reg->val = esdp_read(sd, reg->reg & 0xff);
685 break;
686 case 5:
687 reg->val = dpp_read(sd, reg->reg & 0xff);
688 break;
689 case 6:
690 reg->val = afe_read(sd, reg->reg & 0xff);
691 break;
692 case 7:
693 reg->val = rep_read(sd, reg->reg & 0xff);
694 break;
695 case 8:
696 reg->val = edid_read(sd, reg->reg & 0xff);
697 break;
698 case 9:
699 reg->val = hdmi_read(sd, reg->reg & 0xff);
700 break;
701 case 0xa:
702 reg->val = test_read(sd, reg->reg & 0xff);
703 break;
704 case 0xb:
705 reg->val = cp_read(sd, reg->reg & 0xff);
706 break;
707 case 0xc:
708 reg->val = vdp_read(sd, reg->reg & 0xff);
709 break;
710 default:
711 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
712 adv7604_inv_register(sd);
713 break;
714 }
715 return 0;
716}
717
718static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 719 const struct v4l2_dbg_register *reg)
54450f59 720{
1577461b
HV		 721 u8 val = reg->val & 0xff;
722
54450f59
HV		 723 switch (reg->reg >> 8) {
724 case 0:
1577461b 725 io_write(sd, reg->reg & 0xff, val);
54450f59
HV		 726 break;
727 case 1:
1577461b 728 avlink_write(sd, reg->reg & 0xff, val);
54450f59
HV		 729 break;
730 case 2:
1577461b 731 cec_write(sd, reg->reg & 0xff, val);
54450f59
HV		 732 break;
733 case 3:
1577461b 734 infoframe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 735 break;
736 case 4:
1577461b 737 esdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 738 break;
739 case 5:
1577461b 740 dpp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 741 break;
742 case 6:
1577461b 743 afe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 744 break;
745 case 7:
1577461b 746 rep_write(sd, reg->reg & 0xff, val);
54450f59
HV		 747 break;
748 case 8:
1577461b 749 edid_write(sd, reg->reg & 0xff, val);
54450f59
HV		 750 break;
751 case 9:
1577461b 752 hdmi_write(sd, reg->reg & 0xff, val);
54450f59
HV		 753 break;
754 case 0xa:
1577461b 755 test_write(sd, reg->reg & 0xff, val);
54450f59
HV		 756 break;
757 case 0xb:
1577461b 758 cp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 759 break;
760 case 0xc:
1577461b 761 vdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 762 break;
763 default:
764 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
765 adv7604_inv_register(sd);
766 break;
767 }
768 return 0;
769}
770#endif
771
772static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
773{
774 struct adv7604_state *state = to_state(sd);
4a31a93a 775 u8 reg_io_6f = io_read(sd, 0x6f);
54450f59 776
54450f59 777 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
4a31a93a
MR		 778 ((reg_io_6f & 0x10) >> 4) |
779 ((reg_io_6f & 0x08) >> 2) |
780 (reg_io_6f & 0x04) |
781 ((reg_io_6f & 0x02) << 2));
54450f59
HV		 782}
783
ccbd5bc4
HV		 784static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
785 u8 prim_mode,
786 const struct adv7604_video_standards *predef_vid_timings,
787 const struct v4l2_dv_timings *timings)
788{
ccbd5bc4
HV		 789 int i;
790
791 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 792 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 793 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 794 continue;
795 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
796 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
797 prim_mode); /* v_freq and prim mode */
798 return 0;
799 }
800
801 return -1;
802}
803
804static int configure_predefined_video_timings(struct v4l2_subdev *sd,
805 struct v4l2_dv_timings *timings)
54450f59 806{
ccbd5bc4
HV		 807 struct adv7604_state *state = to_state(sd);
808 int err;
809
810 v4l2_dbg(1, debug, sd, "%s", __func__);
811
812 /* reset to default values */
813 io_write(sd, 0x16, 0x43);
814 io_write(sd, 0x17, 0x5a);
815 /* disable embedded syncs for auto graphics mode */
816 cp_write_and_or(sd, 0x81, 0xef, 0x00);
817 cp_write(sd, 0x8f, 0x00);
818 cp_write(sd, 0x90, 0x00);
819 cp_write(sd, 0xa2, 0x00);
820 cp_write(sd, 0xa3, 0x00);
821 cp_write(sd, 0xa4, 0x00);
822 cp_write(sd, 0xa5, 0x00);
823 cp_write(sd, 0xa6, 0x00);
824 cp_write(sd, 0xa7, 0x00);
825 cp_write(sd, 0xab, 0x00);
826 cp_write(sd, 0xac, 0x00);
827
4a31a93a 828 if (is_analog_input(sd)) {
ccbd5bc4
HV		 829 err = find_and_set_predefined_video_timings(sd,
830 0x01, adv7604_prim_mode_comp, timings);
831 if (err)
832 err = find_and_set_predefined_video_timings(sd,
833 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 834 } else if (is_digital_input(sd)) {
ccbd5bc4
HV		 835 err = find_and_set_predefined_video_timings(sd,
836 0x05, adv7604_prim_mode_hdmi_comp, timings);
837 if (err)
838 err = find_and_set_predefined_video_timings(sd,
839 0x06, adv7604_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 840 } else {
841 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
842 __func__, state->selected_input);
ccbd5bc4 843 err = -1;
ccbd5bc4
HV		 844 }
845
846
847 return err;
848}
849
850static void configure_custom_video_timings(struct v4l2_subdev *sd,
851 const struct v4l2_bt_timings *bt)
852{
853 struct adv7604_state *state = to_state(sd);
54450f59 854 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 855 u32 width = htotal(bt);
856 u32 height = vtotal(bt);
857 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
858 u16 cp_start_eav = width - bt->hfrontporch;
859 u16 cp_start_vbi = height - bt->vfrontporch;
860 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
861 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
862 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
863 const u8 pll[2] = {
864 0xc0 | ((width >> 8) & 0x1f),
865 width & 0xff
866 };
54450f59
HV		 867
868 v4l2_dbg(2, debug, sd, "%s\n", __func__);
869
4a31a93a 870 if (is_analog_input(sd)) {
ccbd5bc4
HV		 871 /* auto graphics */
872 io_write(sd, 0x00, 0x07); /* video std */
873 io_write(sd, 0x01, 0x02); /* prim mode */
874 /* enable embedded syncs for auto graphics mode */
875 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 876
ccbd5bc4 877 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 878 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
879 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
4a31a93a 880 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
54450f59 881 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 882
883 /* active video - horizontal timing */
54450f59 884 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 885 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 886 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 887 cp_write(sd, 0xa4, cp_start_eav & 0xff);
888
889 /* active video - vertical timing */
54450f59 890 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 891 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 892 ((cp_end_vbi >> 8) & 0xf));
54450f59 893 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 894 } else if (is_digital_input(sd)) {
ccbd5bc4 895 /* set default prim_mode/vid_std for HDMI
39c1cb2b 896 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 897 io_write(sd, 0x00, 0x02); /* video std */
898 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 899 } else {
900 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
901 __func__, state->selected_input);
54450f59 902 }
54450f59 903
ccbd5bc4
HV		 904 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
905 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
906 cp_write(sd, 0xab, (height >> 4) & 0xff);
907 cp_write(sd, 0xac, (height & 0x0f) << 4);
908}
54450f59
HV		 909
910static void set_rgb_quantization_range(struct v4l2_subdev *sd)
911{
912 struct adv7604_state *state = to_state(sd);
913
9833239e
MR		 914 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
915 __func__, state->rgb_quantization_range);
916
54450f59
HV		 917 switch (state->rgb_quantization_range) {
918 case V4L2_DV_RGB_RANGE_AUTO:
9833239e
MR		 919 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
920 /* Receiving analog RGB signal
921 * Set RGB full range (0-255) */
922 io_write_and_or(sd, 0x02, 0x0f, 0x10);
923 break;
924 }
925
926 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
927 /* Receiving analog YPbPr signal
928 * Set automode */
929 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
930 break;
931 }
932
933 if (hdmi_read(sd, 0x05) & 0x80) {
934 /* Receiving HDMI signal
935 * Set automode */
6b0d5d34 936 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
9833239e
MR		 937 break;
938 }
939
940 /* Receiving DVI-D signal
941 * ADV7604 selects RGB limited range regardless of
942 * input format (CE/IT) in automatic mode */
943 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
944 /* RGB limited range (16-235) */
945 io_write_and_or(sd, 0x02, 0x0f, 0x00);
946 } else {
947 /* RGB full range (0-255) */
948 io_write_and_or(sd, 0x02, 0x0f, 0x10);
54450f59
HV		 949 }
950 break;
951 case V4L2_DV_RGB_RANGE_LIMITED:
d261e842
MR		 952 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
953 /* YCrCb limited range (16-235) */
954 io_write_and_or(sd, 0x02, 0x0f, 0x20);
955 } else {
956 /* RGB limited range (16-235) */
957 io_write_and_or(sd, 0x02, 0x0f, 0x00);
958 }
54450f59
HV		 959 break;
960 case V4L2_DV_RGB_RANGE_FULL:
d261e842
MR		 961 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
962 /* YCrCb full range (0-255) */
963 io_write_and_or(sd, 0x02, 0x0f, 0x60);
964 } else {
965 /* RGB full range (0-255) */
966 io_write_and_or(sd, 0x02, 0x0f, 0x10);
967 }
54450f59
HV		 968 break;
969 }
970}
971
54450f59
HV		 972static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
973{
974 struct v4l2_subdev *sd = to_sd(ctrl);
975 struct adv7604_state *state = to_state(sd);
976
977 switch (ctrl->id) {
978 case V4L2_CID_BRIGHTNESS:
979 cp_write(sd, 0x3c, ctrl->val);
980 return 0;
981 case V4L2_CID_CONTRAST:
982 cp_write(sd, 0x3a, ctrl->val);
983 return 0;
984 case V4L2_CID_SATURATION:
985 cp_write(sd, 0x3b, ctrl->val);
986 return 0;
987 case V4L2_CID_HUE:
988 cp_write(sd, 0x3d, ctrl->val);
989 return 0;
990 case V4L2_CID_DV_RX_RGB_RANGE:
991 state->rgb_quantization_range = ctrl->val;
992 set_rgb_quantization_range(sd);
993 return 0;
994 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
995 /* Set the analog sampling phase. This is needed to find the
996 best sampling phase for analog video: an application or
997 driver has to try a number of phases and analyze the picture
998 quality before settling on the best performing phase. */
999 afe_write(sd, 0xc8, ctrl->val);
1000 return 0;
1001 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1002 /* Use the default blue color for free running mode,
1003 or supply your own. */
1004 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1005 return 0;
1006 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1007 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1008 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1009 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1010 return 0;
1011 }
1012 return -EINVAL;
1013}
1014
54450f59
HV		 1015/* ----------------------------------------------------------------------- */
1016
1017static inline bool no_power(struct v4l2_subdev *sd)
1018{
1019 /* Entire chip or CP powered off */
1020 return io_read(sd, 0x0c) & 0x24;
1021}
1022
1023static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1024{
4a31a93a
MR		 1025 struct adv7604_state *state = to_state(sd);
1026
1027 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1028}
1029
1030static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1031{
1032 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1033}
1034
bb88f325
MB		 1035static inline bool is_hdmi(struct v4l2_subdev *sd)
1036{
1037 return hdmi_read(sd, 0x05) & 0x80;
1038}
1039
54450f59
HV		 1040static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1041{
1042 /* TODO channel 2 */
1043 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1044}
1045
1046static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1047{
1048 /* TODO channel 2 */
1049 return !(cp_read(sd, 0xb1) & 0x80);
1050}
1051
1052static inline bool no_signal(struct v4l2_subdev *sd)
1053{
54450f59
HV		 1054 bool ret;
1055
1056 ret = no_power(sd);
1057
1058 ret |= no_lock_stdi(sd);
1059 ret |= no_lock_sspd(sd);
1060
4a31a93a 1061 if (is_digital_input(sd)) {
54450f59
HV		 1062 ret |= no_lock_tmds(sd);
1063 ret |= no_signal_tmds(sd);
1064 }
1065
1066 return ret;
1067}
1068
1069static inline bool no_lock_cp(struct v4l2_subdev *sd)
1070{
1071 /* CP has detected a non standard number of lines on the incoming
1072 video compared to what it is configured to receive by s_dv_timings */
1073 return io_read(sd, 0x12) & 0x01;
1074}
1075
1076static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1077{
54450f59
HV		 1078 *status = 0;
1079 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1080 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1081 if (no_lock_cp(sd))
4a31a93a 1082 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1083
1084 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1085
1086 return 0;
1087}
1088
1089/* ----------------------------------------------------------------------- */
1090
54450f59
HV		 1091struct stdi_readback {
1092 u16 bl, lcf, lcvs;
1093 u8 hs_pol, vs_pol;
1094 bool interlaced;
1095};
1096
1097static int stdi2dv_timings(struct v4l2_subdev *sd,
1098 struct stdi_readback *stdi,
1099 struct v4l2_dv_timings *timings)
1100{
1101 struct adv7604_state *state = to_state(sd);
1102 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1103 u32 pix_clk;
1104 int i;
1105
1106 for (i = 0; adv7604_timings[i].bt.height; i++) {
1107 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1108 continue;
1109 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1110 continue;
1111
1112 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1113
1114 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1115 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1116 *timings = adv7604_timings[i];
1117 return 0;
1118 }
1119 }
1120
1121 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1122 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1123 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1124 timings))
1125 return 0;
1126 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1127 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1128 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1129 state->aspect_ratio, timings))
1130 return 0;
1131
ccbd5bc4
HV		 1132 v4l2_dbg(2, debug, sd,
1133 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1134 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1135 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1136 return -1;
1137}
1138
1139static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1140{
1141 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1142 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1143 return -1;
1144 }
1145
1146 /* read STDI */
1147 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1148 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1149 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1150 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1151
1152 /* read SSPD */
1153 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1154 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1155 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1156 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1157 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1158 } else {
1159 stdi->hs_pol = 'x';
1160 stdi->vs_pol = 'x';
1161 }
1162
1163 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1164 v4l2_dbg(2, debug, sd,
1165 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1166 return -1;
1167 }
1168
1169 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1170 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1171 memset(stdi, 0, sizeof(struct stdi_readback));
1172 return -1;
1173 }
1174
1175 v4l2_dbg(2, debug, sd,
1176 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1177 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1178 stdi->hs_pol, stdi->vs_pol,
1179 stdi->interlaced ? "interlaced" : "progressive");
1180
1181 return 0;
1182}
1183
1184static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1185 struct v4l2_enum_dv_timings *timings)
1186{
1187 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1188 return -EINVAL;
1189 memset(timings->reserved, 0, sizeof(timings->reserved));
1190 timings->timings = adv7604_timings[timings->index];
1191 return 0;
1192}
1193
1194static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1195 struct v4l2_dv_timings_cap *cap)
1196{
54450f59
HV		 1197 cap->type = V4L2_DV_BT_656_1120;
1198 cap->bt.max_width = 1920;
1199 cap->bt.max_height = 1200;
fe9c2564 1200 cap->bt.min_pixelclock = 25000000;
4a31a93a 1201 if (is_digital_input(sd))
54450f59
HV		 1202 cap->bt.max_pixelclock = 225000000;
1203 else
1204 cap->bt.max_pixelclock = 170000000;
1205 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1206 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1207 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1208 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1209 return 0;
1210}
1211
1212/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1213 if the format is listed in adv7604_timings[] */
1214static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1215 struct v4l2_dv_timings *timings)
1216{
54450f59
HV		 1217 int i;
1218
1219 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1220 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
4a31a93a 1221 is_digital_input(sd) ? 250000 : 1000000)) {
54450f59
HV		 1222 *timings = adv7604_timings[i];
1223 break;
1224 }
1225 }
1226}
1227
1228static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1229 struct v4l2_dv_timings *timings)
1230{
1231 struct adv7604_state *state = to_state(sd);
1232 struct v4l2_bt_timings *bt = &timings->bt;
1233 struct stdi_readback stdi;
1234
1235 if (!timings)
1236 return -EINVAL;
1237
1238 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1239
1240 if (no_signal(sd)) {
1241 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1242 return -ENOLINK;
1243 }
1244
1245 /* read STDI */
1246 if (read_stdi(sd, &stdi)) {
1247 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1248 return -ENOLINK;
1249 }
1250 bt->interlaced = stdi.interlaced ?
1251 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1252
4a31a93a 1253 if (is_digital_input(sd)) {
bb88f325
MB		 1254 uint32_t freq;
1255
54450f59
HV		 1256 timings->type = V4L2_DV_BT_656_1120;
1257
1258 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1259 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
bb88f325 1260 freq = (hdmi_read(sd, 0x06) * 1000000) +
54450f59 1261 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
bb88f325
MB		 1262 if (is_hdmi(sd)) {
1263 /* adjust for deep color mode */
1264 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1265
1266 freq = freq * 8 / bits_per_channel;
1267 }
1268 bt->pixelclock = freq;
54450f59
HV		 1269 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1270 hdmi_read(sd, 0x21);
1271 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1272 hdmi_read(sd, 0x23);
1273 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1274 hdmi_read(sd, 0x25);
1275 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1276 hdmi_read(sd, 0x2b)) / 2;
1277 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1278 hdmi_read(sd, 0x2f)) / 2;
1279 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1280 hdmi_read(sd, 0x33)) / 2;
1281 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1282 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1283 if (bt->interlaced == V4L2_DV_INTERLACED) {
1284 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1285 hdmi_read(sd, 0x0c);
1286 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1287 hdmi_read(sd, 0x2d)) / 2;
1288 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1289 hdmi_read(sd, 0x31)) / 2;
1290 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1291 hdmi_read(sd, 0x35)) / 2;
1292 }
1293 adv7604_fill_optional_dv_timings_fields(sd, timings);
1294 } else {
1295 /* find format
80939647 1296 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1297 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1298 */
1299 if (!stdi2dv_timings(sd, &stdi, timings))
1300 goto found;
1301 stdi.lcvs += 1;
1302 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1303 if (!stdi2dv_timings(sd, &stdi, timings))
1304 goto found;
1305 stdi.lcvs -= 2;
1306 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1307 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1308 /*
1309 * The STDI block may measure wrong values, especially
1310 * for lcvs and lcf. If the driver can not find any
1311 * valid timing, the STDI block is restarted to measure
1312 * the video timings again. The function will return an
1313 * error, but the restart of STDI will generate a new
1314 * STDI interrupt and the format detection process will
1315 * restart.
1316 */
1317 if (state->restart_stdi_once) {
1318 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1319 /* TODO restart STDI for Sync Channel 2 */
1320 /* enter one-shot mode */
1321 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1322 /* trigger STDI restart */
1323 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1324 /* reset to continuous mode */
1325 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1326 state->restart_stdi_once = false;
1327 return -ENOLINK;
1328 }
54450f59
HV		 1329 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1330 return -ERANGE;
1331 }
cf9afb1d 1332 state->restart_stdi_once = true;
54450f59
HV		 1333 }
1334found:
1335
1336 if (no_signal(sd)) {
1337 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1338 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1339 return -ENOLINK;
1340 }
1341
4a31a93a
MR		 1342 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1343 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1344 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1345 __func__, (u32)bt->pixelclock);
1346 return -ERANGE;
1347 }
1348
1349 if (debug > 1)
11d034c8
HV		 1350 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1351 timings, true);
54450f59
HV		 1352
1353 return 0;
1354}
1355
1356static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1357 struct v4l2_dv_timings *timings)
1358{
1359 struct adv7604_state *state = to_state(sd);
1360 struct v4l2_bt_timings *bt;
ccbd5bc4 1361 int err;
54450f59
HV		 1362
1363 if (!timings)
1364 return -EINVAL;
1365
1366 bt = &timings->bt;
1367
4a31a93a
MR		 1368 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1369 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1370 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1371 __func__, (u32)bt->pixelclock);
1372 return -ERANGE;
1373 }
ccbd5bc4 1374
54450f59
HV		 1375 adv7604_fill_optional_dv_timings_fields(sd, timings);
1376
1377 state->timings = *timings;
1378
ccbd5bc4
HV		 1379 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1380
1381 /* Use prim_mode and vid_std when available */
1382 err = configure_predefined_video_timings(sd, timings);
1383 if (err) {
1384 /* custom settings when the video format
1385 does not have prim_mode/vid_std */
1386 configure_custom_video_timings(sd, bt);
1387 }
54450f59
HV		 1388
1389 set_rgb_quantization_range(sd);
1390
1391
1392 if (debug > 1)
11d034c8
HV		 1393 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1394 timings, true);
54450f59
HV		 1395 return 0;
1396}
1397
1398static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1399 struct v4l2_dv_timings *timings)
1400{
1401 struct adv7604_state *state = to_state(sd);
1402
1403 *timings = state->timings;
1404 return 0;
1405}
1406
6b0d5d34 1407static void enable_input(struct v4l2_subdev *sd)
54450f59 1408{
6b0d5d34
HV		 1409 struct adv7604_state *state = to_state(sd);
1410
4a31a93a 1411 if (is_analog_input(sd)) {
54450f59
HV		 1412 /* enable */
1413 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1414 } else if (is_digital_input(sd)) {
54450f59 1415 /* enable */
4a31a93a 1416 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
54450f59
HV		 1417 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1418 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1419 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
4a31a93a
MR		 1420 } else {
1421 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1422 __func__, state->selected_input);
54450f59
HV		 1423 }
1424}
1425
1426static void disable_input(struct v4l2_subdev *sd)
1427{
1428 /* disable */
1429 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1430 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1431 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1432}
1433
6b0d5d34 1434static void select_input(struct v4l2_subdev *sd)
54450f59 1435{
6b0d5d34 1436 struct adv7604_state *state = to_state(sd);
54450f59 1437
4a31a93a 1438 if (is_analog_input(sd)) {
54450f59
HV		 1439 /* reset ADI recommended settings for HDMI: */
1440 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1441 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1442 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1443 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1444 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1445 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1446 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1447 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1448 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1449 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1450 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1451 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1452
1453 afe_write(sd, 0x00, 0x08); /* power up ADC */
1454 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1455 afe_write(sd, 0xc8, 0x00); /* phase control */
1456
1457 /* set ADI recommended settings for digitizer */
1458 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1459 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1460 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1461 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1462 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1463 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1464 } else if (is_digital_input(sd)) {
1465 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1466
54450f59
HV		 1467 /* set ADI recommended settings for HDMI: */
1468 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1469 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1470 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1471 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1472 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1473 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1474 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1475 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1476 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1477 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1478 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1479 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1480
1481 afe_write(sd, 0x00, 0xff); /* power down ADC */
1482 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1483 afe_write(sd, 0xc8, 0x40); /* phase control */
1484
1485 /* reset ADI recommended settings for digitizer */
1486 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1487 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1488 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1489 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1490 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1491 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1492 } else {
1493 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1494 __func__, state->selected_input);
54450f59
HV		 1495 }
1496}
1497
1498static int adv7604_s_routing(struct v4l2_subdev *sd,
1499 u32 input, u32 output, u32 config)
1500{
1501 struct adv7604_state *state = to_state(sd);
1502
1503 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1504
4a31a93a 1505 state->selected_input = input;
54450f59
HV		 1506
1507 disable_input(sd);
1508
6b0d5d34 1509 select_input(sd);
54450f59 1510
6b0d5d34 1511 enable_input(sd);
54450f59
HV		 1512
1513 return 0;
1514}
1515
1516static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1517 enum v4l2_mbus_pixelcode *code)
1518{
1519 if (index)
1520 return -EINVAL;
1521 /* Good enough for now */
1522 *code = V4L2_MBUS_FMT_FIXED;
1523 return 0;
1524}
1525
1526static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1527 struct v4l2_mbus_framefmt *fmt)
1528{
1529 struct adv7604_state *state = to_state(sd);
1530
1531 fmt->width = state->timings.bt.width;
1532 fmt->height = state->timings.bt.height;
1533 fmt->code = V4L2_MBUS_FMT_FIXED;
1534 fmt->field = V4L2_FIELD_NONE;
1535 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1536 fmt->colorspace = (state->timings.bt.height <= 576) ?
1537 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1538 }
1539 return 0;
1540}
1541
1542static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1543{
1544 struct adv7604_state *state = to_state(sd);
1545 u8 fmt_change, fmt_change_digital, tx_5v;
25a64ac9 1546 u32 input_status;
54450f59
HV		 1547
1548 /* format change */
1549 fmt_change = io_read(sd, 0x43) & 0x98;
1550 if (fmt_change)
1551 io_write(sd, 0x44, fmt_change);
4a31a93a 1552 fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
54450f59
HV		 1553 if (fmt_change_digital)
1554 io_write(sd, 0x6c, fmt_change_digital);
1555 if (fmt_change || fmt_change_digital) {
1556 v4l2_dbg(1, debug, sd,
25a64ac9 1557 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1558 __func__, fmt_change, fmt_change_digital);
25a64ac9
MR		 1559
1560 adv7604_g_input_status(sd, &input_status);
1561 if (input_status != state->prev_input_status) {
1562 v4l2_dbg(1, debug, sd,
1563 "%s: input_status = 0x%x, prev_input_status = 0x%x\n",
1564 __func__, input_status, state->prev_input_status);
1565 state->prev_input_status = input_status;
1566 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1567 }
1568
54450f59
HV		 1569 if (handled)
1570 *handled = true;
1571 }
1572 /* tx 5v detect */
4a31a93a 1573 tx_5v = io_read(sd, 0x70) & 0x1e;
54450f59
HV		 1574 if (tx_5v) {
1575 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1576 io_write(sd, 0x71, tx_5v);
1577 adv7604_s_detect_tx_5v_ctrl(sd);
1578 if (handled)
1579 *handled = true;
1580 }
1581 return 0;
1582}
1583
1584static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1585{
1586 struct adv7604_state *state = to_state(sd);
4a31a93a 1587 u8 *data = NULL;
54450f59 1588
4a31a93a 1589 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1590 return -EINVAL;
1591 if (edid->blocks == 0)
1592 return -EINVAL;
4a31a93a 1593 if (edid->blocks > 2)
54450f59 1594 return -EINVAL;
4a31a93a
MR		 1595 if (edid->start_block > 1)
1596 return -EINVAL;
1597 if (edid->start_block == 1)
1598 edid->blocks = 1;
54450f59
HV		 1599 if (!edid->edid)
1600 return -EINVAL;
4a31a93a
MR		 1601
1602 if (edid->blocks > state->edid.blocks)
1603 edid->blocks = state->edid.blocks;
1604
1605 switch (edid->pad) {
1606 case ADV7604_EDID_PORT_A:
1607 case ADV7604_EDID_PORT_B:
1608 case ADV7604_EDID_PORT_C:
1609 case ADV7604_EDID_PORT_D:
1610 if (state->edid.present & (1 << edid->pad))
1611 data = state->edid.edid;
1612 break;
1613 default:
1614 return -EINVAL;
1615 break;
1616 }
1617 if (!data)
1618 return -ENODATA;
1619
1620 memcpy(edid->edid,
1621 data + edid->start_block * 128,
54450f59
HV		 1622 edid->blocks * 128);
1623 return 0;
1624}
1625
1626static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1627{
1628 struct adv7604_state *state = to_state(sd);
1629 int err;
1630
4a31a93a 1631 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1632 return -EINVAL;
1633 if (edid->start_block != 0)
1634 return -EINVAL;
1635 if (edid->blocks == 0) {
1636 /* Pull down the hotplug pin */
4a31a93a
MR		 1637 state->edid.present &= ~(1 << edid->pad);
1638 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
54450f59
HV		 1639 /* Disables I2C access to internal EDID ram from DDC port */
1640 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
4a31a93a 1641 state->edid.blocks = 0;
54450f59
HV		 1642 /* Fall back to a 16:9 aspect ratio */
1643 state->aspect_ratio.numerator = 16;
1644 state->aspect_ratio.denominator = 9;
4a31a93a 1645 v4l2_dbg(2, debug, sd, "%s: clear edid\n", __func__);
54450f59
HV		 1646 return 0;
1647 }
4a31a93a
MR		 1648 if (edid->blocks > 2) {
1649 edid->blocks = 2;
54450f59 1650 return -E2BIG;
4a31a93a 1651 }
54450f59
HV		 1652 if (!edid->edid)
1653 return -EINVAL;
4a31a93a
MR		 1654
1655 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
1656 state->edid.present &= ~(1 << edid->pad);
1657 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1658
1659 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1660 state->edid.blocks = edid->blocks;
54450f59
HV		 1661 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1662 edid->edid[0x16]);
4a31a93a
MR		 1663 state->edid.present |= edid->pad;
1664
1665 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1666 if (err < 0) {
54450f59 1667 v4l2_err(sd, "error %d writing edid\n", err);
4a31a93a
MR		 1668 return err;
1669 }
1670
1671 /* enable hotplug after 100 ms */
1672 queue_delayed_work(state->work_queues,
1673 &state->delayed_work_enable_hotplug, HZ / 10);
1674 return 0;
54450f59
HV		 1675}
1676
1677/*********** avi info frame CEA-861-E **************/
1678
1679static void print_avi_infoframe(struct v4l2_subdev *sd)
1680{
1681 int i;
1682 u8 buf[14];
1683 u8 avi_len;
1684 u8 avi_ver;
1685
bb88f325 1686 if (!is_hdmi(sd)) {
54450f59
HV		 1687 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1688 return;
1689 }
1690 if (!(io_read(sd, 0x60) & 0x01)) {
1691 v4l2_info(sd, "AVI infoframe not received\n");
1692 return;
1693 }
1694
1695 if (io_read(sd, 0x83) & 0x01) {
1696 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1697 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1698 if (io_read(sd, 0x83) & 0x01) {
1699 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1700 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1701 }
1702 }
1703
1704 avi_len = infoframe_read(sd, 0xe2);
1705 avi_ver = infoframe_read(sd, 0xe1);
1706 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1707 avi_ver, avi_len);
1708
1709 if (avi_ver != 0x02)
1710 return;
1711
1712 for (i = 0; i < 14; i++)
1713 buf[i] = infoframe_read(sd, i);
1714
1715 v4l2_info(sd,
1716 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1717 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1718 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1719}
1720
1721static int adv7604_log_status(struct v4l2_subdev *sd)
1722{
1723 struct adv7604_state *state = to_state(sd);
1724 struct v4l2_dv_timings timings;
1725 struct stdi_readback stdi;
1726 u8 reg_io_0x02 = io_read(sd, 0x02);
1727
1728 char *csc_coeff_sel_rb[16] = {
1729 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1730 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1731 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1732 "reserved", "reserved", "reserved", "reserved", "manual"
1733 };
1734 char *input_color_space_txt[16] = {
1735 "RGB limited range (16-235)", "RGB full range (0-255)",
1736 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 1737 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 1738 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1739 "invalid", "invalid", "invalid", "invalid", "invalid",
1740 "invalid", "invalid", "automatic"
1741 };
1742 char *rgb_quantization_range_txt[] = {
1743 "Automatic",
1744 "RGB limited range (16-235)",
1745 "RGB full range (0-255)",
1746 };
bb88f325
MB		 1747 char *deep_color_mode_txt[4] = {
1748 "8-bits per channel",
1749 "10-bits per channel",
1750 "12-bits per channel",
1751 "16-bits per channel (not supported)"
1752 };
54450f59
HV		 1753
1754 v4l2_info(sd, "-----Chip status-----\n");
1755 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1756 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
4a31a93a
MR		 1757 "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A"));
1758 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1759 ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1760 ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1761 ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1762 ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
54450f59
HV		 1763 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1764 "enabled" : "disabled");
1765
1766 v4l2_info(sd, "-----Signal status-----\n");
4a31a93a
MR		 1767 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1768 ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1769 ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1770 ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1771 ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
54450f59
HV		 1772 v4l2_info(sd, "TMDS signal detected: %s\n",
1773 no_signal_tmds(sd) ? "false" : "true");
1774 v4l2_info(sd, "TMDS signal locked: %s\n",
1775 no_lock_tmds(sd) ? "false" : "true");
1776 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1777 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1778 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1779 v4l2_info(sd, "CP free run: %s\n",
1780 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1781 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1782 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1783 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1784
1785 v4l2_info(sd, "-----Video Timings-----\n");
1786 if (read_stdi(sd, &stdi))
1787 v4l2_info(sd, "STDI: not locked\n");
1788 else
1789 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1790 stdi.lcf, stdi.bl, stdi.lcvs,
1791 stdi.interlaced ? "interlaced" : "progressive",
1792 stdi.hs_pol, stdi.vs_pol);
1793 if (adv7604_query_dv_timings(sd, &timings))
1794 v4l2_info(sd, "No video detected\n");
1795 else
11d034c8
HV		 1796 v4l2_print_dv_timings(sd->name, "Detected format: ",
1797 &timings, true);
1798 v4l2_print_dv_timings(sd->name, "Configured format: ",
1799 &state->timings, true);
54450f59 1800
76eb2d30
MR		 1801 if (no_signal(sd))
1802 return 0;
1803
54450f59
HV		 1804 v4l2_info(sd, "-----Color space-----\n");
1805 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1806 rgb_quantization_range_txt[state->rgb_quantization_range]);
1807 v4l2_info(sd, "Input color space: %s\n",
1808 input_color_space_txt[reg_io_0x02 >> 4]);
1809 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1810 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1811 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1812 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 1813 "enabled" : "disabled");
54450f59
HV		 1814 v4l2_info(sd, "Color space conversion: %s\n",
1815 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1816
4a31a93a 1817 if (!is_digital_input(sd))
76eb2d30
MR		 1818 return 0;
1819
1820 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 1821 v4l2_info(sd, "Digital video port selected: %c\n",
1822 (hdmi_read(sd, 0x00) & 0x03) + 'A');
1823 v4l2_info(sd, "HDCP encrypted content: %s\n",
1824 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 1825 v4l2_info(sd, "HDCP keys read: %s%s\n",
1826 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1827 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1828 if (!is_hdmi(sd)) {
1829 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1830 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1831 bool audio_mute = io_read(sd, 0x65) & 0x40;
1832
1833 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1834 audio_pll_locked ? "locked" : "not locked",
1835 audio_sample_packet_detect ? "detected" : "not detected",
1836 audio_mute ? "muted" : "enabled");
1837 if (audio_pll_locked && audio_sample_packet_detect) {
1838 v4l2_info(sd, "Audio format: %s\n",
1839 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1840 }
1841 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1842 (hdmi_read(sd, 0x5c) << 8) +
1843 (hdmi_read(sd, 0x5d) & 0xf0));
1844 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1845 (hdmi_read(sd, 0x5e) << 8) +
1846 hdmi_read(sd, 0x5f));
1847 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1848
1849 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1850
54450f59
HV		 1851 print_avi_infoframe(sd);
1852 }
1853
1854 return 0;
1855}
1856
1857/* ----------------------------------------------------------------------- */
1858
1859static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1860 .s_ctrl = adv7604_s_ctrl,
1861};
1862
1863static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1864 .log_status = adv7604_log_status,
1865 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1866 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1867 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1868 .g_ctrl = v4l2_subdev_g_ctrl,
1869 .s_ctrl = v4l2_subdev_s_ctrl,
1870 .queryctrl = v4l2_subdev_queryctrl,
1871 .querymenu = v4l2_subdev_querymenu,
54450f59
HV		 1872 .interrupt_service_routine = adv7604_isr,
1873#ifdef CONFIG_VIDEO_ADV_DEBUG
1874 .g_register = adv7604_g_register,
1875 .s_register = adv7604_s_register,
1876#endif
1877};
1878
1879static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1880 .s_routing = adv7604_s_routing,
1881 .g_input_status = adv7604_g_input_status,
1882 .s_dv_timings = adv7604_s_dv_timings,
1883 .g_dv_timings = adv7604_g_dv_timings,
1884 .query_dv_timings = adv7604_query_dv_timings,
1885 .enum_dv_timings = adv7604_enum_dv_timings,
1886 .dv_timings_cap = adv7604_dv_timings_cap,
1887 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1888 .g_mbus_fmt = adv7604_g_mbus_fmt,
1889 .try_mbus_fmt = adv7604_g_mbus_fmt,
1890 .s_mbus_fmt = adv7604_g_mbus_fmt,
1891};
1892
1893static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1894 .get_edid = adv7604_get_edid,
1895 .set_edid = adv7604_set_edid,
1896};
1897
1898static const struct v4l2_subdev_ops adv7604_ops = {
1899 .core = &adv7604_core_ops,
1900 .video = &adv7604_video_ops,
1901 .pad = &adv7604_pad_ops,
1902};
1903
1904/* -------------------------- custom ctrls ---------------------------------- */
1905
1906static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1907 .ops = &adv7604_ctrl_ops,
1908 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1909 .name = "Analog Sampling Phase",
1910 .type = V4L2_CTRL_TYPE_INTEGER,
1911 .min = 0,
1912 .max = 0x1f,
1913 .step = 1,
1914 .def = 0,
1915};
1916
1917static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1918 .ops = &adv7604_ctrl_ops,
1919 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1920 .name = "Free Running Color, Manual",
1921 .type = V4L2_CTRL_TYPE_BOOLEAN,
1922 .min = false,
1923 .max = true,
1924 .step = 1,
1925 .def = false,
1926};
1927
1928static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1929 .ops = &adv7604_ctrl_ops,
1930 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1931 .name = "Free Running Color",
1932 .type = V4L2_CTRL_TYPE_INTEGER,
1933 .min = 0x0,
1934 .max = 0xffffff,
1935 .step = 0x1,
1936 .def = 0x0,
1937};
1938
1939/* ----------------------------------------------------------------------- */
1940
1941static int adv7604_core_init(struct v4l2_subdev *sd)
1942{
1943 struct adv7604_state *state = to_state(sd);
1944 struct adv7604_platform_data *pdata = &state->pdata;
1945
1946 hdmi_write(sd, 0x48,
1947 (pdata->disable_pwrdnb ? 0x80 : 0) |
1948 (pdata->disable_cable_det_rst ? 0x40 : 0));
1949
1950 disable_input(sd);
1951
1952 /* power */
1953 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
1954 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
1955 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
1956
1957 /* video format */
1958 io_write_and_or(sd, 0x02, 0xf0,
1959 pdata->alt_gamma << 3 |
1960 pdata->op_656_range << 2 |
1961 pdata->rgb_out << 1 |
1962 pdata->alt_data_sat << 0);
1963 io_write(sd, 0x03, pdata->op_format_sel);
1964 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1965 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1966 pdata->insert_av_codes << 2 |
1967 pdata->replicate_av_codes << 1 |
1968 pdata->invert_cbcr << 0);
1969
1970 /* TODO from platform data */
1971 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
1972 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
f31b62e1
MK		 1973
1974 /* Adjust drive strength */
1975 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
1976 pdata->dr_str_clk << 2 |
1977 pdata->dr_str_sync);
1978
54450f59
HV		 1979 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1980 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1981 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 1982 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 1983 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 1984 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 1985 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1986 for digital formats */
4a31a93a 1987 rep_write(sd, 0x76, 0xc0); /* SPA location for port B, C and D */
54450f59
HV		 1988
1989 /* TODO from platform data */
1990 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1991
1992 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1993 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1994
54450f59
HV		 1995 /* interrupts */
1996 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1997 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1998 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1999 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
4a31a93a 2000 io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
54450f59
HV		 2001
2002 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2003}
2004
2005static void adv7604_unregister_clients(struct adv7604_state *state)
2006{
2007 if (state->i2c_avlink)
2008 i2c_unregister_device(state->i2c_avlink);
2009 if (state->i2c_cec)
2010 i2c_unregister_device(state->i2c_cec);
2011 if (state->i2c_infoframe)
2012 i2c_unregister_device(state->i2c_infoframe);
2013 if (state->i2c_esdp)
2014 i2c_unregister_device(state->i2c_esdp);
2015 if (state->i2c_dpp)
2016 i2c_unregister_device(state->i2c_dpp);
2017 if (state->i2c_afe)
2018 i2c_unregister_device(state->i2c_afe);
2019 if (state->i2c_repeater)
2020 i2c_unregister_device(state->i2c_repeater);
2021 if (state->i2c_edid)
2022 i2c_unregister_device(state->i2c_edid);
2023 if (state->i2c_hdmi)
2024 i2c_unregister_device(state->i2c_hdmi);
2025 if (state->i2c_test)
2026 i2c_unregister_device(state->i2c_test);
2027 if (state->i2c_cp)
2028 i2c_unregister_device(state->i2c_cp);
2029 if (state->i2c_vdp)
2030 i2c_unregister_device(state->i2c_vdp);
2031}
2032
2033static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2034 u8 addr, u8 io_reg)
2035{
2036 struct i2c_client *client = v4l2_get_subdevdata(sd);
2037
2038 if (addr)
2039 io_write(sd, io_reg, addr << 1);
2040 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2041}
2042
2043static int adv7604_probe(struct i2c_client *client,
2044 const struct i2c_device_id *id)
2045{
2046 struct adv7604_state *state;
2047 struct adv7604_platform_data *pdata = client->dev.platform_data;
2048 struct v4l2_ctrl_handler *hdl;
2049 struct v4l2_subdev *sd;
2050 int err;
2051
2052 /* Check if the adapter supports the needed features */
2053 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2054 return -EIO;
2055 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2056 client->addr << 1);
2057
c02b211d 2058 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 2059 if (!state) {
2060 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2061 return -ENOMEM;
2062 }
2063
25a64ac9
MR		 2064 /* initialize variables */
2065 state->restart_stdi_once = true;
2066 state->prev_input_status = ~0;
2067
54450f59
HV		 2068 /* platform data */
2069 if (!pdata) {
2070 v4l_err(client, "No platform data!\n");
c02b211d 2071 return -ENODEV;
54450f59
HV		 2072 }
2073 memcpy(&state->pdata, pdata, sizeof(state->pdata));
2074
2075 sd = &state->sd;
2076 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2077 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2078 state->connector_hdmi = pdata->connector_hdmi;
2079
2080 /* i2c access to adv7604? */
2081 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2082 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2083 client->addr << 1);
c02b211d 2084 return -ENODEV;
54450f59
HV		 2085 }
2086
2087 /* control handlers */
2088 hdl = &state->hdl;
2089 v4l2_ctrl_handler_init(hdl, 9);
2090
2091 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2092 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2093 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2094 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2095 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2096 V4L2_CID_SATURATION, 0, 255, 1, 128);
2097 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2098 V4L2_CID_HUE, 0, 128, 1, 0);
2099
2100 /* private controls */
2101 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
4a31a93a 2102 V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
54450f59
HV		 2103 state->rgb_quantization_range_ctrl =
2104 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2105 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2106 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2107
2108 /* custom controls */
2109 state->analog_sampling_phase_ctrl =
2110 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2111 state->free_run_color_manual_ctrl =
2112 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2113 state->free_run_color_ctrl =
2114 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2115
2116 sd->ctrl_handler = hdl;
2117 if (hdl->error) {
2118 err = hdl->error;
2119 goto err_hdl;
2120 }
8c0eadb8
HV		 2121 state->detect_tx_5v_ctrl->is_private = true;
2122 state->rgb_quantization_range_ctrl->is_private = true;
2123 state->analog_sampling_phase_ctrl->is_private = true;
2124 state->free_run_color_manual_ctrl->is_private = true;
2125 state->free_run_color_ctrl->is_private = true;
2126
54450f59
HV		 2127 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2128 err = -ENODEV;
2129 goto err_hdl;
2130 }
2131
2132 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2133 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2134 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2135 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2136 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2137 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2138 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2139 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2140 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2141 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2142 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2143 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2144 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2145 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2146 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2147 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2148 err = -ENOMEM;
2149 v4l2_err(sd, "failed to create all i2c clients\n");
2150 goto err_i2c;
2151 }
2152
2153 /* work queues */
2154 state->work_queues = create_singlethread_workqueue(client->name);
2155 if (!state->work_queues) {
2156 v4l2_err(sd, "Could not create work queue\n");
2157 err = -ENOMEM;
2158 goto err_i2c;
2159 }
2160
2161 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2162 adv7604_delayed_work_enable_hotplug);
2163
2164 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2165 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2166 if (err)
2167 goto err_work_queues;
2168
2169 err = adv7604_core_init(sd);
2170 if (err)
2171 goto err_entity;
2172 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2173 client->addr << 1, client->adapter->name);
2174 return 0;
2175
2176err_entity:
2177 media_entity_cleanup(&sd->entity);
2178err_work_queues:
2179 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2180 destroy_workqueue(state->work_queues);
2181err_i2c:
2182 adv7604_unregister_clients(state);
2183err_hdl:
2184 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2185 return err;
2186}
2187
2188/* ----------------------------------------------------------------------- */
2189
2190static int adv7604_remove(struct i2c_client *client)
2191{
2192 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2193 struct adv7604_state *state = to_state(sd);
2194
2195 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2196 destroy_workqueue(state->work_queues);
2197 v4l2_device_unregister_subdev(sd);
2198 media_entity_cleanup(&sd->entity);
2199 adv7604_unregister_clients(to_state(sd));
2200 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2201 return 0;
2202}
2203
2204/* ----------------------------------------------------------------------- */
2205
2206static struct i2c_device_id adv7604_id[] = {
2207 { "adv7604", 0 },
2208 { }
2209};
2210MODULE_DEVICE_TABLE(i2c, adv7604_id);
2211
2212static struct i2c_driver adv7604_driver = {
2213 .driver = {
2214 .owner = THIS_MODULE,
2215 .name = "adv7604",
2216 },
2217 .probe = adv7604_probe,
2218 .remove = adv7604_remove,
2219 .id_table = adv7604_id,
2220};
2221
2222module_i2c_driver(adv7604_driver);
Ubuntu Eoan Linux kernel mirror