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Commit | Line | Data |
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54450f59 HV |
1 | /* |
2 | * adv7604 - Analog Devices ADV7604 video decoder driver | |
3 | * | |
4 | * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. | |
5 | * | |
6 | * This program is free software; you may redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
17 | * SOFTWARE. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * References (c = chapter, p = page): | |
23 | * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, | |
24 | * Revision 2.5, June 2010 | |
25 | * REF_02 - Analog devices, Register map documentation, Documentation of | |
26 | * the register maps, Software manual, Rev. F, June 2010 | |
27 | * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 | |
28 | */ | |
29 | ||
c72a53ce | 30 | #include <linux/delay.h> |
e9d50e9e | 31 | #include <linux/gpio/consumer.h> |
516613c1 | 32 | #include <linux/hdmi.h> |
c72a53ce | 33 | #include <linux/i2c.h> |
54450f59 HV |
34 | #include <linux/kernel.h> |
35 | #include <linux/module.h> | |
36 | #include <linux/slab.h> | |
c72a53ce | 37 | #include <linux/v4l2-dv-timings.h> |
54450f59 HV |
38 | #include <linux/videodev2.h> |
39 | #include <linux/workqueue.h> | |
f862f57d | 40 | #include <linux/regmap.h> |
c72a53ce | 41 | |
b5dcee22 | 42 | #include <media/i2c/adv7604.h> |
54450f59 | 43 | #include <media/v4l2-ctrls.h> |
c72a53ce | 44 | #include <media/v4l2-device.h> |
0975626d | 45 | #include <media/v4l2-event.h> |
25764158 | 46 | #include <media/v4l2-dv-timings.h> |
6fa88045 | 47 | #include <media/v4l2-of.h> |
54450f59 HV |
48 | |
49 | static int debug; | |
50 | module_param(debug, int, 0644); | |
51 | MODULE_PARM_DESC(debug, "debug level (0-2)"); | |
52 | ||
53 | MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); | |
54 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); | |
55 | MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); | |
56 | MODULE_LICENSE("GPL"); | |
57 | ||
58 | /* ADV7604 system clock frequency */ | |
b44b2e06 | 59 | #define ADV76XX_FSC (28636360) |
54450f59 | 60 | |
b44b2e06 | 61 | #define ADV76XX_RGB_OUT (1 << 1) |
539b33b0 | 62 | |
b44b2e06 | 63 | #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) |
539b33b0 | 64 | #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) |
b44b2e06 | 65 | #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) |
539b33b0 | 66 | |
b44b2e06 | 67 | #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) |
539b33b0 | 68 | #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) |
b44b2e06 | 69 | #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) |
539b33b0 | 70 | #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) |
b44b2e06 | 71 | #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) |
539b33b0 LP |
72 | #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) |
73 | ||
b44b2e06 PA |
74 | #define ADV76XX_OP_CH_SEL_GBR (0 << 5) |
75 | #define ADV76XX_OP_CH_SEL_GRB (1 << 5) | |
76 | #define ADV76XX_OP_CH_SEL_BGR (2 << 5) | |
77 | #define ADV76XX_OP_CH_SEL_RGB (3 << 5) | |
78 | #define ADV76XX_OP_CH_SEL_BRG (4 << 5) | |
79 | #define ADV76XX_OP_CH_SEL_RBG (5 << 5) | |
539b33b0 | 80 | |
b44b2e06 | 81 | #define ADV76XX_OP_SWAP_CB_CR (1 << 0) |
539b33b0 | 82 | |
b44b2e06 | 83 | enum adv76xx_type { |
d42010a1 LPC |
84 | ADV7604, |
85 | ADV7611, | |
8331d30b | 86 | ADV7612, |
d42010a1 LPC |
87 | }; |
88 | ||
b44b2e06 | 89 | struct adv76xx_reg_seq { |
d42010a1 LPC |
90 | unsigned int reg; |
91 | u8 val; | |
92 | }; | |
93 | ||
b44b2e06 | 94 | struct adv76xx_format_info { |
f5fe58fd | 95 | u32 code; |
539b33b0 LP |
96 | u8 op_ch_sel; |
97 | bool rgb_out; | |
98 | bool swap_cb_cr; | |
99 | u8 op_format_sel; | |
100 | }; | |
101 | ||
516613c1 HV |
102 | struct adv76xx_cfg_read_infoframe { |
103 | const char *desc; | |
104 | u8 present_mask; | |
105 | u8 head_addr; | |
106 | u8 payload_addr; | |
107 | }; | |
108 | ||
b44b2e06 PA |
109 | struct adv76xx_chip_info { |
110 | enum adv76xx_type type; | |
d42010a1 LPC |
111 | |
112 | bool has_afe; | |
113 | unsigned int max_port; | |
114 | unsigned int num_dv_ports; | |
115 | ||
116 | unsigned int edid_enable_reg; | |
117 | unsigned int edid_status_reg; | |
118 | unsigned int lcf_reg; | |
119 | ||
120 | unsigned int cable_det_mask; | |
121 | unsigned int tdms_lock_mask; | |
122 | unsigned int fmt_change_digital_mask; | |
80f4944e | 123 | unsigned int cp_csc; |
d42010a1 | 124 | |
b44b2e06 | 125 | const struct adv76xx_format_info *formats; |
539b33b0 LP |
126 | unsigned int nformats; |
127 | ||
d42010a1 LPC |
128 | void (*set_termination)(struct v4l2_subdev *sd, bool enable); |
129 | void (*setup_irqs)(struct v4l2_subdev *sd); | |
130 | unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); | |
131 | unsigned int (*read_cable_det)(struct v4l2_subdev *sd); | |
132 | ||
133 | /* 0 = AFE, 1 = HDMI */ | |
b44b2e06 | 134 | const struct adv76xx_reg_seq *recommended_settings[2]; |
d42010a1 LPC |
135 | unsigned int num_recommended_settings[2]; |
136 | ||
137 | unsigned long page_mask; | |
5380baaf | 138 | |
139 | /* Masks for timings */ | |
140 | unsigned int linewidth_mask; | |
141 | unsigned int field0_height_mask; | |
142 | unsigned int field1_height_mask; | |
143 | unsigned int hfrontporch_mask; | |
144 | unsigned int hsync_mask; | |
145 | unsigned int hbackporch_mask; | |
146 | unsigned int field0_vfrontporch_mask; | |
147 | unsigned int field1_vfrontporch_mask; | |
148 | unsigned int field0_vsync_mask; | |
149 | unsigned int field1_vsync_mask; | |
150 | unsigned int field0_vbackporch_mask; | |
151 | unsigned int field1_vbackporch_mask; | |
d42010a1 LPC |
152 | }; |
153 | ||
54450f59 HV |
154 | /* |
155 | ********************************************************************** | |
156 | * | |
157 | * Arrays with configuration parameters for the ADV7604 | |
158 | * | |
159 | ********************************************************************** | |
160 | */ | |
c784b1e2 | 161 | |
b44b2e06 PA |
162 | struct adv76xx_state { |
163 | const struct adv76xx_chip_info *info; | |
164 | struct adv76xx_platform_data pdata; | |
539b33b0 | 165 | |
e9d50e9e LP |
166 | struct gpio_desc *hpd_gpio[4]; |
167 | ||
54450f59 | 168 | struct v4l2_subdev sd; |
b44b2e06 | 169 | struct media_pad pads[ADV76XX_PAD_MAX]; |
c784b1e2 | 170 | unsigned int source_pad; |
539b33b0 | 171 | |
54450f59 | 172 | struct v4l2_ctrl_handler hdl; |
539b33b0 | 173 | |
b44b2e06 | 174 | enum adv76xx_pad selected_input; |
539b33b0 | 175 | |
54450f59 | 176 | struct v4l2_dv_timings timings; |
b44b2e06 | 177 | const struct adv76xx_format_info *format; |
539b33b0 | 178 | |
4a31a93a MR |
179 | struct { |
180 | u8 edid[256]; | |
181 | u32 present; | |
182 | unsigned blocks; | |
183 | } edid; | |
dd08beb9 | 184 | u16 spa_port_a[2]; |
54450f59 HV |
185 | struct v4l2_fract aspect_ratio; |
186 | u32 rgb_quantization_range; | |
187 | struct workqueue_struct *work_queues; | |
188 | struct delayed_work delayed_work_enable_hotplug; | |
cf9afb1d | 189 | bool restart_stdi_once; |
54450f59 HV |
190 | |
191 | /* i2c clients */ | |
b44b2e06 | 192 | struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; |
54450f59 | 193 | |
f862f57d PA |
194 | /* Regmaps */ |
195 | struct regmap *regmap[ADV76XX_PAGE_MAX]; | |
196 | ||
54450f59 HV |
197 | /* controls */ |
198 | struct v4l2_ctrl *detect_tx_5v_ctrl; | |
199 | struct v4l2_ctrl *analog_sampling_phase_ctrl; | |
200 | struct v4l2_ctrl *free_run_color_manual_ctrl; | |
201 | struct v4l2_ctrl *free_run_color_ctrl; | |
202 | struct v4l2_ctrl *rgb_quantization_range_ctrl; | |
203 | }; | |
204 | ||
b44b2e06 | 205 | static bool adv76xx_has_afe(struct adv76xx_state *state) |
d42010a1 LPC |
206 | { |
207 | return state->info->has_afe; | |
208 | } | |
209 | ||
54450f59 | 210 | /* Supported CEA and DMT timings */ |
b44b2e06 | 211 | static const struct v4l2_dv_timings adv76xx_timings[] = { |
54450f59 HV |
212 | V4L2_DV_BT_CEA_720X480P59_94, |
213 | V4L2_DV_BT_CEA_720X576P50, | |
214 | V4L2_DV_BT_CEA_1280X720P24, | |
215 | V4L2_DV_BT_CEA_1280X720P25, | |
54450f59 HV |
216 | V4L2_DV_BT_CEA_1280X720P50, |
217 | V4L2_DV_BT_CEA_1280X720P60, | |
218 | V4L2_DV_BT_CEA_1920X1080P24, | |
219 | V4L2_DV_BT_CEA_1920X1080P25, | |
220 | V4L2_DV_BT_CEA_1920X1080P30, | |
221 | V4L2_DV_BT_CEA_1920X1080P50, | |
222 | V4L2_DV_BT_CEA_1920X1080P60, | |
223 | ||
ccbd5bc4 | 224 | /* sorted by DMT ID */ |
54450f59 HV |
225 | V4L2_DV_BT_DMT_640X350P85, |
226 | V4L2_DV_BT_DMT_640X400P85, | |
227 | V4L2_DV_BT_DMT_720X400P85, | |
228 | V4L2_DV_BT_DMT_640X480P60, | |
229 | V4L2_DV_BT_DMT_640X480P72, | |
230 | V4L2_DV_BT_DMT_640X480P75, | |
231 | V4L2_DV_BT_DMT_640X480P85, | |
232 | V4L2_DV_BT_DMT_800X600P56, | |
233 | V4L2_DV_BT_DMT_800X600P60, | |
234 | V4L2_DV_BT_DMT_800X600P72, | |
235 | V4L2_DV_BT_DMT_800X600P75, | |
236 | V4L2_DV_BT_DMT_800X600P85, | |
237 | V4L2_DV_BT_DMT_848X480P60, | |
238 | V4L2_DV_BT_DMT_1024X768P60, | |
239 | V4L2_DV_BT_DMT_1024X768P70, | |
240 | V4L2_DV_BT_DMT_1024X768P75, | |
241 | V4L2_DV_BT_DMT_1024X768P85, | |
242 | V4L2_DV_BT_DMT_1152X864P75, | |
243 | V4L2_DV_BT_DMT_1280X768P60_RB, | |
244 | V4L2_DV_BT_DMT_1280X768P60, | |
245 | V4L2_DV_BT_DMT_1280X768P75, | |
246 | V4L2_DV_BT_DMT_1280X768P85, | |
247 | V4L2_DV_BT_DMT_1280X800P60_RB, | |
248 | V4L2_DV_BT_DMT_1280X800P60, | |
249 | V4L2_DV_BT_DMT_1280X800P75, | |
250 | V4L2_DV_BT_DMT_1280X800P85, | |
251 | V4L2_DV_BT_DMT_1280X960P60, | |
252 | V4L2_DV_BT_DMT_1280X960P85, | |
253 | V4L2_DV_BT_DMT_1280X1024P60, | |
254 | V4L2_DV_BT_DMT_1280X1024P75, | |
255 | V4L2_DV_BT_DMT_1280X1024P85, | |
256 | V4L2_DV_BT_DMT_1360X768P60, | |
257 | V4L2_DV_BT_DMT_1400X1050P60_RB, | |
258 | V4L2_DV_BT_DMT_1400X1050P60, | |
259 | V4L2_DV_BT_DMT_1400X1050P75, | |
260 | V4L2_DV_BT_DMT_1400X1050P85, | |
261 | V4L2_DV_BT_DMT_1440X900P60_RB, | |
262 | V4L2_DV_BT_DMT_1440X900P60, | |
263 | V4L2_DV_BT_DMT_1600X1200P60, | |
264 | V4L2_DV_BT_DMT_1680X1050P60_RB, | |
265 | V4L2_DV_BT_DMT_1680X1050P60, | |
266 | V4L2_DV_BT_DMT_1792X1344P60, | |
267 | V4L2_DV_BT_DMT_1856X1392P60, | |
268 | V4L2_DV_BT_DMT_1920X1200P60_RB, | |
547ed542 | 269 | V4L2_DV_BT_DMT_1366X768P60_RB, |
54450f59 HV |
270 | V4L2_DV_BT_DMT_1366X768P60, |
271 | V4L2_DV_BT_DMT_1920X1080P60, | |
272 | { }, | |
273 | }; | |
274 | ||
b44b2e06 | 275 | struct adv76xx_video_standards { |
ccbd5bc4 HV |
276 | struct v4l2_dv_timings timings; |
277 | u8 vid_std; | |
278 | u8 v_freq; | |
279 | }; | |
280 | ||
281 | /* sorted by number of lines */ | |
b44b2e06 | 282 | static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { |
ccbd5bc4 HV |
283 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ |
284 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
285 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, | |
286 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, | |
287 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
288 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
289 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
290 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
291 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
292 | /* TODO add 1920x1080P60_RB (CVT timing) */ | |
293 | { }, | |
294 | }; | |
295 | ||
296 | /* sorted by number of lines */ | |
b44b2e06 | 297 | static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { |
ccbd5bc4 HV |
298 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
299 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
300 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
301 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
302 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
303 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
304 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
305 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
306 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
307 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
308 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
309 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
310 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
311 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
312 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
313 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, | |
314 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, | |
315 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, | |
316 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, | |
317 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ | |
318 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ | |
319 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, | |
320 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ | |
321 | { }, | |
322 | }; | |
323 | ||
324 | /* sorted by number of lines */ | |
b44b2e06 | 325 | static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { |
ccbd5bc4 HV |
326 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, |
327 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
328 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, | |
329 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, | |
330 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
331 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
332 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
333 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
334 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
335 | { }, | |
336 | }; | |
337 | ||
338 | /* sorted by number of lines */ | |
b44b2e06 | 339 | static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { |
ccbd5bc4 HV |
340 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, |
341 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
342 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
343 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
344 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
345 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
346 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
347 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
348 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
349 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
350 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
351 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
352 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
353 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
354 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
355 | { }, | |
356 | }; | |
357 | ||
48519838 HV |
358 | static const struct v4l2_event adv76xx_ev_fmt = { |
359 | .type = V4L2_EVENT_SOURCE_CHANGE, | |
360 | .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, | |
361 | }; | |
362 | ||
54450f59 HV |
363 | /* ----------------------------------------------------------------------- */ |
364 | ||
b44b2e06 | 365 | static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) |
54450f59 | 366 | { |
b44b2e06 | 367 | return container_of(sd, struct adv76xx_state, sd); |
54450f59 HV |
368 | } |
369 | ||
54450f59 HV |
370 | static inline unsigned htotal(const struct v4l2_bt_timings *t) |
371 | { | |
eacf8f9a | 372 | return V4L2_DV_BT_FRAME_WIDTH(t); |
54450f59 HV |
373 | } |
374 | ||
54450f59 HV |
375 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) |
376 | { | |
eacf8f9a | 377 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
54450f59 HV |
378 | } |
379 | ||
380 | /* ----------------------------------------------------------------------- */ | |
381 | ||
f862f57d PA |
382 | static int adv76xx_read_check(struct adv76xx_state *state, |
383 | int client_page, u8 reg) | |
54450f59 | 384 | { |
f862f57d | 385 | struct i2c_client *client = state->i2c_clients[client_page]; |
54450f59 | 386 | int err; |
f862f57d | 387 | unsigned int val; |
54450f59 | 388 | |
f862f57d PA |
389 | err = regmap_read(state->regmap[client_page], reg, &val); |
390 | ||
391 | if (err) { | |
392 | v4l_err(client, "error reading %02x, %02x\n", | |
393 | client->addr, reg); | |
394 | return err; | |
54450f59 | 395 | } |
f862f57d | 396 | return val; |
54450f59 HV |
397 | } |
398 | ||
f862f57d PA |
399 | /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX |
400 | * size to one or more registers. | |
401 | * | |
402 | * A value of zero will be returned on success, a negative errno will | |
403 | * be returned in error cases. | |
404 | */ | |
405 | static int adv76xx_write_block(struct adv76xx_state *state, int client_page, | |
406 | unsigned int init_reg, const void *val, | |
407 | size_t val_len) | |
54450f59 | 408 | { |
f862f57d PA |
409 | struct regmap *regmap = state->regmap[client_page]; |
410 | ||
411 | if (val_len > I2C_SMBUS_BLOCK_MAX) | |
412 | val_len = I2C_SMBUS_BLOCK_MAX; | |
54450f59 | 413 | |
f862f57d | 414 | return regmap_raw_write(regmap, init_reg, val, val_len); |
54450f59 HV |
415 | } |
416 | ||
417 | /* ----------------------------------------------------------------------- */ | |
418 | ||
419 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) | |
420 | { | |
b44b2e06 | 421 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 422 | |
f862f57d | 423 | return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); |
54450f59 HV |
424 | } |
425 | ||
426 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
427 | { | |
b44b2e06 | 428 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 429 | |
f862f57d | 430 | return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); |
54450f59 HV |
431 | } |
432 | ||
22d97e56 | 433 | static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 434 | { |
22d97e56 | 435 | return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); |
54450f59 HV |
436 | } |
437 | ||
438 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) | |
439 | { | |
b44b2e06 | 440 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 441 | |
f862f57d | 442 | return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); |
54450f59 HV |
443 | } |
444 | ||
445 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
446 | { | |
b44b2e06 | 447 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 448 | |
f862f57d | 449 | return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); |
54450f59 HV |
450 | } |
451 | ||
452 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) | |
453 | { | |
b44b2e06 | 454 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 455 | |
f862f57d | 456 | return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); |
54450f59 HV |
457 | } |
458 | ||
459 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
460 | { | |
b44b2e06 | 461 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 462 | |
f862f57d | 463 | return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); |
54450f59 HV |
464 | } |
465 | ||
54450f59 HV |
466 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) |
467 | { | |
b44b2e06 | 468 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 469 | |
f862f57d | 470 | return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); |
54450f59 HV |
471 | } |
472 | ||
473 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
474 | { | |
b44b2e06 | 475 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 476 | |
f862f57d | 477 | return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); |
54450f59 HV |
478 | } |
479 | ||
54450f59 HV |
480 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) |
481 | { | |
b44b2e06 | 482 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 483 | |
f862f57d | 484 | return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); |
54450f59 HV |
485 | } |
486 | ||
487 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
488 | { | |
b44b2e06 | 489 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 490 | |
f862f57d | 491 | return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); |
54450f59 HV |
492 | } |
493 | ||
494 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) | |
495 | { | |
b44b2e06 | 496 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 497 | |
f862f57d | 498 | return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); |
54450f59 HV |
499 | } |
500 | ||
501 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
502 | { | |
b44b2e06 | 503 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 504 | |
f862f57d | 505 | return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); |
54450f59 HV |
506 | } |
507 | ||
22d97e56 | 508 | static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 509 | { |
22d97e56 | 510 | return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); |
54450f59 HV |
511 | } |
512 | ||
513 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) | |
514 | { | |
b44b2e06 | 515 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 516 | |
f862f57d | 517 | return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); |
54450f59 HV |
518 | } |
519 | ||
520 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
521 | { | |
b44b2e06 | 522 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 523 | |
f862f57d | 524 | return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); |
54450f59 HV |
525 | } |
526 | ||
54450f59 | 527 | static inline int edid_write_block(struct v4l2_subdev *sd, |
f862f57d | 528 | unsigned int total_len, const u8 *val) |
54450f59 | 529 | { |
b44b2e06 | 530 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 531 | int err = 0; |
f862f57d PA |
532 | int i = 0; |
533 | int len = 0; | |
54450f59 | 534 | |
f862f57d PA |
535 | v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", |
536 | __func__, total_len); | |
537 | ||
538 | while (!err && i < total_len) { | |
539 | len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? | |
540 | I2C_SMBUS_BLOCK_MAX : | |
541 | (total_len - i); | |
542 | ||
543 | err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, | |
544 | i, val + i, len); | |
545 | i += len; | |
546 | } | |
54450f59 | 547 | |
dd08beb9 MR |
548 | return err; |
549 | } | |
54450f59 | 550 | |
b44b2e06 | 551 | static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) |
e9d50e9e LP |
552 | { |
553 | unsigned int i; | |
554 | ||
269bd132 | 555 | for (i = 0; i < state->info->num_dv_ports; ++i) |
e9d50e9e | 556 | gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); |
e9d50e9e | 557 | |
b44b2e06 | 558 | v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); |
e9d50e9e LP |
559 | } |
560 | ||
b44b2e06 | 561 | static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) |
dd08beb9 MR |
562 | { |
563 | struct delayed_work *dwork = to_delayed_work(work); | |
b44b2e06 | 564 | struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, |
dd08beb9 MR |
565 | delayed_work_enable_hotplug); |
566 | struct v4l2_subdev *sd = &state->sd; | |
54450f59 | 567 | |
dd08beb9 | 568 | v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); |
54450f59 | 569 | |
b44b2e06 | 570 | adv76xx_set_hpd(state, state->edid.present); |
54450f59 HV |
571 | } |
572 | ||
573 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) | |
574 | { | |
b44b2e06 | 575 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 576 | |
f862f57d | 577 | return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); |
54450f59 HV |
578 | } |
579 | ||
51182a94 LP |
580 | static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
581 | { | |
582 | return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; | |
583 | } | |
584 | ||
54450f59 HV |
585 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
586 | { | |
b44b2e06 | 587 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 588 | |
f862f57d | 589 | return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); |
54450f59 HV |
590 | } |
591 | ||
22d97e56 | 592 | static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
4a31a93a | 593 | { |
22d97e56 | 594 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); |
4a31a93a MR |
595 | } |
596 | ||
54450f59 HV |
597 | static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
598 | { | |
b44b2e06 | 599 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 600 | |
f862f57d | 601 | return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); |
54450f59 HV |
602 | } |
603 | ||
604 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) | |
605 | { | |
b44b2e06 | 606 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 607 | |
f862f57d | 608 | return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); |
54450f59 HV |
609 | } |
610 | ||
51182a94 LP |
611 | static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
612 | { | |
613 | return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; | |
614 | } | |
615 | ||
54450f59 HV |
616 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
617 | { | |
b44b2e06 | 618 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 619 | |
f862f57d | 620 | return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); |
54450f59 HV |
621 | } |
622 | ||
22d97e56 | 623 | static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
54450f59 | 624 | { |
22d97e56 | 625 | return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); |
54450f59 HV |
626 | } |
627 | ||
628 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) | |
629 | { | |
b44b2e06 | 630 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 631 | |
f862f57d | 632 | return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); |
54450f59 HV |
633 | } |
634 | ||
635 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
636 | { | |
b44b2e06 | 637 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 638 | |
f862f57d | 639 | return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); |
05cacb17 | 640 | } |
d42010a1 | 641 | |
b44b2e06 PA |
642 | #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) |
643 | #define ADV76XX_REG_SEQ_TERM 0xffff | |
d42010a1 LPC |
644 | |
645 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
b44b2e06 | 646 | static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) |
d42010a1 | 647 | { |
b44b2e06 | 648 | struct adv76xx_state *state = to_state(sd); |
d42010a1 | 649 | unsigned int page = reg >> 8; |
f862f57d PA |
650 | unsigned int val; |
651 | int err; | |
d42010a1 LPC |
652 | |
653 | if (!(BIT(page) & state->info->page_mask)) | |
654 | return -EINVAL; | |
655 | ||
656 | reg &= 0xff; | |
f862f57d | 657 | err = regmap_read(state->regmap[page], reg, &val); |
d42010a1 | 658 | |
f862f57d | 659 | return err ? err : val; |
d42010a1 LPC |
660 | } |
661 | #endif | |
662 | ||
b44b2e06 | 663 | static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) |
d42010a1 | 664 | { |
b44b2e06 | 665 | struct adv76xx_state *state = to_state(sd); |
d42010a1 LPC |
666 | unsigned int page = reg >> 8; |
667 | ||
668 | if (!(BIT(page) & state->info->page_mask)) | |
669 | return -EINVAL; | |
670 | ||
671 | reg &= 0xff; | |
672 | ||
f862f57d | 673 | return regmap_write(state->regmap[page], reg, val); |
d42010a1 LPC |
674 | } |
675 | ||
b44b2e06 PA |
676 | static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, |
677 | const struct adv76xx_reg_seq *reg_seq) | |
d42010a1 LPC |
678 | { |
679 | unsigned int i; | |
680 | ||
b44b2e06 PA |
681 | for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) |
682 | adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); | |
d42010a1 LPC |
683 | } |
684 | ||
539b33b0 LP |
685 | /* ----------------------------------------------------------------------------- |
686 | * Format helpers | |
687 | */ | |
688 | ||
b44b2e06 PA |
689 | static const struct adv76xx_format_info adv7604_formats[] = { |
690 | { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, | |
691 | ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
692 | { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, | |
693 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
694 | { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, | |
695 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
696 | { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, | |
697 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
698 | { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, | |
699 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
700 | { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, | |
701 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
702 | { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, | |
703 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
704 | { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, | |
705 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
706 | { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, | |
707 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
708 | { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, | |
709 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
710 | { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, | |
711 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
712 | { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, | |
713 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
714 | { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, | |
715 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
716 | { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, | |
717 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
718 | { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, | |
719 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
720 | { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, | |
721 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
722 | { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, | |
723 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
724 | { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, | |
725 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
726 | { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, | |
727 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
539b33b0 LP |
728 | }; |
729 | ||
b44b2e06 PA |
730 | static const struct adv76xx_format_info adv7611_formats[] = { |
731 | { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, | |
732 | ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
733 | { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, | |
734 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
735 | { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, | |
736 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
737 | { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, | |
738 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
739 | { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, | |
740 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
741 | { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, | |
742 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
743 | { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, | |
744 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
745 | { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, | |
746 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
747 | { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, | |
748 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
749 | { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, | |
750 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
751 | { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, | |
752 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
753 | { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, | |
754 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
755 | { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, | |
756 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, | |
539b33b0 LP |
757 | }; |
758 | ||
8331d30b WT |
759 | static const struct adv76xx_format_info adv7612_formats[] = { |
760 | { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, | |
761 | ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
762 | { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, | |
763 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
764 | { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, | |
765 | ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
766 | { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, | |
767 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
768 | { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, | |
769 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
770 | { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, | |
771 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
772 | { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, | |
773 | ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, | |
774 | }; | |
775 | ||
b44b2e06 PA |
776 | static const struct adv76xx_format_info * |
777 | adv76xx_format_info(struct adv76xx_state *state, u32 code) | |
539b33b0 LP |
778 | { |
779 | unsigned int i; | |
780 | ||
781 | for (i = 0; i < state->info->nformats; ++i) { | |
782 | if (state->info->formats[i].code == code) | |
783 | return &state->info->formats[i]; | |
784 | } | |
785 | ||
786 | return NULL; | |
787 | } | |
788 | ||
54450f59 HV |
789 | /* ----------------------------------------------------------------------- */ |
790 | ||
4a31a93a MR |
791 | static inline bool is_analog_input(struct v4l2_subdev *sd) |
792 | { | |
b44b2e06 | 793 | struct adv76xx_state *state = to_state(sd); |
4a31a93a | 794 | |
c784b1e2 LP |
795 | return state->selected_input == ADV7604_PAD_VGA_RGB || |
796 | state->selected_input == ADV7604_PAD_VGA_COMP; | |
4a31a93a MR |
797 | } |
798 | ||
799 | static inline bool is_digital_input(struct v4l2_subdev *sd) | |
800 | { | |
b44b2e06 | 801 | struct adv76xx_state *state = to_state(sd); |
4a31a93a | 802 | |
b44b2e06 | 803 | return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || |
c784b1e2 LP |
804 | state->selected_input == ADV7604_PAD_HDMI_PORT_B || |
805 | state->selected_input == ADV7604_PAD_HDMI_PORT_C || | |
806 | state->selected_input == ADV7604_PAD_HDMI_PORT_D; | |
4a31a93a MR |
807 | } |
808 | ||
809 | /* ----------------------------------------------------------------------- */ | |
810 | ||
54450f59 | 811 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
b44b2e06 | 812 | static void adv76xx_inv_register(struct v4l2_subdev *sd) |
54450f59 HV |
813 | { |
814 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); | |
815 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); | |
816 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); | |
817 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); | |
818 | v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); | |
819 | v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); | |
820 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); | |
821 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); | |
822 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); | |
823 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); | |
824 | v4l2_info(sd, "0xa00-0xaff: Test Map\n"); | |
825 | v4l2_info(sd, "0xb00-0xbff: CP Map\n"); | |
826 | v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); | |
827 | } | |
828 | ||
b44b2e06 | 829 | static int adv76xx_g_register(struct v4l2_subdev *sd, |
54450f59 HV |
830 | struct v4l2_dbg_register *reg) |
831 | { | |
d42010a1 LPC |
832 | int ret; |
833 | ||
b44b2e06 | 834 | ret = adv76xx_read_reg(sd, reg->reg); |
d42010a1 | 835 | if (ret < 0) { |
54450f59 | 836 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
b44b2e06 | 837 | adv76xx_inv_register(sd); |
d42010a1 | 838 | return ret; |
54450f59 | 839 | } |
d42010a1 LPC |
840 | |
841 | reg->size = 1; | |
842 | reg->val = ret; | |
843 | ||
54450f59 HV |
844 | return 0; |
845 | } | |
846 | ||
b44b2e06 | 847 | static int adv76xx_s_register(struct v4l2_subdev *sd, |
977ba3b1 | 848 | const struct v4l2_dbg_register *reg) |
54450f59 | 849 | { |
d42010a1 | 850 | int ret; |
1577461b | 851 | |
b44b2e06 | 852 | ret = adv76xx_write_reg(sd, reg->reg, reg->val); |
d42010a1 | 853 | if (ret < 0) { |
54450f59 | 854 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
b44b2e06 | 855 | adv76xx_inv_register(sd); |
d42010a1 | 856 | return ret; |
54450f59 | 857 | } |
d42010a1 | 858 | |
54450f59 HV |
859 | return 0; |
860 | } | |
861 | #endif | |
862 | ||
d42010a1 LPC |
863 | static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) |
864 | { | |
865 | u8 value = io_read(sd, 0x6f); | |
866 | ||
867 | return ((value & 0x10) >> 4) | |
868 | | ((value & 0x08) >> 2) | |
869 | | ((value & 0x04) << 0) | |
870 | | ((value & 0x02) << 2); | |
871 | } | |
872 | ||
873 | static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) | |
874 | { | |
875 | u8 value = io_read(sd, 0x6f); | |
876 | ||
877 | return value & 1; | |
878 | } | |
879 | ||
7111cddd WT |
880 | static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) |
881 | { | |
882 | /* Reads CABLE_DET_A_RAW. For input B support, need to | |
883 | * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) | |
884 | */ | |
885 | u8 value = io_read(sd, 0x6f); | |
886 | ||
887 | return value & 1; | |
888 | } | |
889 | ||
b44b2e06 | 890 | static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) |
54450f59 | 891 | { |
b44b2e06 PA |
892 | struct adv76xx_state *state = to_state(sd); |
893 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 | 894 | |
54450f59 | 895 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, |
d42010a1 | 896 | info->read_cable_det(sd)); |
54450f59 HV |
897 | } |
898 | ||
ccbd5bc4 HV |
899 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
900 | u8 prim_mode, | |
b44b2e06 | 901 | const struct adv76xx_video_standards *predef_vid_timings, |
ccbd5bc4 HV |
902 | const struct v4l2_dv_timings *timings) |
903 | { | |
ccbd5bc4 HV |
904 | int i; |
905 | ||
906 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { | |
ef1ed8f5 | 907 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, |
85f9e06c | 908 | is_digital_input(sd) ? 250000 : 1000000, false)) |
ccbd5bc4 HV |
909 | continue; |
910 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ | |
911 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + | |
912 | prim_mode); /* v_freq and prim mode */ | |
913 | return 0; | |
914 | } | |
915 | ||
916 | return -1; | |
917 | } | |
918 | ||
919 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, | |
920 | struct v4l2_dv_timings *timings) | |
54450f59 | 921 | { |
b44b2e06 | 922 | struct adv76xx_state *state = to_state(sd); |
ccbd5bc4 HV |
923 | int err; |
924 | ||
925 | v4l2_dbg(1, debug, sd, "%s", __func__); | |
926 | ||
b44b2e06 | 927 | if (adv76xx_has_afe(state)) { |
d42010a1 LPC |
928 | /* reset to default values */ |
929 | io_write(sd, 0x16, 0x43); | |
930 | io_write(sd, 0x17, 0x5a); | |
931 | } | |
ccbd5bc4 | 932 | /* disable embedded syncs for auto graphics mode */ |
22d97e56 | 933 | cp_write_clr_set(sd, 0x81, 0x10, 0x00); |
ccbd5bc4 HV |
934 | cp_write(sd, 0x8f, 0x00); |
935 | cp_write(sd, 0x90, 0x00); | |
936 | cp_write(sd, 0xa2, 0x00); | |
937 | cp_write(sd, 0xa3, 0x00); | |
938 | cp_write(sd, 0xa4, 0x00); | |
939 | cp_write(sd, 0xa5, 0x00); | |
940 | cp_write(sd, 0xa6, 0x00); | |
941 | cp_write(sd, 0xa7, 0x00); | |
942 | cp_write(sd, 0xab, 0x00); | |
943 | cp_write(sd, 0xac, 0x00); | |
944 | ||
4a31a93a | 945 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
946 | err = find_and_set_predefined_video_timings(sd, |
947 | 0x01, adv7604_prim_mode_comp, timings); | |
948 | if (err) | |
949 | err = find_and_set_predefined_video_timings(sd, | |
950 | 0x02, adv7604_prim_mode_gr, timings); | |
4a31a93a | 951 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 952 | err = find_and_set_predefined_video_timings(sd, |
b44b2e06 | 953 | 0x05, adv76xx_prim_mode_hdmi_comp, timings); |
ccbd5bc4 HV |
954 | if (err) |
955 | err = find_and_set_predefined_video_timings(sd, | |
b44b2e06 | 956 | 0x06, adv76xx_prim_mode_hdmi_gr, timings); |
4a31a93a MR |
957 | } else { |
958 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
959 | __func__, state->selected_input); | |
ccbd5bc4 | 960 | err = -1; |
ccbd5bc4 HV |
961 | } |
962 | ||
963 | ||
964 | return err; | |
965 | } | |
966 | ||
967 | static void configure_custom_video_timings(struct v4l2_subdev *sd, | |
968 | const struct v4l2_bt_timings *bt) | |
969 | { | |
b44b2e06 | 970 | struct adv76xx_state *state = to_state(sd); |
ccbd5bc4 HV |
971 | u32 width = htotal(bt); |
972 | u32 height = vtotal(bt); | |
973 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; | |
974 | u16 cp_start_eav = width - bt->hfrontporch; | |
975 | u16 cp_start_vbi = height - bt->vfrontporch; | |
976 | u16 cp_end_vbi = bt->vsync + bt->vbackporch; | |
977 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? | |
b44b2e06 | 978 | ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; |
ccbd5bc4 HV |
979 | const u8 pll[2] = { |
980 | 0xc0 | ((width >> 8) & 0x1f), | |
981 | width & 0xff | |
982 | }; | |
54450f59 HV |
983 | |
984 | v4l2_dbg(2, debug, sd, "%s\n", __func__); | |
985 | ||
4a31a93a | 986 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
987 | /* auto graphics */ |
988 | io_write(sd, 0x00, 0x07); /* video std */ | |
989 | io_write(sd, 0x01, 0x02); /* prim mode */ | |
990 | /* enable embedded syncs for auto graphics mode */ | |
22d97e56 | 991 | cp_write_clr_set(sd, 0x81, 0x10, 0x10); |
54450f59 | 992 | |
ccbd5bc4 | 993 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
54450f59 HV |
994 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
995 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ | |
f862f57d PA |
996 | if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], |
997 | 0x16, pll, 2)) | |
54450f59 | 998 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); |
54450f59 HV |
999 | |
1000 | /* active video - horizontal timing */ | |
54450f59 | 1001 | cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); |
ccbd5bc4 | 1002 | cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | |
4a31a93a | 1003 | ((cp_start_eav >> 8) & 0x0f)); |
54450f59 HV |
1004 | cp_write(sd, 0xa4, cp_start_eav & 0xff); |
1005 | ||
1006 | /* active video - vertical timing */ | |
54450f59 | 1007 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); |
ccbd5bc4 | 1008 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | |
4a31a93a | 1009 | ((cp_end_vbi >> 8) & 0xf)); |
54450f59 | 1010 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); |
4a31a93a | 1011 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 1012 | /* set default prim_mode/vid_std for HDMI |
39c1cb2b | 1013 | according to [REF_03, c. 4.2] */ |
ccbd5bc4 HV |
1014 | io_write(sd, 0x00, 0x02); /* video std */ |
1015 | io_write(sd, 0x01, 0x06); /* prim mode */ | |
4a31a93a MR |
1016 | } else { |
1017 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1018 | __func__, state->selected_input); | |
54450f59 | 1019 | } |
54450f59 | 1020 | |
ccbd5bc4 HV |
1021 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); |
1022 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); | |
1023 | cp_write(sd, 0xab, (height >> 4) & 0xff); | |
1024 | cp_write(sd, 0xac, (height & 0x0f) << 4); | |
1025 | } | |
54450f59 | 1026 | |
b44b2e06 | 1027 | static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) |
5c6c6349 | 1028 | { |
b44b2e06 | 1029 | struct adv76xx_state *state = to_state(sd); |
5c6c6349 MR |
1030 | u8 offset_buf[4]; |
1031 | ||
1032 | if (auto_offset) { | |
1033 | offset_a = 0x3ff; | |
1034 | offset_b = 0x3ff; | |
1035 | offset_c = 0x3ff; | |
1036 | } | |
1037 | ||
1038 | v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1039 | __func__, auto_offset ? "Auto" : "Manual", | |
1040 | offset_a, offset_b, offset_c); | |
1041 | ||
1042 | offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); | |
1043 | offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); | |
1044 | offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); | |
1045 | offset_buf[3] = offset_c & 0x0ff; | |
1046 | ||
1047 | /* Registers must be written in this order with no i2c access in between */ | |
f862f57d PA |
1048 | if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], |
1049 | 0x77, offset_buf, 4)) | |
5c6c6349 MR |
1050 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); |
1051 | } | |
1052 | ||
b44b2e06 | 1053 | static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) |
5c6c6349 | 1054 | { |
b44b2e06 | 1055 | struct adv76xx_state *state = to_state(sd); |
5c6c6349 MR |
1056 | u8 gain_buf[4]; |
1057 | u8 gain_man = 1; | |
1058 | u8 agc_mode_man = 1; | |
1059 | ||
1060 | if (auto_gain) { | |
1061 | gain_man = 0; | |
1062 | agc_mode_man = 0; | |
1063 | gain_a = 0x100; | |
1064 | gain_b = 0x100; | |
1065 | gain_c = 0x100; | |
1066 | } | |
1067 | ||
1068 | v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1069 | __func__, auto_gain ? "Auto" : "Manual", | |
1070 | gain_a, gain_b, gain_c); | |
1071 | ||
1072 | gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); | |
1073 | gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); | |
1074 | gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); | |
1075 | gain_buf[3] = ((gain_c & 0x0ff)); | |
1076 | ||
1077 | /* Registers must be written in this order with no i2c access in between */ | |
f862f57d PA |
1078 | if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], |
1079 | 0x73, gain_buf, 4)) | |
5c6c6349 MR |
1080 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); |
1081 | } | |
1082 | ||
54450f59 HV |
1083 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) |
1084 | { | |
b44b2e06 | 1085 | struct adv76xx_state *state = to_state(sd); |
5c6c6349 MR |
1086 | bool rgb_output = io_read(sd, 0x02) & 0x02; |
1087 | bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; | |
1088 | ||
1089 | v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", | |
1090 | __func__, state->rgb_quantization_range, | |
1091 | rgb_output, hdmi_signal); | |
54450f59 | 1092 | |
b44b2e06 PA |
1093 | adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); |
1094 | adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); | |
9833239e | 1095 | |
54450f59 HV |
1096 | switch (state->rgb_quantization_range) { |
1097 | case V4L2_DV_RGB_RANGE_AUTO: | |
c784b1e2 | 1098 | if (state->selected_input == ADV7604_PAD_VGA_RGB) { |
9833239e MR |
1099 | /* Receiving analog RGB signal |
1100 | * Set RGB full range (0-255) */ | |
22d97e56 | 1101 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
9833239e MR |
1102 | break; |
1103 | } | |
1104 | ||
c784b1e2 | 1105 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
9833239e MR |
1106 | /* Receiving analog YPbPr signal |
1107 | * Set automode */ | |
22d97e56 | 1108 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); |
9833239e MR |
1109 | break; |
1110 | } | |
1111 | ||
5c6c6349 | 1112 | if (hdmi_signal) { |
9833239e MR |
1113 | /* Receiving HDMI signal |
1114 | * Set automode */ | |
22d97e56 | 1115 | io_write_clr_set(sd, 0x02, 0xf0, 0xf0); |
9833239e MR |
1116 | break; |
1117 | } | |
1118 | ||
1119 | /* Receiving DVI-D signal | |
1120 | * ADV7604 selects RGB limited range regardless of | |
1121 | * input format (CE/IT) in automatic mode */ | |
680fee04 | 1122 | if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { |
9833239e | 1123 | /* RGB limited range (16-235) */ |
22d97e56 | 1124 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); |
9833239e MR |
1125 | } else { |
1126 | /* RGB full range (0-255) */ | |
22d97e56 | 1127 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
5c6c6349 MR |
1128 | |
1129 | if (is_digital_input(sd) && rgb_output) { | |
b44b2e06 | 1130 | adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); |
5c6c6349 | 1131 | } else { |
b44b2e06 PA |
1132 | adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); |
1133 | adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); | |
5c6c6349 | 1134 | } |
54450f59 HV |
1135 | } |
1136 | break; | |
1137 | case V4L2_DV_RGB_RANGE_LIMITED: | |
c784b1e2 | 1138 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 | 1139 | /* YCrCb limited range (16-235) */ |
22d97e56 | 1140 | io_write_clr_set(sd, 0x02, 0xf0, 0x20); |
5c6c6349 | 1141 | break; |
d261e842 | 1142 | } |
5c6c6349 MR |
1143 | |
1144 | /* RGB limited range (16-235) */ | |
22d97e56 | 1145 | io_write_clr_set(sd, 0x02, 0xf0, 0x00); |
5c6c6349 | 1146 | |
54450f59 HV |
1147 | break; |
1148 | case V4L2_DV_RGB_RANGE_FULL: | |
c784b1e2 | 1149 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 | 1150 | /* YCrCb full range (0-255) */ |
22d97e56 | 1151 | io_write_clr_set(sd, 0x02, 0xf0, 0x60); |
5c6c6349 MR |
1152 | break; |
1153 | } | |
1154 | ||
1155 | /* RGB full range (0-255) */ | |
22d97e56 | 1156 | io_write_clr_set(sd, 0x02, 0xf0, 0x10); |
5c6c6349 MR |
1157 | |
1158 | if (is_analog_input(sd) || hdmi_signal) | |
1159 | break; | |
1160 | ||
1161 | /* Adjust gain/offset for DVI-D signals only */ | |
1162 | if (rgb_output) { | |
b44b2e06 | 1163 | adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); |
d261e842 | 1164 | } else { |
b44b2e06 PA |
1165 | adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); |
1166 | adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); | |
d261e842 | 1167 | } |
54450f59 HV |
1168 | break; |
1169 | } | |
1170 | } | |
1171 | ||
b44b2e06 | 1172 | static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) |
54450f59 | 1173 | { |
c269887c | 1174 | struct v4l2_subdev *sd = |
b44b2e06 | 1175 | &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; |
c269887c | 1176 | |
b44b2e06 | 1177 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
1178 | |
1179 | switch (ctrl->id) { | |
1180 | case V4L2_CID_BRIGHTNESS: | |
1181 | cp_write(sd, 0x3c, ctrl->val); | |
1182 | return 0; | |
1183 | case V4L2_CID_CONTRAST: | |
1184 | cp_write(sd, 0x3a, ctrl->val); | |
1185 | return 0; | |
1186 | case V4L2_CID_SATURATION: | |
1187 | cp_write(sd, 0x3b, ctrl->val); | |
1188 | return 0; | |
1189 | case V4L2_CID_HUE: | |
1190 | cp_write(sd, 0x3d, ctrl->val); | |
1191 | return 0; | |
1192 | case V4L2_CID_DV_RX_RGB_RANGE: | |
1193 | state->rgb_quantization_range = ctrl->val; | |
1194 | set_rgb_quantization_range(sd); | |
1195 | return 0; | |
1196 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: | |
b44b2e06 | 1197 | if (!adv76xx_has_afe(state)) |
d42010a1 | 1198 | return -EINVAL; |
54450f59 HV |
1199 | /* Set the analog sampling phase. This is needed to find the |
1200 | best sampling phase for analog video: an application or | |
1201 | driver has to try a number of phases and analyze the picture | |
1202 | quality before settling on the best performing phase. */ | |
1203 | afe_write(sd, 0xc8, ctrl->val); | |
1204 | return 0; | |
1205 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: | |
1206 | /* Use the default blue color for free running mode, | |
1207 | or supply your own. */ | |
22d97e56 | 1208 | cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); |
54450f59 HV |
1209 | return 0; |
1210 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: | |
1211 | cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); | |
1212 | cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); | |
1213 | cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); | |
1214 | return 0; | |
1215 | } | |
1216 | return -EINVAL; | |
1217 | } | |
1218 | ||
54450f59 HV |
1219 | /* ----------------------------------------------------------------------- */ |
1220 | ||
1221 | static inline bool no_power(struct v4l2_subdev *sd) | |
1222 | { | |
1223 | /* Entire chip or CP powered off */ | |
1224 | return io_read(sd, 0x0c) & 0x24; | |
1225 | } | |
1226 | ||
1227 | static inline bool no_signal_tmds(struct v4l2_subdev *sd) | |
1228 | { | |
b44b2e06 | 1229 | struct adv76xx_state *state = to_state(sd); |
4a31a93a MR |
1230 | |
1231 | return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); | |
54450f59 HV |
1232 | } |
1233 | ||
1234 | static inline bool no_lock_tmds(struct v4l2_subdev *sd) | |
1235 | { | |
b44b2e06 PA |
1236 | struct adv76xx_state *state = to_state(sd); |
1237 | const struct adv76xx_chip_info *info = state->info; | |
d42010a1 LPC |
1238 | |
1239 | return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; | |
54450f59 HV |
1240 | } |
1241 | ||
bb88f325 MB |
1242 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
1243 | { | |
1244 | return hdmi_read(sd, 0x05) & 0x80; | |
1245 | } | |
1246 | ||
54450f59 HV |
1247 | static inline bool no_lock_sspd(struct v4l2_subdev *sd) |
1248 | { | |
b44b2e06 | 1249 | struct adv76xx_state *state = to_state(sd); |
d42010a1 LPC |
1250 | |
1251 | /* | |
1252 | * Chips without a AFE don't expose registers for the SSPD, so just assume | |
1253 | * that we have a lock. | |
1254 | */ | |
b44b2e06 | 1255 | if (adv76xx_has_afe(state)) |
d42010a1 LPC |
1256 | return false; |
1257 | ||
54450f59 HV |
1258 | /* TODO channel 2 */ |
1259 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); | |
1260 | } | |
1261 | ||
1262 | static inline bool no_lock_stdi(struct v4l2_subdev *sd) | |
1263 | { | |
1264 | /* TODO channel 2 */ | |
1265 | return !(cp_read(sd, 0xb1) & 0x80); | |
1266 | } | |
1267 | ||
1268 | static inline bool no_signal(struct v4l2_subdev *sd) | |
1269 | { | |
54450f59 HV |
1270 | bool ret; |
1271 | ||
1272 | ret = no_power(sd); | |
1273 | ||
1274 | ret |= no_lock_stdi(sd); | |
1275 | ret |= no_lock_sspd(sd); | |
1276 | ||
4a31a93a | 1277 | if (is_digital_input(sd)) { |
54450f59 HV |
1278 | ret |= no_lock_tmds(sd); |
1279 | ret |= no_signal_tmds(sd); | |
1280 | } | |
1281 | ||
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | static inline bool no_lock_cp(struct v4l2_subdev *sd) | |
1286 | { | |
b44b2e06 | 1287 | struct adv76xx_state *state = to_state(sd); |
d42010a1 | 1288 | |
b44b2e06 | 1289 | if (!adv76xx_has_afe(state)) |
d42010a1 LPC |
1290 | return false; |
1291 | ||
54450f59 HV |
1292 | /* CP has detected a non standard number of lines on the incoming |
1293 | video compared to what it is configured to receive by s_dv_timings */ | |
1294 | return io_read(sd, 0x12) & 0x01; | |
1295 | } | |
1296 | ||
58514625 | 1297 | static inline bool in_free_run(struct v4l2_subdev *sd) |
1298 | { | |
1299 | return cp_read(sd, 0xff) & 0x10; | |
1300 | } | |
1301 | ||
b44b2e06 | 1302 | static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) |
54450f59 | 1303 | { |
54450f59 HV |
1304 | *status = 0; |
1305 | *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; | |
1306 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; | |
58514625 | 1307 | if (!in_free_run(sd) && no_lock_cp(sd)) |
1308 | *status |= is_digital_input(sd) ? | |
1309 | V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; | |
54450f59 HV |
1310 | |
1311 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | /* ----------------------------------------------------------------------- */ | |
1317 | ||
54450f59 HV |
1318 | struct stdi_readback { |
1319 | u16 bl, lcf, lcvs; | |
1320 | u8 hs_pol, vs_pol; | |
1321 | bool interlaced; | |
1322 | }; | |
1323 | ||
1324 | static int stdi2dv_timings(struct v4l2_subdev *sd, | |
1325 | struct stdi_readback *stdi, | |
1326 | struct v4l2_dv_timings *timings) | |
1327 | { | |
b44b2e06 PA |
1328 | struct adv76xx_state *state = to_state(sd); |
1329 | u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; | |
54450f59 HV |
1330 | u32 pix_clk; |
1331 | int i; | |
1332 | ||
b44b2e06 PA |
1333 | for (i = 0; adv76xx_timings[i].bt.height; i++) { |
1334 | if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1) | |
54450f59 | 1335 | continue; |
b44b2e06 | 1336 | if (adv76xx_timings[i].bt.vsync != stdi->lcvs) |
54450f59 HV |
1337 | continue; |
1338 | ||
b44b2e06 | 1339 | pix_clk = hfreq * htotal(&adv76xx_timings[i].bt); |
54450f59 | 1340 | |
b44b2e06 PA |
1341 | if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) && |
1342 | (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) { | |
1343 | *timings = adv76xx_timings[i]; | |
54450f59 HV |
1344 | return 0; |
1345 | } | |
1346 | } | |
1347 | ||
5fea1bb7 | 1348 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, |
54450f59 HV |
1349 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | |
1350 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
061ddda6 | 1351 | false, timings)) |
54450f59 HV |
1352 | return 0; |
1353 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1354 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1355 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
061ddda6 | 1356 | false, state->aspect_ratio, timings)) |
54450f59 HV |
1357 | return 0; |
1358 | ||
ccbd5bc4 HV |
1359 | v4l2_dbg(2, debug, sd, |
1360 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", | |
1361 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, | |
1362 | stdi->hs_pol, stdi->vs_pol); | |
54450f59 HV |
1363 | return -1; |
1364 | } | |
1365 | ||
d42010a1 | 1366 | |
54450f59 HV |
1367 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) |
1368 | { | |
b44b2e06 PA |
1369 | struct adv76xx_state *state = to_state(sd); |
1370 | const struct adv76xx_chip_info *info = state->info; | |
4a2ccdd2 LP |
1371 | u8 polarity; |
1372 | ||
54450f59 HV |
1373 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { |
1374 | v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); | |
1375 | return -1; | |
1376 | } | |
1377 | ||
1378 | /* read STDI */ | |
51182a94 | 1379 | stdi->bl = cp_read16(sd, 0xb1, 0x3fff); |
d42010a1 | 1380 | stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); |
54450f59 HV |
1381 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; |
1382 | stdi->interlaced = io_read(sd, 0x12) & 0x10; | |
1383 | ||
b44b2e06 | 1384 | if (adv76xx_has_afe(state)) { |
d42010a1 LPC |
1385 | /* read SSPD */ |
1386 | polarity = cp_read(sd, 0xb5); | |
1387 | if ((polarity & 0x03) == 0x01) { | |
1388 | stdi->hs_pol = polarity & 0x10 | |
1389 | ? (polarity & 0x08 ? '+' : '-') : 'x'; | |
1390 | stdi->vs_pol = polarity & 0x40 | |
1391 | ? (polarity & 0x20 ? '+' : '-') : 'x'; | |
1392 | } else { | |
1393 | stdi->hs_pol = 'x'; | |
1394 | stdi->vs_pol = 'x'; | |
1395 | } | |
54450f59 | 1396 | } else { |
d42010a1 LPC |
1397 | polarity = hdmi_read(sd, 0x05); |
1398 | stdi->hs_pol = polarity & 0x20 ? '+' : '-'; | |
1399 | stdi->vs_pol = polarity & 0x10 ? '+' : '-'; | |
54450f59 HV |
1400 | } |
1401 | ||
1402 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1403 | v4l2_dbg(2, debug, sd, | |
1404 | "%s: signal lost during readout of STDI/SSPD\n", __func__); | |
1405 | return -1; | |
1406 | } | |
1407 | ||
1408 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { | |
1409 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); | |
1410 | memset(stdi, 0, sizeof(struct stdi_readback)); | |
1411 | return -1; | |
1412 | } | |
1413 | ||
1414 | v4l2_dbg(2, debug, sd, | |
1415 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", | |
1416 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, | |
1417 | stdi->hs_pol, stdi->vs_pol, | |
1418 | stdi->interlaced ? "interlaced" : "progressive"); | |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | ||
b44b2e06 | 1423 | static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1424 | struct v4l2_enum_dv_timings *timings) |
1425 | { | |
b44b2e06 | 1426 | struct adv76xx_state *state = to_state(sd); |
afec5599 | 1427 | |
b44b2e06 | 1428 | if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1) |
54450f59 | 1429 | return -EINVAL; |
afec5599 LP |
1430 | |
1431 | if (timings->pad >= state->source_pad) | |
1432 | return -EINVAL; | |
1433 | ||
54450f59 | 1434 | memset(timings->reserved, 0, sizeof(timings->reserved)); |
b44b2e06 | 1435 | timings->timings = adv76xx_timings[timings->index]; |
54450f59 HV |
1436 | return 0; |
1437 | } | |
1438 | ||
b44b2e06 | 1439 | static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, |
7515e096 | 1440 | struct v4l2_dv_timings_cap *cap) |
54450f59 | 1441 | { |
b44b2e06 | 1442 | struct adv76xx_state *state = to_state(sd); |
7515e096 LP |
1443 | |
1444 | if (cap->pad >= state->source_pad) | |
1445 | return -EINVAL; | |
1446 | ||
54450f59 HV |
1447 | cap->type = V4L2_DV_BT_656_1120; |
1448 | cap->bt.max_width = 1920; | |
1449 | cap->bt.max_height = 1200; | |
fe9c2564 | 1450 | cap->bt.min_pixelclock = 25000000; |
afec5599 | 1451 | |
7515e096 | 1452 | switch (cap->pad) { |
b44b2e06 | 1453 | case ADV76XX_PAD_HDMI_PORT_A: |
afec5599 LP |
1454 | case ADV7604_PAD_HDMI_PORT_B: |
1455 | case ADV7604_PAD_HDMI_PORT_C: | |
1456 | case ADV7604_PAD_HDMI_PORT_D: | |
54450f59 | 1457 | cap->bt.max_pixelclock = 225000000; |
afec5599 LP |
1458 | break; |
1459 | case ADV7604_PAD_VGA_RGB: | |
1460 | case ADV7604_PAD_VGA_COMP: | |
1461 | default: | |
54450f59 | 1462 | cap->bt.max_pixelclock = 170000000; |
afec5599 LP |
1463 | break; |
1464 | } | |
1465 | ||
54450f59 HV |
1466 | cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
1467 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; | |
1468 | cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | | |
1469 | V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; | |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings | |
b44b2e06 PA |
1474 | if the format is listed in adv76xx_timings[] */ |
1475 | static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, | |
54450f59 HV |
1476 | struct v4l2_dv_timings *timings) |
1477 | { | |
54450f59 HV |
1478 | int i; |
1479 | ||
b44b2e06 PA |
1480 | for (i = 0; adv76xx_timings[i].bt.width; i++) { |
1481 | if (v4l2_match_dv_timings(timings, &adv76xx_timings[i], | |
85f9e06c | 1482 | is_digital_input(sd) ? 250000 : 1000000, false)) { |
b44b2e06 | 1483 | *timings = adv76xx_timings[i]; |
54450f59 HV |
1484 | break; |
1485 | } | |
1486 | } | |
1487 | } | |
1488 | ||
d42010a1 LPC |
1489 | static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) |
1490 | { | |
1491 | unsigned int freq; | |
1492 | int a, b; | |
1493 | ||
1494 | a = hdmi_read(sd, 0x06); | |
1495 | b = hdmi_read(sd, 0x3b); | |
1496 | if (a < 0 || b < 0) | |
1497 | return 0; | |
1498 | freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; | |
1499 | ||
1500 | if (is_hdmi(sd)) { | |
1501 | /* adjust for deep color mode */ | |
1502 | unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; | |
1503 | ||
1504 | freq = freq * 8 / bits_per_channel; | |
1505 | } | |
1506 | ||
1507 | return freq; | |
1508 | } | |
1509 | ||
1510 | static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) | |
1511 | { | |
1512 | int a, b; | |
1513 | ||
1514 | a = hdmi_read(sd, 0x51); | |
1515 | b = hdmi_read(sd, 0x52); | |
1516 | if (a < 0 || b < 0) | |
1517 | return 0; | |
1518 | return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; | |
1519 | } | |
1520 | ||
b44b2e06 | 1521 | static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1522 | struct v4l2_dv_timings *timings) |
1523 | { | |
b44b2e06 PA |
1524 | struct adv76xx_state *state = to_state(sd); |
1525 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 HV |
1526 | struct v4l2_bt_timings *bt = &timings->bt; |
1527 | struct stdi_readback stdi; | |
1528 | ||
1529 | if (!timings) | |
1530 | return -EINVAL; | |
1531 | ||
1532 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1533 | ||
1534 | if (no_signal(sd)) { | |
1e0b9156 | 1535 | state->restart_stdi_once = true; |
54450f59 HV |
1536 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); |
1537 | return -ENOLINK; | |
1538 | } | |
1539 | ||
1540 | /* read STDI */ | |
1541 | if (read_stdi(sd, &stdi)) { | |
1542 | v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); | |
1543 | return -ENOLINK; | |
1544 | } | |
1545 | bt->interlaced = stdi.interlaced ? | |
1546 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; | |
1547 | ||
4a31a93a | 1548 | if (is_digital_input(sd)) { |
54450f59 HV |
1549 | timings->type = V4L2_DV_BT_656_1120; |
1550 | ||
5380baaf | 1551 | bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask); |
1552 | bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask); | |
d42010a1 | 1553 | bt->pixelclock = info->read_hdmi_pixelclock(sd); |
5380baaf | 1554 | bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); |
1555 | bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); | |
1556 | bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); | |
1557 | bt->vfrontporch = hdmi_read16(sd, 0x2a, | |
1558 | info->field0_vfrontporch_mask) / 2; | |
1559 | bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; | |
1560 | bt->vbackporch = hdmi_read16(sd, 0x32, | |
1561 | info->field0_vbackporch_mask) / 2; | |
54450f59 HV |
1562 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | |
1563 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); | |
1564 | if (bt->interlaced == V4L2_DV_INTERLACED) { | |
5380baaf | 1565 | bt->height += hdmi_read16(sd, 0x0b, |
1566 | info->field1_height_mask); | |
1567 | bt->il_vfrontporch = hdmi_read16(sd, 0x2c, | |
1568 | info->field1_vfrontporch_mask) / 2; | |
1569 | bt->il_vsync = hdmi_read16(sd, 0x30, | |
1570 | info->field1_vsync_mask) / 2; | |
1571 | bt->il_vbackporch = hdmi_read16(sd, 0x34, | |
1572 | info->field1_vbackporch_mask) / 2; | |
54450f59 | 1573 | } |
b44b2e06 | 1574 | adv76xx_fill_optional_dv_timings_fields(sd, timings); |
54450f59 HV |
1575 | } else { |
1576 | /* find format | |
80939647 | 1577 | * Since LCVS values are inaccurate [REF_03, p. 275-276], |
54450f59 HV |
1578 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. |
1579 | */ | |
1580 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1581 | goto found; | |
1582 | stdi.lcvs += 1; | |
1583 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); | |
1584 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1585 | goto found; | |
1586 | stdi.lcvs -= 2; | |
1587 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); | |
1588 | if (stdi2dv_timings(sd, &stdi, timings)) { | |
cf9afb1d HV |
1589 | /* |
1590 | * The STDI block may measure wrong values, especially | |
1591 | * for lcvs and lcf. If the driver can not find any | |
1592 | * valid timing, the STDI block is restarted to measure | |
1593 | * the video timings again. The function will return an | |
1594 | * error, but the restart of STDI will generate a new | |
1595 | * STDI interrupt and the format detection process will | |
1596 | * restart. | |
1597 | */ | |
1598 | if (state->restart_stdi_once) { | |
1599 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); | |
1600 | /* TODO restart STDI for Sync Channel 2 */ | |
1601 | /* enter one-shot mode */ | |
22d97e56 | 1602 | cp_write_clr_set(sd, 0x86, 0x06, 0x00); |
cf9afb1d | 1603 | /* trigger STDI restart */ |
22d97e56 | 1604 | cp_write_clr_set(sd, 0x86, 0x06, 0x04); |
cf9afb1d | 1605 | /* reset to continuous mode */ |
22d97e56 | 1606 | cp_write_clr_set(sd, 0x86, 0x06, 0x02); |
cf9afb1d HV |
1607 | state->restart_stdi_once = false; |
1608 | return -ENOLINK; | |
1609 | } | |
54450f59 HV |
1610 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); |
1611 | return -ERANGE; | |
1612 | } | |
cf9afb1d | 1613 | state->restart_stdi_once = true; |
54450f59 HV |
1614 | } |
1615 | found: | |
1616 | ||
1617 | if (no_signal(sd)) { | |
1618 | v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); | |
1619 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1620 | return -ENOLINK; | |
1621 | } | |
1622 | ||
4a31a93a MR |
1623 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1624 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1625 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1626 | __func__, (u32)bt->pixelclock); | |
1627 | return -ERANGE; | |
1628 | } | |
1629 | ||
1630 | if (debug > 1) | |
b44b2e06 | 1631 | v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", |
11d034c8 | 1632 | timings, true); |
54450f59 HV |
1633 | |
1634 | return 0; | |
1635 | } | |
1636 | ||
b44b2e06 | 1637 | static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1638 | struct v4l2_dv_timings *timings) |
1639 | { | |
b44b2e06 | 1640 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 1641 | struct v4l2_bt_timings *bt; |
ccbd5bc4 | 1642 | int err; |
54450f59 HV |
1643 | |
1644 | if (!timings) | |
1645 | return -EINVAL; | |
1646 | ||
85f9e06c | 1647 | if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { |
d48eb48c MR |
1648 | v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); |
1649 | return 0; | |
1650 | } | |
1651 | ||
54450f59 HV |
1652 | bt = &timings->bt; |
1653 | ||
4a31a93a MR |
1654 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1655 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1656 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1657 | __func__, (u32)bt->pixelclock); | |
1658 | return -ERANGE; | |
1659 | } | |
ccbd5bc4 | 1660 | |
b44b2e06 | 1661 | adv76xx_fill_optional_dv_timings_fields(sd, timings); |
54450f59 HV |
1662 | |
1663 | state->timings = *timings; | |
1664 | ||
22d97e56 | 1665 | cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); |
ccbd5bc4 HV |
1666 | |
1667 | /* Use prim_mode and vid_std when available */ | |
1668 | err = configure_predefined_video_timings(sd, timings); | |
1669 | if (err) { | |
1670 | /* custom settings when the video format | |
1671 | does not have prim_mode/vid_std */ | |
1672 | configure_custom_video_timings(sd, bt); | |
1673 | } | |
54450f59 HV |
1674 | |
1675 | set_rgb_quantization_range(sd); | |
1676 | ||
54450f59 | 1677 | if (debug > 1) |
b44b2e06 | 1678 | v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", |
11d034c8 | 1679 | timings, true); |
54450f59 HV |
1680 | return 0; |
1681 | } | |
1682 | ||
b44b2e06 | 1683 | static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, |
54450f59 HV |
1684 | struct v4l2_dv_timings *timings) |
1685 | { | |
b44b2e06 | 1686 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
1687 | |
1688 | *timings = state->timings; | |
1689 | return 0; | |
1690 | } | |
1691 | ||
d42010a1 LPC |
1692 | static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) |
1693 | { | |
1694 | hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); | |
1695 | } | |
1696 | ||
1697 | static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) | |
1698 | { | |
1699 | hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); | |
1700 | } | |
1701 | ||
6b0d5d34 | 1702 | static void enable_input(struct v4l2_subdev *sd) |
54450f59 | 1703 | { |
b44b2e06 | 1704 | struct adv76xx_state *state = to_state(sd); |
6b0d5d34 | 1705 | |
4a31a93a | 1706 | if (is_analog_input(sd)) { |
54450f59 | 1707 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ |
4a31a93a | 1708 | } else if (is_digital_input(sd)) { |
22d97e56 | 1709 | hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); |
d42010a1 | 1710 | state->info->set_termination(sd, true); |
54450f59 | 1711 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ |
22d97e56 | 1712 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ |
4a31a93a MR |
1713 | } else { |
1714 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1715 | __func__, state->selected_input); | |
54450f59 HV |
1716 | } |
1717 | } | |
1718 | ||
1719 | static void disable_input(struct v4l2_subdev *sd) | |
1720 | { | |
b44b2e06 | 1721 | struct adv76xx_state *state = to_state(sd); |
d42010a1 | 1722 | |
22d97e56 | 1723 | hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ |
5474b983 | 1724 | msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ |
54450f59 | 1725 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ |
d42010a1 | 1726 | state->info->set_termination(sd, false); |
54450f59 HV |
1727 | } |
1728 | ||
6b0d5d34 | 1729 | static void select_input(struct v4l2_subdev *sd) |
54450f59 | 1730 | { |
b44b2e06 PA |
1731 | struct adv76xx_state *state = to_state(sd); |
1732 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 | 1733 | |
4a31a93a | 1734 | if (is_analog_input(sd)) { |
b44b2e06 | 1735 | adv76xx_write_reg_seq(sd, info->recommended_settings[0]); |
54450f59 HV |
1736 | |
1737 | afe_write(sd, 0x00, 0x08); /* power up ADC */ | |
1738 | afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ | |
1739 | afe_write(sd, 0xc8, 0x00); /* phase control */ | |
4a31a93a MR |
1740 | } else if (is_digital_input(sd)) { |
1741 | hdmi_write(sd, 0x00, state->selected_input & 0x03); | |
54450f59 | 1742 | |
b44b2e06 | 1743 | adv76xx_write_reg_seq(sd, info->recommended_settings[1]); |
d42010a1 | 1744 | |
b44b2e06 | 1745 | if (adv76xx_has_afe(state)) { |
d42010a1 LPC |
1746 | afe_write(sd, 0x00, 0xff); /* power down ADC */ |
1747 | afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ | |
1748 | afe_write(sd, 0xc8, 0x40); /* phase control */ | |
1749 | } | |
1750 | ||
54450f59 HV |
1751 | cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ |
1752 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1753 | cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ | |
4a31a93a MR |
1754 | } else { |
1755 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1756 | __func__, state->selected_input); | |
54450f59 HV |
1757 | } |
1758 | } | |
1759 | ||
b44b2e06 | 1760 | static int adv76xx_s_routing(struct v4l2_subdev *sd, |
54450f59 HV |
1761 | u32 input, u32 output, u32 config) |
1762 | { | |
b44b2e06 | 1763 | struct adv76xx_state *state = to_state(sd); |
54450f59 | 1764 | |
ff4f80fd MR |
1765 | v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", |
1766 | __func__, input, state->selected_input); | |
1767 | ||
1768 | if (input == state->selected_input) | |
1769 | return 0; | |
54450f59 | 1770 | |
d42010a1 LPC |
1771 | if (input > state->info->max_port) |
1772 | return -EINVAL; | |
1773 | ||
4a31a93a | 1774 | state->selected_input = input; |
54450f59 HV |
1775 | |
1776 | disable_input(sd); | |
6b0d5d34 | 1777 | select_input(sd); |
6b0d5d34 | 1778 | enable_input(sd); |
54450f59 | 1779 | |
6f5bcfc3 LPC |
1780 | v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); |
1781 | ||
54450f59 HV |
1782 | return 0; |
1783 | } | |
1784 | ||
b44b2e06 | 1785 | static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, |
f7234138 | 1786 | struct v4l2_subdev_pad_config *cfg, |
539b33b0 | 1787 | struct v4l2_subdev_mbus_code_enum *code) |
54450f59 | 1788 | { |
b44b2e06 | 1789 | struct adv76xx_state *state = to_state(sd); |
539b33b0 LP |
1790 | |
1791 | if (code->index >= state->info->nformats) | |
54450f59 | 1792 | return -EINVAL; |
539b33b0 LP |
1793 | |
1794 | code->code = state->info->formats[code->index].code; | |
1795 | ||
54450f59 HV |
1796 | return 0; |
1797 | } | |
1798 | ||
b44b2e06 | 1799 | static void adv76xx_fill_format(struct adv76xx_state *state, |
539b33b0 | 1800 | struct v4l2_mbus_framefmt *format) |
54450f59 | 1801 | { |
539b33b0 | 1802 | memset(format, 0, sizeof(*format)); |
54450f59 | 1803 | |
539b33b0 LP |
1804 | format->width = state->timings.bt.width; |
1805 | format->height = state->timings.bt.height; | |
1806 | format->field = V4L2_FIELD_NONE; | |
680fee04 | 1807 | format->colorspace = V4L2_COLORSPACE_SRGB; |
539b33b0 | 1808 | |
680fee04 | 1809 | if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) |
539b33b0 | 1810 | format->colorspace = (state->timings.bt.height <= 576) ? |
54450f59 | 1811 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; |
539b33b0 LP |
1812 | } |
1813 | ||
1814 | /* | |
1815 | * Compute the op_ch_sel value required to obtain on the bus the component order | |
1816 | * corresponding to the selected format taking into account bus reordering | |
1817 | * applied by the board at the output of the device. | |
1818 | * | |
1819 | * The following table gives the op_ch_value from the format component order | |
1820 | * (expressed as op_ch_sel value in column) and the bus reordering (expressed as | |
b44b2e06 | 1821 | * adv76xx_bus_order value in row). |
539b33b0 LP |
1822 | * |
1823 | * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) | |
1824 | * ----------+------------------------------------------------- | |
1825 | * RGB (NOP) | GBR GRB BGR RGB BRG RBG | |
1826 | * GRB (1-2) | BGR RGB GBR GRB RBG BRG | |
1827 | * RBG (2-3) | GRB GBR BRG RBG BGR RGB | |
1828 | * BGR (1-3) | RBG BRG RGB BGR GRB GBR | |
1829 | * BRG (ROR) | BRG RBG GRB GBR RGB BGR | |
1830 | * GBR (ROL) | RGB BGR RBG BRG GBR GRB | |
1831 | */ | |
b44b2e06 | 1832 | static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) |
539b33b0 LP |
1833 | { |
1834 | #define _SEL(a,b,c,d,e,f) { \ | |
b44b2e06 PA |
1835 | ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ |
1836 | ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } | |
539b33b0 LP |
1837 | #define _BUS(x) [ADV7604_BUS_ORDER_##x] |
1838 | ||
1839 | static const unsigned int op_ch_sel[6][6] = { | |
1840 | _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), | |
1841 | _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), | |
1842 | _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), | |
1843 | _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), | |
1844 | _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), | |
1845 | _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), | |
1846 | }; | |
1847 | ||
1848 | return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; | |
1849 | } | |
1850 | ||
b44b2e06 | 1851 | static void adv76xx_setup_format(struct adv76xx_state *state) |
539b33b0 LP |
1852 | { |
1853 | struct v4l2_subdev *sd = &state->sd; | |
1854 | ||
22d97e56 | 1855 | io_write_clr_set(sd, 0x02, 0x02, |
b44b2e06 | 1856 | state->format->rgb_out ? ADV76XX_RGB_OUT : 0); |
539b33b0 LP |
1857 | io_write(sd, 0x03, state->format->op_format_sel | |
1858 | state->pdata.op_format_mode_sel); | |
b44b2e06 | 1859 | io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); |
22d97e56 | 1860 | io_write_clr_set(sd, 0x05, 0x01, |
b44b2e06 | 1861 | state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); |
539b33b0 LP |
1862 | } |
1863 | ||
f7234138 HV |
1864 | static int adv76xx_get_format(struct v4l2_subdev *sd, |
1865 | struct v4l2_subdev_pad_config *cfg, | |
539b33b0 LP |
1866 | struct v4l2_subdev_format *format) |
1867 | { | |
b44b2e06 | 1868 | struct adv76xx_state *state = to_state(sd); |
539b33b0 LP |
1869 | |
1870 | if (format->pad != state->source_pad) | |
1871 | return -EINVAL; | |
1872 | ||
b44b2e06 | 1873 | adv76xx_fill_format(state, &format->format); |
539b33b0 LP |
1874 | |
1875 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1876 | struct v4l2_mbus_framefmt *fmt; | |
1877 | ||
f7234138 | 1878 | fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); |
539b33b0 LP |
1879 | format->format.code = fmt->code; |
1880 | } else { | |
1881 | format->format.code = state->format->code; | |
54450f59 | 1882 | } |
539b33b0 LP |
1883 | |
1884 | return 0; | |
1885 | } | |
1886 | ||
b7d4d2f8 UH |
1887 | static int adv76xx_get_selection(struct v4l2_subdev *sd, |
1888 | struct v4l2_subdev_pad_config *cfg, | |
1889 | struct v4l2_subdev_selection *sel) | |
1890 | { | |
1891 | struct adv76xx_state *state = to_state(sd); | |
1892 | ||
1893 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) | |
1894 | return -EINVAL; | |
1895 | /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ | |
1896 | if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) | |
1897 | return -EINVAL; | |
1898 | ||
1899 | sel->r.left = 0; | |
1900 | sel->r.top = 0; | |
1901 | sel->r.width = state->timings.bt.width; | |
1902 | sel->r.height = state->timings.bt.height; | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | ||
f7234138 HV |
1907 | static int adv76xx_set_format(struct v4l2_subdev *sd, |
1908 | struct v4l2_subdev_pad_config *cfg, | |
539b33b0 LP |
1909 | struct v4l2_subdev_format *format) |
1910 | { | |
b44b2e06 PA |
1911 | struct adv76xx_state *state = to_state(sd); |
1912 | const struct adv76xx_format_info *info; | |
539b33b0 LP |
1913 | |
1914 | if (format->pad != state->source_pad) | |
1915 | return -EINVAL; | |
1916 | ||
b44b2e06 | 1917 | info = adv76xx_format_info(state, format->format.code); |
539b33b0 | 1918 | if (info == NULL) |
b44b2e06 | 1919 | info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); |
539b33b0 | 1920 | |
b44b2e06 | 1921 | adv76xx_fill_format(state, &format->format); |
539b33b0 LP |
1922 | format->format.code = info->code; |
1923 | ||
1924 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1925 | struct v4l2_mbus_framefmt *fmt; | |
1926 | ||
f7234138 | 1927 | fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); |
539b33b0 LP |
1928 | fmt->code = format->format.code; |
1929 | } else { | |
1930 | state->format = info; | |
b44b2e06 | 1931 | adv76xx_setup_format(state); |
539b33b0 LP |
1932 | } |
1933 | ||
54450f59 HV |
1934 | return 0; |
1935 | } | |
1936 | ||
b44b2e06 | 1937 | static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) |
54450f59 | 1938 | { |
b44b2e06 PA |
1939 | struct adv76xx_state *state = to_state(sd); |
1940 | const struct adv76xx_chip_info *info = state->info; | |
f24d229c MR |
1941 | const u8 irq_reg_0x43 = io_read(sd, 0x43); |
1942 | const u8 irq_reg_0x6b = io_read(sd, 0x6b); | |
1943 | const u8 irq_reg_0x70 = io_read(sd, 0x70); | |
1944 | u8 fmt_change_digital; | |
1945 | u8 fmt_change; | |
1946 | u8 tx_5v; | |
1947 | ||
1948 | if (irq_reg_0x43) | |
1949 | io_write(sd, 0x44, irq_reg_0x43); | |
1950 | if (irq_reg_0x70) | |
1951 | io_write(sd, 0x71, irq_reg_0x70); | |
1952 | if (irq_reg_0x6b) | |
1953 | io_write(sd, 0x6c, irq_reg_0x6b); | |
54450f59 | 1954 | |
ff4f80fd MR |
1955 | v4l2_dbg(2, debug, sd, "%s: ", __func__); |
1956 | ||
54450f59 | 1957 | /* format change */ |
f24d229c | 1958 | fmt_change = irq_reg_0x43 & 0x98; |
d42010a1 LPC |
1959 | fmt_change_digital = is_digital_input(sd) |
1960 | ? irq_reg_0x6b & info->fmt_change_digital_mask | |
1961 | : 0; | |
14d03233 | 1962 | |
54450f59 HV |
1963 | if (fmt_change || fmt_change_digital) { |
1964 | v4l2_dbg(1, debug, sd, | |
25a64ac9 | 1965 | "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", |
54450f59 | 1966 | __func__, fmt_change, fmt_change_digital); |
25a64ac9 | 1967 | |
6f5bcfc3 | 1968 | v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); |
25a64ac9 | 1969 | |
54450f59 HV |
1970 | if (handled) |
1971 | *handled = true; | |
1972 | } | |
f24d229c MR |
1973 | /* HDMI/DVI mode */ |
1974 | if (irq_reg_0x6b & 0x01) { | |
1975 | v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, | |
1976 | (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); | |
1977 | set_rgb_quantization_range(sd); | |
1978 | if (handled) | |
1979 | *handled = true; | |
1980 | } | |
1981 | ||
54450f59 | 1982 | /* tx 5v detect */ |
d42010a1 | 1983 | tx_5v = io_read(sd, 0x70) & info->cable_det_mask; |
54450f59 HV |
1984 | if (tx_5v) { |
1985 | v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); | |
1986 | io_write(sd, 0x71, tx_5v); | |
b44b2e06 | 1987 | adv76xx_s_detect_tx_5v_ctrl(sd); |
54450f59 HV |
1988 | if (handled) |
1989 | *handled = true; | |
1990 | } | |
1991 | return 0; | |
1992 | } | |
1993 | ||
b44b2e06 | 1994 | static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 | 1995 | { |
b44b2e06 | 1996 | struct adv76xx_state *state = to_state(sd); |
4a31a93a | 1997 | u8 *data = NULL; |
54450f59 | 1998 | |
dd9ac11a | 1999 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
4a31a93a MR |
2000 | |
2001 | switch (edid->pad) { | |
b44b2e06 | 2002 | case ADV76XX_PAD_HDMI_PORT_A: |
c784b1e2 LP |
2003 | case ADV7604_PAD_HDMI_PORT_B: |
2004 | case ADV7604_PAD_HDMI_PORT_C: | |
2005 | case ADV7604_PAD_HDMI_PORT_D: | |
4a31a93a MR |
2006 | if (state->edid.present & (1 << edid->pad)) |
2007 | data = state->edid.edid; | |
2008 | break; | |
2009 | default: | |
2010 | return -EINVAL; | |
4a31a93a | 2011 | } |
dd9ac11a HV |
2012 | |
2013 | if (edid->start_block == 0 && edid->blocks == 0) { | |
2014 | edid->blocks = data ? state->edid.blocks : 0; | |
2015 | return 0; | |
2016 | } | |
2017 | ||
2018 | if (data == NULL) | |
4a31a93a MR |
2019 | return -ENODATA; |
2020 | ||
dd9ac11a HV |
2021 | if (edid->start_block >= state->edid.blocks) |
2022 | return -EINVAL; | |
2023 | ||
2024 | if (edid->start_block + edid->blocks > state->edid.blocks) | |
2025 | edid->blocks = state->edid.blocks - edid->start_block; | |
2026 | ||
2027 | memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); | |
2028 | ||
54450f59 HV |
2029 | return 0; |
2030 | } | |
2031 | ||
dd08beb9 | 2032 | static int get_edid_spa_location(const u8 *edid) |
3e86aa85 MR |
2033 | { |
2034 | u8 d; | |
2035 | ||
2036 | if ((edid[0x7e] != 1) || | |
2037 | (edid[0x80] != 0x02) || | |
2038 | (edid[0x81] != 0x03)) { | |
2039 | return -1; | |
2040 | } | |
2041 | ||
2042 | /* search Vendor Specific Data Block (tag 3) */ | |
2043 | d = edid[0x82] & 0x7f; | |
2044 | if (d > 4) { | |
2045 | int i = 0x84; | |
2046 | int end = 0x80 + d; | |
2047 | ||
2048 | do { | |
2049 | u8 tag = edid[i] >> 5; | |
2050 | u8 len = edid[i] & 0x1f; | |
2051 | ||
2052 | if ((tag == 3) && (len >= 5)) | |
2053 | return i + 4; | |
2054 | i += len + 1; | |
2055 | } while (i < end); | |
2056 | } | |
2057 | return -1; | |
2058 | } | |
2059 | ||
b44b2e06 | 2060 | static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 | 2061 | { |
b44b2e06 PA |
2062 | struct adv76xx_state *state = to_state(sd); |
2063 | const struct adv76xx_chip_info *info = state->info; | |
dd08beb9 | 2064 | int spa_loc; |
54450f59 | 2065 | int err; |
dd08beb9 | 2066 | int i; |
54450f59 | 2067 | |
dd9ac11a HV |
2068 | memset(edid->reserved, 0, sizeof(edid->reserved)); |
2069 | ||
c784b1e2 | 2070 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) |
54450f59 HV |
2071 | return -EINVAL; |
2072 | if (edid->start_block != 0) | |
2073 | return -EINVAL; | |
2074 | if (edid->blocks == 0) { | |
3e86aa85 | 2075 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a | 2076 | state->edid.present &= ~(1 << edid->pad); |
b44b2e06 | 2077 | adv76xx_set_hpd(state, state->edid.present); |
22d97e56 | 2078 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); |
3e86aa85 | 2079 | |
54450f59 HV |
2080 | /* Fall back to a 16:9 aspect ratio */ |
2081 | state->aspect_ratio.numerator = 16; | |
2082 | state->aspect_ratio.denominator = 9; | |
3e86aa85 MR |
2083 | |
2084 | if (!state->edid.present) | |
2085 | state->edid.blocks = 0; | |
2086 | ||
2087 | v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", | |
2088 | __func__, edid->pad, state->edid.present); | |
54450f59 HV |
2089 | return 0; |
2090 | } | |
4a31a93a MR |
2091 | if (edid->blocks > 2) { |
2092 | edid->blocks = 2; | |
54450f59 | 2093 | return -E2BIG; |
4a31a93a | 2094 | } |
4a31a93a | 2095 | |
dd08beb9 MR |
2096 | v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", |
2097 | __func__, edid->pad, state->edid.present); | |
2098 | ||
3e86aa85 | 2099 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a | 2100 | cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); |
b44b2e06 | 2101 | adv76xx_set_hpd(state, 0); |
22d97e56 | 2102 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); |
3e86aa85 | 2103 | |
dd08beb9 MR |
2104 | spa_loc = get_edid_spa_location(edid->edid); |
2105 | if (spa_loc < 0) | |
2106 | spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ | |
2107 | ||
3e86aa85 | 2108 | switch (edid->pad) { |
b44b2e06 | 2109 | case ADV76XX_PAD_HDMI_PORT_A: |
dd08beb9 MR |
2110 | state->spa_port_a[0] = edid->edid[spa_loc]; |
2111 | state->spa_port_a[1] = edid->edid[spa_loc + 1]; | |
3e86aa85 | 2112 | break; |
c784b1e2 | 2113 | case ADV7604_PAD_HDMI_PORT_B: |
dd08beb9 MR |
2114 | rep_write(sd, 0x70, edid->edid[spa_loc]); |
2115 | rep_write(sd, 0x71, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2116 | break; |
c784b1e2 | 2117 | case ADV7604_PAD_HDMI_PORT_C: |
dd08beb9 MR |
2118 | rep_write(sd, 0x72, edid->edid[spa_loc]); |
2119 | rep_write(sd, 0x73, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2120 | break; |
c784b1e2 | 2121 | case ADV7604_PAD_HDMI_PORT_D: |
dd08beb9 MR |
2122 | rep_write(sd, 0x74, edid->edid[spa_loc]); |
2123 | rep_write(sd, 0x75, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2124 | break; |
dd08beb9 MR |
2125 | default: |
2126 | return -EINVAL; | |
3e86aa85 | 2127 | } |
d42010a1 LPC |
2128 | |
2129 | if (info->type == ADV7604) { | |
2130 | rep_write(sd, 0x76, spa_loc & 0xff); | |
22d97e56 | 2131 | rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); |
d42010a1 LPC |
2132 | } else { |
2133 | /* FIXME: Where is the SPA location LSB register ? */ | |
22d97e56 | 2134 | rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); |
d42010a1 | 2135 | } |
3e86aa85 | 2136 | |
dd08beb9 MR |
2137 | edid->edid[spa_loc] = state->spa_port_a[0]; |
2138 | edid->edid[spa_loc + 1] = state->spa_port_a[1]; | |
4a31a93a MR |
2139 | |
2140 | memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); | |
2141 | state->edid.blocks = edid->blocks; | |
54450f59 HV |
2142 | state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], |
2143 | edid->edid[0x16]); | |
3e86aa85 | 2144 | state->edid.present |= 1 << edid->pad; |
4a31a93a MR |
2145 | |
2146 | err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); | |
2147 | if (err < 0) { | |
3e86aa85 | 2148 | v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); |
4a31a93a MR |
2149 | return err; |
2150 | } | |
2151 | ||
b44b2e06 | 2152 | /* adv76xx calculates the checksums and enables I2C access to internal |
dd08beb9 | 2153 | EDID RAM from DDC port. */ |
22d97e56 | 2154 | rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); |
dd08beb9 MR |
2155 | |
2156 | for (i = 0; i < 1000; i++) { | |
d42010a1 | 2157 | if (rep_read(sd, info->edid_status_reg) & state->edid.present) |
dd08beb9 MR |
2158 | break; |
2159 | mdelay(1); | |
2160 | } | |
2161 | if (i == 1000) { | |
2162 | v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); | |
2163 | return -EIO; | |
2164 | } | |
2165 | ||
4a31a93a MR |
2166 | /* enable hotplug after 100 ms */ |
2167 | queue_delayed_work(state->work_queues, | |
2168 | &state->delayed_work_enable_hotplug, HZ / 10); | |
2169 | return 0; | |
54450f59 HV |
2170 | } |
2171 | ||
2172 | /*********** avi info frame CEA-861-E **************/ | |
2173 | ||
516613c1 HV |
2174 | static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { |
2175 | { "AVI", 0x01, 0xe0, 0x00 }, | |
2176 | { "Audio", 0x02, 0xe3, 0x1c }, | |
2177 | { "SDP", 0x04, 0xe6, 0x2a }, | |
2178 | { "Vendor", 0x10, 0xec, 0x54 } | |
2179 | }; | |
2180 | ||
2181 | static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, | |
2182 | union hdmi_infoframe *frame) | |
54450f59 | 2183 | { |
516613c1 HV |
2184 | uint8_t buffer[32]; |
2185 | u8 len; | |
54450f59 | 2186 | int i; |
54450f59 | 2187 | |
516613c1 HV |
2188 | if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { |
2189 | v4l2_info(sd, "%s infoframe not received\n", | |
2190 | adv76xx_cri[index].desc); | |
2191 | return -ENOENT; | |
54450f59 | 2192 | } |
516613c1 HV |
2193 | |
2194 | for (i = 0; i < 3; i++) | |
2195 | buffer[i] = infoframe_read(sd, | |
2196 | adv76xx_cri[index].head_addr + i); | |
2197 | ||
2198 | len = buffer[2] + 1; | |
2199 | ||
2200 | if (len + 3 > sizeof(buffer)) { | |
2201 | v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, | |
2202 | adv76xx_cri[index].desc, len); | |
2203 | return -ENOENT; | |
54450f59 HV |
2204 | } |
2205 | ||
516613c1 HV |
2206 | for (i = 0; i < len; i++) |
2207 | buffer[i + 3] = infoframe_read(sd, | |
2208 | adv76xx_cri[index].payload_addr + i); | |
2209 | ||
2210 | if (hdmi_infoframe_unpack(frame, buffer) < 0) { | |
2211 | v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, | |
2212 | adv76xx_cri[index].desc); | |
2213 | return -ENOENT; | |
54450f59 | 2214 | } |
516613c1 HV |
2215 | return 0; |
2216 | } | |
54450f59 | 2217 | |
516613c1 HV |
2218 | static void adv76xx_log_infoframes(struct v4l2_subdev *sd) |
2219 | { | |
2220 | int i; | |
54450f59 | 2221 | |
516613c1 HV |
2222 | if (!is_hdmi(sd)) { |
2223 | v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); | |
54450f59 | 2224 | return; |
516613c1 | 2225 | } |
54450f59 | 2226 | |
516613c1 HV |
2227 | for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { |
2228 | union hdmi_infoframe frame; | |
2229 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
54450f59 | 2230 | |
516613c1 HV |
2231 | if (adv76xx_read_infoframe(sd, i, &frame)) |
2232 | return; | |
2233 | hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); | |
2234 | } | |
54450f59 HV |
2235 | } |
2236 | ||
b44b2e06 | 2237 | static int adv76xx_log_status(struct v4l2_subdev *sd) |
54450f59 | 2238 | { |
b44b2e06 PA |
2239 | struct adv76xx_state *state = to_state(sd); |
2240 | const struct adv76xx_chip_info *info = state->info; | |
54450f59 HV |
2241 | struct v4l2_dv_timings timings; |
2242 | struct stdi_readback stdi; | |
2243 | u8 reg_io_0x02 = io_read(sd, 0x02); | |
4a2ccdd2 LP |
2244 | u8 edid_enabled; |
2245 | u8 cable_det; | |
54450f59 | 2246 | |
f216ccb3 | 2247 | static const char * const csc_coeff_sel_rb[16] = { |
54450f59 HV |
2248 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", |
2249 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", | |
2250 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", | |
2251 | "reserved", "reserved", "reserved", "reserved", "manual" | |
2252 | }; | |
f216ccb3 | 2253 | static const char * const input_color_space_txt[16] = { |
54450f59 HV |
2254 | "RGB limited range (16-235)", "RGB full range (0-255)", |
2255 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
9833239e | 2256 | "xvYCC Bt.601", "xvYCC Bt.709", |
54450f59 HV |
2257 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", |
2258 | "invalid", "invalid", "invalid", "invalid", "invalid", | |
2259 | "invalid", "invalid", "automatic" | |
2260 | }; | |
7a5d99e7 HV |
2261 | static const char * const hdmi_color_space_txt[16] = { |
2262 | "RGB limited range (16-235)", "RGB full range (0-255)", | |
2263 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
2264 | "xvYCC Bt.601", "xvYCC Bt.709", | |
2265 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", | |
2266 | "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid", | |
2267 | "invalid", "invalid", "invalid" | |
2268 | }; | |
f216ccb3 | 2269 | static const char * const rgb_quantization_range_txt[] = { |
54450f59 HV |
2270 | "Automatic", |
2271 | "RGB limited range (16-235)", | |
2272 | "RGB full range (0-255)", | |
2273 | }; | |
f216ccb3 | 2274 | static const char * const deep_color_mode_txt[4] = { |
bb88f325 MB |
2275 | "8-bits per channel", |
2276 | "10-bits per channel", | |
2277 | "12-bits per channel", | |
2278 | "16-bits per channel (not supported)" | |
2279 | }; | |
54450f59 HV |
2280 | |
2281 | v4l2_info(sd, "-----Chip status-----\n"); | |
2282 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); | |
d42010a1 | 2283 | edid_enabled = rep_read(sd, info->edid_status_reg); |
4a31a93a | 2284 | v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", |
4a2ccdd2 LP |
2285 | ((edid_enabled & 0x01) ? "Yes" : "No"), |
2286 | ((edid_enabled & 0x02) ? "Yes" : "No"), | |
2287 | ((edid_enabled & 0x04) ? "Yes" : "No"), | |
2288 | ((edid_enabled & 0x08) ? "Yes" : "No")); | |
54450f59 HV |
2289 | v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? |
2290 | "enabled" : "disabled"); | |
2291 | ||
2292 | v4l2_info(sd, "-----Signal status-----\n"); | |
d42010a1 | 2293 | cable_det = info->read_cable_det(sd); |
4a31a93a | 2294 | v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", |
d42010a1 LPC |
2295 | ((cable_det & 0x01) ? "Yes" : "No"), |
2296 | ((cable_det & 0x02) ? "Yes" : "No"), | |
4a2ccdd2 | 2297 | ((cable_det & 0x04) ? "Yes" : "No"), |
d42010a1 | 2298 | ((cable_det & 0x08) ? "Yes" : "No")); |
54450f59 HV |
2299 | v4l2_info(sd, "TMDS signal detected: %s\n", |
2300 | no_signal_tmds(sd) ? "false" : "true"); | |
2301 | v4l2_info(sd, "TMDS signal locked: %s\n", | |
2302 | no_lock_tmds(sd) ? "false" : "true"); | |
2303 | v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); | |
2304 | v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); | |
2305 | v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); | |
2306 | v4l2_info(sd, "CP free run: %s\n", | |
58514625 | 2307 | (in_free_run(sd)) ? "on" : "off"); |
ccbd5bc4 HV |
2308 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", |
2309 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, | |
2310 | (io_read(sd, 0x01) & 0x70) >> 4); | |
54450f59 HV |
2311 | |
2312 | v4l2_info(sd, "-----Video Timings-----\n"); | |
2313 | if (read_stdi(sd, &stdi)) | |
2314 | v4l2_info(sd, "STDI: not locked\n"); | |
2315 | else | |
2316 | v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", | |
2317 | stdi.lcf, stdi.bl, stdi.lcvs, | |
2318 | stdi.interlaced ? "interlaced" : "progressive", | |
2319 | stdi.hs_pol, stdi.vs_pol); | |
b44b2e06 | 2320 | if (adv76xx_query_dv_timings(sd, &timings)) |
54450f59 HV |
2321 | v4l2_info(sd, "No video detected\n"); |
2322 | else | |
11d034c8 HV |
2323 | v4l2_print_dv_timings(sd->name, "Detected format: ", |
2324 | &timings, true); | |
2325 | v4l2_print_dv_timings(sd->name, "Configured format: ", | |
2326 | &state->timings, true); | |
54450f59 | 2327 | |
76eb2d30 MR |
2328 | if (no_signal(sd)) |
2329 | return 0; | |
2330 | ||
54450f59 HV |
2331 | v4l2_info(sd, "-----Color space-----\n"); |
2332 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", | |
2333 | rgb_quantization_range_txt[state->rgb_quantization_range]); | |
2334 | v4l2_info(sd, "Input color space: %s\n", | |
2335 | input_color_space_txt[reg_io_0x02 >> 4]); | |
7a5d99e7 | 2336 | v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n", |
54450f59 HV |
2337 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", |
2338 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", | |
5dd7d88a | 2339 | (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? |
7a5d99e7 HV |
2340 | "enabled" : "disabled", |
2341 | (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); | |
54450f59 | 2342 | v4l2_info(sd, "Color space conversion: %s\n", |
80f4944e | 2343 | csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); |
54450f59 | 2344 | |
4a31a93a | 2345 | if (!is_digital_input(sd)) |
76eb2d30 MR |
2346 | return 0; |
2347 | ||
2348 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); | |
4a31a93a MR |
2349 | v4l2_info(sd, "Digital video port selected: %c\n", |
2350 | (hdmi_read(sd, 0x00) & 0x03) + 'A'); | |
2351 | v4l2_info(sd, "HDCP encrypted content: %s\n", | |
2352 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); | |
76eb2d30 MR |
2353 | v4l2_info(sd, "HDCP keys read: %s%s\n", |
2354 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", | |
2355 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); | |
77639ff2 | 2356 | if (is_hdmi(sd)) { |
76eb2d30 MR |
2357 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; |
2358 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; | |
2359 | bool audio_mute = io_read(sd, 0x65) & 0x40; | |
2360 | ||
2361 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", | |
2362 | audio_pll_locked ? "locked" : "not locked", | |
2363 | audio_sample_packet_detect ? "detected" : "not detected", | |
2364 | audio_mute ? "muted" : "enabled"); | |
2365 | if (audio_pll_locked && audio_sample_packet_detect) { | |
2366 | v4l2_info(sd, "Audio format: %s\n", | |
2367 | (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); | |
2368 | } | |
2369 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + | |
2370 | (hdmi_read(sd, 0x5c) << 8) + | |
2371 | (hdmi_read(sd, 0x5d) & 0xf0)); | |
2372 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + | |
2373 | (hdmi_read(sd, 0x5e) << 8) + | |
2374 | hdmi_read(sd, 0x5f)); | |
2375 | v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); | |
2376 | ||
2377 | v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); | |
7a5d99e7 | 2378 | v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); |
76eb2d30 | 2379 | |
516613c1 | 2380 | adv76xx_log_infoframes(sd); |
54450f59 HV |
2381 | } |
2382 | ||
2383 | return 0; | |
2384 | } | |
2385 | ||
6f5bcfc3 LPC |
2386 | static int adv76xx_subscribe_event(struct v4l2_subdev *sd, |
2387 | struct v4l2_fh *fh, | |
2388 | struct v4l2_event_subscription *sub) | |
2389 | { | |
2390 | switch (sub->type) { | |
2391 | case V4L2_EVENT_SOURCE_CHANGE: | |
2392 | return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); | |
2393 | case V4L2_EVENT_CTRL: | |
2394 | return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); | |
2395 | default: | |
2396 | return -EINVAL; | |
2397 | } | |
2398 | } | |
2399 | ||
54450f59 HV |
2400 | /* ----------------------------------------------------------------------- */ |
2401 | ||
b44b2e06 PA |
2402 | static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { |
2403 | .s_ctrl = adv76xx_s_ctrl, | |
54450f59 HV |
2404 | }; |
2405 | ||
b44b2e06 PA |
2406 | static const struct v4l2_subdev_core_ops adv76xx_core_ops = { |
2407 | .log_status = adv76xx_log_status, | |
2408 | .interrupt_service_routine = adv76xx_isr, | |
6f5bcfc3 | 2409 | .subscribe_event = adv76xx_subscribe_event, |
0975626d | 2410 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, |
54450f59 | 2411 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
b44b2e06 PA |
2412 | .g_register = adv76xx_g_register, |
2413 | .s_register = adv76xx_s_register, | |
54450f59 HV |
2414 | #endif |
2415 | }; | |
2416 | ||
b44b2e06 PA |
2417 | static const struct v4l2_subdev_video_ops adv76xx_video_ops = { |
2418 | .s_routing = adv76xx_s_routing, | |
2419 | .g_input_status = adv76xx_g_input_status, | |
2420 | .s_dv_timings = adv76xx_s_dv_timings, | |
2421 | .g_dv_timings = adv76xx_g_dv_timings, | |
2422 | .query_dv_timings = adv76xx_query_dv_timings, | |
54450f59 HV |
2423 | }; |
2424 | ||
b44b2e06 PA |
2425 | static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { |
2426 | .enum_mbus_code = adv76xx_enum_mbus_code, | |
b7d4d2f8 | 2427 | .get_selection = adv76xx_get_selection, |
b44b2e06 PA |
2428 | .get_fmt = adv76xx_get_format, |
2429 | .set_fmt = adv76xx_set_format, | |
2430 | .get_edid = adv76xx_get_edid, | |
2431 | .set_edid = adv76xx_set_edid, | |
2432 | .dv_timings_cap = adv76xx_dv_timings_cap, | |
2433 | .enum_dv_timings = adv76xx_enum_dv_timings, | |
54450f59 HV |
2434 | }; |
2435 | ||
b44b2e06 PA |
2436 | static const struct v4l2_subdev_ops adv76xx_ops = { |
2437 | .core = &adv76xx_core_ops, | |
2438 | .video = &adv76xx_video_ops, | |
2439 | .pad = &adv76xx_pad_ops, | |
54450f59 HV |
2440 | }; |
2441 | ||
2442 | /* -------------------------- custom ctrls ---------------------------------- */ | |
2443 | ||
2444 | static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { | |
b44b2e06 | 2445 | .ops = &adv76xx_ctrl_ops, |
54450f59 HV |
2446 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, |
2447 | .name = "Analog Sampling Phase", | |
2448 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2449 | .min = 0, | |
2450 | .max = 0x1f, | |
2451 | .step = 1, | |
2452 | .def = 0, | |
2453 | }; | |
2454 | ||
b44b2e06 PA |
2455 | static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { |
2456 | .ops = &adv76xx_ctrl_ops, | |
54450f59 HV |
2457 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, |
2458 | .name = "Free Running Color, Manual", | |
2459 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
2460 | .min = false, | |
2461 | .max = true, | |
2462 | .step = 1, | |
2463 | .def = false, | |
2464 | }; | |
2465 | ||
b44b2e06 PA |
2466 | static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { |
2467 | .ops = &adv76xx_ctrl_ops, | |
54450f59 HV |
2468 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, |
2469 | .name = "Free Running Color", | |
2470 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2471 | .min = 0x0, | |
2472 | .max = 0xffffff, | |
2473 | .step = 0x1, | |
2474 | .def = 0x0, | |
2475 | }; | |
2476 | ||
2477 | /* ----------------------------------------------------------------------- */ | |
2478 | ||
b44b2e06 | 2479 | static int adv76xx_core_init(struct v4l2_subdev *sd) |
54450f59 | 2480 | { |
b44b2e06 PA |
2481 | struct adv76xx_state *state = to_state(sd); |
2482 | const struct adv76xx_chip_info *info = state->info; | |
2483 | struct adv76xx_platform_data *pdata = &state->pdata; | |
54450f59 HV |
2484 | |
2485 | hdmi_write(sd, 0x48, | |
2486 | (pdata->disable_pwrdnb ? 0x80 : 0) | | |
2487 | (pdata->disable_cable_det_rst ? 0x40 : 0)); | |
2488 | ||
2489 | disable_input(sd); | |
2490 | ||
5ef54b59 LP |
2491 | if (pdata->default_input >= 0 && |
2492 | pdata->default_input < state->source_pad) { | |
2493 | state->selected_input = pdata->default_input; | |
2494 | select_input(sd); | |
2495 | enable_input(sd); | |
2496 | } | |
2497 | ||
54450f59 HV |
2498 | /* power */ |
2499 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ | |
2500 | io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ | |
2501 | cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ | |
2502 | ||
2503 | /* video format */ | |
22d97e56 | 2504 | io_write_clr_set(sd, 0x02, 0x0f, |
54450f59 HV |
2505 | pdata->alt_gamma << 3 | |
2506 | pdata->op_656_range << 2 | | |
54450f59 | 2507 | pdata->alt_data_sat << 0); |
22d97e56 | 2508 | io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | |
539b33b0 LP |
2509 | pdata->insert_av_codes << 2 | |
2510 | pdata->replicate_av_codes << 1); | |
b44b2e06 | 2511 | adv76xx_setup_format(state); |
54450f59 | 2512 | |
54450f59 | 2513 | cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ |
98908696 MB |
2514 | |
2515 | /* VS, HS polarities */ | |
1b5ab875 LP |
2516 | io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | |
2517 | pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); | |
f31b62e1 MK |
2518 | |
2519 | /* Adjust drive strength */ | |
2520 | io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | | |
2521 | pdata->dr_str_clk << 2 | | |
2522 | pdata->dr_str_sync); | |
2523 | ||
54450f59 HV |
2524 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ |
2525 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ | |
2526 | cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - | |
80939647 | 2527 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 | 2528 | cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - |
80939647 | 2529 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 HV |
2530 | cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution |
2531 | for digital formats */ | |
2532 | ||
5474b983 | 2533 | /* HDMI audio */ |
22d97e56 LP |
2534 | hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ |
2535 | hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ | |
2536 | hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ | |
5474b983 | 2537 | |
54450f59 HV |
2538 | /* TODO from platform data */ |
2539 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ | |
2540 | ||
b44b2e06 | 2541 | if (adv76xx_has_afe(state)) { |
d42010a1 | 2542 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ |
22d97e56 | 2543 | io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); |
d42010a1 | 2544 | } |
54450f59 | 2545 | |
54450f59 | 2546 | /* interrupts */ |
d42010a1 | 2547 | io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ |
54450f59 | 2548 | io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ |
d42010a1 LPC |
2549 | io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ |
2550 | io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ | |
2551 | info->setup_irqs(sd); | |
54450f59 HV |
2552 | |
2553 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); | |
2554 | } | |
2555 | ||
d42010a1 LPC |
2556 | static void adv7604_setup_irqs(struct v4l2_subdev *sd) |
2557 | { | |
2558 | io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ | |
2559 | } | |
2560 | ||
2561 | static void adv7611_setup_irqs(struct v4l2_subdev *sd) | |
2562 | { | |
2563 | io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ | |
2564 | } | |
2565 | ||
8331d30b WT |
2566 | static void adv7612_setup_irqs(struct v4l2_subdev *sd) |
2567 | { | |
2568 | io_write(sd, 0x41, 0xd0); /* disable INT2 */ | |
2569 | } | |
2570 | ||
b44b2e06 | 2571 | static void adv76xx_unregister_clients(struct adv76xx_state *state) |
54450f59 | 2572 | { |
05cacb17 LP |
2573 | unsigned int i; |
2574 | ||
2575 | for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { | |
2576 | if (state->i2c_clients[i]) | |
2577 | i2c_unregister_device(state->i2c_clients[i]); | |
2578 | } | |
54450f59 HV |
2579 | } |
2580 | ||
b44b2e06 | 2581 | static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, |
54450f59 HV |
2582 | u8 addr, u8 io_reg) |
2583 | { | |
2584 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2585 | ||
2586 | if (addr) | |
2587 | io_write(sd, io_reg, addr << 1); | |
2588 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); | |
2589 | } | |
2590 | ||
b44b2e06 | 2591 | static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { |
d42010a1 LPC |
2592 | /* reset ADI recommended settings for HDMI: */ |
2593 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
b44b2e06 PA |
2594 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ |
2595 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2596 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ | |
2597 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ | |
2598 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2599 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ | |
2600 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ | |
2601 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2602 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2603 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ | |
2604 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ | |
2605 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ | |
d42010a1 LPC |
2606 | |
2607 | /* set ADI recommended settings for digitizer */ | |
2608 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
b44b2e06 PA |
2609 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ |
2610 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ | |
2611 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ | |
2612 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ | |
2613 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ | |
d42010a1 | 2614 | |
b44b2e06 | 2615 | { ADV76XX_REG_SEQ_TERM, 0 }, |
d42010a1 LPC |
2616 | }; |
2617 | ||
b44b2e06 | 2618 | static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { |
d42010a1 LPC |
2619 | /* set ADI recommended settings for HDMI: */ |
2620 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
b44b2e06 PA |
2621 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ |
2622 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ | |
2623 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ | |
2624 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2625 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ | |
2626 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ | |
2627 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2628 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2629 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ | |
2630 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ | |
2631 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ | |
d42010a1 LPC |
2632 | |
2633 | /* reset ADI recommended settings for digitizer */ | |
2634 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
b44b2e06 PA |
2635 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ |
2636 | { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ | |
d42010a1 | 2637 | |
b44b2e06 | 2638 | { ADV76XX_REG_SEQ_TERM, 0 }, |
d42010a1 LPC |
2639 | }; |
2640 | ||
b44b2e06 | 2641 | static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { |
c41ad9c3 | 2642 | /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ |
b44b2e06 PA |
2643 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, |
2644 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, | |
2645 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, | |
2646 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, | |
2647 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, | |
2648 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, | |
2649 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, | |
2650 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, | |
2651 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, | |
2652 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, | |
2653 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, | |
2654 | ||
2655 | { ADV76XX_REG_SEQ_TERM, 0 }, | |
d42010a1 LPC |
2656 | }; |
2657 | ||
8331d30b WT |
2658 | static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { |
2659 | { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, | |
2660 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, | |
2661 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, | |
2662 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, | |
2663 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, | |
2664 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, | |
2665 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, | |
2666 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, | |
2667 | { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, | |
2668 | { ADV76XX_REG_SEQ_TERM, 0 }, | |
2669 | }; | |
2670 | ||
b44b2e06 | 2671 | static const struct adv76xx_chip_info adv76xx_chip_info[] = { |
d42010a1 LPC |
2672 | [ADV7604] = { |
2673 | .type = ADV7604, | |
2674 | .has_afe = true, | |
c784b1e2 | 2675 | .max_port = ADV7604_PAD_VGA_COMP, |
d42010a1 LPC |
2676 | .num_dv_ports = 4, |
2677 | .edid_enable_reg = 0x77, | |
2678 | .edid_status_reg = 0x7d, | |
2679 | .lcf_reg = 0xb3, | |
2680 | .tdms_lock_mask = 0xe0, | |
2681 | .cable_det_mask = 0x1e, | |
2682 | .fmt_change_digital_mask = 0xc1, | |
80f4944e | 2683 | .cp_csc = 0xfc, |
539b33b0 LP |
2684 | .formats = adv7604_formats, |
2685 | .nformats = ARRAY_SIZE(adv7604_formats), | |
d42010a1 LPC |
2686 | .set_termination = adv7604_set_termination, |
2687 | .setup_irqs = adv7604_setup_irqs, | |
2688 | .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, | |
2689 | .read_cable_det = adv7604_read_cable_det, | |
2690 | .recommended_settings = { | |
2691 | [0] = adv7604_recommended_settings_afe, | |
2692 | [1] = adv7604_recommended_settings_hdmi, | |
2693 | }, | |
2694 | .num_recommended_settings = { | |
2695 | [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), | |
2696 | [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), | |
2697 | }, | |
b44b2e06 PA |
2698 | .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | |
2699 | BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | | |
d42010a1 | 2700 | BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | |
b44b2e06 PA |
2701 | BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | |
2702 | BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | | |
2703 | BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | | |
d42010a1 | 2704 | BIT(ADV7604_PAGE_VDP), |
5380baaf | 2705 | .linewidth_mask = 0xfff, |
2706 | .field0_height_mask = 0xfff, | |
2707 | .field1_height_mask = 0xfff, | |
2708 | .hfrontporch_mask = 0x3ff, | |
2709 | .hsync_mask = 0x3ff, | |
2710 | .hbackporch_mask = 0x3ff, | |
2711 | .field0_vfrontporch_mask = 0x1fff, | |
2712 | .field0_vsync_mask = 0x1fff, | |
2713 | .field0_vbackporch_mask = 0x1fff, | |
2714 | .field1_vfrontporch_mask = 0x1fff, | |
2715 | .field1_vsync_mask = 0x1fff, | |
2716 | .field1_vbackporch_mask = 0x1fff, | |
d42010a1 LPC |
2717 | }, |
2718 | [ADV7611] = { | |
2719 | .type = ADV7611, | |
2720 | .has_afe = false, | |
b44b2e06 | 2721 | .max_port = ADV76XX_PAD_HDMI_PORT_A, |
d42010a1 LPC |
2722 | .num_dv_ports = 1, |
2723 | .edid_enable_reg = 0x74, | |
2724 | .edid_status_reg = 0x76, | |
2725 | .lcf_reg = 0xa3, | |
2726 | .tdms_lock_mask = 0x43, | |
2727 | .cable_det_mask = 0x01, | |
2728 | .fmt_change_digital_mask = 0x03, | |
80f4944e | 2729 | .cp_csc = 0xf4, |
539b33b0 LP |
2730 | .formats = adv7611_formats, |
2731 | .nformats = ARRAY_SIZE(adv7611_formats), | |
d42010a1 LPC |
2732 | .set_termination = adv7611_set_termination, |
2733 | .setup_irqs = adv7611_setup_irqs, | |
2734 | .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, | |
2735 | .read_cable_det = adv7611_read_cable_det, | |
2736 | .recommended_settings = { | |
2737 | [1] = adv7611_recommended_settings_hdmi, | |
2738 | }, | |
2739 | .num_recommended_settings = { | |
2740 | [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), | |
2741 | }, | |
b44b2e06 PA |
2742 | .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | |
2743 | BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | | |
2744 | BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | | |
2745 | BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), | |
5380baaf | 2746 | .linewidth_mask = 0x1fff, |
2747 | .field0_height_mask = 0x1fff, | |
2748 | .field1_height_mask = 0x1fff, | |
2749 | .hfrontporch_mask = 0x1fff, | |
2750 | .hsync_mask = 0x1fff, | |
2751 | .hbackporch_mask = 0x1fff, | |
2752 | .field0_vfrontporch_mask = 0x3fff, | |
2753 | .field0_vsync_mask = 0x3fff, | |
2754 | .field0_vbackporch_mask = 0x3fff, | |
2755 | .field1_vfrontporch_mask = 0x3fff, | |
2756 | .field1_vsync_mask = 0x3fff, | |
2757 | .field1_vbackporch_mask = 0x3fff, | |
d42010a1 | 2758 | }, |
8331d30b WT |
2759 | [ADV7612] = { |
2760 | .type = ADV7612, | |
2761 | .has_afe = false, | |
7111cddd WT |
2762 | .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ |
2763 | .num_dv_ports = 1, /* normally 2 */ | |
8331d30b WT |
2764 | .edid_enable_reg = 0x74, |
2765 | .edid_status_reg = 0x76, | |
2766 | .lcf_reg = 0xa3, | |
2767 | .tdms_lock_mask = 0x43, | |
2768 | .cable_det_mask = 0x01, | |
2769 | .fmt_change_digital_mask = 0x03, | |
7111cddd | 2770 | .cp_csc = 0xf4, |
8331d30b WT |
2771 | .formats = adv7612_formats, |
2772 | .nformats = ARRAY_SIZE(adv7612_formats), | |
2773 | .set_termination = adv7611_set_termination, | |
2774 | .setup_irqs = adv7612_setup_irqs, | |
2775 | .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, | |
7111cddd | 2776 | .read_cable_det = adv7612_read_cable_det, |
8331d30b WT |
2777 | .recommended_settings = { |
2778 | [1] = adv7612_recommended_settings_hdmi, | |
2779 | }, | |
2780 | .num_recommended_settings = { | |
2781 | [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), | |
2782 | }, | |
2783 | .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | | |
2784 | BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | | |
2785 | BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | | |
2786 | BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), | |
2787 | .linewidth_mask = 0x1fff, | |
2788 | .field0_height_mask = 0x1fff, | |
2789 | .field1_height_mask = 0x1fff, | |
2790 | .hfrontporch_mask = 0x1fff, | |
2791 | .hsync_mask = 0x1fff, | |
2792 | .hbackporch_mask = 0x1fff, | |
2793 | .field0_vfrontporch_mask = 0x3fff, | |
2794 | .field0_vsync_mask = 0x3fff, | |
2795 | .field0_vbackporch_mask = 0x3fff, | |
2796 | .field1_vfrontporch_mask = 0x3fff, | |
2797 | .field1_vsync_mask = 0x3fff, | |
2798 | .field1_vbackporch_mask = 0x3fff, | |
2799 | }, | |
d42010a1 LPC |
2800 | }; |
2801 | ||
7f099a75 | 2802 | static const struct i2c_device_id adv76xx_i2c_id[] = { |
b44b2e06 PA |
2803 | { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, |
2804 | { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, | |
8331d30b | 2805 | { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, |
f82f313e LP |
2806 | { } |
2807 | }; | |
b44b2e06 | 2808 | MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); |
f82f313e | 2809 | |
7f099a75 | 2810 | static const struct of_device_id adv76xx_of_id[] __maybe_unused = { |
b44b2e06 | 2811 | { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, |
8331d30b | 2812 | { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, |
f82f313e LP |
2813 | { } |
2814 | }; | |
b44b2e06 | 2815 | MODULE_DEVICE_TABLE(of, adv76xx_of_id); |
f82f313e | 2816 | |
b44b2e06 | 2817 | static int adv76xx_parse_dt(struct adv76xx_state *state) |
f82f313e | 2818 | { |
6fa88045 LP |
2819 | struct v4l2_of_endpoint bus_cfg; |
2820 | struct device_node *endpoint; | |
2821 | struct device_node *np; | |
2822 | unsigned int flags; | |
bf9c8227 | 2823 | u32 v; |
6fa88045 | 2824 | |
b44b2e06 | 2825 | np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; |
6fa88045 LP |
2826 | |
2827 | /* Parse the endpoint. */ | |
2828 | endpoint = of_graph_get_next_endpoint(np, NULL); | |
2829 | if (!endpoint) | |
2830 | return -EINVAL; | |
2831 | ||
2832 | v4l2_of_parse_endpoint(endpoint, &bus_cfg); | |
bf9c8227 IM |
2833 | |
2834 | if (!of_property_read_u32(endpoint, "default-input", &v)) | |
2835 | state->pdata.default_input = v; | |
2836 | else | |
2837 | state->pdata.default_input = -1; | |
2838 | ||
6fa88045 LP |
2839 | of_node_put(endpoint); |
2840 | ||
2841 | flags = bus_cfg.bus.parallel.flags; | |
2842 | ||
2843 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
2844 | state->pdata.inv_hs_pol = 1; | |
2845 | ||
2846 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
2847 | state->pdata.inv_vs_pol = 1; | |
2848 | ||
2849 | if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
2850 | state->pdata.inv_llc_pol = 1; | |
2851 | ||
2852 | if (bus_cfg.bus_type == V4L2_MBUS_BT656) { | |
2853 | state->pdata.insert_av_codes = 1; | |
2854 | state->pdata.op_656_range = 1; | |
2855 | } | |
2856 | ||
f82f313e | 2857 | /* Disable the interrupt for now as no DT-based board uses it. */ |
b44b2e06 | 2858 | state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; |
f82f313e LP |
2859 | |
2860 | /* Use the default I2C addresses. */ | |
2861 | state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; | |
b44b2e06 PA |
2862 | state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40; |
2863 | state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e; | |
f82f313e LP |
2864 | state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; |
2865 | state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; | |
b44b2e06 PA |
2866 | state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26; |
2867 | state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32; | |
2868 | state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36; | |
2869 | state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34; | |
2870 | state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30; | |
2871 | state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22; | |
f82f313e LP |
2872 | state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; |
2873 | ||
2874 | /* Hardcode the remaining platform data fields. */ | |
2875 | state->pdata.disable_pwrdnb = 0; | |
2876 | state->pdata.disable_cable_det_rst = 0; | |
f82f313e | 2877 | state->pdata.blank_data = 1; |
f82f313e | 2878 | state->pdata.alt_data_sat = 1; |
f82f313e LP |
2879 | state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; |
2880 | state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; | |
2881 | ||
2882 | return 0; | |
2883 | } | |
2884 | ||
f862f57d PA |
2885 | static const struct regmap_config adv76xx_regmap_cnf[] = { |
2886 | { | |
2887 | .name = "io", | |
2888 | .reg_bits = 8, | |
2889 | .val_bits = 8, | |
2890 | ||
2891 | .max_register = 0xff, | |
2892 | .cache_type = REGCACHE_NONE, | |
2893 | }, | |
2894 | { | |
2895 | .name = "avlink", | |
2896 | .reg_bits = 8, | |
2897 | .val_bits = 8, | |
2898 | ||
2899 | .max_register = 0xff, | |
2900 | .cache_type = REGCACHE_NONE, | |
2901 | }, | |
2902 | { | |
2903 | .name = "cec", | |
2904 | .reg_bits = 8, | |
2905 | .val_bits = 8, | |
2906 | ||
2907 | .max_register = 0xff, | |
2908 | .cache_type = REGCACHE_NONE, | |
2909 | }, | |
2910 | { | |
2911 | .name = "infoframe", | |
2912 | .reg_bits = 8, | |
2913 | .val_bits = 8, | |
2914 | ||
2915 | .max_register = 0xff, | |
2916 | .cache_type = REGCACHE_NONE, | |
2917 | }, | |
2918 | { | |
2919 | .name = "esdp", | |
2920 | .reg_bits = 8, | |
2921 | .val_bits = 8, | |
2922 | ||
2923 | .max_register = 0xff, | |
2924 | .cache_type = REGCACHE_NONE, | |
2925 | }, | |
2926 | { | |
2927 | .name = "epp", | |
2928 | .reg_bits = 8, | |
2929 | .val_bits = 8, | |
2930 | ||
2931 | .max_register = 0xff, | |
2932 | .cache_type = REGCACHE_NONE, | |
2933 | }, | |
2934 | { | |
2935 | .name = "afe", | |
2936 | .reg_bits = 8, | |
2937 | .val_bits = 8, | |
2938 | ||
2939 | .max_register = 0xff, | |
2940 | .cache_type = REGCACHE_NONE, | |
2941 | }, | |
2942 | { | |
2943 | .name = "rep", | |
2944 | .reg_bits = 8, | |
2945 | .val_bits = 8, | |
2946 | ||
2947 | .max_register = 0xff, | |
2948 | .cache_type = REGCACHE_NONE, | |
2949 | }, | |
2950 | { | |
2951 | .name = "edid", | |
2952 | .reg_bits = 8, | |
2953 | .val_bits = 8, | |
2954 | ||
2955 | .max_register = 0xff, | |
2956 | .cache_type = REGCACHE_NONE, | |
2957 | }, | |
2958 | ||
2959 | { | |
2960 | .name = "hdmi", | |
2961 | .reg_bits = 8, | |
2962 | .val_bits = 8, | |
2963 | ||
2964 | .max_register = 0xff, | |
2965 | .cache_type = REGCACHE_NONE, | |
2966 | }, | |
2967 | { | |
2968 | .name = "test", | |
2969 | .reg_bits = 8, | |
2970 | .val_bits = 8, | |
2971 | ||
2972 | .max_register = 0xff, | |
2973 | .cache_type = REGCACHE_NONE, | |
2974 | }, | |
2975 | { | |
2976 | .name = "cp", | |
2977 | .reg_bits = 8, | |
2978 | .val_bits = 8, | |
2979 | ||
2980 | .max_register = 0xff, | |
2981 | .cache_type = REGCACHE_NONE, | |
2982 | }, | |
2983 | { | |
2984 | .name = "vdp", | |
2985 | .reg_bits = 8, | |
2986 | .val_bits = 8, | |
2987 | ||
2988 | .max_register = 0xff, | |
2989 | .cache_type = REGCACHE_NONE, | |
2990 | }, | |
2991 | }; | |
2992 | ||
2993 | static int configure_regmap(struct adv76xx_state *state, int region) | |
2994 | { | |
2995 | int err; | |
2996 | ||
2997 | if (!state->i2c_clients[region]) | |
2998 | return -ENODEV; | |
2999 | ||
3000 | state->regmap[region] = | |
3001 | devm_regmap_init_i2c(state->i2c_clients[region], | |
3002 | &adv76xx_regmap_cnf[region]); | |
3003 | ||
3004 | if (IS_ERR(state->regmap[region])) { | |
3005 | err = PTR_ERR(state->regmap[region]); | |
3006 | v4l_err(state->i2c_clients[region], | |
3007 | "Error initializing regmap %d with error %d\n", | |
3008 | region, err); | |
3009 | return -EINVAL; | |
3010 | } | |
3011 | ||
3012 | return 0; | |
3013 | } | |
3014 | ||
3015 | static int configure_regmaps(struct adv76xx_state *state) | |
3016 | { | |
3017 | int i, err; | |
3018 | ||
3019 | for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { | |
3020 | err = configure_regmap(state, i); | |
3021 | if (err && (err != -ENODEV)) | |
3022 | return err; | |
3023 | } | |
3024 | return 0; | |
3025 | } | |
3026 | ||
b44b2e06 | 3027 | static int adv76xx_probe(struct i2c_client *client, |
54450f59 HV |
3028 | const struct i2c_device_id *id) |
3029 | { | |
591b72fe HV |
3030 | static const struct v4l2_dv_timings cea640x480 = |
3031 | V4L2_DV_BT_CEA_640X480P59_94; | |
b44b2e06 | 3032 | struct adv76xx_state *state; |
54450f59 HV |
3033 | struct v4l2_ctrl_handler *hdl; |
3034 | struct v4l2_subdev *sd; | |
c784b1e2 | 3035 | unsigned int i; |
f862f57d | 3036 | unsigned int val, val2; |
54450f59 HV |
3037 | int err; |
3038 | ||
3039 | /* Check if the adapter supports the needed features */ | |
3040 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
3041 | return -EIO; | |
b44b2e06 | 3042 | v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", |
54450f59 HV |
3043 | client->addr << 1); |
3044 | ||
c02b211d | 3045 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
54450f59 | 3046 | if (!state) { |
b44b2e06 | 3047 | v4l_err(client, "Could not allocate adv76xx_state memory!\n"); |
54450f59 HV |
3048 | return -ENOMEM; |
3049 | } | |
3050 | ||
b44b2e06 | 3051 | state->i2c_clients[ADV76XX_PAGE_IO] = client; |
d42010a1 | 3052 | |
25a64ac9 MR |
3053 | /* initialize variables */ |
3054 | state->restart_stdi_once = true; | |
ff4f80fd | 3055 | state->selected_input = ~0; |
25a64ac9 | 3056 | |
f82f313e LP |
3057 | if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { |
3058 | const struct of_device_id *oid; | |
3059 | ||
b44b2e06 | 3060 | oid = of_match_node(adv76xx_of_id, client->dev.of_node); |
f82f313e LP |
3061 | state->info = oid->data; |
3062 | ||
b44b2e06 | 3063 | err = adv76xx_parse_dt(state); |
f82f313e LP |
3064 | if (err < 0) { |
3065 | v4l_err(client, "DT parsing error\n"); | |
3066 | return err; | |
3067 | } | |
3068 | } else if (client->dev.platform_data) { | |
b44b2e06 | 3069 | struct adv76xx_platform_data *pdata = client->dev.platform_data; |
f82f313e | 3070 | |
b44b2e06 | 3071 | state->info = (const struct adv76xx_chip_info *)id->driver_data; |
f82f313e LP |
3072 | state->pdata = *pdata; |
3073 | } else { | |
54450f59 | 3074 | v4l_err(client, "No platform data!\n"); |
c02b211d | 3075 | return -ENODEV; |
54450f59 | 3076 | } |
e9d50e9e LP |
3077 | |
3078 | /* Request GPIOs. */ | |
3079 | for (i = 0; i < state->info->num_dv_ports; ++i) { | |
3080 | state->hpd_gpio[i] = | |
269bd132 UKK |
3081 | devm_gpiod_get_index_optional(&client->dev, "hpd", i, |
3082 | GPIOD_OUT_LOW); | |
e9d50e9e | 3083 | if (IS_ERR(state->hpd_gpio[i])) |
269bd132 | 3084 | return PTR_ERR(state->hpd_gpio[i]); |
e9d50e9e | 3085 | |
269bd132 UKK |
3086 | if (state->hpd_gpio[i]) |
3087 | v4l_info(client, "Handling HPD %u GPIO\n", i); | |
e9d50e9e LP |
3088 | } |
3089 | ||
591b72fe | 3090 | state->timings = cea640x480; |
b44b2e06 | 3091 | state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); |
54450f59 HV |
3092 | |
3093 | sd = &state->sd; | |
b44b2e06 | 3094 | v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); |
d42010a1 LPC |
3095 | snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", |
3096 | id->name, i2c_adapter_id(client->adapter), | |
3097 | client->addr); | |
0975626d | 3098 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; |
54450f59 | 3099 | |
f862f57d PA |
3100 | /* Configure IO Regmap region */ |
3101 | err = configure_regmap(state, ADV76XX_PAGE_IO); | |
3102 | ||
3103 | if (err) { | |
3104 | v4l2_err(sd, "Error configuring IO regmap region\n"); | |
3105 | return -ENODEV; | |
3106 | } | |
3107 | ||
d42010a1 LPC |
3108 | /* |
3109 | * Verify that the chip is present. On ADV7604 the RD_INFO register only | |
3110 | * identifies the revision, while on ADV7611 it identifies the model as | |
3111 | * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. | |
3112 | */ | |
8331d30b WT |
3113 | switch (state->info->type) { |
3114 | case ADV7604: | |
f862f57d PA |
3115 | err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); |
3116 | if (err) { | |
3117 | v4l2_err(sd, "Error %d reading IO Regmap\n", err); | |
3118 | return -ENODEV; | |
3119 | } | |
d42010a1 | 3120 | if (val != 0x68) { |
f862f57d | 3121 | v4l2_err(sd, "not an adv7604 on address 0x%x\n", |
d42010a1 LPC |
3122 | client->addr << 1); |
3123 | return -ENODEV; | |
3124 | } | |
8331d30b WT |
3125 | break; |
3126 | case ADV7611: | |
3127 | case ADV7612: | |
f862f57d PA |
3128 | err = regmap_read(state->regmap[ADV76XX_PAGE_IO], |
3129 | 0xea, | |
3130 | &val); | |
3131 | if (err) { | |
3132 | v4l2_err(sd, "Error %d reading IO Regmap\n", err); | |
3133 | return -ENODEV; | |
3134 | } | |
3135 | val2 = val << 8; | |
3136 | err = regmap_read(state->regmap[ADV76XX_PAGE_IO], | |
3137 | 0xeb, | |
3138 | &val); | |
3139 | if (err) { | |
3140 | v4l2_err(sd, "Error %d reading IO Regmap\n", err); | |
3141 | return -ENODEV; | |
3142 | } | |
c1362384 | 3143 | val |= val2; |
8331d30b WT |
3144 | if ((state->info->type == ADV7611 && val != 0x2051) || |
3145 | (state->info->type == ADV7612 && val != 0x2041)) { | |
3146 | v4l2_err(sd, "not an adv761x on address 0x%x\n", | |
d42010a1 LPC |
3147 | client->addr << 1); |
3148 | return -ENODEV; | |
3149 | } | |
8331d30b | 3150 | break; |
54450f59 HV |
3151 | } |
3152 | ||
3153 | /* control handlers */ | |
3154 | hdl = &state->hdl; | |
b44b2e06 | 3155 | v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); |
54450f59 | 3156 | |
b44b2e06 | 3157 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 | 3158 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); |
b44b2e06 | 3159 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 | 3160 | V4L2_CID_CONTRAST, 0, 255, 1, 128); |
b44b2e06 | 3161 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 | 3162 | V4L2_CID_SATURATION, 0, 255, 1, 128); |
b44b2e06 | 3163 | v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, |
54450f59 HV |
3164 | V4L2_CID_HUE, 0, 128, 1, 0); |
3165 | ||
3166 | /* private controls */ | |
3167 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, | |
d42010a1 LPC |
3168 | V4L2_CID_DV_RX_POWER_PRESENT, 0, |
3169 | (1 << state->info->num_dv_ports) - 1, 0, 0); | |
54450f59 | 3170 | state->rgb_quantization_range_ctrl = |
b44b2e06 | 3171 | v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, |
54450f59 HV |
3172 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, |
3173 | 0, V4L2_DV_RGB_RANGE_AUTO); | |
54450f59 HV |
3174 | |
3175 | /* custom controls */ | |
b44b2e06 | 3176 | if (adv76xx_has_afe(state)) |
d42010a1 LPC |
3177 | state->analog_sampling_phase_ctrl = |
3178 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); | |
54450f59 | 3179 | state->free_run_color_manual_ctrl = |
b44b2e06 | 3180 | v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); |
54450f59 | 3181 | state->free_run_color_ctrl = |
b44b2e06 | 3182 | v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); |
54450f59 HV |
3183 | |
3184 | sd->ctrl_handler = hdl; | |
3185 | if (hdl->error) { | |
3186 | err = hdl->error; | |
3187 | goto err_hdl; | |
3188 | } | |
8c0eadb8 HV |
3189 | state->detect_tx_5v_ctrl->is_private = true; |
3190 | state->rgb_quantization_range_ctrl->is_private = true; | |
b44b2e06 | 3191 | if (adv76xx_has_afe(state)) |
d42010a1 | 3192 | state->analog_sampling_phase_ctrl->is_private = true; |
8c0eadb8 HV |
3193 | state->free_run_color_manual_ctrl->is_private = true; |
3194 | state->free_run_color_ctrl->is_private = true; | |
3195 | ||
b44b2e06 | 3196 | if (adv76xx_s_detect_tx_5v_ctrl(sd)) { |
54450f59 HV |
3197 | err = -ENODEV; |
3198 | goto err_hdl; | |
3199 | } | |
3200 | ||
b44b2e06 | 3201 | for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { |
05cacb17 LP |
3202 | if (!(BIT(i) & state->info->page_mask)) |
3203 | continue; | |
54450f59 | 3204 | |
05cacb17 | 3205 | state->i2c_clients[i] = |
b44b2e06 | 3206 | adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i], |
05cacb17 LP |
3207 | 0xf2 + i); |
3208 | if (state->i2c_clients[i] == NULL) { | |
d42010a1 | 3209 | err = -ENOMEM; |
05cacb17 | 3210 | v4l2_err(sd, "failed to create i2c client %u\n", i); |
d42010a1 LPC |
3211 | goto err_i2c; |
3212 | } | |
3213 | } | |
05cacb17 | 3214 | |
54450f59 HV |
3215 | /* work queues */ |
3216 | state->work_queues = create_singlethread_workqueue(client->name); | |
3217 | if (!state->work_queues) { | |
3218 | v4l2_err(sd, "Could not create work queue\n"); | |
3219 | err = -ENOMEM; | |
3220 | goto err_i2c; | |
3221 | } | |
3222 | ||
3223 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, | |
b44b2e06 | 3224 | adv76xx_delayed_work_enable_hotplug); |
54450f59 | 3225 | |
c784b1e2 LP |
3226 | state->source_pad = state->info->num_dv_ports |
3227 | + (state->info->has_afe ? 2 : 0); | |
3228 | for (i = 0; i < state->source_pad; ++i) | |
3229 | state->pads[i].flags = MEDIA_PAD_FL_SINK; | |
3230 | state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; | |
3231 | ||
ab22e77c | 3232 | err = media_entity_pads_init(&sd->entity, state->source_pad + 1, |
18095107 | 3233 | state->pads); |
54450f59 HV |
3234 | if (err) |
3235 | goto err_work_queues; | |
3236 | ||
f862f57d PA |
3237 | /* Configure regmaps */ |
3238 | err = configure_regmaps(state); | |
3239 | if (err) | |
3240 | goto err_entity; | |
3241 | ||
b44b2e06 | 3242 | err = adv76xx_core_init(sd); |
54450f59 HV |
3243 | if (err) |
3244 | goto err_entity; | |
3245 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, | |
3246 | client->addr << 1, client->adapter->name); | |
bedc3939 LPC |
3247 | |
3248 | err = v4l2_async_register_subdev(sd); | |
3249 | if (err) | |
3250 | goto err_entity; | |
3251 | ||
54450f59 HV |
3252 | return 0; |
3253 | ||
3254 | err_entity: | |
3255 | media_entity_cleanup(&sd->entity); | |
3256 | err_work_queues: | |
3257 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
3258 | destroy_workqueue(state->work_queues); | |
3259 | err_i2c: | |
b44b2e06 | 3260 | adv76xx_unregister_clients(state); |
54450f59 HV |
3261 | err_hdl: |
3262 | v4l2_ctrl_handler_free(hdl); | |
54450f59 HV |
3263 | return err; |
3264 | } | |
3265 | ||
3266 | /* ----------------------------------------------------------------------- */ | |
3267 | ||
b44b2e06 | 3268 | static int adv76xx_remove(struct i2c_client *client) |
54450f59 HV |
3269 | { |
3270 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
b44b2e06 | 3271 | struct adv76xx_state *state = to_state(sd); |
54450f59 HV |
3272 | |
3273 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
3274 | destroy_workqueue(state->work_queues); | |
bedc3939 | 3275 | v4l2_async_unregister_subdev(sd); |
54450f59 | 3276 | media_entity_cleanup(&sd->entity); |
b44b2e06 | 3277 | adv76xx_unregister_clients(to_state(sd)); |
54450f59 | 3278 | v4l2_ctrl_handler_free(sd->ctrl_handler); |
54450f59 HV |
3279 | return 0; |
3280 | } | |
3281 | ||
3282 | /* ----------------------------------------------------------------------- */ | |
3283 | ||
b44b2e06 | 3284 | static struct i2c_driver adv76xx_driver = { |
54450f59 | 3285 | .driver = { |
54450f59 | 3286 | .name = "adv7604", |
b44b2e06 | 3287 | .of_match_table = of_match_ptr(adv76xx_of_id), |
54450f59 | 3288 | }, |
b44b2e06 PA |
3289 | .probe = adv76xx_probe, |
3290 | .remove = adv76xx_remove, | |
3291 | .id_table = adv76xx_i2c_id, | |
54450f59 HV |
3292 | }; |
3293 | ||
b44b2e06 | 3294 | module_i2c_driver(adv76xx_driver); |