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[media] media: i2c: ADV7604: Migrate to regmap
[mirror_ubuntu-artful-kernel.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
516613c1 32#include <linux/hdmi.h>
c72a53ce 33#include <linux/i2c.h>
54450f59
HV		 34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
c72a53ce 37#include <linux/v4l2-dv-timings.h>
54450f59
HV		 38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
f862f57d 40#include <linux/regmap.h>
c72a53ce
LP		 41
42#include <media/adv7604.h>
54450f59 43#include <media/v4l2-ctrls.h>
c72a53ce 44#include <media/v4l2-device.h>
25764158 45#include <media/v4l2-dv-timings.h>
6fa88045 46#include <media/v4l2-of.h>
54450f59
HV		 47
48static int debug;
49module_param(debug, int, 0644);
50MODULE_PARM_DESC(debug, "debug level (0-2)");
51
52MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
53MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
54MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
55MODULE_LICENSE("GPL");
56
57/* ADV7604 system clock frequency */
b44b2e06 58#define ADV76XX_FSC (28636360)
54450f59 59
b44b2e06 60#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 61
b44b2e06 62#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 63#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 64#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 65
b44b2e06 66#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 67#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 68#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 69#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 70#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 71#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
72
b44b2e06
PA		 73#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
74#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
75#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
76#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
77#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
78#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 79
b44b2e06 80#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 81
b44b2e06 82enum adv76xx_type {
d42010a1
LPC		 83 ADV7604,
84 ADV7611,
85};
86
b44b2e06 87struct adv76xx_reg_seq {
d42010a1
LPC		 88 unsigned int reg;
89 u8 val;
90};
91
b44b2e06 92struct adv76xx_format_info {
f5fe58fd 93 u32 code;
539b33b0
LP		 94 u8 op_ch_sel;
95 bool rgb_out;
96 bool swap_cb_cr;
97 u8 op_format_sel;
98};
99
516613c1
HV		 100struct adv76xx_cfg_read_infoframe {
101 const char *desc;
102 u8 present_mask;
103 u8 head_addr;
104 u8 payload_addr;
105};
106
b44b2e06
PA		 107struct adv76xx_chip_info {
108 enum adv76xx_type type;
d42010a1
LPC		 109
110 bool has_afe;
111 unsigned int max_port;
112 unsigned int num_dv_ports;
113
114 unsigned int edid_enable_reg;
115 unsigned int edid_status_reg;
116 unsigned int lcf_reg;
117
118 unsigned int cable_det_mask;
119 unsigned int tdms_lock_mask;
120 unsigned int fmt_change_digital_mask;
80f4944e 121 unsigned int cp_csc;
d42010a1 122
b44b2e06 123 const struct adv76xx_format_info *formats;
539b33b0
LP		 124 unsigned int nformats;
125
d42010a1
LPC		 126 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
127 void (*setup_irqs)(struct v4l2_subdev *sd);
128 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
129 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
130
131 /* 0 = AFE, 1 = HDMI */
b44b2e06 132 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 133 unsigned int num_recommended_settings[2];
134
135 unsigned long page_mask;
5380baaf 136
137 /* Masks for timings */
138 unsigned int linewidth_mask;
139 unsigned int field0_height_mask;
140 unsigned int field1_height_mask;
141 unsigned int hfrontporch_mask;
142 unsigned int hsync_mask;
143 unsigned int hbackporch_mask;
144 unsigned int field0_vfrontporch_mask;
145 unsigned int field1_vfrontporch_mask;
146 unsigned int field0_vsync_mask;
147 unsigned int field1_vsync_mask;
148 unsigned int field0_vbackporch_mask;
149 unsigned int field1_vbackporch_mask;
d42010a1
LPC		 150};
151
54450f59
HV		 152/*
153 **********************************************************************
154 *
155 * Arrays with configuration parameters for the ADV7604
156 *
157 **********************************************************************
158 */
c784b1e2 159
b44b2e06
PA		 160struct adv76xx_state {
161 const struct adv76xx_chip_info *info;
162 struct adv76xx_platform_data pdata;
539b33b0 163
e9d50e9e
LP		 164 struct gpio_desc *hpd_gpio[4];
165
54450f59 166 struct v4l2_subdev sd;
b44b2e06 167 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 168 unsigned int source_pad;
539b33b0 169
54450f59 170 struct v4l2_ctrl_handler hdl;
539b33b0 171
b44b2e06 172 enum adv76xx_pad selected_input;
539b33b0 173
54450f59 174 struct v4l2_dv_timings timings;
b44b2e06 175 const struct adv76xx_format_info *format;
539b33b0 176
4a31a93a
MR		 177 struct {
178 u8 edid[256];
179 u32 present;
180 unsigned blocks;
181 } edid;
dd08beb9 182 u16 spa_port_a[2];
54450f59
HV		 183 struct v4l2_fract aspect_ratio;
184 u32 rgb_quantization_range;
185 struct workqueue_struct *work_queues;
186 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 187 bool restart_stdi_once;
54450f59
HV		 188
189 /* i2c clients */
b44b2e06 190 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59 191
f862f57d
PA		 192 /* Regmaps */
193 struct regmap *regmap[ADV76XX_PAGE_MAX];
194
54450f59
HV		 195 /* controls */
196 struct v4l2_ctrl *detect_tx_5v_ctrl;
197 struct v4l2_ctrl *analog_sampling_phase_ctrl;
198 struct v4l2_ctrl *free_run_color_manual_ctrl;
199 struct v4l2_ctrl *free_run_color_ctrl;
200 struct v4l2_ctrl *rgb_quantization_range_ctrl;
201};
202
b44b2e06 203static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 204{
205 return state->info->has_afe;
206}
207
54450f59 208/* Supported CEA and DMT timings */
b44b2e06 209static const struct v4l2_dv_timings adv76xx_timings[] = {
54450f59
HV		 210 V4L2_DV_BT_CEA_720X480P59_94,
211 V4L2_DV_BT_CEA_720X576P50,
212 V4L2_DV_BT_CEA_1280X720P24,
213 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 214 V4L2_DV_BT_CEA_1280X720P50,
215 V4L2_DV_BT_CEA_1280X720P60,
216 V4L2_DV_BT_CEA_1920X1080P24,
217 V4L2_DV_BT_CEA_1920X1080P25,
218 V4L2_DV_BT_CEA_1920X1080P30,
219 V4L2_DV_BT_CEA_1920X1080P50,
220 V4L2_DV_BT_CEA_1920X1080P60,
221
ccbd5bc4 222 /* sorted by DMT ID */
54450f59
HV		 223 V4L2_DV_BT_DMT_640X350P85,
224 V4L2_DV_BT_DMT_640X400P85,
225 V4L2_DV_BT_DMT_720X400P85,
226 V4L2_DV_BT_DMT_640X480P60,
227 V4L2_DV_BT_DMT_640X480P72,
228 V4L2_DV_BT_DMT_640X480P75,
229 V4L2_DV_BT_DMT_640X480P85,
230 V4L2_DV_BT_DMT_800X600P56,
231 V4L2_DV_BT_DMT_800X600P60,
232 V4L2_DV_BT_DMT_800X600P72,
233 V4L2_DV_BT_DMT_800X600P75,
234 V4L2_DV_BT_DMT_800X600P85,
235 V4L2_DV_BT_DMT_848X480P60,
236 V4L2_DV_BT_DMT_1024X768P60,
237 V4L2_DV_BT_DMT_1024X768P70,
238 V4L2_DV_BT_DMT_1024X768P75,
239 V4L2_DV_BT_DMT_1024X768P85,
240 V4L2_DV_BT_DMT_1152X864P75,
241 V4L2_DV_BT_DMT_1280X768P60_RB,
242 V4L2_DV_BT_DMT_1280X768P60,
243 V4L2_DV_BT_DMT_1280X768P75,
244 V4L2_DV_BT_DMT_1280X768P85,
245 V4L2_DV_BT_DMT_1280X800P60_RB,
246 V4L2_DV_BT_DMT_1280X800P60,
247 V4L2_DV_BT_DMT_1280X800P75,
248 V4L2_DV_BT_DMT_1280X800P85,
249 V4L2_DV_BT_DMT_1280X960P60,
250 V4L2_DV_BT_DMT_1280X960P85,
251 V4L2_DV_BT_DMT_1280X1024P60,
252 V4L2_DV_BT_DMT_1280X1024P75,
253 V4L2_DV_BT_DMT_1280X1024P85,
254 V4L2_DV_BT_DMT_1360X768P60,
255 V4L2_DV_BT_DMT_1400X1050P60_RB,
256 V4L2_DV_BT_DMT_1400X1050P60,
257 V4L2_DV_BT_DMT_1400X1050P75,
258 V4L2_DV_BT_DMT_1400X1050P85,
259 V4L2_DV_BT_DMT_1440X900P60_RB,
260 V4L2_DV_BT_DMT_1440X900P60,
261 V4L2_DV_BT_DMT_1600X1200P60,
262 V4L2_DV_BT_DMT_1680X1050P60_RB,
263 V4L2_DV_BT_DMT_1680X1050P60,
264 V4L2_DV_BT_DMT_1792X1344P60,
265 V4L2_DV_BT_DMT_1856X1392P60,
266 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 267 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 268 V4L2_DV_BT_DMT_1366X768P60,
269 V4L2_DV_BT_DMT_1920X1080P60,
270 { },
271};
272
b44b2e06 273struct adv76xx_video_standards {
ccbd5bc4
HV		 274 struct v4l2_dv_timings timings;
275 u8 vid_std;
276 u8 v_freq;
277};
278
279/* sorted by number of lines */
b44b2e06 280static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 281 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
282 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
283 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
284 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
285 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
286 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
287 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
288 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
289 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
290 /* TODO add 1920x1080P60_RB (CVT timing) */
291 { },
292};
293
294/* sorted by number of lines */
b44b2e06 295static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 296 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
297 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
298 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
299 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
300 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
301 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
302 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
303 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
304 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
305 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
306 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
307 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
308 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
309 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
310 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
311 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
312 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
313 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
314 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
315 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
316 /* TODO add 1600X1200P60_RB (not a DMT timing) */
317 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
318 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
319 { },
320};
321
322/* sorted by number of lines */
b44b2e06 323static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 324 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
325 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
326 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
327 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
328 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
329 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
330 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
331 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
332 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
333 { },
334};
335
336/* sorted by number of lines */
b44b2e06 337static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 338 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
339 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
340 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
341 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
342 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
343 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
344 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
345 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
346 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
347 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
348 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
349 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
350 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
351 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
352 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
353 { },
354};
355
48519838
HV		 356static const struct v4l2_event adv76xx_ev_fmt = {
357 .type = V4L2_EVENT_SOURCE_CHANGE,
358 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
359};
360
54450f59
HV		 361/* ----------------------------------------------------------------------- */
362
b44b2e06 363static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 364{
b44b2e06 365 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 366}
367
54450f59
HV		 368static inline unsigned htotal(const struct v4l2_bt_timings *t)
369{
eacf8f9a 370 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 371}
372
54450f59
HV		 373static inline unsigned vtotal(const struct v4l2_bt_timings *t)
374{
eacf8f9a 375 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 376}
377
378/* ----------------------------------------------------------------------- */
379
f862f57d
PA		 380static int adv76xx_read_check(struct adv76xx_state *state,
381 int client_page, u8 reg)
54450f59 382{
f862f57d 383 struct i2c_client *client = state->i2c_clients[client_page];
54450f59 384 int err;
f862f57d 385 unsigned int val;
54450f59 386
f862f57d
PA		 387 err = regmap_read(state->regmap[client_page], reg, &val);
388
389 if (err) {
390 v4l_err(client, "error reading %02x, %02x\n",
391 client->addr, reg);
392 return err;
54450f59 393 }
f862f57d 394 return val;
54450f59
HV		 395}
396
f862f57d
PA		 397/* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
398 * size to one or more registers.
399 *
400 * A value of zero will be returned on success, a negative errno will
401 * be returned in error cases.
402 */
403static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
404 unsigned int init_reg, const void *val,
405 size_t val_len)
54450f59 406{
f862f57d
PA		 407 struct regmap *regmap = state->regmap[client_page];
408
409 if (val_len > I2C_SMBUS_BLOCK_MAX)
410 val_len = I2C_SMBUS_BLOCK_MAX;
54450f59 411
f862f57d 412 return regmap_raw_write(regmap, init_reg, val, val_len);
54450f59
HV		 413}
414
415/* ----------------------------------------------------------------------- */
416
417static inline int io_read(struct v4l2_subdev *sd, u8 reg)
418{
b44b2e06 419 struct adv76xx_state *state = to_state(sd);
54450f59 420
f862f57d 421 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 422}
423
424static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
425{
b44b2e06 426 struct adv76xx_state *state = to_state(sd);
54450f59 427
f862f57d 428 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
54450f59
HV		 429}
430
22d97e56 431static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 432{
22d97e56 433 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 434}
435
436static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
437{
b44b2e06 438 struct adv76xx_state *state = to_state(sd);
54450f59 439
f862f57d 440 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 441}
442
443static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
444{
b44b2e06 445 struct adv76xx_state *state = to_state(sd);
54450f59 446
f862f57d 447 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
54450f59
HV		 448}
449
450static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
451{
b44b2e06 452 struct adv76xx_state *state = to_state(sd);
54450f59 453
f862f57d 454 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 455}
456
457static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
458{
b44b2e06 459 struct adv76xx_state *state = to_state(sd);
54450f59 460
f862f57d 461 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
54450f59
HV		 462}
463
54450f59
HV		 464static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
465{
b44b2e06 466 struct adv76xx_state *state = to_state(sd);
54450f59 467
f862f57d 468 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 469}
470
471static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
472{
b44b2e06 473 struct adv76xx_state *state = to_state(sd);
54450f59 474
f862f57d 475 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
54450f59
HV		 476}
477
54450f59
HV		 478static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
479{
b44b2e06 480 struct adv76xx_state *state = to_state(sd);
54450f59 481
f862f57d 482 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 483}
484
485static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
486{
b44b2e06 487 struct adv76xx_state *state = to_state(sd);
54450f59 488
f862f57d 489 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
54450f59
HV		 490}
491
492static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
493{
b44b2e06 494 struct adv76xx_state *state = to_state(sd);
54450f59 495
f862f57d 496 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 497}
498
499static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
500{
b44b2e06 501 struct adv76xx_state *state = to_state(sd);
54450f59 502
f862f57d 503 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
54450f59
HV		 504}
505
22d97e56 506static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 507{
22d97e56 508 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 509}
510
511static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
512{
b44b2e06 513 struct adv76xx_state *state = to_state(sd);
54450f59 514
f862f57d 515 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 516}
517
518static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
519{
b44b2e06 520 struct adv76xx_state *state = to_state(sd);
54450f59 521
f862f57d 522 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
54450f59
HV		 523}
524
54450f59 525static inline int edid_write_block(struct v4l2_subdev *sd,
f862f57d 526 unsigned int total_len, const u8 *val)
54450f59 527{
b44b2e06 528 struct adv76xx_state *state = to_state(sd);
54450f59 529 int err = 0;
f862f57d
PA		 530 int i = 0;
531 int len = 0;
54450f59 532
f862f57d
PA		 533 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
534 __func__, total_len);
535
536 while (!err && i < total_len) {
537 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
538 I2C_SMBUS_BLOCK_MAX :
539 (total_len - i);
540
541 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
542 i, val + i, len);
543 i += len;
544 }
54450f59 545
dd08beb9
MR		 546 return err;
547}
54450f59 548
b44b2e06 549static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 550{
551 unsigned int i;
552
269bd132 553 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 554 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 555
b44b2e06 556 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 557}
558
b44b2e06 559static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 560{
561 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 562 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 563 delayed_work_enable_hotplug);
564 struct v4l2_subdev *sd = &state->sd;
54450f59 565
dd08beb9 566 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 567
b44b2e06 568 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 569}
570
571static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
572{
b44b2e06 573 struct adv76xx_state *state = to_state(sd);
54450f59 574
f862f57d 575 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 576}
577
51182a94
LP		 578static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
579{
580 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
581}
582
54450f59
HV		 583static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584{
b44b2e06 585 struct adv76xx_state *state = to_state(sd);
54450f59 586
f862f57d 587 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
54450f59
HV		 588}
589
22d97e56 590static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 591{
22d97e56 592 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 593}
594
54450f59
HV		 595static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
596{
b44b2e06 597 struct adv76xx_state *state = to_state(sd);
54450f59 598
f862f57d 599 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
54450f59
HV		 600}
601
602static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
603{
b44b2e06 604 struct adv76xx_state *state = to_state(sd);
54450f59 605
f862f57d 606 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 607}
608
51182a94
LP		 609static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
610{
611 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
612}
613
54450f59
HV		 614static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
615{
b44b2e06 616 struct adv76xx_state *state = to_state(sd);
54450f59 617
f862f57d 618 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
54450f59
HV		 619}
620
22d97e56 621static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 622{
22d97e56 623 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 624}
625
626static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
627{
b44b2e06 628 struct adv76xx_state *state = to_state(sd);
54450f59 629
f862f57d 630 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 631}
632
633static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
634{
b44b2e06 635 struct adv76xx_state *state = to_state(sd);
54450f59 636
f862f57d 637 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
05cacb17 638}
d42010a1 639
b44b2e06
PA		 640#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
641#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 642
643#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 644static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 645{
b44b2e06 646 struct adv76xx_state *state = to_state(sd);
d42010a1 647 unsigned int page = reg >> 8;
f862f57d
PA		 648 unsigned int val;
649 int err;
d42010a1
LPC		 650
651 if (!(BIT(page) & state->info->page_mask))
652 return -EINVAL;
653
654 reg &= 0xff;
f862f57d 655 err = regmap_read(state->regmap[page], reg, &val);
d42010a1 656
f862f57d 657 return err ? err : val;
d42010a1
LPC		 658}
659#endif
660
b44b2e06 661static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 662{
b44b2e06 663 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 664 unsigned int page = reg >> 8;
665
666 if (!(BIT(page) & state->info->page_mask))
667 return -EINVAL;
668
669 reg &= 0xff;
670
f862f57d 671 return regmap_write(state->regmap[page], reg, val);
d42010a1
LPC		 672}
673
b44b2e06
PA		 674static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
675 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 676{
677 unsigned int i;
678
b44b2e06
PA		 679 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
680 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 681}
682
539b33b0
LP		 683/* -----------------------------------------------------------------------------
684 * Format helpers
685 */
686
b44b2e06
PA		 687static const struct adv76xx_format_info adv7604_formats[] = {
688 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
689 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
690 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
691 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
692 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
693 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
694 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
695 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
696 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
697 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
698 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
699 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
700 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
701 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
704 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
705 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
706 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
707 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
708 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
709 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
710 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
711 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
712 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
713 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
714 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
715 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
716 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
717 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
718 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
719 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
720 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
722 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
724 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 726};
727
b44b2e06
PA		 728static const struct adv76xx_format_info adv7611_formats[] = {
729 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
730 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
731 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
732 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
733 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
734 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
735 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
736 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
737 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
738 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
739 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
740 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
741 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
742 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
743 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
744 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
745 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
746 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
747 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
748 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
749 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
750 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
751 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
752 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
753 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
754 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 755};
756
b44b2e06
PA		 757static const struct adv76xx_format_info *
758adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 759{
760 unsigned int i;
761
762 for (i = 0; i < state->info->nformats; ++i) {
763 if (state->info->formats[i].code == code)
764 return &state->info->formats[i];
765 }
766
767 return NULL;
768}
769
54450f59
HV		 770/* ----------------------------------------------------------------------- */
771
4a31a93a
MR		 772static inline bool is_analog_input(struct v4l2_subdev *sd)
773{
b44b2e06 774 struct adv76xx_state *state = to_state(sd);
4a31a93a 775
c784b1e2
LP		 776 return state->selected_input == ADV7604_PAD_VGA_RGB ||
777 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 778}
779
780static inline bool is_digital_input(struct v4l2_subdev *sd)
781{
b44b2e06 782 struct adv76xx_state *state = to_state(sd);
4a31a93a 783
b44b2e06 784 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 785 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
786 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
787 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 788}
789
790/* ----------------------------------------------------------------------- */
791
54450f59 792#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 793static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 794{
795 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
796 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
797 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
798 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
799 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
800 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
801 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
802 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
803 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
804 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
805 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
806 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
807 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
808}
809
b44b2e06 810static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 811 struct v4l2_dbg_register *reg)
812{
d42010a1
LPC		 813 int ret;
814
b44b2e06 815 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 816 if (ret < 0) {
54450f59 817 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 818 adv76xx_inv_register(sd);
d42010a1 819 return ret;
54450f59 820 }
d42010a1
LPC		 821
822 reg->size = 1;
823 reg->val = ret;
824
54450f59
HV		 825 return 0;
826}
827
b44b2e06 828static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 829 const struct v4l2_dbg_register *reg)
54450f59 830{
d42010a1 831 int ret;
1577461b 832
b44b2e06 833 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 834 if (ret < 0) {
54450f59 835 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 836 adv76xx_inv_register(sd);
d42010a1 837 return ret;
54450f59 838 }
d42010a1 839
54450f59
HV		 840 return 0;
841}
842#endif
843
d42010a1
LPC		 844static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
845{
846 u8 value = io_read(sd, 0x6f);
847
848 return ((value & 0x10) >> 4)
849 | ((value & 0x08) >> 2)
850 | ((value & 0x04) << 0)
851 | ((value & 0x02) << 2);
852}
853
854static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
855{
856 u8 value = io_read(sd, 0x6f);
857
858 return value & 1;
859}
860
b44b2e06 861static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 862{
b44b2e06
PA		 863 struct adv76xx_state *state = to_state(sd);
864 const struct adv76xx_chip_info *info = state->info;
54450f59 865
54450f59 866 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 867 info->read_cable_det(sd));
54450f59
HV		 868}
869
ccbd5bc4
HV		 870static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
871 u8 prim_mode,
b44b2e06 872 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 873 const struct v4l2_dv_timings *timings)
874{
ccbd5bc4
HV		 875 int i;
876
877 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 878 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 879 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 880 continue;
881 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
882 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
883 prim_mode); /* v_freq and prim mode */
884 return 0;
885 }
886
887 return -1;
888}
889
890static int configure_predefined_video_timings(struct v4l2_subdev *sd,
891 struct v4l2_dv_timings *timings)
54450f59 892{
b44b2e06 893 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 894 int err;
895
896 v4l2_dbg(1, debug, sd, "%s", __func__);
897
b44b2e06 898 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 899 /* reset to default values */
900 io_write(sd, 0x16, 0x43);
901 io_write(sd, 0x17, 0x5a);
902 }
ccbd5bc4 903 /* disable embedded syncs for auto graphics mode */
22d97e56 904 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 905 cp_write(sd, 0x8f, 0x00);
906 cp_write(sd, 0x90, 0x00);
907 cp_write(sd, 0xa2, 0x00);
908 cp_write(sd, 0xa3, 0x00);
909 cp_write(sd, 0xa4, 0x00);
910 cp_write(sd, 0xa5, 0x00);
911 cp_write(sd, 0xa6, 0x00);
912 cp_write(sd, 0xa7, 0x00);
913 cp_write(sd, 0xab, 0x00);
914 cp_write(sd, 0xac, 0x00);
915
4a31a93a 916 if (is_analog_input(sd)) {
ccbd5bc4
HV		 917 err = find_and_set_predefined_video_timings(sd,
918 0x01, adv7604_prim_mode_comp, timings);
919 if (err)
920 err = find_and_set_predefined_video_timings(sd,
921 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 922 } else if (is_digital_input(sd)) {
ccbd5bc4 923 err = find_and_set_predefined_video_timings(sd,
b44b2e06 924 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 925 if (err)
926 err = find_and_set_predefined_video_timings(sd,
b44b2e06 927 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 928 } else {
929 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
930 __func__, state->selected_input);
ccbd5bc4 931 err = -1;
ccbd5bc4
HV		 932 }
933
934
935 return err;
936}
937
938static void configure_custom_video_timings(struct v4l2_subdev *sd,
939 const struct v4l2_bt_timings *bt)
940{
b44b2e06 941 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 942 u32 width = htotal(bt);
943 u32 height = vtotal(bt);
944 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
945 u16 cp_start_eav = width - bt->hfrontporch;
946 u16 cp_start_vbi = height - bt->vfrontporch;
947 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
948 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 949 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 950 const u8 pll[2] = {
951 0xc0 | ((width >> 8) & 0x1f),
952 width & 0xff
953 };
54450f59
HV		 954
955 v4l2_dbg(2, debug, sd, "%s\n", __func__);
956
4a31a93a 957 if (is_analog_input(sd)) {
ccbd5bc4
HV		 958 /* auto graphics */
959 io_write(sd, 0x00, 0x07); /* video std */
960 io_write(sd, 0x01, 0x02); /* prim mode */
961 /* enable embedded syncs for auto graphics mode */
22d97e56 962 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 963
ccbd5bc4 964 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 965 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
966 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
f862f57d
PA		 967 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
968 0x16, pll, 2))
54450f59 969 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 970
971 /* active video - horizontal timing */
54450f59 972 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 973 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 974 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 975 cp_write(sd, 0xa4, cp_start_eav & 0xff);
976
977 /* active video - vertical timing */
54450f59 978 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 979 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 980 ((cp_end_vbi >> 8) & 0xf));
54450f59 981 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 982 } else if (is_digital_input(sd)) {
ccbd5bc4 983 /* set default prim_mode/vid_std for HDMI
39c1cb2b 984 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 985 io_write(sd, 0x00, 0x02); /* video std */
986 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 987 } else {
988 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
989 __func__, state->selected_input);
54450f59 990 }
54450f59 991
ccbd5bc4
HV		 992 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
993 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
994 cp_write(sd, 0xab, (height >> 4) & 0xff);
995 cp_write(sd, 0xac, (height & 0x0f) << 4);
996}
54450f59 997
b44b2e06 998static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 999{
b44b2e06 1000 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1001 u8 offset_buf[4];
1002
1003 if (auto_offset) {
1004 offset_a = 0x3ff;
1005 offset_b = 0x3ff;
1006 offset_c = 0x3ff;
1007 }
1008
1009 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1010 __func__, auto_offset ? "Auto" : "Manual",
1011 offset_a, offset_b, offset_c);
1012
1013 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1014 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1015 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1016 offset_buf[3] = offset_c & 0x0ff;
1017
1018 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1019 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1020 0x77, offset_buf, 4))
5c6c6349
MR		 1021 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1022}
1023
b44b2e06 1024static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1025{
b44b2e06 1026 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1027 u8 gain_buf[4];
1028 u8 gain_man = 1;
1029 u8 agc_mode_man = 1;
1030
1031 if (auto_gain) {
1032 gain_man = 0;
1033 agc_mode_man = 0;
1034 gain_a = 0x100;
1035 gain_b = 0x100;
1036 gain_c = 0x100;
1037 }
1038
1039 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1040 __func__, auto_gain ? "Auto" : "Manual",
1041 gain_a, gain_b, gain_c);
1042
1043 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1044 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1045 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1046 gain_buf[3] = ((gain_c & 0x0ff));
1047
1048 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1049 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1050 0x73, gain_buf, 4))
5c6c6349
MR		 1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1052}
1053
54450f59
HV		 1054static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1055{
b44b2e06 1056 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1057 bool rgb_output = io_read(sd, 0x02) & 0x02;
1058 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1059
1060 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1061 __func__, state->rgb_quantization_range,
1062 rgb_output, hdmi_signal);
54450f59 1063
b44b2e06
PA		 1064 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1065 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1066
54450f59
HV		 1067 switch (state->rgb_quantization_range) {
1068 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1069 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1070 /* Receiving analog RGB signal
1071 * Set RGB full range (0-255) */
22d97e56 1072 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1073 break;
1074 }
1075
c784b1e2 1076 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1077 /* Receiving analog YPbPr signal
1078 * Set automode */
22d97e56 1079 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1080 break;
1081 }
1082
5c6c6349 1083 if (hdmi_signal) {
9833239e
MR		 1084 /* Receiving HDMI signal
1085 * Set automode */
22d97e56 1086 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1087 break;
1088 }
1089
1090 /* Receiving DVI-D signal
1091 * ADV7604 selects RGB limited range regardless of
1092 * input format (CE/IT) in automatic mode */
680fee04 1093 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
9833239e 1094 /* RGB limited range (16-235) */
22d97e56 1095 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1096 } else {
1097 /* RGB full range (0-255) */
22d97e56 1098 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1099
1100 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1101 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1102 } else {
b44b2e06
PA		 1103 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1104 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1105 }
54450f59
HV		 1106 }
1107 break;
1108 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1109 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1110 /* YCrCb limited range (16-235) */
22d97e56 1111 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1112 break;
d261e842 1113 }
5c6c6349
MR		 1114
1115 /* RGB limited range (16-235) */
22d97e56 1116 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1117
54450f59
HV		 1118 break;
1119 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1120 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1121 /* YCrCb full range (0-255) */
22d97e56 1122 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1123 break;
1124 }
1125
1126 /* RGB full range (0-255) */
22d97e56 1127 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1128
1129 if (is_analog_input(sd) || hdmi_signal)
1130 break;
1131
1132 /* Adjust gain/offset for DVI-D signals only */
1133 if (rgb_output) {
b44b2e06 1134 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1135 } else {
b44b2e06
PA		 1136 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1137 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1138 }
54450f59
HV		 1139 break;
1140 }
1141}
1142
b44b2e06 1143static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1144{
c269887c 1145 struct v4l2_subdev *sd =
b44b2e06 1146 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1147
b44b2e06 1148 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1149
1150 switch (ctrl->id) {
1151 case V4L2_CID_BRIGHTNESS:
1152 cp_write(sd, 0x3c, ctrl->val);
1153 return 0;
1154 case V4L2_CID_CONTRAST:
1155 cp_write(sd, 0x3a, ctrl->val);
1156 return 0;
1157 case V4L2_CID_SATURATION:
1158 cp_write(sd, 0x3b, ctrl->val);
1159 return 0;
1160 case V4L2_CID_HUE:
1161 cp_write(sd, 0x3d, ctrl->val);
1162 return 0;
1163 case V4L2_CID_DV_RX_RGB_RANGE:
1164 state->rgb_quantization_range = ctrl->val;
1165 set_rgb_quantization_range(sd);
1166 return 0;
1167 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1168 if (!adv76xx_has_afe(state))
d42010a1 1169 return -EINVAL;
54450f59
HV		 1170 /* Set the analog sampling phase. This is needed to find the
1171 best sampling phase for analog video: an application or
1172 driver has to try a number of phases and analyze the picture
1173 quality before settling on the best performing phase. */
1174 afe_write(sd, 0xc8, ctrl->val);
1175 return 0;
1176 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1177 /* Use the default blue color for free running mode,
1178 or supply your own. */
22d97e56 1179 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1180 return 0;
1181 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1182 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1183 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1184 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1185 return 0;
1186 }
1187 return -EINVAL;
1188}
1189
54450f59
HV		 1190/* ----------------------------------------------------------------------- */
1191
1192static inline bool no_power(struct v4l2_subdev *sd)
1193{
1194 /* Entire chip or CP powered off */
1195 return io_read(sd, 0x0c) & 0x24;
1196}
1197
1198static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1199{
b44b2e06 1200 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1201
1202 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1203}
1204
1205static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1206{
b44b2e06
PA		 1207 struct adv76xx_state *state = to_state(sd);
1208 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1209
1210 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1211}
1212
bb88f325
MB		 1213static inline bool is_hdmi(struct v4l2_subdev *sd)
1214{
1215 return hdmi_read(sd, 0x05) & 0x80;
1216}
1217
54450f59
HV		 1218static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1219{
b44b2e06 1220 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1221
1222 /*
1223 * Chips without a AFE don't expose registers for the SSPD, so just assume
1224 * that we have a lock.
1225 */
b44b2e06 1226 if (adv76xx_has_afe(state))
d42010a1
LPC		 1227 return false;
1228
54450f59
HV		 1229 /* TODO channel 2 */
1230 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1231}
1232
1233static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1234{
1235 /* TODO channel 2 */
1236 return !(cp_read(sd, 0xb1) & 0x80);
1237}
1238
1239static inline bool no_signal(struct v4l2_subdev *sd)
1240{
54450f59
HV		 1241 bool ret;
1242
1243 ret = no_power(sd);
1244
1245 ret |= no_lock_stdi(sd);
1246 ret |= no_lock_sspd(sd);
1247
4a31a93a 1248 if (is_digital_input(sd)) {
54450f59
HV		 1249 ret |= no_lock_tmds(sd);
1250 ret |= no_signal_tmds(sd);
1251 }
1252
1253 return ret;
1254}
1255
1256static inline bool no_lock_cp(struct v4l2_subdev *sd)
1257{
b44b2e06 1258 struct adv76xx_state *state = to_state(sd);
d42010a1 1259
b44b2e06 1260 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1261 return false;
1262
54450f59
HV		 1263 /* CP has detected a non standard number of lines on the incoming
1264 video compared to what it is configured to receive by s_dv_timings */
1265 return io_read(sd, 0x12) & 0x01;
1266}
1267
58514625 1268static inline bool in_free_run(struct v4l2_subdev *sd)
1269{
1270 return cp_read(sd, 0xff) & 0x10;
1271}
1272
b44b2e06 1273static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1274{
54450f59
HV		 1275 *status = 0;
1276 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1277 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1278 if (!in_free_run(sd) && no_lock_cp(sd))
1279 *status |= is_digital_input(sd) ?
1280 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1281
1282 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1283
1284 return 0;
1285}
1286
1287/* ----------------------------------------------------------------------- */
1288
54450f59
HV		 1289struct stdi_readback {
1290 u16 bl, lcf, lcvs;
1291 u8 hs_pol, vs_pol;
1292 bool interlaced;
1293};
1294
1295static int stdi2dv_timings(struct v4l2_subdev *sd,
1296 struct stdi_readback *stdi,
1297 struct v4l2_dv_timings *timings)
1298{
b44b2e06
PA		 1299 struct adv76xx_state *state = to_state(sd);
1300 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1301 u32 pix_clk;
1302 int i;
1303
b44b2e06
PA		 1304 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1305 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
54450f59 1306 continue;
b44b2e06 1307 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
54450f59
HV		 1308 continue;
1309
b44b2e06 1310 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
54450f59 1311
b44b2e06
PA		 1312 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1313 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1314 *timings = adv76xx_timings[i];
54450f59
HV		 1315 return 0;
1316 }
1317 }
1318
5fea1bb7 1319 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
54450f59
HV		 1320 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1321 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1322 false, timings))
54450f59
HV		 1323 return 0;
1324 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1325 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1326 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1327 false, state->aspect_ratio, timings))
54450f59
HV		 1328 return 0;
1329
ccbd5bc4
HV		 1330 v4l2_dbg(2, debug, sd,
1331 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1332 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1333 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1334 return -1;
1335}
1336
d42010a1 1337
54450f59
HV		 1338static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1339{
b44b2e06
PA		 1340 struct adv76xx_state *state = to_state(sd);
1341 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1342 u8 polarity;
1343
54450f59
HV		 1344 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1345 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1346 return -1;
1347 }
1348
1349 /* read STDI */
51182a94 1350 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1351 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1352 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1353 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1354
b44b2e06 1355 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1356 /* read SSPD */
1357 polarity = cp_read(sd, 0xb5);
1358 if ((polarity & 0x03) == 0x01) {
1359 stdi->hs_pol = polarity & 0x10
1360 ? (polarity & 0x08 ? '+' : '-') : 'x';
1361 stdi->vs_pol = polarity & 0x40
1362 ? (polarity & 0x20 ? '+' : '-') : 'x';
1363 } else {
1364 stdi->hs_pol = 'x';
1365 stdi->vs_pol = 'x';
1366 }
54450f59 1367 } else {
d42010a1
LPC		 1368 polarity = hdmi_read(sd, 0x05);
1369 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1370 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1371 }
1372
1373 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1374 v4l2_dbg(2, debug, sd,
1375 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1376 return -1;
1377 }
1378
1379 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1380 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1381 memset(stdi, 0, sizeof(struct stdi_readback));
1382 return -1;
1383 }
1384
1385 v4l2_dbg(2, debug, sd,
1386 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1387 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1388 stdi->hs_pol, stdi->vs_pol,
1389 stdi->interlaced ? "interlaced" : "progressive");
1390
1391 return 0;
1392}
1393
b44b2e06 1394static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1395 struct v4l2_enum_dv_timings *timings)
1396{
b44b2e06 1397 struct adv76xx_state *state = to_state(sd);
afec5599 1398
b44b2e06 1399 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
54450f59 1400 return -EINVAL;
afec5599
LP		 1401
1402 if (timings->pad >= state->source_pad)
1403 return -EINVAL;
1404
54450f59 1405 memset(timings->reserved, 0, sizeof(timings->reserved));
b44b2e06 1406 timings->timings = adv76xx_timings[timings->index];
54450f59
HV		 1407 return 0;
1408}
1409
b44b2e06 1410static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1411 struct v4l2_dv_timings_cap *cap)
54450f59 1412{
b44b2e06 1413 struct adv76xx_state *state = to_state(sd);
7515e096
LP		 1414
1415 if (cap->pad >= state->source_pad)
1416 return -EINVAL;
1417
54450f59
HV		 1418 cap->type = V4L2_DV_BT_656_1120;
1419 cap->bt.max_width = 1920;
1420 cap->bt.max_height = 1200;
fe9c2564 1421 cap->bt.min_pixelclock = 25000000;
afec5599 1422
7515e096 1423 switch (cap->pad) {
b44b2e06 1424 case ADV76XX_PAD_HDMI_PORT_A:
afec5599
LP		 1425 case ADV7604_PAD_HDMI_PORT_B:
1426 case ADV7604_PAD_HDMI_PORT_C:
1427 case ADV7604_PAD_HDMI_PORT_D:
54450f59 1428 cap->bt.max_pixelclock = 225000000;
afec5599
LP		 1429 break;
1430 case ADV7604_PAD_VGA_RGB:
1431 case ADV7604_PAD_VGA_COMP:
1432 default:
54450f59 1433 cap->bt.max_pixelclock = 170000000;
afec5599
LP		 1434 break;
1435 }
1436
54450f59
HV		 1437 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1438 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1439 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1440 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1441 return 0;
1442}
1443
1444/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1445 if the format is listed in adv76xx_timings[] */
1446static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1447 struct v4l2_dv_timings *timings)
1448{
54450f59
HV		 1449 int i;
1450
b44b2e06
PA		 1451 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1452 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
4a31a93a 1453 is_digital_input(sd) ? 250000 : 1000000)) {
b44b2e06 1454 *timings = adv76xx_timings[i];
54450f59
HV		 1455 break;
1456 }
1457 }
1458}
1459
d42010a1
LPC		 1460static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1461{
1462 unsigned int freq;
1463 int a, b;
1464
1465 a = hdmi_read(sd, 0x06);
1466 b = hdmi_read(sd, 0x3b);
1467 if (a < 0 || b < 0)
1468 return 0;
1469 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1470
1471 if (is_hdmi(sd)) {
1472 /* adjust for deep color mode */
1473 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1474
1475 freq = freq * 8 / bits_per_channel;
1476 }
1477
1478 return freq;
1479}
1480
1481static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1482{
1483 int a, b;
1484
1485 a = hdmi_read(sd, 0x51);
1486 b = hdmi_read(sd, 0x52);
1487 if (a < 0 || b < 0)
1488 return 0;
1489 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1490}
1491
b44b2e06 1492static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1493 struct v4l2_dv_timings *timings)
1494{
b44b2e06
PA		 1495 struct adv76xx_state *state = to_state(sd);
1496 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1497 struct v4l2_bt_timings *bt = &timings->bt;
1498 struct stdi_readback stdi;
1499
1500 if (!timings)
1501 return -EINVAL;
1502
1503 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1504
1505 if (no_signal(sd)) {
1e0b9156 1506 state->restart_stdi_once = true;
54450f59
HV		 1507 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1508 return -ENOLINK;
1509 }
1510
1511 /* read STDI */
1512 if (read_stdi(sd, &stdi)) {
1513 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1514 return -ENOLINK;
1515 }
1516 bt->interlaced = stdi.interlaced ?
1517 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1518
4a31a93a 1519 if (is_digital_input(sd)) {
54450f59
HV		 1520 timings->type = V4L2_DV_BT_656_1120;
1521
5380baaf 1522 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1523 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
d42010a1 1524 bt->pixelclock = info->read_hdmi_pixelclock(sd);
5380baaf 1525 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1526 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1527 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1528 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1529 info->field0_vfrontporch_mask) / 2;
1530 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1531 bt->vbackporch = hdmi_read16(sd, 0x32,
1532 info->field0_vbackporch_mask) / 2;
54450f59
HV		 1533 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1534 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1535 if (bt->interlaced == V4L2_DV_INTERLACED) {
5380baaf 1536 bt->height += hdmi_read16(sd, 0x0b,
1537 info->field1_height_mask);
1538 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1539 info->field1_vfrontporch_mask) / 2;
1540 bt->il_vsync = hdmi_read16(sd, 0x30,
1541 info->field1_vsync_mask) / 2;
1542 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1543 info->field1_vbackporch_mask) / 2;
54450f59 1544 }
b44b2e06 1545 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1546 } else {
1547 /* find format
80939647 1548 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1549 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1550 */
1551 if (!stdi2dv_timings(sd, &stdi, timings))
1552 goto found;
1553 stdi.lcvs += 1;
1554 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1555 if (!stdi2dv_timings(sd, &stdi, timings))
1556 goto found;
1557 stdi.lcvs -= 2;
1558 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1559 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1560 /*
1561 * The STDI block may measure wrong values, especially
1562 * for lcvs and lcf. If the driver can not find any
1563 * valid timing, the STDI block is restarted to measure
1564 * the video timings again. The function will return an
1565 * error, but the restart of STDI will generate a new
1566 * STDI interrupt and the format detection process will
1567 * restart.
1568 */
1569 if (state->restart_stdi_once) {
1570 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1571 /* TODO restart STDI for Sync Channel 2 */
1572 /* enter one-shot mode */
22d97e56 1573 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1574 /* trigger STDI restart */
22d97e56 1575 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1576 /* reset to continuous mode */
22d97e56 1577 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1578 state->restart_stdi_once = false;
1579 return -ENOLINK;
1580 }
54450f59
HV		 1581 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1582 return -ERANGE;
1583 }
cf9afb1d 1584 state->restart_stdi_once = true;
54450f59
HV		 1585 }
1586found:
1587
1588 if (no_signal(sd)) {
1589 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1590 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1591 return -ENOLINK;
1592 }
1593
4a31a93a
MR		 1594 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1595 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1596 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1597 __func__, (u32)bt->pixelclock);
1598 return -ERANGE;
1599 }
1600
1601 if (debug > 1)
b44b2e06 1602 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1603 timings, true);
54450f59
HV		 1604
1605 return 0;
1606}
1607
b44b2e06 1608static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1609 struct v4l2_dv_timings *timings)
1610{
b44b2e06 1611 struct adv76xx_state *state = to_state(sd);
54450f59 1612 struct v4l2_bt_timings *bt;
ccbd5bc4 1613 int err;
54450f59
HV		 1614
1615 if (!timings)
1616 return -EINVAL;
1617
d48eb48c
MR		 1618 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1619 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1620 return 0;
1621 }
1622
54450f59
HV		 1623 bt = &timings->bt;
1624
4a31a93a
MR		 1625 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1626 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1627 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1628 __func__, (u32)bt->pixelclock);
1629 return -ERANGE;
1630 }
ccbd5bc4 1631
b44b2e06 1632 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1633
1634 state->timings = *timings;
1635
22d97e56 1636 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1637
1638 /* Use prim_mode and vid_std when available */
1639 err = configure_predefined_video_timings(sd, timings);
1640 if (err) {
1641 /* custom settings when the video format
1642 does not have prim_mode/vid_std */
1643 configure_custom_video_timings(sd, bt);
1644 }
54450f59
HV		 1645
1646 set_rgb_quantization_range(sd);
1647
54450f59 1648 if (debug > 1)
b44b2e06 1649 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1650 timings, true);
54450f59
HV		 1651 return 0;
1652}
1653
b44b2e06 1654static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1655 struct v4l2_dv_timings *timings)
1656{
b44b2e06 1657 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1658
1659 *timings = state->timings;
1660 return 0;
1661}
1662
d42010a1
LPC		 1663static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1664{
1665 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1666}
1667
1668static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1669{
1670 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1671}
1672
6b0d5d34 1673static void enable_input(struct v4l2_subdev *sd)
54450f59 1674{
b44b2e06 1675 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1676
4a31a93a 1677 if (is_analog_input(sd)) {
54450f59 1678 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1679 } else if (is_digital_input(sd)) {
22d97e56 1680 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1681 state->info->set_termination(sd, true);
54450f59 1682 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1683 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1684 } else {
1685 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1686 __func__, state->selected_input);
54450f59
HV		 1687 }
1688}
1689
1690static void disable_input(struct v4l2_subdev *sd)
1691{
b44b2e06 1692 struct adv76xx_state *state = to_state(sd);
d42010a1 1693
22d97e56 1694 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1695 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1696 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1697 state->info->set_termination(sd, false);
54450f59
HV		 1698}
1699
6b0d5d34 1700static void select_input(struct v4l2_subdev *sd)
54450f59 1701{
b44b2e06
PA		 1702 struct adv76xx_state *state = to_state(sd);
1703 const struct adv76xx_chip_info *info = state->info;
54450f59 1704
4a31a93a 1705 if (is_analog_input(sd)) {
b44b2e06 1706 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1707
1708 afe_write(sd, 0x00, 0x08); /* power up ADC */
1709 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1710 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1711 } else if (is_digital_input(sd)) {
1712 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1713
b44b2e06 1714 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1715
b44b2e06 1716 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1717 afe_write(sd, 0x00, 0xff); /* power down ADC */
1718 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1719 afe_write(sd, 0xc8, 0x40); /* phase control */
1720 }
1721
54450f59
HV		 1722 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1723 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1724 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1725 } else {
1726 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1727 __func__, state->selected_input);
54450f59
HV		 1728 }
1729}
1730
b44b2e06 1731static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1732 u32 input, u32 output, u32 config)
1733{
b44b2e06 1734 struct adv76xx_state *state = to_state(sd);
54450f59 1735
ff4f80fd
MR		 1736 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1737 __func__, input, state->selected_input);
1738
1739 if (input == state->selected_input)
1740 return 0;
54450f59 1741
d42010a1
LPC		 1742 if (input > state->info->max_port)
1743 return -EINVAL;
1744
4a31a93a 1745 state->selected_input = input;
54450f59
HV		 1746
1747 disable_input(sd);
6b0d5d34 1748 select_input(sd);
6b0d5d34 1749 enable_input(sd);
54450f59 1750
48519838
HV		 1751 v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT,
1752 (void *)&adv76xx_ev_fmt);
54450f59
HV		 1753 return 0;
1754}
1755
b44b2e06 1756static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1757 struct v4l2_subdev_pad_config *cfg,
539b33b0 1758 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1759{
b44b2e06 1760 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1761
1762 if (code->index >= state->info->nformats)
54450f59 1763 return -EINVAL;
539b33b0
LP		 1764
1765 code->code = state->info->formats[code->index].code;
1766
54450f59
HV		 1767 return 0;
1768}
1769
b44b2e06 1770static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1771 struct v4l2_mbus_framefmt *format)
54450f59 1772{
539b33b0 1773 memset(format, 0, sizeof(*format));
54450f59 1774
539b33b0
LP		 1775 format->width = state->timings.bt.width;
1776 format->height = state->timings.bt.height;
1777 format->field = V4L2_FIELD_NONE;
680fee04 1778 format->colorspace = V4L2_COLORSPACE_SRGB;
539b33b0 1779
680fee04 1780 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
539b33b0 1781 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1782 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1783}
1784
1785/*
1786 * Compute the op_ch_sel value required to obtain on the bus the component order
1787 * corresponding to the selected format taking into account bus reordering
1788 * applied by the board at the output of the device.
1789 *
1790 * The following table gives the op_ch_value from the format component order
1791 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1792 * adv76xx_bus_order value in row).
539b33b0
LP		 1793 *
1794 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1795 * ----------+-------------------------------------------------
1796 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1797 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1798 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1799 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1800 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1801 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1802 */
b44b2e06 1803static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1804{
1805#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1806 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1807 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1808#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1809
1810 static const unsigned int op_ch_sel[6][6] = {
1811 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1812 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1813 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1814 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1815 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1816 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1817 };
1818
1819 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1820}
1821
b44b2e06 1822static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1823{
1824 struct v4l2_subdev *sd = &state->sd;
1825
22d97e56 1826 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1827 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1828 io_write(sd, 0x03, state->format->op_format_sel |
1829 state->pdata.op_format_mode_sel);
b44b2e06 1830 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1831 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1832 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1833}
1834
f7234138
HV		 1835static int adv76xx_get_format(struct v4l2_subdev *sd,
1836 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1837 struct v4l2_subdev_format *format)
1838{
b44b2e06 1839 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1840
1841 if (format->pad != state->source_pad)
1842 return -EINVAL;
1843
b44b2e06 1844 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1845
1846 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1847 struct v4l2_mbus_framefmt *fmt;
1848
f7234138 1849 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1850 format->format.code = fmt->code;
1851 } else {
1852 format->format.code = state->format->code;
54450f59 1853 }
539b33b0
LP		 1854
1855 return 0;
1856}
1857
f7234138
HV		 1858static int adv76xx_set_format(struct v4l2_subdev *sd,
1859 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1860 struct v4l2_subdev_format *format)
1861{
b44b2e06
PA		 1862 struct adv76xx_state *state = to_state(sd);
1863 const struct adv76xx_format_info *info;
539b33b0
LP		 1864
1865 if (format->pad != state->source_pad)
1866 return -EINVAL;
1867
b44b2e06 1868 info = adv76xx_format_info(state, format->format.code);
539b33b0 1869 if (info == NULL)
b44b2e06 1870 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1871
b44b2e06 1872 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1873 format->format.code = info->code;
1874
1875 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1876 struct v4l2_mbus_framefmt *fmt;
1877
f7234138 1878 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1879 fmt->code = format->format.code;
1880 } else {
1881 state->format = info;
b44b2e06 1882 adv76xx_setup_format(state);
539b33b0
LP		 1883 }
1884
54450f59
HV		 1885 return 0;
1886}
1887
b44b2e06 1888static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1889{
b44b2e06
PA		 1890 struct adv76xx_state *state = to_state(sd);
1891 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1892 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1893 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1894 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1895 u8 fmt_change_digital;
1896 u8 fmt_change;
1897 u8 tx_5v;
1898
1899 if (irq_reg_0x43)
1900 io_write(sd, 0x44, irq_reg_0x43);
1901 if (irq_reg_0x70)
1902 io_write(sd, 0x71, irq_reg_0x70);
1903 if (irq_reg_0x6b)
1904 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1905
ff4f80fd
MR		 1906 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1907
54450f59 1908 /* format change */
f24d229c 1909 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1910 fmt_change_digital = is_digital_input(sd)
1911 ? irq_reg_0x6b & info->fmt_change_digital_mask
1912 : 0;
14d03233 1913
54450f59
HV		 1914 if (fmt_change || fmt_change_digital) {
1915 v4l2_dbg(1, debug, sd,
25a64ac9 1916 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1917 __func__, fmt_change, fmt_change_digital);
25a64ac9 1918
48519838
HV		 1919 v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT,
1920 (void *)&adv76xx_ev_fmt);
25a64ac9 1921
54450f59
HV		 1922 if (handled)
1923 *handled = true;
1924 }
f24d229c
MR		 1925 /* HDMI/DVI mode */
1926 if (irq_reg_0x6b & 0x01) {
1927 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1928 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1929 set_rgb_quantization_range(sd);
1930 if (handled)
1931 *handled = true;
1932 }
1933
54450f59 1934 /* tx 5v detect */
d42010a1 1935 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
54450f59
HV		 1936 if (tx_5v) {
1937 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1938 io_write(sd, 0x71, tx_5v);
b44b2e06 1939 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1940 if (handled)
1941 *handled = true;
1942 }
1943 return 0;
1944}
1945
b44b2e06 1946static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1947{
b44b2e06 1948 struct adv76xx_state *state = to_state(sd);
4a31a93a 1949 u8 *data = NULL;
54450f59 1950
dd9ac11a 1951 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1952
1953 switch (edid->pad) {
b44b2e06 1954 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1955 case ADV7604_PAD_HDMI_PORT_B:
1956 case ADV7604_PAD_HDMI_PORT_C:
1957 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1958 if (state->edid.present & (1 << edid->pad))
1959 data = state->edid.edid;
1960 break;
1961 default:
1962 return -EINVAL;
4a31a93a 1963 }
dd9ac11a
HV		 1964
1965 if (edid->start_block == 0 && edid->blocks == 0) {
1966 edid->blocks = data ? state->edid.blocks : 0;
1967 return 0;
1968 }
1969
1970 if (data == NULL)
4a31a93a
MR		 1971 return -ENODATA;
1972
dd9ac11a
HV		 1973 if (edid->start_block >= state->edid.blocks)
1974 return -EINVAL;
1975
1976 if (edid->start_block + edid->blocks > state->edid.blocks)
1977 edid->blocks = state->edid.blocks - edid->start_block;
1978
1979 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1980
54450f59
HV		 1981 return 0;
1982}
1983
dd08beb9 1984static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1985{
1986 u8 d;
1987
1988 if ((edid[0x7e] != 1) ||
1989 (edid[0x80] != 0x02) ||
1990 (edid[0x81] != 0x03)) {
1991 return -1;
1992 }
1993
1994 /* search Vendor Specific Data Block (tag 3) */
1995 d = edid[0x82] & 0x7f;
1996 if (d > 4) {
1997 int i = 0x84;
1998 int end = 0x80 + d;
1999
2000 do {
2001 u8 tag = edid[i] >> 5;
2002 u8 len = edid[i] & 0x1f;
2003
2004 if ((tag == 3) && (len >= 5))
2005 return i + 4;
2006 i += len + 1;
2007 } while (i < end);
2008 }
2009 return -1;
2010}
2011
b44b2e06 2012static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 2013{
b44b2e06
PA		 2014 struct adv76xx_state *state = to_state(sd);
2015 const struct adv76xx_chip_info *info = state->info;
dd08beb9 2016 int spa_loc;
54450f59 2017 int err;
dd08beb9 2018 int i;
54450f59 2019
dd9ac11a
HV		 2020 memset(edid->reserved, 0, sizeof(edid->reserved));
2021
c784b1e2 2022 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2023 return -EINVAL;
2024 if (edid->start_block != 0)
2025 return -EINVAL;
2026 if (edid->blocks == 0) {
3e86aa85 2027 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2028 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2029 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2030 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2031
54450f59
HV		 2032 /* Fall back to a 16:9 aspect ratio */
2033 state->aspect_ratio.numerator = 16;
2034 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2035
2036 if (!state->edid.present)
2037 state->edid.blocks = 0;
2038
2039 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2040 __func__, edid->pad, state->edid.present);
54450f59
HV		 2041 return 0;
2042 }
4a31a93a
MR		 2043 if (edid->blocks > 2) {
2044 edid->blocks = 2;
54450f59 2045 return -E2BIG;
4a31a93a 2046 }
4a31a93a 2047
dd08beb9
MR		 2048 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2049 __func__, edid->pad, state->edid.present);
2050
3e86aa85 2051 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2052 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2053 adv76xx_set_hpd(state, 0);
22d97e56 2054 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2055
dd08beb9
MR		 2056 spa_loc = get_edid_spa_location(edid->edid);
2057 if (spa_loc < 0)
2058 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2059
3e86aa85 2060 switch (edid->pad) {
b44b2e06 2061 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2062 state->spa_port_a[0] = edid->edid[spa_loc];
2063 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2064 break;
c784b1e2 2065 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2066 rep_write(sd, 0x70, edid->edid[spa_loc]);
2067 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2068 break;
c784b1e2 2069 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2070 rep_write(sd, 0x72, edid->edid[spa_loc]);
2071 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2072 break;
c784b1e2 2073 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2074 rep_write(sd, 0x74, edid->edid[spa_loc]);
2075 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2076 break;
dd08beb9
MR		 2077 default:
2078 return -EINVAL;
3e86aa85 2079 }
d42010a1
LPC		 2080
2081 if (info->type == ADV7604) {
2082 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2083 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2084 } else {
2085 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2086 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2087 }
3e86aa85 2088
dd08beb9
MR		 2089 edid->edid[spa_loc] = state->spa_port_a[0];
2090 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2091
2092 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2093 state->edid.blocks = edid->blocks;
54450f59
HV		 2094 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2095 edid->edid[0x16]);
3e86aa85 2096 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2097
2098 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2099 if (err < 0) {
3e86aa85 2100 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2101 return err;
2102 }
2103
b44b2e06 2104 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2105 EDID RAM from DDC port. */
22d97e56 2106 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2107
2108 for (i = 0; i < 1000; i++) {
d42010a1 2109 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2110 break;
2111 mdelay(1);
2112 }
2113 if (i == 1000) {
2114 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2115 return -EIO;
2116 }
2117
4a31a93a
MR		 2118 /* enable hotplug after 100 ms */
2119 queue_delayed_work(state->work_queues,
2120 &state->delayed_work_enable_hotplug, HZ / 10);
2121 return 0;
54450f59
HV		 2122}
2123
2124/*********** avi info frame CEA-861-E **************/
2125
516613c1
HV		 2126static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2127 { "AVI", 0x01, 0xe0, 0x00 },
2128 { "Audio", 0x02, 0xe3, 0x1c },
2129 { "SDP", 0x04, 0xe6, 0x2a },
2130 { "Vendor", 0x10, 0xec, 0x54 }
2131};
2132
2133static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2134 union hdmi_infoframe *frame)
54450f59 2135{
516613c1
HV		 2136 uint8_t buffer[32];
2137 u8 len;
54450f59 2138 int i;
54450f59 2139
516613c1
HV		 2140 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2141 v4l2_info(sd, "%s infoframe not received\n",
2142 adv76xx_cri[index].desc);
2143 return -ENOENT;
54450f59 2144 }
516613c1
HV		 2145
2146 for (i = 0; i < 3; i++)
2147 buffer[i] = infoframe_read(sd,
2148 adv76xx_cri[index].head_addr + i);
2149
2150 len = buffer[2] + 1;
2151
2152 if (len + 3 > sizeof(buffer)) {
2153 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2154 adv76xx_cri[index].desc, len);
2155 return -ENOENT;
54450f59
HV		 2156 }
2157
516613c1
HV		 2158 for (i = 0; i < len; i++)
2159 buffer[i + 3] = infoframe_read(sd,
2160 adv76xx_cri[index].payload_addr + i);
2161
2162 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2163 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2164 adv76xx_cri[index].desc);
2165 return -ENOENT;
54450f59 2166 }
516613c1
HV		 2167 return 0;
2168}
54450f59 2169
516613c1
HV		 2170static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2171{
2172 int i;
54450f59 2173
516613c1
HV		 2174 if (!is_hdmi(sd)) {
2175 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
54450f59 2176 return;
516613c1 2177 }
54450f59 2178
516613c1
HV		 2179 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2180 union hdmi_infoframe frame;
2181 struct i2c_client *client = v4l2_get_subdevdata(sd);
54450f59 2182
516613c1
HV		 2183 if (adv76xx_read_infoframe(sd, i, &frame))
2184 return;
2185 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2186 }
54450f59
HV		 2187}
2188
b44b2e06 2189static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2190{
b44b2e06
PA		 2191 struct adv76xx_state *state = to_state(sd);
2192 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2193 struct v4l2_dv_timings timings;
2194 struct stdi_readback stdi;
2195 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2196 u8 edid_enabled;
2197 u8 cable_det;
54450f59 2198
f216ccb3 2199 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2200 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2201 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2202 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2203 "reserved", "reserved", "reserved", "reserved", "manual"
2204 };
f216ccb3 2205 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2206 "RGB limited range (16-235)", "RGB full range (0-255)",
2207 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2208 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2209 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2210 "invalid", "invalid", "invalid", "invalid", "invalid",
2211 "invalid", "invalid", "automatic"
2212 };
7a5d99e7
HV		 2213 static const char * const hdmi_color_space_txt[16] = {
2214 "RGB limited range (16-235)", "RGB full range (0-255)",
2215 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2216 "xvYCC Bt.601", "xvYCC Bt.709",
2217 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2218 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2219 "invalid", "invalid", "invalid"
2220 };
f216ccb3 2221 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2222 "Automatic",
2223 "RGB limited range (16-235)",
2224 "RGB full range (0-255)",
2225 };
f216ccb3 2226 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2227 "8-bits per channel",
2228 "10-bits per channel",
2229 "12-bits per channel",
2230 "16-bits per channel (not supported)"
2231 };
54450f59
HV		 2232
2233 v4l2_info(sd, "-----Chip status-----\n");
2234 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2235 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2236 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2237 ((edid_enabled & 0x01) ? "Yes" : "No"),
2238 ((edid_enabled & 0x02) ? "Yes" : "No"),
2239 ((edid_enabled & 0x04) ? "Yes" : "No"),
2240 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2241 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2242 "enabled" : "disabled");
2243
2244 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2245 cable_det = info->read_cable_det(sd);
4a31a93a 2246 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2247 ((cable_det & 0x01) ? "Yes" : "No"),
2248 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2249 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2250 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2251 v4l2_info(sd, "TMDS signal detected: %s\n",
2252 no_signal_tmds(sd) ? "false" : "true");
2253 v4l2_info(sd, "TMDS signal locked: %s\n",
2254 no_lock_tmds(sd) ? "false" : "true");
2255 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2256 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2257 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2258 v4l2_info(sd, "CP free run: %s\n",
58514625 2259 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2260 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2261 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2262 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2263
2264 v4l2_info(sd, "-----Video Timings-----\n");
2265 if (read_stdi(sd, &stdi))
2266 v4l2_info(sd, "STDI: not locked\n");
2267 else
2268 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2269 stdi.lcf, stdi.bl, stdi.lcvs,
2270 stdi.interlaced ? "interlaced" : "progressive",
2271 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2272 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2273 v4l2_info(sd, "No video detected\n");
2274 else
11d034c8
HV		 2275 v4l2_print_dv_timings(sd->name, "Detected format: ",
2276 &timings, true);
2277 v4l2_print_dv_timings(sd->name, "Configured format: ",
2278 &state->timings, true);
54450f59 2279
76eb2d30
MR		 2280 if (no_signal(sd))
2281 return 0;
2282
54450f59
HV		 2283 v4l2_info(sd, "-----Color space-----\n");
2284 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2285 rgb_quantization_range_txt[state->rgb_quantization_range]);
2286 v4l2_info(sd, "Input color space: %s\n",
2287 input_color_space_txt[reg_io_0x02 >> 4]);
7a5d99e7 2288 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n",
54450f59
HV		 2289 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2290 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
5dd7d88a 2291 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
7a5d99e7
HV		 2292 "enabled" : "disabled",
2293 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
54450f59 2294 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2295 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2296
4a31a93a 2297 if (!is_digital_input(sd))
76eb2d30
MR		 2298 return 0;
2299
2300 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2301 v4l2_info(sd, "Digital video port selected: %c\n",
2302 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2303 v4l2_info(sd, "HDCP encrypted content: %s\n",
2304 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2305 v4l2_info(sd, "HDCP keys read: %s%s\n",
2306 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2307 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2308 if (is_hdmi(sd)) {
76eb2d30
MR		 2309 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2310 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2311 bool audio_mute = io_read(sd, 0x65) & 0x40;
2312
2313 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2314 audio_pll_locked ? "locked" : "not locked",
2315 audio_sample_packet_detect ? "detected" : "not detected",
2316 audio_mute ? "muted" : "enabled");
2317 if (audio_pll_locked && audio_sample_packet_detect) {
2318 v4l2_info(sd, "Audio format: %s\n",
2319 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2320 }
2321 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2322 (hdmi_read(sd, 0x5c) << 8) +
2323 (hdmi_read(sd, 0x5d) & 0xf0));
2324 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2325 (hdmi_read(sd, 0x5e) << 8) +
2326 hdmi_read(sd, 0x5f));
2327 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2328
2329 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
7a5d99e7 2330 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
76eb2d30 2331
516613c1 2332 adv76xx_log_infoframes(sd);
54450f59
HV		 2333 }
2334
2335 return 0;
2336}
2337
2338/* ----------------------------------------------------------------------- */
2339
b44b2e06
PA		 2340static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2341 .s_ctrl = adv76xx_s_ctrl,
54450f59
HV		 2342};
2343
b44b2e06
PA		 2344static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2345 .log_status = adv76xx_log_status,
2346 .interrupt_service_routine = adv76xx_isr,
54450f59 2347#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2348 .g_register = adv76xx_g_register,
2349 .s_register = adv76xx_s_register,
54450f59
HV		 2350#endif
2351};
2352
b44b2e06
PA		 2353static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2354 .s_routing = adv76xx_s_routing,
2355 .g_input_status = adv76xx_g_input_status,
2356 .s_dv_timings = adv76xx_s_dv_timings,
2357 .g_dv_timings = adv76xx_g_dv_timings,
2358 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2359};
2360
b44b2e06
PA		 2361static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2362 .enum_mbus_code = adv76xx_enum_mbus_code,
2363 .get_fmt = adv76xx_get_format,
2364 .set_fmt = adv76xx_set_format,
2365 .get_edid = adv76xx_get_edid,
2366 .set_edid = adv76xx_set_edid,
2367 .dv_timings_cap = adv76xx_dv_timings_cap,
2368 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2369};
2370
b44b2e06
PA		 2371static const struct v4l2_subdev_ops adv76xx_ops = {
2372 .core = &adv76xx_core_ops,
2373 .video = &adv76xx_video_ops,
2374 .pad = &adv76xx_pad_ops,
54450f59
HV		 2375};
2376
2377/* -------------------------- custom ctrls ---------------------------------- */
2378
2379static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2380 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2381 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2382 .name = "Analog Sampling Phase",
2383 .type = V4L2_CTRL_TYPE_INTEGER,
2384 .min = 0,
2385 .max = 0x1f,
2386 .step = 1,
2387 .def = 0,
2388};
2389
b44b2e06
PA		 2390static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2391 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2392 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2393 .name = "Free Running Color, Manual",
2394 .type = V4L2_CTRL_TYPE_BOOLEAN,
2395 .min = false,
2396 .max = true,
2397 .step = 1,
2398 .def = false,
2399};
2400
b44b2e06
PA		 2401static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2402 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2403 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2404 .name = "Free Running Color",
2405 .type = V4L2_CTRL_TYPE_INTEGER,
2406 .min = 0x0,
2407 .max = 0xffffff,
2408 .step = 0x1,
2409 .def = 0x0,
2410};
2411
2412/* ----------------------------------------------------------------------- */
2413
b44b2e06 2414static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2415{
b44b2e06
PA		 2416 struct adv76xx_state *state = to_state(sd);
2417 const struct adv76xx_chip_info *info = state->info;
2418 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2419
2420 hdmi_write(sd, 0x48,
2421 (pdata->disable_pwrdnb ? 0x80 : 0) |
2422 (pdata->disable_cable_det_rst ? 0x40 : 0));
2423
2424 disable_input(sd);
2425
5ef54b59
LP		 2426 if (pdata->default_input >= 0 &&
2427 pdata->default_input < state->source_pad) {
2428 state->selected_input = pdata->default_input;
2429 select_input(sd);
2430 enable_input(sd);
2431 }
2432
54450f59
HV		 2433 /* power */
2434 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2435 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2436 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2437
2438 /* video format */
22d97e56 2439 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2440 pdata->alt_gamma << 3 |
2441 pdata->op_656_range << 2 |
54450f59 2442 pdata->alt_data_sat << 0);
22d97e56 2443 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2444 pdata->insert_av_codes << 2 |
2445 pdata->replicate_av_codes << 1);
b44b2e06 2446 adv76xx_setup_format(state);
54450f59 2447
54450f59 2448 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2449
2450 /* VS, HS polarities */
1b5ab875
LP		 2451 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2452 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2453
2454 /* Adjust drive strength */
2455 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2456 pdata->dr_str_clk << 2 |
2457 pdata->dr_str_sync);
2458
54450f59
HV		 2459 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2460 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2461 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2462 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2463 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2464 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2465 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2466 for digital formats */
2467
5474b983 2468 /* HDMI audio */
22d97e56
LP		 2469 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2470 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2471 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2472
54450f59
HV		 2473 /* TODO from platform data */
2474 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2475
b44b2e06 2476 if (adv76xx_has_afe(state)) {
d42010a1 2477 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2478 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2479 }
54450f59 2480
54450f59 2481 /* interrupts */
d42010a1 2482 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2483 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2484 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2485 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2486 info->setup_irqs(sd);
54450f59
HV		 2487
2488 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2489}
2490
d42010a1
LPC		 2491static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2492{
2493 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2494}
2495
2496static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2497{
2498 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2499}
2500
b44b2e06 2501static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2502{
05cacb17
LP		 2503 unsigned int i;
2504
2505 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2506 if (state->i2c_clients[i])
2507 i2c_unregister_device(state->i2c_clients[i]);
2508 }
54450f59
HV		 2509}
2510
b44b2e06 2511static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2512 u8 addr, u8 io_reg)
2513{
2514 struct i2c_client *client = v4l2_get_subdevdata(sd);
2515
2516 if (addr)
2517 io_write(sd, io_reg, addr << 1);
2518 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2519}
2520
b44b2e06 2521static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2522 /* reset ADI recommended settings for HDMI: */
2523 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2529 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2530 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2531 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2532 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2533 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2534 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2535 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2536
2537 /* set ADI recommended settings for digitizer */
2538 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2539 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2540 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2541 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2542 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2543 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2544
b44b2e06 2545 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2546};
2547
b44b2e06 2548static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2549 /* set ADI recommended settings for HDMI: */
2550 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2551 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2552 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2553 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2554 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2555 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2556 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2557 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2558 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2559 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2560 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2561 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2562
2563 /* reset ADI recommended settings for digitizer */
2564 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2565 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2566 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2567
b44b2e06 2568 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2569};
2570
b44b2e06 2571static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2572 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2573 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2574 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2575 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2576 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2577 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2578 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2579 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2580 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2581 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2582 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2583 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2584
2585 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2586};
2587
b44b2e06 2588static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2589 [ADV7604] = {
2590 .type = ADV7604,
2591 .has_afe = true,
c784b1e2 2592 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2593 .num_dv_ports = 4,
2594 .edid_enable_reg = 0x77,
2595 .edid_status_reg = 0x7d,
2596 .lcf_reg = 0xb3,
2597 .tdms_lock_mask = 0xe0,
2598 .cable_det_mask = 0x1e,
2599 .fmt_change_digital_mask = 0xc1,
80f4944e 2600 .cp_csc = 0xfc,
539b33b0
LP		 2601 .formats = adv7604_formats,
2602 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2603 .set_termination = adv7604_set_termination,
2604 .setup_irqs = adv7604_setup_irqs,
2605 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2606 .read_cable_det = adv7604_read_cable_det,
2607 .recommended_settings = {
2608 [0] = adv7604_recommended_settings_afe,
2609 [1] = adv7604_recommended_settings_hdmi,
2610 },
2611 .num_recommended_settings = {
2612 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2613 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2614 },
b44b2e06
PA		 2615 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2616 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2617 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2618 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2619 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2620 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1 2621 BIT(ADV7604_PAGE_VDP),
5380baaf 2622 .linewidth_mask = 0xfff,
2623 .field0_height_mask = 0xfff,
2624 .field1_height_mask = 0xfff,
2625 .hfrontporch_mask = 0x3ff,
2626 .hsync_mask = 0x3ff,
2627 .hbackporch_mask = 0x3ff,
2628 .field0_vfrontporch_mask = 0x1fff,
2629 .field0_vsync_mask = 0x1fff,
2630 .field0_vbackporch_mask = 0x1fff,
2631 .field1_vfrontporch_mask = 0x1fff,
2632 .field1_vsync_mask = 0x1fff,
2633 .field1_vbackporch_mask = 0x1fff,
d42010a1
LPC		 2634 },
2635 [ADV7611] = {
2636 .type = ADV7611,
2637 .has_afe = false,
b44b2e06 2638 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2639 .num_dv_ports = 1,
2640 .edid_enable_reg = 0x74,
2641 .edid_status_reg = 0x76,
2642 .lcf_reg = 0xa3,
2643 .tdms_lock_mask = 0x43,
2644 .cable_det_mask = 0x01,
2645 .fmt_change_digital_mask = 0x03,
80f4944e 2646 .cp_csc = 0xf4,
539b33b0
LP		 2647 .formats = adv7611_formats,
2648 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2649 .set_termination = adv7611_set_termination,
2650 .setup_irqs = adv7611_setup_irqs,
2651 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2652 .read_cable_det = adv7611_read_cable_det,
2653 .recommended_settings = {
2654 [1] = adv7611_recommended_settings_hdmi,
2655 },
2656 .num_recommended_settings = {
2657 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2658 },
b44b2e06
PA		 2659 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2660 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2661 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2662 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
5380baaf 2663 .linewidth_mask = 0x1fff,
2664 .field0_height_mask = 0x1fff,
2665 .field1_height_mask = 0x1fff,
2666 .hfrontporch_mask = 0x1fff,
2667 .hsync_mask = 0x1fff,
2668 .hbackporch_mask = 0x1fff,
2669 .field0_vfrontporch_mask = 0x3fff,
2670 .field0_vsync_mask = 0x3fff,
2671 .field0_vbackporch_mask = 0x3fff,
2672 .field1_vfrontporch_mask = 0x3fff,
2673 .field1_vsync_mask = 0x3fff,
2674 .field1_vbackporch_mask = 0x3fff,
d42010a1
LPC		 2675 },
2676};
2677
7f099a75 2678static const struct i2c_device_id adv76xx_i2c_id[] = {
b44b2e06
PA		 2679 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2680 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
f82f313e
LP		 2681 { }
2682};
b44b2e06 2683MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2684
7f099a75 2685static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
b44b2e06 2686 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
f82f313e
LP		 2687 { }
2688};
b44b2e06 2689MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2690
b44b2e06 2691static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2692{
6fa88045
LP		 2693 struct v4l2_of_endpoint bus_cfg;
2694 struct device_node *endpoint;
2695 struct device_node *np;
2696 unsigned int flags;
2697
b44b2e06 2698 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2699
2700 /* Parse the endpoint. */
2701 endpoint = of_graph_get_next_endpoint(np, NULL);
2702 if (!endpoint)
2703 return -EINVAL;
2704
2705 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2706 of_node_put(endpoint);
2707
2708 flags = bus_cfg.bus.parallel.flags;
2709
2710 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2711 state->pdata.inv_hs_pol = 1;
2712
2713 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2714 state->pdata.inv_vs_pol = 1;
2715
2716 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2717 state->pdata.inv_llc_pol = 1;
2718
2719 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2720 state->pdata.insert_av_codes = 1;
2721 state->pdata.op_656_range = 1;
2722 }
2723
f82f313e 2724 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2725 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2726
2727 /* Use the default I2C addresses. */
2728 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2729 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2730 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2731 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2732 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2733 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2734 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2735 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2736 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2737 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2738 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2739 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2740
2741 /* Hardcode the remaining platform data fields. */
2742 state->pdata.disable_pwrdnb = 0;
2743 state->pdata.disable_cable_det_rst = 0;
2744 state->pdata.default_input = -1;
2745 state->pdata.blank_data = 1;
f82f313e 2746 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2747 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2748 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2749
2750 return 0;
2751}
2752
f862f57d
PA		 2753static const struct regmap_config adv76xx_regmap_cnf[] = {
2754 {
2755 .name = "io",
2756 .reg_bits = 8,
2757 .val_bits = 8,
2758
2759 .max_register = 0xff,
2760 .cache_type = REGCACHE_NONE,
2761 },
2762 {
2763 .name = "avlink",
2764 .reg_bits = 8,
2765 .val_bits = 8,
2766
2767 .max_register = 0xff,
2768 .cache_type = REGCACHE_NONE,
2769 },
2770 {
2771 .name = "cec",
2772 .reg_bits = 8,
2773 .val_bits = 8,
2774
2775 .max_register = 0xff,
2776 .cache_type = REGCACHE_NONE,
2777 },
2778 {
2779 .name = "infoframe",
2780 .reg_bits = 8,
2781 .val_bits = 8,
2782
2783 .max_register = 0xff,
2784 .cache_type = REGCACHE_NONE,
2785 },
2786 {
2787 .name = "esdp",
2788 .reg_bits = 8,
2789 .val_bits = 8,
2790
2791 .max_register = 0xff,
2792 .cache_type = REGCACHE_NONE,
2793 },
2794 {
2795 .name = "epp",
2796 .reg_bits = 8,
2797 .val_bits = 8,
2798
2799 .max_register = 0xff,
2800 .cache_type = REGCACHE_NONE,
2801 },
2802 {
2803 .name = "afe",
2804 .reg_bits = 8,
2805 .val_bits = 8,
2806
2807 .max_register = 0xff,
2808 .cache_type = REGCACHE_NONE,
2809 },
2810 {
2811 .name = "rep",
2812 .reg_bits = 8,
2813 .val_bits = 8,
2814
2815 .max_register = 0xff,
2816 .cache_type = REGCACHE_NONE,
2817 },
2818 {
2819 .name = "edid",
2820 .reg_bits = 8,
2821 .val_bits = 8,
2822
2823 .max_register = 0xff,
2824 .cache_type = REGCACHE_NONE,
2825 },
2826
2827 {
2828 .name = "hdmi",
2829 .reg_bits = 8,
2830 .val_bits = 8,
2831
2832 .max_register = 0xff,
2833 .cache_type = REGCACHE_NONE,
2834 },
2835 {
2836 .name = "test",
2837 .reg_bits = 8,
2838 .val_bits = 8,
2839
2840 .max_register = 0xff,
2841 .cache_type = REGCACHE_NONE,
2842 },
2843 {
2844 .name = "cp",
2845 .reg_bits = 8,
2846 .val_bits = 8,
2847
2848 .max_register = 0xff,
2849 .cache_type = REGCACHE_NONE,
2850 },
2851 {
2852 .name = "vdp",
2853 .reg_bits = 8,
2854 .val_bits = 8,
2855
2856 .max_register = 0xff,
2857 .cache_type = REGCACHE_NONE,
2858 },
2859};
2860
2861static int configure_regmap(struct adv76xx_state *state, int region)
2862{
2863 int err;
2864
2865 if (!state->i2c_clients[region])
2866 return -ENODEV;
2867
2868 state->regmap[region] =
2869 devm_regmap_init_i2c(state->i2c_clients[region],
2870 &adv76xx_regmap_cnf[region]);
2871
2872 if (IS_ERR(state->regmap[region])) {
2873 err = PTR_ERR(state->regmap[region]);
2874 v4l_err(state->i2c_clients[region],
2875 "Error initializing regmap %d with error %d\n",
2876 region, err);
2877 return -EINVAL;
2878 }
2879
2880 return 0;
2881}
2882
2883static int configure_regmaps(struct adv76xx_state *state)
2884{
2885 int i, err;
2886
2887 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
2888 err = configure_regmap(state, i);
2889 if (err && (err != -ENODEV))
2890 return err;
2891 }
2892 return 0;
2893}
2894
b44b2e06 2895static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 2896 const struct i2c_device_id *id)
2897{
591b72fe
HV		 2898 static const struct v4l2_dv_timings cea640x480 =
2899 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 2900 struct adv76xx_state *state;
54450f59
HV		 2901 struct v4l2_ctrl_handler *hdl;
2902 struct v4l2_subdev *sd;
c784b1e2 2903 unsigned int i;
f862f57d 2904 unsigned int val, val2;
54450f59
HV		 2905 int err;
2906
2907 /* Check if the adapter supports the needed features */
2908 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2909 return -EIO;
b44b2e06 2910 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 2911 client->addr << 1);
2912
c02b211d 2913 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 2914 if (!state) {
b44b2e06 2915 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 2916 return -ENOMEM;
2917 }
2918
b44b2e06 2919 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 2920
25a64ac9
MR		 2921 /* initialize variables */
2922 state->restart_stdi_once = true;
ff4f80fd 2923 state->selected_input = ~0;
25a64ac9 2924
f82f313e
LP		 2925 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2926 const struct of_device_id *oid;
2927
b44b2e06 2928 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 2929 state->info = oid->data;
2930
b44b2e06 2931 err = adv76xx_parse_dt(state);
f82f313e
LP		 2932 if (err < 0) {
2933 v4l_err(client, "DT parsing error\n");
2934 return err;
2935 }
2936 } else if (client->dev.platform_data) {
b44b2e06 2937 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 2938
b44b2e06 2939 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 2940 state->pdata = *pdata;
2941 } else {
54450f59 2942 v4l_err(client, "No platform data!\n");
c02b211d 2943 return -ENODEV;
54450f59 2944 }
e9d50e9e
LP		 2945
2946 /* Request GPIOs. */
2947 for (i = 0; i < state->info->num_dv_ports; ++i) {
2948 state->hpd_gpio[i] =
269bd132
UKK		 2949 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2950 GPIOD_OUT_LOW);
e9d50e9e 2951 if (IS_ERR(state->hpd_gpio[i]))
269bd132 2952 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 2953
269bd132
UKK		 2954 if (state->hpd_gpio[i])
2955 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e
LP		 2956 }
2957
591b72fe 2958 state->timings = cea640x480;
b44b2e06 2959 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 2960
2961 sd = &state->sd;
b44b2e06 2962 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 2963 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2964 id->name, i2c_adapter_id(client->adapter),
2965 client->addr);
54450f59 2966 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59 2967
f862f57d
PA		 2968 /* Configure IO Regmap region */
2969 err = configure_regmap(state, ADV76XX_PAGE_IO);
2970
2971 if (err) {
2972 v4l2_err(sd, "Error configuring IO regmap region\n");
2973 return -ENODEV;
2974 }
2975
d42010a1
LPC		 2976 /*
2977 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2978 * identifies the revision, while on ADV7611 it identifies the model as
2979 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2980 */
2981 if (state->info->type == ADV7604) {
f862f57d
PA		 2982 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
2983 if (err) {
2984 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
2985 return -ENODEV;
2986 }
d42010a1 2987 if (val != 0x68) {
f862f57d 2988 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
d42010a1
LPC		 2989 client->addr << 1);
2990 return -ENODEV;
2991 }
2992 } else {
f862f57d
PA		 2993 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
2994 0xea,
2995 &val);
2996 if (err) {
2997 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
2998 return -ENODEV;
2999 }
3000 val2 = val << 8;
3001 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3002 0xeb,
3003 &val);
3004 if (err) {
3005 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3006 return -ENODEV;
3007 }
3008 val2 |= val;
3009 if (val2 != 0x2051) {
3010 v4l2_err(sd, "not an adv7611 on address 0x%x\n",
d42010a1
LPC		 3011 client->addr << 1);
3012 return -ENODEV;
3013 }
54450f59
HV		 3014 }
3015
3016 /* control handlers */
3017 hdl = &state->hdl;
b44b2e06 3018 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 3019
b44b2e06 3020 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3021 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 3022 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3023 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 3024 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3025 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 3026 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3027 V4L2_CID_HUE, 0, 128, 1, 0);
3028
3029 /* private controls */
3030 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 3031 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3032 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 3033 state->rgb_quantization_range_ctrl =
b44b2e06 3034 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3035 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3036 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 3037
3038 /* custom controls */
b44b2e06 3039 if (adv76xx_has_afe(state))
d42010a1
LPC		 3040 state->analog_sampling_phase_ctrl =
3041 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 3042 state->free_run_color_manual_ctrl =
b44b2e06 3043 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 3044 state->free_run_color_ctrl =
b44b2e06 3045 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 3046
3047 sd->ctrl_handler = hdl;
3048 if (hdl->error) {
3049 err = hdl->error;
3050 goto err_hdl;
3051 }
8c0eadb8
HV		 3052 state->detect_tx_5v_ctrl->is_private = true;
3053 state->rgb_quantization_range_ctrl->is_private = true;
b44b2e06 3054 if (adv76xx_has_afe(state))
d42010a1 3055 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 3056 state->free_run_color_manual_ctrl->is_private = true;
3057 state->free_run_color_ctrl->is_private = true;
3058
b44b2e06 3059 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 3060 err = -ENODEV;
3061 goto err_hdl;
3062 }
3063
b44b2e06 3064 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 3065 if (!(BIT(i) & state->info->page_mask))
3066 continue;
54450f59 3067
05cacb17 3068 state->i2c_clients[i] =
b44b2e06 3069 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 3070 0xf2 + i);
3071 if (state->i2c_clients[i] == NULL) {
d42010a1 3072 err = -ENOMEM;
05cacb17 3073 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 3074 goto err_i2c;
3075 }
3076 }
05cacb17 3077
54450f59
HV		 3078 /* work queues */
3079 state->work_queues = create_singlethread_workqueue(client->name);
3080 if (!state->work_queues) {
3081 v4l2_err(sd, "Could not create work queue\n");
3082 err = -ENOMEM;
3083 goto err_i2c;
3084 }
3085
3086 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 3087 adv76xx_delayed_work_enable_hotplug);
54450f59 3088
c784b1e2
LP		 3089 state->source_pad = state->info->num_dv_ports
3090 + (state->info->has_afe ? 2 : 0);
3091 for (i = 0; i < state->source_pad; ++i)
3092 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3093 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3094
3095 err = media_entity_init(&sd->entity, state->source_pad + 1,
3096 state->pads, 0);
54450f59
HV		 3097 if (err)
3098 goto err_work_queues;
3099
f862f57d
PA		 3100 /* Configure regmaps */
3101 err = configure_regmaps(state);
3102 if (err)
3103 goto err_entity;
3104
b44b2e06 3105 err = adv76xx_core_init(sd);
54450f59
HV		 3106 if (err)
3107 goto err_entity;
3108 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3109 client->addr << 1, client->adapter->name);
bedc3939
LPC		 3110
3111 err = v4l2_async_register_subdev(sd);
3112 if (err)
3113 goto err_entity;
3114
54450f59
HV		 3115 return 0;
3116
3117err_entity:
3118 media_entity_cleanup(&sd->entity);
3119err_work_queues:
3120 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3121 destroy_workqueue(state->work_queues);
3122err_i2c:
b44b2e06 3123 adv76xx_unregister_clients(state);
54450f59
HV		 3124err_hdl:
3125 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 3126 return err;
3127}
3128
3129/* ----------------------------------------------------------------------- */
3130
b44b2e06 3131static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 3132{
3133 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 3134 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 3135
3136 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3137 destroy_workqueue(state->work_queues);
bedc3939 3138 v4l2_async_unregister_subdev(sd);
54450f59 3139 media_entity_cleanup(&sd->entity);
b44b2e06 3140 adv76xx_unregister_clients(to_state(sd));
54450f59 3141 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 3142 return 0;
3143}
3144
3145/* ----------------------------------------------------------------------- */
3146
b44b2e06 3147static struct i2c_driver adv76xx_driver = {
54450f59
HV		 3148 .driver = {
3149 .owner = THIS_MODULE,
3150 .name = "adv7604",
b44b2e06 3151 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 3152 },
b44b2e06
PA		 3153 .probe = adv76xx_probe,
3154 .remove = adv76xx_remove,
3155 .id_table = adv76xx_i2c_id,
54450f59
HV		 3156};
3157
b44b2e06 3158module_i2c_driver(adv76xx_driver);
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