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[media] adv7842: restart STDI once if format is not found
[mirror_ubuntu-bionic-kernel.git] / drivers / media / i2c / adv7842.c
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a89bcd4c
HV		 1/*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
5b64b205
MR		 23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
7de6fab1
MR		 25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
5b64b205
MR		 27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
a89bcd4c
HV		 30 */
31
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
36#include <linux/i2c.h>
37#include <linux/delay.h>
38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
40#include <linux/v4l2-dv-timings.h>
41#include <media/v4l2-device.h>
42#include <media/v4l2-ctrls.h>
43#include <media/v4l2-dv-timings.h>
44#include <media/adv7842.h>
45
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7842 system clock frequency */
56#define ADV7842_fsc (28636360)
57
58/*
59**********************************************************************
60*
61* Arrays with configuration parameters for the ADV7842
62*
63**********************************************************************
64*/
65
66struct adv7842_state {
7de5be44 67 struct adv7842_platform_data pdata;
a89bcd4c
HV		 68 struct v4l2_subdev sd;
69 struct media_pad pad;
70 struct v4l2_ctrl_handler hdl;
71 enum adv7842_mode mode;
72 struct v4l2_dv_timings timings;
73 enum adv7842_vid_std_select vid_std_select;
74 v4l2_std_id norm;
75 struct {
76 u8 edid[256];
77 u32 present;
78 } hdmi_edid;
79 struct {
80 u8 edid[256];
81 u32 present;
82 } vga_edid;
83 struct v4l2_fract aspect_ratio;
84 u32 rgb_quantization_range;
85 bool is_cea_format;
86 struct workqueue_struct *work_queues;
87 struct delayed_work delayed_work_enable_hotplug;
6e9071f2 88 bool restart_stdi_once;
a89bcd4c
HV		 89 bool hdmi_port_a;
90
91 /* i2c clients */
92 struct i2c_client *i2c_sdp_io;
93 struct i2c_client *i2c_sdp;
94 struct i2c_client *i2c_cp;
95 struct i2c_client *i2c_vdp;
96 struct i2c_client *i2c_afe;
97 struct i2c_client *i2c_hdmi;
98 struct i2c_client *i2c_repeater;
99 struct i2c_client *i2c_edid;
100 struct i2c_client *i2c_infoframe;
101 struct i2c_client *i2c_cec;
102 struct i2c_client *i2c_avlink;
103
104 /* controls */
105 struct v4l2_ctrl *detect_tx_5v_ctrl;
106 struct v4l2_ctrl *analog_sampling_phase_ctrl;
107 struct v4l2_ctrl *free_run_color_ctrl_manual;
108 struct v4l2_ctrl *free_run_color_ctrl;
109 struct v4l2_ctrl *rgb_quantization_range_ctrl;
110};
111
112/* Unsupported timings. This device cannot support 720p30. */
113static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
114 V4L2_DV_BT_CEA_1280X720P30,
115 { }
116};
117
118static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
119{
120 int i;
121
122 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
123 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
124 return false;
125 return true;
126}
127
128struct adv7842_video_standards {
129 struct v4l2_dv_timings timings;
130 u8 vid_std;
131 u8 v_freq;
132};
133
134/* sorted by number of lines */
135static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
136 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
137 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
138 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
139 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
140 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
141 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
142 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
143 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
144 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
145 /* TODO add 1920x1080P60_RB (CVT timing) */
146 { },
147};
148
149/* sorted by number of lines */
150static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
151 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
152 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
153 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
154 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
156 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
157 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
158 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
159 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
160 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
161 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
162 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
163 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
164 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
165 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
166 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
167 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
168 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
169 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
170 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
171 /* TODO add 1600X1200P60_RB (not a DMT timing) */
172 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
173 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
174 { },
175};
176
177/* sorted by number of lines */
178static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
179 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
180 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
181 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
182 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
183 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
184 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
185 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
186 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
187 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
188 { },
189};
190
191/* sorted by number of lines */
192static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
208 { },
209};
210
211/* ----------------------------------------------------------------------- */
212
213static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
214{
215 return container_of(sd, struct adv7842_state, sd);
216}
217
218static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
219{
220 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
221}
222
223static inline unsigned hblanking(const struct v4l2_bt_timings *t)
224{
225 return V4L2_DV_BT_BLANKING_WIDTH(t);
226}
227
228static inline unsigned htotal(const struct v4l2_bt_timings *t)
229{
230 return V4L2_DV_BT_FRAME_WIDTH(t);
231}
232
233static inline unsigned vblanking(const struct v4l2_bt_timings *t)
234{
235 return V4L2_DV_BT_BLANKING_HEIGHT(t);
236}
237
238static inline unsigned vtotal(const struct v4l2_bt_timings *t)
239{
240 return V4L2_DV_BT_FRAME_HEIGHT(t);
241}
242
243
244/* ----------------------------------------------------------------------- */
245
246static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
247 u8 command, bool check)
248{
249 union i2c_smbus_data data;
250
251 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
252 I2C_SMBUS_READ, command,
253 I2C_SMBUS_BYTE_DATA, &data))
254 return data.byte;
255 if (check)
256 v4l_err(client, "error reading %02x, %02x\n",
257 client->addr, command);
258 return -EIO;
259}
260
261static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
262{
263 int i;
264
265 for (i = 0; i < 3; i++) {
266 int ret = adv_smbus_read_byte_data_check(client, command, true);
267
268 if (ret >= 0) {
269 if (i)
270 v4l_err(client, "read ok after %d retries\n", i);
271 return ret;
272 }
273 }
274 v4l_err(client, "read failed\n");
275 return -EIO;
276}
277
278static s32 adv_smbus_write_byte_data(struct i2c_client *client,
279 u8 command, u8 value)
280{
281 union i2c_smbus_data data;
282 int err;
283 int i;
284
285 data.byte = value;
286 for (i = 0; i < 3; i++) {
287 err = i2c_smbus_xfer(client->adapter, client->addr,
288 client->flags,
289 I2C_SMBUS_WRITE, command,
290 I2C_SMBUS_BYTE_DATA, &data);
291 if (!err)
292 break;
293 }
294 if (err < 0)
295 v4l_err(client, "error writing %02x, %02x, %02x\n",
296 client->addr, command, value);
297 return err;
298}
299
300static void adv_smbus_write_byte_no_check(struct i2c_client *client,
301 u8 command, u8 value)
302{
303 union i2c_smbus_data data;
304 data.byte = value;
305
306 i2c_smbus_xfer(client->adapter, client->addr,
307 client->flags,
308 I2C_SMBUS_WRITE, command,
309 I2C_SMBUS_BYTE_DATA, &data);
310}
311
312static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
313 u8 command, unsigned length, const u8 *values)
314{
315 union i2c_smbus_data data;
316
317 if (length > I2C_SMBUS_BLOCK_MAX)
318 length = I2C_SMBUS_BLOCK_MAX;
319 data.block[0] = length;
320 memcpy(data.block + 1, values, length);
321 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
322 I2C_SMBUS_WRITE, command,
323 I2C_SMBUS_I2C_BLOCK_DATA, &data);
324}
325
326/* ----------------------------------------------------------------------- */
327
328static inline int io_read(struct v4l2_subdev *sd, u8 reg)
329{
330 struct i2c_client *client = v4l2_get_subdevdata(sd);
331
332 return adv_smbus_read_byte_data(client, reg);
333}
334
335static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
336{
337 struct i2c_client *client = v4l2_get_subdevdata(sd);
338
339 return adv_smbus_write_byte_data(client, reg, val);
340}
341
342static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
343{
344 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
345}
346
347static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
348{
349 struct adv7842_state *state = to_state(sd);
350
351 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
352}
353
354static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
355{
356 struct adv7842_state *state = to_state(sd);
357
358 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
359}
360
361static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
362{
363 struct adv7842_state *state = to_state(sd);
364
365 return adv_smbus_read_byte_data(state->i2c_cec, reg);
366}
367
368static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
369{
370 struct adv7842_state *state = to_state(sd);
371
372 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
373}
374
375static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
376{
377 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
378}
379
380static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
381{
382 struct adv7842_state *state = to_state(sd);
383
384 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
385}
386
387static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
388{
389 struct adv7842_state *state = to_state(sd);
390
391 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
392}
393
394static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
395{
396 struct adv7842_state *state = to_state(sd);
397
398 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
399}
400
401static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
402{
403 struct adv7842_state *state = to_state(sd);
404
405 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
406}
407
408static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
409{
410 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
411}
412
413static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
414{
415 struct adv7842_state *state = to_state(sd);
416
417 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
418}
419
420static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421{
422 struct adv7842_state *state = to_state(sd);
423
424 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
425}
426
427static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
428{
429 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
430}
431
432static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
433{
434 struct adv7842_state *state = to_state(sd);
435
436 return adv_smbus_read_byte_data(state->i2c_afe, reg);
437}
438
439static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440{
441 struct adv7842_state *state = to_state(sd);
442
443 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
444}
445
446static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
447{
448 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
449}
450
451static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
452{
453 struct adv7842_state *state = to_state(sd);
454
455 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
456}
457
458static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
459{
460 struct adv7842_state *state = to_state(sd);
461
462 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
463}
464
465static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
466{
467 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
468}
469
470static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
471{
472 struct adv7842_state *state = to_state(sd);
473
474 return adv_smbus_read_byte_data(state->i2c_edid, reg);
475}
476
477static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
478{
479 struct adv7842_state *state = to_state(sd);
480
481 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
482}
483
484static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
485{
486 struct adv7842_state *state = to_state(sd);
487
488 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
489}
490
491static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
492{
493 struct adv7842_state *state = to_state(sd);
494
495 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
496}
497
5b64b205
MR		 498static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
499{
500 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
501}
502
a89bcd4c
HV		 503static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
504{
505 struct adv7842_state *state = to_state(sd);
506
507 return adv_smbus_read_byte_data(state->i2c_cp, reg);
508}
509
510static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
511{
512 struct adv7842_state *state = to_state(sd);
513
514 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
515}
516
517static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
518{
519 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
520}
521
522static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
523{
524 struct adv7842_state *state = to_state(sd);
525
526 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
527}
528
529static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
530{
531 struct adv7842_state *state = to_state(sd);
532
533 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
534}
535
536static void main_reset(struct v4l2_subdev *sd)
537{
538 struct i2c_client *client = v4l2_get_subdevdata(sd);
539
540 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
541
542 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
543
84aeed53 544 mdelay(5);
a89bcd4c
HV		 545}
546
547/* ----------------------------------------------------------------------- */
548
549static inline bool is_digital_input(struct v4l2_subdev *sd)
550{
551 struct adv7842_state *state = to_state(sd);
552
553 return state->mode == ADV7842_MODE_HDMI;
554}
555
556static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
557 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 558 /* keep this initialization for compatibility with GCC < 4.4.6 */
559 .reserved = { 0 },
560 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
561 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 562 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 563 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
564 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 565};
566
567static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
568 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 569 /* keep this initialization for compatibility with GCC < 4.4.6 */
570 .reserved = { 0 },
571 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
572 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 573 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 574 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
575 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 576};
577
578static inline const struct v4l2_dv_timings_cap *
579adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
580{
581 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
582 &adv7842_timings_cap_analog;
583}
584
585/* ----------------------------------------------------------------------- */
586
587static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
588{
589 struct delayed_work *dwork = to_delayed_work(work);
590 struct adv7842_state *state = container_of(dwork,
591 struct adv7842_state, delayed_work_enable_hotplug);
592 struct v4l2_subdev *sd = &state->sd;
593 int present = state->hdmi_edid.present;
594 u8 mask = 0;
595
596 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
597 __func__, present);
598
7de6fab1
MR		 599 if (present & (0x04 << ADV7842_EDID_PORT_A))
600 mask |= 0x20;
601 if (present & (0x04 << ADV7842_EDID_PORT_B))
602 mask |= 0x10;
a89bcd4c
HV		 603 io_write_and_or(sd, 0x20, 0xcf, mask);
604}
605
606static int edid_write_vga_segment(struct v4l2_subdev *sd)
607{
608 struct i2c_client *client = v4l2_get_subdevdata(sd);
609 struct adv7842_state *state = to_state(sd);
610 const u8 *val = state->vga_edid.edid;
611 int err = 0;
612 int i;
613
614 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
615
616 /* HPA disable on port A and B */
617 io_write_and_or(sd, 0x20, 0xcf, 0x00);
618
619 /* Disable I2C access to internal EDID ram from VGA DDC port */
620 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
621
622 /* edid segment pointer '1' for VGA port */
623 rep_write_and_or(sd, 0x77, 0xef, 0x10);
624
625 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
626 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
627 I2C_SMBUS_BLOCK_MAX, val + i);
628 if (err)
629 return err;
630
631 /* Calculates the checksums and enables I2C access
632 * to internal EDID ram from VGA DDC port.
633 */
634 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
635
636 for (i = 0; i < 1000; i++) {
637 if (rep_read(sd, 0x79) & 0x20)
638 break;
639 mdelay(1);
640 }
641 if (i == 1000) {
642 v4l_err(client, "error enabling edid on VGA port\n");
643 return -EIO;
644 }
645
646 /* enable hotplug after 200 ms */
647 queue_delayed_work(state->work_queues,
648 &state->delayed_work_enable_hotplug, HZ / 5);
649
650 return 0;
651}
652
653static int edid_spa_location(const u8 *edid)
654{
655 u8 d;
656
657 /*
658 * TODO, improve and update for other CEA extensions
659 * currently only for 1 segment (256 bytes),
660 * i.e. 1 extension block and CEA revision 3.
661 */
662 if ((edid[0x7e] != 1) ||
663 (edid[0x80] != 0x02) ||
664 (edid[0x81] != 0x03)) {
665 return -EINVAL;
666 }
667 /*
668 * search Vendor Specific Data Block (tag 3)
669 */
670 d = edid[0x82] & 0x7f;
671 if (d > 4) {
672 int i = 0x84;
673 int end = 0x80 + d;
674 do {
675 u8 tag = edid[i]>>5;
676 u8 len = edid[i] & 0x1f;
677
678 if ((tag == 3) && (len >= 5))
679 return i + 4;
680 i += len + 1;
681 } while (i < end);
682 }
683 return -EINVAL;
684}
685
686static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
687{
688 struct i2c_client *client = v4l2_get_subdevdata(sd);
689 struct adv7842_state *state = to_state(sd);
690 const u8 *val = state->hdmi_edid.edid;
a89bcd4c
HV		 691 int spa_loc = edid_spa_location(val);
692 int err = 0;
693 int i;
694
7de6fab1
MR		 695 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
696 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
a89bcd4c
HV		 697
698 /* HPA disable on port A and B */
699 io_write_and_or(sd, 0x20, 0xcf, 0x00);
700
701 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
702 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
703
fc2e991e
MB		 704 if (!state->hdmi_edid.present)
705 return 0;
706
a89bcd4c
HV		 707 /* edid segment pointer '0' for HDMI ports */
708 rep_write_and_or(sd, 0x77, 0xef, 0x00);
709
710 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
711 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
712 I2C_SMBUS_BLOCK_MAX, val + i);
713 if (err)
714 return err;
715
7de6fab1
MR		 716 if (spa_loc < 0)
717 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
718
719 if (port == ADV7842_EDID_PORT_A) {
720 rep_write(sd, 0x72, val[spa_loc]);
721 rep_write(sd, 0x73, val[spa_loc + 1]);
a89bcd4c 722 } else {
7de6fab1
MR		 723 rep_write(sd, 0x74, val[spa_loc]);
724 rep_write(sd, 0x75, val[spa_loc + 1]);
a89bcd4c 725 }
7de6fab1
MR		 726 rep_write(sd, 0x76, spa_loc & 0xff);
727 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
a89bcd4c
HV		 728
729 /* Calculates the checksums and enables I2C access to internal
730 * EDID ram from HDMI DDC ports
731 */
7de6fab1 732 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
a89bcd4c
HV		 733
734 for (i = 0; i < 1000; i++) {
7de6fab1 735 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
a89bcd4c
HV		 736 break;
737 mdelay(1);
738 }
739 if (i == 1000) {
7de6fab1
MR		 740 v4l_err(client, "error enabling edid on port %c\n",
741 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
a89bcd4c
HV		 742 return -EIO;
743 }
744
745 /* enable hotplug after 200 ms */
746 queue_delayed_work(state->work_queues,
747 &state->delayed_work_enable_hotplug, HZ / 5);
748
749 return 0;
750}
751
752/* ----------------------------------------------------------------------- */
753
754#ifdef CONFIG_VIDEO_ADV_DEBUG
755static void adv7842_inv_register(struct v4l2_subdev *sd)
756{
757 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
758 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
759 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
760 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
761 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
762 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
763 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
764 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
765 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
766 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
767 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
768 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
769}
770
771static int adv7842_g_register(struct v4l2_subdev *sd,
772 struct v4l2_dbg_register *reg)
773{
774 reg->size = 1;
775 switch (reg->reg >> 8) {
776 case 0:
777 reg->val = io_read(sd, reg->reg & 0xff);
778 break;
779 case 1:
780 reg->val = avlink_read(sd, reg->reg & 0xff);
781 break;
782 case 2:
783 reg->val = cec_read(sd, reg->reg & 0xff);
784 break;
785 case 3:
786 reg->val = infoframe_read(sd, reg->reg & 0xff);
787 break;
788 case 4:
789 reg->val = sdp_io_read(sd, reg->reg & 0xff);
790 break;
791 case 5:
792 reg->val = sdp_read(sd, reg->reg & 0xff);
793 break;
794 case 6:
795 reg->val = afe_read(sd, reg->reg & 0xff);
796 break;
797 case 7:
798 reg->val = rep_read(sd, reg->reg & 0xff);
799 break;
800 case 8:
801 reg->val = edid_read(sd, reg->reg & 0xff);
802 break;
803 case 9:
804 reg->val = hdmi_read(sd, reg->reg & 0xff);
805 break;
806 case 0xa:
807 reg->val = cp_read(sd, reg->reg & 0xff);
808 break;
809 case 0xb:
810 reg->val = vdp_read(sd, reg->reg & 0xff);
811 break;
812 default:
813 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
814 adv7842_inv_register(sd);
815 break;
816 }
817 return 0;
818}
819
820static int adv7842_s_register(struct v4l2_subdev *sd,
821 const struct v4l2_dbg_register *reg)
822{
823 u8 val = reg->val & 0xff;
824
825 switch (reg->reg >> 8) {
826 case 0:
827 io_write(sd, reg->reg & 0xff, val);
828 break;
829 case 1:
830 avlink_write(sd, reg->reg & 0xff, val);
831 break;
832 case 2:
833 cec_write(sd, reg->reg & 0xff, val);
834 break;
835 case 3:
836 infoframe_write(sd, reg->reg & 0xff, val);
837 break;
838 case 4:
839 sdp_io_write(sd, reg->reg & 0xff, val);
840 break;
841 case 5:
842 sdp_write(sd, reg->reg & 0xff, val);
843 break;
844 case 6:
845 afe_write(sd, reg->reg & 0xff, val);
846 break;
847 case 7:
848 rep_write(sd, reg->reg & 0xff, val);
849 break;
850 case 8:
851 edid_write(sd, reg->reg & 0xff, val);
852 break;
853 case 9:
854 hdmi_write(sd, reg->reg & 0xff, val);
855 break;
856 case 0xa:
857 cp_write(sd, reg->reg & 0xff, val);
858 break;
859 case 0xb:
860 vdp_write(sd, reg->reg & 0xff, val);
861 break;
862 default:
863 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
864 adv7842_inv_register(sd);
865 break;
866 }
867 return 0;
868}
869#endif
870
871static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
872{
873 struct adv7842_state *state = to_state(sd);
874 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
875 u8 reg_io_6f = io_read(sd, 0x6f);
876 int val = 0;
877
878 if (reg_io_6f & 0x02)
879 val |= 1; /* port A */
880 if (reg_io_6f & 0x01)
881 val |= 2; /* port B */
882
883 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
884
885 if (val != prev)
886 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
887 return 0;
888}
889
890static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
891 u8 prim_mode,
892 const struct adv7842_video_standards *predef_vid_timings,
893 const struct v4l2_dv_timings *timings)
894{
895 int i;
896
897 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
898 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
899 is_digital_input(sd) ? 250000 : 1000000))
900 continue;
901 /* video std */
902 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
903 /* v_freq and prim mode */
904 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
905 return 0;
906 }
907
908 return -1;
909}
910
911static int configure_predefined_video_timings(struct v4l2_subdev *sd,
912 struct v4l2_dv_timings *timings)
913{
914 struct adv7842_state *state = to_state(sd);
915 int err;
916
917 v4l2_dbg(1, debug, sd, "%s\n", __func__);
918
919 /* reset to default values */
920 io_write(sd, 0x16, 0x43);
921 io_write(sd, 0x17, 0x5a);
922 /* disable embedded syncs for auto graphics mode */
923 cp_write_and_or(sd, 0x81, 0xef, 0x00);
924 cp_write(sd, 0x26, 0x00);
925 cp_write(sd, 0x27, 0x00);
926 cp_write(sd, 0x28, 0x00);
927 cp_write(sd, 0x29, 0x00);
6251e65f 928 cp_write(sd, 0x8f, 0x40);
a89bcd4c
HV		 929 cp_write(sd, 0x90, 0x00);
930 cp_write(sd, 0xa5, 0x00);
931 cp_write(sd, 0xa6, 0x00);
932 cp_write(sd, 0xa7, 0x00);
933 cp_write(sd, 0xab, 0x00);
934 cp_write(sd, 0xac, 0x00);
935
936 switch (state->mode) {
937 case ADV7842_MODE_COMP:
938 case ADV7842_MODE_RGB:
939 err = find_and_set_predefined_video_timings(sd,
940 0x01, adv7842_prim_mode_comp, timings);
941 if (err)
942 err = find_and_set_predefined_video_timings(sd,
943 0x02, adv7842_prim_mode_gr, timings);
944 break;
945 case ADV7842_MODE_HDMI:
946 err = find_and_set_predefined_video_timings(sd,
947 0x05, adv7842_prim_mode_hdmi_comp, timings);
948 if (err)
949 err = find_and_set_predefined_video_timings(sd,
950 0x06, adv7842_prim_mode_hdmi_gr, timings);
951 break;
952 default:
953 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
954 __func__, state->mode);
955 err = -1;
956 break;
957 }
958
959
960 return err;
961}
962
963static void configure_custom_video_timings(struct v4l2_subdev *sd,
964 const struct v4l2_bt_timings *bt)
965{
966 struct adv7842_state *state = to_state(sd);
967 struct i2c_client *client = v4l2_get_subdevdata(sd);
968 u32 width = htotal(bt);
969 u32 height = vtotal(bt);
970 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
971 u16 cp_start_eav = width - bt->hfrontporch;
972 u16 cp_start_vbi = height - bt->vfrontporch + 1;
973 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
974 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
975 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
976 const u8 pll[2] = {
977 0xc0 | ((width >> 8) & 0x1f),
978 width & 0xff
979 };
980
981 v4l2_dbg(2, debug, sd, "%s\n", __func__);
982
983 switch (state->mode) {
984 case ADV7842_MODE_COMP:
985 case ADV7842_MODE_RGB:
986 /* auto graphics */
987 io_write(sd, 0x00, 0x07); /* video std */
988 io_write(sd, 0x01, 0x02); /* prim mode */
989 /* enable embedded syncs for auto graphics mode */
990 cp_write_and_or(sd, 0x81, 0xef, 0x10);
991
992 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
993 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
994 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
995 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
996 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
997 break;
998 }
999
1000 /* active video - horizontal timing */
1001 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1002 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1003 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1004 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1005
1006 /* active video - vertical timing */
1007 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1008 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1009 ((cp_end_vbi >> 8) & 0xf));
1010 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1011 break;
1012 case ADV7842_MODE_HDMI:
1013 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1014 according to [REF_03, c. 4.2] */
a89bcd4c
HV		 1015 io_write(sd, 0x00, 0x02); /* video std */
1016 io_write(sd, 0x01, 0x06); /* prim mode */
1017 break;
1018 default:
1019 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1020 __func__, state->mode);
1021 break;
1022 }
1023
1024 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1025 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1026 cp_write(sd, 0xab, (height >> 4) & 0xff);
1027 cp_write(sd, 0xac, (height & 0x0f) << 4);
1028}
1029
1030static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1031{
1032 struct adv7842_state *state = to_state(sd);
1033
69e9ba6f
HV		 1034 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
1035 __func__, state->rgb_quantization_range);
1036
a89bcd4c
HV		 1037 switch (state->rgb_quantization_range) {
1038 case V4L2_DV_RGB_RANGE_AUTO:
69e9ba6f
HV		 1039 if (state->mode == ADV7842_MODE_RGB) {
1040 /* Receiving analog RGB signal
1041 * Set RGB full range (0-255) */
1042 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1043 break;
1044 }
1045
1046 if (state->mode == ADV7842_MODE_COMP) {
1047 /* Receiving analog YPbPr signal
1048 * Set automode */
1049 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1050 break;
1051 }
1052
1053 if (hdmi_read(sd, 0x05) & 0x80) {
1054 /* Receiving HDMI signal
1055 * Set automode */
a89bcd4c 1056 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
69e9ba6f
HV		 1057 break;
1058 }
1059
1060 /* Receiving DVI-D signal
1061 * ADV7842 selects RGB limited range regardless of
1062 * input format (CE/IT) in automatic mode */
1063 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1064 /* RGB limited range (16-235) */
1065 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1066 } else {
1067 /* RGB full range (0-255) */
1068 io_write_and_or(sd, 0x02, 0x0f, 0x10);
a89bcd4c
HV		 1069 }
1070 break;
1071 case V4L2_DV_RGB_RANGE_LIMITED:
69e9ba6f
HV		 1072 if (state->mode == ADV7842_MODE_COMP) {
1073 /* YCrCb limited range (16-235) */
1074 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1075 } else {
1076 /* RGB limited range (16-235) */
1077 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1078 }
a89bcd4c
HV		 1079 break;
1080 case V4L2_DV_RGB_RANGE_FULL:
69e9ba6f
HV		 1081 if (state->mode == ADV7842_MODE_COMP) {
1082 /* YCrCb full range (0-255) */
1083 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1084 } else {
1085 /* RGB full range (0-255) */
1086 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1087 }
a89bcd4c
HV		 1088 break;
1089 }
1090}
1091
1092static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1093{
1094 struct v4l2_subdev *sd = to_sd(ctrl);
1095 struct adv7842_state *state = to_state(sd);
1096
1097 /* TODO SDP ctrls
1098 contrast/brightness/hue/free run is acting a bit strange,
1099 not sure if sdp csc is correct.
1100 */
1101 switch (ctrl->id) {
1102 /* standard ctrls */
1103 case V4L2_CID_BRIGHTNESS:
1104 cp_write(sd, 0x3c, ctrl->val);
1105 sdp_write(sd, 0x14, ctrl->val);
1106 /* ignore lsb sdp 0x17[3:2] */
1107 return 0;
1108 case V4L2_CID_CONTRAST:
1109 cp_write(sd, 0x3a, ctrl->val);
1110 sdp_write(sd, 0x13, ctrl->val);
1111 /* ignore lsb sdp 0x17[1:0] */
1112 return 0;
1113 case V4L2_CID_SATURATION:
1114 cp_write(sd, 0x3b, ctrl->val);
1115 sdp_write(sd, 0x15, ctrl->val);
1116 /* ignore lsb sdp 0x17[5:4] */
1117 return 0;
1118 case V4L2_CID_HUE:
1119 cp_write(sd, 0x3d, ctrl->val);
1120 sdp_write(sd, 0x16, ctrl->val);
1121 /* ignore lsb sdp 0x17[7:6] */
1122 return 0;
1123 /* custom ctrls */
1124 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1125 afe_write(sd, 0xc8, ctrl->val);
1126 return 0;
1127 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1128 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1129 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1130 return 0;
1131 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1132 u8 R = (ctrl->val & 0xff0000) >> 16;
1133 u8 G = (ctrl->val & 0x00ff00) >> 8;
1134 u8 B = (ctrl->val & 0x0000ff);
1135 /* RGB -> YUV, numerical approximation */
1136 int Y = 66 * R + 129 * G + 25 * B;
1137 int U = -38 * R - 74 * G + 112 * B;
1138 int V = 112 * R - 94 * G - 18 * B;
1139
1140 /* Scale down to 8 bits with rounding */
1141 Y = (Y + 128) >> 8;
1142 U = (U + 128) >> 8;
1143 V = (V + 128) >> 8;
1144 /* make U,V positive */
1145 Y += 16;
1146 U += 128;
1147 V += 128;
1148
1149 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1150 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1151
1152 /* CP */
1153 cp_write(sd, 0xc1, R);
1154 cp_write(sd, 0xc0, G);
1155 cp_write(sd, 0xc2, B);
1156 /* SDP */
1157 sdp_write(sd, 0xde, Y);
1158 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1159 return 0;
1160 }
1161 case V4L2_CID_DV_RX_RGB_RANGE:
1162 state->rgb_quantization_range = ctrl->val;
1163 set_rgb_quantization_range(sd);
1164 return 0;
1165 }
1166 return -EINVAL;
1167}
1168
1169static inline bool no_power(struct v4l2_subdev *sd)
1170{
1171 return io_read(sd, 0x0c) & 0x24;
1172}
1173
1174static inline bool no_cp_signal(struct v4l2_subdev *sd)
1175{
1176 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1177}
1178
1179static inline bool is_hdmi(struct v4l2_subdev *sd)
1180{
1181 return hdmi_read(sd, 0x05) & 0x80;
1182}
1183
1184static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1185{
1186 struct adv7842_state *state = to_state(sd);
1187
1188 *status = 0;
1189
1190 if (io_read(sd, 0x0c) & 0x24)
1191 *status |= V4L2_IN_ST_NO_POWER;
1192
1193 if (state->mode == ADV7842_MODE_SDP) {
1194 /* status from SDP block */
1195 if (!(sdp_read(sd, 0x5A) & 0x01))
1196 *status |= V4L2_IN_ST_NO_SIGNAL;
1197
1198 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1199 __func__, *status);
1200 return 0;
1201 }
1202 /* status from CP block */
1203 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1204 !(cp_read(sd, 0xb1) & 0x80))
1205 /* TODO channel 2 */
1206 *status |= V4L2_IN_ST_NO_SIGNAL;
1207
1208 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1209 *status |= V4L2_IN_ST_NO_SIGNAL;
1210
1211 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1212 __func__, *status);
1213
1214 return 0;
1215}
1216
1217struct stdi_readback {
1218 u16 bl, lcf, lcvs;
1219 u8 hs_pol, vs_pol;
1220 bool interlaced;
1221};
1222
1223static int stdi2dv_timings(struct v4l2_subdev *sd,
1224 struct stdi_readback *stdi,
1225 struct v4l2_dv_timings *timings)
1226{
1227 struct adv7842_state *state = to_state(sd);
1228 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1229 u32 pix_clk;
1230 int i;
1231
1232 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1233 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1234
1235 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1236 adv7842_get_dv_timings_cap(sd),
1237 adv7842_check_dv_timings, NULL))
1238 continue;
1239 if (vtotal(bt) != stdi->lcf + 1)
1240 continue;
1241 if (bt->vsync != stdi->lcvs)
1242 continue;
1243
1244 pix_clk = hfreq * htotal(bt);
1245
1246 if ((pix_clk < bt->pixelclock + 1000000) &&
1247 (pix_clk > bt->pixelclock - 1000000)) {
1248 *timings = v4l2_dv_timings_presets[i];
1249 return 0;
1250 }
1251 }
1252
1253 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1254 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1255 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1256 timings))
1257 return 0;
1258 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1259 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1260 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1261 state->aspect_ratio, timings))
1262 return 0;
1263
1264 v4l2_dbg(2, debug, sd,
1265 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1266 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1267 stdi->hs_pol, stdi->vs_pol);
1268 return -1;
1269}
1270
1271static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1272{
1273 u32 status;
1274
1275 adv7842_g_input_status(sd, &status);
1276 if (status & V4L2_IN_ST_NO_SIGNAL) {
1277 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1278 return -ENOLINK;
1279 }
1280
1281 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1282 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1283 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1284
1285 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1286 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1287 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1288 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1289 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1290 } else {
1291 stdi->hs_pol = 'x';
1292 stdi->vs_pol = 'x';
1293 }
1294 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1295
1296 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1297 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1298 return -ENOLINK;
1299 }
1300
1301 v4l2_dbg(2, debug, sd,
1302 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1303 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1304 stdi->hs_pol, stdi->vs_pol,
1305 stdi->interlaced ? "interlaced" : "progressive");
1306
1307 return 0;
1308}
1309
1310static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1311 struct v4l2_enum_dv_timings *timings)
1312{
1313 return v4l2_enum_dv_timings_cap(timings,
1314 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1315}
1316
1317static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1318 struct v4l2_dv_timings_cap *cap)
1319{
1320 *cap = *adv7842_get_dv_timings_cap(sd);
1321 return 0;
1322}
1323
1324/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
69e9ba6f 1325 if the format is listed in adv7842_timings[] */
a89bcd4c
HV		 1326static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1327 struct v4l2_dv_timings *timings)
1328{
1329 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1330 is_digital_input(sd) ? 250000 : 1000000,
1331 adv7842_check_dv_timings, NULL);
1332}
1333
1334static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1335 struct v4l2_dv_timings *timings)
1336{
1337 struct adv7842_state *state = to_state(sd);
1338 struct v4l2_bt_timings *bt = &timings->bt;
1339 struct stdi_readback stdi = { 0 };
1340
e78d834a
MB		 1341 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1342
a89bcd4c
HV		 1343 /* SDP block */
1344 if (state->mode == ADV7842_MODE_SDP)
1345 return -ENODATA;
1346
1347 /* read STDI */
1348 if (read_stdi(sd, &stdi)) {
6e9071f2 1349 state->restart_stdi_once = true;
a89bcd4c
HV		 1350 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1351 return -ENOLINK;
1352 }
1353 bt->interlaced = stdi.interlaced ?
1354 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
a89bcd4c
HV		 1355
1356 if (is_digital_input(sd)) {
e78d834a
MB		 1357 uint32_t freq;
1358
1359 timings->type = V4L2_DV_BT_656_1120;
6e9071f2 1360
e78d834a
MB		 1361 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1362 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1363 freq = (hdmi_read(sd, 0x06) * 1000000) +
1364 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
a89bcd4c
HV		 1365
1366 if (is_hdmi(sd)) {
1367 /* adjust for deep color mode */
e78d834a 1368 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
a89bcd4c 1369 }
e78d834a
MB		 1370 bt->pixelclock = freq;
1371 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
a89bcd4c 1372 hdmi_read(sd, 0x21);
e78d834a 1373 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
a89bcd4c 1374 hdmi_read(sd, 0x23);
e78d834a 1375 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
a89bcd4c 1376 hdmi_read(sd, 0x25);
e78d834a
MB		 1377 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1378 hdmi_read(sd, 0x2b)) / 2;
1379 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1380 hdmi_read(sd, 0x2f)) / 2;
1381 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1382 hdmi_read(sd, 0x33)) / 2;
1383 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1384 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1385 if (bt->interlaced == V4L2_DV_INTERLACED) {
1386 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1387 hdmi_read(sd, 0x0c);
1388 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1389 hdmi_read(sd, 0x2d)) / 2;
1390 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1391 hdmi_read(sd, 0x31)) / 2;
1392 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1393 hdmi_read(sd, 0x35)) / 2;
1394 }
1395 adv7842_fill_optional_dv_timings_fields(sd, timings);
a89bcd4c 1396 } else {
6e9071f2
MB		 1397 /* find format
1398 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1399 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1400 */
1401 if (!stdi2dv_timings(sd, &stdi, timings))
1402 goto found;
1403 stdi.lcvs += 1;
1404 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1405 if (!stdi2dv_timings(sd, &stdi, timings))
1406 goto found;
1407 stdi.lcvs -= 2;
1408 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
a89bcd4c 1409 if (stdi2dv_timings(sd, &stdi, timings)) {
6e9071f2
MB		 1410 /*
1411 * The STDI block may measure wrong values, especially
1412 * for lcvs and lcf. If the driver can not find any
1413 * valid timing, the STDI block is restarted to measure
1414 * the video timings again. The function will return an
1415 * error, but the restart of STDI will generate a new
1416 * STDI interrupt and the format detection process will
1417 * restart.
1418 */
1419 if (state->restart_stdi_once) {
1420 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1421 /* TODO restart STDI for Sync Channel 2 */
1422 /* enter one-shot mode */
1423 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1424 /* trigger STDI restart */
1425 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1426 /* reset to continuous mode */
1427 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1428 state->restart_stdi_once = false;
1429 return -ENOLINK;
1430 }
a89bcd4c
HV		 1431 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1432 return -ERANGE;
1433 }
6e9071f2 1434 state->restart_stdi_once = true;
a89bcd4c 1435 }
6e9071f2 1436found:
a89bcd4c
HV		 1437
1438 if (debug > 1)
6e9071f2
MB		 1439 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1440 timings, true);
a89bcd4c
HV		 1441 return 0;
1442}
1443
1444static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1445 struct v4l2_dv_timings *timings)
1446{
1447 struct adv7842_state *state = to_state(sd);
1448 struct v4l2_bt_timings *bt;
1449 int err;
1450
e78d834a
MB		 1451 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1452
a89bcd4c
HV		 1453 if (state->mode == ADV7842_MODE_SDP)
1454 return -ENODATA;
1455
1456 bt = &timings->bt;
1457
1458 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1459 adv7842_check_dv_timings, NULL))
1460 return -ERANGE;
1461
1462 adv7842_fill_optional_dv_timings_fields(sd, timings);
1463
1464 state->timings = *timings;
1465
6251e65f 1466 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
a89bcd4c
HV		 1467
1468 /* Use prim_mode and vid_std when available */
1469 err = configure_predefined_video_timings(sd, timings);
1470 if (err) {
1471 /* custom settings when the video format
1472 does not have prim_mode/vid_std */
1473 configure_custom_video_timings(sd, bt);
1474 }
1475
1476 set_rgb_quantization_range(sd);
1477
1478
1479 if (debug > 1)
1480 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1481 timings, true);
1482 return 0;
1483}
1484
1485static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1486 struct v4l2_dv_timings *timings)
1487{
1488 struct adv7842_state *state = to_state(sd);
1489
1490 if (state->mode == ADV7842_MODE_SDP)
1491 return -ENODATA;
1492 *timings = state->timings;
1493 return 0;
1494}
1495
1496static void enable_input(struct v4l2_subdev *sd)
1497{
1498 struct adv7842_state *state = to_state(sd);
69e9ba6f
HV		 1499
1500 set_rgb_quantization_range(sd);
a89bcd4c
HV		 1501 switch (state->mode) {
1502 case ADV7842_MODE_SDP:
1503 case ADV7842_MODE_COMP:
1504 case ADV7842_MODE_RGB:
a89bcd4c
HV		 1505 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1506 break;
1507 case ADV7842_MODE_HDMI:
a89bcd4c
HV		 1508 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1509 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5b64b205 1510 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
a89bcd4c
HV		 1511 break;
1512 default:
1513 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1514 __func__, state->mode);
1515 break;
1516 }
1517}
1518
1519static void disable_input(struct v4l2_subdev *sd)
1520{
5b64b205
MR		 1521 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1522 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
a89bcd4c 1523 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
a89bcd4c
HV		 1524 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1525}
1526
1527static void sdp_csc_coeff(struct v4l2_subdev *sd,
1528 const struct adv7842_sdp_csc_coeff *c)
1529{
1530 /* csc auto/manual */
1531 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1532
1533 if (!c->manual)
1534 return;
1535
1536 /* csc scaling */
1537 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1538
1539 /* A coeff */
1540 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1541 sdp_io_write(sd, 0xe1, c->A1);
1542 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1543 sdp_io_write(sd, 0xe3, c->A2);
1544 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1545 sdp_io_write(sd, 0xe5, c->A3);
1546
1547 /* A scale */
1548 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1549 sdp_io_write(sd, 0xe7, c->A4);
1550
1551 /* B coeff */
1552 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1553 sdp_io_write(sd, 0xe9, c->B1);
1554 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1555 sdp_io_write(sd, 0xeb, c->B2);
1556 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1557 sdp_io_write(sd, 0xed, c->B3);
1558
1559 /* B scale */
1560 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1561 sdp_io_write(sd, 0xef, c->B4);
1562
1563 /* C coeff */
1564 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1565 sdp_io_write(sd, 0xf1, c->C1);
1566 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1567 sdp_io_write(sd, 0xf3, c->C2);
1568 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1569 sdp_io_write(sd, 0xf5, c->C3);
1570
1571 /* C scale */
1572 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1573 sdp_io_write(sd, 0xf7, c->C4);
1574}
1575
1576static void select_input(struct v4l2_subdev *sd,
1577 enum adv7842_vid_std_select vid_std_select)
1578{
1579 struct adv7842_state *state = to_state(sd);
1580
1581 switch (state->mode) {
1582 case ADV7842_MODE_SDP:
1583 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1584 io_write(sd, 0x01, 0); /* prim mode */
1585 /* enable embedded syncs for auto graphics mode */
1586 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1587
1588 afe_write(sd, 0x00, 0x00); /* power up ADC */
1589 afe_write(sd, 0xc8, 0x00); /* phase control */
1590
1591 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1592 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1593
1594 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1595 /* script says register 0xde, which don't exist in manual */
1596
1597 /* Manual analog input muxing mode, CVBS (6.4)*/
1598 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1599 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1600 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1601 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1602 } else {
1603 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1604 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1605 }
1606 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1607 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1608
1609 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1610 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1611
1612 /* SDP recommended settings */
1613 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1614 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1615
1616 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1617 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1618 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1619 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1620 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1621 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1622 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1623
1624 /* deinterlacer enabled and 3D comb */
1625 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1626
1627 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1628
1629 break;
1630
1631 case ADV7842_MODE_COMP:
1632 case ADV7842_MODE_RGB:
1633 /* Automatic analog input muxing mode */
1634 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1635 /* set mode and select free run resolution */
1636 io_write(sd, 0x00, vid_std_select); /* video std */
1637 io_write(sd, 0x01, 0x02); /* prim mode */
1638 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1639 for auto graphics mode */
1640
1641 afe_write(sd, 0x00, 0x00); /* power up ADC */
1642 afe_write(sd, 0xc8, 0x00); /* phase control */
69e9ba6f
HV		 1643 if (state->mode == ADV7842_MODE_COMP) {
1644 /* force to YCrCb */
1645 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1646 } else {
1647 /* force to RGB */
1648 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1649 }
a89bcd4c
HV		 1650
1651 /* set ADI recommended settings for digitizer */
1652 /* "ADV7842 Register Settings Recommendations
1653 * (rev. 1.8, November 2010)" p. 9. */
1654 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1655 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1656
1657 /* set to default gain for RGB */
1658 cp_write(sd, 0x73, 0x10);
1659 cp_write(sd, 0x74, 0x04);
1660 cp_write(sd, 0x75, 0x01);
1661 cp_write(sd, 0x76, 0x00);
1662
1663 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1664 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1665 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1666 break;
1667
1668 case ADV7842_MODE_HDMI:
1669 /* Automatic analog input muxing mode */
1670 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1671 /* set mode and select free run resolution */
1672 if (state->hdmi_port_a)
1673 hdmi_write(sd, 0x00, 0x02); /* select port A */
1674 else
1675 hdmi_write(sd, 0x00, 0x03); /* select port B */
1676 io_write(sd, 0x00, vid_std_select); /* video std */
1677 io_write(sd, 0x01, 5); /* prim mode */
1678 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1679 for auto graphics mode */
1680
1681 /* set ADI recommended settings for HDMI: */
1682 /* "ADV7842 Register Settings Recommendations
1683 * (rev. 1.8, November 2010)" p. 3. */
1684 hdmi_write(sd, 0xc0, 0x00);
1685 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1686 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1687 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1688 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1689 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1690 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1691 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1692 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1693 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1694 Improve robustness */
1695 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1696 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1697 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1698 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1699 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1700 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1701 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1702 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1703 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1704 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1705
1706 afe_write(sd, 0x00, 0xff); /* power down ADC */
1707 afe_write(sd, 0xc8, 0x40); /* phase control */
1708
1709 /* set to default gain for HDMI */
1710 cp_write(sd, 0x73, 0x10);
1711 cp_write(sd, 0x74, 0x04);
1712 cp_write(sd, 0x75, 0x01);
1713 cp_write(sd, 0x76, 0x00);
1714
1715 /* reset ADI recommended settings for digitizer */
1716 /* "ADV7842 Register Settings Recommendations
1717 * (rev. 2.5, June 2010)" p. 17. */
1718 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1719 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1720 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1721 enable color control */
1722 /* CP coast control */
1723 cp_write(sd, 0xc3, 0x33); /* Component mode */
1724
1725 /* color space conversion, autodetect color space */
1726 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1727 break;
1728
1729 default:
1730 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1731 __func__, state->mode);
1732 break;
1733 }
1734}
1735
1736static int adv7842_s_routing(struct v4l2_subdev *sd,
1737 u32 input, u32 output, u32 config)
1738{
1739 struct adv7842_state *state = to_state(sd);
1740
1741 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1742
1743 switch (input) {
1744 case ADV7842_SELECT_HDMI_PORT_A:
a89bcd4c
HV		 1745 state->mode = ADV7842_MODE_HDMI;
1746 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1747 state->hdmi_port_a = true;
1748 break;
1749 case ADV7842_SELECT_HDMI_PORT_B:
a89bcd4c
HV		 1750 state->mode = ADV7842_MODE_HDMI;
1751 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1752 state->hdmi_port_a = false;
1753 break;
1754 case ADV7842_SELECT_VGA_COMP:
69e9ba6f
HV		 1755 state->mode = ADV7842_MODE_COMP;
1756 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1757 break;
a89bcd4c
HV		 1758 case ADV7842_SELECT_VGA_RGB:
1759 state->mode = ADV7842_MODE_RGB;
1760 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1761 break;
1762 case ADV7842_SELECT_SDP_CVBS:
1763 state->mode = ADV7842_MODE_SDP;
1764 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1765 break;
1766 case ADV7842_SELECT_SDP_YC:
1767 state->mode = ADV7842_MODE_SDP;
1768 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1769 break;
1770 default:
1771 return -EINVAL;
1772 }
1773
1774 disable_input(sd);
1775 select_input(sd, state->vid_std_select);
1776 enable_input(sd);
1777
1778 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1779
1780 return 0;
1781}
1782
1783static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1784 enum v4l2_mbus_pixelcode *code)
1785{
1786 if (index)
1787 return -EINVAL;
1788 /* Good enough for now */
1789 *code = V4L2_MBUS_FMT_FIXED;
1790 return 0;
1791}
1792
1793static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1794 struct v4l2_mbus_framefmt *fmt)
1795{
1796 struct adv7842_state *state = to_state(sd);
1797
1798 fmt->width = state->timings.bt.width;
1799 fmt->height = state->timings.bt.height;
1800 fmt->code = V4L2_MBUS_FMT_FIXED;
1801 fmt->field = V4L2_FIELD_NONE;
1802
1803 if (state->mode == ADV7842_MODE_SDP) {
1804 /* SPD block */
1805 if (!(sdp_read(sd, 0x5A) & 0x01))
1806 return -EINVAL;
1807 fmt->width = 720;
1808 /* valid signal */
1809 if (state->norm & V4L2_STD_525_60)
1810 fmt->height = 480;
1811 else
1812 fmt->height = 576;
1813 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1814 return 0;
1815 }
1816
1817 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1818 fmt->colorspace = (state->timings.bt.height <= 576) ?
1819 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1820 }
1821 return 0;
1822}
1823
1824static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1825{
1826 if (enable) {
1827 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1828 io_write(sd, 0x46, 0x9c);
1829 /* ESDP_50HZ_DET interrupt */
1830 io_write(sd, 0x5a, 0x10);
1831 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1832 io_write(sd, 0x73, 0x03);
1833 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1834 io_write(sd, 0x78, 0x03);
1835 /* Enable SDP Standard Detection Change and SDP Video Detected */
1836 io_write(sd, 0xa0, 0x09);
1837 } else {
1838 io_write(sd, 0x46, 0x0);
1839 io_write(sd, 0x5a, 0x0);
1840 io_write(sd, 0x73, 0x0);
1841 io_write(sd, 0x78, 0x0);
1842 io_write(sd, 0xa0, 0x0);
1843 }
1844}
1845
1846static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1847{
1848 struct adv7842_state *state = to_state(sd);
1849 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1850 u8 irq_status[5];
a89bcd4c 1851
c9f1f271 1852 adv7842_irq_enable(sd, false);
a89bcd4c
HV		 1853
1854 /* read status */
1855 irq_status[0] = io_read(sd, 0x43);
1856 irq_status[1] = io_read(sd, 0x57);
1857 irq_status[2] = io_read(sd, 0x70);
1858 irq_status[3] = io_read(sd, 0x75);
1859 irq_status[4] = io_read(sd, 0x9d);
1860
1861 /* and clear */
1862 if (irq_status[0])
1863 io_write(sd, 0x44, irq_status[0]);
1864 if (irq_status[1])
1865 io_write(sd, 0x58, irq_status[1]);
1866 if (irq_status[2])
1867 io_write(sd, 0x71, irq_status[2]);
1868 if (irq_status[3])
1869 io_write(sd, 0x76, irq_status[3]);
1870 if (irq_status[4])
1871 io_write(sd, 0x9e, irq_status[4]);
1872
c9f1f271
MB		 1873 adv7842_irq_enable(sd, true);
1874
a89bcd4c
HV		 1875 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1876 irq_status[0], irq_status[1], irq_status[2],
1877 irq_status[3], irq_status[4]);
1878
1879 /* format change CP */
1880 fmt_change_cp = irq_status[0] & 0x9c;
1881
1882 /* format change SDP */
1883 if (state->mode == ADV7842_MODE_SDP)
1884 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1885 else
1886 fmt_change_sdp = 0;
1887
1888 /* digital format CP */
1889 if (is_digital_input(sd))
1890 fmt_change_digital = irq_status[3] & 0x03;
1891 else
1892 fmt_change_digital = 0;
1893
1894 /* notify */
1895 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1896 v4l2_dbg(1, debug, sd,
1897 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1898 __func__, fmt_change_cp, fmt_change_digital,
1899 fmt_change_sdp);
1900 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1901 }
1902
1903 /* 5v cable detect */
1904 if (irq_status[2])
1905 adv7842_s_detect_tx_5v_ctrl(sd);
1906
1907 if (handled)
1908 *handled = true;
1909
a89bcd4c
HV		 1910 return 0;
1911}
1912
1913static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1914{
1915 struct adv7842_state *state = to_state(sd);
1916 int err = 0;
1917
7de6fab1 1918 if (e->pad > ADV7842_EDID_PORT_VGA)
a89bcd4c
HV		 1919 return -EINVAL;
1920 if (e->start_block != 0)
1921 return -EINVAL;
1922 if (e->blocks > 2)
1923 return -E2BIG;
1924 if (!e->edid)
1925 return -EINVAL;
1926
1927 /* todo, per edid */
1928 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1929 e->edid[0x16]);
1930
7de6fab1
MR		 1931 switch (e->pad) {
1932 case ADV7842_EDID_PORT_VGA:
a89bcd4c
HV		 1933 memset(&state->vga_edid.edid, 0, 256);
1934 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1935 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1936 err = edid_write_vga_segment(sd);
7de6fab1
MR		 1937 break;
1938 case ADV7842_EDID_PORT_A:
1939 case ADV7842_EDID_PORT_B:
a89bcd4c
HV		 1940 memset(&state->hdmi_edid.edid, 0, 256);
1941 if (e->blocks)
7de6fab1 1942 state->hdmi_edid.present |= 0x04 << e->pad;
a89bcd4c 1943 else
7de6fab1
MR		 1944 state->hdmi_edid.present &= ~(0x04 << e->pad);
1945 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
a89bcd4c 1946 err = edid_write_hdmi_segment(sd, e->pad);
7de6fab1
MR		 1947 break;
1948 default:
1949 return -EINVAL;
a89bcd4c
HV		 1950 }
1951 if (err < 0)
1952 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1953 return err;
1954}
1955
1956/*********** avi info frame CEA-861-E **************/
1957/* TODO move to common library */
1958
1959struct avi_info_frame {
1960 uint8_t f17;
1961 uint8_t y10;
1962 uint8_t a0;
1963 uint8_t b10;
1964 uint8_t s10;
1965 uint8_t c10;
1966 uint8_t m10;
1967 uint8_t r3210;
1968 uint8_t itc;
1969 uint8_t ec210;
1970 uint8_t q10;
1971 uint8_t sc10;
1972 uint8_t f47;
1973 uint8_t vic;
1974 uint8_t yq10;
1975 uint8_t cn10;
1976 uint8_t pr3210;
1977 uint16_t etb;
1978 uint16_t sbb;
1979 uint16_t elb;
1980 uint16_t srb;
1981};
1982
1983static const char *y10_txt[4] = {
1984 "RGB",
1985 "YCbCr 4:2:2",
1986 "YCbCr 4:4:4",
1987 "Future",
1988};
1989
1990static const char *c10_txt[4] = {
1991 "No Data",
1992 "SMPTE 170M",
1993 "ITU-R 709",
1994 "Extended Colorimetry information valied",
1995};
1996
1997static const char *itc_txt[2] = {
1998 "No Data",
1999 "IT content",
2000};
2001
2002static const char *ec210_txt[8] = {
2003 "xvYCC601",
2004 "xvYCC709",
2005 "sYCC601",
2006 "AdobeYCC601",
2007 "AdobeRGB",
2008 "5 reserved",
2009 "6 reserved",
2010 "7 reserved",
2011};
2012
2013static const char *q10_txt[4] = {
2014 "Default",
2015 "Limited Range",
2016 "Full Range",
2017 "Reserved",
2018};
2019
2020static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
2021 struct avi_info_frame *avi)
2022{
2023 avi->f17 = (buf[1] >> 7) & 0x1;
2024 avi->y10 = (buf[1] >> 5) & 0x3;
2025 avi->a0 = (buf[1] >> 4) & 0x1;
2026 avi->b10 = (buf[1] >> 2) & 0x3;
2027 avi->s10 = buf[1] & 0x3;
2028 avi->c10 = (buf[2] >> 6) & 0x3;
2029 avi->m10 = (buf[2] >> 4) & 0x3;
2030 avi->r3210 = buf[2] & 0xf;
2031 avi->itc = (buf[3] >> 7) & 0x1;
2032 avi->ec210 = (buf[3] >> 4) & 0x7;
2033 avi->q10 = (buf[3] >> 2) & 0x3;
2034 avi->sc10 = buf[3] & 0x3;
2035 avi->f47 = (buf[4] >> 7) & 0x1;
2036 avi->vic = buf[4] & 0x7f;
2037 avi->yq10 = (buf[5] >> 6) & 0x3;
2038 avi->cn10 = (buf[5] >> 4) & 0x3;
2039 avi->pr3210 = buf[5] & 0xf;
2040 avi->etb = buf[6] + 256*buf[7];
2041 avi->sbb = buf[8] + 256*buf[9];
2042 avi->elb = buf[10] + 256*buf[11];
2043 avi->srb = buf[12] + 256*buf[13];
2044}
2045
2046static void print_avi_infoframe(struct v4l2_subdev *sd)
2047{
2048 int i;
2049 uint8_t buf[14];
2050 uint8_t avi_inf_len;
2051 struct avi_info_frame avi;
2052
2053 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2054 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2055 return;
2056 }
2057 if (!(io_read(sd, 0x60) & 0x01)) {
2058 v4l2_info(sd, "AVI infoframe not received\n");
2059 return;
2060 }
2061
2062 if (io_read(sd, 0x88) & 0x10) {
2063 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2064 with a length of 14 or 15. See the ADV7842 Register Settings
2065 Recommendations document for more details. */
2066 v4l2_info(sd, "AVI infoframe checksum error\n");
2067 return;
2068 }
2069
2070 avi_inf_len = infoframe_read(sd, 0xe2);
2071 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2072 infoframe_read(sd, 0xe1), avi_inf_len);
2073
2074 if (infoframe_read(sd, 0xe1) != 0x02)
2075 return;
2076
2077 for (i = 0; i < 14; i++)
2078 buf[i] = infoframe_read(sd, i);
2079
2080 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2081 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2082 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2083
2084 parse_avi_infoframe(sd, buf, &avi);
2085
2086 if (avi.vic)
2087 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2088 if (avi.itc)
2089 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2090
2091 if (avi.y10)
2092 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2093 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2094 else
2095 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2096}
2097
2098static const char * const prim_mode_txt[] = {
2099 "SDP",
2100 "Component",
2101 "Graphics",
2102 "Reserved",
2103 "CVBS & HDMI AUDIO",
2104 "HDMI-Comp",
2105 "HDMI-GR",
2106 "Reserved",
2107 "Reserved",
2108 "Reserved",
2109 "Reserved",
2110 "Reserved",
2111 "Reserved",
2112 "Reserved",
2113 "Reserved",
2114 "Reserved",
2115};
2116
2117static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2118{
2119 /* SDP (Standard definition processor) block */
2120 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2121
2122 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2123 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2124 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2125
2126 v4l2_info(sd, "SDP: free run: %s\n",
2127 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2128 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2129 "valid SD/PR signal detected" : "invalid/no signal");
2130 if (sdp_signal_detected) {
2131 static const char * const sdp_std_txt[] = {
2132 "NTSC-M/J",
2133 "1?",
2134 "NTSC-443",
2135 "60HzSECAM",
2136 "PAL-M",
2137 "5?",
2138 "PAL-60",
2139 "7?", "8?", "9?", "a?", "b?",
2140 "PAL-CombN",
2141 "d?",
2142 "PAL-BGHID",
2143 "SECAM"
2144 };
2145 v4l2_info(sd, "SDP: standard %s\n",
2146 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2147 v4l2_info(sd, "SDP: %s\n",
2148 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2149 v4l2_info(sd, "SDP: %s\n",
2150 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2151 v4l2_info(sd, "SDP: deinterlacer %s\n",
2152 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2153 v4l2_info(sd, "SDP: csc %s mode\n",
2154 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2155 }
2156 return 0;
2157}
2158
2159static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2160{
2161 /* CP block */
2162 struct adv7842_state *state = to_state(sd);
2163 struct v4l2_dv_timings timings;
2164 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2165 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2166 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2167 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2168 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2169 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2170 bool audio_mute = io_read(sd, 0x65) & 0x40;
2171
2172 static const char * const csc_coeff_sel_rb[16] = {
2173 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2174 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2175 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2176 "reserved", "reserved", "reserved", "reserved", "manual"
2177 };
2178 static const char * const input_color_space_txt[16] = {
2179 "RGB limited range (16-235)", "RGB full range (0-255)",
2180 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
69e9ba6f 2181 "xvYCC Bt.601", "xvYCC Bt.709",
a89bcd4c
HV		 2182 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2183 "invalid", "invalid", "invalid", "invalid", "invalid",
2184 "invalid", "invalid", "automatic"
2185 };
2186 static const char * const rgb_quantization_range_txt[] = {
2187 "Automatic",
2188 "RGB limited range (16-235)",
2189 "RGB full range (0-255)",
2190 };
2191 static const char * const deep_color_mode_txt[4] = {
2192 "8-bits per channel",
2193 "10-bits per channel",
2194 "12-bits per channel",
2195 "16-bits per channel (not supported)"
2196 };
2197
2198 v4l2_info(sd, "-----Chip status-----\n");
2199 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
a89bcd4c
HV		 2200 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2201 state->hdmi_port_a ? "A" : "B");
2202 v4l2_info(sd, "EDID A %s, B %s\n",
2203 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2204 "enabled" : "disabled",
2205 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2206 "enabled" : "disabled");
2207 v4l2_info(sd, "HPD A %s, B %s\n",
2208 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2209 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2210 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2211 "enabled" : "disabled");
2212
2213 v4l2_info(sd, "-----Signal status-----\n");
2214 if (state->hdmi_port_a) {
2215 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2216 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2217 v4l2_info(sd, "TMDS signal detected: %s\n",
2218 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2219 v4l2_info(sd, "TMDS signal locked: %s\n",
2220 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2221 } else {
2222 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2223 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2224 v4l2_info(sd, "TMDS signal detected: %s\n",
2225 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2226 v4l2_info(sd, "TMDS signal locked: %s\n",
2227 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2228 }
2229 v4l2_info(sd, "CP free run: %s\n",
2230 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2231 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2232 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2233 (io_read(sd, 0x01) & 0x70) >> 4);
2234
2235 v4l2_info(sd, "-----Video Timings-----\n");
2236 if (no_cp_signal(sd)) {
2237 v4l2_info(sd, "STDI: not locked\n");
2238 } else {
2239 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2240 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2241 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2242 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2243 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2244 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2245 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2246 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2247 v4l2_info(sd,
2248 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2249 lcf, bl, lcvs, fcl,
2250 (cp_read(sd, 0xb1) & 0x40) ?
2251 "interlaced" : "progressive",
2252 hs_pol, vs_pol);
2253 }
2254 if (adv7842_query_dv_timings(sd, &timings))
2255 v4l2_info(sd, "No video detected\n");
2256 else
2257 v4l2_print_dv_timings(sd->name, "Detected format: ",
2258 &timings, true);
2259 v4l2_print_dv_timings(sd->name, "Configured format: ",
2260 &state->timings, true);
2261
2262 if (no_cp_signal(sd))
2263 return 0;
2264
2265 v4l2_info(sd, "-----Color space-----\n");
2266 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2267 rgb_quantization_range_txt[state->rgb_quantization_range]);
2268 v4l2_info(sd, "Input color space: %s\n",
2269 input_color_space_txt[reg_io_0x02 >> 4]);
2270 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2271 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2272 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2273 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2274 "enabled" : "disabled");
2275 v4l2_info(sd, "Color space conversion: %s\n",
2276 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2277
2278 if (!is_digital_input(sd))
2279 return 0;
2280
2281 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2282 v4l2_info(sd, "HDCP encrypted content: %s\n",
2283 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2284 v4l2_info(sd, "HDCP keys read: %s%s\n",
2285 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2286 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2287 if (!is_hdmi(sd))
2288 return 0;
2289
2290 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2291 audio_pll_locked ? "locked" : "not locked",
2292 audio_sample_packet_detect ? "detected" : "not detected",
2293 audio_mute ? "muted" : "enabled");
2294 if (audio_pll_locked && audio_sample_packet_detect) {
2295 v4l2_info(sd, "Audio format: %s\n",
2296 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2297 }
2298 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2299 (hdmi_read(sd, 0x5c) << 8) +
2300 (hdmi_read(sd, 0x5d) & 0xf0));
2301 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2302 (hdmi_read(sd, 0x5e) << 8) +
2303 hdmi_read(sd, 0x5f));
2304 v4l2_info(sd, "AV Mute: %s\n",
2305 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2306 v4l2_info(sd, "Deep color mode: %s\n",
2307 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2308
2309 print_avi_infoframe(sd);
2310 return 0;
2311}
2312
2313static int adv7842_log_status(struct v4l2_subdev *sd)
2314{
2315 struct adv7842_state *state = to_state(sd);
2316
2317 if (state->mode == ADV7842_MODE_SDP)
2318 return adv7842_sdp_log_status(sd);
2319 return adv7842_cp_log_status(sd);
2320}
2321
2322static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2323{
2324 struct adv7842_state *state = to_state(sd);
2325
2326 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2327
2328 if (state->mode != ADV7842_MODE_SDP)
2329 return -ENODATA;
2330
2331 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2332 *std = 0;
2333 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2334 return 0;
2335 }
2336
2337 switch (sdp_read(sd, 0x52) & 0x0f) {
2338 case 0:
2339 /* NTSC-M/J */
2340 *std &= V4L2_STD_NTSC;
2341 break;
2342 case 2:
2343 /* NTSC-443 */
2344 *std &= V4L2_STD_NTSC_443;
2345 break;
2346 case 3:
2347 /* 60HzSECAM */
2348 *std &= V4L2_STD_SECAM;
2349 break;
2350 case 4:
2351 /* PAL-M */
2352 *std &= V4L2_STD_PAL_M;
2353 break;
2354 case 6:
2355 /* PAL-60 */
2356 *std &= V4L2_STD_PAL_60;
2357 break;
2358 case 0xc:
2359 /* PAL-CombN */
2360 *std &= V4L2_STD_PAL_Nc;
2361 break;
2362 case 0xe:
2363 /* PAL-BGHID */
2364 *std &= V4L2_STD_PAL;
2365 break;
2366 case 0xf:
2367 /* SECAM */
2368 *std &= V4L2_STD_SECAM;
2369 break;
2370 default:
2371 *std &= V4L2_STD_ALL;
2372 break;
2373 }
2374 return 0;
2375}
2376
3c4da74f
MB		 2377static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2378{
2379 if (s && s->adjust) {
2380 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2381 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2382 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2383 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2384 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2385 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2386 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2387 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2388 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2389 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2390 sdp_io_write(sd, 0xae, s->de_v_end_o);
2391 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2392 } else {
2393 /* set to default */
2394 sdp_io_write(sd, 0x94, 0x00);
2395 sdp_io_write(sd, 0x95, 0x00);
2396 sdp_io_write(sd, 0x96, 0x00);
2397 sdp_io_write(sd, 0x97, 0x20);
2398 sdp_io_write(sd, 0x98, 0x00);
2399 sdp_io_write(sd, 0x99, 0x00);
2400 sdp_io_write(sd, 0x9a, 0x00);
2401 sdp_io_write(sd, 0x9b, 0x00);
2402 sdp_io_write(sd, 0xac, 0x04);
2403 sdp_io_write(sd, 0xad, 0x04);
2404 sdp_io_write(sd, 0xae, 0x04);
2405 sdp_io_write(sd, 0xaf, 0x04);
2406 }
2407}
2408
a89bcd4c
HV		 2409static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2410{
2411 struct adv7842_state *state = to_state(sd);
3c4da74f 2412 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2413
2414 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2415
2416 if (state->mode != ADV7842_MODE_SDP)
2417 return -ENODATA;
2418
3c4da74f
MB		 2419 if (norm & V4L2_STD_625_50)
2420 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2421 else if (norm & V4L2_STD_525_60)
2422 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2423 else
2424 adv7842_s_sdp_io(sd, NULL);
2425
a89bcd4c
HV		 2426 if (norm & V4L2_STD_ALL) {
2427 state->norm = norm;
2428 return 0;
2429 }
2430 return -EINVAL;
2431}
2432
2433static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2434{
2435 struct adv7842_state *state = to_state(sd);
2436
2437 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2438
2439 if (state->mode != ADV7842_MODE_SDP)
2440 return -ENODATA;
2441
2442 *norm = state->norm;
2443 return 0;
2444}
2445
2446/* ----------------------------------------------------------------------- */
2447
69e9ba6f 2448static int adv7842_core_init(struct v4l2_subdev *sd)
a89bcd4c 2449{
69e9ba6f
HV		 2450 struct adv7842_state *state = to_state(sd);
2451 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2452 hdmi_write(sd, 0x48,
2453 (pdata->disable_pwrdnb ? 0x80 : 0) |
2454 (pdata->disable_cable_det_rst ? 0x40 : 0));
2455
2456 disable_input(sd);
2457
2458 /* power */
2459 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2460 io_write(sd, 0x15, 0x80); /* Power up pads */
2461
2462 /* video format */
2463 io_write(sd, 0x02,
69e9ba6f 2464 0xf0 |
a89bcd4c
HV		 2465 pdata->alt_gamma << 3 |
2466 pdata->op_656_range << 2 |
2467 pdata->rgb_out << 1 |
2468 pdata->alt_data_sat << 0);
2469 io_write(sd, 0x03, pdata->op_format_sel);
2470 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2471 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2472 pdata->insert_av_codes << 2 |
2473 pdata->replicate_av_codes << 1 |
2474 pdata->invert_cbcr << 0);
2475
5b64b205
MR		 2476 /* HDMI audio */
2477 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2478
a89bcd4c
HV		 2479 /* Drive strength */
2480 io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2481 pdata->drive_strength.clock<<2 |
2482 pdata->drive_strength.sync);
2483
2484 /* HDMI free run */
2485 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2486
2487 /* TODO from platform data */
2488 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2489 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2490 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2491 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2492
2493 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2494 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2495
2496 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2497
a89bcd4c
HV		 2498 /* todo, improve settings for sdram */
2499 if (pdata->sd_ram_size >= 128) {
2500 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2501 if (pdata->sd_ram_ddr) {
2502 /* SDP setup for the AD eval board */
2503 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2504 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2505 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2506 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2507 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2508 } else {
2509 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2510 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2511 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2512 depends on memory */
2513 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2514 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2515 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2516 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2517 }
2518 } else {
2519 /*
2520 * Manual UG-214, rev 0 is bit confusing on this bit
2521 * but a '1' disables any signal if the Ram is active.
2522 */
2523 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2524 }
2525
2526 select_input(sd, pdata->vid_std_select);
2527
2528 enable_input(sd);
2529
2530 /* disable I2C access to internal EDID ram from HDMI DDC ports */
2531 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2532
2533 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2534 /* HPA disable on port A and B */
2535 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2536
2537 /* LLC */
2538 /* Set phase to 16. TODO: get this from platform_data */
2539 io_write(sd, 0x19, 0x90);
2540 io_write(sd, 0x33, 0x40);
2541
2542 /* interrupts */
c9f1f271 2543 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
a89bcd4c
HV		 2544
2545 adv7842_irq_enable(sd, true);
2546
2547 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2548}
2549
2550/* ----------------------------------------------------------------------- */
2551
2552static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2553{
2554 /*
2555 * From ADV784x external Memory test.pdf
2556 *
2557 * Reset must just been performed before running test.
2558 * Recommended to reset after test.
2559 */
2560 int i;
2561 int pass = 0;
2562 int fail = 0;
2563 int complete = 0;
2564
2565 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2566 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2567 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2568 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2569 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2570 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2571 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2572 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2573 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2574 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2575 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2576 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2577
2578 mdelay(5);
2579
2580 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2581 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2582 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2583 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2584 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2585 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2586 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2587 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2588 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2589 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2590 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2591
2592 mdelay(5);
2593
2594 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2595 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2596
2597 mdelay(20);
2598
2599 for (i = 0; i < 10; i++) {
2600 u8 result = sdp_io_read(sd, 0xdb);
2601 if (result & 0x10) {
2602 complete++;
2603 if (result & 0x20)
2604 fail++;
2605 else
2606 pass++;
2607 }
2608 mdelay(20);
2609 }
2610
2611 v4l2_dbg(1, debug, sd,
2612 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2613 complete, i, pass, fail);
2614
2615 if (!complete || fail)
2616 return -EIO;
2617 return 0;
2618}
2619
2620static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2621 struct adv7842_platform_data *pdata)
2622{
2623 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2624 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2625 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2626 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2627 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2628
2629 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2630 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2631 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2632 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2633
2634 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2635 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2636}
2637
2638static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2639{
2640 struct i2c_client *client = v4l2_get_subdevdata(sd);
2641 struct adv7842_state *state = to_state(sd);
2642 struct adv7842_platform_data *pdata = client->dev.platform_data;
2643 int ret = 0;
2644
2645 if (!pdata)
2646 return -ENODEV;
2647
2648 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2649 v4l2_info(sd, "no sdram or no ddr sdram\n");
2650 return -EINVAL;
2651 }
2652
2653 main_reset(sd);
2654
2655 adv7842_rewrite_i2c_addresses(sd, pdata);
2656
2657 /* run ram test */
2658 ret = adv7842_ddr_ram_test(sd);
2659
2660 main_reset(sd);
2661
2662 adv7842_rewrite_i2c_addresses(sd, pdata);
2663
2664 /* and re-init chip and state */
69e9ba6f 2665 adv7842_core_init(sd);
a89bcd4c
HV		 2666
2667 disable_input(sd);
2668
2669 select_input(sd, state->vid_std_select);
2670
2671 enable_input(sd);
2672
2673 adv7842_s_dv_timings(sd, &state->timings);
2674
2675 edid_write_vga_segment(sd);
fc2e991e
MB		 2676 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2677 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
a89bcd4c
HV		 2678
2679 return ret;
2680}
2681
2682static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2683{
2684 switch (cmd) {
2685 case ADV7842_CMD_RAM_TEST:
2686 return adv7842_command_ram_test(sd);
2687 }
2688 return -ENOTTY;
2689}
2690
2691/* ----------------------------------------------------------------------- */
2692
2693static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2694 .s_ctrl = adv7842_s_ctrl,
2695};
2696
2697static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2698 .log_status = adv7842_log_status,
2699 .g_std = adv7842_g_std,
2700 .s_std = adv7842_s_std,
2701 .ioctl = adv7842_ioctl,
2702 .interrupt_service_routine = adv7842_isr,
2703#ifdef CONFIG_VIDEO_ADV_DEBUG
2704 .g_register = adv7842_g_register,
2705 .s_register = adv7842_s_register,
2706#endif
2707};
2708
2709static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2710 .s_routing = adv7842_s_routing,
2711 .querystd = adv7842_querystd,
2712 .g_input_status = adv7842_g_input_status,
2713 .s_dv_timings = adv7842_s_dv_timings,
2714 .g_dv_timings = adv7842_g_dv_timings,
2715 .query_dv_timings = adv7842_query_dv_timings,
2716 .enum_dv_timings = adv7842_enum_dv_timings,
2717 .dv_timings_cap = adv7842_dv_timings_cap,
2718 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2719 .g_mbus_fmt = adv7842_g_mbus_fmt,
2720 .try_mbus_fmt = adv7842_g_mbus_fmt,
2721 .s_mbus_fmt = adv7842_g_mbus_fmt,
2722};
2723
2724static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2725 .set_edid = adv7842_set_edid,
2726};
2727
2728static const struct v4l2_subdev_ops adv7842_ops = {
2729 .core = &adv7842_core_ops,
2730 .video = &adv7842_video_ops,
2731 .pad = &adv7842_pad_ops,
2732};
2733
2734/* -------------------------- custom ctrls ---------------------------------- */
2735
2736static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2737 .ops = &adv7842_ctrl_ops,
2738 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2739 .name = "Analog Sampling Phase",
2740 .type = V4L2_CTRL_TYPE_INTEGER,
2741 .min = 0,
2742 .max = 0x1f,
2743 .step = 1,
2744 .def = 0,
2745};
2746
2747static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2748 .ops = &adv7842_ctrl_ops,
2749 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2750 .name = "Free Running Color, Manual",
2751 .type = V4L2_CTRL_TYPE_BOOLEAN,
2752 .max = 1,
2753 .step = 1,
2754 .def = 1,
2755};
2756
2757static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2758 .ops = &adv7842_ctrl_ops,
2759 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2760 .name = "Free Running Color",
2761 .type = V4L2_CTRL_TYPE_INTEGER,
2762 .max = 0xffffff,
2763 .step = 0x1,
2764};
2765
2766
2767static void adv7842_unregister_clients(struct adv7842_state *state)
2768{
2769 if (state->i2c_avlink)
2770 i2c_unregister_device(state->i2c_avlink);
2771 if (state->i2c_cec)
2772 i2c_unregister_device(state->i2c_cec);
2773 if (state->i2c_infoframe)
2774 i2c_unregister_device(state->i2c_infoframe);
2775 if (state->i2c_sdp_io)
2776 i2c_unregister_device(state->i2c_sdp_io);
2777 if (state->i2c_sdp)
2778 i2c_unregister_device(state->i2c_sdp);
2779 if (state->i2c_afe)
2780 i2c_unregister_device(state->i2c_afe);
2781 if (state->i2c_repeater)
2782 i2c_unregister_device(state->i2c_repeater);
2783 if (state->i2c_edid)
2784 i2c_unregister_device(state->i2c_edid);
2785 if (state->i2c_hdmi)
2786 i2c_unregister_device(state->i2c_hdmi);
2787 if (state->i2c_cp)
2788 i2c_unregister_device(state->i2c_cp);
2789 if (state->i2c_vdp)
2790 i2c_unregister_device(state->i2c_vdp);
2791}
2792
2793static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2794 u8 addr, u8 io_reg)
2795{
2796 struct i2c_client *client = v4l2_get_subdevdata(sd);
2797
2798 io_write(sd, io_reg, addr << 1);
2799 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2800}
2801
2802static int adv7842_probe(struct i2c_client *client,
2803 const struct i2c_device_id *id)
2804{
2805 struct adv7842_state *state;
2806 struct adv7842_platform_data *pdata = client->dev.platform_data;
2807 struct v4l2_ctrl_handler *hdl;
2808 struct v4l2_subdev *sd;
2809 u16 rev;
2810 int err;
2811
2812 /* Check if the adapter supports the needed features */
2813 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2814 return -EIO;
2815
2816 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2817 client->addr << 1);
2818
2819 if (!pdata) {
2820 v4l_err(client, "No platform data!\n");
2821 return -ENODEV;
2822 }
2823
2824 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2825 if (!state) {
2826 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2827 return -ENOMEM;
2828 }
2829
7de5be44
MB		 2830 /* platform data */
2831 state->pdata = *pdata;
2832
a89bcd4c
HV		 2833 sd = &state->sd;
2834 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2835 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
a89bcd4c
HV		 2836 state->mode = pdata->mode;
2837
8e4e3631 2838 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
6e9071f2 2839 state->restart_stdi_once = true;
a89bcd4c
HV		 2840
2841 /* i2c access to adv7842? */
2842 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2843 adv_smbus_read_byte_data_check(client, 0xeb, false);
2844 if (rev != 0x2012) {
2845 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2846 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2847 adv_smbus_read_byte_data_check(client, 0xeb, false);
2848 }
2849 if (rev != 0x2012) {
2850 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2851 client->addr << 1, rev);
2852 return -ENODEV;
2853 }
2854
2855 if (pdata->chip_reset)
2856 main_reset(sd);
2857
2858 /* control handlers */
2859 hdl = &state->hdl;
2860 v4l2_ctrl_handler_init(hdl, 6);
2861
2862 /* add in ascending ID order */
2863 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2864 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2865 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2866 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2867 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2868 V4L2_CID_SATURATION, 0, 255, 1, 128);
2869 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2870 V4L2_CID_HUE, 0, 128, 1, 0);
2871
2872 /* custom controls */
2873 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2874 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2875 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2876 &adv7842_ctrl_analog_sampling_phase, NULL);
2877 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2878 &adv7842_ctrl_free_run_color_manual, NULL);
2879 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2880 &adv7842_ctrl_free_run_color, NULL);
2881 state->rgb_quantization_range_ctrl =
2882 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2883 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2884 0, V4L2_DV_RGB_RANGE_AUTO);
2885 sd->ctrl_handler = hdl;
2886 if (hdl->error) {
2887 err = hdl->error;
2888 goto err_hdl;
2889 }
2890 state->detect_tx_5v_ctrl->is_private = true;
2891 state->rgb_quantization_range_ctrl->is_private = true;
2892 state->analog_sampling_phase_ctrl->is_private = true;
2893 state->free_run_color_ctrl_manual->is_private = true;
2894 state->free_run_color_ctrl->is_private = true;
2895
2896 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2897 err = -ENODEV;
2898 goto err_hdl;
2899 }
2900
2901 state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2902 state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2903 state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2904 state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2905 state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2906 state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2907 state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2908 state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2909 state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2910 state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2911 state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2912 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2913 !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2914 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2915 !state->i2c_cp || !state->i2c_vdp) {
2916 err = -ENOMEM;
2917 v4l2_err(sd, "failed to create all i2c clients\n");
2918 goto err_i2c;
2919 }
2920
2921 /* work queues */
2922 state->work_queues = create_singlethread_workqueue(client->name);
2923 if (!state->work_queues) {
2924 v4l2_err(sd, "Could not create work queue\n");
2925 err = -ENOMEM;
2926 goto err_i2c;
2927 }
2928
2929 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2930 adv7842_delayed_work_enable_hotplug);
2931
2932 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2933 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2934 if (err)
2935 goto err_work_queues;
2936
7de5be44 2937 err = adv7842_core_init(sd);
a89bcd4c
HV		 2938 if (err)
2939 goto err_entity;
2940
2941 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2942 client->addr << 1, client->adapter->name);
2943 return 0;
2944
2945err_entity:
2946 media_entity_cleanup(&sd->entity);
2947err_work_queues:
2948 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2949 destroy_workqueue(state->work_queues);
2950err_i2c:
2951 adv7842_unregister_clients(state);
2952err_hdl:
2953 v4l2_ctrl_handler_free(hdl);
2954 return err;
2955}
2956
2957/* ----------------------------------------------------------------------- */
2958
2959static int adv7842_remove(struct i2c_client *client)
2960{
2961 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2962 struct adv7842_state *state = to_state(sd);
2963
2964 adv7842_irq_enable(sd, false);
2965
2966 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2967 destroy_workqueue(state->work_queues);
2968 v4l2_device_unregister_subdev(sd);
2969 media_entity_cleanup(&sd->entity);
2970 adv7842_unregister_clients(to_state(sd));
2971 v4l2_ctrl_handler_free(sd->ctrl_handler);
2972 return 0;
2973}
2974
2975/* ----------------------------------------------------------------------- */
2976
2977static struct i2c_device_id adv7842_id[] = {
2978 { "adv7842", 0 },
2979 { }
2980};
2981MODULE_DEVICE_TABLE(i2c, adv7842_id);
2982
2983/* ----------------------------------------------------------------------- */
2984
2985static struct i2c_driver adv7842_driver = {
2986 .driver = {
2987 .owner = THIS_MODULE,
2988 .name = "adv7842",
2989 },
2990 .probe = adv7842_probe,
2991 .remove = adv7842_remove,
2992 .id_table = adv7842_id,
2993};
2994
2995module_i2c_driver(adv7842_driver);
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