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[mirror_ubuntu-hirsute-kernel.git] / drivers / media / i2c / cx25840 / cx25840-ir.c
CommitLineData
52fd3dda
AW		 1/*
2 * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
3 *
4 * Integrated Consumer Infrared Controller
5 *
6 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
52fd3dda
AW		 17 */
18
19#include <linux/slab.h>
20#include <linux/kfifo.h>
7a707b89 21#include <linux/module.h>
d647f0b7 22#include <media/drv-intf/cx25840.h>
6bda9644 23#include <media/rc-core.h>
52fd3dda
AW		 24
25#include "cx25840-core.h"
26
27static unsigned int ir_debug;
28module_param(ir_debug, int, 0644);
29MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
30
31#define CX25840_IR_REG_BASE 0x200
32
33#define CX25840_IR_CNTRL_REG 0x200
34#define CNTRL_WIN_3_3 0x00000000
35#define CNTRL_WIN_4_3 0x00000001
36#define CNTRL_WIN_3_4 0x00000002
37#define CNTRL_WIN_4_4 0x00000003
38#define CNTRL_WIN 0x00000003
39#define CNTRL_EDG_NONE 0x00000000
40#define CNTRL_EDG_FALL 0x00000004
41#define CNTRL_EDG_RISE 0x00000008
42#define CNTRL_EDG_BOTH 0x0000000C
43#define CNTRL_EDG 0x0000000C
44#define CNTRL_DMD 0x00000010
45#define CNTRL_MOD 0x00000020
46#define CNTRL_RFE 0x00000040
47#define CNTRL_TFE 0x00000080
48#define CNTRL_RXE 0x00000100
49#define CNTRL_TXE 0x00000200
50#define CNTRL_RIC 0x00000400
51#define CNTRL_TIC 0x00000800
52#define CNTRL_CPL 0x00001000
53#define CNTRL_LBM 0x00002000
54#define CNTRL_R 0x00004000
55
56#define CX25840_IR_TXCLK_REG 0x204
57#define TXCLK_TCD 0x0000FFFF
58
59#define CX25840_IR_RXCLK_REG 0x208
60#define RXCLK_RCD 0x0000FFFF
61
62#define CX25840_IR_CDUTY_REG 0x20C
63#define CDUTY_CDC 0x0000000F
64
65#define CX25840_IR_STATS_REG 0x210
66#define STATS_RTO 0x00000001
67#define STATS_ROR 0x00000002
68#define STATS_RBY 0x00000004
69#define STATS_TBY 0x00000008
70#define STATS_RSR 0x00000010
71#define STATS_TSR 0x00000020
72
73#define CX25840_IR_IRQEN_REG 0x214
74#define IRQEN_RTE 0x00000001
75#define IRQEN_ROE 0x00000002
76#define IRQEN_RSE 0x00000010
77#define IRQEN_TSE 0x00000020
78#define IRQEN_MSK 0x00000033
79
80#define CX25840_IR_FILTR_REG 0x218
81#define FILTR_LPF 0x0000FFFF
82
83#define CX25840_IR_FIFO_REG 0x23C
84#define FIFO_RXTX 0x0000FFFF
85#define FIFO_RXTX_LVL 0x00010000
86#define FIFO_RXTX_RTO 0x0001FFFF
87#define FIFO_RX_NDV 0x00020000
88#define FIFO_RX_DEPTH 8
89#define FIFO_TX_DEPTH 8
90
91#define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
92#define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2)
93
c02e0d12
AW		 94/*
95 * We use this union internally for convenience, but callers to tx_write
96 * and rx_read will be expecting records of type struct ir_raw_event.
97 * Always ensure the size of this union is dictated by struct ir_raw_event.
98 */
99union cx25840_ir_fifo_rec {
100 u32 hw_fifo_data;
101 struct ir_raw_event ir_core_data;
102};
103
104#define CX25840_IR_RX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
105#define CX25840_IR_TX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
52fd3dda
AW		 106
107struct cx25840_ir_state {
108 struct i2c_client *c;
109
110 struct v4l2_subdev_ir_parameters rx_params;
111 struct mutex rx_params_lock; /* protects Rx parameter settings cache */
112 atomic_t rxclk_divider;
113 atomic_t rx_invert;
114
115 struct kfifo rx_kfifo;
116 spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
117
118 struct v4l2_subdev_ir_parameters tx_params;
119 struct mutex tx_params_lock; /* protects Tx parameter settings cache */
120 atomic_t txclk_divider;
121};
122
123static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
124{
125 struct cx25840_state *state = to_state(sd);
126 return state ? state->ir_state : NULL;
127}
128
129
130/*
131 * Rx and Tx Clock Divider register computations
132 *
133 * Note the largest clock divider value of 0xffff corresponds to:
4a3fad70 134 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
52fd3dda
AW		 135 * which fits in 21 bits, so we'll use unsigned int for time arguments.
136 */
137static inline u16 count_to_clock_divider(unsigned int d)
138{
139 if (d > RXCLK_RCD + 1)
140 d = RXCLK_RCD;
141 else if (d < 2)
142 d = 1;
143 else
144 d--;
145 return (u16) d;
146}
147
148static inline u16 ns_to_clock_divider(unsigned int ns)
149{
150 return count_to_clock_divider(
151 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
152}
153
154static inline unsigned int clock_divider_to_ns(unsigned int divider)
155{
156 /* Period of the Rx or Tx clock in ns */
157 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
158 CX25840_IR_REFCLK_FREQ / 1000000);
159}
160
161static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
162{
163 return count_to_clock_divider(
164 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
165}
166
167static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
168{
169 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
170}
171
172static inline u16 freq_to_clock_divider(unsigned int freq,
173 unsigned int rollovers)
174{
175 return count_to_clock_divider(
176 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers));
177}
178
179static inline unsigned int clock_divider_to_freq(unsigned int divider,
180 unsigned int rollovers)
181{
182 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
183 (divider + 1) * rollovers);
184}
185
186/*
187 * Low Pass Filter register calculations
188 *
189 * Note the largest count value of 0xffff corresponds to:
4a3fad70 190 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
52fd3dda
AW		 191 * which fits in 21 bits, so we'll use unsigned int for time arguments.
192 */
193static inline u16 count_to_lpf_count(unsigned int d)
194{
195 if (d > FILTR_LPF)
196 d = FILTR_LPF;
197 else if (d < 4)
198 d = 0;
199 return (u16) d;
200}
201
202static inline u16 ns_to_lpf_count(unsigned int ns)
203{
204 return count_to_lpf_count(
205 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
206}
207
208static inline unsigned int lpf_count_to_ns(unsigned int count)
209{
210 /* Duration of the Low Pass Filter rejection window in ns */
211 return DIV_ROUND_CLOSEST(count * 1000,
212 CX25840_IR_REFCLK_FREQ / 1000000);
213}
214
215static inline unsigned int lpf_count_to_us(unsigned int count)
216{
217 /* Duration of the Low Pass Filter rejection window in us */
218 return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
219}
220
221/*
a395adcf 222 * FIFO register pulse width count computations
52fd3dda
AW		 223 */
224static u32 clock_divider_to_resolution(u16 divider)
225{
226 /*
227 * Resolution is the duration of 1 tick of the readable portion of
228 * of the pulse width counter as read from the FIFO. The two lsb's are
229 * not readable, hence the << 2. This function returns ns.
230 */
231 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
232 CX25840_IR_REFCLK_FREQ / 1000000);
233}
234
235static u64 pulse_width_count_to_ns(u16 count, u16 divider)
236{
237 u64 n;
238 u32 rem;
239
240 /*
241 * The 2 lsb's of the pulse width timer count are not readable, hence
242 * the (count << 2) | 0x3
243 */
244 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
245 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
246 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
247 n++;
248 return n;
249}
250
251#if 0
252/* Keep as we will need this for Transmit functionality */
253static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
254{
255 u64 n;
256 u32 d;
257 u32 rem;
258
259 /*
b595076a 260 * The 2 lsb's of the pulse width timer count are not accessible, hence
52fd3dda
AW		 261 * the (1 << 2)
262 */
263 n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
264 d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
265 rem = do_div(n, d);
266 if (rem >= d / 2)
267 n++;
268
269 if (n > FIFO_RXTX)
270 n = FIFO_RXTX;
271 else if (n == 0)
272 n = 1;
273 return (u16) n;
274}
275
276#endif
277static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
278{
279 u64 n;
280 u32 rem;
281
282 /*
283 * The 2 lsb's of the pulse width timer count are not readable, hence
284 * the (count << 2) | 0x3
285 */
286 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
287 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
288 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
289 n++;
290 return (unsigned int) n;
291}
292
293/*
294 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
295 *
296 * The total pulse clock count is an 18 bit pulse width timer count as the most
297 * significant part and (up to) 16 bit clock divider count as a modulus.
298 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
299 * width timer count's least significant bit.
300 */
301static u64 ns_to_pulse_clocks(u32 ns)
302{
303 u64 clocks;
304 u32 rem;
305 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
306 rem = do_div(clocks, 1000); /* /1000 = cycles */
307 if (rem >= 1000 / 2)
308 clocks++;
309 return clocks;
310}
311
312static u16 pulse_clocks_to_clock_divider(u64 count)
313{
e92ba283 314 do_div(count, (FIFO_RXTX << 2) | 0x3);
52fd3dda
AW		 315
316 /* net result needs to be rounded down and decremented by 1 */
317 if (count > RXCLK_RCD + 1)
318 count = RXCLK_RCD;
319 else if (count < 2)
320 count = 1;
321 else
322 count--;
323 return (u16) count;
324}
325
326/*
327 * IR Control Register helpers
328 */
329enum tx_fifo_watermark {
330 TX_FIFO_HALF_EMPTY = 0,
331 TX_FIFO_EMPTY = CNTRL_TIC,
332};
333
334enum rx_fifo_watermark {
335 RX_FIFO_HALF_FULL = 0,
336 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
337};
338
339static inline void control_tx_irq_watermark(struct i2c_client *c,
340 enum tx_fifo_watermark level)
341{
342 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
343}
344
345static inline void control_rx_irq_watermark(struct i2c_client *c,
346 enum rx_fifo_watermark level)
347{
348 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
349}
350
351static inline void control_tx_enable(struct i2c_client *c, bool enable)
352{
353 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
354 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
355}
356
357static inline void control_rx_enable(struct i2c_client *c, bool enable)
358{
359 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
360 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
361}
362
363static inline void control_tx_modulation_enable(struct i2c_client *c,
364 bool enable)
365{
366 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
367 enable ? CNTRL_MOD : 0);
368}
369
370static inline void control_rx_demodulation_enable(struct i2c_client *c,
371 bool enable)
372{
373 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
374 enable ? CNTRL_DMD : 0);
375}
376
377static inline void control_rx_s_edge_detection(struct i2c_client *c,
378 u32 edge_types)
379{
380 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
381 edge_types & CNTRL_EDG_BOTH);
382}
383
384static void control_rx_s_carrier_window(struct i2c_client *c,
385 unsigned int carrier,
386 unsigned int *carrier_range_low,
387 unsigned int *carrier_range_high)
388{
389 u32 v;
390 unsigned int c16 = carrier * 16;
391
392 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
393 v = CNTRL_WIN_3_4;
394 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
395 } else {
396 v = CNTRL_WIN_3_3;
397 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
398 }
399
400 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
401 v |= CNTRL_WIN_4_3;
402 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
403 } else {
404 v |= CNTRL_WIN_3_3;
405 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
406 }
407 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
408}
409
410static inline void control_tx_polarity_invert(struct i2c_client *c,
411 bool invert)
412{
413 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
414 invert ? CNTRL_CPL : 0);
415}
416
417/*
418 * IR Rx & Tx Clock Register helpers
419 */
420static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
421 unsigned int freq,
422 u16 *divider)
423{
424 *divider = carrier_freq_to_clock_divider(freq);
425 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
426 return clock_divider_to_carrier_freq(*divider);
427}
428
429static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
430 unsigned int freq,
431 u16 *divider)
432{
433 *divider = carrier_freq_to_clock_divider(freq);
434 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
435 return clock_divider_to_carrier_freq(*divider);
436}
437
438static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
439 u16 *divider)
440{
441 u64 pulse_clocks;
442
c02e0d12
AW		 443 if (ns > IR_MAX_DURATION)
444 ns = IR_MAX_DURATION;
52fd3dda
AW		 445 pulse_clocks = ns_to_pulse_clocks(ns);
446 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
447 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
448 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
449}
450
451static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
452 u16 *divider)
453{
454 u64 pulse_clocks;
455
c02e0d12
AW		 456 if (ns > IR_MAX_DURATION)
457 ns = IR_MAX_DURATION;
52fd3dda
AW		 458 pulse_clocks = ns_to_pulse_clocks(ns);
459 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
460 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
461 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
462}
463
464/*
465 * IR Tx Carrier Duty Cycle register helpers
466 */
467static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
468 unsigned int duty_cycle)
469{
470 u32 n;
471 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
472 if (n != 0)
473 n--;
474 if (n > 15)
475 n = 15;
476 cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
477 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
478}
479
480/*
481 * IR Filter Register helpers
482 */
483static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
484{
485 u32 count = ns_to_lpf_count(min_width_ns);
486 cx25840_write4(c, CX25840_IR_FILTR_REG, count);
487 return lpf_count_to_ns(count);
488}
489
490/*
491 * IR IRQ Enable Register helpers
492 */
493static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
494{
495 struct cx25840_state *state = to_state(sd);
496
497 if (is_cx23885(state) || is_cx23887(state))
498 mask ^= IRQEN_MSK;
499 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
500 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
501 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
502}
503
504static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
505{
506 struct cx25840_state *state = to_state(sd);
507
508 if (is_cx23885(state) || is_cx23887(state))
509 mask ^= IRQEN_MSK;
510 mask &= IRQEN_TSE;
511 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
512}
513
514/*
515 * V4L2 Subdevice IR Ops
516 */
517int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
518{
519 struct cx25840_state *state = to_state(sd);
520 struct cx25840_ir_state *ir_state = to_ir_state(sd);
521 struct i2c_client *c = NULL;
522 unsigned long flags;
523
c02e0d12
AW		 524 union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
525 unsigned int i, j, k;
52fd3dda
AW		 526 u32 events, v;
527 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
528 u32 cntrl, irqen, stats;
529
530 *handled = false;
531 if (ir_state == NULL)
532 return -ENODEV;
533
534 c = ir_state->c;
535
536 /* Only support the IR controller for the CX2388[57] AV Core for now */
537 if (!(is_cx23885(state) || is_cx23887(state)))
538 return -ENODEV;
539
540 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
541 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
542 if (is_cx23885(state) || is_cx23887(state))
543 irqen ^= IRQEN_MSK;
544 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
545
546 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
547 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
548 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
549 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
550
551 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
552 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
553 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
554 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
555
556 v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n",
557 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
558 rto ? "rto" : " ", ror ? "ror" : " ",
559 stats & STATS_TBY ? "tby" : " ",
560 stats & STATS_RBY ? "rby" : " ");
561
562 v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
563 tse ? "tse" : " ", rse ? "rse" : " ",
564 rte ? "rte" : " ", roe ? "roe" : " ");
565
566 /*
567 * Transmitter interrupt service
568 */
569 if (tse && tsr) {
570 /*
571 * TODO:
572 * Check the watermark threshold setting
573 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
574 * Push the data to the hardware FIFO.
575 * If there was nothing more to send in the tx_kfifo, disable
576 * the TSR IRQ and notify the v4l2_device.
577 * If there was something in the tx_kfifo, check the tx_kfifo
578 * level and notify the v4l2_device, if it is low.
579 */
580 /* For now, inhibit TSR interrupt until Tx is implemented */
581 irqenable_tx(sd, 0);
582 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
583 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
584 *handled = true;
585 }
586
587 /*
588 * Receiver interrupt service
589 */
590 kror = 0;
591 if ((rse && rsr) || (rte && rto)) {
592 /*
593 * Receive data on RSR to clear the STATS_RSR.
594 * Receive data on RTO, since we may not have yet hit the RSR
595 * watermark when we receive the RTO.
596 */
597 for (i = 0, v = FIFO_RX_NDV;
598 (v & FIFO_RX_NDV) && !kror; i = 0) {
599 for (j = 0;
600 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
601 v = cx25840_read4(c, CX25840_IR_FIFO_REG);
c02e0d12
AW		 602 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
603 i++;
52fd3dda
AW		 604 }
605 if (i == 0)
606 break;
c02e0d12 607 j = i * sizeof(union cx25840_ir_fifo_rec);
52fd3dda
AW		 608 k = kfifo_in_locked(&ir_state->rx_kfifo,
609 (unsigned char *) rx_data, j,
610 &ir_state->rx_kfifo_lock);
611 if (k != j)
612 kror++; /* rx_kfifo over run */
613 }
614 *handled = true;
615 }
616
617 events = 0;
618 v = 0;
619 if (kror) {
620 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
621 v4l2_err(sd, "IR receiver software FIFO overrun\n");
622 }
623 if (roe && ror) {
624 /*
625 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
626 * the Rx FIFO Over Run status (STATS_ROR)
627 */
628 v |= CNTRL_RFE;
629 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
630 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
631 }
632 if (rte && rto) {
633 /*
634 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
635 * the Rx Pulse Width Timer Time Out (STATS_RTO)
636 */
637 v |= CNTRL_RXE;
638 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
639 }
640 if (v) {
641 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
642 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
643 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
644 *handled = true;
645 }
646 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
647 if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
648 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
649 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
650
651 if (events)
652 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
653 return 0;
654}
655
656/* Receiver */
657static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
658 ssize_t *num)
659{
660 struct cx25840_ir_state *ir_state = to_ir_state(sd);
661 bool invert;
662 u16 divider;
663 unsigned int i, n;
c02e0d12 664 union cx25840_ir_fifo_rec *p;
bd829e9d 665 unsigned u, v, w;
52fd3dda
AW		 666
667 if (ir_state == NULL)
668 return -ENODEV;
669
670 invert = (bool) atomic_read(&ir_state->rx_invert);
671 divider = (u16) atomic_read(&ir_state->rxclk_divider);
672
c02e0d12
AW		 673 n = count / sizeof(union cx25840_ir_fifo_rec)
674 * sizeof(union cx25840_ir_fifo_rec);
52fd3dda
AW		 675 if (n == 0) {
676 *num = 0;
677 return 0;
678 }
679
680 n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
681 &ir_state->rx_kfifo_lock);
682
c02e0d12
AW		 683 n /= sizeof(union cx25840_ir_fifo_rec);
684 *num = n * sizeof(union cx25840_ir_fifo_rec);
52fd3dda 685
c02e0d12 686 for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
2560d94e 687
c02e0d12 688 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
2560d94e
AW		 689 /* Assume RTO was because of no IR light input */
690 u = 0;
bd829e9d 691 w = 1;
2560d94e 692 } else {
c02e0d12 693 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
2560d94e 694 if (invert)
c02e0d12 695 u = u ? 0 : 1;
bd829e9d 696 w = 0;
52fd3dda
AW		 697 }
698
c02e0d12
AW		 699 v = (unsigned) pulse_width_count_to_ns(
700 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
701 if (v > IR_MAX_DURATION)
702 v = IR_MAX_DURATION;
52fd3dda 703
dc697984 704 init_ir_raw_event(&p->ir_core_data);
c02e0d12
AW		 705 p->ir_core_data.pulse = u;
706 p->ir_core_data.duration = v;
bd829e9d 707 p->ir_core_data.timeout = w;
52fd3dda 708
bd829e9d
AW		 709 v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s %s\n",
710 v, u ? "mark" : "space", w ? "(timed out)" : "");
711 if (w)
712 v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
52fd3dda
AW		 713 }
714 return 0;
715}
716
717static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
718 struct v4l2_subdev_ir_parameters *p)
719{
720 struct cx25840_ir_state *ir_state = to_ir_state(sd);
721
722 if (ir_state == NULL)
723 return -ENODEV;
724
725 mutex_lock(&ir_state->rx_params_lock);
726 memcpy(p, &ir_state->rx_params,
727 sizeof(struct v4l2_subdev_ir_parameters));
728 mutex_unlock(&ir_state->rx_params_lock);
729 return 0;
730}
731
732static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
733{
734 struct cx25840_ir_state *ir_state = to_ir_state(sd);
735 struct i2c_client *c;
736
737 if (ir_state == NULL)
738 return -ENODEV;
739
740 c = ir_state->c;
741 mutex_lock(&ir_state->rx_params_lock);
742
743 /* Disable or slow down all IR Rx circuits and counters */
744 irqenable_rx(sd, 0);
745 control_rx_enable(c, false);
746 control_rx_demodulation_enable(c, false);
747 control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
748 filter_rx_s_min_width(c, 0);
749 cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
750
751 ir_state->rx_params.shutdown = true;
752
753 mutex_unlock(&ir_state->rx_params_lock);
754 return 0;
755}
756
757static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
758 struct v4l2_subdev_ir_parameters *p)
759{
760 struct cx25840_ir_state *ir_state = to_ir_state(sd);
761 struct i2c_client *c;
762 struct v4l2_subdev_ir_parameters *o;
763 u16 rxclk_divider;
764
765 if (ir_state == NULL)
766 return -ENODEV;
767
768 if (p->shutdown)
769 return cx25840_ir_rx_shutdown(sd);
770
771 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
772 return -ENOSYS;
773
774 c = ir_state->c;
775 o = &ir_state->rx_params;
776
777 mutex_lock(&ir_state->rx_params_lock);
778
779 o->shutdown = p->shutdown;
780
781 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
782 o->mode = p->mode;
783
c02e0d12 784 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
52fd3dda
AW		 785 o->bytes_per_data_element = p->bytes_per_data_element;
786
787 /* Before we tweak the hardware, we have to disable the receiver */
788 irqenable_rx(sd, 0);
789 control_rx_enable(c, false);
790
791 control_rx_demodulation_enable(c, p->modulation);
792 o->modulation = p->modulation;
793
794 if (p->modulation) {
795 p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
796 &rxclk_divider);
797
798 o->carrier_freq = p->carrier_freq;
799
800 p->duty_cycle = 50;
801 o->duty_cycle = p->duty_cycle;
802
803 control_rx_s_carrier_window(c, p->carrier_freq,
804 &p->carrier_range_lower,
805 &p->carrier_range_upper);
806 o->carrier_range_lower = p->carrier_range_lower;
807 o->carrier_range_upper = p->carrier_range_upper;
ceb152ad
AW		 808
809 p->max_pulse_width =
810 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
52fd3dda
AW		 811 } else {
812 p->max_pulse_width =
813 rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
814 &rxclk_divider);
52fd3dda 815 }
ceb152ad 816 o->max_pulse_width = p->max_pulse_width;
52fd3dda
AW		 817 atomic_set(&ir_state->rxclk_divider, rxclk_divider);
818
819 p->noise_filter_min_width =
820 filter_rx_s_min_width(c, p->noise_filter_min_width);
821 o->noise_filter_min_width = p->noise_filter_min_width;
822
823 p->resolution = clock_divider_to_resolution(rxclk_divider);
824 o->resolution = p->resolution;
825
826 /* FIXME - make this dependent on resolution for better performance */
827 control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
828
829 control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
830
831 o->invert_level = p->invert_level;
832 atomic_set(&ir_state->rx_invert, p->invert_level);
833
834 o->interrupt_enable = p->interrupt_enable;
835 o->enable = p->enable;
836 if (p->enable) {
837 unsigned long flags;
838
839 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
840 kfifo_reset(&ir_state->rx_kfifo);
841 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
842 if (p->interrupt_enable)
843 irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
844 control_rx_enable(c, p->enable);
845 }
846
847 mutex_unlock(&ir_state->rx_params_lock);
848 return 0;
849}
850
851/* Transmitter */
852static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
853 ssize_t *num)
854{
855 struct cx25840_ir_state *ir_state = to_ir_state(sd);
52fd3dda
AW		 856
857 if (ir_state == NULL)
858 return -ENODEV;
859
52fd3dda
AW		 860#if 0
861 /*
862 * FIXME - the code below is an incomplete and untested sketch of what
863 * may need to be done. The critical part is to get 4 (or 8) pulses
864 * from the tx_kfifo, or converted from ns to the proper units from the
865 * input, and push them off to the hardware Tx FIFO right away, if the
866 * HW TX fifo needs service. The rest can be pushed to the tx_kfifo in
867 * a less critical timeframe. Also watch out for overruning the
868 * tx_kfifo - don't let it happen and let the caller know not all his
869 * pulses were written.
870 */
871 u32 *ns_pulse = (u32 *) buf;
872 unsigned int n;
873 u32 fifo_pulse[FIFO_TX_DEPTH];
874 u32 mark;
875
876 /* Compute how much we can fit in the tx kfifo */
877 n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
878 n = min(n, (unsigned int) count);
879 n /= sizeof(u32);
880
881 /* FIXME - turn on Tx Fifo service interrupt
882 * check hardware fifo level, and other stuff
883 */
884 for (i = 0; i < n; ) {
885 for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
d69e85b6 886 mark = ns_pulse[i] & LEVEL_MASK;
52fd3dda
AW		 887 fifo_pulse[j] = ns_to_pulse_width_count(
888 ns_pulse[i] &
d69e85b6 889 ~LEVEL_MASK,
52fd3dda
AW		 890 ir_state->txclk_divider);
891 if (mark)
892 fifo_pulse[j] &= FIFO_RXTX_LVL;
893 i++;
894 }
895 kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
896 j * sizeof(u32));
897 }
898 *num = n * sizeof(u32);
899#else
900 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
901 irqenable_tx(sd, IRQEN_TSE);
902 *num = count;
903#endif
904 return 0;
905}
906
907static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
908 struct v4l2_subdev_ir_parameters *p)
909{
910 struct cx25840_ir_state *ir_state = to_ir_state(sd);
911
912 if (ir_state == NULL)
913 return -ENODEV;
914
915 mutex_lock(&ir_state->tx_params_lock);
916 memcpy(p, &ir_state->tx_params,
917 sizeof(struct v4l2_subdev_ir_parameters));
918 mutex_unlock(&ir_state->tx_params_lock);
919 return 0;
920}
921
922static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
923{
924 struct cx25840_ir_state *ir_state = to_ir_state(sd);
925 struct i2c_client *c;
926
927 if (ir_state == NULL)
928 return -ENODEV;
929
930 c = ir_state->c;
931 mutex_lock(&ir_state->tx_params_lock);
932
933 /* Disable or slow down all IR Tx circuits and counters */
934 irqenable_tx(sd, 0);
935 control_tx_enable(c, false);
936 control_tx_modulation_enable(c, false);
937 cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
938
939 ir_state->tx_params.shutdown = true;
940
941 mutex_unlock(&ir_state->tx_params_lock);
942 return 0;
943}
944
945static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
946 struct v4l2_subdev_ir_parameters *p)
947{
948 struct cx25840_ir_state *ir_state = to_ir_state(sd);
949 struct i2c_client *c;
950 struct v4l2_subdev_ir_parameters *o;
951 u16 txclk_divider;
952
953 if (ir_state == NULL)
954 return -ENODEV;
955
956 if (p->shutdown)
957 return cx25840_ir_tx_shutdown(sd);
958
959 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
960 return -ENOSYS;
961
962 c = ir_state->c;
963 o = &ir_state->tx_params;
964 mutex_lock(&ir_state->tx_params_lock);
965
966 o->shutdown = p->shutdown;
967
968 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
969 o->mode = p->mode;
970
c02e0d12 971 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
52fd3dda
AW		 972 o->bytes_per_data_element = p->bytes_per_data_element;
973
974 /* Before we tweak the hardware, we have to disable the transmitter */
975 irqenable_tx(sd, 0);
976 control_tx_enable(c, false);
977
978 control_tx_modulation_enable(c, p->modulation);
979 o->modulation = p->modulation;
980
981 if (p->modulation) {
982 p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
983 &txclk_divider);
984 o->carrier_freq = p->carrier_freq;
985
986 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
987 o->duty_cycle = p->duty_cycle;
ceb152ad
AW		 988
989 p->max_pulse_width =
990 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
52fd3dda
AW		 991 } else {
992 p->max_pulse_width =
993 txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
994 &txclk_divider);
52fd3dda 995 }
ceb152ad 996 o->max_pulse_width = p->max_pulse_width;
52fd3dda
AW		 997 atomic_set(&ir_state->txclk_divider, txclk_divider);
998
999 p->resolution = clock_divider_to_resolution(txclk_divider);
1000 o->resolution = p->resolution;
1001
1002 /* FIXME - make this dependent on resolution for better performance */
1003 control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
1004
1005 control_tx_polarity_invert(c, p->invert_carrier_sense);
1006 o->invert_carrier_sense = p->invert_carrier_sense;
1007
1008 /*
1009 * FIXME: we don't have hardware help for IO pin level inversion
1010 * here like we have on the CX23888.
1011 * Act on this with some mix of logical inversion of data levels,
1012 * carrier polarity, and carrier duty cycle.
1013 */
1014 o->invert_level = p->invert_level;
1015
1016 o->interrupt_enable = p->interrupt_enable;
1017 o->enable = p->enable;
1018 if (p->enable) {
1019 /* reset tx_fifo here */
1020 if (p->interrupt_enable)
1021 irqenable_tx(sd, IRQEN_TSE);
1022 control_tx_enable(c, p->enable);
1023 }
1024
1025 mutex_unlock(&ir_state->tx_params_lock);
1026 return 0;
1027}
1028
1029
1030/*
1031 * V4L2 Subdevice Core Ops support
1032 */
1033int cx25840_ir_log_status(struct v4l2_subdev *sd)
1034{
1035 struct cx25840_state *state = to_state(sd);
1036 struct i2c_client *c = state->c;
1037 char *s;
1038 int i, j;
1039 u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1040
1041 /* The CX23888 chip doesn't have an IR controller on the A/V core */
1042 if (is_cx23888(state))
1043 return 0;
1044
1045 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1046 txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1047 rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1048 cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1049 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1050 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1051 if (is_cx23885(state) || is_cx23887(state))
1052 irqen ^= IRQEN_MSK;
1053 filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1054
1055 v4l2_info(sd, "IR Receiver:\n");
1056 v4l2_info(sd, "\tEnabled: %s\n",
1057 cntrl & CNTRL_RXE ? "yes" : "no");
1058 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
1059 cntrl & CNTRL_DMD ? "enabled" : "disabled");
1060 v4l2_info(sd, "\tFIFO: %s\n",
1061 cntrl & CNTRL_RFE ? "enabled" : "disabled");
1062 switch (cntrl & CNTRL_EDG) {
1063 case CNTRL_EDG_NONE:
1064 s = "disabled";
1065 break;
1066 case CNTRL_EDG_FALL:
1067 s = "falling edge";
1068 break;
1069 case CNTRL_EDG_RISE:
1070 s = "rising edge";
1071 break;
1072 case CNTRL_EDG_BOTH:
1073 s = "rising & falling edges";
1074 break;
1075 default:
1076 s = "??? edge";
1077 break;
1078 }
1079 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
1080 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1081 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1082 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1083 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1084 v4l2_info(sd, "\tLoopback mode: %s\n",
1085 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1086 if (cntrl & CNTRL_DMD) {
1087 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
1088 clock_divider_to_carrier_freq(rxclk));
1089 switch (cntrl & CNTRL_WIN) {
1090 case CNTRL_WIN_3_3:
1091 i = 3;
1092 j = 3;
1093 break;
1094 case CNTRL_WIN_4_3:
1095 i = 4;
1096 j = 3;
1097 break;
1098 case CNTRL_WIN_3_4:
1099 i = 3;
1100 j = 4;
1101 break;
1102 case CNTRL_WIN_4_4:
1103 i = 4;
1104 j = 4;
1105 break;
1106 default:
1107 i = 0;
1108 j = 0;
1109 break;
1110 }
72cc0671
MCC		 1111 v4l2_info(sd, "\tNext carrier edge window: 16 clocks -%1d/+%1d, %u to %u Hz\n",
1112 i, j,
52fd3dda
AW		 1113 clock_divider_to_freq(rxclk, 16 + j),
1114 clock_divider_to_freq(rxclk, 16 - i));
52fd3dda 1115 }
ceb152ad
AW		 1116 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1117 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1118 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
52fd3dda
AW		 1119 v4l2_info(sd, "\tLow pass filter: %s\n",
1120 filtr ? "enabled" : "disabled");
1121 if (filtr)
72cc0671 1122 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, %u ns\n",
52fd3dda
AW		 1123 lpf_count_to_us(filtr),
1124 lpf_count_to_ns(filtr));
1125 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1126 stats & STATS_RTO ? "yes" : "no");
1127 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1128 irqen & IRQEN_RTE ? "enabled" : "disabled");
1129 v4l2_info(sd, "\tFIFO overrun: %s\n",
1130 stats & STATS_ROR ? "yes" : "no");
1131 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1132 irqen & IRQEN_ROE ? "enabled" : "disabled");
1133 v4l2_info(sd, "\tBusy: %s\n",
1134 stats & STATS_RBY ? "yes" : "no");
1135 v4l2_info(sd, "\tFIFO service requested: %s\n",
1136 stats & STATS_RSR ? "yes" : "no");
1137 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1138 irqen & IRQEN_RSE ? "enabled" : "disabled");
1139
1140 v4l2_info(sd, "IR Transmitter:\n");
1141 v4l2_info(sd, "\tEnabled: %s\n",
1142 cntrl & CNTRL_TXE ? "yes" : "no");
1143 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1144 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1145 v4l2_info(sd, "\tFIFO: %s\n",
1146 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1147 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1148 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1149 v4l2_info(sd, "\tCarrier polarity: %s\n",
1150 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1151 : "space:noburst mark:burst");
1152 if (cntrl & CNTRL_MOD) {
1153 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1154 clock_divider_to_carrier_freq(txclk));
1155 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1156 cduty + 1);
52fd3dda 1157 }
ceb152ad
AW		 1158 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1159 pulse_width_count_to_us(FIFO_RXTX, txclk),
1160 pulse_width_count_to_ns(FIFO_RXTX, txclk));
52fd3dda
AW		 1161 v4l2_info(sd, "\tBusy: %s\n",
1162 stats & STATS_TBY ? "yes" : "no");
1163 v4l2_info(sd, "\tFIFO service requested: %s\n",
1164 stats & STATS_TSR ? "yes" : "no");
1165 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1166 irqen & IRQEN_TSE ? "enabled" : "disabled");
1167
1168 return 0;
1169}
1170
1171
1172const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1173 .rx_read = cx25840_ir_rx_read,
1174 .rx_g_parameters = cx25840_ir_rx_g_parameters,
1175 .rx_s_parameters = cx25840_ir_rx_s_parameters,
1176
1177 .tx_write = cx25840_ir_tx_write,
1178 .tx_g_parameters = cx25840_ir_tx_g_parameters,
1179 .tx_s_parameters = cx25840_ir_tx_s_parameters,
1180};
1181
1182
1183static const struct v4l2_subdev_ir_parameters default_rx_params = {
c02e0d12 1184 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
52fd3dda
AW		 1185 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1186
1187 .enable = false,
1188 .interrupt_enable = false,
1189 .shutdown = true,
1190
1191 .modulation = true,
1192 .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1193
1194 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1195 /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1196 .noise_filter_min_width = 333333, /* ns */
1197 .carrier_range_lower = 35000,
1198 .carrier_range_upper = 37000,
1199 .invert_level = false,
1200};
1201
1202static const struct v4l2_subdev_ir_parameters default_tx_params = {
c02e0d12 1203 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
52fd3dda
AW		 1204 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1205
1206 .enable = false,
1207 .interrupt_enable = false,
1208 .shutdown = true,
1209
1210 .modulation = true,
1211 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1212 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1213 .invert_level = false,
1214 .invert_carrier_sense = false,
1215};
1216
1217int cx25840_ir_probe(struct v4l2_subdev *sd)
1218{
1219 struct cx25840_state *state = to_state(sd);
1220 struct cx25840_ir_state *ir_state;
1221 struct v4l2_subdev_ir_parameters default_params;
1222
1223 /* Only init the IR controller for the CX2388[57] AV Core for now */
1224 if (!(is_cx23885(state) || is_cx23887(state)))
1225 return 0;
1226
c02b211d 1227 ir_state = devm_kzalloc(&state->c->dev, sizeof(*ir_state), GFP_KERNEL);
52fd3dda
AW		 1228 if (ir_state == NULL)
1229 return -ENOMEM;
1230
1231 spin_lock_init(&ir_state->rx_kfifo_lock);
1232 if (kfifo_alloc(&ir_state->rx_kfifo,
c02b211d 1233 CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL))
52fd3dda 1234 return -ENOMEM;
52fd3dda
AW		 1235
1236 ir_state->c = state->c;
1237 state->ir_state = ir_state;
1238
1239 /* Ensure no interrupts arrive yet */
1240 if (is_cx23885(state) || is_cx23887(state))
1241 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1242 else
1243 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1244
1245 mutex_init(&ir_state->rx_params_lock);
8ba6220f 1246 default_params = default_rx_params;
52fd3dda
AW		 1247 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1248
1249 mutex_init(&ir_state->tx_params_lock);
8ba6220f 1250 default_params = default_tx_params;
52fd3dda
AW		 1251 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1252
1253 return 0;
1254}
1255
1256int cx25840_ir_remove(struct v4l2_subdev *sd)
1257{
1258 struct cx25840_state *state = to_state(sd);
1259 struct cx25840_ir_state *ir_state = to_ir_state(sd);
1260
1261 if (ir_state == NULL)
1262 return -ENODEV;
1263
1264 cx25840_ir_rx_shutdown(sd);
1265 cx25840_ir_tx_shutdown(sd);
1266
1267 kfifo_free(&ir_state->rx_kfifo);
52fd3dda
AW		 1268 state->ir_state = NULL;
1269 return 0;
1270}
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